Z32F12811ARS

ZNEO32! Family of Microcontrollers Z32F1281 MCU Product Specification PS034504-0617 PRELIMINARY Copyright ©2017 Zilog®, Inc. All rights reserved. www.zilog.com Z32F1281 MCU Product Specification ii Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2017 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. ZNEO32! is a trademark or registered trademark of Zilog, Inc. All other product or service names are the property of their respective owners. PS034504-0617 PRELIMINARY Z32F1281 MCU Product Specification iii Revision History Each instance in this document’s revision history reflects a change from its previous edition. For more details, refer to the corresponding page(s) or appropriate links furnished in the table below. Revision Level Description Page Jun 2017 04 Updated part numbers to include the Cortex M identifier. All May 2016 03 Added Quadrature Encoder Interface information. 122 Apr 2016 02 Added timing information for peripherals; global edits for clarity. All Nov 2015 01 Original issue. Date PS034504-0617 PRELIMINARY Revision History Z32F1281 Product Specification Overview 1. Overview Introduction Zilog’s Z32F1281 MCU, a member of the ZNEO32! Family of microcontrollers is a cost-effective and highperformance 32-bit microcontroller. The Z32F1281 MCU provides 3-phase PWM generator units which are suitable for inverter bridges, including motor drive systems. The two built-in channels of these generators control two inverter motors simultaneously. Three 12-bit high speed ADC units with 16-channel analog multiplexed inputs are included to gather information from the motor. The Z32F1281 MCU can control up to two inverter motors or one inverter motor and the Power Factor Correction (PFC) function simultaneously. Four on-chip operational AMPs and four analog comparators are available to measure analog input signals. The operational amplifier can amplify the input signal to the proper signal range and transfer it to the ADC input channel. The comparator monitors external signals and helps create an internal emergency signal. Multiple powerful external serial interface engines communicate with on-board sensors. Figure 1.1 shows a block diagram of the Z32F1281 MCU. Figure 1.1. Z32F1281 MCU Block Diagram PS034504-0617 PRELIMINARY 1 Z32F1281 Product Specification Overview Figure 1.2 and Figure 1.3 show the pin layouts. Figure 1.2. Pin Layout (LQFP-80) PS034504-0617 PRELIMINARY 2 Z32F1281 Product Specification Overview Figure 1.3. Pin Layout (LQFP-64) PS034504-0617 PRELIMINARY 3 Z32F1281 Product Specification Overview Product Features The Z32F1281 MCU offers the following features:                     High performance low-power Cortex-M3 core 128 KB code Flash memory with cache function 12 KB SRAM 3-Phase Motor PWM with ADC triggering function o 2 channels 1.5Msps high-speed ADC with burst conversion function o 2 or 3 units with 16 channel input Built-in Programmable Gain Amplifier (PGA) for ADC inputs o 4 channels  3 channels for 3 shunt resistor configuration  1 channel for 1 shunt resistor configuration Built-in analog comparator o 4 channels  3 channels for 3 shunt resistor configuration  1 channel for 1 shunt resistor configuration System fail-safe function by clock monitoring XTAL OSC fail monitoring Precision internal oscillator clock (20MHz ±3%) Watchdog timer Six general purpose timers Quadrature encoder interface counter 2 External communication ports: 4 UARTs, 2 I Cs, 2 SPIs High current driving port for UART photo couplers Debug and emergency stop function Real-time monitoring function support for more effective development JTAG and Serial Wire Debug (SWD) in-circuit debugger Various memory size and package options o LQFP-80, LQFP-64 Industrial grade operating temperature (-40 ~ +85℃) Table 1.1. Device Type Part Number Flash SRAM Z32F12811ATS Z32F12811ARS PS034504-0617 128KB 12KB UART SPI I2C 4 2 2 2 2 2 1 2 PRELIMINARY MPWM ADC 3-unit 16 ch I/O PORT PKG 68 LQFP-80 48 LQFP-64 4 Z32F1281 Product Specification Overview Architecture Block Diagram An internal block diagram of the Z32F1281 MCU is shown in Figure 1.4. Figure 1.4. Internal Block Diagram PS034504-0617 PRELIMINARY 5 Z32F1281 Product Specification Overview Functional Description The following section provides an overview of the features of the Z32F1281 microcontroller. ARM Cortex-M3       ARM powered Cortex-M3 Core based on v7M architecture, which is optimized for small size and low-power systems. On core system timer (SYSTICK) provides a simple 24-bit timer that makes it easy to manage the system operations Thumb-compatible Thumb-2 only instruction set processor core makes code high-density Hardware division and single-cycle multiplication Integrated Nested Vectored Interrupt Controller (NVIC) provides deterministic interrupt handling Full featured debug solutions – JTAG and SWD, FPB, DWT, ITM, and TPIU Maximum 72 MHz operating frequency with zero wait execution Nested Vector-Interrupt Controller (NVIC)    The ARM Nested Vectored Interrupt Controller (NVIC) on the ARM Cortex-M3 core handles all internal and external exceptions. When an interrupt condition is detected, the processor state is automatically stored to the stack and automatically restored from the stack at the end of the interrupt service routine. The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoring. 128 KB Internal Code Flash Memory   The Z32F1281 MCU provides internal 128 KB code Flash memory and its controller. This is enough to program the motor algorithm and control the system. Self-programming is available and ISP and JTAG programming is also supported in Boot or Debugging Mode. Instruction and data cache buffer overcome the limitations of low-bandwidth Flash memory. The CPU can execute from Flash memory with zero wait state up to 72 MHz bus frequency. 12 KB Zero-wait Internal SRAM  On chip 12 KB zero-wait SRAM can be used for working memory space and program code can be loaded on this SRAM. Boot Logic  The smart boot logic supports Flash programming. The Z32F1281 MCU can be entered by external boot pin and UART and SPI programming are available in Boot Mode. UART0 or SPI0 is used in Boot mode communication. System Control Unit (SCU)  The SCU block manages internal power, clock, reset and operation mode. It also controls analog blocks (INTOSC, VDC and LVD). 32-bit Watchdog Timer (WDT)  The watchdog timer performs the system monitoring function. It generates an internal reset or interrupt to notice an abnormal status of the system. Multi-purpose 16-bit Timer  PS034504-0617 Six-channel 16-bit general purpose timers support: o Periodic timer mode o Counter mode o PWM mode o Capture mode PRELIMINARY 6 Z32F1281 Product Specification Overview PWM Generator    Two channels of the 3-phase PWM generator are implemented. 16 bit up/down counter with prescaler supports triangular and saw tooth waveforms. The PWM generates an internal ADC trigger signal to measure the signal on time. Dead time insertion and emergency stop functionality ensure that the chip and system operate under safe conditions. Serial Peripheral Interface (SPI)   Synchronous serial communication is provided by the SPI block. The Z32F1281 MCU has 2 channel SPI modules. The DMA function is supported by the DMA controller. Transfer data is moved to/from the memory area without CPU operation. Boot mode uses this SPI block to download the Flash program. Inter-Integrated Circuit Interface (I2C)  2 2 The Z32F1281 MCU has a 2-channel I C block and it supports up to 400 kHz I C communication. Master and the slave modes are supported. Universal Asynchronous Receiver/Transmitter (UART)   The Z32F1281 MCU includes a 4-channel UART block. For accurate baud rate control, a fractional baud rate generator is provided. The DMA function is supported by the DMA controller. Transfer data is moved to/from memory area without CPU operation. General PORT I/Os       16-bit PA, PB, PC, PD ports are available and provide multiple functionality: General I/O port Independent bit set/clear function External interrupt input port Pull-up/Open-drain On chip debounce Filter 12-bit Analog-to-Digital Converter (ADC)  3 built-in ADCs can convert analog signal up to 1usec conversion rate. 16-channel analog mux and OP-AMP provides various combinations from external analog signals. Analog Front End (AFE)   Operational Amplifier (OPAMP) o 4 built-in OPAMPs amplify analog signals up to x8.74 gain Analog Comparator (COMP) o 4 built-in analog comparators Pin Description The pin configurations are shown in Table 1.2. 16 pins are reserved for power/ground pair and dedicated pins. PS034504-0617 PRELIMINARY 7 Z32F1281 Product Specification Overview Table 1.2. Pin Description Pin Name LQFP80 LQFP64 79 63 Type Description VDD P VDD 80 64 GND P Ground 1 1 2 - 3 - 4 2 5 3 6 4 7 5 8 6 9 7 10 8 11 9 12 13 10 11 14 12 15 13 16 14 17 15 GND PD2 MOSI1 PD3* MISOI1 PA0* AN0 COMP0 PA1* AN1 COMP1 PA2* AN2 COMP2 PA3* AN3 COMP3 PA4* T0O AN4 PA5* T1O AN5 PA6* T2O AN6 CREF0 PA7* TRACED3 T3O AN7 CREF1 AGND AVDD PA8* TRACECLK AD0O AN8 PA9* TRACED0 AD1O AN9 PA10* TRACED1 AD2O AN10 PA11* TRACED2 PS034504-0617 P IOUS I/O IOUS I/O IOUS IA IA IOUS IA IA IOUS IA IA IOUS IA IA IOUS Output IA IOUS Output IA IOUS Output IA IA IOUS Output Output IA IA P P IOUS Output Output IA IOUS Output Output IA IOUS Output Output IA IOUS Output Remark Ground PORT D Bit 2 Input/Output SPI Channel 1 Master Out / Slave In PORT D Bit 3 Input/Output SPI Channel 1 Master In / Slave Out PORT A Bit 0 Input/Output Analog Input 0 Comparator 0 Input PORT A Bit 1 Input/Output Analog Input1 Comparator 1 Input PORT A Bit 2 Input/Output Analog Input 2 Comparator 2 Input PORT A Bit 3 Input/Output Analog Input 3 Comparator 3 Input PORT A Bit 4 Input/Output Timer 0 Output Analog Input 4 PORT A Bit 5 Input/Output Timer 1 Output Analog Input 5 PORT A Bit 6 Input/Output Timer 2 Output Analog Input 6 Comparator 0 Reference Input PORT A Bit 7 Input/Output ETM Trace Data 3 Timer 3 Output Analog Input 7 Comparator 1 Reference Input Analog Ground Analog VDD PORT A Bit 8 Input/Output ETM Trace Clock ADC0 Start Signal Analog Input 8 PORT A Bit 9 Input/Output ETM Trace Data 0 ADC1 Start Signal Analog Input 9 PORT A Bit 10 Input/Output ETM Trace Data 1 ADC2 Start Signal Analog Input 10 PORT A Bit 11 Input/Output ETM Trace Data 2 PRELIMINARY 8 Z32F1281 Product Specification AN11 PA12* SS0 AD2I AN12 PD4 SCL1 PD5 SDA1 VDD GND PD6* TXD2 AD0I PD7* RXD2 AD1I PA13* SCK0 AN13 PA14* MOSI0 AN14 PA15* MISO0 AN15 PB0 PWM0H0 PB1 PWM0L0 PB2 PWM0H1 PB3 PWM0L1 IA IOUS I/O Input IA IOUS Output IOUS Output P P IOUS Output Input IOUS Input Input IOUS I/O IA IOUS I/O IA IOUS I/O IA IOUS Output IOUS Output IOUS Output IOUS Output Analog Input 11 PORT A Bit 12 Input/Output SPI0 Slave Select signal ADC2 Start Input signal Analog Input 12 PORT D Bit 4 Input/Output 2 I C Channel 1 SCL In/Out PORT D Bit 5 Input/Output 2 I C Channel 1 SDA In/Out VDD Ground PORT D Bit 6 Input/Output UART Channel 2 TxD Input ADC0 Start Input signal PORT D Bit 7 Input/Output UART Channel 2 RxD Input ADC1 Start Input signal PORT A Bit 13 Input/Output SPI0 Data Clock Input/Output Analog Input 13 PORT A Bit 14 Input/Output SPI0 Master-Output/Slave-Input Data signal Analog Input 14 PORT A Bit 15 Input/Output SPI0 Master-Input/Slave-Output Data signal Analog Input 15 PORT B Bit 0 Input/Output PWM0 H0 Output PORT B Bit 1 Input/Output PWM0 L0 Output PORT B Bit 0 Input/Output PWM0 H1 Output PORT B Bit 1 Input/Output PWM0 L1 Output 18 16 19 - 20 - 21 22 17 18 23 - 24 - 25 19 26 20 27 21 28 22 29 23 30 24 31 25 32 26 TEST Input Test-mode Input (Always tied ‘L’) 33 27 SCANMD Input Scan-mode Input (Always tied ‘L’) 34 28 35 29 36 30 37 31 38 32 PB4 PWM0H2 T9C PB5 PWM0L2 T9O PB6 PRTIN0 WDTO PB7 OVIN0 STBYO PB8 PRTIN1 RXD3 IOUS Output I/O IOUS Output I/O IOUS Input Output IOUS Input Output IOUS Input Input PS034504-0617 Overview Pulldown Pulldown PORT B Bit 4 Input/Output PWM0 H2 Output Timer 9 Clock/Capture Input PORT B Bit 5 Input/Output PWM0 L2 Output Timer 9 Output PORT B Bit 6 Input/Output PWM0 Protection Input signal 0 WDT Output PORT B Bit 7 Input/Output PWM0 Over-voltage put signal 1 Power-down mode indication signal PORT B Bit 8 Input/Output PWM1 Protection Input signal 0 UART3 RXD Input PRELIMINARY 9 Z32F1281 Product Specification 39 - 30 - 41 42 33 34 43 35 44 36 45 37 46 38 47 39 48 40 49 41 50 51 42 43 52 44 53 45 54 - 55 - 56 46 57 - 58 - 59 60 47 48 61 49 62 50 63 51 64 52 65 53 PS034504-0617 PD8 WDTO PD9 STBYO VDD GND PB9 OVIN1 TXD3 PB10 PWM1H0 PB11 PWM1L0 PB12 PWM1H1 PB13 PWM1L1 PB14 PWM1H2 PB15 PWM1L2 GND VDD PC0 TCK/SWCK PC1 TMS/SWDIO PD10 AD0SOC T0C/PHA PD11 AD0EOC T1C/PHB NMI PD12 AD1SOC T2C/PHZ0 PD13 AD1EOC T3C VDD GND PC2 TDO/SWO PC3 TDI PC4 nTRST T0C/PHA PC5 RXD1 T1C/PHB PC6 IOUS Output IOUS Output P P IOUS Input Output IOUS Output IOUS Output IOUS Output IOUS Output IOUS Output IOUS Output P P IOUS Input IOUS I/O IOUS Output Input IOUS Output Input Input IOUS Output Input IOUS Output Input P P IOUS Output IOUS Input IOUS Input Input IOUS Input Input IOUS Overview PORT D Bit 8 Input/Output WDT Output PORT D Bit 9 Input/Output Power-down mode indication signal VDD Ground PORT B Bit 9 Input/Output PWM1 Over-voltage Input signal 1 UART3 TXD Output PORT B Bit 10 Input/Output PWM Channel 1 Phase 0 H-side Output PORT B Bit 11 Input/Output PWM Channel 1 Phase 0 L-side Output PORT B Bit 12 Input/Output PWM Channel 1 Phase 1 H-side Output PORT B Bit 13 Input/Output PWM Channel 1 Phase 1 L-side Output PORT B Bit 14 Input/Output PWM Channel 1 Phase 2 H-side Output PORT B Bit 15 Input/Output PWM Channel 1 Phase 2 L-side Output Ground VDD PORT C Bit 0 Input/Output JTAG TCK, SWD Clock Input PORT C Bit 1 Input/Output JTAG TMS, SWD Data Input/Output PORT D Bit 10 Input/Output ADC0 Start-of-Conversion Timer 0 Clock/Capture/Phase-A Input PORT D Bit 10 Input/Output ADC0 End-of-Conversion Timer 1 Clock/Capture/Phase-B Input Non-maskable Interrupt Input PORT D Bit 12 Input/Output ADC1 Start-of-Conversion Timer 2 Clock/Capture/Phase-Z Input PORT D Bit 13 Input/Output ADC1 End-of-Conversion Timer 3 Clock/Capture Input VDD Ground PORT C Bit 2 Input/Output JTAG TDO, SWO Output PORT C Bit 3 Input/Output JTAG TDI Input PORT C Bit 4Input/Output JTAG nTRST Input Timer 0 Clock/Capture/Phase-A Input PORT C Bit 5Input/Output UART1 RXD Input Timer 1 Clock/Capture/Phase-B Input PORT C Bit 6Input/Output PRELIMINARY 10 Z32F1281 Product Specification TXD1 Output UART1 TXD Output T2C/PHZ Input Timer 2 Clock/Capture/Phase-Z Input PC7 IOUS PORT C Bit 7Input/Output 2 66 54 SCL0 Output I C Channel 0 SCL In/Out T3C Input Timer 3 Clock/Capture input PC8 IOUS PORT C Bit 8 Input/Output 67 55 2 SDA0 Output I C Channel 0 SDA In/Out PC9 IOUS PORT C Bit 9 Input/Output 68 56 CLKO Output System Clock Output T8O Output Timer 8 Output PC10 IOUS PORT C Bit 10 Input/Output 69 57 nRESET Input External Reset Input PC11 IOUS PORT C Bit 11 Input/Output 70 58 BOOT Input Boot mode Selection Input T8C Input Timer 8 Clock/Capture Input PD14 IOUS PORT D Bit 14 Input/Output 71 AD2SOC Output ADC2 Start-of-Conversion Output signal TD15 IOUS PORT D Bit 15 Input/Output 72 AD2EOC Output ADC2 Start-of-Conversion Output signal PC15 IOUS PORT C Bit 14 Input/Output 73 59 TXD0 Output UART0 TXD Output MISO0 I/O SPI0 Master-Input/Slave-Output PC14 IOUS PORT C Bit 14 Input/Output RXD0 Input UART0 RXD Input 74 60 MOSI0 I/O SPI0 Master-Output/Slave-Input VMARGIN OA Not used. (test purpose) PC13 IOUS PORT C Bit 13 Input/Output 75 61 XOUT OA External Crystal Oscillator Output PC12 IOUS PORT C Bit 12 Input/Output 76 62 XIN IA External Crystal Oscillator Input PD0 IOUS PORT D Bit 0 Input/Output 77 SS1 I/O SPI1 Slave Select PD1 IOUS PORT D Bit 1 Input/Output 78 SCK1 I/O SPI1 Clock Input/Output *Notation: I=Input, O=Output, U=Pull-up, D=Pull-down, S=Schmitt-Trigger Input Type, C=CMOS Input Type, A=Analog, P=Power (*) Selected pin function after reset condition Pin order may be changed with revision notice PS034504-0617 PRELIMINARY Overview Pull-up 11 Z32F1281 Product Specification Overview Memory Map Memory map Address 0x0000_0000 0x0001_FFFF 0x0002_0000 Code Flash ROM (128KB) Reserved 0x1FFE_FFFF 0x1FFF_0000 Boot ROM 0x1FFF_07FF 0x1FFF_0800 Reserved 0x1FFF_FFFF 0x2000_0000 0x2000_5FFF 0x2000_6000 0x2FFF_FFFF 0x2200_0000 0x23FF_FFFF 0x2400_0000 0x2FFF_FFFF 0x3000_0000 0x3001_FFFF 0x3002_0000 0x3002_07FF 0x3003_0000 0x3003_07FF 0x3004_0000 0x3FFF_FFFF 0x4000_0000 SRAM (12K) Reserved SRAM Bit-banding region Reserved Code Flash ROM(Mirrored) (128KB) Boot ROM (Mirrored) OTP ROM (Mirrored) Reserved Peripherals 0x4000_FFFF 0x4001_0000 0x41FF_FFFF 0x4200_0000 0x43FF_FFFF 0x4400_0000 0x5FFF_FFFF 0x6000_0000 0x9FFF_FFFF 0xA000_0000 0xDFFF_FFFF 0xE000_0000 0xE003_FFFF 0xE004_0000 0xE00F_FFFF 0xE010_0000 Reserved Peripherals bit-banding region Reserved External Memory (Not supported) External Device (Not supported) Private peripheral bus: Internal Private peripheral bus: Debug/External Vendor Specific 0xFFFF_FFFF Figure 1.5. Main Memory Map PS034504-0617 PRELIMINARY 12 Z32F1281 Product Specification Overview Core memory map Address 0xE000_0000 ITM 0xE000_0FFF 0xE000_1000 DWT 0xE000_1FFF 0xE000_2000 FPB 0xE000_2FFF 0xE000_3000 Reserved 0xE000_DFFF 0xE000_E000 System Control 0xE000_EFFF 0xE000_F000 0xE003_FFFF 0xE004_0000 Reserved TPIU 0xE004_0FFF 0xE004_1000 ETM 0xE004_1FFF 0xE004_2000 External PPB 0xE00F_EFFF 0xE00F_F000 ROM Table 0xE00F_FFFF Figure 1.6. Cortex-M3 Private Memory Map Note: For more information about the memory maps, refer to document number DDI337 from ARM. PS034504-0617 PRELIMINARY 13 Z32F1281 Product Specification Address 0x4000_0000 0x4000_0100 0x4000_0200 0x4000_0300 0x4000_0400 0x4000_0500 0x4000_1000 0x4000_2000 0x4000_3000 Overview Peripheral map SCU FMC WDT Reserved DMAC(15) Reserved PCU GPIO(A,B,C,D) TIMER(6) 0x4000_4000 MPWM0 0x4000_5000 0x4000_6000 0x4000_8000 0x4000_8100 0x4000_8200 0x4000_8300 0x4000_8600 0x4000_9000 0x4000_9100 0x4000_9200 0x4000_A000 0x4000_A100 0x4000_A200 0z4000_B000 0x4000_B100 0x4000_B200 MPWM1 Reserved UART0 UART1 UART2 UART3 Reserved SPI0 SPI1 Reserved 2 I C0 2 I C1 Reserved ADC0 ADC1 ADC2 0x4000_B300 AFE 0x4000_B400 0x4000_FFFF Reserved Figure 1.7. Peripheral Memory Map PS034504-0617 PRELIMINARY 14 Z32F1281 Product Specification CPU 2. CPU Cortex-M3 Core The CPU core is supported by the ARM Cortex-M3 processor which provides a high-performance, low-cost platform. For more information about Cortex-M3, refer to document number DDI337 from ARM. System Timer The System Timer (SYSTICK) is a 24-bit timer and is part of the Cortex-M3 core. The system timer can be configured either through the registers (see the Cortex-M3 Technical Reference Manual) or through the provided functions defined in core_cm3.h. There is an interrupt vector for the system timer. To configure the system timer, call SysTickConfig() with the number of system clocks in between interrupt intervals (up to a maximum of 24 bits). PS034504-0617 PRELIMINARY 15 Z32F1281 Product Specification CPU Interrupt Controller The Nested Vectored Interrupt Controller (NVIC) is part of the core Cortex-M3 MCU. The NVIC controls system exceptions and peripheral interrupts and is closely coupled with the core to provide low latency and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the nested interrupts to enable tail-chaining of interrupts. The Z32F1281 MCU supports 64 peripheral interrupts (of which 25 are not used) and 16 system interrupts. The NVIC also allows setting software interrupts and resetting the system. Interrupts can be assigned a PRIORITY GROUP (common interrupts with the same priorities) as well as individual priorities. There are 8 priority levels available. For an interrupt to be active, it must be enabled in the peripheral and the NVIC registers. For more information on NVIC, see the Cortex M3 Technical Reference Manual. The system includes functions to set the NVIC registers which are defined in core_cm3.h. Table2.1. Interrupt Vector Map PS034504-0617 Interrupt Number Vector Address Interrupt Source -16 0x0000_0000 Stack Pointer -15 0x0000_0004 Reset Address -14 0x0000_0008 NMI Handler -13 0x0000_000C Hard Fault Handler -12 0x0000_0010 MPU Fault Handler -11 0x0000_0014 BUS Fault Handler -10 0x0000_0018 Usage Fault Handler -9 0x0000_001C -8 0x0000_0020 -7 0x0000_0024 -6 0x0000_0028 -5 0x0000_002C SVCall Handler -4 0x0000_0030 Debug Monitor Handler -3 0x0000_0034 Reserved -2 0x0000_0038 PenSV Handler -1 0x0000_003C SysTick Handler 0 0x0000_0040 LVDDETECT 1 0x0000_0044 SCLKFAIL 2 0x0000_0048 XOSCFAIL 3 0x0000_004C WDT 4 0x0000_0050 Reserved 5 0x0000_0054 TIMER0 6 0x0000_0058 TIMER1 7 0x0000_005C TIMER2 8 0x0000_0060 TIMER3 9 0x0000_0064 10 0x0000_0068 Reserved Reserved PRELIMINARY 16 Z32F1281 Product Specification PS034504-0617 11 0x0000_006C 12 0x0000_0070 13 0x0000_0074 TIMER8 14 0x0000_0078 TIMER9 15 0x0000_007C Reserved 16 0x0000_0080 GPIOAE 17 0x0000_0084 GPIOAO 18 0x0000_0088 GPIOBE 19 0x0000_008C GPIOBO 20 0x0000_0090 GPIOCE 21 0x0000_0094 GPIOCO 22 0x0000_0098 GPIODE 23 0x0000_009C GPIODO 24 0x0000_00A0 MPWM0 25 0x0000_00A4 MPWM0PROT 26 0x0000_00A8 MPWM0OVV 27 0x0000_00AC MPWM1 28 0x0000_00B0 MPWM1PROT 29 0x0000_00B4 MPWM1OVV 30 0x0000_00B8 Reserved 31 0x0000_00BC Reserved 32 0x0000_00C0 SPI0 33 0x0000_00C4 SPI1 34 0x0000_00C8 35 0x0000_00CC 36 0x0000_00D0 I2C0 37 0x0000_00D4 I2C1 38 0x0000_00D8 UART0 39 0x0000_00DC UART1 40 0x0000_00E0 UART2 41 0x0000_00E4 UART3 42 0x0000_00E8 Reserved 43 0x0000_00EC ADC0 44 0x0000_00F0 ADC1 45 0x0000_00F4 ADC2 46 0x0000_00F8 COMP0 47 0x0000_00FC COMP1 48 0x0000_0100 COMP2 49 0x0000_0104 COMP3 50 0x0000_0108 Reserved 51 0x0000_010C Reserved 52 0x0000_0110 Reserved 53 0x0000_0114 Reserved CPU Reserved PRELIMINARY 17 Z32F1281 Product Specification PS034504-0617 54 0x0000_0118 Reserved 55 0x0000_011C Reserved 56 0x0000_0120 Reserved 57 0x0000_0124 Reserved 58 0x0000_0128 Reserved 59 0x0000_012C Reserved 60 0x0000_0130 Reserved 61 0x0000_0134 Reserved 62 0x0000_0138 Reserved 63 0x0000_013C Reserved PRELIMINARY CPU 18 Z32F1281 Product Specification Boot Mode 3. Boot Mode Boot Mode Pins The Z32F1281 MCU has a Boot Mode option to program internal Flash memory. When the BOOT pin is pulled low, the system will start up in the BOOT area (0x1FFF_0000) instead of the default Flash area (0x0000_0000). This provides the ability to flash the part using either UART or SPI interfaces. The BOOT pin has an internal pull up resistor. Therefore, when the BOOT pin is not connected, it rides high (normal state). Boot Mode uses the UART0 port and the SPI0 ports for the interface. The JTAG and SW interfaces can also be used, which provide the ability to recover from a bad Flash update that prevents the JTAG or SW debugger from attaching. The pins for Boot Mode are listed in Table 3.1. Table 3.1. Boot Mode Pin List Block SYSTEM UART0 SPI0 PS034504-0617 Pin Name Dir Description nRESET/PC10 I Reset Input signal BOOT/PC11 I ‘0’ to enter Boot mode RXD0/PC14 I UART Boot Receive Data TXD0/PC15 O UART Boot Transmit Data SS0/PA12 I SPI Boot Slave Select SCK0/PA13 I SPI Boot Clock Input MOSI0/PA14 I SPI Boot Data Input MISO0/PA15 O SPI Boot Data Output PRELIMINARY 19 Z32F1281 Product Specification Boot Mode Boot Mode Connections The target board can be designed using either of the Boot Mode ports – UART or SPI. Figure 3.1 and Figure 4.1Figure 3.2 show sample connection diagrams in Boot Mode. 3.3 ~ 5V 10kΩ VDD nRESET TARGET_RESET BOOT BOOT_SW Z32F1281 HOST_TXD RXD0 HOST_RXD TXD0 GND Figure 3.1. Connection Diagram of UART Boot 3.3 ~ 5V 10kΩ TARGET_RESET VDD nRESET BOOT_SW BOOT HOST_SS SS0 HOST_SCK Z32F1281 SCK0 HOST_SDOUT MOSI0 HOST_SDIN MISO0 GND Figure 3.2. Connection Diagram of SPI Boot PS034504-0617 PRELIMINARY 20 Z32F1281 Product Specification System Control Unit 4. System Control Unit Overview The Z32F1281 MCU has a built-in intelligent power control block which manages system analog blocks and operating modes. Internal reset and clock signals are controlled by the SCU block to maintain optimal system performance and power dissipation. APB BUS SCU MODE CONTROL SCU SCU CLOCK GEN HCLK PCLK RESET INTERRUPT SLEEP WAKE UP INTERRUPT VDC/LVD/PLL IntOSC CONTROL Wakeup Source VDC/LVD/PLL IntOSC Figure 4.1. SCU Block Diagram Clock System The Z32F1281 MCU contains two main operating clocks – HCLK, which supplies the clock to the CPU and the AHB bus system; and PCLK, which supplies the clock to the peripheral systems. Users can control the clock system variation by software. Figure 4.2 shows the clock system of the chip. Table 4.1 lists the clock source descriptions. IOSCCON[0] O_rcclk_pre IOSC (16MHz) En/Dis 0 /2 1 0 IOSCCON[1] PLL PLLCLK 1 (20MHz) MCLKSEL[0] MCLKSEL[1] FINSEL MOSC (4MHz/8MHz) En/Dis MOSCCON[1] FINCLK 0 /2 1 1 O_emclk_pre 1 MCLK HCLK_FREE PCLK CM3_HCLK BUS_HCLK SLEEP MEM_HCLK PD SUBCLK 0 1 HCLK PD MOSCCON[0] /2 CM3_FCLK 0 SOSCCON[0] SOSC (1MHz) En/Dis HCLK_FREE 0 DMA_HCLK O_rclk_pre DMAEN SOSCCON[1] Figure 4.2. System Clock Configuration Each of the registers to switch the clock source has a glitch-free circuit. Therefore, the clock can be switched without the risk of glitches. Table 4.1. Clock Sources PS034504-0617 PRELIMINARY 21 Z32F1281 Product Specification Clock name Frequency System Control Unit Description IOSC20 20MHz Internal OSC MOSC XTAL(4MHz~8MHz) External Crystal IOSC PLL Clock 8MHz ~ 80MHz On Chip PLL ROSC 1MHz Internal RING OSC The PLL can synthesize the PLLCLK clock up to 80 MHz with the FIN reference clock. It also has an internal pre-divider and post-divider. HCLK Clock Domain The HCLK clock feeds the clock to the CPU and AHB bus. The Cortex-M3 CPU requires two clocks related with HCLK clock – FCLK and HCLK. FCLK is the free running clock and it is always running except in Powerdown mode. HCLK can be stopped in Idle mode. PS034504-0617 PRELIMINARY 22 Z32F1281 Product Specification System Control Unit Miscellaneous Clock Domain for Cortex-M3 MCLK MCLK FCLK SUBCLK SUBCLK SYNC /N IOSC CM3_STCLK MOSC /N IOSC TIMER_EXT0 MOSC STCLKDIV[7:0] PLL STSRCSEL[2:0] TEXT0SRCSEL[2:0] MCLK MCLK SUBCLK SUBCLK /N IOSC TEXT0CLKDIV[7:0] PLL TRACECLK /N IOSC WDT_EXT0 MOSC MOSC WDTEXTSRCSEL[2:0] TRACESRCSEL[2:0] MCLK MCLK SUBCLK SUBCLK /N IOSC WDTEXTCLKDIV[7:0] PLL TRACECLKDIV[7:0] PLL PWM0CLK PWM1CLK /N IOSC MOSC MOSC DEBPxTCLKDIV[7:0] PLL PWM0CLKDIV[7:0] PWM1CLKDIV[7:0] PLL DEB_PA_CLK DEB_PB_CLK DEB_PC_CLK DEB_PD_CLK DEB_ETC_CLK DEBPxSRCSEL[2:0] PWM0SRCSEL[2:0] PWM1SRCSEL[2:0] Figure 4.3. Miscellaneous Clock Configuration PCLK Clock Domain PCLK is the master clock of all the peripherals. It can be stopped in Power-down mode. Each peripheral clock is generated by the PCER register set. Clock Configuration After power up, the default system clock is fed by the RINGOSC (1MHz) clock. RINGOSC is enabled by default during the power up sequence. The other clock sources are enabled by user controls with the RINGOSC system clock. The MOSC clock can be enabled by the CSCR register. Before enabling the MOSC block, the pin mux configuration should be set for XIN, XOUT function. PC12 and PC13 pins are shared with MOSC’s XIN and XOUT function - PCCMR and PCCCR registers should be configured properly. After enabling the MOSC block, you must wait for more than 1 msec to ensure stable operation of crystal oscillation. The PLL clock can be enabled by the PLLCON register. After enabling the PLL block, you must wait for the PLL lock flag. When the PLL output clock is stable, you can select MCLK for your system requirement. Before changing the system clock, set Flash access wait to the maximum value. After the system clock is changed, set the desired Flash access wait time. Figure 4.4 shows a flow chart outlining the process to configure the system clock. PS034504-0617 PRELIMINARY 23 Z32F1281 Product Specification System Control Unit Power up MCLK == RING OSC (default set) Set Flash wait control in FM.CFG.WAIT == Maximum wait Set PLL CON N Set IOSC Set MOSC PCCMR[27:24]←XIN,XOUT PCCCR[27:24]←analog CSCR.IOSCCON[3] = 1 CSCR.EOSCCON[1] = 1 Check PLL LOCK bit in PLLCON Y Change MCLK from MOSC to PLL in SCCR (MCLK == PLL) N check EOSCSTS bit in CMR Set flash wait control in FM.CFG.WAIT Y Wait 5msec for MOSC crystal oscillation stabilizing END Change MCLK from RINGOSC to MOSC in SCCR (MCLK == MOSC) Figure 4.4. Clock Configuration Procedure Flowchart When you speed up the system clock up to the maximum operating frequency, check the Flash wait control configuration. The CLK3 and CLK4 bit fields in the FMCR register can control the wait time. Flash read access time is one of the limiting factors that can impact performance. The wait control recommendation is provided in Table 4.2. Table 4.2. Flash Wait Control Recommendation FMCR Flash Access Wait Available Max System Clock Frequency CLK3 3 Clock Wait ~48MHz CLK4 4 Clock Wait ~72MHz Reset The Z32F1281 MCU has two system resets:  Cold reset by POR which is effective during power up or down sequence  Warm reset which is generated by several reset sources. The reset event causes the chip to return to its initial state. PS034504-0617 PRELIMINARY 24 Z32F1281 Product Specification System Control Unit Cold reset has only one reset source, which is POR. Warm reset has the following reset sources:        nRESET pin WDT reset LVD reset MCLK Fail reset MOSC Fail reset S/W reset CPU request reset Cold Reset The cold reset is an important feature of the chip when power is up. This characteristic affects the system boot globally. Internal VDC is enabled when VDD power is turned on. The internal VDD level slope is followed by the external VDD power slope. The boot operation is started when the internal PoR trigger level is 1.4V of the internal VDC voltage out level. The RINGOSC clock is enabled and counts 4 msec to stabilize the internal VDC level. During this time, the external VDD voltage level should be higher than the initial LVD level (2.3V). After counting 4 msec, the CPU reset is released and the operation is started. Figure 4.5 shows the power up sequence and internal reset waveform. Figure 4.5. Power Up POR Sequence The RSSR register shows the POR reset status. The last reset comes from POR. RSSR.PORST is set to “1”. After power up, this bit is always “1”. If an abnormal internal voltage drop occurs during normal operation, the system is reset and this bit is also set to “1”. When a cold reset is applied, the entire chip returns to its initial state. Warm Reset The warm reset event has several reset sources and some parts of the chip return to initial state when a warm reset condition occurs. The warm reset source is controlled by the RSER register and the status appears in the RSSR register. The reset for each peripheral block is controlled by the PRER register. The reset can be masked independently. PS034504-0617 PRELIMINARY 25 Z32F1281 Product Specification System Control Unit The CM3_SYSRESETn signal resets the processor, excluding debug logic in the processor. Figure 4.6. Reset Configuration PS034504-0617 PRELIMINARY 26 Z32F1281 Product Specification System Control Unit Operation Mode Three operational states are available in addition to the Initialization state (INIT). When the reset is asserted (brought low), the Z32F1281 MCU runs at 1 MHz, driven by the ROSC. All the other clocks are disabled and peripheral power and clocks are reset. The RUN mode is designed to run at maximum performance of the CPU with a high-speed clock system. The IOSC must be enabled in order to enable the MOSC. The SLEEP mode is designed to run in Low Power consumption mode by halting the processor core and any unused peripherals. Figure 4.7 shows the operation mode transition diagram. Power-on Reset INIT Reset Event Reset Event MCU Initialization Wake-up Event SLEEP WFI SLEEPDEEP=0 RUN Figure 4.7. Operating Mode RUN Mode This mode operates the MCU core and the peripheral hardware by using the high-speed clock. After reset, followed by the INIT state, the system can be configured to enter into RUN mode. SLEEP Mode Only the CPU is stopped in this mode. Each peripheral function can be enabled by the function enable and clock enable bit in the PER and PCER registers. To enter sleep mode, configure the system for the desired low power state then use the "wfi" instruction. When exiting sleep mode, the clock will be set to the RING oscillator. PS034504-0617 PRELIMINARY 27 Z32F1281 Product Specification System Control Unit Pin Description Table 4.3. SCU and PLL Pins PIN NAME TYPE DESCRIPTION nRESET I XIN/XOUT OSC STBYO O Stand-by Output Signal CLKO O Clock Output Monitoring Signal External Reset Input External Crystal Oscillator Registers The base address of SCU is 0x4000_0000. The register map is described in Table 4.4. Table 4.4. SCU Register Map Name Offset R/W CIDR 0x0000 R SMR 0x0004 SRCR Description Reset CHIP ID Register AC33_8128 R/W System Mode Register 0000_0000 0x0008 R/W System Reset Control Register 0000_0000 WUER 0x0010 R/W Wake up source enable register 0000_0000 WUSR 0x0014 R/W Wake up source status register 0000_0000 RSER 0x0018 R/W Reset source enable register 0000_0049 RSSR 0x001C R/W Reset source status register 0000_0080* PRER1 0x0020 R/W Peripheral reset enable register 1 03FF_1F1F* PRER2 0x0024 R/W Peripheral reset enable register 2 00F3_0F33* PER1 0x0028 R/W Peripheral enable register 1 0000_000F* PER2 0x002C R/W Peripheral enable register 2 0000_0101* PCER1 0x0030 R/W Peripheral clock enable register 1 0000_000F* PCER2 0x0034 R/W Peripheral clock enable register 2 0000_0101* CSCR 0x0040 R/W Clock Source Control register 0000_0020 SCCR 0x0044 R/W System Clock Control register 0000_0000 CMR 0x0048 R/W Clock Monitoring register 0000_0003 NMIR 0x004C R/W NMI control register 0000_0000 COR 0x0050 R/W Clock Output Control register 0000_000F PLLCON 0x0060 R/W PLL Control register 0000_1000 VDCCON 0x0064 R/W VDC Control register 0000_000F LVDCON 0x0068 R/W LVD Control register 0000_0001 IOSCTRIM 0x006C R/W Internal RC OSC Control Register 0000_0000 OPA0TRIM 0x0070 R/W OPAM 0 trim register 0000_0000 OPA1TRIM 0x0074 R/W OPAM 1 trim register 0000_0000 OPA2TRIM 0x0078 R/W OPAM 2 trim register 0000_0000 OPA3TRIM 0x007C R/W OPAM 3 trim register 0000_0000 EOSCR 0x0080 R/W External Oscillator control register 0000_0000 EMODR 0x0084 R/W External mode pin read register 0000_000X PS034504-0617 PRELIMINARY 28 Z32F1281 Product Specification System Control Unit DBCLK1 0x009C R/W Debounce Clock Control register 1 0000_0000 DBCLK2 0x00A0 R/W Debounce Clock Control register 2 0000_0000 MCCR1 0x0090 R/W Misc Clock Control register 1 0404_0001 MCCR2 0x0094 R/W Misc Clock Control register 2 0000_0000 MCCR3 0x0098 R/W Misc Clock Control register 3 0000_0001 MCCR4 0x00A4 R/W Misc Clock Control register 4 0000_0001 PS034504-0617 PRELIMINARY 29 Z32F1281 Product Specification CIDR System Control Unit Chip ID Register The Chip ID Register shows chip identification information. This register is a 32-bit read-only register. CIDR=0x4000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHIPID 0xAC33_8128 R 31 0 SMR CHIP ID Device ID 0xAC33_8128 System Mode Register The current operating mode is shown in this SCU mode register and the operation mode can be changed by writing the new mode in this register. The previous operating mode will be saved in this register after a reset event. System Mode Register is a 16-bit register. SMR=0x4000_0004 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 0 0 PREVMODE 15 00 R 5 4 PS034504-0617 PREVMODE Previous operating mode before current reset event. 00 Previous operating mode was RUN mode 01 Previous operating mode was SLEEP mode 10 Previous operating mode was Power-down mode 11 Previous operating mode was INIT mode PRELIMINARY 30 Z32F1281 Product Specification System Control Unit SRCR System Reset Control Register The System Reset Control Register allows the software to initiate a reset. This register also provides the polarity for the STBYOP pin. SCR=0x4000_0008 7 6 5 4 3 2 1 0 SWRST 0 0 0 0 0 0 0 0 W 1 PS034504-0617 SWRST Internal soft reset activation bit 0 Normal operation 1 Internal soft reset is applied and auto cleared PRELIMINARY 31 Z32F1281 Product Specification System Control Unit WUER Wakeup Source Enable Register This is the enable wakeup source. The source of chip wakeup should be enabled in each bit field. If the source will be used as the wakeup source, write 1 to its enable bit. If the source will not be used as the wakeup source, write 0 into its enable bit. This register is a 16-bit register. 13 12 11 GPIOCWUE GPIOBWUE GPIOAWUE 0 0 0 0 0 0 0 0 RW RW RW RW PS034504-0617 10 9 12 GPIOEWUE 11 GPIODWUE 10 GPIOCWUE 9 GPIOBWUE 8 GPIOAWUE 1 WDTWUE 0 LVDWUE 8 7 6 5 4 3 2 1 LVDWUE 14 WDTWUE 15 GPIODWUE WUER=-0x4000_0010 0 0 0 0 0 0 0 0 0 RW RW Enable wakeup source of GPIOE port pin change event 0 Not used for wakeup source 1 Enable the wakeup event generation Enable wakeup source of GPIOD port pin change event 0 Not used for wakeup source 1 Enable the wakeup event generation Enable wakeup source of GPIOC port pin change event 0 Not used for wakeup source 1 Enable the wakeup event generation Enable wakeup source of GPIOB port pin change event 0 Not used for wakeup source 1 Enable the wakeup event generation Enable wakeup source of GPIOA port pin change event 0 Not used for wakeup source 1 Enable the wakeup event generation Enable wakeup source of watchdog timer event 0 Not used for wakeup source 1 Enable the wakeup event generation Enable wakeup source of LVD event 0 Not used for wakeup source 1 Enable the wakeup event generation PRELIMINARY 32 Z32F1281 Product Specification System Control Unit WUSR Wakeup Source Status Register When the system is woken up by any wakeup source, the wakeup source is identified by reading this register. When the bit is set to 1, the related wakeup source issues the wakeup to the SCU. The bit will be cleared when the event is cleared by the software. 13 12 11 GPIOCWU GPIOBWU GPIOAWU 0 0 0 0 0 0 0 0 R R R R PS034504-0617 10 9 12 GPIOEWU 11 GPIODWU 10 GPIOCWU 9 GPIOBWU 8 GPIOAWU 1 WDTWU 0 LVDWU 8 7 6 5 4 3 2 1 LVDWU 14 WDTWU 15 GPIODWU WUSR=0x4000_0014 0 0 0 0 0 0 0 0 0 R R Status of wakeup source of GPIOE port pin change event 0 No wakeup event 1 Wakeup event was generated Status of wakeup source of GPIOD port pin change event 0 No wakeup event 1 Wakeup event was generated Status of wakeup source of GPIOC port pin change event 0 No wakeup event 1 Wakeup event was generated Status of wakeup source of GPIOB port pin change event 0 No wakeup event 1 Wakeup event was generated Status of wakeup source of GPIOA port pin change event 0 No wakeup event 1 Wakeup event was generated Status of wakeup source of watchdog timer event 0 No wakeup event 1 Wakeup event was generated Status of wakeup source of LVD event 0 No wakeup event 1 Wakeup event was generated PRELIMINARY 33 Z32F1281 Product Specification System Control Unit RSER Reset Source Enable Register The reset source which will generate the reset event can be selected by the RSER register. Write 1 in the bit field of each reset source to transfer the reset source event to the reset generator. Write 0 in the bit field of each reset source to mask the reset source event, and therefore, not generate the reset event. RSER=0x4000_0018 7 0 PS034504-0617 6 5 4 3 2 1 0 PINRST CPURST SWRST WDTRST MCKFRST XFRST LVDRST 1 0 0 1 0 0 1 RW RW RW RW RW RW RW 6 PINRST 5 CPURST 4 SWRST 3 WDTRST 2 MCKFRST 1 XFRST 0 LVDRST External pin reset enable bit 0 Reset from this event is masked 1 Reset from this event is enabled CPU request reset enable bit 0 Reset from this event is masked 1 Reset from this event is enabled Software reset enable bit 0 Reset from this event is masked 1 Reset from this event is enabled Watchdog Timer reset enable bit 0 Reset from this event is masked 1 Reset from this event is enabled MCLK Clock fail reset enable bit 0 Reset from this event is masked 1 Reset from this event is enabled External OSC Clock fail reset enable bit 0 Reset from this event is masked 1 Reset from this event is enabled LVD reset enable bit 0 Reset from this event is masked 1 Reset from this event is enabled PRELIMINARY 34 Z32F1281 Product Specification System Control Unit RSSR Reset Source Status Register The RSSR shows the reset source information when a reset event occurs. For a given reset source, 1 indicates that a reset event exists and 0 shows that a reset event does not exist. When a reset source is found, writing 1 to the corresponding bit will clear the reset status. This register is an 8-bit register. RSSR=0x4000_001C 7 6 5 4 3 2 1 0 PORST PINRST CPURST SWRST WDTRST MCKFRST XFRST LVDRST 1 0 0 0 0 0 0 0 RC1 RC1 RC1 RC1 RC1 RC1 RC1 RC1 PS034504-0617 7 PORST 6 PINRST 5 CPURST 4 SWRST 3 WDTRST 2 MCLKFRST 1 XFRST 0 LVDRST Power on reset status bit 0 Read : Reset from this event was not exist Write : no effect 1 Read :Reset from this event was occurred Write : Clear the status External pin reset status bit 0 Read : Reset from this event was not exist Write : no effect 1 Read :Reset from this event was occurred Write : Clear the status CPU request reset status bit 0 Read : Reset from this event was not exist Write : no effect 1 Read :Reset from this event was occurred Write : Clear the status Software reset status bit 0 Read : Reset from this event was not exist Write : no effect 1 Read :Reset from this event was occurred Write : Clear the status Watchdog Timer reset status bit 0 Read : Reset from this event was not exist Write : no effect 1 Read :Reset from this event was occurred Write : Clear the status MCLK Fail reset status bit 0 Read : Reset from this event was not exist Write : no effect 1 Read :Reset from this event was occurred Write : Clear the status Clock fail reset status bit 0 Read : Reset from this event was not exist Write : no effect 1 Read :Reset from this event was occurred Write : Clear the status LVD reset status bit 0 Read : Reset from this event was not exist Write : no effect 1 Read :Reset from this event was occurred Write : Clear the status PRELIMINARY 35 Z32F1281 Product Specification System Control Unit PRER1 Peripheral Reset Enable Register 1 The reset of each peripheral by an event reset can be masked by user settings. The PRER1/2 register controls enabling of the event reset. If the corresponding bit is 1, the peripheral corresponding to this bit accepts the reset event. Otherwise, the peripheral is protected from the reset event and maintains its current operation. 25 24 19 18 17 16 11 10 9 8 4 3 2 1 0 PS034504-0617 TIMER9 TIMER8 TIMER3 TIMER2 TIMER1 TIMER0 GPIOD GPIOC GPIOB GPIOA DMA PCU WDT FMC SCU PCU FMC SCU 0 0 0 1 1 1 1 1 RW RW 1 4 WDT 1 5 RW 1 6 RW 1 7 DMA 0 GPIOA 0 RW 0 GPIOB 0 RW 1 GPIOC 1 RW 1 8 GPIOD 1 9 RW 0 TIMER0 0 RW 0 TIMER1 0 TIMER2 1 RW 1 RW 0 TIMER3 0 RW 0 TIMER8 0 RW 0 TIMER9 0 RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RW PRER1=0x4000_0020 3 2 1 0 TIMER9 reset mask TIMER8 reset mask TIMER3 reset mask TIMER2 reset mask TIMER1 reset mask TIMER0 reset mask GPIOE reset mask GPIOE reset mask GPIOE reset mask GPIOA reset mask DMA reset mask Port Control Unit reset mask Watchdog Timer reset mask Flash memory controller reset mask System Control Unit reset mask PRELIMINARY 36 Z32F1281 Product Specification System Control Unit PRER2 Peripheral Reset Enable Register 2 The reset of each peripheral by an event reset can be masked by user settings. The PRER1/2 register controls enabling of the event reset. If the corresponding bit is 1, the peripheral corresponding to this bit accepts the reset event. Otherwise, the peripheral is protected from the reset event and maintains its current operation. 23 22 21 20 17 16 11 10 9 8 5 4 1 0 PS034504-0617 AFE ADC2 ADC1 ADC0 MPWM1 MPWM0 UART3 UART2 UART1 UART0 I2C1 I2C0 SPI1 SPI0 1 1 1 SPI0 0 2 0 0 1 1 RW 0 3 SPI1 1 4 RW 1 5 I2C0 1 6 RW 1 7 I2C1 0 UART0 0 UART1 0 RW 0 RW 1 UART2 1 RW 0 8 UART3 0 9 RW 1 MWPM0 1 RW 1 MPWM1 1 RW 0 ADC0 0 RW 0 ADC1 0 RW 0 AFE 0 ADC2 0 RW 0 RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RW PRER2=0x4000_0024 0 AFE reset enable ADC2 reset enable ADC1 reset enable ADC0 reset enable MPWM1 reset enable MPWM0 reset enable UART3 reset enable UART2 reset enable UART1 reset enable UART0 reset enable I2C1 reset enable I2C0 reset enable SPI1 reset enable SPI0 reset enable PRELIMINARY 37 Z32F1281 Product Specification System Control Unit PER1 Peripheral Enable Register 1 To use a peripheral unit, it should be activated by writing 1 to the corresponding bit in the PER1/2 register. Prior to activation, the peripheral stays in reset state. To disable the peripheral unit, write 0 to the corresponding bit in the PER0/1 register, after which the peripheral enters the reset state. 25 24 19 18 17 16 11 10 9 8 4 3 2 1 0 PS034504-0617 TIMER9 TIMER8 TIMER3 TIMER2 TIMER1 TIMER0 GPIOD GPIOC GPIOB GPIOA DMA 0 0 1 1 1 1 R 0 1 R 0 2 R 0 7 6 5 4 0 0 0 DMA 0 3 R 0 GPIOA 0 GPIOB 0 RW 0 RW 0 GPIOC 0 RW 0 8 GPIOD 0 9 RW 0 TIMER0 0 RW 0 TIMER1 0 TIMER2 0 RW 0 RW 0 TIMER3 0 RW 0 TIMER8 0 RW 0 TIMER9 0 RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RW PER1=0x4000_0028 TIMER9 function enable TIMER8 function enable TIMER3 function enable TIMER2 function enable TIMER1 function enable TIMER0 function enable GPIOD function enable GPIOC function enable GPIOB function enable GPIOA function enable DMA function enable Reserved PRELIMINARY 38 Z32F1281 Product Specification System Control Unit PER2 Peripheral Enable Register 2 To use a peripheral unit, it should be activated by writing 1 to the corresponding bit in the PER1/2 register. Prior to activation, the peripheral stays in reset state. To disable the peripheral unit, write 0 to the corresponding bit in the PER0/1 register, after which the peripheral enters the reset state. 23 22 21 20 17 16 11 10 9 8 5 4 1 0 PS034504-0617 AFE ADC2 ADC1 ADC0 MPWM1 MPWM0 UART3 UART2 UART1 UART0 I2C1 I2C0 SPI1 SPI0 0 0 1 SPI0 0 2 0 0 0 1 RW 0 3 SPI1 1 4 RW 0 5 I2C0 0 6 RW 0 7 I2C1 0 UART0 0 UART1 0 RW 0 RW 0 UART2 0 RW 0 8 UART3 0 9 RW 0 MWPM0 0 RW 0 MPWM1 0 RW 0 ADC0 0 RW 0 ADC1 0 RW 0 ADC2 0 RW 0 RW 0 AFE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RW PER2=0x4000_002C 0 AFE function enable ADC2 function enable ADC1 function enable ADC0 function enable MPWM1 function enable MPWM0 function enable UART3 function enable UART2 function enable UART1 function enable UART0 function enable I2C1 function enable I2C0 function enable SPI1 function enable SPI0 function enable PRELIMINARY 39 Z32F1281 Product Specification System Control Unit PCER1 Peripheral Clock Enable Register 1 To use a peripheral unit, its clock should be activated by writing 1 to the corresponding bit in the PCER1/2 register. The peripheral will not operate correctly until its clock is enabled. To stop the clock of the peripheral unit, write 0 to the corresponding bit in the PCER1/2 register. 25 24 19 18 17 16 11 10 9 8 4 3 2 1 0 PS034504-0617 TIMER9 TIMER8 TIMER3 TIMER2 TIMER1 TIMER0 GPIOD GPIOC GPIOB GPIOA DMA 0 0 1 1 1 1 R 0 1 R 0 2 R 0 7 6 5 4 0 0 0 DMA 0 3 R 0 GPIOA 0 GPIOB 0 RW 0 RW 0 GPIOC 0 RW 0 8 GPIOD 0 9 RW 0 TIMER0 0 RW 0 TIMER1 0 RW 0 TIMER2 0 TIMER3 0 RW 0 RW 0 TIMER8 0 RW 0 TIMER9 0 RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RW PCER1=0x4000_0030 TIMER9 clock enable TIMER8 clock enable TIMER3 clock enable TIMER2 clock enable TIMER1 clock enable TIMER0 clock enable GPIOD clock enable GPIOC clock enable GPIOB clock enable GPIOA clock enable DMA clock enable Reserved PRELIMINARY 40 Z32F1281 Product Specification PCER2 System Control Unit Peripheral Clock Enable Register 2 To use a peripheral unit, activate its clock by writing 1 to the corresponding bit in the PCER1/2 register. The peripheral will not operate correctly until its clock is enabled. To stop the clock of the peripheral unit, write 0 to the corresponding bit in the PCER1/2 register. 23 22 21 20 17 16 11 10 9 8 5 4 1 0 PS034504-0617 AFE ADC2 ADC1 ADC0 MPWM1 MPWM0 UART3 UART2 UART1 UART0 I2C1 I2C0 SPI1 SPI0 0 0 1 SPI0 0 2 0 0 0 1 RW 0 3 SPI1 1 4 RW 0 5 I2C0 0 6 RW 0 7 I2C1 0 UART0 0 UART1 0 RW 0 RW 0 UART2 0 RW 0 8 UART3 0 9 RW 0 MWPM0 0 RW 0 MPWM1 0 RW 0 ADC0 0 RW 0 ADC1 0 RW 0 ADC2 0 RW 0 RW 0 AFE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RW PCER2=0x4000_0034 0 AFE clock enable ADC2 clock enable ADC1 clock enable ADC0 clock enable MPWM1 clock enable MPWM0 clock enable UART3 clock enable UART2 clock enable UART1 clock enable UART0 clock enable I2C1 clock enable I2C0 clock enable SPI1 clock enable SPI0 clock enable PRELIMINARY 41 Z32F1281 Product Specification System Control Unit CSCR Clock Source Control Register The Z32F1281 MCU has multiple clock sources to generate internal operating clocks. Each clock source can be controlled by the CSCR register. This register is an 8-bit register. CSCR=0x4000_0040 7 6 5 4 3 2 1 0 - RINGOSCCON IOSCCON EOSCCON 00 10 00 00 R RW RW RW 5 4 RINGOSCCON 3 2 IOSCCON 1 0 EOSCCON Internal ring oscillator control 0X Stop internal sub oscillator 10 Enable internal sub oscillator 11 Enable internal sub oscillator divide by 2 Internal oscillator control 0X Stop internal oscillator 10 Enable internal oscillator 11 Enable internal oscillator divide by 2 External crystal oscillator control 0X Stop External Crystal oscillator 10 Enable External Crystal oscillator 11 Enable External Crystal divide by 2 SCCR System Clock Control Register The Z32F1281 MCU has multiple clock sources to generate internal operating clocks. Each clock source can be controlled by the SCU CSCR register. The MOSC must be running and stable before setting the FINSEL bit. SCCR=0x4000_0044 7 6 5 4 3 2 1 0 - FINSEL MCLKSEL 0000 0 00 R RW RW 2 FINSEL 1 0 MCLKSEL PLL input source FIN select register 0 IOSC clock is used as FIN clock 1 MOSC clock is used as FIN clock System clock select register 0X Internal sub oscillator 10 PLL bypassed clock 11 PLL output clock Note: When changing FINSEL, both internal OSC and external OSC should be alive, otherwise the chip will malfunction. PS034504-0617 PRELIMINARY 42 Z32F1281 Product Specification CMR System Control Unit Clock Monitoring Register To monitor the internal clock and external oscillator, the MCLKMNT/EOSCMNT bits must be set before the MCLK and EOSC bits are valid. The Clock Monitoring Register is a 16-bit register. Note: The EOSC bit only checks for the EOSC oscillation, not its stability. When the system detects an MCLKFAIL interrupt, the MCLKREC bit determines if the system dies or will auto-recover using the ROSC. The system usually auto-recovers so that it can continue running. 14 13 12 11 10 9 8 7 MCLKIE MCLKFAIL MCLKSTS EOSCMNT EOSCIE EOSCFAIL EOSCSTS 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 RW RW RC1 RC1 RW RW RC1 RC1 MCLKREC 15 MCLKMNT CMR=0x4000_0048 0 RW 15 MCLKREC 7 MCLKMNT 6 MCLKIE 5 MCLKFAIL 4 MCLKSTS 3 EOSCMNT 2 EOSCIE 1 EOSCFAIL 0 EOSCSTS 6 5 4 3 2 1 0 MCLK fail auto recovery 0 MCLK is changed to RINGOSC by default when MCLKFAIL issued 1 MCLK auto recovery is disabled MCLK monitoring enable 0 MCLK monitoring disabled 1 MCLK monitoring enabled MCLK fail interrupt enable 0 MCLK fail interrupt disabled 1 MCLK fail interrupt enabled MCLK fail interrupt 0 MCLK fail interrupt not occurred 1 Read : MCLK fail interrupt is pending Write : Clear pending interrupt MCLK clock status 0 No clock is present on MCLK 1 Clock is present on MCLK External oscillator monitoring enable 0 External oscillator monitoring disabled 1 External oscillator monitoring enabled External oscillator fail interrupt enable 0 External oscillator fail interrupt disabled 1 External oscillator fail interrupt enabled External oscillator fail interrupt 0 External oscillator fail interrupt not occurred 1 Read : External oscillator fail interrupt is pending Write : Clear pending interrupt External oscillator status 0 Not oscillate 1 External oscillator is working normally The clock monitoring function cannot cover all malfunction cases. It is just used for the reference. Figure 4.8 shows the operational diagram for the clock monitoring function. PS034504-0617 PRELIMINARY 43 Z32F1281 Product Specification System Control Unit Figure 4.8. Clock Monitoring Function Diagram NMIR NMI Control Register Non-Maskable Interrupt pin configuration provides the ability to enable/disable and set the debounce of the NMI pin. It also provides the ability to monitor the interrupt and status of the NMI pin. 12 11 10 9 0x00 8 7 6 5 4 3 NMIEN 13 NMIDBEN 14 NMIFLAG 15 NMISTAT NMIR=0x4000_004C 0 0 0 0 0 0 0 0 RW RW RW RW RW PS034504-0617 3 MMISTAT 2 NMIFLAG 1 NMIDBEN 0 NMIEN 2 1 0 NMI Pin status 0 NMI pin is low status 1 NMI pin is high status NMI interrupt flag 0 NMI interrupt is not pending 1 NMI interrupt is pending NMI pin debounce enable 0 NMI pin debounce disable 1 NMI pin debounce enable NMI Enable Write permission is required by PCU write enable sequence 0 NMI pin disable 1 NMI pin enable PRELIMINARY 44 Z32F1281 Product Specification COR System Control Unit Clock Output Register The clock output register controls the enabling/disabling of the clock signal and provides a divider for the clock output. In order to output the clock signal, you must enable the Clock out function pin. For more information, see Chapter 5, Port Control Unit. COR=0x4000_0050 7 6 5 4 3 1 - CLKOEN CLKODIV 000 0 1111 R RW RW 4 CLKOEN 3 0 CLKODIV 0 Clock output enable 0 CLKO is disabled and stay “L” output 1 CLKO Is enabled Clock output divider value CLKO = MCLK CLKO = PS034504-0617 2 PRELIMINARY (CLKODIV = 0) 𝑀𝐶𝐿𝐾 2 ∗ (CLKODIV + 1) (𝐶𝐿𝐾𝑂𝐷𝐼𝑉 > 0) 45 Z32F1281 Product Specification PLLCON System Control Unit PLL Control Register Integrated PLL can synthesize the high speed clock for extremely high performance of the CPU from either the internal oscillator (IOSC) or the external oscillator (MOSC). The PLL Control register provides the configuration for the PLL system. By default, the PLL system is in reset mode and disabled. You must negate the reset and enable the PLL to operate (bits 14 and 15 must be set). The Bypass bit must be set to output the PLL clock. The active clock is defined in SCCR bit 2 (FIN). To calculate the PLL output: PLL Out = ((Active clock / PREDIV) * FBCTRL) / POSTDIV For example: Using MOSC (assuming it is running at 8 MHz and selected): PREDIV set to 1 (FIN / 2) FBCTRL set to 0x05 (M=18) POSTDIV set to 0x00 (N=1) ((8 MHz / 2) * 18) = 72 MHz PLLCON=0x4000_0060 0 0 RW RW RW R 9 8 0 0 0 0 0000 0000 RW RW RW 15 PLLRSTB 14 PLLEN 13 BYPASS 12 LOCKSTS 8 PREDIV 7 4 FBCTRL 3 0 PS034504-0617 7 POSTDIV 6 5 4 3 PLL reset 0 PLL reset is asserted 1 PLL reset is negated PLL enable 0 PLL is disabled 1 PLL is enabled FIN bypass 0 FOUT is bypassed as FIN 1 FOUT is PLL output LOCK status 0 PLL is not locked 1 PLL is locked FIN predivider 0 FIN divided by 1 1 FIN divided by 2 Feedback control 0000 M=6 0001 M=8 0010 M = 10 0011 M = 12 0100 M = 16 0101 M = 18 0110 M = 20 0111 M = 26 Post divider control 000 N=1 001 N=2 010 N=3 011 N=4 PRELIMINARY 2 1 0 POSTDIV 0 10 FBCTRL 0 11 PREDIV LOCKSTS 12 BYPASS 13 PLLEN 14 PLLRSTB 15 1000 1001 1010 1011 1100 1101 1110 1111 M = 32 M = 36 M = 40 M = 64 Not available 46 Z32F1281 Product Specification 100 101 110 111 PS034504-0617 System Control Unit N=6 N=8 Not available N =16 PRELIMINARY 47 Z32F1281 Product Specification VDCCON System Control Unit VDC Control Register The On-chip VDC control register, VDCTRIM, is used for the trim value of VDC output. To modify the VDCTRIM bit, write 1 to VDCTE. The VDCWDLY value can be written when writing 1 to the VDCDE bit simultaneously. 0 0 W PS034504-0617 0 0 8 0 0 0x7F W RW VDCTRIM 100 9 VDCWDLY 0 VDCTE 0 BMRTRIM BMRTE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VDCDE VDCCON=0x4000_0064 0 0 0 RW 0000 0 0 0 RW 31 BMRTE 26 24 23 BMRTRIM 19 16 8 VDCTRIM 7 0 VDCWDLY VDCTE VDCDE 0 0 0 7 6 5 4 3 2 1 0 Reference BGR trim write enable. 0 BMRTRIM field is not updated by writing 1 BMRTRIM filed can be updated by writing Reference BGR output voltage trim value VDCTRIM value write enable. Write only with VDCTRIM value. 0 VDCTRIM field is not updated by writing 1 VDCTRIM filed can be updated by writing VDC output voltage trim value VDCWDLY value write enable. Write only with VDCWDLY value 0 Disable writing warm-up delay count value 1 Enable writing warm-up delay count value VDC warm-up delay count value. When SCU is woken up from power-down mode, the warm-up delay is inserted to stabilize VDC output. The amount of delay can be defined with this register value 7F : 2msec PRELIMINARY 48 Z32F1281 Product Specification LVDCON System Control Unit LVD Control Register The LVD Control Register is an on-chip brown-out detector control register. There are four voltage levels that can be set for the Low Voltage Detect monitoring and the ability to trim the monitoring voltages. This register is a 32-bit register. 0 0 0 0 0 0 0 0 IOSCTRIM 23 LVDTE 17 16 15 LVDTRIM 9 8 LVDSEL 1 LVDLVL 0 LVDEN 4 3 2 1 0 0 0 0 0 0 0 1 LVDSEL 0 5 LVDEN 0 6 RW 0 7 LVDLVL 0 8 0 0 0 0 0 00 RW SELEN 0 RW 0 W 0 9 W 00 LVDTE LVDTRIM 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R LVDCON=0x4000_0068 0 LVDTRIM value write enable. Write only with LVDTRIM value. 0 LVDTRIM field is not updated by writing 1 LVDTRIM filed can be updated by writing LVD voltage level trim value It can writable when trim enable mode in FMC LVDSEL value write enable. Write only with LVDSEL value. 0 LVDSEL field is not updated by writing 1 LVDSEL filed can be updated by writing LVD detect level select 00 LVD detect level is 1.8V- 50mV 01 LVD detect level is 2.2V – 50mV 10 LVD detect level is 2.7V -50mV 11 LVD detect level is 4.3V – 50mV LVD Level 0 LVD level is not detected 1 LVD level is detected LVD Function enable 0 LVD is not enabled 1 LVD is enabled SELEN Internal OSC Trim Register This is the internal oscillator frequency trim register, which is a 32-bit register. IOSCTRIM=0x4000_006C 23 PS034504-0617 0 TSLEN 0 0000 00 0 0 0 3 2 1 UDCL 000 4 00 000 RW 0 5 UDCH 0 6 RW 0 UDCEN 0 W 0 LTM 0 7 RW 0 8 LT 0 9 RW 0 LTEN 0 W 0 RW 0 W 0 TSL TSLEN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 TSL trim value write enable. Write only with TSL trim value. 0 TSL field is not updated by writing PRELIMINARY 49 Z32F1281 Product Specification 18 16 15 TSL[2:0] 13 8 7 LTM/LT 4 0 UDCH/UDCL System Control Unit 1 TSL filed can be updated by writing TSL trim value LTEN LTM/LT value write enable. Write only with LTM/LT value 0 LT field is not updated by writing 1 LT filed can be updated by writing Internal oscillator LT trim value Not recommended strongly to write into this field UDCH/UDCL value write enable. Write only with UDC value 0 UDC field is not updated by writing 1 UDC filed can be updated by writing Internal oscillator UDC trim value Not recommended strongly to write into this field UDCEN All trim bits are writable when Trim mode is enabled. PS034504-0617 PRELIMINARY 50 Z32F1281 Product Specification EOSCR System Control Unit External Oscillator Control Register The External Oscillator control register provides the configuration of the external oscillator connections. The current and amplification types can be modified. The external main crystal oscillator has two characteristics. For noise immunity, the NMOS amp type is recommended and for the low power characteristic, the INV amp type is recommended. This register is a 16-bit register. EOSCR=0x4000_0080 11 10 0 0 0 0 0 0 W PS034504-0617 15 ISELEN 9 8 ISEL 7 AMPEN 0 AMPSEL 9 8 7 11 0 RW W 6 5 4 3 2 1 0 0 0 0 0 0 0 0 AMPSEL 12 AMPEN 13 ISEL 14 ISELEN 15 RW Write enable of bit field ISEL. 0 Write access of ISEL field is masked 1 Write access of ISEL field is accepted Select current. 00 Minimum current driving option 01 Low current driving option 10 High current driving option 11 Maximum current driving option Write enable of bit field AMPSEL 0 Write access of AMPSEL field is masked 1 Write access of AMPSEL field is accepted Select amplifier type 0 NMOS type 1 Inverter type PRELIMINARY 51 Z32F1281 Product Specification OPAnTRIM System Control Unit Internal OPAMP n Trim Register OPA0TRIM OPA1TRIM OPA2TRIM OPA3TRIM Internal OPAMP 0 Trim Register Internal OPAMP 1 Trim Register Internal OPAMP 2 Trim Register Internal OPAMP 3 Trim Register The Internal OPAMP Trim Register trims the OPAMP. OPATRIM0=0x4000_0070, OPATRIM1=0x4000_0074 OPATRIM2=0x4000_0078 , OPATRIM3=0x4000_007C 0 0 0 0 0 0 0 0 0 0 W PS034504-0617 0 RW W 23 ABMEN 18 16 15 ABM[1:0] 11 8 7 GTRIMHL[1:0]/G TRIML[1:0] ATRIMEN 3 0 ATRIM[3:0] 0 0 0 00 10 0 RW RW W 6 5 4 0 0 0 3 2 1 0 ATRIM 00 7 ATRIMEN 0 8 GTRIML 0 9 GTRIMH 0 GTRIMEN 0 ABM ABMEN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0000 RW ABM trim value write enable. Write only with ABM trim value. 0 ABM field is not updated by writing 1 ABM filed can be updated by writing OPAMP BIAS trim value GTRIMEN GTRIM value write enable. Write only with GTRIM value 0 GTRIM field is not updated by writing 1 GTRIM filed can be updated by writing OPAMP Gain trim value GAINH[1:0],GAINL[1:0] ATRIM value write enable. Write only with ATRIM value 0 ATRIM field is not updated by writing 1 ATRIM filed can be updated by writing OPAMP VIO ( Offset ) Trimming value PRELIMINARY 52 Z32F1281 Product Specification EMODR System Control Unit External Mode Status Register The External Mode Status Register shows the status of the external mode pins while booting. This register is an 8-bit register. EMODR=0x4000_0084 7 PS034504-0617 6 5 4 2 1 0 SCANMD TEST BOOT 0x0 0 0 - R R R R 2 SCANMD 1 TEST 0 BOOT 3 SCANMD pin level 0 SCANMD pin is low 1 SCANMD pin is high TEST pin level 0 TEST pin is low 1 TEST pin is high BOOT pin level 0 BOOT pin is low 1 BOOT pin is high PRELIMINARY 53 Z32F1281 Product Specification DBCLK1 System Control Unit Debounce Clock Control Register 1 The Debounce Clock Control Register 1 controls the debounce timing configuration for Port A and Port B. DBCLK1=0x4000_009C 0 PS034504-0617 0 000 0x01 RW RW 26 24 PBDCSEL 23 16 PBDDIV 10 8 PADCSEL 7 0 PADDIV 0 0 0 0 0 8 7 6 5 4 3 PADDIV 0 9 PADCSEL 0 PBDDIV 0 PBDCSEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 000 0x01 RW RW 2 1 0 Debounce Clock for Port B source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 INT OSC 20MHz 110 External Main OSC 111 PLL Clock PORT B Debounce Clock N divider PORT B Debounce clock = Clock source / PBDDIV (If PBDDIV is 0, input clock will be stopped) Debounce Clock for Port A source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 INT OSC 20MHz 110 External Main OSC 111 PLL Clock PORT A Debounce Clock N divider PORT A Debounce clock = Clock source / PADDIV (If PADDIV is 0, input clock will be stopped) PRELIMINARY 54 Z32F1281 Product Specification DBCLK2 System Control Unit Debounce Clock Control Register 2 The Debounce Clock Control Register 2 controls the debounce timing configuration for Port C and Port D. DBCLK2=0x4000_00A0 0 PS034504-0617 0 000 0x01 RW RW 26 24 PDDCSEL 23 16 PDDDIV 10 8 PCDCSEL 7 0 PCDDIV 0 0 0 0 0 8 7 6 5 4 3 PCDDIV 0 9 PCDCSEL 0 PDDDIV 0 PDDCSEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 000 0x01 RW RW 2 1 0 Debounce Clock for PORT D source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 INT OSC 20MHz 110 External Main OSC 111 PLL Clock PORT D Debounce Clock N divider PORT D Debounce clock = Clock source / PDDDIV (If PDDDIV is 0, input clock will be stopped) Debounce Clock for PORT C source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 INT OSC 20MHz 110 External Main OSC 111 PLL Clock PORT C Debounce Clock N divider PORT C Debounce clock = Clock source / PCDDIV (If PCDDIV is 0, input clock will be stopped) PRELIMINARY 55 Z32F1281 Product Specification MCCR1 System Control Unit Miscellaneous Clock Control Register 1 The Miscellaneous Clock Control Register 1 controls the configuration for both the Trace and the System Tick clocks. MCCR1=0x4000_0090 0 W PS034504-0617 0 100 0x04 RW RW 26 24 TRCSEL 23 16 TRACEDIV 10 8 STCSEL 7 0 STDIV 0 0 0 0 0 8 7 6 5 4 3 STDIV 0 9 STCSEL 0 TRACEDIV 0 TRCSEL TRCPOL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 000 0x01 RW RW 2 1 0 TRACE Clock source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 INT OSC 20MHz 110 External Main OSC 111 PLL Clock TRACE Clock N divider TRACE Clock = CLK_IN/DIV (If TRACEDIV is 0, input clock will be stopped) SYSTIC Clock source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 INT OSC 20MHz 110 External Main OSC 111 PLL Clock SYSTIC Clock N divider Systick input clock = Clock source / STDIV (If STDIV is 0 or 1, input clock will be stopped) PRELIMINARY 56 Z32F1281 Product Specification MCCR2 System Control Unit Miscellaneous Clock Control Register 2 The Miscellaneous Clock Control Register 2 controls the configuration of MPWM0 and MPWM1 clocks. MCCR2=0x4000_0094 0 PS034504-0617 0 000 0x00 RW RW 26 24 PWM1CSEL 23 16 PWM1DIV 10 8 PWM0CSEL 7 0 PWM0DIV 0 0 0 0 0 8 7 6 5 4 3 PWM0DIV 0 9 PWM0CSEL 0 PWM1DIV 0 PWM1CSEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 000 0x00 RW RW 2 1 0 PWM1 Clock source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 INT OSC 20MHz 110 External Main OSC 111 PLL Clock PWM1 Clock N divider PWM1 input clock = Clock source / PWM1DIV (If PWM1DIV is 0, input clock will be stopped) PWM0 Clock source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 INT OSC 20MHz 110 External Main OSC 111 PLL Clock PWM0 Clock N divider PWM0 input clock = Clock source / PWM0DIV (If PWM0DIV is 0, input clock will be stopped) PRELIMINARY 57 Z32F1281 Product Specification MCCR3 System Control Unit Miscellaneous Clock Control Register 3 The Miscellaneous Clock Control Register 3 controls the configuration for the Timer EXT0 and WDT clocks. MCCR3=0x4000_0098 0 PS034504-0617 0 000 0x01 RW RW 26 24 TEXT0CSEL 23 16 TEXT0DIV 10 8 WDTCSEL 7 0 WDTDIV 0 0 0 0 0 8 7 6 5 4 3 WDTDIV 0 9 WDTCSEL 0 TEXT0DIV 0 TEXT0CSEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 000 0x01 RW RW 2 1 0 TIMER EXT0 Clock source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 INT OSC 20MHz 110 External Main OSC 111 PLL Clock TEXT0 Clock N divider TEXT0 input clock = Clock source / TEXT0DIV (If TEXT0DIV is 0, input clock will be stopped) WDT Clock source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 INT OSC 20MHz 110 External Main OSC 111 PLL Clock WDT Clock N divider WDT input clock = Clock source / WDTDIV (If WDTDIV is 0, input clock will be stopped) PRELIMINARY 58 Z32F1281 Product Specification MCCR4 System Control Unit Miscellaneous Clock Control Register 4 The Miscellaneous Clock Control Register 4 controls the debounce timing configuration for the NMI pin and the clock setting for the ADC peripheral. 0x4000_00A4 0 0 000 0x00 RW RW 26 24 ADCCSEL 23 16 ADCCDIV 10 8 ETCDCSEL 7 0 ETCDDIV 0 0 0 0 0 8 7 6 5 4 3 ETCDDIV 0 9 ETCDSEL 0 ADCCDIV 0 ADCCSEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 000 0x01 RW RW 2 1 0 ADC clock source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 INT OSC 20MHz 110 External Main OSC 111 PLL Clock ADC Clock N divider ADC clock = Clock source / ADCCDIV (If ADCCDIV is 0, input clock will be stopped) Debounce Clock for ETC(NMI) source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 INT OSC 20MHz 110 External Main OSC 111 PLL Clock ETC Debounce Clock N divider ETC clock = Clock source / ETCDDIV (If ETCDDIV is 0, input clock will be stopped) Functional Description System Clock Setup Procedure Example for the Internal Clock with PLL         Configure the FM.CR (after selecting CFG mode through FM.MR) register to the maximum wait Enable the internal clock IOSC in the CSCR register. Write 0x02 to the SCCR register (system clock control register) to select the IOSC as the PLL source (FIN) with bypassing the PLL output In the PLLCON register, Set bits 14,15 to enable PLL, clear bit 13 to bypass PLL output and configure bits 0-8 to the PREDIV/FBCTRL/POSTDIV for desired PLL output. For full speed, the PLLCON register would be set to 0xC110 Wait for the PLL to be locked by monitoring the LOCK bit (bit 12) in the PLLCON register. Set bit 13 of the PLLCON register to enable the PLL output Set bit 0 of SCCR to enable the PLL for the system clock Set the FM.CR (after selecting CFG mode through FM.MR) register for the appropriate Flash Wait states for the speed selected. PS034504-0617 PRELIMINARY 59 Z32F1281 Product Specification System Control Unit System Clock Setup Procedure Example for the External Clock with PLL                  Enable the Port C peripheral and clock in the SCU PER1 and PCER1 registers Unlock the Port Controller using the PORTEN register as defined in PORT CONTROL UNIT (PCU) Enable the Alternative function 01b for pins 12 and 13 on PORT C through the PCC_MR register Set the Pin type for pins 12 and 13 on PORT C to analog (11b) Lock the Port Controller by writing any value to PORTEN register Configure the FM.CR (after selecting CFG mode through FM.MR) register to the maximum wait If not already enabled, enable Internal oscillator in CSCR Set bit 3 in the CMR register to monitor External Oscillator Enable External Oscillator in CSCR register Wait for bit 0 of the CMR register to be set. Note: if the external oscillator does not start, this bit will never be set. Wait for an additional time (more than 1 ms) to allow the oscillator to stabilize Write 0x06 to the SCCR register (system clock control register) to select the External Oscillator as the PLL source (FIN) Set PLLCON high byte (8-15) to 0xC and low byte (0-7) to the FBCTRL/POSTDIV for desired PLL output. Wait until bit 12 of PLLCON is set. Note: if the PLL does not lock, this bit will never be set. Set bit 13 to enable the PLL output Set bit 0 of SCCR to enable the PLL for the system clock Set the FM.CR (after selecting CFG mode through FM.MR) register for the appropriate Flash Wait states for the speed selected. To Enable Clock Out for monitoring actual clock output        Enable the Port C peripheral and clock in the SCU PER1 and PCER1 registers Unlock the Port Controller using the PORTEN register as defined in PORT CONTROL UNIT (PCU) Enable the Alternative function 01b for pin 9 on PORT C through the PCC_MR register Set the Pin type for pin 9 on PORT C to output (00b) Lock the Port Controller by writing any value to PORTEN register Set bit 4 of the COR register (Clock Output Register) to enable the output Configure the CLKODIV to the desired output divider PS034504-0617 PRELIMINARY 60 Z32F1281 Product Specification Port Control Unit 5. Port Control Unit Overview The Port Control Unit (PCU) controls the external I/O configuration to:      Set the multiplex state of each pin (for alternative functions) Set external signal type (Analog / Push-Pull output /Open Drain output /Input) Set enable/monitor/trigger type for interrupts for each pin Set internal pull-up register control for each pin Set debounce for each pin Note: You must enable both the Port Peripheral and the Port Peripheral Clock in PER1/PCER1/ to use the pins of the port. Figure 5.1 shows a block diagram of the PCU. Figure 5.2 and Figure 5.3 show I/O Port Block diagrams. APB BUS Function I/Os NVIC PORT CONTROL FUNCTION MUX PA/PB/PC PD/PE/PF PORTs INTERRUPT CONTROL Figure 5.1. PCU Block Diagram PS034504-0617 PRELIMINARY 61 Z32F1281 Product Specification Port Control Unit VDDI O Pull-up Enable VDDI VDDI O Open-drain Enable O Input Mode Port MUX PIN -ad GPIO output 00 01 10 11 Function 1 Output Function 1 Output Function 3 Output Analog Disable 0 Function Input 1 Debounce Logic Debounce Enable Debounce Count Analog Input (AN0~AN15, XTALI,XTALO,SXIN, SXOUT) Figure 5.2. I/O Port Block Diagram (ADC and External Oscillator Pins) VDDI O Pull-up Enable VDDI O Open-drain Enable VDDI O Input Mode Port MUX PIN -ad GPIO output Function 1 Output Function 1 Output 00 01 10 11 Function 3 Output Analog Disable Function Input 0 1 Debounce Logic Debounce Enable * Debounce Count Figure 5.3. I/O Port Block Diagram (General I/O Pins) PS034504-0617 PRELIMINARY 62 Z32F1281 Product Specification Port Control Unit Pin Multiplexing GPIO pins have alternative function pins. Table 5.1 shows the pin multiplexing information. Table 5.1. GPIO Alternative Function FUNCTION PORT PA PB 00 01 10 11 0 PA0* AIN0/COMP0 1 PA1* AIN1/COMP1 2 PA2* AIN2/COMP2 3 PA3* AIN3/COMP3 4 PA4* T0O AIN4 5 PA5* T1O AIN5 6 PA6* T2O AIN6/CREF0 7 PA7* TRACED3 T3O AIN7/CREF1 8 PA8* TRACECLK AD0O AIN8 9 PA9* TRACED0 AD1O AIN9 10 PA10* TRACED1 AD2O AIN10 11 PA11* TRACED2 12 PA12* SS0 13 PA13* SCK0 AIN13 14 PA14* MOSI0 AIN14 15 PA15* MISO0 AIN15 0 PB0* PWM0H0 1 PB1* PWM0L0 2 PB2* PWM0H1 3 PB3* PWM0L1 4 PB4* PWM0H2 T9C 5 PB5* PWM0L2 T9O 6 PB6* PRTIN0 WDTO 7 PB7* OVIN0 8 PB8* PRTIN1 RXD3 9 PB9* OVIN1 TXD3 10 PB10* PWM1H0 11 PB11* PWM1L0 12 PB12* PWM1H1 13 PB13* PWM1L1 14 PB14* PWM1H2 15 PB15* PWM1L2 AIN11 AD2I AIN12 (2) (*) Indicates default pin setting (2) Indicates secondary port PS034504-0617 PRELIMINARY 63 Z32F1281 Product Specification Port Control Unit Table 5.1. GPIO Alternative Function (Continued) FUNCTION PORT PC PD 00 01 10 11 0 PC0 TCK/SWCLK* 1 PC1 TMS/SWDIO* 2 PC2 TDO/SWO* 3 PC3 TDI* 4 PC4 nTRST* T0C/PHA (2) 5 PC5* RXD1 T1C/PHB (2) 6 PC6* TXD1 T2C/PHZ 7 PC7* SCL0 T3C 8 PC8* SDA0 9 PC9* CLKO 10 PC10 nRESET* 11 PC11/BOOT* 12 PC12* XIN 13 PC13* XOUT 14 PC14* RXD0 MISO0 (2) 15 PC15* TXD0 MOSI0 (2) 0 PD0* SS1 1 PD1* SCK1 2 PD2* MOSI1 3 PD3* MISO1 4 PD4* SCL1 5 PD5* SDA1 6 PD6* TXD2 AD0I 7 PD7* RXD2 AD1I 8 PD8* 9 PD9* 10 PD10* AD0SOC T0C/PHA 11 PD11* AD0EOC T1C/PHB 12 PD12* AD1SOC T2C/PHZ 13 PD13* AD1EOC T3C 14 PD14* AD2SOC 15 PD15* AD2EOC (2) T8O T8C WDTO (*) Indicates default pin setting (2) Indicates secondary port PS034504-0617 PRELIMINARY 64 Z32F1281 Product Specification Port Control Unit Registers The base address of the PCU block is 0x4000_1000. Table 5.2. Base Address of Port PORT ADDRESS PA 0x4000_1000 PB 0x4000_1100 PC 0x4000_1200 PD 0x4000_1300 Table 5.3. PCU Register Map PS034504-0617 Register Offset R/W Description PnMR 0x--00 R/W Port n pin mux select register PnCR 0x--04 R/W Port n pin control register PnPCR 0x--08 R/W Port n internal pull-up control register PnDER 0x--0C R/W Port n debounce control register PnIER 0x--10 R/W Port n interrupt enable register PnISR 0x--14 R/W Port n interrupt status register PnICR 0x--18 R/W Port n interrupt control register PORTEN 0x1FF0 R/W Port Access enable PRELIMINARY 65 Z32F1281 Product Specification Port Control Unit PAMR PORT A Pin MUX Register PAMR is the PA port mode select register. This register and the PERx and PCERx registers must be configured properly before using the port to guarantee its functionality. PERx enables the port and PCERx enables the clock to the port. PAMR=0x4000_1000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 9 8 PA4 7 6 PA3 5 4 PA2 3 2 PA1 1 0 PA0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW SELECTION BIT PORT PS034504-0617 00 01 10 11 PA0 PA0 AN0_CP0 PA1 PA1 AN1_CP1 PA2 PA2 AN2_CP2 PA3 PA3 AN3_CP3 PA4 PA4 T0O AN4 PA5 PA5 T1O AN5 PA6 PA6 T2O AN6_CREF0 PA7 PA7 TRACED3 T3O AN7_CREF1 PA8 PA8 TRACECLK AD0O AN8 PA9 PA9 TRACED0 AD1O AN9 PA10 PA10 TRACED1 AD2O AN10 PA11 PA11 TRACED2 PA12 PA12 SS0 PA13 PA13 SCK0 AN13 PA14 PA14 MOSI0 AN14 PA15 PA15 MISO0 AN15 AN11 AD2I PRELIMINARY AN12 66 Z32F1281 Product Specification PBMR Port Control Unit PORT B Pin MUX Register PBMR is the PB port mode select register. This register and the PERx and PCERx registers must be configured properly before using the port to guarantee its functionality. PERx enables the port and PCERx enables the clock to the port. PBMR=0x4000_1100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 9 8 PB4 7 6 PB3 5 4 PB2 3 2 PB1 1 0 PB0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW SELECTION BIT PORT PS034504-0617 00 01 10 PB0 PB0 MP0UH PB1 PB1 MP0UL PB2 PB2 MP0VH PB3 PB3 MP0VL PB4 PB4 MP0WH T9C PB5 PB5 MP0WL T9O PB6 PB6 PRTIN0 WDTO PB7 PB7 OVIN0 PB8 PB8 PRTIN1 RXD3 PB9 PB9 OVIN1 TXD3 PB10 PB10 MP1UH PB11 PB11 MP1UL PB12 PB12 MP1VH PB13 PB13 MP1VL PB14 PB14 MP1WH PB15 PB15 MP1WL PRELIMINARY 11 67 Z32F1281 Product Specification PCMR Port Control Unit PORT C Pin MUX Register PCMR is the PC port mode select register. This register and the PERx and PCERx registers must be configured properly before using the port to guarantee its functionality. PERx enables the port and PCERx enables the clock to the port. PCMR=0x4000_1200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 9 8 7 PC4 6 PC3 5 4 PC2 3 2 PC1 1 0 PC0 00 00 00 00 00 01 00 00 00 00 00 01 01 01 01 01 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW SELECTION BIT PORT PS034504-0617 00 01 10 PC0 PC0 TCK_SWCLK PC1 PC1 TMS_SWDIO PC2 PC2 TDO_SWO PC3 PC3 TDI PC4 PC4 nTRST T0C_PHA PC5 PC5 RXD1 T1C_PHB PC6 PC6 TXD1 T2C_PHZ PC7 PC7 SCL0 T3C PC8 PC8 SDA0 PC9 PC9 CLKO PC10 PC10 nRESET PC11 PC11(BOOT) PC12 PC12 XIN PC13 PC13 XOUT PC14 PC14 RXD0 MISO0 PC15 PC15 TXD0 MOSI0 11 T8O T8C PRELIMINARY 68 Z32F1281 Product Specification PDMR Port Control Unit PORT D Pin MUX Register PDMR is the PD port mode select register. This register and the PERx and PCERx registers must be configured properly before using the port to guarantee its functionality. The PERx enables the port and PCERx enables the clock to the port. PDMR=0x4000_1300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 9 8 PD4 7 6 PD3 5 4 PD2 3 2 PD1 1 0 PD0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW SELECTION BIT PORT PS034504-0617 00 01 10 PD0 PD0 SS1 PD1 PD1 SCK1 PD2 PD2 MOSI1 PD3 PD3 MISO1 PD4 PD4 SCL1 PD5 PD5 SDA1 PD6 PD6 TXD2 AD0I PD7 PD7 RXD2 AD1I PD8 PD8 11 WDTO PD9 PD9 PD10 PD10 AD0SOC T0C_PHA PD11 PD11 AD0EOC T1C_PHB PD12 PD12 AD1SOC T2C_PHZ PD13 PD13 AD1EOC T3C PD14 PD14 AD2SOC PD15 PD15 AD2EOC PRELIMINARY 69 Z32F1281 Product Specification PnCR Port Control Unit PORT n Pin Control Register (Except for PCCR) PnCR is the input or output control of each port pin. Each pin can be configured as an input pin, output pin, or open-drain pin. PACR=0x4000_1004, PBCR=0x4000_1104, PDCR=0x4000_1304 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 9 P5 8 7 P4 6 5 P3 4 3 P2 2 1 P1 0 P0 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Pn Port control 00 Push-pull output 01 Open-drain output 10 Input 11 Analog PCCR PORT C Pin Control Register This register controls the input or output of each port pin. Each pin can be configured as an input pin, output pin, or open-drain pin. PCCR=0x4000_1204 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 11 11 11 11 10 10 11 11 11 11 11 10 10 00 10 10 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Pn PnPCR Port control 00 Push-pull output 01 Open-drain output 10 Input 11 Analog PORT n Pull-up Resistor Control Register Every pin in the port has on-chip pull-up resistors which can be configured by the PnPCR registers. PUE14 PUE13 PUE12 PUE11 PUE10 PUE9 PUE8 7 6 5 4 3 2 1 0 PUE0 8 PUE1 9 PUE2 10 PUE3 11 PUE4 12 PUE5 13 PUE6 14 PUE7 15 PUE15 PAPCR=0x4000_1008, PBPCR=0x4000_1108 PCPCR=0x4000_1208, PDPCR=0x4000_1308 0000 RW n PS034504-0617 PUEn Port pull-up control 0 Disable pull-up resistor 1 Enable pull-up resister PRELIMINARY 70 Z32F1281 Product Specification PnDER Port Control Unit PORT n Debounce Enable Register Every pin in the port has a digital debounce filter which can be configured by the PnDER registers. The Debounce clock can be configured in the DBCLKx registers. PDE14 PDE13 PDE12 PDE11 PDE10 PDE9 PDE8 7 6 5 4 3 2 1 0 PDE0 8 PDE1 9 PDE2 10 PDE3 11 PDE4 12 PDE5 13 PDE6 14 PDE7 15 PDE15 PADER=0x4000_100C, PBDER=0x4000_110C PCDER=0x4000_120C, PDDER=0x4000_130C 0000 RW n PDEn Pin debounce enable 0 Disable debounce filter 1 Enable debounce filter PnIER PORT n Interrupt Enable Register Each individual pin can be an external interrupt source. The edge trigger interrupt and level trigger interrupt are both supported. The interrupt mode can be configured by setting the PnIER registers. PAIER=0x4000_1010, PBIER=0x4000_1110 PCIER=0x4000_1210, PDIER=0x4000_1310 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 PIE15 PIE4 PIE14 PIE13 PIE12 PIE11 PIE10 PIE9 PIE8 PIE7 PIE6 PIE5 8 7 6 PIE3 5 4 PIE2 3 2 PIE1 1 0 PIE0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PIEn PS034504-0617 Pin interrupt enable 00 Interrupt disabled 01 Enable interrupt as level trigger mode 10 Reserved 11 Enable interrupt as edge trigger mode PRELIMINARY 71 Z32F1281 Product Specification Port Control Unit PnISR PORT n Interrupt Status Register When an interrupt is delivered to the CPU, the interrupt status can be detected by reading the PnISR register. The PnISR register will report a source pin of interrupt and a type of interrupt. PAISR=0x4000_1014, PBISR=0x4000_1114 PCISR=0x4000_1214, PDISR=0x4000_1314 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 PIS15 PIS14 PIS13 PIS12 PIS11 PIS10 PIS9 PIS8 PIS7 PIS6 PIS5 PIS4 PIS3 PIS2 PIS1 PIS0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PISn 8 7 6 5 4 3 2 1 0 Pin interrupt status 00 No interrupt event 01 Low level interrupt or Falling edge interrupt event is present 10 High level interrupt or rising edge interrupt event is present 11 Both of rising and falling edge interrupt event is present in edge trigger interrupt mode. Not available in level trigger interrupt mode PnICR PORT n Interrupt Control Register This is the Interrupt mode control register. PAICR=0x4000_1018, PBICR=0x4000_1118 PCICR=0x4000_1218, PDICR=0x4000_1318 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 PIC15 PIC14 8 7 6 5 4 3 2 1 0 PIC13 PIC12 PIC11 PIC10 PIC9 PIC8 PIC7 PIC6 PIC5 PIC4 PIC3 PIC2 PIC1 PIC0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PICn PS034504-0617 Pin interrupt mode 00 Prohibit external interrupt 01 Low level interrupt or Falling edge interrupt mode 10 High level interrupt or rising edge interrupt mode 11 Both of rising and falling edge interrupt mode. Not support for level trigger mode PRELIMINARY 72 Z32F1281 Product Specification PORTEN Port Control Unit Port Access Enable Register The Port Access Enable register enables the register writing permission of all PCU registers. PORTEN=0x4000_1FF0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PORTEN -WO 7 0 PS034504-0617 PORTEN Writing the sequence of 0x15 and 0x51 in this register enables writing to PCU registers, and writing other values protects all PCU registers from writing. PRELIMINARY 73 Z32F1281 Product Specification Port Control Unit Functional Description All the GPIO pins can be configured for different operations – inputs, outputs, and triggered interrupts (both level and edge) through the PDU. The system is also able to disable ports by setting the PER1 and PCER1 registers in the SCU. By default, all pins are disabled (except for UART0/SPI0) so the developer must enable these to operate. All configuration parameters are protected by the Port Access Enable register. You must write the sequence in order (0x15, 0x51) to the PORTEN register to configure any pin(s). Once the configuration is complete, write any other value to the PORTEN register to lock it. Note: Do not read in between the sequence; it will prevent the configuration registers from being unlocked. When the input function of I/O port is used by the Pin Control Register, the output function of I/O port is disabled. The Port Function differs according to the Pin Mux Register. The Input Data Register captures the data present on the I/O pin or debounced input data at every GPIO clock cycle. INPUT CONTROL LOGIC R/W GPIO IN FUNC 2 IN FUNC 3 IN De-Bounce Enable Register P-MOS 00 0 DEMUX FUNC 1 IN Pull Up Register R/W VDD 01 1 10 200 Ohm 200 Ohm De-Bounce Logic 11 APB AIN5V R/W VDD Pin Mux Register DIODE 00 DIODE PAD GPIO OUT FUNC 1 OUT FUNC 2 OUT FUNC 3 OUT 01 VSS 10 11 R/W VDD Pin Control Register Control Logic P-MOS N-MOS VSS OUTPUT CONTROL LOGIC Figure 5.4. Port Diagram PS034504-0617 PRELIMINARY 74 Z32F1281 Product Specification Port Control Unit De-bounce CLK External Input 1 1 1 0 1 0 0 0 1 1 0 1 1 0 CNT[1:0] 01 00 11 FF=1 FF=1 FF=1 FF=1 10 De-bounced Input FF=0 1 1 1 0 1 Figure 5.5. Debounce Diagram When the debounce function of input data is used by the Debounce Enable Register, the external input data is captured by the debounce clock.  If CNT value is “01”, debounced input data is “1”.  If CNT Value is “10”, debounced input data is “0” It is possible to change the Debounce CLK of each port group used by the DBCLK Registers. PS034504-0617 PRELIMINARY 75 Z32F1281 Product Specification General Purpose I/O 6. General Purpose I/O Overview Most pins, except the dedicated function pins, can be used as general I/O ports. General input/output ports are controlled by the GPIO block.    Output signal level (H/L) select Input signal level Output Set/Clear pin by writing a 1 GPIO Port PSEL PnSRR DOUT[31:0] PnODR PCU DIN[31:0] PINs PnIDR Figure 6.1. Block Diagram Pin Description Table 6.1. External Signal PIN NAME PS034504-0617 TYPE DESCRIPTION PA IO PA0 - PA15 PB IO PB0 - PB15 PC IO PC0 - PC15 PD IO PD0 - PD15 PRELIMINARY 76 Z32F1281 Product Specification General Purpose I/O Registers The base address of GPIO is 0x4000_2000 and register map is described in Table 6.2 and Table 6.3. Table 6.2. Base Address of Each Port PORT Address PA PORT 0x4000_2000 PB PORT 0x4000_2100 PC PORT 0x4000_2200 PD PORT 0x4000_2300 Table 6.3. GPIO Register Map Name Offset R/W PnODR 0x--00 R/W Port n Output data register 0x00000000 PnIDR 0x--04 RO Port n Input data register 0x00000000 PnBSR 0x--08 WO Port n Pin set register 0x00000000 PnBCR 0x—0C WO Port n Pin clear register 0x00000000 PnODR Description Reset PORT n Output Data Register When the pin is set as output and GPIO mode, the pin output level is defined by the PnODR registers. PAODR=0x4000_2000, PBODR=0x4000_2100 PCODR=0x4000_2200, PDODR=0x4000_2300 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODR 0000 RW ODR Pin output level 0 Output low level 1 Output high level PnIDR PORT n Input Data Register Each pin level status can be read in the PnIDR register. Even if the pin is in an alternative mode except analog mode, the pin level can be detected in the PnIDR register. PAIDR=0x4000_2004, PBIDR=0x4000_2104 PCIDR=0x4000_2204, PDIDR=0x4000_2304 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDR 0000 RO IDR PS034504-0617 Pin current level 0 The pin is low level 1 The pin is high level PRELIMINARY 77 Z32F1281 Product Specification PnBSR General Purpose I/O PORT n Bit Set Register PnBSR is a register for controlling each bit of the PnODR register. When you write 1 to a specific bit, the corresponding bit in the PnODR register will be set. PABSR=0x4000_2008, PBBSR=0x4000_2108 PCBSR=0x4000_2208, PDBSR=0x4000_2308 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BSR 0000 WO BSR PnBCR Pin current level 0 Not effect 1 Set correspondent bit in PnODR register PORT n Bit Clear Register PnBRR is a register for controlling each bit of the PnODR register. When you write 1 to a specific bit then the correspondent bit in the PnODR register will be clear. PABCR=0x4000_200C, PBBCR=0x4000_210C PCBCR=0x4000_220C, PDBCR=0x4000_230C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BCR 0000 WO BCR Pin current level 0 Not effect 1 Clear correspondent bit in PnODR register Functional Description The GPIO registers provide the input/output condition of the GPIO pins. The input data registers give the states of the pins of the ports. The output data register is used to set the port pins. The Set and Clear registers control the pins at the individual level. When configured as output, the value written to the GPIO Output Data Register is output on the I/O Pin. When setting the Bit Set Register, set the GPIO Output Data Register high. When setting the Bit Clear Register, set the GPIO Output Data Register low. The Input Data Register captures the data present on the I/O pin or debounced input data at every GPIO clock cycle. PS034504-0617 PRELIMINARY 78 PORT CONTROL UNIT BIT CLR REGISTER ( WRITE ONLY ) OUTPUT DATA REGISTER ( READ WRITE ) BIT SET REGISTER ( WRITE ONLY ) APB INPUT DATA REGISTER ( READ ONLY ) 79 PRELIMINARY PS034504-0617 General Purpose I/O Z32F1281 Product Specification GPIO BLOCK PAD Figure 6.2. GPIO Diagram Z32F1281 Product Specification Flash Memory Controller 7. Flash Memory Controller Introduction Flash Memory Controller is an internal Flash memory interface controller with the following features:       128 KB Flash code memory 32-bit read data bus width Code cache block for fast access mode 128-byte page size Support page erase and macro erase 128-byte unit program Table 7.1. Internal Flash Specification Item Description Size 128KB Start Address 0x0000_0000 End Address 0x0001_FFFF Page Size 128-byte Total Page Count 1,024 pages PGM Unit 128-byte Erase Unit 128-byte Figure 7.1 shows a block diagram of the Flash Memory Controller. PS034504-0617 PRELIMINARY 80 Z32F1281 Product Specification Flash Memory Controller B U S AHB BUS Read CACHE C O N T R O L APB BUS Register file CODE FlashROM 128KB (32K x 32bit) M U X Figure 7.1. Flash Memory Controller Block Diagram Pin Description There are no external interface pins for this peripheral. Registers The base address of the Flash Memory Controller is shown in Table 7.2. Table 7.2. Flash Memory Controller Base Address Address Flash Controller PS034504-0617 0x4000_0100 PRELIMINARY 81 Z32F1281 Product Specification Flash Memory Controller Table 7.3 shows the register memory map. Table 7.3. Flash Memory Controller Register Map PS034504-0617 Name Offset R/W FMMR 0x0004 R/W Flash Memory Mode Select register Description 0x01000000 Reset FMCR 0x0008 R/W Flash Memory Control register 0x82000000 FMAR 0x000C R/W Flash Memory Address register 0x00000000 FMDR 0x0010 R/W Flash Memory Data register 0x00000000 FMTMR 0x0014 R/W Flash Memory Timer register 0x000000bb FMDRTY 0x0018 R/W Flash Memory Dirty bit FMTICK 0x001C RO Flash Memory Tick Timer FMCRC 0x0020 RO Flash Memory Read CRC Value BOOTCR 0x0074 R/W Boot ROM Remap Clear register PRELIMINARY 0x00000000 0x00000000 82 Z32F1281 Product Specification Flash Memory Controller FMMR Flash Memory Mode Register FMMR is the internal Flash Memory Mode Register. This register is a 32-bit register. FMMR=0x4000_0104 PS034504-0617 31 BOOT 24 IDLE 23 VERIFY 22 AMBAEN 17 TRMEN 16 TRM 9 FEMOD 8 FMOD 7 0 ACODE 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 5A  A5 A5  5A 81 28 0 0 0 0 0 0 4 3 ACODE 0 5 0 0 0x00 RW 0 6 FMOD 0 7 R 0 8 FEMOD 0 9 R 0 TRM 0 RW 1 TRMEN 0 RW 0 AMBAEN 0 RW 0 VERIFY 0 RW 0 IDLE 0 R R BOOT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 2 1 0 Boot mode enable status(read only) Boot mode enable status(read only) Flash Verify mode enable status(read only) AMBA mode disable AMBA mode enable (can change wait state and etc) Trim mode entry status(read only) Trim mode status(read only) Flash mode entry status(read only) Flash mode status(read only) Flash mode Trim mode CFG mode (FMCR[31:24]) PRELIMINARY 83 Z32F1281 Product Specification Flash Memory Controller FMCR Flash Memory Control Register FMCR is the internal Flash Memory Control Register. 31 HRESPD 27 PCLK2 25 CLK4 24 CLK3 23 CRCINIT 22 CRCEN 20 TIMER 17 16 TEST[1:0] 15 14 13 11 10 8 5 4 3 2 1 VPPOUT EVER PVER OTPBE OTPAE AE PMODE WE PBLD PGM ERS 0 PBR 0 1 0 1 00 01 01 10 11 6 5 PMOD WE PBLD PGM ERS PBR 0 0 0 0 0 0 0 0 RW RW RW RW RW 0 7 AE 0 8 0 0 RW RW OTPAE RW 0 RW PVER 0 OTPBE EVER 0 RW VPPOUT 0 0 0 1 0 1 0 1 0 1 0 R 0 TEST0 0 RW 0 TEST1 0 RW 0 TIMER CRCEN 0 RW CRCINIT 0 RW RW 1 RW RW PS034504-0617 0 CLK3 0 RW PCLK2 0 CLK4 TRIM0 0 RW TRIM1 0 RW 1 RW R WHRESPD TRIM2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RW FMCR=0x4000_0108 4 3 2 1 0 Disable HRESP(error response function) of Data or System bus (HRESP is AMBA AHB signal) Set this bit when PCLK is 1/2 of HCLK (default PCLK = HCLK) It affects state machine of PMODE operation If CLK4, CLK3 are 00, flash access in 5 cycles Flash access in 4 cycles If CLK4, CLK3 are 00, flash access in 5 cycles Flash access in 3 cycles CRC register will be initialized. It should be reset again before read flash to generate CRC16 calculation (Initial value of FMCRC is 0xFFFF) CRC16 enable CRC value will be calculated at every flash read timing Program/Erase timer enable (timer can be enable by PGM or ERS bit) Normal operation (read) Row voltage mode (write) ODD Row program Even Row program All Row program Enable charge-pump Vpp output Set erase verify mode Set program verify mode OTP area B enable OTP area A enable All erase enable PMODE enable(Address path changing) Write enable Page buffer load(WE should be set) Program enable Program mode enable Erase mode enable Page buffer reset PRELIMINARY 84 Z32F1281 Product Specification Flash Memory Controller FMAR Flash Memory Address Register FMAR is the internal Flash memory program erase address register. FMAR=0x4000_010C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FADDR 0 0x0000 RW 14 0 FADDR 32K words address (one word = 4 bytes) FMDR Flash Memory Data Register FMDR is the internal Flash memory program data register. FMDR=0x4000_0110 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FDATA 0x0000_0000 RW 31 0 FMTMR FDATA Flash PGM data (32-bit) Flash Memory Timer Register The Internal Flash Memory Timer value register (9-bit), Erase/Program timer runs up to {TMR[8:0],0xFF} FMTMR=0x4000_0114 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMR 0 0 0 0 0 0 0 0x0BB RW 8 0 PS034504-0617 TMR Erase/PGM timer (default, 0xBB) Timer counts up to {TMR[8:0], 0xFF} by 20MHz int. OSC clock PRELIMINARY 85 Z32F1281 Product Specification FMDRTY Flash Memory Controller Flash Memory Dirty Bit Register FMDRTY is the internal Flash memory dirty bit clear register. FMDRTY=0x4000_0118 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FDRTY WO 31 0 FMTICK FDRTY Write any value here, cache line fill flag will be cleared. Flash Memory Tick Timer Register FMTICK is the internal Flash memory Burst Mode channel selection register. FMTICK=0x4000_011C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FTICK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000 RW 17 0 FMCRC FTICK TICK goes to 0x3FFFF from written TICK value while TRM runs by PCLK clock Flash Memory CRC Value Register The register shows the CRC value resulting from read accesses on internal Flash memory. FMTICK=0x4000_0120 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -RO 15 0 PS034504-0617 CRC CRC16 value PRELIMINARY 86 Z32F1281 Product Specification BOOTCR Flash Memory Controller Boot ROM Remap Clear Register The Boot ROM remap clear register is an 8-bit register. BOOTCR=0x4000_0174 7 6 5 4 3 2 1 0 BOOTROM 0 0 0 0 0 0 0 1 R 0 BOOTROM Boot Mode (only can be written in boot loader mode) This bit is used to clear boot loader mode at end of boot code (when BOOTROM low, external BOOT pin signal is masked) Functional Description Flash Memory Controller is an internal Flash memory interface controller which primarily controls the programming of Flash memory and preparing read data to be requested from the bus. Flash Organization The 128 Kbytes code Flash memory consists of 1,024 pages which have a uniform 128 bytes page size. The Flash controller allows reading or writing of Flash memory data. This memory is located at 0x0000_0000 address on the system memory map. The system boot address is 0x0000_0000; therefore, this Flash memory is boot memory. The code data which is programmed in Flash memory will boot up the device after the boot ROM sequence is completed. Flash Read Operation The Flash data read operation is requested from the bus. The Flash controller responds to the request. The wait time should be correctly defined because the bus speed is usually faster than Flash data access time. The normal read operation is not available in Flash mode in the ACODE.FM.MR field. Flash Program Operation The erase and program access of Flash memory is available only in Flash mode in the ACODE.FM.MR field. Therefore, self-programming is not supported. The Flash program/erase operation should be performed by the execution program on the SRAM memory. The Flash program operation writes one page to the target address selected by the FM.AR register. At first, users should write the program data into the page buffer. Page buffer write is performed by word write access to the FM.DR register at FM.AR address. After filling the page buffer, users can begin the Flash write operation and should wait for the IDLE bit to be set. Figure 7.2 shows the page buffer loading operation. PS034504-0617 PRELIMINARY 87 Z32F1281 Product Specification Flash Memory Controller Figure 7.2. Page Buffer Load Timing Diagram The Flash write of page buffer data is done by the PRGM.FM.CR command. A safe writing operation requires the correct program time. The tPGM program time is defined by the FM.TMR register. When the timer is activated (TIMER.FM.CR bit is set), the IDLE.FM.MR bit is cleared and the Flash controller will start counting the HCLK pulses until the pulse count matches the value in the FM.TMR. When the count is reached, the Flash controller will set the IDLE.FM.MR bit to show the time has elapsed. In this page write operation, the target page address should be written in the FM.AR register. Figure 7.3 shows the page write operation. Figure 7.3. Page Write Timing Diagram Flash Erase Operation The erase and program access of Flash memory is available only in Flash mode in the ACODE.FM.MR field. Therefore, self-programming is not supported. The Flash program/erase operation should be performed by the execution program on the SRAM memory. Two types of Flash erase operations are supported – Page erase and Bulk erase. The page erase operation erases one page to the target address selected by the FM.AR register. User starts the Flash write operation and should wait for the IDLE bit to be set. The bulk erase operation erases the entire Flash memory data and the FM.AR address is ignored. The process is the same between page and bulk erase with the exception of the AE.FM.CR bit. When the AE.FM.CR bit is set, the Flash controller will perform a bulk erase. Figure 7.4 shows the page erase operation. PS034504-0617 PRELIMINARY 88 Z32F1281 Product Specification Flash Memory Controller Figure 7.4. Page Erase Timing Diagram Flash erase is done by the ERS.FM.CR command. A safe writing operation requires the correct program time. The tERS erase time is defined by the FM.TMR register. When the timer is activated (TIMER.FM.CR bit is set), the IDLE.FM.MR bit is cleared and the Flash controller will start counting the HCLK pulses until the pulse count matches the value in the FM.TMR. When the count is reached, the Flash controller will set the IDLE.FM.MR bit to show the time has elapsed. Figure 7.5 shows the bulk erase operation. Figure 7.5. Bulk Erase Timing Diagram The Flash area can be read from directly via the memory address. Writing of Flash memory can be done through Boot mode or in-application programming. The execution for the writing of Flash must occur from the RAM area. The Flash controller cannot read Flash memory (including instructions) once the program bit has been set. Caution: If the vector table is not placed in RAM, you MUST disable interrupts so as to prevent reading the interrupt service routine in Flash. To write to Flash memory: 1. Disable the Watch Dog Timer (if enabled). 2. Set the clock to internal oscillator ( 20 MHz ). 3. Write configuration sequence to the MR register to enable Control Register upper bits (24-31). 4. Configure upper bits of the Control Register (HRESPD and Flash access of 4 cycles). 5. Lock the Flash controller by writing 0x00 to the MR register. PS034504-0617 PRELIMINARY 89 Z32F1281 Product Specification 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. Flash Memory Controller Write the Flash sequence to the MR register. Clear the DRTY register. Set the PMODE bit in the CR register to set Program Mode. Wait until the IDLE bit in MR register is set. Reset the page buffer (setting and clearing PBR bit in CR register). Set the PBLD bit in the CR register to allow the page buffer to be written to. Write to the page buffer by loading the DR register with each 32-bit word of the page. Clear the PBLD bit in the CR register. Write the address to which the page buffer will be written (in 32-bit words) to the AR register. Set the PGM bit in the CR register. Set the WE bit in the CR register to start writing. Wait until the IDLE bit in MR register is set. Clear the WE bit in the CR register. Clear the PGM bit in the CR register. If there are additional pages to write, repeat the process, starting at step 10. Load 2500 into the TMR register (2.5mS). Set the TIMER bit in the CR register to start the timer. Wait until the IDLE bit in the MR register is set. Clear the Timer bit in the CR register to stop the timer. Clear the PMODE bit in the CR register to take out of Program Mode. Lock the Flash controller by writing 0x00 to the MR Register. Write the configuration sequence to the MR register to enable the Control Register upper bits (24-31). Restore the upper bits of the Control Register. Lock the Flash controller by writing 0x00 to the MR register. Reset the system clock to normal operations. Enable the Watch Dog timer (if desired). To erase Flash memory: 1. Disable the Watch Dog Timer (if enabled). 2. Set the clock to internal oscillator (20 MHz). 3. Write the configuration sequence to the MR register to enable Control Register upper bits (2431). 4. Configure upper bits of the Control Register (HRESPD and Flash access of 4 cycles). 5. Lock the Flash controller by writing 0x00 to the MR register. 6. Write the Flash sequence to the MR register. 7. Clear the DRTY register. 8. Set the PMODE bit in the CR register to set Program Mode. 9. Wait until the IDLE bit in the MR register is set. 10. If erasing all the Flash, set the AE bit in the CR register; otherwise, load the page address in the AR register. 11. Set the ERS bit in the CR register. 12. Set the WE bit in the CR register to start the erase operation. 13. Wait until the IDLE bit in the MR register is set. 14. Clear the WE, ERS and AE bits. 15. Load 2500 into the TMR register (2.5mS). 16. Set the TIMER bit in the CR register to start the timer. 17. Wait until the IDLE bit in the MR register is set. 18. Clear the Timer bit in the CR register to stop the timer. PS034504-0617 PRELIMINARY 90 Z32F1281 Product Specification Flash Memory Controller 19. Clear the PMODE bit in the CR register to take out of Program Mode. 20. Lock the Flash controller by writing 0x00 to the MR Register. 21. Write the configuration sequence to the MR register to enable the Control Register upper bits (24-31). 22. Restore the upper bits of the Control Register. 23. Lock the Flash controller by writing 0x00 to the MR register. 24. Reset the system clock to normal operations. 25. Enable the Watch Dog timer (if desired). The CRC16 function allows a CRC check on the Flash bytes to a known value. To run a CRC16 check on Flash bytes (must be done in memory, since every read, including instructions, would be part of the CRC16 calculations). 1. 2. 3. 4. 5. PS034504-0617 Disable the Watch Dog Timer (if enabled). Set the CRCINIT bit in the CR register. Clear the CRCINIT bit in the CR register. Read the Flash memory that is to be processed. When completed, the CRC value is located in the CRC register. PRELIMINARY 91 Z32F1281 Product Specification Internal SRAM 8. Internal SRAM Overview The Z32F1281 MCU implements zero-wait on the chip’s SRAM. The size of SRAM is 12 KB. The SRAM base address is 0x2000_0000. The SRAM memory area is usually used for data memory and stack memory. Sometimes, the code is dumped into the SRAM memory for fast operation or Flash erase/PGM operation. This device does not support a memory remap strategy; therefore, a jump and return is required to execute the code in the SRAM memory area. Figure 8.1 shows a block diagram of the SRAM. 0x0000_000 0 Code Flash (128KB) 0x0001_FFF F 0x2000_000 SRAM (12KB) 0 0x2000_5FF F Figure 8.1. SRAM Block Diagram PS034504-0617 PRELIMINARY 92 Z32F1281 Product Specification Direct Memory Access Controller 9. Direct Memory Access Controller Introduction The Direct Memory Access (DMA) controller includes the following features:  15 channels  Single transfer only  Supports 8/16/32-bit data size  Supports multiple buffers with the same size  Interrupt condition is transferred through a peripheral interrupt A block diagram of the DMA controller is shown in Figure 9.1. Figure 9.1. DMAC Block Diagram Pin Description There are no external interface pins. PS034504-0617 PRELIMINARY 93 Z32F1281 Product Specification Direct Memory Access Controller Registers The base address of the DMA controller is shown in Table 9.1. Table 9.1. DMA Controller Base Address Ch. No. BASE ADDRESS Assigned Peripheral DMACH0 0x4000_0400 UART0 RX DMACH1 0x4000_0410 UART0 TX DMACH2 0x4000_0420 UART1 RX DMACH3 0x4000_0430 UART1 TX DMACH4 0x4000_0440 UART2 RX DMACH5 0x4000_0450 UART2 TX DMACH6 0x4000_0460 UART3 RX DMACH7 0x4000_0470 UART3 TX DMACH8 0x4000_0480 SPI0 RX DMACH9 0x4000_0490 SPI0 TX DMACH10 0x4000_04A0 SPI1 RX DMACH11 0x4000_04B0 SPI1 TX DMACH12 0x4000_04C0 ADC0 DMACH13 0x4000_04D0 ADC1 DMACH14 0x4000_04E0 ADC2 Table 9.2 shows the register map of the DMA controller. Table 9.2. DMAC Register Map Name PS034504-0617 Offset R/W Description Reset DC0CR 0x0000 R/W DMA Channel 0 Control Register 0x0000_0000 DC0SR 0x0004 R/W DMA Channel 0 Status Register 0x0000_0000 DC0PAR 0x0008 R DMA Channel 0 Peripheral Address UART0_RBR DC0MAR 0x000C R/W DMA Channel 0 Memory Address 0x2000_0000 DC1CR 0x0010 R/W DMA Channel 1 Control Register 0x0000_0000 DC1SR 0x0014 R/W DMA Channel 1 Status Register 0x0000_0000 DC1PAR 0x0018 R DMA Channel 1 Peripheral Address UART0_THR DC1MAR 0x001C R/W DMA Channel 1 Memory Address 0x2000_0000 DC2CR 0x0020 R/W DMA Channel 2 Control Register 0x0000_0000 DC2SR 0x0024 R/W DMA Channel 2 Status Register 0x0000_0000 DC2PAR 0x0028 R DMA Channel 2 Peripheral Address UART1_RBR DC2MAR 0x002C R/W DMA Channel 2 Memory Address 0x2000_0000 DC3CR 0x0030 R/W DMA Channel 3 Control Register 0x0000_0000 DC3SR 0x0034 R/W DMA Channel 3 Status Register 0x0000_0000 DC3PAR 0x0038 R DMA Channel 3 Peripheral Address UART1_THR DC3MAR 0x003C R/W DMA Channel 3 Memory Address 0x2000_0000 DC4CR 0x0040 R/W DMA Channel 4 Control Register 0x0000_0000 DC4SR 0x0044 R/W DMA Channel 4 Status Register 0x0000_0000 PRELIMINARY 94 Z32F1281 Product Specification Direct Memory Access Controller DC4PAR 0x0048 R DMA Channel 4 Peripheral Address UART2_RBR DC4MAR 0x004C R/W DMA Channel 4 Memory Address 0x2000_0000 DC5CR 0x0050 R/W DMA Channel 5 Control Register 0x0000_0000 DC5SR 0x0054 R/W DMA Channel 5 Status Register 0x0000_0000 DC5PAR 0x0058 R DMA Channel 5 Peripheral Address UART2_THR DC5MAR 0x005C R/W DMA Channel 5 Memory Address 0x2000_0000 DC6CR 0x0060 R/W DMA Channel 6 Control Register 0x0000_0000 DC6SR 0x0064 R/W DMA Channel 6 Status Register 0x0000_0000 DC6PAR 0x0068 R DMA Channel 6 Peripheral Address UART3_RBR DC6MAR 0x006C R/W DMA Channel 6 Memory Address 0x2000_0000 DC7CR 0x0070 R/W DMA Channel 7 Control Register 0x0000_0000 DC7SR 0x0074 R/W DMA Channel 7 Status Register 0x0000_0000 DC7PAR 0x0078 R DMA Channel 7 Peripheral Address UART3_THR DC7MAR 0x007C R/W DMA Channel 7 Memory Address 0x2000_0000 DC8CR 0x0080 R/W DMA Channel 8 Control Register 0x0000_0000 DC8SR 0x0084 R/W DMA Channel 8 Status Register 0x0000_0000 DC8PAR 0x0088 R DMA Channel 8 Peripheral Address SPI0_RDR DC8MAR 0x008C R/W DMA Channel 8 Memory Address 0x2000_0000 DC9CR 0x0090 R/W DMA Channel 9 Control Register 0x0000_0000 DC9SR 0x0094 R/W DMA Channel 9 Status Register 0x0000_0000 DC9PAR 0x0098 R DMA Channel 9 Peripheral Address SPI0_TDR DC9MAR 0x009C R/W DMA Channel 9 Memory Address 0x2000_0000 DC10CR 0x00A0 R/W DMA Channel 10 Control Register 0x0000_0000 DC10SR 0x00A4 R/W DMA Channel 10 Status Register 0x0000_0000 DC10PAR 0x00A8 R DMA Channel 10 Peripheral Address SPI1_RDR DC10MAR 0x00AC R/W DMA Channel 10 Memory Address 0x2000_0000 DC11CR 0x00B0 R/W DMA Channel 11 Control Register 0x0000_0000 DC11SR 0x00B4 R/W DMA Channel 11 Status Register 0x0000_0000 DC11PAR 0x00B8 R DMA Channel 11 Peripheral Address SPI1_TDR DC11MAR 0x00BC R/W DMA Channel 11 Memory Address 0x2000_0000 DC12CR 0x00C0 R/W DMA Channel 12 Control Register 0x0000_0000 DC12SR 0x00C4 R/W DMA Channel 12 Status Register 0x0000_0000 DC12PAR 0x00C8 R DMA Channel 12 Peripheral Address AD0DDR DC12MAR 0x00CC R/W DMA Channel 12 Memory Address 0x2000_0000 DC13CR 0x00D0 R/W DMA Channel 13 Control Register 0x0000_0000 DC13SR 0x00D4 R/W DMA Channel 13 Status Register 0x0000_0000 DC13PAR 0x00D8 R DMA Channel 13 Peripheral Address AD1DDR DC13MAR 0x00DC R/W DMA Channel 13 Memory Address 0x2000_0000 DC14CR 0x00E0 R/W DMA Channel 14 Control Register 0x0000_0000 DC14SR 0x00E4 R/W DMA Channel 14 Status Register 0x0000_0000 DC14PAR 0x00E8 R DMA Channel 14 Peripheral Address AD2DDR DC14MAR 0x00EC R/W DMA Channel 14 Memory Address 0x2000_0000 PS034504-0617 PRELIMINARY 95 Z32F1281 Product Specification DCnCR Direct Memory Access Controller DMA Controller Configuration Register The DMA operation control register is a 32-bit register. DC0CR=0x4000_0400 , DC1CR=0x4000_0410 DC2CR=0x4000_0420 , DC3CR=0x4000_0430 DC4CR=0x4000_0440 , DC5CR=0x4000_0450 DC6CR=0x4000_0460 , DC7CR=0x4000_0470 DC8CR=0x4000_0480 , DC9CR=0x4000_0490 DC10CR=0x4000_04A0 , DC11CR=0x4000_04B0 DC12CR=0x4000_04C0 , Dc13CR=0x4000_04D0 DC14CR=0x4000_04E0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 TRANSCNT 0 0 0 0 0x000 2 1 0 0 0 SIZE 0 0 0 RW PS034504-0617 3 0 0 0 0 0 0 0 0 0 00 RW 31 16 TRANSCNT 3 2 SIZE Number of DMA transfer remaining Required transfer number should be written before enable DMA transfer. 0 DMA transfer is done N N transfers are remaining Bus transfer size 00 DMA transfer is byte size transfer 01 DMA transfer is half word size transfer 10 DMA transfer is word size transfer 11 Reserved PRELIMINARY 96 Z32F1281 Product Specification DCnSR Direct Memory Access Controller DMA Controller Status Register The DMA Controller Status Register is an 8-bit register. This register represents the current status of the DMA controller and enables the DMA function. DC0SR=0x4000_0404 , DC1SR=0x4000_0414 DC2SR=0x4000_0424 , DC3SR=0x4000_0434 DC4SR=0x4000_0444 , DC5SR=0x4000_0454 DC6SR=0x4000_0464 , DC7SR=0x4000_0474 DC8SR=0x4000_0484 , DC9SR=0x4000_0494 DC10SR=0x4000_04A4 , DC11SR=0x4000_04B4 DC12SR=0x4000_04C4 , Dc13SR=0x4000_04D4 DC14SR=0x4000_04E4 7 6 5 4 3 2 1 EOT 1 DMAEN 0 0 0 0 0 RO PS034504-0617 0 0 0 RW 7 EOT 0 DMAEN End of transfer 0 Data to be transferred exists TRANSCNT shows non zero value 1 All data is transferred TRANSCNT shows now 0 DMA Enable 0 DMA is in stop or hold state 1 DMA is running or enabled PRELIMINARY 97 Z32F1281 Product Specification DCnPAR Direct Memory Access Controller DMA Controller Peripheral Address Register The DMA Controller Peripheral Address register represent the peripheral address. DC0PAR=0x4000_0408 , DC1PAR=0x4000_0418 DC2PAR=0x4000_0428 , DC3PAR=0x4000_0438 DC4PAR=0x4000_0448 , DC5PAR=0x4000_0458 DC6PAR=0x4000_0468 , DC7PAR=0x4000_0478 DC8PAR=0x4000_0488 , DC9PAR=0x4000_0498 DC10PAR=0x4000_04A8,, DC11PAR=0x4000_04B8 DC12PAR=0x4000_04C8,, Dc13PAR=0x4000_04D8 DC14PAR=0x4000_04E8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAR DC0PAR=U0RBR, DC1PAR=U0THR DC2PAR=U10RBR, DC3PAR=U10THR DC4PAR=U20RBR, DC5PAR=U20THR DC6PAR=U30RBR, DC7PAR=U30THR DC8PAR=SPI0_RDR, DC9PAR=SPI0_TDR DC10PAR=SPI1_RDR, DC11PAR=SPI1_TDR DC12PAR=AD0DDR, DC13PAR=AD1DDR, DC14PAR=AD2DDR RO 31 0 PS034504-0617 PAR Target Peripheral address of transmit buffer or receive buffer. Address is fixed address when each transfer is done. PRELIMINARY 98 Z32F1281 Product Specification DCnMAR Direct Memory Access Controller DMA Controller Memory Address Register The DMA Controller Memory Address register represents the memory address. DC0MAR=0x4000_040C , DC1MAR=0x4000_041C DC2MAR=0x4000_042C , DC3MAR=0x4000_043C DC4MAR=0x4000_044C , DC5MAR=0x4000_045C DC6MAR=0x4000_046C , DC7MAR=0x4000_047C DC8MAR=0x4000_048C , DC9MAR=0x4000_049C DC10MAR=0x4000_04AC,, DC11MAR=0x4000_04B8C DC12MAR=0x4000_04CC,, Dc13MAR=0x4000_04DC DC14MAR=0x4000_04EC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAR 0x2000 0x0000 RO RW 31 0 MAR Target memory address of data transfer. Address is automatically incremented according to SIZE bits when each transfer is done. Functional Description The DMA controller performs direct memory transfer by sharing the system bus with the CPU core. The system bus is shared by two AHB masters following the round-robin priority strategy. Therefore, the DMA controller can share half of the system bandwidth. The DMA controller can be triggered only by a peripheral request. When a peripheral requests the transfer to the DMA controller, the related channel is activated and accesses the bus to transfer the requested data from memory to the peripheral data buffer or from the peripheral data buffer to memory space. The transfer process involves the following steps: 1. 2. 3. 4. 5. 6. 7. 8. 9. User sets the peripheral and memory addresses. User configures the DMA operation mode and transfer count. User enables the DMA channel. The peripheral sends a DMA request. DMA activates the channel that was requested. DMA reads data from the source address and saves it to the internal buffer. DMA writes the buffered data to the destination address. The transfer count number is decreased by 1. When the transfer count becomes 0, the EOT flag is set and a notice is sent to the peripheral to issue the interrupt. 10. DMA does not have an interrupt source; the interrupt-related DMA status can be shown from the assigned peripheral interrupt. PS034504-0617 PRELIMINARY 99 Z32F1281 Product Specification Direct Memory Access Controller DST MODE DST_CH0 dma_done0 CNT_CH0 haddr0 SRC_CH0 dma_ack SRC MODE dma_req dma_req_n FSM EN_CHn haddr AHB IDLE_TIMER DST MODE DST_CH1 haddr1 SRC_CH1 CNT_CH1 dma_done0 SRC MODE Figure 9.2. DMA Controller Block Diagram Figure 9.3 shows the functional timing diagram of the DMA controller. The transfer request from the peripheral is pended internally and it invokes source data read transfer on the AHB bus. The read data from the source address is stored in the internal buffer. This data is transferred to the destination address when the AHB bus is available. The timing diagram for a DMA transfer from peripheral to memory is shown in Figure 9.3. A 4-clock cycle latency exists when accessing the peripheral. If the bus is occupied by a different bus master, the number of bus waiting cycles increase until the bus is available. Figure 9.3. DMA Transfer from Peripheral to Memory The timing diagram for a DMA transfer from memory to peripheral is shown in Figure 9.4. A 4-clock cycle latency exists while accessing the peripheral. If the bus is occupied by a different bus master, the number of bus waiting cycles increase until the bus is available. PS034504-0617 PRELIMINARY 100 Z32F1281 Product Specification Direct Memory Access Controller Figure 9.4. DMA Transfer from Memory to Peripheral Figure 9.5 is an example of N data transfers with the DMA. The DMA transfer is started when DCnSR.DMAEN is set and will be cleared when all transfers are completed. Figure 9.5. N DMA Transfer Example PS034504-0617 PRELIMINARY 101 Z32F1281 Product Specification Watch-Dog Timer 10. Watch-Dog Timer Overview The Watchdog Timer can monitor the system and generate an interrupt or a reset. It has a 32-bit downcounter. The Miscellaneous Clock Control Register 3 provides base clock options with clock dividers to drive the WDT clock. This can be selected in the WDTCON register. To prevent the WDT from firing, reload the LR register with the appropriate value before the WDT times out. Features include:      32-bit down counter (WDTCVR) Select reset or periodic interrupt Count clock selection Dedicated prescaler Watchdog overflow output signal Figure 10.1 shows a block diagram of the Watch-dog Timer. Figure 10.1. WDT Block Diagram PS034504-0617 PRELIMINARY 102 Z32F1281 Product Specification Watch-Dog Timer Registers The base address of the watch-dog timer is 0x4000_0200 and the register map is described in Table 10.1. The initial watch-dog time-out period is set to 2000-miliseconds. Table 10.1. Watchdog Timer Register Map WDTLR Name Offset R/W WDTLR 0x0000 R/W WDTCNT 0x0004 R WDTCON 0x0008 R/W Description Reset WDT Load register 0x00000000 WDT Current counter register 0x0000FFFF WDT Control register 0x0000805C Watchdog Timer Load Register The WDTLR register is used to update the WDTCVR register. To update the WDTCVR register, the WDTEN bit of WDTCON should be set to 1 and written into the WDTLR register with target value of WDTCVR. WDTLR=0x4000_0200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTLR 0x0000_0000 RW 31 0 WDTCNT WDTLR Watchdog timer load value register Keeping WDTEN bit as ‘1’, write WDTLR register will update WDTCVR value with written value Watchdog Timer Current Counter Register The WDTCNT register represents the current count value of the 32-bit down counter .When the counter value reaches 0, an interrupt or reset will take effect. WDTLR=0x4000_0204 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTCNT 0x0000_FFFF R 31 0 PS034504-0617 WDTCNT Watchdog timer current counter register 32-bit down counter will run from the written value. PRELIMINARY 103 Z32F1281 Product Specification WDTCON Watch-Dog Timer Watchdog Timer Control Register The WDT module should be configured properly before running. When the target purpose is defined, the WDT can be configured in the WDTCON register. 11 10 9 8 WDTIE WDTRE 1 0 0 0 0 0 0 0 0 1 R RW RW RW 15 WDBG 8 WUF 7 WDTIE 6 WDTRE 4 WDTEN 3 CKSEL 2 0 WPRS[2:0] 7 6 5 4 WPRS 12 CKSEL 13 WDTEN 14 WDBG 15 WUF WDTCON=0x4000_0208 3 2 1 0 1 1 100 RW RW RW 0 Watchdog operation control in debug mode 0 Watchdog counter running when debug mode 1 Watchdog counter stopped when debug mode Watchdog timer underflow flag (This bit is cleared when WDTLR is written) 0 No underflow 1 Underflow is pending Watchdog timer counter underflow interrupt enable 0 Disable interrupt 1 Enable interrupt Watchdog timer counter underflow reset enable 0 Disable reset 1 Enable reset Watchdog Counter enable 0 Watch dog counter disabled 1 Watch dog counter enabled WDTCLKIN clock source select 0 PCLK 1 External clock (MCCR3) Counter clock prescaler WDTCLK = WDTCLKIN/WPRS 000 WDTCLKIN 001 WDTCLKIN / 4 010 WDTCLKIN / 8 011 WDTCLKIN / 16 100 WDTCLKIN / 32 101 WDTCLKIN / 64 110 WDTCLKIN / 128 111 WDTCLKIN / 256 Functional Description The watchdog timer count can be enabled by WDTEN (WDT.CON[4]) to 1. As the watchdog timer is enabled, the down counter will start counting from the Load Value. If WDTRE (WDT.CON[6]) is set to 1, WDT reset will be asserted when the WDT counter value reaches 0 (underflow event) from the WDTLR value. Before the WDT counter goes down to 0, the software can write a certain value to the WDTLR register to reload the WDT counter. PS034504-0617 PRELIMINARY 104 Z32F1281 Product Specification Watch-Dog Timer Timing Diagram Figure 10.2. Timing Diagram in Interrupt Mode Operation when WDT clock is External Clock In WDT interrupt mode, after WDT underflow occurs, a certain count value is reloaded to prevent the next WDT interrupt in a short time period. This reloading action is only activated when the watchdog timer counter is set to Interrupt mode (set WDTIE of WDT.CON). It takes up to 5 cycles to go from the Load value to the CNT value. The WDT interrupt signal and CNT value data may be delayed by a maximum of 2 system bus clocks in synchronous logic. Prescale Table The WDT includes a 32-bit down counter with programmable pre-scaler to define different time-out intervals. The clock sources of the watchdog timer can be the peripheral clock (PCLK) or one of 5 external clock sources. The external clock source can be enabled by CKSEL (WDT.CON[3]) set to ‘1’. The external clock source was chosen in the MCCR3 register of the SCU block. To make the WDT counter base clock, users can control the 3-bit pre-scaler WPRS [2:0] in the WDT.CON register and the maximum pre-scaled value is “clock source frequency/256”. The pre-scaled WDT counter clock frequency values are listed in Table 10.2. Selectable clock source (40 kHz ~ 16 MHz) and the time out interval when 1 count Time out period = {(Load Value) * (1/pre-scaled WDT counter clock frequency) + max 5T ext} + max 4Tclk *Time out period (time out period from load value to interrupt set ‘1’) Table 10.2. Pre-scaled WDT Counter Clock Frequency Clock source WDTCLKIN WDTCLKIN /4 WDTCLKIN /8 WDTCLKIN /16 WDTCLKIN /32 WDTCLKIN /64 WDTCLKIN /128 WDTCLKIN /256 Ring OSC 1Mhz 250khz 125khz 62.5khz 31.25khz 15.625khz 7.8125khz 3.90625khz MCLK MCLK (BUS CLK) MCLK/4 MCLK/8 MCLK/16 MCLK/32 MCLK/64 MCLK/128 MCLK/256 IOSC 20Mhz 5Mhz 2.5Mhz 1.25Mhz 625khz 312.5khz 156.25khz 78.125khz EOSC XTAL XTAL/4 XTAL/8 XTAL/16 XTAL/32 XTAL/64 XTAL/128 XTAL/256 PLL PLL PLL/4 PLL/8 PLL/16 PLL/32 PLL/64 PLL/128 PLL/256 PS034504-0617 PRELIMINARY 105 Z32F1281 Product Specification 16-Bit Timer 11. 16-Bit Timer Overview The timer block consists of 6 channels of 16-bit general-purpose timers. They can support periodic timer, PWM pulse, one-shot timer, and capture mode. Features include:       16-bit up-counter Periodic timer mode One-shot timer mode PWM pulse mode Capture mode 10-bit prescaler Figure 11.1 shows a block diagram of the 16-bit timer. TIMERn PCLK TIMER EXT CLK TnI 1/2 000 1/4 001 1/16 010 1/64 011 TnADTRG Output Generator TnO TMCLK 1/N 16-bit Counter Count up Clear TnCR1.ADCTRGEN TnCR1.STARTLVL Tn.PRS 10X 11X TnCR1.CKSEL OTHER TIMER START TnINT Comparator 0 Comparator 1 Data0 buffer Data1 buffer TnCR1.OUTPOL TnCR1.CSYNC TnCR1.SSYNC SYNC CLEAR OUT Tn.GRB Tn.GRA TnCR2.TEN OTHER TIMER CLEAR TnCR1.CSYNC Figure 11.1. 16-bit Timer Block Diagram PS034504-0617 PRELIMINARY 106 Z32F1281 Product Specification 16-Bit Timer Pin Description Table 11.1. External Pin PS034504-0617 PIN NAME TYPE DESCRIPTION TnC I External clock / capture input TnO O Timer output PRELIMINARY 107 Z32F1281 Product Specification 16-Bit Timer Registers The base address of the Timer is 0x4000_3000 and the register map is described in Table 11.2 and Table 11.3. Table 11.2. Base Address of Each Channel CHANNEL Address T0 0x4000_3000 T1 0x4000_3020 T2 0x4000_3040 T3 0x4000_3060 T8 0x4000_3100 T9 0x4000_3120 Table 11.3. Timer Register Map Name Offset R/W Description Reset TnCR1 0x--00 R/W Timer control register 1 0x00000000 TnCR2 0x--04 R/W Timer control register 2 0x00000000 TnPRS 0x--08 R/W Timer prescaler register 0x00000000 TnGRA 0x--0C R/W Timer general data register A 0x00000000 TnGRB 0x--10 R/W Timer general data register B 0x00000000 TnCNT 0x--14 R/W Timer counter register 0x00000000 TnSR 0x--18 R/W Timer status register 0x00000000 TnIER 0x--1C R/W Timer interrupt enable register 0x00000000 TGECR 0x0140 R/W Timer Group Encoder Control Register 0x00000000 PS034504-0617 PRELIMINARY 108 Z32F1281 Product Specification 16-Bit Timer TnCR1 Timer n Control Register 1 Timer Control Register 1 is a 16-bit register. The Timer module should be configured properly before running. When the target purpose is defined, the timer can be configured in the TnCR1 register. 15 14 13 12 11 10 9 8 ADCTRGEN STARTLV CKSEL CLRMOD MODE T0CR1=0x4000_3000, T1CR1=0x4000_3020 T2CR1=0x4000_3040, T3CR1=0x4000_3060 T8CR1=0x4000_3100, T9CR1=0x4000_3120 0 0 0 0 0 0 0 0 0 000 00 00 RW RW RW RW RW PS034504-0617 8 ADCTRGEN 7 STARTLVL 6 4 CKSEL[2:0] 3 2 CLRMOD 1 0 MODE[1:0] 7 6 5 4 3 2 1 0 ADC Trigger source enable 0 Timer does not trigger ADC 1 Timer triggers ADC Interval/PWM/One-shot mode initial output value 0 Output starts with ‘L’ 1 Output starts with ‘H’ Counter clock source select 000 PCLK/2 001 PCLK/4 010 PCLK/16 011 PCLK/64 10X TEXT0 (in MCCR3) 11X TnC pin input Clear select when capture mode 00 Rising edge clear mode 01 Falling edge clear mode 10 Both edge clear mode 11 None clear mode Timer operation mode control 00 Normal periodic operation mode 01 PWM mode 10 One shot mode 11 Capture mode PRELIMINARY 109 Z32F1281 Product Specification TnCR2 16-Bit Timer Timer n Control Register 2 Timer Control Register 2 is an 8-bit register. T0CR2=0x4000_3004, T1CR2=0x4000_3024 T2CR2=0x4000_3044, T3CR2=0x4000_3064 T8CR2=0x4000_3104, T9CR2=0x4000_3124 7 6 5 4 3 2 1 0 TCLR TEN 0 0 0 0 0 0 0 0 R R R R R R WO RW TnPRS 1 TCLR 0 TEN Timer Count register clear 0 No 1 Initialize timer. If set to ‘1’, count register will be cleared. This is write-only. Timer enable bit 0 Disable timer 1 Enable timer Timer n Prescaler Register Timer Prescaler Register sets the pre-scale of the input clock for the timer counter. T0PRS=0x4000_3008, T1PRS=0x4000_3028 T2PRS =0x4000_3048, T3PRS=0x4000_3068 T8PRS=0x4000_3108, T9PRS=0x4000_3128 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRS 0 0 0 0 0 0 000 RW 9 0 PRS Pre-scale value of count clock TCLK = CLOCK_IN/(PRS+1) (CLOCK_IN is a selected timer input clock in TnCR1[CKSEL]) PS034504-0617 PRELIMINARY 110 Z32F1281 Product Specification TnGRA 16-Bit Timer Timer n General Register A Timer General Register A is a 16-bit register. T0GRA=0x4000_300C, T1GRA=0x4000_302C T2GRA =0x4000_304C, T3GRA=0x4000_306C T8GRA=0x4000_310C, T9GRA=0x4000_312C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GRA 0x0000 RW 15 0 PS034504-0617 GRA Timer n General Register A Periodic mode - Period value of time internal. - When the counter value is matched with this value, GRA Match interrupt is requested PWM mode - Duty value of PWM Output - When the counter value is matched with this value, GRA Match interrupt is requested One-shot mode - One-shot delay timing before output pulse. - When the counter value is matched with this value, GRA Match interrupt is requested Capture mode - Falling edge of TnC port will capture the count value when rising edge clear mode - Rising edge of TnC port will capture the count value when falling edge clear mode PRELIMINARY 111 Z32F1281 Product Specification TnGRB 16-Bit Timer Timer n General Register B Timer General Register B is a 16-bit register. This register is used for the Timer in PWM modes. T0GRB=0x4000_3010, T1GRB=0x4000_3030 T2GRB=0x4000_3050, T3GRB=0x4000_3070 T8GRB=0x4000_3110, T9GRB=0x4000_3130 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GRB 0x0000 RW 15 0 TnCNT GRB Timer n General Register B Periodic mode - Not used. No interrupt generated. PWM mode - Time interval value of PWM carrier frequency. - When the counter value is matched with this value, GRB Match interrupt is requested only in PWM and one-shot modes. One-shot mode - One-shot pulse output stop timing value. - When the counter value is matched with this value, GRB Match interrupt is requested only in PWM and one-shot modes. Capture mode - Rising edge of TnC port will capture the count value when rising edge clear mode - Falling edge of TnC port will capture the count value when falling edge clear mode Timer n Count Register Timer Count Register is a 16-bit register. T0CNT=0x4000_3014, T1CNT=0x4000_3034 T2CNT=0x4000_3054, T3CNT=0x4000_3074 T8CNT=0x4000_3114, T9CNT=0x4000_3134 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 0x0000 RW 15 0 PS034504-0617 CNT Timer count value register R Read current timer count value W Set count value PRELIMINARY 112 Z32F1281 Product Specification 16-Bit Timer TnSR Timer n Status Register Timer Status Register is a 16-bit register. This register indicates the current status of the timer module. 12 11 10 QDIRCH QRF 0 0 0 0 0 0 0 0 RW RW RW 10 PS034504-0617 9 QDIR 9 QDIRCH 8 QRF 2 MFA 1 MFB 0 OVF 8 7 6 5 4 3 2 OVF 13 MFB 14 MFA 15 QDIR T0SR=0x4000_3018, T1SR=0x4000_3038 T2SR=0x4000_3058, T3SR=0x4000_3078 T8SR=0x4000_3118, T9SR=0x4000_3138 1 0 0 0 0 0 0 0 0 0 RW RW RW Current Direction 0 Phase A leading Phase B (clockwise) 1 Phase B leading Phase A (counterclockwise) Quadrature direction change 0 No direction change 1 Direction is changed. Write '1' to this bit for clear Quadrature revolution flag 0 No revolution flag 1 Revolution flag is detected. Write '1' to this bit for clear GRA Match flag 0 Not match with GRA 1 Match flag with GRA. Write '1' to this bit for clear GRB Match flag 0 Not match with GRB 1 Match flag with GRB. Write '1' to this bit for clear Counter overflow flag 0 No overflow event 1 Counter overflowed. Write '1' to this bit for clear PRELIMINARY 113 Z32F1281 Product Specification 16-Bit Timer TnIER Timer n Interrupt Enable Register The Timer Interrupt Enable Register is a 16-bit register. Each status flag of the timer block can issue the interrupt. To enable the interrupt, write 1 in the corresponding bit in the TnIER register. 12 11 10 9 QRIE 0 0 0 0 0 0 0 0 RW RW 9 QDIRCHIE 8 QRIE 2 MAIE 1 MBIE 0 OVIE 8 7 6 5 4 3 2 OVIE 13 MBIE 14 MAIE 15 QDIRCHIE T0IER=0x4000_301C, T1IER=0x4000_303C T2IER=0x4000_305C, T3IER=0x4000_307C T8IER=0x4000_311C, T9IER=0x4000_313C 1 0 0 0 0 0 0 0 0 0 RW RW RW Quadrature direction change interrupt enable 0 Disable direction change interrupt 1 Enable direction change interrupt Quadrature revolution interrupt enable 0 Disable revolution flag interrupt 1 Enable revolution flag interrupt GRA Match interrupt enable 0 Disable match register A interrupt 1 Enable match register A interrupt GRB Match interrupt enable 0 Disable match register B interrupt 1 Enable match register B interrupt Counter overflow interrupt enable 0 Disable counter overflow interrupt 1 Enable counter overflow interrupt Note: The QMOD in the TGECR register must be set before enabling the Quadrature interrupts. PS034504-0617 PRELIMINARY 114 Z32F1281 Product Specification TGECR 16-Bit Timer Timer Group Encoder Control Register The Timer Group Encoder Control Register is a 16-bit register. Timer0, Timer1, Timer2, and Timer3 can be used for quadrature encoder interface function. 14 13 12 11 PDIRCON BDIRCON ADIRCON QDPHBEG QDPHAEG QDPHZEG QDPHSWAP 0 0 0 0 0 0 0 0 00 00 0 0 RW RW RW RW RW RW RW RW PS034504-0617 10 9 11 RDIRCON 10 PDIRCON 9 BDIRCON 8 ADIRCON 7 6 QDPHBEG[1:0] 5 4 QDPHAEG[1:0] 3 QDPHZEG 2 QDPHSWAP 0 QDMOD 8 7 6 5 4 3 2 1 0 0 0 QDMOD 15 RDIRCON TGECR=0x4000_3140 RW Revolution counter direction control 0 DIR status not affect to the counter 1 DIR status will change count direction Position counter direction control 0 DIR status not affect to the counter 1 DIR status will change count direction Phase B counter direction control 0 DIR status not affect to the counter 1 DIR status will change count direction Phase A counter direction control 0 DIR status not affect to the counter 1 DIR status will change count direction Quadrature mode phase B count for position count 00 Rising edge count 01 Falling edge count 1X Both edge count Quadrature mode phase A count for position count 00 Rising edge count 01 Falling edge count 1X Both edge count Quadrature mode phase Z count for revolution 0 PHZ rising edge count 1 PHZ falling edge count Quadrature input swap 0 No swap 1 Swap PHA and PHB Quadrature decoder mode 0 Normal timer mode 1 Quadrature decoder count mode Timer0 is phase A counter Timer1 is phase B counter Timer2 is position counter Timer3 is revolution counter PRELIMINARY 115 Z32F1281 Product Specification 16-Bit Timer Functional Description Basic Operation of Timer In Figure 11.2, TMCLK is a reference clock for operation of the timer. Divide this clock by the prescaler setting to operate the counting clock. The following images show the starting point of the counter and the ending of the period point of the counter in normal periodic mode. (a) Timer initialization is done by TCLR command and timer will be started by TEN command Match A time Counter reset Next Period start PCLK TMCLK Tn.CR1.CKSEL = 000 Prescale counter Tn.PRS = 02 02 00 01 02 00 01 02 00 01 02 00 01 02 Count enable Counter Data 1 buffer Tn.GRA = 100 FD FE FF 00 01 100 MFA Interrupt (b) Timer end operation Figure 11.2. Basic Start and Match Operation The timer count period can be calculated as follows: The period = TMCLK Period * Tn.GRA value Match A interrupt time = TMCLK Period * Tn.GRA value When you change the timer setting and restart the timer with the new setting, Zilog recommends that you write the CR2.TCLR command before the CR2.TEN command. PS034504-0617 PRELIMINARY 116 Z32F1281 Product Specification 16-Bit Timer Normal Periodic Mode Figure 11.3 shows the timing diagram in normal periodic mode. The Tn.GRA value decides the timer period. The Tn.GRM register value does not matter. Figure 11.3. Normal Periodic Mode Operation The timer count period can be calculated as follows: The period = TMCLK Period * Tn.GRA value Match A interrupt time = TMCLK Period * Tn.GRA value If Tn.GRA = 0, the timer cannot be started even if TnCR2.TEN is “1” because the period is “0”. The values in Tn.GRA and Tn.GRB are loaded into the internal compare data buffer 0 when the loading condition occurs. In this periodic mode, the Tn.CR2.TCLR write operation and the GRA match event will load the compare data buffers. One Shot Mode Figure 11.4 shows the timing diagram in one shot mode. The Tn.GRB value decides the one shot period. An additional comparison point is provided with the Tn.GRA register value. PS034504-0617 PRELIMINARY 117 Z32F1281 Product Specification 16-Bit Timer Figure 11.4. One Shot Mode Operation The one shot count period can be calculated as follows: The period = TMCLK Period * Tn.GRB value Match A interrupt time = TMCLK Period * Tn.GRA value If Tn.GRB = 0, the timer cannot be started even if TnCR2.TEN is “1” because the period is “0”. The values in Tn.GRA and Tn.GRB are loaded into the internal compare data buffers 0 and 1 when the loading condition occurs. In this mode, the Tn.CR2.TCLR write operation and the GRB match event will load the data buffer. The TnIO output signal format is the same as PWM mode. The Tn.GRB value defines the output pulse period and the Tn.GRA value defines the pulse width of one shot pulse. PWM Timer Output Examples Figure 11.5 shows the timing diagram of PWM output mode. The Tn.GRB value decides the PWM pulse period. An additional comparison point is provided with the Tn.GRA register value which defines the pulse width of PWM output. PS034504-0617 PRELIMINARY 118 Z32F1281 Product Specification 16-Bit Timer Figure 11.5. PWM Output Operation The PWM pulse period can be calculated as follows: The period = TMCLK Period * Tn.GRB value Match A interrupt time = TMCLK Period * Tn.GRA value If Tn.GRB = 0, the timer cannot be started even if TnCR2.TEN is “1” because the period is “0”. The values in Tn.GRA and Tn.GRB are loaded into the internal compare data buffers 0 and 1 when the loading condition occurs. In this mode, the Tn.CR2.TCLR write operation and the GRB match event will load the data buffer. The TnIO output signal generates a PWM pulse. The Tn.GRB value defines the output pulse period and the Tn.GRA value defines the pulse width of one shot pulse. The active level of PWM pulse can be controlled by the Tn.CR1.STARTLVL bit value. ADC Trigger generation is available at Match A interrupt time. Capture Mode Figure 11.6 shows the timing diagram in capture mode operation. The TnIO input signal is used for the capture pulse. Both rising and falling edges can capture the counter values in each capture condition. PS034504-0617 PRELIMINARY 119 Z32F1281 Product Specification 16-Bit Timer Figure 11.6. Capture Mode Operation A 5 PCLK clock cycle is required internally. Therefore, the actual capture point is after the 5 PCLK clock cycle from the rising or falling edge of the TnIO input signal. The internal counter can be cleared in multiple modes. The TnCR1.CLRMD field controls the counter clear mode. Rising edge clear mode, falling edge clear mode, both edge clear mode and none clear mode are supported. ADC Trigger Function The timer module can generate ADC start trigger signals. One timer can be one trigger source of the ADC block. Trigger source control is performed by the ADC control register. Figure 11.7 shows the ADC trigger function. The conversion rate must be shorter than the timer period; else an overrun situation can occur. ADC acknowledge is not required because the trigger signal is cleared automatically after 3 PCLK clock pulses. PS034504-0617 PRELIMINARY 120 Z32F1281 Product Specification 16-Bit Timer Figure 11.7. ADC Trigger Function Timing Diagram Setup Example: Using the 16-bit Timer0 for Continuous Mode Operation 1. Enable the Timer0 peripheral by writing the appropriate value to the Peripheral Enable Register (PER1). 2. Enable the Timer0 peripheral clock by writing the appropriate value to the Peripheral Clock Enable Register (PCER). 3. Stop Timer0 before modifying the Timer0 registers by resetting bit0 in the Timer Control Register2 (TnCR2). 4. In Timer Control Register1 (TnCR1), write the appropriate value to enable the Timer0 Normal Period Operation Mode (e.g. 0x0000). 5. Write the appropriate Timer prescalar value to the Timer Prescalar Register (TnPRS). 6. Write the appropriate Timer count match value to the Timer General Register A (TnGRA) register. This timer count match value is compared to the actual count value in the Timer Count Register (TnCNT). 7. Write the appropriate value to Timer Interrupt Enable Register (TnIER) to enable or disable the Timer interrupt. 8. Start the Timer by setting bit0 and bit1; Timer Control Register2 (TnCR2) is enabled and initialized. Note: Timer General Register A (TnGRA) is used for normal Timer operations. Timer General Register B (TnGRB) is used for Timer PWM modes. PS034504-0617 PRELIMINARY 121 Z32F1281 Product Specification 16-Bit Timer Quadrature Encoder Interface To use the Quadrature Encoder Interface Mode, Timer 0–Timer 3 are used for the input signals, holding the counter information and issuing the interrupts as necessary. The Timer mode for each of the timers used must be Capture Mode (TnCR1.MODE). The Quadrature Encoder Interface peripheral receives pulses from the input of Timer 0 (Phase A), Timer 1 (Phase B) and Timer 2 (Phase Z) and processes the information to determine position, direction, and optionally, speed. The input for Timer 3 is not used. The position and revolution counters both use the Timer 2 input (as the Phase Z, or Index input). Figure 11.8. Quadrature Encoder Interface Counter Block PS034504-0617 PRELIMINARY 122 Z32F1281 Product Specification 16-Bit Timer Figure 11.9. Quadrature Encoder Interface Input Block PS034504-0617 PRELIMINARY 123 Z32F1281 Product Specification 16-Bit Timer Figure 11.10. Quadrature Encoder Interface Block The Phase A and Phase B inputs are controlled by the timer clock configuration (TnCR1.CKSEL). The GRA register contains the pulse count from the latest pulse and GRB register contains the previous pulse count. When the MFx interrupt is received, the MFx register has been updated. Depending on how TnCR1.CLRMOD and TnCR1.CKSEL are configured, this value could either be the pulse count or the time between pulses (up to the 16-bit count). Phase A and Phase B can generate interrupts for QRF (Pulse received), QDIRCH (Direction changed). The QDIR status bit is set or cleared depending on the direction calculated from the last set of pulses from Phase A compared to Phase B. Timer 2 (Position counter) counts the pulses from Phase A and Phase B. The GRB register contains the number of Phase A + Phase B pulses for each Phase Z input received. The CNT register is the current Phase A + Phase B pulses (giving the position within the Phase Z revolutions). Timer 3 (Revolution counter) counts the pulses from the Phase Z input. Timer 3 only generates the QRF interrupt on receiving the Phase Z pulse. To enable the Quadrature Encoder Interface interrupts, TGECR.QDMOD must be set before the desired interrupts in the TnIER register can be set. PS034504-0617 PRELIMINARY 124 Z32F1281 Product Specification Universal Asynchronous Receiver/Transmitter 12. Universal Asynchronous Receiver/Transmitter Overview 4-Channel Universal Asynchronous Receiver/Transmitter (UART) modules are provided. Dedicated DMA support exists to transfer data between the memory buffer and the Transmit or Receive buffer of the UART block. The UART operation status, including error status, can be read from the status register. The prescaler which generates the correct baud rate, exists for each UART channel. The prescaler can divide the UART clock source, PCLK/2, from 1 to 65535. The baud rate is generated by the clock which is internally divided by 16 of the prescaled clock and 8-bit precision clock tuning function. A programmable interrupt generation function helps control communication via the UART channel. Features of the UART include:              Compatible with 16450 Supports DMA transfer Standard asynchronous control bit (start, stop, and parity) configurable Programmable 16-bit fractional baud generator Programmable serial communication 5-, 6-, 7,- or 8- bit data transfer Even, odd, or no-parity bit insertion and detection 1-, 1.5,- or 2-stop bit-insertion and detection 16-bit baud rate generation with 8-bit fraction control Hardware inter-frame delay function Stop bit error detection Detail status register Loop-back control Figure 12.1 shows a block diagram of the UART. PS034504-0617 PRELIMINARY 125 Z32F1281 Product Specification Universal Asynchronous Receiver/Transmitter SELECT RECEIVER BUFFER RECEIVER SHIFT REGISTER RECEIVER BUFFER REGISTER LINE CONTROL REGISTER DATA[7:0] RxD RECEIVER TIMING & CONTROL ADDR[4:2] BDR PWRITE PENABLE PCLK APB I/F & CONTROL LOGIC BAUD GENERATOR BFR (Fration) TRNASMITTER TIMING & CONTROL LINE STATUS REGISTER TRANSMITTER BUFFER nRESET SELECT PSEL TRANSMITTER HOLDING REGISTER INTERRUPT ENABLE REGISTER INTERRUPT CONTROL LOGIC TRANSMITTER SHIFTER REGISTER TxD INTERRUPT INTERRUPT ID REGISTER Figure 12.1. UART Block Diagram PS034504-0617 PRELIMINARY 126 Z32F1281 Product Specification Universal Asynchronous Receiver/Transmitter Pin Description Table 12.1. External Signal PIN NAME TYPE DESCRIPTION TXD0 O UART Channel 0 transmit output RXD0 I UART Channel 0 receive input TXD1 O UART Channel 1 transmit output RXD1 I UART Channel 1 receive input TXD2 O UART Channel 2 transmit output RXD2 I UART Channel 2 receive input TXD3 O UART Channel 3 transmit output RXD3 I UART Channel 3 receive input Registers The base address of UART is 0x4000_8000 and the register map is described in Table 12.2 and Table 12.3. Table 12.2. Base Address of Each Port UART Channel Address UART 0 0x4000_8000 UART 1 0x4000_8100 UART 2 0x4000_8200 UART 3 0x4000_8300 Table 12.3. UART Register Map PS034504-0617 Name Offset R/W Description UnRBR 0x00 R Receive data buffer register 0x00 UnTHR 0x00 W Transmit data hold register 0x00 UnIER 0x04 R/W Interrupt enable register 0x00 UnIIR 0x08 R Interrupt ID register 0x01 UnLCR 0x0C R/W Line control register 0x00 UnDCR 0x10 R/W Data Control Register 0x00 UnLSR 0x14 R UnBDR 0x20 R/W Baud rate Divisor Latch Register UnBFR 0x24 R/W Baud rate Fractional Counter Value 0x00 UnIDTR 0x30 R/W Inter-frame Delay Time Register 0x00 Line status register PRELIMINARY Reset 0x60 0x0000 127 Z32F1281 Product Specification UnRBR Universal Asynchronous Receiver/Transmitter Receive Buffer Register The UART Receive Buffer Register is an 8-bit read-only register. U0RBR=0x4000_8000, U1RBR=0x4000_8100 U2RBR=0x4000_8200, U3RBR=0x4000_8300 7 6 5 4 3 2 1 0 RBR RO 7 0 PS034504-0617 RBR Receive Buffer Register PRELIMINARY 128 Z32F1281 Product Specification UnTHR Universal Asynchronous Receiver/Transmitter Transmit Data Hold Register The UART Transmit Data Hold Register is an 8-bit write-only register. U0THR=0x4000_8000, U1THR=0x4000_8100 U2THR=0x4000_8200, U3THR=0x4000_8300 7 6 5 4 3 2 1 0 THR WO 7 0 UnIER THR Transmit Data Hold Register UART Interrupt Enable Register The UART Interrupt Enable Register is an 8-bit register. U0IER=0x4000_8004, U1IER=0x4000_8104 U2IER=0x4000_8204, U3IER=0x4000_8304 7 6 5 4 3 2 1 0 - - DTXIEN DRXIEN - RLSIE THREIE DRIE 0 0 0 0 0 0 0 0 RW RW RW RW RW PS034504-0617 5 DTXIEN 4 DRXIEN 2 RLSIE 1 THREIE 0 DRIE DMA transmit done interrupt enable 0 DMA transmit done interrupt is disabled 1 DMA transmit done interrupt is enabled DMA receive done interrupt enable 0 DMA receive done interrupt is disabled 1 DMA receive done interrupt is enabled Receiver line status interrupt enable 0 Receive line status interrupt is disabled 1 Receive line status interrupt is enabled Transmit holding register empty interrupt enable 0 Transmit holding register empty interrupt is disabled 1 Transmit holding register empty interrupt is enabled Data receive interrupt enable 0 Data receive interrupt is disabled 1 Data receive interrupt is enabled PRELIMINARY 129 Z32F1281 Product Specification UnIIR Universal Asynchronous Receiver/Transmitter UART Interrupt ID Register The UART Interrupt ID Register is an 8-bit register. U0IIR=0x4000_8008, U1IIR=0x4000_8108 U2IIR=0x4000_8208, U3IIR=0x4000_8308 7 6 0 5 0 4 0 3 1 0 3 0 IID 2 1 0 IID IPEN 000 0 R R Interrupt source ID See interrupt source ID table Interrupt pending bit 0 Interrupt is pending 1 No interrupt is pending. IPEN UART supports 3-priority interrupt generation. The interrupt source ID register shows one interrupt source which has the highest priority among pending interrupts. The priority is defined as:     Receive line status interrupt Receive data ready interrupt Transmit hold register empty interrupt Tx/Rx DMA complete interrupts Table 12.4. Interrupt ID and Control DMA IID IPEN Interrupt sources Priority Bit 3 Bit 2 Bit 1 Bit 0 - 0 0 0 1 None - - Highest 1 0 1 1 0 Receiver Line Status Overrun, Parity, Framing or Break Error Read LSR register 2 0 1 0 0 Receiver Data Available Receive data is available. Read receive register or read IIR register 3 0 0 1 0 Transmitter Holding Register Empty Transmit buffer empty Write transmit hold register or read IIR register 4 1 1 0 0 Rx DMA done Rx DMA completed. Read IIR register 5 1 0 1 0 Tx DMA done Tx DMA completed. Read IIR register PS034504-0617 Interrupt Interrupt condition PRELIMINARY Interrupt clear 130 Z32F1281 Product Specification UnLCR Universal Asynchronous Receiver/Transmitter UART Line Control Register The UART Line Control Register is an 8-bit register. U0LCR=0x4000_800C, U1LCR=0x4000_810C U2LCR=0x4000_820C, U3LCR=0x4000_830C 7 0 6 5 4 3 2 BREAK STICKP PARITY PEN STOPBIT 0 0 0 0 0 0 0 RW RW RW RW RW RW RW 6 BREAK 5 STICKP 4 PARITY 3 PEN 2 STOPBIT 1 0 DLEN 1 0 DLEN When this bit is set, TxD pin will be driven at low state in order to notice the alert to the receiver. 0 Normal transfer mode 1 Break transmit mode Force parity and it will be effective when PEN bit is set. See Table9.5 0 Parity stuck is disabled 1 Parity stuck is enabled Parity mode selection bit and stuck parity select bit 0 Odd parity mode 1 Even parity mode Parity bit transfer enable 0 The parity bit disabled 1 The parity bit enabled The number of stop bit followed by data bits. 0 1 stop bit 1 1.5 / 2 stop bit In case of 5 bit data case, 1.5 stop bit is added. In case of 6,7 or 8 bit data, 2 stop bit is added The data length in one transfer word. 00 5 bit data 01 6 bit data 10 7 bit data 11 8 bit data The parity bit is generated according to bits 3,4,5 of the UnLCR register. Table 12.5 shows the variation of parity bit generation. Table 12.5. Variation of Parity Bit Generation PS034504-0617 STICKP PARITY PEN Parity X X 0 No Parity 0 0 1 Odd Parity 0 1 1 Even Parity 1 0 1 Force parity as “1” 1 1 1 Force parity as “0” PRELIMINARY 131 Z32F1281 Product Specification UnDCR Universal Asynchronous Receiver/Transmitter UART Data Control Register The UART Data Control Register is an 8-bit register. U0DCR=0x4000_8010, U1DCR=0x4000_8110 U2DCR=0x4000_8210, U3DCR=0x4000_8310 7 0 PS034504-0617 6 5 0 0 4 LBON 3 RXINV 2 TXINV 4 3 2 LBON RXINV TXINV 0 0 0 RW RW RW 1 0 0 0 Local loopback test mode enable 0 Normal mode 1 Local loopback mode (TxD connected to RxD internally) Rx Data Inversion Selection 0 Normal RxData Input 1 Inverted RxData Input Tx Data Inversion Selection 0 Normal TxData Output 1 Inverted TxData Output PRELIMINARY 132 Z32F1281 Product Specification UnLSR Universal Asynchronous Receiver/Transmitter UART Line Status Register The UART Line Status Register is an 8-bit register. U0LSR=0x4000_8014, U1LSR=0x4000_8114 U2LSR=0x4000_8214, U3LSR=0x4000_8314 7 6 5 4 3 2 1 0 - TEMT THRE BI FE PE OE DR 0 1 1 0 0 0 0 0 R R R R R R R 6 TEMT 5 THRE 4 BI 3 FE 2 PE 1 OE 0 DR Transmit empty. 0 Transmit register has the data is now transferring 1 Transmit register is empty. Transmit holding empty. 0 Transmit holding register is not empty. 1 Transmit holding register empty Break condition indication bit 0 Normal status 1 Break condition is detected Frame Error. 0 No framing error. 1 Framing error. The receive character did not have a valid stop bit Parity Error 0 No parity error 1 Parity error. The receive character does not have correct parity information. Overrun error 0 No overrun error 1 Overrun error. Additional data arrives while the RHR is full Data received 0 No data in receive holding register. 1 Data has been received and is saved in the receive holding register This register provides the status of data transfers between the transmitter and the receiver. Users can get the line status information from this register to handle the next process. Bits 1,2,3,4 will raise the line status interrupt when the RLSIE bit in UnIEN register is set. Other bits can generate its interrupt when its interrupt enable bit in the UnIEN register is set. PS034504-0617 PRELIMINARY 133 Z32F1281 Product Specification UnBDR Universal Asynchronous Receiver/Transmitter Baud rate Divisor Latch Register The UART Baud rate Divisor Latch Register is a 16-bit register. U0BDR=0x4000_8020, U1BDR=0x4000_8120 U2BDR=0x4000_8220, U3BDR=0x4000_8320 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BDR 0x0000 RW 15 0 BDR Baud rate Divider latch value To establish communication with the UART channel, the baud rate should be set properly. The programmable baud rate generator UnBDR provides the 16-bit dividers values. The 16 bit divider register (UnBDR) should be written for the expected baud rate. The baud rate calculation formula is: BDR = 𝑃𝐶𝐿𝐾 / 2 16 × 𝐵𝑎𝑢𝑑𝑅𝑎𝑡𝑒 For a speed of 72 MHz PCLK, the divider value and error rate is described in Table 12.6. Table 12.6. Example of Baud Rate Calculation PCLK=72 MHz PS034504-0617 Baud rate Divider (BDR) Error (%) 1200 1875 0.00% 2400 937 0.05% 4800 468 0.16% 9600 234 0.16% 19200 117 0.16% 38400 58 1.02% 57600 39 0.16% 115200 19 2.79% PRELIMINARY 134 Z32F1281 Product Specification UnBFR Universal Asynchronous Receiver/Transmitter Baud Rate Fraction Counter Register The Baud Rate Fraction Counter Register is an 8-bit register. U0BFR=0x4000_8024, U1BFR=0x4000_8124 U2BFR=0x4000_8224, U3BFR=0x4000_8324 7 6 5 4 3 2 1 0 BFR 0x00 RW 7 0 BFR Fractions counter value. 0 Fraction counter is disabled N Fraction counter enabled. Fraction compensation mode is operating. Fraction counter is incremented by FCNT. Table 12.7. Example of Baud Rate Calculation with BFR PCLK=72 MHz Baud rate Divider (BDR) FCNT (BFR) Error (%) 1200 1875 0 0.0% 2400 937 128 0.0% 4800 468 192 0.0% 9600 234 96 0.0% 19200 117 48 0.0% 38400 58 152 0.0% 57600 39 16 0.0% 115200 19 136 0.0% FCNT = Float ∗ 256 The 8-bit fractional counter counts up by FCNT value every (baud rate)/16 period and whenever the fractional counter overflows, the divisor value increments by 1. Therefore, this period will be compensated. In the next period, the divisor value returns to the original set value. For example, if 9600 bps, 𝑃𝐶𝐿𝐾 / 2 72000000 / 2 = = 234.375 𝐷𝑖𝑣𝑖𝑑𝑒𝑟 = 234, 𝐹𝑙𝑜𝑎𝑡 = 0.375 16 × 𝐵𝑎𝑢𝑑𝑅𝑎𝑡𝑒 16 × 9600 FCNT = Float ∗ 256 = 0.375 ∗ 256 = 96 BDR = 234, BFR = 96 PS034504-0617 PRELIMINARY 135 Z32F1281 Product Specification UnIDTR Universal Asynchronous Receiver/Transmitter Inter-frame Delay Time Register The UART Inter-frame Time Register is an 8-bit register. A dummy delay can be inserted between 2 continuous transmits. U0IDTR=0x4000_8030, U1IDTR=0x4000_8130 U2IDTR=0x4000_8230, U3IDTR=0x4000_8330 7 6 5 4 3 2 0 0 1 0 WAITVAL 0 0 0 000 RW 2 0 WAITVAL Wait time is decided by this value [unit: 1 bit time] Wait Time = 𝑊𝐴𝐼𝑇𝑉𝐴𝐿 𝐵𝐴𝑈𝐷𝑅𝐴𝑇𝐸 Functional Description The PER2 and PCER2 registers must be configured to enable the UART peripheral and UART peripheral clock. The UART module is compatible with 16450 UART. Additionally, dedicated DMA channels and fractional baud rate compensation logic are provided. Because there is no internal FIFO block, data transfers are established interactively or by using DMA support. The DMA operation is described here. 2 DMA channels are provided for each UART module – TX transfer and RX transfer. Each channel has a 32bit memory address register and a 16-bit transfer counter register. Prior to the DMA operation, the DMA Memory Address register and the Transfer Count register should be configured. For the RX operation, the memory address will be the destination memory address and for the TX operation, the memory address will be the source memory address. The transfer counter register will store the number of transfer data. When a single transfer is done, the counter will be decremented by 1. When the counter reaches zero, the DMA done flag will be delivered to the UART control block. If the interrupt is enabled, this flag will generate the interrupt. Receiver Sampling Timing The UARTs operate per the following timing: If the falling edge is on the receive line, UART judges it as the start bit. From the start timing, the UART oversamples 16 times of 1-bit and detects the bit value at the 7th sample of 16 samples. PS034504-0617 PRELIMINARY 136 Z32F1281 Product Specification Universal Asynchronous Receiver/Transmitter START bit UnRX D STOP bit 0 Bit Samples Start bit 1 Bit 0 0 Bit 1 0 Bit 2 0 Bit 3 0 Bit 4 0 Bit 5 1 Bit 6 0 Bit 7 Stop bit UnRXD SubSample 0 1 2 3 4 5 6 7 8 1 11 12 13 14 1 5 0 Bit Sampling Position (7/16) 9 Figure 12.2. Sampling Timing of UART Receiver Note: Zilog recommends enabling of debounce settings in the PCU block to reinforce the immunity of external glitch noise. Transmitter The transmitter’s function is to transmit data. The start bit, data bits, optional parity bit, and stop bit are serially shifted, with the least significant bit first. The number of data bits is selected in the DLAN[1:0] field of the Un.LCR register. The parity bit is set according to the PARITY and PEN bit field of the Un.LCR register. If the parity type is even, it depends on the one bit sum of all data bits. For odd parity, the parity bit is the inverted sum of all data bits. The number of stop bits is selected in the STOPBIT field of the Un.LCR register. An example of transmit data format is shown in Figure 12.3. Figure 12.3. Transmit Data Format Example Inter-frame Delay Transmission The inter-frame delay function allows the transmitter to insert an idle state on the TXD line between two characters. The width of the idle state is defined in the WAITVAL field of the Un.IDTR register. When this field is set to 0, zero time-delay is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted character during the number of bit periods defined in the WATIVAL field. PS034504-0617 PRELIMINARY 137 Z32F1281 Product Specification Universal Asynchronous Receiver/Transmitter Figure 12.4. Transmit Data Format Example Transmit Interrupt The transmit operation generates interrupt flags. When the transmitter holding register is empty, the THRE interrupt flag is set. When the transmitter shifter register is empty, the TXE interrupt flag is set. Users can select the interrupt timing that is best for the application. Figure 12.5. Transmit Data Format Example DMA Transfers The UART supports the DMA interface function. It is optionally provided depending on the device. The start memory address for transfer data and the length of transfer data are programmed in the registers in the DMA block. The end of transfer is notified by the related transfer done flag. The transmit with DMA operation invokes the DMA TX done flag DTX.UnIIR and sets the DMA TX done interrupt ID when all the transmit data is written to the transmit holding register. Two transmit data values remain in the UART block registers after the DMA transfer done interrupt. The Receive with DMA operation invokes the DMA RX done flag RXT.UnIIR and sets the DMA RX done interrupt ID when all the receive data is written to the destination memory. Therefore, the UART RXD signal is already in Idle state when the DMA RX done interrupt is issued. PS034504-0617 PRELIMINARY 138 Z32F1281 Product Specification Serial Peripheral Interface 13. Serial Peripheral Interface Overview 2-channel serial interface is provided for synchronous serial communication with external peripherals. The SPI block supports master and slave modes. 4 signals are used for SPI communication – SS, SCK, MOSI, and MISO. Features include:        Master or slave operation Programmable clock polarity and phase 8,9,16,17-bit wide transmit/receive register 8,9,16,17-bit wide data frame Loop-back mode Programmable start, burst, and stop delay time DMA transfer operation. Figure 13.1 shows the SPI Block Diagram. PRESET TxSData[16:0] TxData[16:0] Tx Data PSEL Tx Shifter Register SS PENABLE PWRITE PADDR PWDATA[31:0] SCK Transmit/ Register Receive block MOSI MISO logic RxSData[16:0] RxData[16:0] R Rx Data PRDATA[31:0] xShifter Register PENABLE PENABLE DMA req ( Tx & Rx) Clock SPICLKDIV divider SSDET TRDY DMA en (Tx & Rx) DMA ack ( Tx & Rx) DMA done (Tx & Rx) RRDY Interrupt SPIIRQ generator DMA Tx/Rx done Interrupt Figure 13.1. SPI Block Diagram PS034504-0617 PRELIMINARY 139 Z32F1281 Product Specification Serial Peripheral Interface Pin Description Table 13.1. External Pins PIN NAME TYPE DESCRIPTION SS0 I/O SPI0 Slave select (Master output, Slave input) SCK0 I/O SPI0 Serial clock (Master output, Slave input) MOSI0 I/O SPI0 Serial data (Master output, Slave input) MISO0 I/O SPI0 Serial data (Master input, Slave output) SS1 I/O SPI1 Slave select (Master output, Slave input) SCK1 I/O SPI1 Serial clock (Master output, Slave input) MOSI1 I/O SPI1 Serial data (Master output, Slave input) MISO1 I/O SPI1 Serial data (Master input, Slave output) Registers The base address of SPI is 0x4000_9000 and the register map is described in Table 13.2 and Table 13.3. Table 13.2. SPI Base Address Channel Base address SPI0 0x4000_9000 SPI1 0x4000_9100 Table 13.3. SPI Register Map PS034504-0617 Name Offset R/W Description SPnTDR 0x--00 W SPI n Transmit Data Register - SPnRDR 0x--00 R SPI n Receive Data Register 0x000000 SPnCR 0x--04 R/W SPI n Control Register 0x001020 SPnSR 0x--08 R/W SPI n Status Register 0x000006 SPnBR 0x--0C R/W SPI n Baud rate Register 0x0000FF SPnEN 0x--10 R/W SPI n Enable register 0x000000 SPnLR 0x--14 R/W SPI n delay Length Register 0x010101 PRELIMINARY Reset 140 Z32F1281 Product Specification SPnCR Serial Peripheral Interface SPI n Control Register SPnCR is a 20-bit read/write register and can be set to configure the SPI operation mode. 1 0 0 0 0 20 TXBC 19 RXBC 18 TXDIE 17 RXDIE 16 SSCIE 15 TXIE 14 RXIE 13 SSMOD 12 SSOUT 11 LBE 10 SSMASK 9 SSMO 8 SSPOL 7 PS034504-0617 RW RW RW RW RW RW RW BITSZ 0 0 0 1 0 0 0 00 RW SSPOL 0 CPOL SSMO 0 CPHA SSMASK 0 RW LBE 0 RW SSOUT 0 5 MSBF SSMOD 0 6 RW RXIE 0 7 MS TXIE 0 RW 0 SSCIE 0 RW 0 TXDIE 0 RXDIE 0 RW 0 RW 0 RXBC 0 8 W 0 W 0 9 TXBC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RW SP0CR=0x4000_9004, SP1CR=0x4000_9104 4 3 2 1 0 Tx buffer clear bit. 0 No action 1 Clear Tx buffer Rx buffer clear bit 0 No action 1 Clear Rx buffer DMA Tx Done Interrupt Enable bit. 0 DMA Tx Done Interrupt is disabled. 1 DMA Tx Done Interrupt is enabled. DMA Rx Done Interrupt Enable bit. 0 DMA Rx Done Interrupt is disabled. 1 DMA Rx Done Interrupt is enabled. SS Edge Change Interrupt Enable bit. 0 nSS interrupt is disabled. 1 nSS interrupt is enabled for both edges (LH, HL) Transmit Interrupt Enable bit. 0 Transmit Interrupt is disabled. 1 Transmit Interrupt is enabled. Receive Interrupt Enable bit.. 0 Receive Interrupt is disabled. 1 Receive Interrupt is enabled. SS Auto/Manual output select bit in master mode. 0 SS output is not set by SSOUT (SPnCR[12]). SS signal is in normal operation mode. 1 SS output signal is set by SSOUT. SS output signal select bit in master mode. 0 SS output is ‘L.’ 1 SS output is ‘H’. Loop-back mode select bit in master mode. 0 Loop-back mode is disabled. 1 Loop-back mode is enabled. SS signal masking bit in slave mode. 0 SS signal masking is disabled. Receive data when SS signal is active. 1 SS signal masking is enabled. Receive data at SCLK edges. SS signal is ignored. SS output signal select bit. 0 SS output signal is disabled. 1 SS output signal is enabled. SS signal Polarity select bit. 0 SS signal is Active-Low. 1 SS signal is Active-High. Reserved PRELIMINARY 141 Z32F1281 Product Specification 6 5 MS 4 MSBF 3 CPHA 2 CPOL 1 BITSZ 0 Serial Peripheral Interface Master/Slave select bit. 0 SPI is in Slave mode. 1 SPI is in Master mode. MSB/LSB Transmit select bit. 0 LSB is transferred first. 1 MSB is transferred first. SPI Clock Phase bit. 0 Sampling of data occurs at odd edges (1,3,5,…,15). 1 Sampling of data occurs at even edges (2,4,6,…,16). SPI Clock Polarity bit. 0 Active-high clocks selected. 1 Active-low clocks selected. Transmit/Receive Data Bits select bit. 00 8 bits 01 9 bits 10 16 bits 11 17 bits CPOL=0, CPHA=0: data sampling at rising edge, data changing at falling edge CPOL=0, CPHA=1: data sampling at falling edge, data changing at rising edge CPOL=1, CPHA=0: data sampling at falling edge, data changing at rising edge CPOL=1, CPHA=1: data sampling at rising edge, data changing at falling edge PS034504-0617 PRELIMINARY 142 Z32F1281 Product Specification SPnSR Serial Peripheral Interface SPI n Status Register SPnSR is a 10-bit read/write register. It contains the status of the SPI interface. RXDMAF 0 0 0 0 0 0 0 0 RC1 RC1 PS034504-0617 9 TXDMAF 8 RXDMAF 7 6 SSDET 5 SSON 4 OVRF 3 UDRF 2 TXIDLE 1 TRDY 0 RRDY 8 7 6 RRDY 9 TRDY 10 TXIDLE 11 UDRF 12 OVRF 13 SSON 14 SSDET 15 TXDMAF SP0SR=0x4000_9008, SP1SR=0x4000_9108 5 4 3 2 1 0 0 0 0 0 0 1 1 0 RC1 RC1 RC1 RC1 R R R DMA Transmit Operation Complete flag. (DMA to SPI) 0 DMA Transmit Op is working or is disabled. 1 DMA Transmit Op is done. DMA Receive Operation Complete flag. (SPI to DMA ) 0 DMA Receive Operation is working or is disabled. 1 DMA Transmit Op is done. Reserved The rising or falling edge of SS signal Detect flag. 0 SS edge is not detected. 1 SS edge is detected. The bit is cleared when it is written as “0”. SS signal Status flag. 0 SS signal is inactive. 1 SS signal is active. Receive Overrun Error flag. 0 Receive Overrun error is not detected. 1 Receive Overrun error is detected. This bit is cleared by writing or reading SPnRDR. Transmit Underrun Error flag. 0 Transmit Underrun is not occurred. 1 Transmit Underrun is occurred. This bit is cleared by writing or reading SPnTDR. Transmit/Receive Operation flag. 0 SPI is transmitting data 1 SPI is in IDLE state. Transmit buffer Empty flag. 0 Transmit buffer is busy. 1 Transmit buffer is ready. This bit is cleared by writing data to SPnTDR. Receive buffer Ready flag. 0 Receive buffer has no data. 1 Receive buffer has data. This bit is cleared by reading data to SPnRDR. PRELIMINARY 143 Z32F1281 Product Specification SPnTDR Serial Peripheral Interface SPI n Transmit Data Register SPnTDR is a 17-bit read/write register. It contains serial transmit data. SP0TDR=0x4000_9000, SP1TDR=0x4000_9100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000 RW 16 0 TDR SPnRDR Transmit Data Register SPI n Receive Data Register SPnRDR is a 17-bit read/write register. It contains serial receive data. SP0RDR=0x4000_9000, SP1RDR=0x4000_9100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000 RW 16 0 SPnBR RDR Receive Data Register SPI n Baud Rate Register SPnBR is a 16-bit read/write register. Baud rate can be set by writing the register. SP0BR=0x4000_900C, SP1BR=0x4000_910C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BR 0x00FF RW 15 0 PS034504-0617 BR Baud rate setting bits Baud Rate = PCLK / (BR + 1). (BR must be bigger than “0”, BR >= 2 ) PRELIMINARY 144 Z32F1281 Product Specification SPnEN Serial Peripheral Interface SPI n Enable Register SPnEN is an 8-bit read/write register. It contains the SPI enable bit. SP0EN=0x4000_9010, SP1EN=0x4000_9110 7 6 5 4 3 2 1 0 ENABLE 0 0 0 0 0 0 0 0 RW 0 PS034504-0617 ENABLE SPI Enable bit 0 SPI is disabled. - SPnSR is initialized by writing “0” to this bit but other registers aren’t initialized. 1 SPI is enabled. - When this bit is written as “1”, the dummy data of transmit buffer will be shifted. To prevent this, write data to SPTDR before this bit is active. PRELIMINARY 145 Z32F1281 Product Specification SPnLR Serial Peripheral Interface SPI n Delay Length Register SPnLR is a 24-bit read/write register. It contains start, burst, and stop length value. SP0CR=0x4000_9014, SP1CR=0x4000_9114 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 0 0 0 0 0 0 23 16 15 8 7 0 SPL 7 6 5 4 3 BTL STL 0x01 0x01 0x01 RW RW RW 2 1 0 StoPLength value (SPL >= 1) BursTLength value 0x01 ~ 0xFF : 1 ~ 255 SCLKs. STL 8 SPL 0x01 ~ 0xFF : 1 ~ 255 SCLKs. BTL 9 (BTL >= 1) STart Length value 0x01 ~ 0xFF : 1 ~ 255 SCLKs. (STL >= 1) SS STL SPL SCLK BTL MISO MISO MISO MOSI MOSI MOSI Figure 13.2. SPI waveform (STL, BTL, and SPL) Functional Description The SPI Transmit and Receive blocks share the Clock Gen Block; however, they are independent of each other. The Transmit and Receive blocks have double buffers and SPI is available for back-to-back transfer operations. SPI Timing The SPI has four modes of operation. These modes essentially control the way data is clocked in or out of an SPI device. The configuration is done by two bits in the SPI Control Register (SPnCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock. The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats. To ensure proper communication PS034504-0617 PRELIMINARY 146 Z32F1281 Product Specification Serial Peripheral Interface between master and slave, both devices have to run in the same mode. This may require a reconfiguration of the master to match the requirements of different peripheral slaves. The clock polarity has no significant effect on the transfer format. Switching this bit causes the clock signal to be inverted (active high becomes active low and idle low becomes idle high). However, the settings of the clock phase select one of two different transfer timings, which are described in further detail in the next two chapters. Since the MOSI and MISO lines of the master and the slave are directly connected to each other, the diagrams show the timing of both these devices. The nSS line is the slave select input of the slave. The nSS pin of the master is not shown in the diagrams. It has to be inactivated by a high level on this pin (if configured as an input pin) or by configuring it as an output pin. The timing of an SPI transfer where CPHA is zero is shown in Figure 13.3 and Figure 13.4. Two wave forms are shown for the SCK signal - one for CPOL equals zero and another for CPOL equals one. When the SPI is configured as a slave, the transmission starts with the falling edge of the /SS line. This activates the SPI of the slave and the MSB of the byte stored in its data register (SPnTDR) is output on the MISO line. The actual transfer is started by a software write to the SPnTDR of the master. This causes the clock signal to be generated. If the CPHA equals zero, the SCLK signal remains zero for the first half of the first SCLK cycle. This ensures that the data is stable on the input lines of both the master and the slave. The data on the input lines is read with the edge of the SCLK line from its inactive to its active state. The edge of the SCLK line from its active to its inactive state (falling edge if CPOL equals zero and rising edge if CPOL equals one) causes the data to be shifted one bit further so that the next bit is output on the MOSI and MISO lines. SCK MOSI MISO D0 D0 D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 Figure 13.3. SPI Transfer Timing 1/4 (CPHA=0, CPOL=0, MSBF=0) PS034504-0617 PRELIMINARY 147 Z32F1281 Product Specification Serial Peripheral Interface SS SCK MOSI D7 D6 D5 D4 D3 D2 D1 D0 MISO D7 D6 D5 D4 D3 D2 D1 D0 Figure 13.4.SPI Transfer Timing 2/4 (CPHA=0, CPOL=1, MSBF=1) The timing of an SPI transfer where CPHA is one is shown in Figure 13.5 and Figure 13.6.Two wave forms are shown for the SCLK signal - one for CPOL equals zero and another for CPOL equals one. As in the previous scenarios, the falling edge of the nSS lines selects and activates the slave. However, in contrast to the previous cases, where CPHA equals zero, the transmission is not started and the MSB is not output by the slave at this stage. The actual transfer is started by a software write to the SPnTDR of the master which causes the clock signal to be generated. The first edge of the SCLK signal from its inactive to its active state (rising edge if CPOL equals zero and falling edge if CPOL equals one) causes both the master and the slave to output the MSB of the byte in the SPnTDR. As shown in Figure 13.3 and Figure 13.4, there is no delay of half a SCLK-cycle. The SCLK line changes its level immediately at the beginning of the first SCLK-cycle. The data on the input lines is read with the edge of the SCLK line from its active to its inactive state (falling edge if CPOL equals zero and rising edge if CPOL equals one). After eight clock pulses, the transmission is complete. SS SCK MOSI D0 D1 D2 D3 D4 D5 D6 D7 MISO D0 D1 D2 D3 D4 D5 D6 D7 Figure 13.5.SPI Transfer Timing 3/4 (CPHA=1, CPOL=0, MSBF=0) PS034504-0617 PRELIMINARY 148 Z32F1281 Product Specification Serial Peripheral Interface SS SCKSS MOSI D7 D6 D5 D4 D3 D2 D1 D0 MISO D7 D6 D5 D4 D3 D2 D1 D0 Figure 13.6.SPI Transfer Timing 4/4 (CPHA=1, CPOL=1, MSBF=1) PS034504-0617 PRELIMINARY 149 Z32F1281 Product Specification Serial Peripheral Interface DMA Handshake SPI supports the DMA handshaking operation. To operate a DMA handshake, DMA registers should be set first (see Chapter 9, Direct Memory Access Controller). SPI0 has 2 DMA channels – Channel 8 for the receiver and Channel 9 for the transmitter. SPI1 has Channel 10 for the receiver and Channel 11 for the transmitter. Because the transmitter and receiver are independent of each other, SPI can operate the two channels at the same time. After the DMA channel for receiver is enabled and the receive buffer is filled, SPI sends Rx request to DMA to empty the buffer and waits for an ACK signal from DMA. If the Receive buffer is filled again after the ACK signal, SPI sends an Rx request. If DMA Rx DONE becomes high, RXDMAF (SPnSR[8]) is 1 and an interrupt is serviced when RXDIE (SPnCR[17]) is set. Similarly, if the transmit buffer is empty after the DMA channel for transmitter is enabled, SPI sends a Tx request to the DMA to fill the buffer and waits for an ACK signal from the DMA. If the transmit buffer is empty again after the ACK signal, SPI sends a Tx request. If DMA Tx DONE becomes high, TXDMAF (SPnSR[9]) is 1 and an interrupt is serviced when TXDIE(SPnCR[18]) is set. The slave transmitter sends dummy data at the first transfer (8~17 SCLKs) in DMA handshake mode. Figure 13.7 shows a flowchart of the DMA handshaking process. DMA EN IDLE Rx or Tx Req (to DMA) DONE INT gen SPnSR[9] or [8] set DMA DONE DMA ACK WAIT Figure 13.7. DMA Handshake Flowchart PS034504-0617 PRELIMINARY 150 Z32F1281 Product Specification I²C Interface 14. I²C Interface Overview 2 2 The Inter-Integrated Circuit (I C) bus serves as an interface between the microcontroller and the serial I C bus. It provides two wires, a serial bus interface to a large number of popular devices and allows parallel-bus 2 systems to communicate bi-directionally with the I C-bus. Features include:         Master and slave operation Programmable communication speed Multi-master bus configuration 7-bit addressing mode Standard data rate of 100/400 kbps STOP signal generation and detection START signal generation ACK bit generation and detection 2 Figure 14.1 shows the I C block diagram. Slave Addr. Register (I2CSAR) Debounce Slave Addr. Register1 (I2CSAR1) enable SDAIN SDA Noise Canceller (debounce) 1 F/F 8-bit Shift Register (SHFTR) SDA Out Controller Data Out Register (I2CDR) SCL Out Controller SCL High Period Register (I2CSCLHR) SCL Low Period Register (I2CSCLLR) SDAHoldTimeRegister (I2CDAHR) 0 SDAOUT Debounce enable SCL Noise Canceller (debounce) SCLIN 1 0 I n t e r n a l B u s L i n e SCLOU T 2 Figure 14.1. I C Block Diagram PS034504-0617 PRELIMINARY 151 Z32F1281 Product Specification I²C Interface Pin Description 2 Table 14.1. I C Interface External Pins PIN NAME TYPE DESCRIPTION 2 SCL0 I/O I C channel 0 Serial clock bus line (open-drain) SDA0 I/O I C channel 0 Serial data bus line (open-drain) SCL1 I/O I C channel 1 Serial clock bus line (open-drain) SDA1 I/O I C channel 1 Serial data bus line (open-drain) 2 2 2 Registers 2 2 The base address of I C0 is 0x4000_A000 and the base address of I C1 is 0x4000_A100. The register map is described in Table 14.2 and Table 14.3. 2 Table 14.2.I C Interface Base Address Channel Base address 2 0x4000_A000 2 0x4000_A100 I C0 I C1 2 Table 14.3.I C Register Map Name Offset R/W IC0DR 0xA000 R/W IC0SR 0xA008 R, R/W IC0SAR 0xA00C R/W IC0CR R/W 0xFF 2 0x00 2 0x00 2 0x00 2 0xFFFF 2 0xFFFF 2 0x7FFF 2 0xFF 2 0x00 2 0x00 2 0x00 2 0xFFFF 2 0xFFFF 2 0x7FFF I C0 Status Register I C0 Slave Address Register I C0 Control Register 0xA018 R/W I C0 SCL LOW duration Register IC0SCLH 0xA01C R/W I C0 SCL HIGH duration Register IC0SDH 0xA020 R/W I C0 SDA Hold Register IC1DR 0xA100 R/W I C1 Data Register IC1SR 0xA108 R, R/W IC1SAR 0xA10C R/W 0xA114 R/W Reset 2 I C0 Data Register IC0SCLL IC1CR PS034504-0617 0xA014 Description I C1 Status Register I C1 Slave Address Register I C1 Control Register IC1SCLL 0xA118 R/W I C1 SCL LOW duration Register IC1SCLH 0xA11C R/W I C1 SCL HIGH duration Register IC1SDH 0xA120 R/W I C1 SDA Hold Register PRELIMINARY 152 Z32F1281 Product Specification I²C Interface ICnDR I2C Data Register ICnDR is an 8-bit read/write register. It contains a byte of serial data to be transmitted or a byte which has just been received. IC0DR=0x4000_A000, IC1DR=0x4000_A100, 7 6 5 4 3 2 1 0 DR 0xFF RW 7 0 PS034504-0617 ICDR The most recently received data or data to be transmitted. PRELIMINARY 153 Z32F1281 Product Specification I²C Interface I2C Status Register ICnSR 2 ICnSR is an 8-bit read/write register. It contains the status of the I C bus interface. Writing to the register clears the status bits. IC0SR=0x4000_A008, IC1SR=0x4000_A008 7 6 5 4 3 2 1 0 GCALL TEND STOP SSEL MLOST BUSY TMOD RXACK 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW 7 GCALL 6 TEND 5 STOP 4 SSEL 3 MLOST 2 BUSY 1 TMOD 0 RXACK 2 This bit has different meaning depending on whether I C is master or slave 2 When I C is a master, this bit represents whether it received AACK(Address ACK) from slave. 2 When I C is slave, this bit is used to indicate general call. 0 No AACK is received (master mode) 1 AACK is received (master mode). 0 General call is not detected (slave mode) 1 General call is detected (slave mode) 1 Byte transmission complete flag 0 The transmission is working or not completed. 1 The transmission is completed. STOP flag 0 STOP is not detected. 1 STOP is detected. Slave flag 0 Slave is not selected. 1 Slave is selected. Mastership lost flag 0 Mastership is not lost. 1 Mastership is lost. BUSY flag 2 0 I C bus is in IDLE state. 2 1 I C bus is busy. Transmitter/Receiver mode flag 0 Receiver mode. 1 Transmitter mode. Rx ACK flag 0 Rx ACK is not received. 1 Rx ACK is received. 2 When an I C interrupt occurs, except for the STOP interrupt, the SCL line is held LOW. To release SCL, write an arbitrary value to ICnSR. When ICnSR is written, the TEND, STOP, SSEL, MLOST, and RXACK bits are cleared. PS034504-0617 PRELIMINARY 154 Z32F1281 Product Specification I²C Interface I2C Slave Address Register ICnSAR ICnSAR is an 8-bit read/write register. It shows the address in slave mode. IC0SAR=0x4000_A00C, IC1SAR=0x4000_A10C 7 6 5 7 1 0 PS034504-0617 4 3 2 1 0 SVAD GCEN 0x00 0 RW RW SVAD 7-bit Slave Address GCEN General call enable bit 0 General call is disabled. 1 General call is enabled. PRELIMINARY 155 Z32F1281 Product Specification I²C Interface ICnCR I2C Control Register 2 ICnCR is an 8-bit read/write register. This register can be set to configure I C operation mode and 2 simultaneously allows for I C transactions to be kicked off. IC0CR=0x4000_A014, IC1CR=0x4000_A114 7 6 IIF 0 5 4 3 SOFTRST INTEN ACKEN 0 0 0 RW RW RW 0 RW PS034504-0617 7 IIF 5 SOFTRST 4 INTEN 3 ACKEN 1 STOP 0 START 2 0 1 0 STOP START 0 0 RW RW Interrupt flag bit 0 No interrupt is generated or interrupt is cleared 1 Interrupt is generated Soft Reset enable bit. 0 Soft Reset is disabled. 1 Soft Reset is enabled.. Interrupt enabled bit. 0 Interrupt is disabled. 1 Interrupt is enabled. ACK enable bit in Receiver mode. 0 ACK is not sent after receiving data. 1 ACK is sent after receiving data. Stop enable bit. When this bit is set as “1” in transmitter mode, next transmission will be stopped even though ACK signal has been received. 0 Stop is disabled. 1 Stop is enabled. When this bit is set, transmission will be stopped. Transmission start bit in master mode. 0 Waits in slave mode. 1 Starts transmission in master mode. PRELIMINARY 156 Z32F1281 Product Specification I²C Interface I2C SCL LOW Duration Register ICnSCLL ICnSCLL is a 16-bit read/write register. SCL LOW time can be set by writing this register in master mode. IC0SDLL=0x4000_A018, IC1SDLL=0x4000_A118 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCLL 0xFFFF RW 15 0 SCLL SCL LOW duration value. SCLL = ( PCLK * SCLL[15:0] ) + 2*PCLKs Default value is 0xFFFF. SCLL SCL Figure 14.2.SCL LOW Timing PS034504-0617 PRELIMINARY 157 Z32F1281 Product Specification I²C Interface I2C SCL HIGH duration Register ICnSCLH ICnSCLH is a 16-bit read/write register. SCL HIGH time will be set by writing this register in master mode. IC0SDLH=0x4000_A01C, IC1SDLH=0x4000_A11C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCLH 0xFFFF RW 15 0 SCLH SCL HIGH duration value. SCLH = ( PCLK * SCLH[15:0] ) + 3 PCLKs Default value is 0xFFFF. SCLH SCL Figure 14.3.SCL HIGH Timing PS034504-0617 PRELIMINARY 158 Z32F1281 Product Specification ICnSDH I²C Interface SDA Hold Register ICnSDH is a 15-bit read/write register. SDA HOLD time will be set by writing this register in master mode. IC0SDH=0x4000_A020, IC1SDH=0x4000_A120 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDH 0x7FFF RW 14 SDH 0 SDA HOLD time setting value. SDH = ( PCLK * SDH[14:0] ) + 4 PCLKs Default value is 0x7FFF. SDH SDA SCL Figure 14.4.SDA HOLD Timing PS034504-0617 PRELIMINARY 159 Z32F1281 Product Specification I²C Interface Functional Description I2C Bit Transfer The data on the SDA line must be stable during the “H” period of the clock. The “H” or “L” state of the data line can only change when the clock signal on the SCL line is “L” as shown in Figure 14.5. SDA SCL Data line Stable: Data valid except S, Sr, P Change of Data allowed 2 Figure 14.5. I C Bus Bit Transfer PS034504-0617 PRELIMINARY 160 Z32F1281 Product Specification I²C Interface START/Repeated START/STOP 2 Within the procedure of the I C-bus, unique situations arise which are defined as START(S) and STOP(P) conditions; see Figure 14.6. An “H” to “L” transition on the SDA line while SCL is “H” is one such unique case. This situation indicates a START condition. An “L” to “H” transition on the SDA line while SCL is “H” defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. The bus is busy if a repeated START(Sr) is generated instead of a STOP condition. In this respect, the START(S) and repeated START(Sr) conditions are functionally identical. Therefore, for the remainder of this document, the S symbol will be used as a generic term to represent both the START and repeated START conditions, unless Sr is particularly relevant. Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware. However, microcontrollers with no such interface have to sample the SDA line at least twice per clock period to sense the transition. SDA SCL S P START Condition STOP Condition Figure 14.6. START and STOP Condition PS034504-0617 PRELIMINARY 161 Z32F1281 Product Specification I²C Interface Data Transfer Every byte put on the SDA line must be 8-bit long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first; see Figure 14.7. If a slave can’t receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL “L” to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL. A message which starts with such an address can be terminated by generation of a STOP condition, even during the transmission of a byte. In this case, no acknowledge is generated. P SDA MSB Acknowledgemen Acknowledgemen t Signal form Slave Byte Complete, t Signal form Slave Clock line held low Interrupt within Device SCL S or Sr 1 while interrupts served. 1 9 ACK Sr are 9 ACK Sr or P START or Repeated STOPor Repeated START Condition START Condition 2 Figure 14.7. I C Bus Data Transfer PS034504-0617 PRELIMINARY 162 Z32F1281 Product Specification I²C Interface Acknowledge Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable “L” during the “H” period of this clock pulse as shown in Figure 14.8. Set-up and hold times must also be taken into account. When a slave doesn’t acknowledge the slave address (for example, it is unable to receive or transmit because it is performing a real-time function), the data line must be left “H” by the slave. The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. If a slave-receiver does acknowledge the slave address but, sometime later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by the slave generating the notacknowledge on the first byte to follow. The slave leaves the data line “H” and the master generates a STOP or a repeated START condition. If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating an acknowledge signal on the last byte that was clocked out of the slave. The slave-transmitter must release the data line to allow the master to generate a STOP or repeated START condition. Data Output By Transmitter NAC K Data Output By Receiver AC K 1 SCL From MASTER 2 8 9 Clock pulse for ACK 2 Figure 14.8. I C Bus Acknowledge PS034504-0617 PRELIMINARY 163 Z32F1281 Product Specification I²C Interface Synchronization 2 All masters generate their own clock on the SCL line to transfer messages on the I C-bus. Data is only valid during the “H” period of the clock. A defined clock is therefore required for the bit-by-bit arbitration procedure to take place. 2 Clock synchronization is performed using the wires AND connection of I C interfaces to the SCL line. This means that an “H” to “L” transition on the SCL line will cause the devices concerned to start counting off their “L” period and, once a device clock has gone to “L” period, it will hold the SCL line in that state until the clock “H” state is reached as shown in Figure 14.9. However, the “L” to “H” transition of this clock may not change the state of the SCL line if another clock is still within its “L” period by the device with the longest “L” period. Devices with shorter “L” periods enter an “H” wait-state during this time. When all devices concerned have counted off their “L” period, the clock line will be released and go to “H” state. At this point, there will be no difference between the device clocks and the state of the SCL line, and the devices will start counting their “H” periods. The first device to complete its “H” period will again pull the SCL line “L”. Wait High Start High Counting Counting Fast Device SCLOUT High Slow Device SCLOUT Counter Reset SCL Figure 14.9. Clock Synchronization during the Arbitration Procedure Arbitration A master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold time of the START condition which results in a defined START condition to the bus. Arbitration takes place on the SDA line, while the SCL line is at the “H” level, in such a way that the master which transmits “H” level, while another master is transmitting a “L” level, will switch off its DATA output stage because the level on the bus doesn’t correspond to its own level. Arbitration can continue for many bits. The first stage of arbitration is comparison of the address bits. If the masters are each trying to address the same device, arbitration continues with comparison of the data-bits if they are master-transmitter or acknowledge-bits if they are master-receiver. Because address and data 2 information on the I C-bus is determined by the winning master, no information is lost during the arbitration process. A master that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration. If a master also incorporates a slave function and it loses arbitration during the addressing stage, it’s possible that the winning master is trying to address it. The losing master must therefore switch over immediately to its slave mode. Figure 14.10 shows the arbitration procedure for two masters. More masters may be involved, depending on the number of masters connected to the bus. As soon as there is a difference between the internal data level of the master generating Device1 Dataout and the actual level on the SDA line, its data output is switched off, which means that an “H” output level is then connected to the bus. This will not affect the data transfer PS034504-0617 PRELIMINARY 164 Z32F1281 Product Specification I²C Interface initiated by the winning master. Arbitration Process not adapted Device 1 loses Arbitration Device1 outputs High Device1 DataOut Device2 DataOut SDA on BUS SCL on BUS S Figure 14.10. Arbitration Procedure of Two Masters I2C Operation 2 I C supports the interrupt operation. Once an interrupt is serviced, the IIF (ICnCR[7]) flag is set. ICnSR shows 2 I C-bus status information and the SCL line stays “L” before the register is written as a certain value. The status register can be cleared by writing a zero. Master Transmitter The master transmitter shows the flow of the transmitter in Master Mode as shown in Figure 14.11. PS034504-0617 PRELIMINARY 165 Z32F1281 Product Specification I²C Interface IDLE Master Receiver SLA+R S or Sr SLA+W ACK N STOP P Y LOST DATA ACK Rs N STOP LOST Cont? Lost? LOST& STOP Y Y LOST P Other master continues Y From master to slave / Master command or Data Write N From slave to master STOP ACK Interrupt, SCL line is held low P Interrupt after stop command P LOST& Arbitration lost as master and addressed as slave Figure 14.11. Transmitter Flowchart in Master Mode PS034504-0617 PRELIMINARY 166 Z32F1281 Product Specification I²C Interface Master Receiver The master receiver shows the flow of the receiver in Master Mode as shown in Figure 14.12. IDLE Master Transmitter SLA+W S or Sr SLA+R N ACK STOP P Y LOST DATA Rs LOST LOST& Sr ACK N STOP P Y LOST From master to slave / Master command or Data Write From slave to master Other master continues ACK Interrupt, SCL line is held low ACK P LOST& Interrupt after stop command Arbitration lost as master and addressed as slave Figure 14.12. Receiver Flowchart in Master Mode PS034504-0617 PRELIMINARY 167 Z32F1281 Product Specification I²C Interface Slave Transmitter The slave transmitter shows the flow of the transmitter in Slave Mode as shown in Figure 14.13. IDLE S or Sr SLA+R GCALL ACK LOST& Y DATA Y ACK N STOP P Y IDLE From master to slave / Master command or Data Write From slave to master ACK Interrupt, SCL line is held low P Interrupt after stop command LOST& GCALL Arbitration lost as master and addressed as slave General Call Address Figure 14.13. Transmitter Flowchart in Slave Mode PS034504-0617 PRELIMINARY 168 Z32F1281 Product Specification I²C Interface Slave Receiver The slave receiver shows the flow of the receiver in Slave Mode as shown in Figure 14.14. IDLE S or Sr SLA+W ACK LOST& GCALL N Y DATA Y ACK N STOP P Y IDLE From master to slave / Master command or Data Write From slave to master ACK Interrupt, SCL line is held low P Interrupt after stop command LOST& GCALL Arbitration lost as master and addressed as slave General Call Address Figure 14.14. Receiver Flowchart in Slave Mode PS034504-0617 PRELIMINARY 169 Z32F1281 Product Specification Motor Pulse-Width-Modulator 15. Motor Pulse-Width-Modulator Introduction The Motor Pulse Width Modulator (MPWM) is a programmable motor controller. Features include:       6-channel output for motor control Dead- time zone support Protection event and over voltage event handling Six ADC trigger outputs Interval interrupt mode (period interrupt only) Up-down count mode Figure 15.1 shows the MPWM block diagram. Over voltage detection Protection event PWM CONTROL POLVH Dead time generator POLVL POLWH Over Voltage control POLUL Protection control Dead time UH Force Mode Control Period Duty UH Duty UL Duty VH Duty VL Duty WH Duty WL POLUH POLWL UL VH VL WH WL APB I/F Main Counter ADC Trigger5 PWM port Control Port Hi-Z control Over voltage IRQ ADC Trigger4 ADC Trigger3 Protection IRQ ADC Trigger2 Interrupt & Status PWM IRQ ADC Trigger1 Trigger 0 Trigger 1 Trigger 2 Trigger 3 Trigger 4 Trigger 5 ADC Trigger0 Figure 15.1. MPWM Block Diagram PS034504-0617 PRELIMINARY 170 Z32F1281 Product Specification Motor Pulse-Width-Modulator Pin Description Table 15.1. External Signals PIN NAME TYPE DESCRIPTION MP0UH O MPWM 0 Phase-U H-side output MP0UL O MPWM 0 Phase-U L-side output MP0VH O MPWM 0 Phase-V H-side output MP0VL O MPWM 0 Phase-V L-side output MP0WH O MPWM 0 Phase-W H-side output MP0WL O MPWM 0 Phase-W L-side output MP1UH O MPWM 1 Phase-U H-side output MP1UL O MPWM 1 Phase-U L-side output MP1VH O MPWM 1 Phase-V H-side output MP1VL O MPWM 1 Phase-V L-side output MP1WH O MPWM 1 Phase-W H-side output MP1WL O MPWM 1 Phase-W L-side output PRTIN0 I MPWM 0 Protection Input 0 OVIN0 I MPWM 0 Over-voltage Input 1 PRTIN1 I MPWM 1 Protection Input 0 OVIN1 I MPWM 1 Over-voltage Input 1 Registers The base address of MPWM is shown in Table 15.2. Table 15.2. MPWM Base Address BASE ADDRESS PS034504-0617 MPWM0 0x4000_4000 MPWM1 0x4000_5000 PRELIMINARY 171 Z32F1281 Product Specification Motor Pulse-Width-Modulator Table 15.3 lists the register memory map. Table 15.3. MPWM Register Map Name Offset R/W MPnMR 0x0000 R/W PWM Mode register Description 0x0000_0000 Reset MPnPMR 0x0004 R/W PWM Port Mode register 0x0000_0000 MPnOCR 0x0008 R/W PWM Output control 0x0000_0000 MPnPRD 0x000C R/W PWM Period register 0x0000_0002 MPnDUH 0x0010 R/W PWM Duty UH register 0x0000_0001 MPnDVH 0x0014 R/W PWM Duty VH register 0x0000_0001 MPnDWH 0x0018 R/W PWM Duty WH register 0x0000_0001 MPnDUL 0x001C R/W PWM Duty UL register 0x0000_0001 MPnDVL 0x0020 R/W PWM Duty VL register 0x0000_0001 MPnDWL 0x0024 R/W PWM Duty WL register 0x0000_0001 MPnCR1 0x0028 R/W PWM Control 0x0000_0000 MPnCR2 0x002C R/W PWM Start 0x0000_0000 MPnSR 0x0030 R PWM Status 0x0000_0000 MPnIER 0x0034 R/W PWM Interrupt Enable 0x0000_0000 MPnCNT 0x0038 R PWM counter register 0x0000_0001 MPnDTR 0x003C R/W PWM dead time control 0x0000_0000 MPnPCR 0x0040 R/W PWM protection control register 0x0000_0000 MPnPSR 0x0044 R/W PWM protection status 0x0000_0080 MPnOVCR 0x0048 R/W PWM over voltage control 0x0000_0000 MPnOVSR 0x004C R/W PWM over voltage status 0x0000_0000 MPnATCR 0x0054 R/W PWM ADC Trigger control 0x0000_0000 MPnATR1 0x0058 R/W PWM ADC Trigger reg1 0x0000_0000 MPnATR2 0x005C R/W PWM ADC Trigger reg2 0x0000_0000 MPnATR3 0x0060 R/W PWM ADC Trigger reg3 0x0000_0000 MPnATR4 0x0064 R/W PWM ADC Trigger reg4 0x0000_0000 MPnATR5 0x0068 R/W PWM ADC Trigger reg5 0x0000_0000 MPnATR6 0x006C R/W PWM ADC Trigger reg6 0x0000_0000 PS034504-0617 PRELIMINARY 172 Z32F1281 Product Specification MPnMR Motor Pulse-Width-Modulator MPWM Mode Register The MPWM operation mode register is a 16-bit register. 0 RW 00 0 0 0 0 0 RW RW RW RW 8 15 MOTOR 0 1 13 12 MCHMOD 00 01 10 11 0 1 9 UPDATE 8 UALL 0 1 7 FORCEN 0 1 5 4 FORCM 00 01 10 11 1 PDUP 0 1 0 PS034504-0617 UPDOWN 0 1 7 6 5 4 3 2 1 UPDOWN 9 PDUP 10 0 0 0 0 RW RW FORCM 11 FORCEN 12 UALL 0 13 MCHMOD 14 MOTOR 15 UPDATE MP0MR=0x4000_4000, MP1MR=0x4000_5000 0 00 RW 0 Normal PWM mode Motor PWM mode In Motor mode initial outputs of H-ch become LOW and outputs of L-ch become High (before PWM START) Motor control channel mode 2 channels symmetric mode Duty H decides the duty value of H-ch Duty L decides the duty value of L-ch 1 channel asymmetric mode Duty H decides the up-counting duty value of H-ch Duty L decides the down-counting duty value of H-ch L channel become the inversion of H channel 1 channel symmetric mode Duty H decides the duty value of H-ch L channel become the inversion of H channel Not valid (same with 00) Update all duty, period register after Update all duty, period register enable. When UPDATE set, Duty and Period V registers are updated after two PWM clocks It should be cleared before PWM start(set PSTART) No effect. Duty V and Duty W register will be stored with the same value of Duty U value when Duty U is written. Force mode disable(normal mode) user can enable and disable each channels by Output control register Each channel is “AND”ed with MPnOCR (when port enable is low, output becomes low) Each channel is “OR”ed with MPnOCR (when port enable is high, output becomes high) Each channel is “XOR”ed with MPnOCR (when port enable is low, output becomes low) Each channel is “AND”ed with MPnOCR but when port is disabled, output becomes high-Z Period, duty value updated at every period match (both up count mode and BTB mode) Period, duty value updated at every period match and bottom(valid in up/down count mode) PWM Up count mode PWM Up and Down count mode Note: See Figure 15.2 for timing and operation. PRELIMINARY 173 Z32F1281 Product Specification Motor Pulse-Width-Modulator pwmclk counter 01 02 FE FF 01 02 FE FF FE 01 00 01 02 FE FF 01 02 TOP BOTTOM UPDOWN UP_COUNT UPDOWN = 0 UPDOWN = 1 set UPDOWN_int UPDOWN = 1 UPDOWN = 0 UPDOWN = 0 clear UPDOWN_int Figure 15.2. MPWM Register Mode MPnPMR MPWM Port Mode Register The MPWM Port Mode register is a 16-bit register. 0 0 0 0 0 0 9 8 7 6 5 POLWL 10 POLWH 11 POLVL 12 POLVH 13 POLUL 14 0 0 0 0 0 0 0 0 RW RW RW RW RW RW PMOD 15 POLUH MP0PMR=0x4000_4004, MP1PMR=0x4000_5004 00 RW 9 8 PMOD 5 3 1 POLxH 00 01 10 11 0 POLxL 0 1 POL=0 PS034504-0617 3 2 1 0 H-ch PWM pulse out, L-ch PWM pulse out H-ch PWM pulse out , L-ch out High-Z H-ch out High-Z, L-ch PWM pulse out H-ch out High-Z, L-ch out High-Z Normal polarity for UH/VH/WH pins (‘H’ during duty period in normal mode, ‘L’ in motor mode. Initial output is ‘H’) Inversion polarity for UH/VH/WH pins (‘L’ during duty period in normal mode, ‘H’ in motor mode. Initial output is ‘L’) Normal polarity for UL/VL/WL pins (‘H’ during duty period in normal mode, ‘L’ in motor mode. Initial output is ‘L’) Inversion polarity for UL/VL/WL pins (‘L’ during duty period in normal mode, ‘H’ in motor mode. Initial output is ‘H’) 1 4 2 0 4 POL=1 PMODE UH UL UH UL 00 PWMUH PWMUL ~PWMUH ~PWMUL 01 PWMUH Hi-Z ~PWMUH Hi-Z 10 Hi-Z PWMUL Hi-Z ~PWMUL 11 Hi-Z Hi-Z Hi-Z Hi-Z PRELIMINARY 174 Z32F1281 Product Specification MPnOCR Motor Pulse-Width-Modulator MPWM Output Control Register The MPWM output control register is an 8-bit register. MP0OCR=0x4000_4008, MP1OCR=0x4000_5008, 7 6 0 5 4 3 2 1 0 UHVAL ULVAL VHVAL VLVAL WHVAL WLVAL 0 0 0 0 0 0 RW RW RW RW RW RW 0 xHVAL xLVAL MPnPRD Operator value for each output port in Force Mode (ports output become High/Low or High-Z by FORCM[1:0]) in MPnMR register. Depending on FORCM selection, the output values are calculated with MPnOCR and current MPWM outputs. MPWM Period Register The MPWM Period Register is a 16-bit register. MP0PRD=0x4000400C, MP1PRD=0x40000500C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PERIOD 0x0002 RW 15:0 MPnDUH PERIOD 16-bit PWM period. It should be larger than 0x0010 (if Duty is 0x0000, PWM will not work) MPWM Duty UH Register The MPWM U channel duty register is a 16-bit register. MP0DUH=0x4000_4010, MP1DUH=0x4000_5010 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DUH 0x0001 RW 15:0 PS034504-0617 DUTY UH [15:0] 16-bit PWM Duty for UH output. It should be larger than 0x0001 (if Duty is 0x0000, PWM will not work) PRELIMINARY 175 Z32F1281 Product Specification MPnDVH Motor Pulse-Width-Modulator MPWM Duty VH Register The MPWM V channel duty register is a 16-bit register. MP0DVH=0x4000_4014, MP1DVH=0x4000_5014 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DVH 0x0001 RW 15:0 MPnDWH DUTY VH 16-bit PWM Duty for VH output. It should be larger than 0x0001 (if Duty is 0x0000, PWM will not work) MPWM Duty WH Register The MPWM W channel duty register is a 16-bit register. MP0DWH=0x4000_4018, MP1DWH=0x4000_5018 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DWH 0x0001 RW 15:0 MPnDUL DUTY WH 16-bit PWM Duty for WH output. It should be larger than 0x0001 (if Duty is 0x0000, PWM will not work) MPWM Duty UL Register The MPWM U channel duty register is a 16-bit register. MP0DUL=0x4000_401C, MP1DUL=0x4000_501C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DUL 0x0001 RW 15:0 PS034504-0617 DUTY UL 16-bit PWM Duty for UL output. It should be larger than 0x0001 (if Duty is 0x0000, PWM will not work) PRELIMINARY 176 Z32F1281 Product Specification MPnDVL Motor Pulse-Width-Modulator MPWM Duty VL Register The MPWM V channel duty register is a 16-bit register. MP0DVL=0x4000_4020, MP1DVL=0x4000_5020 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DVL 0x0001 RW 15:0 MPnDWL DUTY VL 16-bit PWM Duty for VL output. It should be larger than 0x0001 (if Duty is 0x0000, PWM will not work) MPWM Duty WL Register The PWM W channel duty register is a 16-bit register. MP0DWL=0x4000_4024, MP1DWL=0x4000_5024 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DWL 0x0001 RW 15:0 MPnCR1 DUTY WL [15:0] 16-bit PWM Duty for WL output. It should be larger than 0x0001 (if Duty is 0x0000, PWM will not work) MPWM Control Register 1 The MPWM Control Register 1 is a 16-bit register. MP0CR1=0x4000_4028, MP1CR1=0x4000_5028 10 9 0 RW PS034504-0617 0 7 0 0 RW RW 0 RW 8 15 INTVEN 13 12 IRQMD 10 8 7 0 IRQN[2:0] PWMEN HALT 6 5 4 3 2 1 0 0 0 0 0 0 0 0 HALT 11 IRQMD 12 PWMEN 0 13 IRQN 14 INTVEN 15 RW IRQ interval mode (IRQ asserts to CPU at every N-th period IRQ) 0 IRQ at period, duty match (UP) 1 IRQ at bottom, duty match (DOWN) (only valid in UPDOWN mode) 2 IRQ at every period, bottom, duty match (UP & DOWN) IRQ interval number (1~8th PRDIRQ) PWM enable PWM HALT (PWM counter stop but not reset) PWM outputs keep previous state PRELIMINARY 177 Z32F1281 Product Specification Motor Pulse-Width-Modulator Each interrupt source can be enabled or disabled by the MPWM interrupt enable register. TOP BOTTOM DUTY UH IRQMD=0 DUHIRQ PRDIRQ DUHIRQ PRDIRQ DUHIRQ PRDIRQ DUHIRQ DUHIRQ PRDIRQ DUHIRQ IRQMD=1 DUHIRQ BOTIRQ DUHIRQ BOTIRQ IRQMD=2 DUHIRQ PRDIRQ DUHIRQ PRDIRQ TOP BOTTOM DUTY UH IRQMD=0 DUHIRQ PRDIRQ DUHIRQ PRDIRQ DUHIRQ IRQMD=1 DUHIRQ BOTIRQ DUHIRQ BOTIRQ DUHIRQ BOTIRQ DUHIRQ BOTIRQ IRQMD=2 DUHIRQ PRDIRQ DUHIRQ PRDIRQ DUHIRQ Figure 15.3. PWM-related Interrupt Sources MPnCR2 MPWM Control Register 2 The MPWM Control Register 2 is an 8-bit register. MP0CR2=0x4000_402C, MP1CR2=0x4000_502C, 7 6 5 4 3 2 1 0 PSTART 0 0 0 0 0 0 0 0 RW 0 PSTART 0 1 PWM counter stop and clear PWM counter start (will be re-synced @PWM clock twice) PWMEN should be “1” to start PWM counter PS034504-0617 PRELIMINARY 178 Z32F1281 Product Specification MPnSR Motor Pulse-Width-Modulator MPWM Status Register The PWM Status Register is a 16-bit register. 11 10 9 8 7 DUHIRQ DULIRQ DVHIRQ DVLIRQ DWHIRQ DWLIRQ 0 000 RW RW PS034504-0617 12 BOTIRQ 13 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW IRQCNT 14 DOWN 15 PRDIRQ MP0SR=0x4000_4030, MP1CR=0x4000_5030 15 DOWN 14 12 7 IRQCNT[2:0] 6 BOTIRQ 5 DUHIRQ 4 DULIRQ 3 DVHIRQ 2 DVLIRQ 1 DWHIRQ 0 DWLIRQ PRDIRQ 0 1 6 5 4 3 2 1 0 PWM Count Up PWM Count Down (in BTB mode) Interrupt count number of period match (Interval PRDIRQ mode) PWM period interrupt flag (0: no int / 1: int occurred) Write “1” to clear flag PWM bottom interrupt flag (0: no int / 1: int occurred) Write “1” to clear flag PWM duty UH interrupt flag (0: no int / 1: int occurred) Write “1” to clear flag PWM duty UL interrupt flag (0: no int / 1: int occurred) Write “1” to clear flag PWM duty VH interrupt flag (0: no int / 1: int occurred) Write “1” to clear flag PWM duty VL interrupt flag (0: no int / 1: int occurred) Write “1” to clear flag PWM duty UH interrupt flag (0: no int / 1: int occurred) Write “1” to clear flag *This flag will be enabled by DUHIEN bit. PWM duty WL interrupt flag (0: no int / 1: int occurred) Write “1” to clear flag PRELIMINARY 179 Z32F1281 Product Specification MPnIER Motor Pulse-Width-Modulator MPWM Interrupt Enable Register The MPWM Interrupt Enable Register is an 8-bit register. MP0IER=0x4000_4034, MP1IER=0x4000_5034, 7 6 5 4 3 2 1 0 PRDIEN BOTIEN DUHIEN DULIEN DVHIEN DVLIEN DWHIEN DWLIEN 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW MPnCNT 7 PRDIEN 6 BOTIEN 5 DUHIEN 4 DULIEN 3 DVHIEN 2 DVLIEN 1 DWHIEN 0 DWLIEN PWM period interrupt enable 0: interrupt disable 1: interrupt enable PWM bottom interrupt enable 0: interrupt disable 1: interrupt enable PWM U Duty H match interrupt enable 0: interrupt disable 1: interrupt enable PWM U Duty L match interrupt enable 0: interrupt disable 1: interrupt enable PWM V Duty H match interrupt enable 0: interrupt disable 1: interrupt enable PWM V Duty L match interrupt enable 0: interrupt disable 1: interrupt enable PWM W Duty H match interrupt enable 0: interrupt disable 1: interrupt enable PWM W Duty L match interrupt enable 0: interrupt disable 1: interrupt enable MPWM Counter Register The PWM Counter Register is a 16-bit read-only register. MP0CNT=0x4000_4038, MP1CNT=0x4000_5038 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 0x0000 RW MPnCNT PS034504-0617 PWM counter value read (16-bit) PRELIMINARY 180 Z32F1281 Product Specification MPnDTR Motor Pulse-Width-Modulator MPWM Dead Time Register The PWM Dead Time Register is a 16-bit register. 14 13 12 11 10 9 8 DT 0 0 0 0 0 0 0 0x00 RW RW DTEN 15 DTCLK MP0DTR=0x4000_403C, MP1DTR=0x4000_503C 0 RW PS034504-0617 15 DTEN 8 DTCLK 7 0 DT[7:0] 7 6 5 4 3 2 1 0 0 Dead Time disable 1 Dead Time enable 0 Dead time counter uses PWM CLK/4 1 Dead time counter uses PWM CLK/8 Dead Time value (Dead time setting makes output delay of ‘low to high transition’ in normal polarity) 0x01 ~0xFF : Dead time PRELIMINARY 181 Z32F1281 Product Specification MPnPCR Motor Pulse-Width-Modulator MPWM Protection Control Register The PWM Protection Control Register is a 32-bit register. MP0PCR=0x4000_4040, MP1PCR=0x4000_5040 UHPROT ULPROT VHPROT VLPROT WHPROT WLPROT PROTCLR 6 4 PTDBC[2:0] 3 2 1 0 PS034504-0617 PTSEL[1:0] PROTCLR PTDBC 0 0 0 0 000 RW RW 3 2 0 0 1 0 PTSEL WLPROT 0 4 00 RW WHPROT RW 13 12 11 10 9 8 7 0 RW RW PRTIN C3IN C2IN C1IN C0IN AD2IN AD1IN AD0IN PROTDIS 0 RW RW 23 22 21 20 19 18 17 16 15 0 VLPROT 0 RW 0 VHPROT 0 5 RW 0 6 ULPROT 0 7 RW PROTDIS 0 8 UHPROT AD0IN 0 9 RW AD1IN 0 RW C0IN AD2IN 0 RW 0 C1IN 0 RW 0 C2IN 0 RW 0 C3IN 0 RW 0 RW 0 PRTIN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 External PRTIN pin input (Active High) Comparator #3 output Comparator #2 output Comparator #1 output Comparator #0 output ADC2 comparator output ADC1 comparator output ADC0 comparator output Protection mode disable (default 0, protection enable) To set PROTDIS as ‘1’, 0xA5A5 should be written to PROTPAT[31:16] U-phase H-side protection output (‘0’=L/’1’=H) U-phase L-side protection output (‘0’=L/’1’=H) V-phase H-side protection output (‘0’=L/’1’=H) V-phase L-side protection output (‘0’=L/’1’=H) W-phase H-side protection output (‘0’=L/’1’=H) W-phase L-side protection output (‘0’=L/’1’=H) Protection clear (after protection mode active) To clear PROTCLR bit, 0x39AA should be written to PROTPAT[31:16] Protection signal debounce 00 – no debounce 1~7 – debounce by (fsystem * PTDBC[2:0]) reserved Protection mode select 00 – no output control 01 – no control for UH/VH/WH UL/VL/WL controlled by UL~WLPROT 10 – no control for UL/VL/WL UH/VH/WH controlled by UH~WHPROT 11 – all outputs controlled by UH~WLPROT PRELIMINARY 182 Z32F1281 Product Specification MPnPSR Motor Pulse-Width-Modulator MPWM Protection Status Register The PWM Protection Status Register is a 32-bit register. MP0PSR=0x4000_4044, MP1PSR=0x4000_5044 8 7 0 0 1 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 RW 0x0000 PROTIN PROTPAT RW 31 16 7 0 PS034504-0617 6 PROTPAT PROTEN PROTIN RW 9 PROTEN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Lock PROTPAT to set or reset Protection or Over voltage control bit Protection mode enable status Protection input status PRELIMINARY 183 Z32F1281 Product Specification MPnOVCR Motor Pulse-Width-Modulator MPWM Over Voltage Control Register The PWM Over Voltage Control Register is a 32-bit register. 0 0 0 PS034504-0617 RW RW RW 23 22 21 20 19 18 17 16 15 OVIN C3IN C2IN C1IN C0IN AD2IN AD1IN AD0IN OVEN 7 OVCLR 6 5 4 1 0 OVDBC OVSEL 0 0 0 0 0 5 0 0 0 000 4 3 2 0 0 1 0 OVSEL 0 6 00 RW 0 7 OVDBC OVEN 0 8 RW AD0IN 0 9 OVCLR AD1IN 0 RW C0IN AD2IN 0 RW 0 C1IN 0 RW 0 C2IN 0 RW 0 C3IN 0 RW 0 RW 0 OVIN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RW MP0PCR=0x4000_4048, MP1PCR=0x4000_5048 External OVIN pin input Comparator #3 output Comparator #2 output Comparator #1 output Comparator #0 output ADC2 comparator output (AD2CCR[23]) ADC1 comparator output (AD1CCR[23]) ADC0 comparator output (AD0CCR[23]) Over voltage protection mode enable (default 0, over voltage protection disable) To set OVEN as ‘1’, 0x7788 should be written to PROTPAT[31:16] OV Protection clear (after OV protection mode active) To clear the OVCLR flag, 0x5596 should be written to PROTPAT[31:16] Over voltage protection signal debounce 00 – no debounce 1~7 – debounce by (fsystem * PTDBC[2:0]) Over Voltage Protection mode select 00 – no output control 01 – High output for UH/VH/WH + POL Low output for UL/VL/WL + POL 10 – Low output for UH/VH/WH + POL High output for UL/VL/WL + POL 11 – all outputs controlled by UH~WLPROT PRELIMINARY 184 Z32F1281 Product Specification MPnOVSR Motor Pulse-Width-Modulator MPWM Over-Voltage Status Register The PWM Over Voltage Status Register is an 8-bit read-only register. MP0OVSR=0x4000_404C, MP1OVCR=0x4000_504C, 7 6 5 4 3 2 1 0 OVSTAT OVPIN 0 0 0 0 0 0 0 0 R R 7 0 MPnATCR OVSTAT OVPIN Over voltage protection mode status Over voltage protection input status MPWM ADC Trigger Control Register The PWM ADC Trigger Control Register is a 16-bit register. 14 13 12 11 10 9 8 ATRGEN 0 0 0 0 0 0 0 0 0 RW RW 8 7 1 0 PS034504-0617 ATRGALL ATRGEN ATRGM 7 6 5 4 3 2 0 0 0 0 0 1 0 ATRGM 15 ATRGALL MP0ATCR=0x4000_4054, MP1ATCR=0x4000_5054 00 RW ADC Trigger register 0 match event makes all trigger signals ADC Trigger mode enable 00 Always ADC Trigger enable when TRGEN is high 01 ADC Trigger disable in protection state 10 ADC Trigger disable in over voltage state 11 ADC Trigger disable in protection, over voltage state PRELIMINARY 185 Z32F1281 Product Specification MPnATRm Motor Pulse-Width-Modulator MPWMn ADC Trigger Counter m Register MPnATR1 MPnATR2 MPnATR3 MPnATR4 MPnATR5 MPnATR6 MPWM ADC Trigger Counter 1 Register MPWM ADC Trigger Counter 2 Register MPWM ADC Trigger Counter 3 Register MPWM ADC Trigger Counter 4 Register MPWM ADC Trigger Counter 5 Register MPWM ADC Trigger Counter 6 Register The PWM ADC Trigger Counter Register is a 32-bit register. MP0ATR1=0x4000_4058, MP1ATR1=0x4000_5058 MP0ATR2=0x4000_405C, MP1ATR2=0x4000_505C MP0ATR3=0x4000_4060, MP1ATR3=0x4000_5060 MP0ATR4=0x4000_4064, MP1ATR4=0x4000_5064 MP0ATR5=0x4000_4068, MP1ATR5=0x4000_5068 MP0ATR6=0x4000_406C, MP1ATR6=0x4000_506C 0 0 0 0 0 0 0 0 0 0 0 0 PS034504-0617 19 ATUDT 17 16 ATMOD 15 0 ATCNT 8 7 ATMOD 0 RW 0 9 ATCNT 0 0x0000 RW ATUDT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RW 6 5 4 3 2 1 0 0 Trigger register update mode ADC trigger value applied at period match event (at the same time with period and duty registers update) 1 Trigger register update mode When this bit set, written Trigger register values are sent to trigger compare block after two PWM clocks (through synchronization logic) 00 ADC trigger Mode register ADC trigger Disable 01 Trigger out when up count match 10 Trigger out when down count match 11 Trigger out when up-down count match ADC Trigger counter 0 (it should be less than PWM period) PRELIMINARY 186 Z32F1281 Product Specification Motor Pulse-Width-Modulator Functional Description The PWMx module allows users to configure the PWM for different types of modulation schemes described in the previous section. The PER2 and PCER2 registers must be configured to enable the PWMx peripheral and the PWMx peripheral clock. Setting or resetting the MOTOR bit in the MPnMR register allows users to operate the motor in Independent or Complementary PWM modes. For more information about operating modes, refer to the diagrams in the following section. Normal PWM Mode Timing Diagram Register Normal PWM Mode UP Count mode Period Duty UL Duty UH PWM UH PWM UL PWM UL’ (POLUL = 1) UP/DOWN Count mode Period Duty UL Duty UH PWM UH PWM UL PWM UL’ (POLUL = 1) Figure 15.4. Normal PWM Mode PS034504-0617 PRELIMINARY 187 Z32F1281 Product Specification Motor Pulse-Width-Modulator Motor PWM Mode Timing Diagram Figure 15.5. Motor PWM Mode Timing Diagram PS034504-0617 PRELIMINARY 188 Z32F1281 Product Specification Motor Pulse-Width-Modulator Motor PWM Mode with Dead Time Zone Motor Control Mode with Dead Time S mode – Symmetry mode AS mode – Asymmetry mode NO 2-ch AS mode 2-ch S mode UH, UL, VH, VL, WH, WL Period Duty UH Duty UL PWM UH PWM UL PWM UL’ (POLUL=1) 1-ch AS mode UH, UL, VH, VL, WH, WL Period Duty UL Duty UH PWM UH PWM UL 1-ch S mode UH, VH, WH Period Duty UH PWM UH PWM UL Figure 15.6. Motor PWM Mode with Dead Time Zone PS034504-0617 PRELIMINARY 189 Z32F1281 Product Specification Motor Pulse-Width-Modulator PWM Output Combination Table PWM mode : PWM out becomes high for duty duration Motor mode : PWM out becomes low for duty duration PWM mode UPDOWN =0 UPDOWN =1 UHOUT ULOUT VHOUT VLOUT WHOUT WLOUT initial L L L L L L up count up@period up@period up@period up@period up@period up@period up count down@dutyU H down@dutyU L down@dutyV H down@dutyV L down@dutyW H down@dutyW L up count down@dutyU H down@dutyU L down@dutyV H down@dutyV L down@dutyW H down@dutyW L down count up@dutyUH up@dutyUL up@dutyVH up@dutyVL up@dutyWH up@dutyWL WLOUT MOTOR mode 2CHS 1CHAS UHOUT ULOUT VHOUT VLOUT WHOUT initial L L L L L L up count up@dutyUH up@dutyUL up@dutyVH up@dutyVL up@dutyWH up@dutyWL down count down@dutyU H down@dutyU L down@dutyV H down@dutyV L down@dutyW H down@dutyW L initial L ~UHOUT L ~VHOUT L ~WHOUT up count up@dutyUH ~UHOUT up@dutyVH ~VHOUT up@dutyWH ~WHOUT down count down@dutyU L ~UHOUT down@dutyV L ~VHOUT down@dutyWL ~WHOUT initial L ~UHOUT L ~VHOUT L ~WHOUT up count up@dutyUH ~UHOUT up@dutyVH ~VHOUT up@dutyWH ~WHOUT down count down@dutyU H ~UHOUT down@dutyV H ~VHOUT down@dutyW H ~WHOUT Polarity UH Polarity UL Polarity VH Polarity VL Polarity WH Polarity WL 00 UHOUT ULOUT VHOUT VLOUT WHOUT WLOUT 01 UHOUT hi-Z VHOUT hi-Z WHOUT hi-Z 10 hi-Z ULOUT hi-Z VLOUT hi-Z WLOUT priority = 4 11 hi-Z hi-Z hi-Z hi-Z hi-Z hi-Z FORCM 00 UHOUT & UHEN ULOUT & ULEN VHOUT & VHEN VLOUT & VLEN WHOUT & WHEN WLOUT & WLEN 01 UHOUT | UHEN ULOUT | ULEN VHOUT | VHEN VLOUT | VLEN WHOUT | WHEN WLOUT | WLEN 10 UHOUT ^ UHEN ULOUT ^ ULEN VHOUT ^ VHEN VLOUT ^ VLEN WHOUT ^ WHEN WLOUT ^ WLEN 11 UHOUT & UHEN ULOUT & ULEN VHOUT & VHEN VLOUT & VLEN WHOUT & WHEN WLOUT & WLEN if ~UHEN, hi-Z if ~ULEN, hi-Z if ~VHEN, hi-Z if ~VLEN, hi-Z if ~WHEN, hi-Z if ~WLEN, hi-Z 1CHS POLARITY control PMOD priority = 3 PTSEL 00 UHOUT ULOUT VHOUT VLOUT WHOUT WLOUT PROTIN= 1 01 UHOUT ULPROT VHOUT VLPROT WHOUT WLPROT 10 UHPROT ULOUT VHPROT VLOUT WHPROT WLOUT priority = 2 11 UHPROT ULPROT VHPROT VLPROT WHPROT WLPROT OVSEL 00 UHOUT ULOUT VHOUT VLOUT WHOUT WLOUT OVPIN=1 01 high low high low high low 10 low high low high low high 11 UHPROT ULPROT VHPROT VLPROT WHPROT WLPROT priority = 1 Figure 15.7. PWM Output Combination Table PS034504-0617 PRELIMINARY 190 Z32F1281 Product Specification 12-Bit A/D Converter 16. 12-Bit A/D Converter Introduction The ADC block consists of 3 independent ADC units that provide:        16 channels of analog inputs Single and Continuous conversion mode Up to 8 times burst conversion support External pin trigger support 4 internal trigger sources support (PWMs, timers) Adjustable sample & hold time ADC clock can be derived from all sources available with configurable dividers Figure 16.1 shows a block diagram of the 12-bit A/D Converter. Figure 16.1. 12-bit A/D Converter Block Diagram PS034504-0617 PRELIMINARY 191 Z32F1281 Product Specification 12-Bit A/D Converter Pin Description Table 16.1. External Signal PIN NAME TYPE DESCRIPTION Access PIN from ADC Channel AVDD P Analog Power(3.0V~VDD) AVSS P Analog GND ADC0 ADC1 ADC2 AN0 A ADC Input 0 Channel 0 Channel 0 Channel 0 AN1 A ADC Input 1 Channel 2 Channel 2 Channel 2 AN2 A ADC Input 2 Channel 4 Channel 4 Channel 4 AN3 A ADC Input 3 Channel 6 Channel 6 Channel 6 AN4 A ADC Input 4 Channel 8 Channel 8 Channel 8 AN5 A ADC Input 5 Channel 9 Channel 9 Channel 9 AN6 A ADC Input 6 Channel 10 Channel 10 Channel 10 AN7 A ADC Input 7 Channel 11 AN8 A ADC Input 8 AN9 A ADC Input 9 AN10 A ADC Input 10 AN11 A ADC Channels to Pin Mapping Channel 12 --- --- Channel 13 -- -- Channel 11 -- ADC Input 11 --- Channel 12 -- Channel 13 -- AN12 A ADC Input 12 -- AN13 A ADC Input 13 A ADC Input 14 --- --- Channel 11 AN14 AN15 A ADC Input 15 -- -- Channel 13 Channel 12 Registers The base addresses of ADC units are listed in Table 16.2. Table 16.2. ADC Base Address BASE ADDRESS PS034504-0617 ADC0 0x4000_B000 ADC1 0x4000_B100 ADC2 0x4000_B200 PRELIMINARY 192 Z32F1281 Product Specification 12-Bit A/D Converter Table 16.3 lists the register memory map. Table 16.3. ADC Register Map PS034504-0617 Name Offset R/W ADnMR 0x0000 R/W ADC Mode register Description Reset 0x00 ADnCSR 0x0004 R/W ADC Channel Select register 0x00 ADnCR1 0x0008 R/W ADC Control register 0x80 ADnTRG0 0x000C R/W ADC Trigger 0 channel register 0x00 ADnTRG1 0x0010 R/W ADC Trigger 1 channel register 0x00 ADnTRG2 0x0014 R/W ADC Trigger 2 channel register 0x00 ADnBCSR 0x0018 R/W ADC Burst mode channel select 0x00 ADnCR2 0x0020 R/W ADC Start 0x00 ADnSR 0x0024 R/W ADC Status 0x00 ADnIER 0x0028 R/W ADC Interrupt Enable register 0x00 AD0/1/2 DDR 0x002C R ADC0/1/2 DMA Data Register 0x00 ADnCCR 0x0070 R/W ADC Channel compare register 0x00 PRELIMINARY 193 Z32F1281 Product Specification ADnMR 12-Bit A/D Converter ADCn Mode Register ADC Mode Registers are 32-bit registers. This register configures the ADC operation mode. AD0MR=0x4000_B000, AD1MR=0x4000_B100, AD2MR=0x4000_B200 31 24 BWAIT 17 DMAEN 0 000 0 0 1 TRGSRC 0 2 00 0 000 RW 0 3 TRGEN 0 4 RW 0 5 ADCMOD BWAITEN 0 6 RW RW 0 ADCEN 0 7 RW 0 8 BSTCNT 0 9 RW 0 RW 0 DMACH 0 RW 0x00 DMAEN BWAIT RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 Burst wait count value (8-bit) ADC conversion delayed for “BWAIT value” * ADCCLK for next conversion in burst mode DMA enable bit – should be set to ‘1’ when ADCEN=’1’. When this bit is set to ‘1’ the DDR register will be populated with the ADC reading. When the bit is set to ‘0’ the DDR register is not populated. When DMA function is enabled, DMA request at the end of every conversion (also in burst mode) and interrupt request can only be generated when ADC receives DMA done from DMAC. 16 DMACH 12 BWAITEN 0 1 10 8 PS034504-0617 BSTCNT 7 ADCEN 5 4 ADCMOD 3 TRGEN 2 0 TRGSRC 000 001 010 011 0 1 00 01 10 11 0 1 000 001 010 011 100 DMA channel option When DMACH is set, Channel information of DMA data will be located at ADDMAR[3:0] for half word size transfer. Channel information is at ADDMAR[19:16] in default.(DMACH is low) Burst wait Enable In burst mode, wait cycles can be inserted between next channel selection and conversion start BWAIT in burst mode disable BWAIT in burst mode enable Burst Count This identifies how many burst conversions to do during burst mode. No Burst mode(Single) 100 5 burst AD conversion 2 burst AD conversion 101 6 burst AD conversion 3 burst AD conversion 110 7 burst AD conversion 4 burst AD conversion 111 8 burst AD conversion ADC disable ADC enable Single conversion mode Continuous conversion mode Reserved Burst Mode Trigger sources disable Trigger sources enable Trigger sources only support single & burst mode (not support continuous mode) External pin Trigger Timer 0 Trigger Timer 1 Trigger Timer 2 Trigger MPWM 0 trigger PRELIMINARY 194 Z32F1281 Product Specification 101 110 111 PS034504-0617 12-Bit A/D Converter MPWM 1 trigger Reserved Reserved PRELIMINARY 195 Z32F1281 Product Specification 12-Bit A/D Converter If ADCMOD is set for Burst Mode, ADC channels are controlled by BST1CH ~ BST8CH. Burst mode always starts from BST1CH (In 3 burst mode, analog inputs of channels which are assigned at BST1CH/BST2CH /BST3CH are converted sequentially). COMP ALERT 0 COMP ALERT 1 COMP ALERT 2 COMP ALERT 3 CH0 OPAMP AIN0 CH1 CH2 OPAMP AIN1 CH3 CH4 OPAMP AIN2 CH5 12bit SAR ADC 0 ADOUT0[11:0] 12bit SAR ADC 1 ADOUT1[11:0] 12bit SAR ADC 2 ADOUT2[11:0] CH6 OPAMP AIN3 CH7 CH8 AIN4 AIN5 CH9 AIN6 CH10 AIN7 CH11 AIN8 CH12 AIN9 CH13 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 AIN10 CH11 AIN11 CH12 AIN12 CH13 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 AIN13 CH11 AIN14 CH12 AIN15 CH13 Figure 16.2. Analog Channel Block Diagram PS034504-0617 PRELIMINARY 196 Z32F1281 Product Specification ADnCSR 12-Bit A/D Converter ADCn Channel Select Register ADC Channel Select Registers are 8-bit registers. AD0SR=0x4000_B004, AD1SR=0x4000_B104, AD2SR=0x4000_B204, 7 6 5 4 3 2 1 0 CHSEL 0 0 0 0 0x0 RW 3 0 CHSEL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC channel 0 selection ADC channel 1 selection ADC channel 2 selection ADC channel 3 selection ADC channel 4 selection ADC channel 5 selection ADC channel 6 selection ADC channel 7 selection ADC channel 8 selection ADC channel 9 selection ADC channel 10 selection ADC channel 11 selection ADC channel 12 selection ADC channel 13 selection ADC channel 14 selection ADC channel 15 selection Table16.1. ADC Channel Select CHSEL PS034504-0617 ADC0 ADC1 ADC2 0000 AIN0 AIN0 AIN0 CH0 0001 AIN0_OPAMP AIN0_OPAMP AIN0_OPAMP CH1 0010 AIN1 AIN1 AIN1 CH2 0011 AIN1_OPAMP AIN1_OPAMP AIN1_OPAMP CH3 0100 AIN2 AIN2 AIN2 CH4 0101 AIN2_OPAMP AIN2_OPAMP AIN2_OPAMP CH5 0110 AIN3 AIN3 AIN3 CH6 0111 AIN3_OPAMP AIN3_OPAMP AIN3_OPAMP CH7 1000 AIN4 AIN4 AIN4 CH8 1001 AIN5 AIN5 AIN5 CH9 1010 AIN6 AIN6 AIN6 CH10 1011 AIN7 AIN10 AIN13 CH11 1100 AIN8 AIN11 AIN14 CH12 1101 AIN9 AIN12 AIN15 CH13 1110 - - - CH14 1111 - - - CH15 PRELIMINARY 197 Z32F1281 Product Specification ADnCR1 12-Bit A/D Converter ADCn Control Register 1 ADC Control Registers are 16-bit registers. AD0CR1=0x4000_B008, AD1CR1=0x4000_B108, AD2CR1=0x4000_B208 12 11 10 9 8 7 6 5 4 3 2 STSEL 0 0x00 1 0 0 0x00 RW RW RW RW RW RW ADCPDA CLKINVT 13 EXTCLK 14 ADCPD 15 CLKDIV ADnCR2 15 ADCPDA 14 8 CLKDIV[6:0] 7 ADCPD 6 EXTCLK 5 CLKINVT 4 0 STSEL[4:0] 1 0 ADC R-DAC disable to save power Don’t set “1” here(it’s optional bit) ADC clock divider when EXTCLK is ‘0’. ADC clock = system clock/CLKDIV CLKDIV=0 : ADC clock=system clock CLKDIV=1 : ADC clock=stop ADC Power Down 0 – ADC normal mode 1 – ADC Power Down mode (no ADC conversion will occur) ADC Clock Select. Clear this bit if the ADC will use the System clock using the CLKDIV for the divider. Set this bit if the ADC is configured through MCCR4 in the SCU. 0 – Use System clock(CLKDIV enabled to provide divider) 1 – ADC clock is externally configured (MCCR4) Divided clock inversion(optional bit) 0 – duty ratio of divided clock is larger than 50% 1 – duty ratio of divided clock is less than 50% Sampling Time Selection ADC Sample & Hold circuit sampling time become (2 + STSEL[4:0]) ADCCLK cycles Minimum sampling time is 2 ADCCLK cycle When STSEL[4:0]=11111, sampling channel is always on. ADCn Control Register 2 The ADCn Control Register 2 is the ADC start register and is an 8-bit register. AD0CR2=0x4000_B020, AD1CR=0x4000_B120, AD2CR=0x4000_B220, 7 6 5 4 3 2 1 ASTOP 0 0 0 ASTART 0 0 W PS034504-0617 0 0 0 0 RW 4 ASTOP 0 1 0 ASTART 0 1 No ADC conversion stop (will be clear next @ADC clock) This will stop the continuous and burst conversions. If ASTOP set after conversion cycle start, present conversion would be completed. No ADC conversion ADC conversion start (will be clear next @ADC clock) ADCEN should be “1” to start ADC PRELIMINARY 198 Z32F1281 Product Specification ADnTRG0 12-Bit A/D Converter ADC Trigger 0 Channel Register The ADC Trigger 0 registers are 32-bit registers. AD0TRG0=0x4000_B00C, AD1TRG0=0x4000_B10C, AD2TRG0=0x4000_B20C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 9 8 7 6 5 4 3 2 1 TRG0EN MP0TRG6 MP0TRG5 MP0TRG4 MP0TRG3 MP0TRG2 MP0TRG1 0x00 0x0 0x0 0x0 0x0 0x0 0x0 RW RW RW RW RW RW RW 0 29 24 TRG0EN Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 23 20 19 16 15 12 11 8 7 4 3 0 PS034504-0617 MP0TRG6 MP0TRG5 MP0TRG4 MP0TRG3 MP0TRG2 MP0TRG1 0 0 – MP0TRG6 disable 1 – MP0TRG6 enable 0 – MP0TRG5 disable 1 – MP0TRG5 enable 0 – MP0TRG4 disable 1 – MP0TRG4 enable 0 – MP0TRG3 disable 1 – MP0TRG3 enable 0 – MP0TRG2 disable 1 – MP0TRG2 enable 0 – MP0TRG1 disable 1 – MP0TRG1 enable ADC trigger channel number for MP0ATR6 trigger (Channel number 14 and 15 are prohibited) ADC trigger channel number for MP0ATR5 trigger (Channel number 14 and 15 are prohibited) ADC trigger channel number for MP0ATR4 trigger (Channel number 14 and 15 are prohibited) ADC trigger channel number for MP0ATR3 trigger (Channel number 14 and 15 are prohibited) ADC trigger channel number for MP0ATR2 trigger (Channel number 14 and 15 are prohibited) ADC trigger channel number for MP0ATR1 trigger (Channel number 14 and 15 are prohibited) PRELIMINARY 199 Z32F1281 Product Specification ADnTRG1 12-Bit A/D Converter ADC Trigger 1 Channel Register ADC Trigger 1 registers are 32-bit registers. AD0TRG1=0x4000_B010, AD1TRG1=0x4000_B110, AD2TRG1=0x4000_B210 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 9 8 7 6 5 4 3 2 1 TRG1EN MP1TRG6 MP1TRG5 MP1TRG4 MP1TRG3 MP1TRG2 MP1TRG1 0x00 0x0 0x0 0x0 0x0 0x0 0x0 RW RW RW RW RW RW RW 0 29 24 TRG1EN Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 23 20 19 16 15 12 11 8 7 4 3 0 PS034504-0617 MP1TRG6 MP1TRG5 MP1TRG4 MP1TRG3 MP1TRG2 MP1TRG1 0 0 – MP1TRG6 disable 1 – MP1TRG6 enable 0 – MP1TRG5 disable 1 – MP1TRG5 enable 0 – MP1TRG4 disable 1 – MP1TRG4 enable 0 – MP1TRG3 disable 1 – MP1TRG3 enable 0 – MP1TRG2 disable 1 – MP1TRG2 enable 0 – MP1TRG1 disable 1 – MP1TRG1 enable ADC trigger channel number by MP1ATR6 trigger (Channel number 14 and 15 are prohibited) ADC trigger channel number by MP1ATR5 trigger (Channel number 14 and 15 are prohibited) ADC trigger channel number by MP1ATR4 trigger (Channel number 14 and 15 are prohibited) ADC trigger channel number by MP1ATR3 trigger (Channel number 14 and 15 are prohibited) ADC trigger channel number by MP1ATR2 trigger (Channel number 14 and 15 are prohibited) ADC trigger channel number by MP1ATR1 trigger (Channel number 14 and 15 are prohibited) PRELIMINARY 200 Z32F1281 Product Specification ADnTRG2 12-Bit A/D Converter ADC Trigger 2 Channel Register ADC Trigger 2 registers are 32-bit registers. AD0TRG2=0x4000_B014, AD1TRG2=0x4000_B114, AD2TRG2=0x4000_B214 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 0 0 0 0 0 0 11 8 7 4 3 0 PS034504-0617 0 0 0 0 EXTCH T1CH T0CH 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 EXTCH T1CH T0CH 0x0 0x0 0x0 RW RW RW 0 ADC trigger channel number by External Trigger (Channel number 14 and 15 are prohibited) ADC trigger channel number by TIMER1 trigger (Channel number 14 and 15 are prohibited) ADC trigger channel number for TIMER0 trigger (Channel number 14 and 15 are prohibited) PRELIMINARY 201 Z32F1281 Product Specification ADnBCSR 12-Bit A/D Converter ADC Burst Mode Channel Select The ADC Burst Mode Channel Select Register is a 32-bit register. AD0BCSR=0x4000_B018, AD1BCSR=0x4000_B118, AD2BCSR=0x4000_B218 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BST8CH BST7CH BST6CH BST5CH BST4CH BST3CH BST2CH BST1CH 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 RW RW RW RW RW RW RW RW 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 PS034504-0617 BST8CH 8th conversion channel selection in burst mode BST7CH 7th conversion channel selection in burst mode BST6CH 6th conversion channel selection in burst mode BST5CH 5th conversion channel selection in burst mode BST4CH 4th conversion channel selection in burst mode BST3CH 3rd conversion channel selection in burst mode BST2CH 2nd conversion channel selection in burst mode BST1CH 1st conversion channel selection in burst mode PRELIMINARY 0 202 Z32F1281 Product Specification ADnSR 12-Bit A/D Converter ADCn Status Register The ADC Status Register is a 32-bit register. AD0SR=0x4000_B024, AD1SR=0x4000_B124, AD2SR=0x4000_B224 TIRQ CIRQ SIRQ 0 BIRQ 1 DMAIRQ 2 DOVRUN 3 0x00 0x0 0 000 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R PS034504-0617 4 ABUSY 0 5 ADEND 0 6 BSTAT 0x00 7 TRG 0 8 ADCH 0 9 MPWM0TRG MPWM1TRG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 29 24 21 16 15 12 11 MPWM1TRG 10 8 7 BSTAT 6 ABUSY 5 DOVRUN 4 DMAIRQ 3 TIRQ 2 BIRQ 1 CIRQ 0 SIRQ MPWM0TRG ADCH TRG ADEND This is only Test which MPWM triggered the ADC reading This is only Test which MPWM1 triggered the ADC reading ADC channel bits of present operation Trigger event status TRG bit set @trigger_event and clear @EOC(end of conversion) Burst mode operation count status ADC conversion end flag (will be reset @next ADC START). ADC conversion busy flag – Conversion in process. Note: this will remain high during burst and continuous modes. DMA overrun flag (not interrupt) (DMA ACK didn’t come until end of next conversion) DMA done received (1: DMA transfer is completed) Write “1” to clear flag ADC Trigger interrupt flag (0: no int / 1: int occurred) Write “1” to clear flag ADC Burst interrupt flag (0: no int / 1: int occurred) Write “1” to clear flag ADC Continuous interrupt flag (0: no int / 1: int occurred) Write “1” to clear flag ADC Single interrupt flag (0: no int / 1: int occurred) Write “1” to clear flag. Use this bit to identify when the ADC conversion data is ready after starting a conversion with the ASTART bit. PRELIMINARY 203 Z32F1281 Product Specification ADnIER 12-Bit A/D Converter Interrupt Enable Register ADC interrupt enable register. Individual interrupt sources can be enabled by writing a 1. AD0IER=0x4000_B028, AD1IER=0x4000_B128, AD2IER=0x4000_B228, 7 6 0 5 0 0 ADnDDR 4 DIEN 3 2 1 0 TIEN BIEN CIEN SIEN 4 3 2 1 0 DIEN TIEN BIEN CIEN SIEN 0 0 0 0 0 RW RW RW RW RW DMA done interrupt enable 0: interrupt disable 1: interrupt enable ADC trigger conversion interrupt enable ADC burst conversion interrupt enable ADC continuous conversion interrupt enable ADC single conversion interrupt enable ADC 0/1/2 DMA Data Register ADC DMA Data Registers are 16-bit registers. ADC conversion result register for DMA and single conversion (AD data of just completed conversion) AD0DDR=0x4000B02C, AD1DDR=0x4000B12C, AD2DDR=0x4000B22C 15 14 13 12 11 15 4 3 0 PS034504-0617 10 9 8 7 6 5 4 3 2 1 ADDMAR ADMACH 0x000 0x0 R R ADDMAR ADC conversion result data (12-bit) ADMACH ADC data channel indicator PRELIMINARY 0 204 Z32F1281 Product Specification ADnCCR 12-Bit A/D Converter ADC Channel Compare Control Register ADC Channel Compare Control Registers are 32-bit registers. AD0CCR=0x4000_B070, AD1CCR=0x4000_B170, AD2CCR=0x4000_B270 0 0 0 0 PS034504-0617 0 CVAL 0 0 000 0x000 8 7 6 5 4 3 2 1 0 0 0 0 0 RW 0 CCH 0 RW 0 LTE 0 R 0 9 RW COMPOUT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 COMPOUT 0 1 0 20 LTE 19 16 15 4 CCH If LTE condition is FALSE If LTE condition is TRUE (MPWM trigger source) Set compare output when AD conversion value is greater than compare value (CVAL) 1 Set compare output when AD conversion value is less than or equal to compare value(CVAL) Compare channel CVAL Compare value PRELIMINARY 205 Z32F1281 Product Specification 12-Bit A/D Converter Functional Description The PER2 and PCER2 registers must be configured to enable the ADC peripheral and the ADC peripheral clock. The ADC block provides the ability to convert an analog signal to a digital value. The ADC compares the input channel with the AVDD voltage and provides a 12-bit value. Voltage value = (ADC Reading / 4096) * AVDD voltage The ADC clock can be configured up to 22.5 MHz and be driven from any of the available clocks – System Clock, Ring OSC, Bus Clock, Int OSC, External OSC, or the PLL clock. There is a 6-bit divider available for the system clock (divider must be greater than 1) or the ADC clock can be configured in the MCCR4 register, which provides access to all clocks and the 8-bit divider. The clock is selected in the CR1 register (and optionally configured in the SCU MCCR4 register). The ADC takes 15 ADC clocks to complete one sample, starting with a single clock, followed by a sample and hold time (minimum of 2 ADC clocks) then 1 clock per bit (12 bits). To increase sample time, configure up to 511 clock sampling time (which would then take 511 + 15 = 526 ADC clocks per sample). The maximum ADC clock that can be used is calculated as: ADC Clock = 1.5Msps * (15 clocks per sample + Sample time) Example (Sampling time = 0): ADC clock = 1.5Msps * (15 clocks + 0) = 22.5 MHz In the above example, if the system clock was running at 72 MHz, the divider cannot be less than 4. The burst feature allows the programmer to retrieve multiple readings (up to 8) with only one start request. The ADC block automatically goes through all 8 and takes readings without intervention. This feature is best utilized with DMA to store the data. It is also possible to wait a specific time (up to 255 ADC clocks) before starting the next conversion. To use the burst feature, populate Burst channels 0-7 of the reading you wish to take. They can be the same or different channels. Provide the count of burst operations (number of channels that have been assigned) in the burst count, then modify the ADCMOD to specify burst mode. If desired, populate the BWAIT value with the number of clocks you wish to have between readings and set the BWAITEN bit. You can either manually start it by setting the AStart bit or set a trigger to start it. BURST Mode Example: To take 3 readings of AN0 and AN2 for an average value, set the Burst channels as: BST1CH = 0x00 (AN0 is ADC Channel 0) BST2CH = 0x04 (AN2 is ADC Channel 4) BST3CH = 0x00 BST4CH = 0x04 BST5CH = 0x00 BST6CH = 0x04 Set the BSTCNT in the MR register to 0x06 Set the ADCMOD in the MR register to 0x03 Set the AStart Bit in the CR2 register to take the readings. It is possible to trigger the burst reading to take the readings when an event occurs. PS034504-0617 PRELIMINARY 206 Z32F1281 Product Specification 12-Bit A/D Converter General ADC Setup Procedure 1. Allow the modification of the I/O pins to use the ADC inputs needed by writing the unlock sequence as described in Port Control Unit (PCU), no pullups enabled. 2. Enable the ADC peripherals needed in the PER2 register. 3. Enable the ADC peripheral clock in the PCER2 register. 4. Select the alternating function for the ADC inputs (Port n MUX registers). 5. Configure the ADC mode in the ADCnMODE register and enabled the channel ADCn. 6. Configure the ADCnCR1 register and write an appropriate clock divider value. 7. Configure TRG0 to enable or disable ADC trigger sources. 8. Configure the ADC Burst Mode (ADnBCSR) register for ADC operation with burst mode described below. 9. Configure the ADnIER ADC interrupt control register. ADC Single Mode Timing Diagram ADC conversion is started when ADCn.CR.ASTART is written as ‘1’ in single conversion mode. After ADCnCR.ASTART is set, SOC (start of Conversion) will be activated in 2 ADC clocks; ADCn.SR.SIRQ will be set in 1 ADC clock and 2 PCLKs after the end of conversion. Figure 16.3. ADC Single Mode Timing Diagram ADC Continuous Mode Timing Diagram The ADC conversion in burst mode is almost the same as continuous mode. Burst mode has ADnCR.BWAIT. BWAIT in 8-bit register and can delay the time of SOC. Burst wait counter (BWAIT) in ADC clock domain. ADnSR.BIRQ is set as 1 after the last burst operation; see Figure 16.4 PS034504-0617 PRELIMINARY 207 Z32F1281 Product Specification 12-Bit A/D Converter Figure 16.4. ADC Continuous Mode Timing ADC Burst Mode Timing Diagram The ADC conversion in burst mode is almost same as in continuous mode. Burst mode has ADnCR.BWAIT. BWAIT in 8-bit register and can delay the time of SOC. Burst wait counter (BWAIT) in the ADC clock domain. ADnSR.BIRQ is set as 1 after the last burst operation; see Figure 16.5 Figure 16.6. ADC Burst Mode Timing (when ADCn.MR.BWAIT = ‘8’h3’ and BSTCNT = ‘3’b111’) PS034504-0617 PRELIMINARY 208 Z32F1281 Product Specification Analog Front End 17. Analog Front End Introduction Analog Front End (AFE) is the interface controller for OPAMPs and comparators. Features include:       4 OPAMPs 4 comparators OPAMP output can be connected with ADC or comparator Internal BGR reference for comparator Comparator output debounce function Level and edge interrupt mode support for comparator Figure 17.1 shows a block diagram of the AFE. OPAMP0 AIN0 To ADC CH1 OPAMP1 AIN1 To ADC CH3 OPAMP2 AIN2 To ADC CH5 OPAMP3 AIN3 To ADC CH7 COMP0 Debounce + COMP1 Debounce + COMP2 Debounce + - COMP_REF COMP3 - COMP3_REF Debounce + IPOL C0IRQ PPOL COMP0_PWM (protection) IPOL C1IRQ PPOL COMP1_PWM (protection) IPOL C2IRQ PPOL COMP2_PWM (protection) IPOL C3IRQ PPOL COMP3_PWM (protection) Internal BGR Figure 17.1. Analog Front End Block Diagram PS034504-0617 PRELIMINARY 209 Z32F1281 Product Specification Analog Front End Pin Description Table 17.1. External Signal PIN NAME TYPE DESCRIPTION AVDD P Analog Power (3.0V~VDD) AVSS P Analog GND CP0 A Comparator Input 0 CP1 A Comparator Input 1 CP2 A Comparator Input 2 CP3 A Comparator Input 3 CREF0 A Comparator Reference Input 0 CREF1 A Comparator Reference Input 1 Registers The base address of AFE is listed in Table 17.2. Table 17.2. AFE Base Address BASE ADDRESS AFE 0x4000_B300 Table 17.3 shows the register memory map. Table 17.3. AFE Register Map PS034504-0617 Name Offset R/W Description Reset OPA0CR 0x0000 R/W AFE OPAMP 0 control register 0x00 OPA1CR 0x0004 R/W AFE OPAMP 1 control register 0x00 OPA2CR 0x0008 R/W AFE OPAMP 2 control register 0x00 OPA3CR 0x000C R/W AFE OPAMP 3 control register 0x00 CMP0CR 0x0020 R/W AFE Comparator 0 control register 0x10 CMP1CR 0x0024 R/W AFE Comparator 1 control register 0x10 CMP2CR 0x0028 R/W AFE Comparator 2 control register 0x10 CMP3CR 0x002C R/W AFE Comparator 3 control register 0x10 CMPDBR 0x0030 R/W AFE Comparator debounce register 0x00 CMPICR 0x0034 R/W AFE Comparator interrupt control 0x00 CMPIER 0x0038 R/W AFE Comparator interrupt enable 0x00 CMPSR 0x003C R AFE Comparator status register 0x00 PRELIMINARY 210 Z32F1281 Product Specification OPAnCR Analog Front End OPAMP 0/1/2/3 Control Registers Analog-front-end OPAMP 0/1/2/3 Control Registers are 8-bit registers. All four registers (AFEOPA0~AFEOPA3) have the same functions. OPA0CR=0x4000_B300, OPA1CR =0x4000_B304 OPA2CR =0x4000_B308, OPA3CR =0x4000_B30C 7 6 5 0 0 0 CMPnCR 4 4 OPAEN 3 0 GAIN 3 2 1 OPAEN GAIN 0 0x0 RW RW 0 1 0000 0001 0010 0011 0100 0101 0110 0111 OPAMP n Disable OPAMP n Enable Gain = 2.19 Gain = 2.33 Gain = 2.5 Gain = 2.69 Gain = 2.92 Gain = 3.18 Gain = 3.5 Gain = 3.89 1000 1001 1010 1011 1100 1101 1110 1111 0 Gain = 4.37 Gain = 5.0 Gain = 5.83 Gain = 7.0 Gain = 8.74 Reserved Reserved Gain = 1.00 Comparator 0/1/2/3 Control Register Analog-front-end Comparator0/1/2/3 Control Registers (AFECOMP0~AFECOMP3) have the same functions. are 8-bit registers. All four registers CMP0CR=0x4000_B320,CMP1CR =0x4000_B324 CMP2CR =0x4000_B328, CMP3CR =0x4000_B32C 7 6 5 0 0 0 4 3 2 0 0 CMPEN 1 RW 4 CMPEN 1 CINSEL 0 1 0 1 0 REFSEL 0 1 1 0 CINSEL REFSEL 0 0 RW RW Comparator 0~3 Enable Comparator 0~3 Disable Comparator input selection Input from OPAMP 0~3 each Input from external pin (see pin mux table) Comparator reference selection Reserved REF input from external pin (see pin mux table) When OPAMP is disabled, the OPAMP output is unknown (floating). Therefore, the user should set (write 1) CINSELx to choose the external input when OPAMP is an inactive state. PS034504-0617 PRELIMINARY 211 Z32F1281 Product Specification CMPDBR Analog Front End Comparator Debounce Register The Analog Front End Comparator Debounce Register is a 32-bit register. CMPDBR=0x4000_B330 0 0 0 0 CMPICR 5 4 3 2 1 C0DBNC 0 6 C1DBNC 0 7 C2DBNC 0 8 C3DBNC 0 9 DBNCTB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0x00 0x0 0x0 0x0 0x0 RW RW RW RW RW 23 16 DBNCTB[3:0] 15 0 CxDBNC[4:0] 0 Debounce time base counter System clock/(DBNCTB *2) becomes shift clock of debounce logic When DBNCTB is 0, system clock would be debounce clock. Debounce shift Selection When it is 0x0, debounce function is disable Shift number of debounce logic is (CxDBNC + 1) when CxDBNC is more than 1. Comparator Interrupt Control Register The Analog Front End Comparator Interrupt Control Register is a 16-bit register. CMPICR=0x4000_B334 3 2 1 0 C0IMOD 4 C1IMOD 5 C2IMOD 6 C3IMOD 7 IPOL0 8 IPOL1 9 IPOL2 10 IPOL3 11 PPOL0 12 PPOL1 13 PPOL2 14 PPOL3 15 - - - - - - - - 00 00 00 00 R R R R R R R R RW RW RW RW 15 14 13 12 11 10 9 8 3 2 1 0 PS034504-0617 PPOL3 PPOL2 PPOL1 PPOL0 IPOL3 IPOL2 IPOL1 IPOL0 C3IMODE C2IMODE C1IMODE C0IMODE 0 1 0 1 00 01 10 11 Comparator outs for PWM protection will not be inverted Comparator outs for PWM protection will be inverted (if debounce is enable, debounced output will be inverted) When comparator output is high, IRQ bit is set (CxIMODE = 00) When comparator output is low, IRQ bit is set (CxIMODE = 00) Comparator interrupt mode IRQ at level output IRQ at rising edge of comparator output IRQ at falling edge of comparator output IRQ at both edge of comparator output PRELIMINARY 212 Z32F1281 Product Specification CMPIER Analog Front End Comparator Interrupt Enable Register The Analog Front End Interrupt Enable Register is an 8-bit register. CMP0CR=0x4000_B338 7 6 0 5 0 4 0 CMPSR 3 2 1 0 CMP3IE CMP2IE CMP1IE CMP0IE 0 0 0 0 RW RW RW RW 0 3 CMP3IE 2 CMP2IE 1 CMP1IE 0 CMP0IE AFE comparator 3 interrupt enable 0 –interrupt disable 1 –interrupt enable AFE comparator 2 interrupt enable 0 –interrupt disable 1 –interrupt enable AFE comparator 1 interrupt enable 0 –interrupt disable 1 –interrupt enable AFE comparator 0 interrupt enable 0 –interrupt disable 1 –interrupt enable Comparator Status Register The Analog Front End Status Register is a 16-bit register. - - - - - - R R R R R R R R 15 12 11 8 3 0 PS034504-0617 C3RAW C2RAW C1RAW C0RAW C3OUT C2OUT C1OUT C0OUT C3IRQ C3IRQ C2IRQ C0IRQ 5 4 3 C0IRQ - 6 C1IRQ - 7 C2IRQ C0OUT 8 C1OUT 9 C2OUT 10 C3OUT 11 C0RAW 12 C1RAW 13 C2RAW 14 C3RAW 15 C3IRQ CMPSR=0x4000_B33C 2 1 0 0 0 0 0 0 0 0 0 RC1 RC1 RC1 RC1 AFE comparator raw outputs These values come from comparator output pin (before debouncing) AFE comparator output monitor bit These values are debounced outputs. AFE comparator interrupt flag (0: no int / 1: int occurred) Write “1” to clear flag PRELIMINARY 213 Z32F1281 Product Specification Analog Front End Functional Description The PER2 and PCER2 registers must be configured to enable the AFE peripheral and the AFE peripheral clock. PS034504-0617 PRELIMINARY 214 Z32F1281 Product Specification Electrical Characteristics 18. Electrical Characteristics DC Characteristics Absolute Maximum Ratings Absolute maximum ratings are limiting values of operating and environmental conditions which should not be exceeded under the worst possible conditions. Table 18.1. Absolute Maximum Ratings Parameter Symbol min max unit Power Supply (VDD) VDD -0.5 +6 V Analog Power Supply (AVDD) AVDD -0.5 +6 V Input High Voltage - VDD+0.5 V Input Low Voltage VSS–0.5 - V IOL - 20 mA 80-pin ∑ IOL - 100 64-pin ∑ IOH - 80 IOH - 10 80-pin ∑ IOH - 100 64-pin ∑ IOH - 80 - 200 mW 0.4 10 MHz - 72 MHz Output Low Current per pin Output Low Current Total mA Output Low Current per pin Output Low Current Total mA mA Power consumption Input Main Clock Range Operating Frequency Storage Temperature Tst -55 +125 ℃ Operating Temperature Top -40 +85 ℃ PS034504-0617 PRELIMINARY 215 Z32F1281 Product Specification Electrical Characteristics DC Characteristics Table 18.2. Recommended Operating Conditions Parameter Symbol Supply Voltage VDD Condition Min Typ. 3.0 Max unit 5.5 V 5.5 V 8 MHz A V D D Supply Voltage 3.0 MOSC Operating Frequency FREQ Operating Temperature 4 INTOSC PLL Top Top 5.0 20 MHz 4 80 MHz -40 +85 ℃ Table 18.3. DC Electrical Characteristics (VDD = +5V, Ta = 25 ℃) Parameter Symbol Input Low Voltage VIL Condition V Input High Voltage I Min Typ. Max unit Schmitt input - - 0.2VDD V Schmitt input 0.8VDD - - V - - VSS+0.5 V VDD–0.5 - 10 H Output Low Voltage VOL IOL = 10mA Output High Voltage VOH IOH = 3mA Output Low Current IOL - - Output High Current IOH -3 - Input High Leakage IIH Input Low Leakage IIL Pull-up Resister PS034504-0617 RPU V mA mA 4 uA 70 kΩ -4 Rmax:VD D=3.0V Rmin:VD D=5V 30 PRELIMINARY - 216 Z32F1281 Product Specification Electrical Characteristics Current Consumption Table 18.4. Current Consumption in Each Mode (Temperature: +25℃) Parameter Symbol Normal Operation IDDNORMAL IDDSLEEP Sleep Mode Condition Min Typ. Max unit ROSC=RUN IOSC20=RUN MXOSC=8MHz HCLK=72MHz - 35 - mA ROSC=RUN IOSC20=RUN MXOSC=STOP HCLK =RUN - 3 - mA POR Electrical Characteristics Table 18.5. POR Electrical Characteristics (Temperature: -40 ~ +85℃) Parameter Symbol Operating Voltage VDD18 Operating Current IDDPoR POR Set Level POR Reset Level Condition Min Typ. Max unit 1.6 1.8 2.0 V Typ.