ZNEO32! Family of Microcontrollers
Z32F3841 MCU
Product Specification
PS034603-0617
PRELIMINARY
Copyright ©2017 Zilog®, Inc. All rights reserved.
www.zilog.com
Z32F3841 MCU
Product Specification
ii
Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
LIFE SUPPORT POLICY
ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
©2017 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
ZNEO32! is a trademark or registered trademark of Zilog, Inc. All other product or service names are the
property of their respective owners.
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Z32F3841 MCU
Product Specification
iii
Revision History
Each instance in this document’s revision history reflects a change from its previous edition. For more details, refer to the corresponding page(s) or appropriate links furnished in
the table below.
Revision
Level
Description
Page
Jun
2017
03
Updated part numbers to include the Cortex M identifier.
All
Mar
2016
02
Update to reflect new part, revision B (0x0002);
Added timing information for most of the peripherals; corrected typos.
All
Dec
2015
01
Original issue.
Date
PS034603-0617
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Revision History
Z32F3841 Product Specification
Overview
1. Overview
Introduction
Zilog’s Z32F3841 MCU, a member of the ZNEO32! Family of microcontrollers, is a cost-effective and highperformance 32-bit microcontroller. The Z32F3841 MCU provides 3-phase PWM generator units which are
suitable for inverter bridges, including motor drive systems. Two built-in channels of these generators control
two inverter bridges simultaneously.
Two 12-bit high speed ADC units with 16-channel analog multiplexed inputs support feedback retrieval from
the inverter bridge. The Z32F3841 MCU can control up to two inverter motors or one inverter motor and the
Power Factor Correction (PFC) function simultaneously.
Figure 1.1 shows a block diagram of the Z32F3841 MCU.
UART x 4
SYSCON
WDT
FLASHROM
(384KB)
FRT
SPI x 2
Cortex-M3
Max 75MHz
2
Flash Controller
I Cx2
JTAG/SWD
SRAM
(16KB)
3-Phase
MPWM x 2
GPIOs
IOSC
(20MHz)
Sub OSC
PLL
(32KHz)
(Max 80MHz)
Ext. OSC
(8MHz Xtal)
TIMER x 10
POR
DMAC
ADC Interface
LVD
VDC
12-bit ADC
1.5Msps
12-bit ADC
1.5Msps
5V-to-1.8V
Figure 1.1. Block Diagram
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Z32F3841 Product Specification
Overview
Z32F38412ALS
Figure 1.2. Pin Layout (LQFP-100)
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Z32F3841 Product Specification
Overview
Product Features
The Z32F3841 MCU includes the following features:
High performance low-power Cortex-M3 core
384KB code Flash memory with cache function
16 KB SRAM
3-Phase PWM with ADC triggering function
o 2 Channels
1.5 MSPS high-speed ADC with sequential conversion
o 2 units with 16 Channel input
System fail-safe function by clock monitoring
o XTAL OSC fail monitoring function
o System clock Fail monitoring function
Internal clock sources
o Internal ring oscillator (1 MHz ±50%)
o Internal oscillator clock (20 MHz ±3%)
Internal Phase Lock Loop (PLL) up to 80Mhz
External clock sources
o External crystal oscillator (4~16 MHz)
o External sub oscillator (32 kHz)
Watchdog timer
10 general purpose timer channels
o Timer/capture/PWM mode
Free run timer
Various external communication ports:
o 4 UARTs
2
o 2 I Cs
o 2 SPIs
High current driving port for UART photo couplers
Direct Memory Access (DMA) controller with 8 channels
Debug and emergency stop function
JTAG and SWD debugger
Package: LQFP-100 (0.5mm pitch)
Industrial grade operating temperature (– 40 ~ +85°C)
o
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Z32F3841 Product Specification
Overview
Architecture
Block Diagram
Figure 1.3 shows the Z32F3841 MCU’s internal block diagram.
JTAG
SWD
NMI
DEBUG
NVIC
Cortex-M3
(Max. 75MHz)
CODE FLASH
(384KB)
SRAM
(16KB)
POR
VDC
AHB BUS Matrix
LVD
IOSC20
DMAC
APB
RingOSC
MainOSC
PLL
SCU
UART (4)
WDT
SPI (2)
SubOSC
FRT
I2C (2)
16-bit TIMER
(10)
12-bit ADC
2-unit
PA
PB
PC
3-Phase PWM
2-unit
PD
PE
PF
Figure1.3. Internal Block Diagram
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Z32F3841 Product Specification
Overview
Functional Description
The following section provides an overview of the features of the Z32F3841 microcontroller.
ARM Cortex-M3
The ARM-powered Cortex-M3 Core based on v7M architecture is optimized for small size and low power
system. An on core system timer (SYSTICK) provides a simple 24-bit timer, that enables easy management of
the system operation. The thumb-compatible Thumb-2 only instruction set processor core makes code highdensity. Hardware division and single-cycle multiplication is present. Integrated Nested Vectored Interrupt
Controller (NVIC) provides deterministic interrupt handling. Full featured debug solutions are provided – JTAG
and SWD, FPB, DWT, ITM and TPIU. It includes a maximum 72 MHz operating frequency with zero wait
execution.
Nested Vector-Interrupt Controller (NVIC)
The ARM Nested Vectored Interrupt Controller (NVIC) on the ARM Cortex-M3 core is included, which handles
all internal and external exceptions. When an interrupt condition is detected, the processor state is
automatically stored to the stack and automatically restored from the stack at the end of the interrupt service
routine. The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The
processor supports tail-chaining, which allows back-to-back interrupts to be performed without the overhead
of state saving and restoring.
384 KB Internal Code Flash Memory
The Z32F3841 MCU provides internal 384 KB code Flash memory and its controller. This is enough to
program the motor algorithm and generally control the system. Self-programming is available and ISP and
JTAG programming is also supported in boot or debugging mode.
Instruction and data cache buffer are present and overcome the low bandwidth Flash memory. The CPU can
execute from Flash memory with zero wait state up to 72 MHz bus frequency.
16 KB Zero-wait Internal SRAM
On chip 16 KB zero-wait SRAM can be used for working memory space and program code can be loaded on
this SRAM.
Boot Logic
The smart boot logic supports Flash programming. The Z32F3841 MCU can be accessed by an external boot
pin and UART and SPI programming are available in boot mode.
System Control Unit (SCU)
The SCU block manages internal power, clock, reset, and operation mode. It also controls analog blocks
(INTOSC, VDC and BOD).
32-bit Watchdog Timer (WDT)
The watchdog timer performs the system monitoring function. It generates an internal reset or interrupt when it
notices abnormal status of the system.
Multi-purpose 16-bit Timer
10 16-bit general purpose timers channels support the following functions:
Periodic timer mode
Counter mode
PWM mode
Capture mode
Free Run Timer
The 32-bit Free run timer has multiple clock sources (XTAL/16, IOSC/16, SXTAL).
Motor PWM Generator
Two channels of the 3-phase PWM generator are implemented. A 16-bit up/down counter with prescaler
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Z32F3841 Product Specification
Overview
supports both the triangular and saw tooth waveform.
The PWM generates an internal ADC trigger signal to measure the signal on time. Dead time insertion and
emergency stop functionality ensure that the chip and system operate under safe conditions.
Serial Peripheral Interface (SPI)
Synchronous serial communication is provided with the SPI block. The Z32F3841 MCU has 2-channel SPI
modules. It includes a DMA function supported by the DMA controller. Transfer data is moved to/from the
memory area without CPU operation. Boot mode uses this SPI block to download the Flash program.
2
Inter-Integrated Circuit Interface (I C)
2
2
The Z32F3841 MCU has a 2-channel I C block and it supports up to 400 KHz I C communication. Master and
slave modes are supported.
Universal Asynchronous Receiver/Transmitter (UART)
The Z32F3841 MCU has a 4-channel UART block. For accurate baud rate control, the fractional baud rate
generator is provided. It includes a DMA function supported by the DMA controller. Transfer data is moved
to/from the memory area without CPU operation.
General PORT I/Os
16-bit PA, PB, PC, PD, PE ports and 6-bit PF are available and provide multiple functionality:
General I/O port
Independent bit set/clear function
External interrupt input port
Pull-up/open-drain
On chip debounce filter
12-bit Analog-to-Digital Converter (ADC)
2 built-in ADCs can convert analog signals up to 1usec conversion rate. A 16-channel analog mux provides
various combinations from external analog signals.
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Pin Description
The pin configurations are shown in Table 1.1. 16 pins are reserved for power/ground pair and dedicated pins.
Table1.1. Pin Description
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
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Pin Name
Type
Description
GND
P
Ground
PD2
MOSI1
PD3*
MISO1
PE0
TXD1
PE1
RXD1
PE2
T4I
T3O
PF2
IOUS
I/O
IOUS
I/O
IOUS
Output
IOUS
Input
IOUS
I/O
I/O
IOUS
PORT D Bit 2 Input/Output
SPI Channel 1 Master Out / Slave In
PORT D Bit 3 Input/Output
SPI Channel 1 Master In / Slave Out
PORT E Bit 0 input/Output
UART Channel 1 TXD output
PORT E Bit 1 input/Output
UART Channel 1 RXD input
PORT E Bit 2 input/Output
Timer 4 Input
Timer 3 Output
PORT F Bit 2 input/Output
AN20
IA
Analog Input 20
PF3
IOUS
PORT F Bit 3 input/Output
AN21
IA
Analog Input 21
PA0*
IOUS
PORT A Bit 0 Input/Output
AN0
PA1*
AN1
PA2*
AN2
PA3*
AN3
PA4*
T0IO
AN4
PA5*
T1IO
AN5
PA6*
T2IO
AN6
PA7*
T3IO
AN7
AGND
AVDD
PA8*
AN8
PA9*
AN9
IA
IOUS
IA
IOUS
IA
IOUS
IA
IOUS
IO
IA
IOUS
IO
IA
IOUS
IO
IA
IOUS
IO
IA
P
P
IOUS
IA
IOUS
IA
Analog Input 0
PORT A Bit 1 Input/Output
Analog Input1
PORT A Bit 2 Input/Output
Analog Input 2
PORT A Bit 3 Input/Output
Analog Input 3
PORT A Bit 4 Input/Output
Timer 0 Input/Output
Analog Input 4
PORT A Bit 5 Input/Output
Timer 1 Input/Output
Analog Input 5
PORT A Bit 6 Input/Output
Timer 2 Input/Output
Analog Input 6
PORT A Bit 7 Input/Output
Timer 3 Input/Output
Analog Input 7
Analog Ground
Analog VDD
PORT A Bit 8 Input/Output
Analog Input 8
PORT A Bit 9 Input/Output
Analog Input 9
PRELIMINARY
Remark
2nd function
2nd function
2nd function
2nd function
3rd function
3rd function
3rd function
3rd function
7
Z32F3841 Product Specification
Overview
PA10*
AN10
PA11*
AN11
PA12*
SS0
AN12
PD4
SCL1
AN16
PD5
SDA1
AN17
GND
VDD
PD6*
TXD2
AN18
PD7*
RXD2
AN19
PA13*
SCK0
AN13
PA14*
MOSI0
AN14
IOUS
IA
IOUS
IA
IOUS
I/O
IA
IOUS
Output
IA
IOUS
Output
IA
P
P
IOUS
Output
IA
IOUS
Input
IA
IOUS
I/O
IA
IOUS
I/O
IA
PORT A Bit 10 Input/Output
Analog Input 10
PORT A Bit 10 Input/Output
Analog Input 11
PORT A Bit 12 Input/Output
SPI Channel 0 Slave Select signal
Analog Input 12
PORT D Bit 4 Input/Output
I2C Channel 1 SCL In/Out
Analog Input 16
PORT D Bit 5 Input/Ouput
I2C Channel 1 SDA In/Out
Analog Input 17
Ground
VDD
PORT D Bit 6 Input/Ouput
UART Channel 2 TxD Output
Analog Input 18
PORT D Bit 7 Input/Ouput
UART Channel 2 RxD Input
Analog Input 19
PORT A Bit 13 Input/Output
SPI Channel 0 Clock Input/Output
Analog Input 13
PORT A Bit 14 Input/Output
SPI Channel 0 Output(M)/Input(S) Data signal
Analog Input 14
PA15*
IOUS
PORT A Bit 15 Input/Output
MISO0
AN15
I/O
IA
SPI Channel 0 Input(M)/Output(S) Data signal
Analog Input 15
PB0
IOUS
PORT B Bit 0 Input/Output
MP0UH
Output
PWM0 UH Output
PB1
IOUS
PORT B Bit 1 Input/Output
MP0UL
PB2
MP0VH
PB3
MP0VL
PF4
PF5
PE3
Output
IOUS
Output
IOUS
Output
IOUS
IOUS
IOUS
PWM0 UL Output
PORT B Bit 0 Input/Output
PWM0 VH Output
PORT B Bit 1 Input/Output
PWM0 VL Output
PORT F Bit 4 Input/Output
PORT F Bit 5 Input/Output
PORT E Bit 3 Input/Output
SCL0
Output
I2C Channel 0 SCL In/Out
PE4
IOUS
PORT E Bit 4 Input/Output
SDA0
Output
I2C Channel 0 SDA In/Out
PE5
IOUS
PORT E Bit 5 Input/Output
T5IO
I/O
Timer 5 Input/Output
42
TEST
Input
Test-mode Input (Always ‘L’)
Pull-down
43
SCANMD
Input
Scan-mode Input (Always ‘L’)
Pull-down
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
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Open-drain
Open-drain
Open-drain
2nd function
Open-drain
2nd function
8
Z32F3841 Product Specification
PB4
IOUS
PORT B Bit 4 Input/Output
MP0WH
T9IO
Output
I/O
PWM0 WH Output
Timer 9 Input/Output
PB5
MP0WL
T9IO
PB6
PRTIN0
WDTO
IOUS
Output
I/O
IOUS
Input
Output
PORT B Bit 5 Input/Output
PWM0 WL Output
Timer 9 Input/Output
PORT B Bit 6 Input/Output
PWM0 Protection Input signal 0
WDT Output
PB7
IOUS
PORT B Bit 7 Input/Output
OVIN0
STBYO
PB8
PRTIN1
RXD3
PD8
WDTO
T6IO
PD9
STBYO
T7IO
GND
VDD
PB9
OVIN1
TXD3
PB10
Input
Output
IOUS
Input
Output
IOUS
Output
I/O
IOUS
Output
I/O
P
P
IOUS
Input
Output
IOUS
PWM0 Over-Current Input signal 1
Power-down mode indication signal
PORT B Bit 8 Input/Output
PWM1 Protection Input signal 0
UART Channel 3 RXD Input
PORT D Bit 8 Input/Output
WDT Output
Timer 6 Input/Output
PORT D Bit 9 Input/Output
Power-down mode indication signal
Timer 7 Input/Output
Ground
VDD
PORT B Bit 9 Input/Output
PWM1 Over-Current Input signal 1
UART Channel 3 TXD Output
PORT B Bit 10 Input/Output
MP1UH
Output
PWM Channel 1 UH Output
PB11
MP1UL
PB12
MP1VH
PB13
MP1VL
PB14
IOUS
Output
IOUS
Output
IOUS
Output
IOUS
PORT B Bit 11 Input/Output
PWM Channel 1 UL Output
PORT B Bit 12 Input/Output
PWM Channel 1 VH Output
PORT B Bit 13 Input/Output
PWM Channel 1 VL Output
PORT B Bit 14 Input/Output
MP1WH
Output
PWM Channel 1 WH Output
PB15
IOUS
PORT B Bit 15 Input/Output
MP1WL
Output
PWM Channel 1 WL Output
60
PF0
IOUS
PORT F Bit 0 Input/Output
61
PF1
IOUS
PORT F Bit 1 Input/Output
PC0
IOUS
PORT C Bit 0 Input/Output
TCK/SWCLK
Input
JTAG TCK, SWD Clock Input
RXD0
Input
UART Channel 0 RXD Input
PC1
IOUS
PORT C Bit 1 Input/Output
TMS/SWDIO
I/O
JTAG TMS, SWD Data Input/Output
TXD0
Input
UART Channel 0 TXD Output
PE6
IOUS
PORT E Bit 6 Input/Output
T5IO
I/O
Timer 5 Input/Output
PE7
IOUS
PORT E Bit 7 Input/Output
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
62
63
64
65
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Overview
2nd function
2nd function
2nd function
2nd function
2nd function
2nd function
9
Z32F3841 Product Specification
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
PS034603-0617
Overview
T6IO
I/O
Timer 6 Input/Output
PE8
IOUS
PORT E Bit 8 Input/Output
T7IO
PE9
I/O
IOUS
Timer 7 Input/Output
PORT E Bit 9 Input/Output
2nd function
T8IO
I/O
Timer 8 Input/Output
3rd function
PE10
T9IO
PD10
AD0SOC
T0IO
PD11
AD0EOC
T1IO
NMI
PD12
AD1SOC
T2IO
PD13
AD1EOC
T3IO
PC2
TDO/SWO
PC3
IOUS
I/O
IOUS
Output
IO
IOUS
Output
IO
Input
IOUS
Output
IO
IOUS
Output
IO
IOUS
Output
IOUS
PORT E Bit 10 Input/Output
Timer 9 Input/Output
PORT D Bit 10 Input/Output
ADC0 Start-of-Conversion
Timer 0 Input/Output
PORT D Bit 10 Input/Output
ADC0 End-of-Conversion
Timer 1 Input/Output
Non-maskable Interrupt Input
PORT D Bit 12 Input/Output
ADC1 Start-of-Conversion
Timer 2 Input/Output
PORT D Bit 13 Input/Output
ADC1 End-of-Conversion
Timer 3 Input/Output
PORT C Bit 2 Input/Output
JTAG TDO, SWO Output
PORT C Bit 3 Input/Output
TDI
GND
Input
P
JTAG TDI Input
Ground
VDD
PC4
nTRST
T0IO
PC5
RXD1
T1IO
PC6
TXD1
T2IO
PC7
SCL0
T3IO
PC8
SDA0
T4IO
PC9
P
IOUS
Input
IO
IOUS
Input
IO
IOUS
Output
IO
IOUS
IO
IO
IOUS
IO
IO
IOUS
VDD
PORT C Bit 4Input/Output
JTAG nTRST Input
Timer 0 Input/Output
PORT C Bit 5Input/Output
UART Channel 1 RXD Input
Timer 1 Input/Output
PORT C Bit 6Input/Output
UART Channel 1 TXD Output
Timer 2 Input/Output
PORT C Bit 7Input/Output
I2C Channel 0 SCL In/Out
Timer 3 Input/Output
PORT C Bit 8 Input/Output
I2C Channel 0 SDA In/Out
Timer 4 Input/Output
PORT C Bit 9 Input/Output
CLKO
T8IO
PC10
Output
IO
IOUS
System Clock Output
Timer 8 Input/Output
PORT C Bit 10 Input/Output
nRESET
PC11
BOOT
T8IO
PE11
Input
IOUS
Input
Input
IOUS
External Reset Input
PORT C Bit 11 Input/Output
Boot mode Selection Input
Timer 8 Input/Output
PORT E Bit 11 Input/Output
Pull-up
T0IO
IO
Timer 0 Input/Output/Phase-A Input
4st function
PRELIMINARY
2nd function
3rd function
3rd function
3rd function
3rd function
3rd function
2nd function
2nd function
2nd function
2nd function
2nd function
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Z32F3841 Product Specification
Overview
SCL1
PE12
T1IO
SDA1
PE13
T2IO
TXD2
PE14
IO
IOUS
IO
IO
IOUS
IO
Output
IOUS
I2C Channel 1 SCL Input/Output
PORT E Bit 12 Input/Output
Timer 1 Input/Output/Phase-B Input
I2C Channel 1 SDA input/Output
PORT E Bit 13 Input/Output
Timer 2 Input/Output/Phase-Z Input
UART Channel 2 TXD Output
PORT E Bit 14 Input/Output
2nd function
T3IO
IO
Timer 3 Input/Output
4st function
RXD2
PE15
T4IO
PD14
SS0
PD15
SCK0
PC15
TXD0
MISO0
PC14
RXD0
MOSI0
VMARGIN
Input
IOUS
IO
IOUS
IO
IOUS
IO
IOUS
Output
I/O
IOUS
Input
I/O
OA
UART Channel 2 RXD Input
PORT E Bit 15 Input/Output
Timer 4 Input/Output
PORT D Bit 14 Input/Output
SPI Channel 0 Slave Select signal
PORT D Bit 15 Input/Output
SPI Channel 0 Clock Input/Output
PORT C Bit 14 Input/Output
UART Channel 0 TXD Output
SPI Channel 0 Input(M)/Output(S)
PORT C Bit 14 Input/Output
UART0 RXD Input
SPI Channel 0 Output(M)/Input(S)
Not used. (test purpose)
2nd function
PC13
IOUS
PORT C Bit 13 Input/Output
99
XOUT
PC12
XIN
PD0
SS1
SXIN
PD1
SCK1
SXOUT
VDD
OA
IOUS
IA
IOUS
I/O
IA
IOUS
I/O
OA
P
External Crystal Oscillator Output
PORT C Bit 12 Input/Output
External Crystal Oscillator Input
PORT D Bit 0 Input/Output
SPI Channel 1 Slave Select signal
Sub Crystal Oscillator Input
PORT D Bit 1 Input/Output
SPI Channel 1 Clock Input/Output
Sub Crystal Oscillator Output
VDD
100
GND
P
Ground
87
88
89
90
91
92
93
94
95
96
97
98
4st function
2nd function
4st function
2nd function
2nd function
2nd function
2nd function
2nd function
2nd function
*Notation: I=Input, O=Output, U=Pull-up, D=Pull-down,
S=Schmitt-Trigger Input Type, C=CMOS Input Type, A=Analog, P=Power
(*) Selected pin function after reset condition
Pin order may be changed with revision notice
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Z32F3841 Product Specification
Overview
Memory Map
Memory map
Address
0x0000_0000
0x0005_FFFF
0x0006_0000
Code Flash ROM
(384KB)
Reserved
0x1FFE_FFFF
0x1FFF_0000
0x1FFF_07FF
0x1FFF_0800
Boot ROM
(2KB)
Reserved
0x1FFF_FFFF
0x2000_0000
0x2000_5FFF
0x2000_6000
0x2FFF_FFFF
0x2200_0000
0x23FF_FFFF
0x2400_0000
0x2FFF_FFFF
0x3000_0000
0x3005_FFFF
0x3008_0000
0x3008_07FF
0x3009_0000
0x3009_01FF
0x3009_0200
0x3FFF_FFFF
0x4000_0000
SRAM
(16K)
Reserved
SRAM Bit-banding region
Reserved
Code Flash ROM(Mirrored)
(384KB)
Boot ROM (Mirrored)
(2KB)
OTP ROM (Mirrored)
Reserved
Periperals
0x4000_FFFF
0x4001_0000
0x41FF_FFFF
0x4200_0000
0x43FF_FFFF
0x4400_0000
0x5FFF_FFFF
0x6000_0000
0x9FFF_FFFF
0xA000_0000
0xDFFF_FFFF
0xE000_0000
0xE003_FFFF
0xE004_0000
0xE00F_FFFF
0xE010_0000
Reserved
Periperals bit-banding region
Reserved
External Memory
(Not supported)
External Device
(Not supported)
Private peripheral bus:
Internal
Private peripheral bus:
Debug/External
Vendor Specific
0xFFFF_FFFF
Figure1.4. Main Memory Map
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Z32F3841 Product Specification
Overview
Core memory map
Address
0xE000_0000
ITM
0xE000_0FFF
0xE000_1000
DWT
0xE000_1FFF
0xE000_2000
FPB
0xE000_2FFF
0xE000_3000
Reserved
0xE000_DFFF
0xE000_E000
System Control
0xE000_EFFF
0xE000_F000
0xE003_FFFF
0xE004_0000
Reserved
TPIU
0xE004_0FFF
0xE004_1000
ETM
0xE004_1FFF
0xE004_2000
External PPB
0xE00F_EFFF
0xE00F_F000
ROM Table
0xE00F_FFFF
Figure1.5. Cortex-M3 Private Memory Map
Note: Please see document number DDI337 from ARM for more information about the Cortex-M3 memory
map.
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Z32F3841 Product Specification
Address
0x4000_0000
0x4000_0100
0x4000_0200
0x4000_0300
0x4000_0400
0x4000_0500
0x4000_0600
0x4000_1000
0x4000_2000
0x4000_3000
0x4000_4000
0x4000_5000
0x4000_6000
0x4000_8000
0x4000_8100
0x4000_8200
0x4000_8300
0x4000_8600
0x4000_9000
0x4000_9100
0x4000_9200
0x4000_A000
0x4000_A100
0x4000_A200
0z4000_B000
0x4000_B100
0x4000_B200
0x4000_B300
0x4000_B400
0x4000_FFFF
Overview
Peripheral map
SCU
FMC
WDT
Reserved
DMAC(8)
Reserved
FRT
PCU
GPIO(A,B,C,D,E,F)
TIMER
MPWM0
MPWM1
Reserved
UART0
UART1
UART2
UART3
Reserved
SPI0
SPI1
Reserved
I2C0
I2C1
Reserved
ADC0
ADC1
Reserved
Reserved
Reserved
Figure1.6. Peripheral Memory Map
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Z32F3841 Product Specification
CPU
2. CPU
Cortex-M3 Core
The CPU core is supported from the ARM Cortex-M3 processor which provides a high-performance, low-cost
platform.
Document DDI337 from ARM provides more information about the Cortex-M3.
System Timer
The System Timer (SYSTICK) is a 24-bit timer and is part of the Cortex-M3 core. The system timer can be
configured either through the registers (see the Cortex-M3 Technical Reference Manual) or through the
provided functions defined in core_cm3.h. There is an interrupt vector for the system timer. To configure the
system timer, call SysTickConfig() with the number of system clocks in between Interrupt intervals (up to
maximum of 24 bits).
Interrupt Controller
The Nested Vectored Interrupt Controller is part of the core Cortex-M3 MCU. The NVIC controls the system
exceptions and peripheral interrupts and is closely coupled with the core to provide low latency and efficient
processing of late arriving interrupts. The NVIC maintains knowledge of the nested interrupts to enable tailchaining of interrupts.
The Z32F3841 MCU supports 64 peripheral interrupts (although 25 are not used) and 16 system interrupts.
The NVIC also allows for setting software interrupts as well as resetting the system.
Interrupts can be assigned a Priority Group (common interrupts with the same priorities) as well as individual
priorities. Eight priority levels are available. For an interrupt to be active, you must enable it in the peripheral
and the NVIC registers. For more information on NVIC, see the Cortex M3 Technical Reference Manual.
The system includes functions to set the NVIC registers, which are defined in the core_cm3.h.
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Z32F3841 Product Specification
CPU
Table2.1. Interrupt Vector Map
PS034603-0617
Priority
Vector Address
Interrupt Source
-16
0x0000_0000
Stack Pointer
-15
0x0000_0004
Reset Address
-14
0x0000_0008
NMI Handler
-13
0x0000_000C
Hard Fault Handler
-12
0x0000_0010
MPU Fault Handler
-11
0x0000_0014
BUS Fault Handler
-10
0x0000_0018
Usage Fault Handler
-9
0x0000_001C
Reserved
-8
0x0000_0020
Reserved
-7
0x0000_0024
Reserved
-6
0x0000_0028
Reserved
-5
0x0000_002C
SVCall Handler
-4
0x0000_0030
Debug Monitor Handler
-3
0x0000_0034
-2
0x0000_0038
PenSV Handler
-1
0x0000_003C
SysTick Handler
0
0x0000_0040
LVDDETECT
1
0x0000_0044
SYSCLKFAIL
2
0x0000_0048
XOSCFAIL
3
0x0000_004C
WDT
4
0x0000_0050
FRT
5
0x0000_0054
TIMER0
6
0x0000_0058
TIMER1
7
0x0000_005C
TIMER2
8
0x0000_0060
TIMER3
9
0x0000_0064
TIMER4
10
0x0000_0068
TIMER5
Reserved
11
0x0000_006C
TIMER6
12
0x0000_0070
TIMER7
13
0x0000_0074
TIMER8
14
0x0000_0078
TIMER9
15
0x0000_007C
16
0x0000_0080
GPIOAE
17
0x0000_0084
GPIOAO
18
0x0000_0088
GPIOBE
19
0x0000_008C
GPIOBO
20
0x0000_0090
GPIOCE
21
0x0000_0094
GPIOCO
22
0x0000_0098
GPIODE
23
0x0000_009C
GPIODO
24
0x0000_00A0
MPWM0
25
0x0000_00A4
MPWM0PROT
Reserved
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Z32F3841 Product Specification
PS034603-0617
26
0x0000_00A8
MPWM0OVV
27
0x0000_00AC
MPWM1
28
0x0000_00B0
MPWM1PROT
29
0x0000_00B4
MPWM1OVV
30
0x0000_00B8
Reserved
31
0x0000_00BC
Reserved
32
0x0000_00C0
SPI0
33
0x0000_00C4
SPI1
34
0x0000_00C8
Reserved
35
0x0000_00CC
Reserved
36
0x0000_00D0
I2C0
37
0x0000_00D4
I2C1
38
0x0000_00D8
UART0
39
0x0000_00DC
UART1
40
0x0000_00E0
UART2
41
0x0000_00E4
UART3
42
0x0000_00E8
43
0x0000_00EC
ADC0
44
0x0000_00F0
ADC1
45
0x0000_00F4
Reserved
46
0x0000_00F8
Reserved
47
0x0000_00FC
Reserved
48
0x0000_0100
Reserved
49
0x0000_0104
Reserved
CPU
Reserved
50
0x0000_0108
GPIOEE
51
0x0000_010C
GPIOEO
52
0x0000_0110
GPIOFE
53
0x0000_0114
GPIOFO
54
0x0000_0118
Reserved
55
0x0000_011C
Reserved
56
0x0000_0120
Reserved
57
0x0000_0124
Reserved
58
0x0000_0128
Reserved
59
0x0000_012C
Reserved
60
0x0000_0130
Reserved
61
0x0000_0134
Reserved
62
0x0000_0138
Reserved
63
0x0000_013C
Reserved
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Z32F3841 Product Specification
Boot Mode
3. Boot Mode
Boot Mode Pins
The Z32F3841 MCU has a boot mode option to program internal Flash memory. When the BOOT pin is pulled
low, the system starts up in the BOOT area (0x1FFF_0000) instead of the default Flash area (0x0000_0000).
This provides the ability to flash the part using either UART or SPI interfaces. The BOOT pin has an internal
pull up resistor; therefore, when the BOOT pin is not connected, it rides high (normal state).
The boot mode uses the UART0 port and the SPI0 ports for the interface. JTAG and SW interfaces can also
be used, which provides the ability to recover from a bad flash update that prevents the JTAG or SW
debugger from attaching.
The pins for boot mode are listed in Table 3.1.
Block
SYSTEM
UART0
SPI0
Pin Name
Table3.1. Boot Mode Pin List
Dir
Description
nRESET/PC10
BOOT/PC11
RXD0/PC14
TXD0/PC15
SS0/PA12
SCK0/PA13
MOSI0/PA14
MISO0/PA15
I
I
I
O
I
I
I
O
Reset Input signal
‘0’ to enter Boot mode
UART Boot Receive Data
UART Boot Transmit Data
SPI Boot Slave Select
SPI Boot Clock Input
SPI Boot Data Input
SPI Boot Data Output
Boot Mode Connections
Users can design the target board using either of the boot mode ports – UART or SPI.
Figures 3.1 and 3.2 show sample boot mode connection diagrams.
3.3
5V
10kΩ
TARGET_RESET
BOOT_SW
~
VDD
nRESET
BOOT
Z32F3841
HOST_TXD
RXD0
HOST_RXD
TXD0
GND
Figure3.1. UART Boot Connection Diagram
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Z32F3841 Product Specification
Boot Mode
3.3
5V
10kΩ
TARGET_RESET
~
VDD
nRESET
BOOT_SW
BOOT
HOST_SS
SS0
HOST_SCK
Z32F3841
SCK0
HOST_SDOUT
MOSI0
HOST_SDIN
MISO0
GND
Figure3.2. SPI Boot Connection Diagram
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Z32F3841 Product Specification
System Control Unit
4. System Control Unit
Overview
The Z32F3841 MCU has a built-in intelligent power control block which manages system analog blocks and
operating modes. Internal reset and clock signals are controlled by SCU block to maintain optimize system
performance and power dissipation.
APB BUS
RESET
INTERRUPT
INTERRUPT
SCU
MODE CONTROL
SCU
SCU
CLOCK GEN
HCLK
POWER DOWN
WAKE UP
VDC/LVD/PLL
IntOSC CONTROL
PCLK
Wakeup
Srouce
VDC/LVD/PLL
IntOSC
Figure 4.1. SCU Block Diagram
Clock System
The Z32F3841 MCU has two main clock systems. One is MCLK which supplies the clock to the HCLK_Free,
CPU and AHB bus system. The PCLK clock is for the Peripheral clock and is supplied from MCLK. Some
peripherals have the option to derive their clock from other clocks or the PCLK. User can control the clock
system variation by software. Figure 4.2 shows the clock system of the chip, Table 4.1 lists the clock source
descriptions.
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Z32F3841 Product Specification
System Control Unit
IOSCCON[0]
O_rcclk_pre
IOSC
(20MHz)
(16MHz)
En/Dis
0
/2
1
0
IOSCCON[1]
PLL
PLLCLK
1
MCLKSEL[0]
MCLKSEL[1]
FINSEL
MOSC
(4MHz/8MHz)
En/Dis
MOSCCON[1]
/2
1
1
O_emclk_pre
MCLK
1
HCLK_FREE
PCLK
CM3_HCLK
BUS_HCLK
SLEEP
MEM_HCLK
PD
SUBCLK
0
1
HCLK
PD
MOSCCON[0]
/2
CM3_FCLK
0
SOSCCON[0]
SOSC
(1MHz)
En/Dis
HCLK_FREE
0
FINCLK
0
DMA_HCLK
O_rclk_pre
DMAEN
SOSCCON[1]
Figure 4.2. System Clock Configuration
Each of the mux to switch clock sources has a glitch-free circuit; therefore, the clock can be switched without
a risk of glitches.
Table 4.1. Clock Sources
Clock name
Frequency
Description
IOSC20
20MHz
Internal OSC
Sub OSC
Sub X-TAL (32.768KHz)
Sub External Crystal OSC
MainOSC
X-TAL(4MHz~16MHz)
External Crystal OSC
PLL Clock
8MHz ~ 80MHz
On Chip PLL
ROSC
1MHz
Internal RING OSC
The PLL can synthesize the PLLCLK clock up to 80 MHz with either the Internal Oscillator or the External
Crystal Oscillator reference clocks. It also has an internal pre-divider and post-divider.
HCLK Clock Domain
The HCLK clock feeds the clock to the CPU and AHB bus. The Cortex-M3 CPU requires two clocks related to
the HCLK clock, FCLK and HCLK. FCLK is a free running clock and is always running except in power down
mode. HCLK can be stopped in idle mode.
MCLK
MCLK
HCLK_FREE
CM3_FCLK
HCLK
CM3_HCLK
BUS_HCLK
IDLE
MEM_HCLK
DMA_HCLK
DMAEN
Figure 4.3. System Clock Configuration
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Z32F3841 Product Specification
System Control Unit
Miscellaneous Clock Domain for Cortex-M3
MCLK
MCLK
FCLK
SUBCLK
SUBCLK
/N
IOSC
SYNC
CM3_STCLK
/N
IOSC
MOSC
TIMER_EXT0
MOSC
STCLKDIV[7:0]
PLL
PLL
STSRCSEL[2:0]
TEXT0SRCSEL[2:0]
MCLK
MCLK
SUBCLK
SUBCLK
/N
IOSC
TEXT0CLKDIV[7:0]
TRACECLK
/N
IOSC
WDT_EXT0
MOSC
MOSC
PLL
TRACECLKDIV[7:0]
PLL
WDTEXTSRCSEL[2:0]
TRACESRCSEL[2:0]
MCLK
MCLK
SUBCLK
SUBCLK
/N
IOSC
WDTEXTCLKDIV[7:0]
PWM0CLK
PWM1CLK
/N
IOSC
MOSC
MOSC
PLL
PWM0CLKDIV[7:0]
PWM1CLKDIV[7:0]
PLL
DEBPxTCLKDIV[7:0]
DEB_PA_CLK
DEB_PB_CLK
DEB_PC_CLK
DEB_PD_CLK
DEB_PE_CLK
DEB_ETC_CLK
DEBPxSRCSEL[2:0]
PWM0SRCSEL[2:0]
PWM1SRCSEL[2:0]
Figure 4.4. Miscellaneous Clock Configuration
PCLK Clock Domain
PCLK is the master clock of all the peripherals. It can be stopped in power down mode. Each peripheral clock
is generated by the PCER register set.
Clock Configuration Procedure
After power up, the default system clock is fed by the RINGOSC (1 MHz) clock. RINGOSC is enabled by
default during the power up sequence. The other clock sources are enabled by user controls with the
RINGOSC system clock.
The MOSC clock can be enabled by the CSCR register. Prior to enabling the MOSC block, the pin mux
configuration should be set for the XIN, XOUT function. PC12 and PC13 pins are shared with the MOSC’s XIN
and XOUT function; the PCCMR and PCCCR registers should be correctly configured. After enabling the
MOSC block, you must wait for more than 1 msec to ensure stable crystal oscillation operation.
The PLL clock can be enabled by the PLLCON register. After enabling the PLL block, you must wait for the
PLL lock, before you can select the PLL clock as the MCLK. Before changing the system clock, Flash access
wait should be set to the maximum value. After the system clock is changed, you can set the desired Flash
access wait value.
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Z32F3841 Product Specification
System Control Unit
Figure 4.5 shows a sample flow chart for configuring the system clock.
Figure 4.5 Clock Configuration Flow Chart
When you speed up the system clock to the maximum operating frequency, check the Flash wait control
configuration. Flash read access time is a limiting factor for optimum performance. The wait control
recommendation is provided in Table 4.1.
FM.CFG.WAIT
Table 4.1. Flash Wait Control Recommendation
Flash Access Wait
Available Max System Clock Frequency
000
0 wait
~25MHz
001
1 wait
~50MHz
010
2 wait
~75MHz
011
3 wait
~75MHz
100
4 wait
~75MHz
101
5 wait
~75MHz
Cold Reset
Cold reset is an important feature of the chip when power is up. This characteristic globally affects the system
boot. Internal VDC is enabled when VDD power is turned on. The internal VDD level slope is followed by the
external VDD power slope. The internal PoR trigger level is 1.4 V of internal VDC voltage out level. At this time,
boot operation is started. The RINGOSC clock is enabled and counts to 4 msec for internal VDC level
stabilizing. During this time, the external VDD voltage level should be greater than the initial LVD level (2.3 V).
After waiting 4 msec, the CPU reset is released and the operation is started.
Figure 4.6 shows the power up sequence and internal reset waveform.
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Z32F3841 Product Specification
System Control Unit
Figure 4.6. Power Up POR Sequence
The RSSR register shows the POR reset status. The last reset comes from POR; RSSR.PORST is set to “1”.
After power up, this bit is always “1”. If an abnormal internal voltage drop occurs during normal operation, the
system will be reset and this bit is also set to “1”.
When cold reset is applied, the chip returns to its initial state.
Warm Reset
The warm reset event has several reset sources. Some parts of the chip return to initial state when a warm
reset condition occurs.
The warm reset source is controlled by the RSER register and the status appears in the RSSR register. The
reset for each peripheral block is controlled by the PRER register. The reset can be masked independently.
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Z32F3841 Product Specification
System Control Unit
Figure 4.7. Warm Reset
The CM3_SYSRESETn signal resets the processor, excluding debug logic in the processor.
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Z32F3841 Product Specification
System Control Unit
Operation Mode
The INIT mode is the initial state of the chip when reset is asserted. The RUN mode is for maximum
performance of the CPU with a high-speed clock system. The SLEEP and POWER DOWN modes can be
used as low- power consumption modes. Low-power consumption is achieved by halting the processor core
and unused peripherals.
Figure 4.5 shows the operating mode transition diagram.
Power-on
Reset
Reset Event
INIT
MCU
Initialization
Reset Event
Reset Event
PCU Wake-up Event
Wake-up Event
SLEEP
PD
RUN
SCUMODE=01
SCUMODE=10
Figure4.5. Operating Mode
RUN Mode
In RUN mode, the CPU core and the peripheral hardware is operated by using the high-speed clock. After
reset, followed by the INIT state, the chip enters RUN mode.
SLEEP Mode
In SLEEP mode, only the CPU is stopped. Each peripheral function can be enabled by the function enable
and clock enable bit in the PER and PCER register.
POWER DOWN Mode
In POWER DOWN mode, all internal circuits enter the stop state. Power down operation has a special power
off sequence, as shown in Figure 4.6.
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Z32F3841 Product Specification
System Control Unit
WFI with deepsleep
RUN mode
HCLK STOP
HCLK RUN
YES
RING OSC EN
PMUCSCR[5] = 1
WakeupCNT ==
VDCDELAY
step 0
No
MCLK = SubOSC
PMUSCCR[1:0] = 2'b00
step 3
Wakeup CNT
CNT == CNT + 1
ANALOG EN MASK
ANANLOGEN & 0
step 4
ANALOG EN Resume
ANANLOGEN & 1
IOSC EN MASK
PMUCSCR[3] & 0
MEOSC EN MASK
PMUCSCR[1] & 0
VDCSTOP
IOSC EN Resume
PMUCSCR[3] & 1
MEOSC EN Resume
PMUCSCR[1] & 1
step 5
VDCRUN
step 6
RING OSC STOP
PMUCSCR[5] = 0
PWDN
RING OSC ON
PMUCSCR[5] = 0
step 7
External Wakeup
Figure 4.6. Power-down and Wake-up Procedure
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Z32F3841 Product Specification
System Control Unit
Pin Description
Table4.2. SCU and PLL Pins
PS034603-0617
PIN NAME
TYPE
nRESET
I
DESCRIPTION
XIN/XOUT
OSC
External Crystal Oscillator
SXIN/SXOUT
OSC
External Sub Crystal Oscillator
STBYO
O
Stand-by Output Signal
CLKO
O
Clock Output Monitoring Signal
External Reset Input
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Z32F3841 Product Specification
System Control Unit
Registers
The base address of SCU is 0x4000_0000 and the register map is described in Table.4.3
Table 4.3. SCU Register Map
Name
Offset
R/W
CIDR
0x0000
R
SMR
Description
Reset
CHIP ID Register
AC33_0384
0x0004
R/W
System Mode Register
0000_0000
SRCR
0x0008
R/W
System Reset Control Register
0000_0000
CIDR2
0x000C
R/W
CHIP Revision ID Register
0000_0000
WUER
0x0010
R/W
Wake up source enable register
0000_0000
WUSR
0x0014
R/W
Wake up source status register
0000_0000
RSER
0x0018
R/W
Reset source enable register
0000_0049
RSSR
0x001C
R/W
Reset source status register
0000_0080*
PRER1
0x0020
R/W
Peripheral reset enable register 1
03FF_1F1F*
PRER2
0x0024
R/W
Peripheral reset enable register 2
00F3_0F33*
PER1
0x0028
R/W
Peripheral enable register 1
0000_000F*
PER2
0x002C
R/W
Peripheral enable register 2
0000_0101*
PCER1
0x0030
R/W
Peripheral clock enable register 1
0000_000F*
PCER2
0x0034
R/W
Peripheral clock enable register 2
0000_0101*
CSCR
0x0040
R/W
Clock Source Control register
0000_0020
SCCR
0x0044
R/W
System Clock Control register
0000_0000
0000_0003
CMR
0x0048
R/W
Clock Monitoring register
NMIR
0x004C
R/W
NMI control register
0000_0000
COR
0x0050
R/W
Clock Output Control register
0000_000F
0x0054
-
PLLCON
0x0060
R/W
PLL Control register
0000_1000
VDCCON
0x0064
R/W
VDC Control register
0000_000F
LVDCON
0x0068
R/W
LVD Control register
0000_0001
IOSCTRIM
0x006C
R/W
Internal RC OSC Control register
0000_0000
0x0070
-
Reserved
0000_0000
0x0074
-
Reserved
0000_0000
0x0078
-
Reserved
0000_0000
PS034603-0617
Reserved
0x007C
-
Reserved
0000_0000
EOSCR
0x0080
R/W
External Oscillator control register
0000_0000
EMODR
0x0084
R/W
External mode pin read register
0000_000X
DBCLK1
0x009C
R/W
Debounce Clock for PA, PB Pins
0000_0000
DBCLK2
0x00A0
R/W
Debounce Clock for PC, PD Pins
0000_0000
DBCLK3
0x00A4
R/W
Debounce Clock for PE, PF pins
0000_0001
MCCR1
0x0090
R/W
Trace and SysClock Clock Control
0404_0001
MCCR2
0x0094
R/W
MPWM0 and MPWM1 Clock Control
0000_0000
MCCR3
0x0098
R/W
TEXT0 and WDT clock control
0000_0001
MCCR4
0x00A8
R/W
ADC and NMI Debounce Clock control
0000_0001
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Z32F3841 Product Specification
CIDR
System Control Unit
Chip ID Register
The Chip ID register shows chip identification information. This register is a 32-bit read-only register.
CIDR=0x4000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CHIPID
AC33_0384
Read Only
31
0
CHIP ID
Device ID
AC33_0384
CIDR2=0x4000_000C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
REVISION ID
0x0000_0002
Read Only
31
0
SMR
REVISION ID
Device Revision ID
0x0000_0002
System Mode Register
The current operating mode is shown in this SCU mode register and the operation mode can be changed by
writing new mode in this register. The previous operating mode is saved in this register after a reset event.
The System Mode register is a 16-bit register.
SMR=0x4000_0004
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
0
0
R/W
PS034603-0617
8
VDCAON
5
4
PREVMODE
5
4
3
2
1
0
0
0
0
0
PREVMODE
14
VDCAON
15
00
R
VDC Always on
0
VDC will be off when Power down mode
1
VDC always on even in power down mode
Previous operating mode before current reset event.
00 Previous operating mode was RUN mode
01 Previous operating mode was SLEEP mode
10 Previous operating mode was PowerDown mode
11 Previous operating mode was INIT mode
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Z32F3841 Product Specification
SRCR
System Control Unit
System Reset Control Register
The Ssystem Reset Control register is an 8-bit register.
SCR=0x4000_0008
7
6
5
4
3
2
1
STBYOP
0
0
0
0
SWRST
0
0
0
RW
PS034603-0617
5
STBYOP
1
SWRST
0
0
W
STBYO pin output polarity select bit
0
Low active when chip is in Power Down
1
High active when chip is in PowerDown
Internal soft reset activation bit
0
Normal operation
1
Internal soft reset is applied and auto cleared
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Z32F3841 Product Specification
WUER
System Control Unit
Wakeup Source Enable Register
The Wakeup Source Enable register enables the wakeup source when the chip is in Power Down mode.
Wakeup sources which will be used as the source of chip wakeup should be enabled in each bit field. If the
source will be used as the wakeup source, write ‘1’ to its enable bit. If the source will not be used as the
wakeup source, write 0 to its enable bit.
This register is a 16-bit register.
GPIOEWUE
GPIODWUE
GPIOCWUE
GPIOBWUE
GPIOAWUE
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
PS034603-0617
12
11
10
9
13
GPIOFWUE
12
GPIOEWUE
11
GPIODWUE
10
GPIOCWUE
9
GPIOBWUE
8
GPIOAWUE
2
FRTWUE
1
WDTWUE
0
LVDWUE
8
7
6
5
4
3
2
LVDWUE
13
WDTWUE
14
FRTWUE
15
GPIOFWUE
WUER=-0x4000_0010
1
0
0
0
0
0
0
0
0
0
RW
RW
RW
Enable wakeup source of GPIOF port pin change event
0
Not used for wakeup source
1
Enable the wakeup event generation
Enable wakeup source of GPIOE port pin change event
0
Not used for wakeup source
1
Enable the wakeup event generation
Enable wakeup source of GPIOD port pin change event
0
Not used for wakeup source
1
Enable the wakeup event generation
Enable wakeup source of GPIOC port pin change event
0
Not used for wakeup source
1
Enable the wakeup event generation
Enable wakeup source of GPIOB port pin change event
0
Not used for wakeup source
1
Enable the wakeup event generation
Enable wakeup source of GPIOA port pin change event
0
Not used for wakeup source
1
Enable the wakeup event generation
Enable wakeup source of free run timer event
0
Not used for wakeup source
1
Enable the wakeup event generation
Enable wakeup source of watchdog timer event
0
Not used for wakeup source
1
Enable the wakeup event generation
Enable wakeup source of LVD event
0
Not used for wakeup source
1
Enable the wakeup event generation
PRELIMINARY
32
Z32F3841 Product Specification
WUSR
System Control Unit
Wakeup Source Status Register
When the system is woken up by any wakeup source, the wakeup source is identified by reading the Wakeup
Source Status register. When the bit is set to 1, the related wakeup source issues the wakeup to the SCU.
The bit will be cleared when the event is cleared by the software.
GPIOEWU
GPIODWU
GPIOCWU
GPIOBWU
GPIOAWU
0
0
0
0
0
0
0
0
R
R
R
R
R
R
PS034603-0617
12
11
10
9
13
GPIOFWU
12
GPIOEWU
11
GPIODWU
10
GPIOCWU
9
GPIOBWU
8
GPIOAWU
2
FRTWU
1
WDTWU
0
LVDWU
8
7
6
5
4
3
2
LVDWU
13
WDTWU
14
FRTWU
15
GPIOFWU
WUSR=0x4000_0014
1
0
0
0
0
0
0
0
0
0
R
R
R
Status of wakeup source of GPIOF port pin change event
0
No wakeup event
1
Wakeup event was generated
Status of wakeup source of GPIOE port pin change event
0
No wakeup event
1
Wakeup event was generated
Status of wakeup source of GPIOD port pin change event
0
No wakeup event
1
Wakeup event was generated
Status of wakeup source of GPIOC port pin change event
0
No wakeup event
1
Wakeup event was generated
Status of wakeup source of GPIOB port pin change event
0
No wakeup event
1
Wakeup event was generated
Status of wakeup source of GPIOA port pin change event
0
No wakeup event
1
Wakeup event was generated
Status of wakeup source of free run timer event
0
No wakeup event
1
Wakeup event was generated
Status of wakeup source of watchdog timer event
0
No wakeup event
1
Wakeup event was generated
Status of wakeup source of LVD event
0
No wakeup event
1
Wakeup event was generated
PRELIMINARY
33
Z32F3841 Product Specification
RSER
System Control Unit
Reset Source Enable Register
The reset source which will generate the reset event can be selected by the Reset Source Enable register.
When writing 1 to the bit field of each reset source, the reset source event will be transferred to the reset
generator. When writing 0 to the bit field of each reset source, the reset source event will be masked and will
not generate a reset event.
RSER=0x4000_0018
7
0
PS034603-0617
6
5
4
3
2
1
0
PINRST
CORERST
SWRST
WDTRST
MCKFRST
XFRST
LVDRST
1
0
0
1
0
0
1
RW
RW
RW
RW
RW
RW
RW
6
PINRST
5
CPURST
4
SWRST
3
WDTRST
2
MCKFRST
1
XFRST
0
LVDRST
External pin reset enable bit
0
Reset from this event is masked
1
Reset from this event is enabled
CPU request reset enable bit
0
Reset from this event is masked
1
Reset from this event is enabled
Software reset enable bit
0
Reset from this event is masked
1
Reset from this event is enabled
Watchdog Timer reset enable bit
0
Reset from this event is masked
1
Reset from this event is enabled
MCLK Clock fail reset enable bit
0
Reset from this event is masked
1
Reset from this event is enabled
External OSC Clock fail reset enable bit
0
Reset from this event is masked
1
Reset from this event is enabled
LVD reset enable bit
0
Reset from this event is masked
1
Reset from this event is enabled
PRELIMINARY
34
Z32F3841 Product Specification
RSSR
System Control Unit
Reset Source Status Register
The Reset Source Status register shows the reset source information when a reset event occurs. “1” indicates
that a reset event exists and “0” indicates that a reset event does not exist for a reset source. When the reset
source is found, writing “1” to the corresponding bit will clear the reset status.
This register is an 8-bit register.
RSSR=0x4000_001C
7
6
5
4
3
2
1
0
PORST
PINRST
CORERST
SWRST
WDTRST
MCKFRST
XFRST
LVDRST
1
0
0
0
0
0
0
0
RC1
RC1
RC1
RC1
RC1
RC1
RC1
RC1
PS034603-0617
7
PORST
6
PINRST
5
CPURST
4
SWRST
3
WDTRST
1
XFRST
0
LVDRST
Power on reset status bit
0
Read : Reset from this event was not exist
Write : no effect
1
Read :Reset from this event was occurred
Write : Clear the status
External pin reset status bit
0
Read : Reset from this event was not exist
Write : no effect
1
Read :Reset from this event was occurred
Write : Clear the status
CPU request reset status bit
0
Read : Reset from this event was not exist
Write : no effect
1
Read :Reset from this event was occurred
Write : Clear the status
Software reset status bit
0
Read : Reset from this event was not exist
Write : no effect
1
Read :Reset from this event was occurred
Write : Clear the status
Watchdog Timer reset status bit
0
Read : Reset from this event was not exist
Write : no effect
1
Read :Reset from this event was occurred
Write : Clear the status
Clock fail reset status bit
0
Read : Reset from this event was not exist
Write : no effect
1
Read :Reset from this event was occurred
Write : Clear the status
LVD reset status bit
0
Read : Reset from this event was not exist
Write : no effect
1
Read :Reset from this event was occurred
Write : Clear the status
PRELIMINARY
35
Z32F3841 Product Specification
PRER1
System Control Unit
Peripheral Reset Enable Register 1
The reset of each peripheral by an event reset can be masked by a user setting. The Peripheral Reset Enable
register controls enabling of the event reset. If the corresponding bit is ‘1’, the peripheral corresponds with this
bit and accepts the reset event. Otherwise, the peripheral is protected from the reset event and maintains its
current operation.
When a reset is issued (enabled by the RSER register), you can configure each peripheral to either reset the
registers to the default settings or ignore the reset. This applies to all resets except for removal of power.
Caution: If you disable the SCU reset response, you may not be able to connect via the debugger without a
power off and on reset. Caution should also be applied with the GPIO/PCU peripherals because the debugger
uses these as well.
PS034603-0617
FMC
SCU
0
0
1
1
1
1
1
RW
RW
1
PCU
1
WDT
1
4
RW
1
5
RW
1
6
DMA
RW
FRT
RW
GPIOA
RW
1
RW
RW
1
RW
RW
TIMER9
TIMER8
TIMER7
TIMER6
TIMER5
TIMER4
TIMER3
TIMER2
TIMER1
TIMER0
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
FRT
DMA
PCU
WDT
FMC
SCU
0
GPIOB
RW
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
4
3
2
1
0
0
RW
1
GPIOC
TIMER0
1
RW
TIMER1
1
GPIOD
TIMER2
1
RW
TIMER3
1
GPIOF
TIMER4
1
7
GPIOE
TIMER5
1
1
8
RW
TIMER6
1
1
9
RW
TIMER7
0
RW
0
TIMER8
0
RW
0
TIMER9
0
RW
0
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
PRER1=0x4000_0020
3
2
1
0
TIMER9 reset mask
TIMER8 reset mask
TIMER3 reset mask
TIMER2 reset mask
TIMER1 reset mask
TIMER0 reset mask
TIMER3 reset mask
TIMER2 reset mask
TIMER1 reset mask
TIMER0 reset mask
GPIOF reset mask
GPIOE reset mask
GPIOE reset mask
GPIOE reset mask
GPIOE reset mask
GPIOA reset mask
FRT reset mask
DMA reset mask
Port Control Unit reset mask
Watchdog Timer reset mask
Flash memory controller reset mask
System Control Unit reset mask
PRELIMINARY
36
Z32F3841 Product Specification
PRER2
System Control Unit
Peripheral Reset Enable Register 2
Peripheral Reset Enable Register 2 is a 32-bit register (See PRER1 for a full explaination of this register).
21
20
17
16
11
10
9
8
5
4
1
0
PS034603-0617
ADC1
ADC0
MPWM1
MPWM0
UART3
UART2
UART1
UART0
I2C1
I2C0
SPI1
SPI0
1
0
0
1
1
1
SPI0
1
2
0
0
1
1
RW
1
3
SPI1
1
4
RW
0
5
I2C0
0
6
RW
0
7
I2C1
0
UART0
1
UART1
1
RW
0
RW
0
UART2
1
RW
1
8
UART3
0
9
RW
1
MWPM0
0
RW
0
MPWM1
0
RW
0
ADC0
0
RW
0
ADC1
0
RW
0
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
PRER2=0x4000_0024
0
ADC1 reset enable
ADC0 reset enable
MPWM1 reset enable
MPWM0 reset enable
UART3 reset enable
UART2 reset enable
UART1 reset enable
UART0 reset enable
I2C1 reset enable
I2C0 reset enable
SPI1 reset enable
SPI0 reset enable
PRELIMINARY
37
Z32F3841 Product Specification
PER1
System Control Unit
Peripheral Enable Register 1
All the peripherals are disabled by default except SPI0 and UART0.
To use the peripheral unit, activate it by writing “1” to the corresponding bit in the PER0/1 register. When the
bit for the peripheral unit is cleared ("0"), the peripheral will stay in a reset state.
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
4
3
2
1
0
PS034603-0617
0
0
0
RW
RW
0
0
1
1
1
1
R
0
1
R
FRT
0
2
R
GPIOA
0
3
R
GPIOB
0
6
5
4
0
0
DMA
GPIOC
0
RW
RW
TIMER9
TIMER8
TIMER7
TIMER6
TIMER5
TIMER4
TIMER3
TIMER2
TIMER1
TIMER0
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
FRT
DMA
0
GPIOD
0
RW
0
GPIOF
0
7
GPIOE
TIMER0
0
8
RW
TIMER1
0
9
RW
TIMER2
0
RW
0
RW
0
TIMER3
0
RW
TIMER5
0
TIMER4
TIMER6
0
TIMER7
0
RW
0
TIMER8
0
RW
0
TIMER9
0
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
PER1=0x4000_0028
TIMER9 function enable
TIMER8 function enable
TIMER7 function enable
TIMER6 function enable
TIMER5 function enable
TIMER4 function enable
TIMER3 function enable
TIMER2 function enable
TIMER1 function enable
TIMER0 function enable
GPIOF function enable
GPIOE function enable
GPIOD function enable
GPIOC function enable
GPIOB function enable
GPIOA function enable
FRT function enable
DMA function enable
Reserved
PRELIMINARY
38
Z32F3841 Product Specification
PER2
System Control Unit
Peripheral Enable Register 2
Peripheral Enable Register 2 is a 32-bit register.
21
20
17
16
11
10
9
8
5
4
1
0
PS034603-0617
ADC1
ADC0
MPWM1
MPWM0
UART3
UART2
UART1
UART0
I2C1
I2C0
SPI1
SPI0
1
0
0
0
0
1
SPI0
0
2
0
0
0
1
RW
0
3
SPI1
0
4
RW
0
5
I2C0
0
6
RW
0
7
I2C1
0
UART0
0
UART1
0
RW
0
RW
0
UART2
0
RW
0
8
UART3
0
9
RW
0
MWPM0
0
RW
0
MPWM1
0
RW
0
ADC0
0
RW
0
ADC1
0
RW
0
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
PER2=0x4000_002C
0
ADC1 function enable
ADC0 function enable
MPWM1 function enable
MPWM0 function enable
UART3 function enable
UART2 function enable
UART1 function enable
UART0 function enable
I2C1 function enable
I2C0 function enable
SPI1 function enable
SPI0 function enable
PRELIMINARY
39
Z32F3841 Product Specification
PCER1
System Control Unit
Peripheral Clock Enable Register 1
To use the peripheral unit, its clock should be activated by writing ‘1’ to the corresponding bit in the PCER0/1
register. Before enabling its clock, the peripheral will not operate correctly.
To stop the clock of the peripheral unit, write ‘0’ to the corresponding bit in the PCER0/1 register, after which
the clock of the peripheral is stopped.
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
4
3
2
1
0
PS034603-0617
0
0
RW
RW
0
0
1
1
1
1
R
0
1
R
FRT
0
2
R
GPIOA
0
3
R
GPIOB
0
6
5
4
0
0
DMA
GPIOC
0
RW
0
GPIOD
RW
TIMER9
TIMER8
TIMER7
TIMER6
TIMER5
TIMER4
TIMER3
TIMER2
TIMER1
TIMER0
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
FRT
DMA
0
RW
0
GPIOE
0
7
RW
0
8
GPIOF
TIMER0
0
9
RW
TIMER1
0
RW
0
TIMER2
0
TIMER3
0
RW
0
RW
TIMER5
0
TIMER4
TIMER6
0
TIMER7
0
TIMER8
0
RW
0
RW
0
TIMER9
0
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
PCER1=0x4000_0030
TIMER9 clock enable
TIMER8 clock enable
TIMER7 clock enable
TIMER6 clock enable
TIMER5 clock enable
TIMER4 clock enable
TIMER3 clock enable
TIMER2 clock enable
TIMER1 clock enable
TIMER0 clock enable
GPIOF clock enable
GPIOE clock enable
GPIOD clock enable
GPIOC clock enable
GPIOB clock enable
GPIOA clock enable
FRT clock enable
DMA clock enable
Reserved
PRELIMINARY
40
Z32F3841 Product Specification
PCER2
System Control Unit
Peripheral Clock Enable Register 2
To use the peripheral unit, its clock should be activated by writing ‘1’ to the corresponding bit.
21
20
17
16
11
10
9
8
5
4
1
0
PS034603-0617
ADC1
ADC0
MPWM1
MPWM0
UART3
UART2
UART1
UART0
I2C1
I2C0
SPI1
SPI0
0
1
0
0
0
0
1
SPI0
0
2
0
0
0
1
RW
0
3
SPI1
0
4
RW
0
5
I2C0
0
6
RW
0
7
I2C1
0
UART0
0
UART1
0
RW
0
RW
0
UART2
0
RW
0
8
UART3
0
9
RW
0
MWPM0
0
RW
0
MPWM1
0
RW
0
ADC0
0
RW
0
ADC1
0
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
PCER2=0x4000_0034
0
ADC1 clock enable
ADC0 clock enable
MPWM1 clock enable
MPWM0 clock enable
UART3 clock enable
UART2 clock enable
UART1 clock enable
UART0 clock enable
I2C1 clock enable
I2C0 clock enable
SPI1 clock enable
SPI0 clock enable
PRELIMINARY
41
Z32F3841 Product Specification
CSCR
System Control Unit
Clock Source Control Register
The Z32F3841 MCU has multiple clock sources to generate internal operating clocks. Each clock source can
be enabled or disabled by the CSCR register.
This register is an 8-bit register.
CSCR=0x4000_0040
7
6
5
SXOSCEN
0
4
2
1
0
RINGOSCCON
IOSCCON
EOSCCON
10
00
00
RW
RW
RW
0
RW
SCCR
3
7
SXOSCEN
5
4
RINGOSCCON
3
2
IOSCCON
1
0
EOSCON
External Sub Oscillator Enable
0
Disable Sub Oscillator
1
Enable Sub Oscillator
Internal ring oscillator control
0X Stop internal sub oscillator
10 Enable internal sub oscillator
11 Enable internal sub oscillator divide by 2
Internal oscillator control
0X Stop internal oscillator
10 Enable internal oscillator
11 Enable internal oscillator divide by 2
External crystal oscillator control
0X Stop internal oscillator
10 Enable internal oscillator
11 Enable internal oscillator divide by 2
System Clock Control Register
The System Clock Control register is the source for the PLL system and clock selection.
FINSEL selects either the IOSC or the External OSC as the input to the PLL system.The System clock select
selects internal sub osciallator (Ring), External OSC, Internal OSC or PLL.
When changing FINSEL to MOSC ("1"), both internal OSC and external OSC should be alive, otherwise the
chip will malfunction.
SCCR=0x4000_0044
7
PS034603-0617
6
5
4
3
2
1
0
-
FINSEL
MCLKSEL
0000
0
00
R
RW
RW
2
FINSEL
1
0
MCLKSEL
PLL input source FIN select register
0
IOSC clock is used as FIN clock
1
MOSC clock is used as FIN clock
System clock select register
0X Internal sub oscillator
10 PLL bypassed clock
11 PLL output clock
PRELIMINARY
42
Z32F3841 Product Specification
CMR
System Control Unit
Clock Monitoring Register
You can monitor the internal clock and external osciallators. To enable monitoring, the
MCLKMNT/EOSCMNTSXOSCMNT bits must be set before the MCLKSTS, EOSCSTS, and SXOSCSTS bits
are valid.
Note: The EOSCSTS bit only checks for the EOSCSTS oscillation and does not check for stability. When the
system detects an MCLKFAIL interrupt, the MCLKREC bit determines if the system just dies or will auto
recover using the ROSC. In most cases, the system should auto recover to keep running. The Clock
Monitoring register is a 16-bit register.
Note: Oscillator clock statuses only refer to oscilliation and are not necessarly stable. After enabling a clock,
check the status for oscillation, then wait for stability before using the clock.
14
13
12
11
SXOSCIE
SXOSCFAIL
SXOSCSTS
MCLKMNT
MCLKIE
MCLKFAIL
MCLKSTS
EOSCMNT
EOSCIE
EOSCFAIL
EOSCSTS
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
RW
RW
WC1
WC1
RW
RW
WC1
WC1
RW
RW
WC1
WC1
MCLKREC
15
SXOSCMNT
MR=0x4000_0048
0
R
PS034603-0617
10
9
15
MCLKREC
11
SXOSCMNT
10
SXOSCIE
9
SXOSCFAIL
8
SXOSCSTS
7
MCLKMNT
6
MCLKIE
5
MCLKFAIL
4
MCLKSTS
3
EOSCMNT
2
EOSCIE
8
7
6
5
4
3
2
1
0
MCLK fail auto recovery
0
MCLK is changed to RINGOSC by default when
MCLKFAIL issued
1
MCLK auto recovery is disabled
Sub Oscillator monitoring enable
0
Sub Oscillator monitoring disabled
1
Sub Oscillator monitoring enabled
Sub Oscillator fail interrupt enable
0
Sub Oscillator fail interrupt disabled
1
Sub Oscillator fail interrupt enabled
Sub Oscillator fail interrupt
0
Sub Oscillator fail interrupt not occurred
1
Read : Sub Oscillator fail interrupt is pending
Write : Clear pending interrupt
Sub Oscillator clock status
0
Not oscillate
1
Sub oscillator is working normally
MCLK monitoring enable
0
MCLK monitoring disabled
1
MCLK monitoring enabled
MCLK fail interrupt enable
0
MCLK fail interrupt disabled
1
MCLK fail interrupt enabled
MCLK fail interrupt
0
MCLK fail interrupt not occurred
1
Read : MCLK fail interrupt is pending
Write : Clear pending interrupt
MCLK clock status
0
No clock is present on MCLK
1
Clock is present on MCLK
External oscillator monitoring enable
0
External oscillator monitoring disabled
1
External oscillator monitoring enabled
External oscillator fail interrupt enable
0
External oscillator fail interrupt disabled
PRELIMINARY
43
Z32F3841 Product Specification
PS034603-0617
1
EOSCFAIL
0
EOSCSTS
System Control Unit
1
External oscillator fail interrupt enabled
External oscillator fail interrupt
0
External oscillator fail interrupt not occurred
1
Read : External oscillator fail interrupt is pending
Write : Clear pending interrupt
External oscillator status
0
Not oscillate
1
External oscillator is working normally
PRELIMINARY
44
Z32F3841 Product Specification
NMIR
System Control Unit
NMI Control Register
The NMI Control register provides control and status for Non-Maskable Interrupt. There are 6 available NMI
sources. Write access key is required 0xA32 on NMIR[31:20] when writing to this register.
NMIR = 0x4000_004C
18
17
15
14
13
12
11
10
9
8
PS034603-0617
BODSTS
NIMPINEN
PROT1EN
0
0
0
0
0
1
0
NMIPINSTS
NMIINT
NMIPINDBEN
NMIINTSTS
PROT1STS
OVP1STS
PROT0STS
OVP0STS
WDTINTSTS
MCLKFAILSTS
BODSTS
0
LVDEN
MCLKFAILSTS
0
1
MCLKFAILEN
WDTSTS
0
2
WDTEN
OVP0STS
0
3
OVP0EN
PROT0STS
1
4
OVP1EN
OVP1STS
0
5
PROT0EN
PROT1STS
6
1
R WC1 RW
19
7
NMIINTSTS
CODE (‘h2)
8
NMIPINDBEN
ACCESS (‘h3)
9
NMIINT
REG (‘hA)
18 17 16 15 14 13 12 11 10
NMIPINSTS
31 30 29 28 27 26 25 24 23 22 21 20 19
0
0
0
0
0
0
R
R
R
R
R
R
R
R RW RW RW RW RW RW RW RW
NMI pin status bit
0
NMI pin is low.
1
NMI pin is high.
NMI interrupt bit, Write 1 to clear
0
NMI interrupt is not pending
1
NMI interrupt is pending
NMI pin debounce enable
0
Disable
1
Enable
NMI pin interrupt status bit
0
NMI interrupt is not pending
1
NMI interrupt is pending
MPWM1’s Protection interrupt status bit.
0
No PROT1 interrupt
1
PROT1 interrupt occurred
MPWM1’s Over Voltage Protection interrupt status bit
0
No OVP1 interrupt
1
OVP1 interrupt occurred
MPWM0’s Protection interrupt status bit.
0
No PROT0 interrupt
1
PROT interrupt occurred
MPWM0’s Over Voltage Protection interrupt status bit
0
No OVP0 interrupt
1
OVP0 interrupt occurred
WDT Interrrupt status bit
0
No WDT interrupt
1
WDT interrupt occurred
MCLK Fail interrupt status bit
0
No MCLK fail interrupt
1
MCLK fail interrupt occurred
BOD interrupt status bit
0
No BOD interrupt
1
BOD interrupt occurred
PRELIMINARY
45
Z32F3841 Product Specification
7
6
5
4
3
2
1
0
PS034603-0617
NMIPINEN
PROT1EN
OVP1EN
PROT0EN
OVP0EN
WDTINTEN
MCLKFAILEN
LVDEN
System Control Unit
NMI pin interrupt Enable
Write permission is required by PCU write enable sequence
0
Disable
1
Enable
MPWM1’s Protection interrupt enable for NMI interrupt
0
Disable
1
Enable
MPWM1’s Over Voltage Protection interrupt enable for NMI
interrupt
0
Disable
1
Enable
MPWM0’s Protection interrupt enable for NMI interrupt
0
Disable
1
Enable
MPWM0’s Over Voltage Protection interrupt enable for NMI
interrupt
0
Disable
1
Enable
WDT Interrrupt condition enable for NMI interrupt
0
Disable
1
Enable
MCLK Fail condition enable for NMI interrupt
0
Disable
1
Enable
LVD Detect condition enable for NMI interrupt
0
Disable
1
Enable
PRELIMINARY
46
Z32F3841 Product Specification
COR
System Control Unit
Clock Output Register
The Clock Output register controls enabling/disabling and provides a divider for the clock output. To output the
clock signal, you must enable the clock out function pin (See Chapter 5, Port Control Unit).
COR=0x4000_0050
7
6
5
4
3
1
-
CLKOEN
CLKODIV
000
0
1111
R
RW
RW
4
CLKOEN
3
0
CLKODIV
0
Clock output enable
0
CLKO is disabled and stay “L” output
1
CLKO Is enabled
Clock output divider value
CLKO = MCLK
𝐂𝐋𝐊𝐎 =
PS034603-0617
2
PRELIMINARY
(CLKODIV = 0)
𝑴𝑪𝑳𝑲
𝟐 ∗ (𝐂𝐋𝐊𝐎𝐃𝐈𝐕 + 𝟏)
(𝑪𝑳𝑲𝑶𝑫𝑰𝑽 > 0)
47
Z32F3841 Product Specification
PLLCON
System Control Unit
PLL Control Register
Integrated PLL can synthesize the high speed clock for extremely high performance of the CPU from either
the internal oscillator (IOSC) or the external oscillator (MOSC). The PLL Control register provides the
configuration for the PLL system. By default, the PLL system is in reset mode and disabled. You must negate
the reset and enable the PLL to operate (bits 14 and 15 must be set). The Bypass bit must be set to output the
PLL clock. The active clock is defined in SCCR bit 2 (FIN).
To calculate the PLL output:
PLL Out = ( (Active clock / PREDIV) * FBCTRL) / POSTDI
Note: (Active Clock/PREDIV) * FBCTRL) must be below 224
MHz else PLL will not lock.
PLLCON=0x4000_0060
0
0
RW
RW
RW
R
9
8
0
0
0
0
0000
0000
RW
RW
RW
15
PLLRSTB
14
PLLEN
13
BYPASS
12
LOCK
8
PREDIV
7
4
FBCTRL
3
0
PS034603-0617
7
POSTDIV
6
5
4
3
PLL reset
0
PLL reset is asserted
1
PLL reset is negated
PLL enable
0
PLL is disabled
1
PLL is enabled
FIN bypass
0
FOUT is bypassed as FIN
1
FOUT is PLL output
LOCK status
0
PLL is not locked
1
PLL is locked
FIN predivider
0
FIN divided by 1
1
FIN divided by 2
Feedback control
0000
M=8
0001
M = 12
0010
M = 14
0011
M = 16
0100
M = 18
0101
M = 20
0110
M = 22
0111
M = 28
Post divider control
000
N=1
001
N=2
010
N=3
011
N =4
100
N=6
101
N=8
110
N = 12
111
N =16
PRELIMINARY
2
1
0
POSTDIV
0
10
FBCTRL
0
11
PREDIV
LOCKSTS
12
BYPASS
13
PLLEN
14
PLLRSTB
15
1000
1001
1010
1011
1100
1101
1110
1111
M = 30
M =32
M = 38
M = 40
Not available
48
Z32F3841 Product Specification
VDCCON
System Control Unit
VDC Control Register
The on chip VDC control register is shown below.
VDCTRIM is used for the trim value of VDC output. To modify the VDCTRIM bit, VDCTE should write
“1”simultaneously. VDCWDLY value can be written with writing “1” to VDCDE bit simultaneously.
0
0
PS034603-0617
0
0
RW
W
8
0
0
0x0F
W
RW
VDCTRIM
00
9
VDCWDLY
0
VDCTE
0
W
BMRTRIM
BMRTE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VDCDE
VDCCON=0x4000_0064
0
0
0
0000
0
0
0
RW
31
BMRTE
26
24
23
BMRTRIM
19
16
8
VDCTRIM
7
0
VDCWDLY
VDCTE
VDCDE
0
0
0
7
6
5
4
3
2
1
0
Reference BGR trim write enable.
0
BMRTRIM field is not updated by writing
1
BMRTRIM filed can be updated by writing
Reference BGR output voltage trim value
VDCTRIM value write enable. Write only with VDCTRIM
value.
0
VDCTRIM field is not updated by writing
1
VDCTRIM filed can be updated by writing
VDC output voltage trim value
VDCWDLY value write enable. Write only with VDCWDLY
value
0
VDCWLDLY field is not updated by writing
0
VDCWLDLY field can be updated by writing
VDC warm-up delay count value.
When SCU is waked up from powerdown mode, the warm-up
delay is inserted for VDC output being stabilized.
The amount of delay can be defined with this register value
7F : 2msec
PRELIMINARY
49
Z32F3841 Product Specification
LVDCON
System Control Unit
LVD Control Register
The on chip brown-out detector control register is a 32-bit register.
0
0
0
0
0
PS034603-0617
0
0
23
BODTE
17
16
BODTRIM
9
8
BODSEL
0
BODEN
5
4
3
2
1
0
0
0
0
0
0
0
1
BODSEL
00
6
BODEN
0
7
RW
0
8
BODLVL
0
9
0
0
0
0
0
00
RW
0
SELEN
0
RW
0
RW
0
RW
0
BODTRIM
BODTE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
LVDCON=0x4000_0068
0
BODTRIM value write enable. Write only with BODTRIM
value.
0
BODTRIM field is not updated by writing
1
BODTRIM filed can be updated by writing
BOD voltage level trim value
It can writable when trim enable mode in FMC
BOD detect level select
00 BOD detect level is 1.8V- 50mV
01 BOD detect level is 2.2V – 50mV
10 BOD detect level is 2.7V -50mV
11 BOD detect level is 4.3V – 50mV
BOD Function enable
0
BOD is not enabled
1
BOD is enabled
PRELIMINARY
50
Z32F3841 Product Specification
IOSCTRIM
System Control Unit
Internal OSC Trim Register
The Internal Oscillator Frequency Trim register. Is a 32-bit register. All trim bits are writable when trim mode in
FMC is enabled.
IOSCTRIM=0x4000_006C
0
EOSCR
23
TSLEN
18
16
15
TSL[2:0]
13
8
7
LTM/LT
4
0
UDCH/UDCL
0
0000
00
0
0
0
3
2
1
0
UDCL
000
4
00
000
RW
0
5
UDCH
0
6
RW
0
UDCEN
0
W
0
LTM
0
7
RW
0
8
LT
0
9
RW
0
LTEN
0
W
0
RW
0
W
0
TSL
TSLEN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TSL trim value write enable. Write only with TSL trim value.
0
TSL field is not updated by writing
1
TSL filed can be updated by writing
TSL trim value
LTEN
LTM/LT value write enable. Write only with LTM/LT value
0
LT field is not updated by writing
1
LT filed can be updated by writing
Internal oscillator LT trim value
UDCEN
UDCH/UDCL value write enable. Write only with UDC value
0
UDC field is not updated by writing
1
UDC filed can be updated by writing
Internal oscillator UDC trim value
External Oscillator Control Register
The External Oscillator Control register is a 16-bit register. The external main crystal oscillator has two
characteristics. For noise immunity, NMOS amp type is recommended and for the low power characteristic,
INV amp type is recommended.
EOSCR=0x4000_0080
11
10
0
0
0
0
0
0
W
PS034603-0617
15
ISELEN
9
8
ISEL
9
8
7
00
0
RW
W
6
5
4
3
2
0
0
0
0
0
1
0
NCSEL
12
NCEN
13
ISEL
14
ISELEN
15
10
RW
Write enable of bit field ISEL.
0
Write access of ISEL field is masked
1
Write access of ISEL field is accepted
Select current. Default 0x0
00 Minimum current driving option
01 Low current driving option
PRELIMINARY
51
Z32F3841 Product Specification
PS034603-0617
7
NCEN
1
0
NCSEL
System Control Unit
10 High current driving option
11 Maximum current driving option
Write enable of bit field NCSEL
0
Write access of NCSEL field is masked
1
Write access of NCSEL field is accepted
Select noise cancel delay , default 0x2
00 10ns
01 15ns
10 20ns
11 25ns
PRELIMINARY
52
Z32F3841 Product Specification
EMODR
System Control Unit
External Mode Status Register
The External Mode Status register shows external mode pin status while booting. This register is an 8-bit
register.
EMODR=0x4000_0084
7
PS034603-0617
6
5
4
2
1
0
SCANMD
TEST
BOOT
0x0
0
0
-
R
R
R
R
2
SCANMD
1
TEST
0
BOOT
3
SCANMD pin level
0
SCANMD pin is low
1
SCANMD pin is high
TEST pin level
0
TEST pin is low
1
TEST pin is high
BOOT pin level
0
BOOT(PC11) pin is low
1
BOOT(PC11) pin is high
PRELIMINARY
53
Z32F3841 Product Specification
DBCLK1
System Control Unit
Debounce Clock Control Register 1
The Debounce Clock Control Register 1 is a register for PA and PB port pins.
MCCR4=0x4000_009C
0
PS034603-0617
0
000
0x01
RW
RW
26
24
PBDCSEL
23
16
10
8
PBDDIV
7
0
PADDIV
PADCSEL
0
0
0
0
0
8
7
6
5
4
3
PADDIV
0
9
PADCSEL
0
PBDDIV
0
PBDCSEL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
000
0x01
RW
RW
2
1
0
Debounce Clock for Port B source select bit
0xx
RING OSC 1MHz
100
MCLK (bus clock)
101
INT OSC 20MHz
110
External Main OSC
111
PLL Clock
PORT B Debounce Clock N divider
Debounce Clock for Port A source select bit
0xx
RING OSC 1MHz
100
MCLK (bus clock)
101
INT OSC 20MHz
110
External Main OSC
111
PLL Clock
PORT A Debounce Clock N divider
PRELIMINARY
54
Z32F3841 Product Specification
DBCLK2
System Control Unit
Debounce Clock Control Register 2
The Debounce Clock Control Register 2 is a register for PC and PD port pins.
MCCR5=0x4000_00A0
0
PS034603-0617
0
000
0x01
RW
RW
26
24
PDDCSEL
23
16
10
8
PDDDIV
7
0
PCDDIV
PCDCSEL
0
0
0
0
0
8
7
6
5
4
3
PCDDIV
0
9
PCDCSEL
0
PDDDIV
0
PDDCSEL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
000
0x01
RW
RW
2
1
0
Debounce Clock for PORT D source select bit
0xx
RING OSC 1MHz
100
MCLK (bus clock)
101
INT OSC 20MHz
110
External Main OSC
111
PLL Clock
PORT D Debounce Clock N divider
Debounce Clock for PORT C source select bit
0xx
RING OSC 1MHz
100
MCLK (bus clock)
101
INT OSC 20MHz
110
External Main OSC
111
PLL Clock
PORT C Debounce Clock N divider
PRELIMINARY
55
Z32F3841 Product Specification
DBCLK3
System Control Unit
Debounce Clock Control Register 3
The Debounce Clock Control Register 3 is a register for PE and PF port pins.
0x4000_00A4
0
PS034603-0617
0
000
0x00
RW
RW
26
24
PFDCSEL
23
16
10
8
PFDDIV
7
0
PEDDIV
PEDCSEL
0
0
0
0
0
8
7
6
5
4
3
PEDDIV
0
9
PEDCSEL
0
PFDDIV
0
PFDCSEL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
000
0x01
RW
RW
2
1
0
Debounce Clock for PORT F source select bit
0xx
RING OSC 1MHz
100
MCLK (bus clock)
101
INT OSC 20MHz
110
External Main OSC
111
PLL Clock
PORT F Debounce Clock N divider
Debounce Clock for PORT E source select bit
0xx
RING OSC 1MHz
100
MCLK (bus clock)
101
INT OSC 20MHz
110
External Main OSC
111
PLL Clock
PORT E Debounce Clock N divider
PRELIMINARY
56
Z32F3841 Product Specification
MCCR1
System Control Unit
Miscellaneous Clock Control Register 1
The Miscellaneous Clock Control Register 1 sets Trace and SysTick clock sources and dividers.
MCCR1=0x4000_0090
0
W
PS034603-0617
0
100
0x04
RW
RW
10
8
TRCSEL
7
0
10
8
TRACEDIV
7
0
STDIV
STCSEL
0
0
0
0
0
8
7
6
5
4
3
STDIV
0
9
STCSEL
0
TRACEDIV
0
TRCSEL
TRCPOL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
000
0x01
RW
RW
2
1
0
TRACE Clock source select bit
0xx
RING OSC 1MHz
100
MCLK (bus clock)
101
INT OSC 20MHz
110
External Main OSC
111
PLL Clock
TRACE Clock N divider
SYSTIC Clock source select bit
0xx
RING OSC 1MHz
100
MCLK (bus clock)
101
INT OSC 20MHz
110
External Main OSC
111
PLL Clock
SYSTIC Clock N divider
PRELIMINARY
57
Z32F3841 Product Specification
MCCR2
System Control Unit
Miscellaneous Clock Control Register 2
The Miscellaneous Clock Control Register 2 is the clock source and divider register for the MPWM generator
units.
MCCR2=0x4000_0094
0
PS034603-0617
0
000
0x00
RW
RW
10
8
PWM1CSEL
7
0
10
8
PWM1DIV
7
0
PWM0DIV
PWM0CSEL
0
0
0
0
0
8
7
6
5
4
3
PWM0DIV
0
9
PWM0CSEL
0
PWM1DIV
0
PWM1CSEL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
000
0x00
RW
RW
2
1
0
PWM1 Clock source select bit
0xx
RING OSC 1MHz
100
MCLK (bus clock)
101
INT OSC 20MHz
110
External Main OSC
111
PLL Clock
PWM1 Clock N divider
PWM0 Clock source select bit
0xx
RING OSC 1MHz
100
MCLK (bus clock)
101
INT OSC 20MHz
110
External Main OSC
111
PLL Clock
PWM0 Clock N divider
PRELIMINARY
58
Z32F3841 Product Specification
MCCR3
System Control Unit
Miscellaneous Clock Control Register 3
The Miscellaneous Clock Control Register 3 is the Timer EXT0 Clock and Watch Dog Timer clock control
register.
MCCR3=0x4000_0098
0
PS034603-0617
0
000
0x01
RW
RW
10
8
TEXT0CSEL
7
0
10
8
TEXT0DIV
7
0
WDTDIV
WDTCSEL
0
0
0
0
0
8
7
6
5
4
3
WDTDIV
0
9
WDTCSEL
0
TEXT0DIV
0
TEXT0CSEL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
000
0x01
RW
RW
2
1
0
TEXT0 Clock source select bit
0xx
RING OSC 1MHz
100
MCLK (bus clock)
101
INT OSC 20MHz
110
External Main OSC
111
PLL Clock
TEXT0 Clock N divider
WDT Clock source select bit
0xx
RING OSC 1MHz
100
MCLK (bus clock)
101
INT OSC 20MHz
110
External Main OSC
111
PLL Clock
WDT Clock N divider
PRELIMINARY
59
Z32F3841 Product Specification
MCCR4
System Control Unit
Miscellaneous Clock Control Register 4
The Miscellaneous Clock Control Register 4 is the alterntative ADC and NMI Debounce Clock Control register.
0x4000_00A8
0
PS034603-0617
0
000
0x00
RW
RW
26
24
ADCCSEL
23
16
10
8
ADCCDIV
7
0
NMIDDIV
NMIDCSEL
0
0
0
0
0
8
7
6
5
4
3
NMIDDIV
0
9
NMICSEL
0
ADCCDIV
0
ADCCSEL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
000
0x01
RW
RW
2
1
0
ADC clock source select bit
0xx
RING OSC 1MHz
100
MCLK (bus clock)
101
INT OSC 20MHz
110
External Main OSC
111
PLL Clock
ADC Clock N divider
Debounce Clock for NMI source select bit
0xx
RING OSC 1MHz
100
MCLK (bus clock)
101
INT OSC 20MHz
110
External Main OSC
111
PLL Clock
NMI Debounce Clock N divider
PRELIMINARY
60
Z32F3841 Product Specification
System Control Unit
Functional Description
System Clock Setup Procedure Example for the Internal Clock with PLL
Configure the FM.CFG register to the maximum wait
Enable the internal clock IOSC in the CSCR register.
Write 0x02 to the SCCR register (system clock control register) to select the IOSC as the PLL source
(FIN) with bypassing the PLL output
In the PLLCON register, Set bits 14,15 to enable PLL, clear bit 13 to bypass PLL output and configure
bits 0-8 to the PREDIV/FBCTRL/POSTDIV for desired PLL output. For full speed, the PLLCON
register would be set to 0xC100
Wait for the PLL to be locked by monitoring the LOCK bit (bit 12) in the PLLCON register.
Set bit 13 of the PLLCON register to enable the PLL output
Set bit 0 of SCCR to enable the PLL for the system clock
Set FM.CFG for the appropriate Flash Wait states for the speed selected.
System Clock Setup Procedure Example for the External Clock with PLL
Enable the Port C peripheral and clock in the SCU PER1 and PCER1 registers
Unlock the Port Controller using the PORTEN register as defined in PORT CONTROL UNIT (PCU)
Enable the Alternative function 11b for pins 12 and 13 on PORT C through the PCC_MR register
Set the Pin type for pins 12 and 13 on PORT C to analog (11b)
Lock the Port Controller by writing any value to PORTEN register
Configure the FM.CFG register to the maximum wait
If not already enabled, enable Internal oscillator in CSCR
Set bit 3 in the CMR register to monitor External Oscillator
Enable External Oscillator in CSCR register
Wait for bit 0 of the CMR register to be set. Note: if the external oscillator does not start, this bit will
never be set.
Wait for an additional time (more than 1 ms) to allow the oscillator to stabilize
Write 0x06 to the SCCR register (system clock control register) to select the External Oscillator as the
PLL source (FIN)
Set PLLCON high byte (8-15) to 0xC and low byte (0-7) to the FBCTRL/POSTDIV for desired PLL
output.
Wait until bit 12 of PLLCON is set. Note: if the PLL does not lock, this bit will never be set.
Set bit 13 to enable the PLL output
Set bit 0 of SCCR to enable the PLL for the system clock
Set FM.CFG for the appropriate Flash Wait states for the speed selected.
To Enable Clock Out for monitoring actual clock output
Enable the Port C peripheral and clock in the SCU PER1 and PCER1 registers
Unlock the Port Controller using the PORTEN register as defined in PORT CONTROL UNIT (PCU)
Enable the Alternative function 01b for pin 9 on PORT C through the PCC_MR register
Set the Pin type for pin 9 on PORT C to output (00b)
Lock the Port Controller by writing any value to PORTEN register
Set bit 4 of the Clock Output Register (COR) to enable the output
Configure the CLKODIV to the desired output divider
PS034603-0617
PRELIMINARY
61
Z32F3841 Product Specification
Port Control Unit
5. Port Control Unit
Overview
Port Control Unit (PCU) controls the external I/Os as follows:
Set the multiplex state of each pin (for alternative functions)
Set external signal type (Analog / Push-Pull output /Open Drain output /Input)
Set enable/monitor/trigger type for interrupts for each pin
Set internal pull-up register control for each pin
Set debounce for each pin
Note: You must enable both the Port Peripheral and the Port Peripheral CLOCK in PER1/PCER1 to use the
pins of the port.
Figure 5.1 shows a block diagram of the PCU. Figures 2.2 and 2.3 show I/O Port Block diagrams.
APB BUS
Function I/Os
NVIC
PORT
CONTROL
FUNCTION
MUX
PA/PB/PC
PD/PE/PF
PORTs
INTERRUPT
CONTROL
Figure 5.1. Block Diagram
PS034603-0617
PRELIMINARY
62
Z32F3841 Product Specification
Port Control Unit
VDDIO
Pull-up Enable
VDDIO
VDDIO
Open-drain Enable
Input Mode
Port MUX
PIN
-ad
GPIO output
00
01
10
11
Function 1 Output
Function 1 Output
Function 3 Output
Analog Disable
0
Function Input
1
Debounce
Logic
Debounce Enable
Debounce Count
Analog Input
(AN0~AN15,
XTALI,XTALO,SXIN,S
XOUT)
Figure 5.2. I/O Port Block Diagram (ADC and External Oscillator Pins)
VDDIO
Pull-up Enable
VDDIO
VDDIO
Open-drain Enable
Input Mode
Port MUX
PIN
-ad
GPIO output
Function 1 Output
Function 1 Output
00
01
10
11
Function 3 Output
Analog Disable
Function Input
0
1
Debounce
Logic
Debounce Enable
*
Debounce Count
Figure 5.3. I/O Port Block Diagram (General I/O Pins)
PS034603-0617
PRELIMINARY
63
Z32F3841 Product Specification
Port Control Unit
Pin Multiplexing
GPIO pins have alternative function pins. Table 5.1 lists the pin multiplexing information.
Table 5.1. GPIO Alternative Function
FUNCTION
PORT
PA
PB
00
01
10
11
0
PA0*
AN0
1
PA1*
AN1
2
PA2*
AN2
3
PA3*
AN3
4
PA4*
T0IO
AN4
5
PA5*
T1IO
AN5
6
PA6*
T2IO
AN6
7
PA7*
T3IO
AN7
8
PA8*
AN8
9
PA9*
AN9
10
PA10*
AN10
11
PA11*
AN11
12
PA12*
SS0
AN12
13
PA13*
SCK0
AN13
14
PA14*
MOSI0
AN14
15
PA15*
MISO0
AN15
0
PB0*
MP0UH
1
PB1*
MP0UL
2
PB2*
MP0VH
3
PB3*
MP0VL
4
PB4*
MP0WH
5
PB5*
MP0WL
6
PB6*
PRTIN0
WDTO
7
PB7*
OVIN0
STBYO
8
PB8*
PRTIN1
RXD3
9
PB9*
OVIN1
TXD3
10
PB10*
MP1UH
11
PB11*
MP1UL
12
PB12*
MP1VH
13
PB13*
MP1VL
14
PB14*
MP1WH
15
PB15*
MP1WL
(2)
(2)
(*) mark indicates default pin setting.
(2)
mark indicates secondary port
PS034603-0617
PRELIMINARY
64
Z32F3841 Product Specification
Port Control Unit
Table 5.1. GPIO Alternative Function (Continued)
FUNCTION
PORT
PC
PD
00
01
10
11
(2)
0
PC0
TCK/SWCLK*
RXD0
1
PC1
TMS/SWDIO*
RXD0(2)
2
PC2
TDO/SWO*
3
PC3
TDI*
4
PC4
nTRST*
T0IO
5
PC5*
RXD1
T1IO
6
PC6*
TXD1
T2IO
7
PC7*
SCL0
T3IO
8
PC8*
SDA0
T4IO
9
PC9*
CLKO
T8IO
10
PC10
nRESET*
11
PC11/BOOT*
12
PC12*
13
PC13*
14
PC14*
RXD0
MISO0
(2)
15
PC15*
TXD0
MOSI0
(2)
0
PD0*
SS1
SXIN
1
PD1*
SCK1
SXOUT
2
PD2*
MOSI1
3
PD3*
MISO1
4
PD4*
SCL1
AN16
5
PD5*
SDA1
AN17
6
PD6*
TXD2
7
PD7*
RXD2
8
PD8*
(2)
(2)
(2)
(2)
(2)
T8IO(2)
XIN
XOUT
I
AN19
(2)
WDTO
(2)
T6IO
AN18
9
PD9*
T7IO
STBO
10
PD10*
AD0SOC
T0IO
11
PD11*
AD0EOC
T1IO
12
PD12*
AD1SOC
T2IO
13
PD13*
AD1EOC
T3IO
14
PD14*
SS0*
15
PD15*
SCK0*
(*) mark indicates default pin setting.
(2)
mark indicates secondary port
PS034603-0617
PRELIMINARY
65
Z32F3841 Product Specification
Port Control Unit
Table 5.1. GPIO Alternative Function (Continued)
FUNCTION
PORT
PE
00
01
10
0
PE0
TXD1
1
PE1
RXD1
2
PE2
3
PE3
AD0O*
SCL0*
4
PE4
AD1O*
SDA0*
5
PE5*
T5IO
6
PE6*
T5IO
7
PE7*
T6IO
8
PE8*
T7IO
9
PE9*
T8IO
10
PE10
T9IO
11
PE11
12
PE12*
T1IO
13
PE13*
T2IO
14
PE14*
11
T4I(3)/T3O(5)
(2)
(2)
(2)
(2)
(2)
(2)
SCL1*
(2)
SDA1*
(2)
TXD2*
(2)
RXD2*
T0IO
T3IO
(2)
15
PE15*
0
PF0*
1
PF1*
2
PF2*
AN20
3
PF3*
AN21
4
PF4*
5
PF5*
T4IO
PF
(*) mark indicates default pin setting.
(2)
mark indicates secondary port
PS034603-0617
PRELIMINARY
66
Z32F3841 Product Specification
Port Control Unit
Registers
The base address of the PCU block is 0x4000_1000.
Table 5.2. Base Address of Port
PORT
ADDRESS
PA
0x4000_1000
PB
0x4000_1100
PC
0x4000_1200
PD
0x4000_1300
PE
0x4000_1400
PF
0x4000_1500
Table 5.3. PCU Register Map
PS034603-0617
Register
Offset
R/W
Description
PCn.MR
0x--00
R/W
Port n pin mux select register
PCn.CR
0x--04
R/W
Port n pin control register
PCn.PCR
0x--08
R/W
Port n internal pull-up control register
PCn.DER
0x--0C
R/W
Port n debounce register
PCn.IER
0x--10
R/W
Port n interrupt enable register
PCn.ISR
0x--14
R/W
Port n interrupt status register
PCn.ICR
0x--18
R/W
Port n interrupt control register
PORTEN
0x1FF0
R/W
Port Access enable
PRELIMINARY
67
Z32F3841 Product Specification
PCA.MR
Port Control Unit
Port A Pin Mux Register
The Port A Pin Mux register is the PA port mode select register. This register and the PERx and PCERx
registers must be configured correctly before using the port to guarantee its functionality. PERx enables the
port and PCERx enables the clock to the port.
PCA.MR=0x4000_1000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
PA7
PA6
PA5
9
8
PA4
7
6
PA3
5
4
PA2
3
2
PA1
1
0
PA0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
SELECTION BIT
PORT
01
10
11
PA0
PA0
AN0
PA1
PA1
AN1
PA2
PA2
AN2
PA3
PA3
AN3
PA4
PA4
T0IO
AN4
PA5
PA5
T1IO
AN5
PA6
PA6
T2IO
AN6
PA7
PA7
T3IO
AN7
PA8
PA8
AN8
PA9
PA9
AN9
PA10
PA10
AN10
PA11
PA11
AN11
PA12
PA12
SS0
AN12
PA13
PA13
SCK0
AN13
PA14
PA14
MOSI0
AN14
PA15
PA15
MISO0
AN15
nd
*:2
PS034603-0617
00
function
PRELIMINARY
68
Z32F3841 Product Specification
PCB.MR
Port Control Unit
Port B Pin Mux Register
The Port B Pin Mux register is the PB port mode select register. This register and the PERx and PCERx
registers must be configured correctly before using the port to guarantee its functionality. PERx enables the
port and PCERx enables the clock to the port.
PCB.MR=0x4000_1100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PB15
PB14
PB13
PB12
PB11
PB10
PB9
PB8
PB7
PB6
PB5
9
8
PB4
7
6
PB3
5
4
PB2
3
2
PB1
1
0
PB0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
SELECTION BIT
PORT
PS034603-0617
00
01
10
PB0
PB0
MP0UH
PB1
PB1
MP0UL
PB2
PB2
MP0VH
PB3
PB3
MP0VL
PB4
PB4
MP0WH
T9IO
PB5
PB5
MP0WL
T9IO(2)
PB6
PB6
PRTIN0
WDTO
PB7
PB7
OVIN0
STBYO
PB8
PB8
PRTIN1
RXD3
TXD3
PB9
PB9
OVIN1
PB10
PB10
MP1UH
PB11
PB11
MP1UL
PB12
PB12
MP1VH
PB13
PB13
MP1VL
PB14
PB14
MP1WH
PB15
PB15
MP1WL
11
(2)
(2)
PRELIMINARY
69
Z32F3841 Product Specification
PCC.MR
Port Control Unit
Port C Pin Mux Register
The Port C Pin Mux register is the PC port mode select register. This register and the PERx and PCERx
registers must be configured correctly before using the port to guarantee its functionality. PERx enables the
port and PCERx enables the clock to the port.
PCC.MR=0x4000_1200
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
PC7
PC6
PC5
9
8
7
PC4
6
PC3
5
4
PC2
3
2
PC1
1
0
PC0
00
00
00
00
00
01
00
00
00
00
00
01
01
01
01
01
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
SELECTION BIT
PORT
01
10
PC0
TCK/SWCLK*
RXD0
PC1
PC1
TMS/SWDIO*
TXD0(2)
PC2
PC2
TDO/SWO*
PC3
PC3
TDI*
PC4
PC4
nTRST*
T0IO
PC5
PC5
RXD1
T1IO
PC6
PC6
TXD1
T2IO
PC7
PC7
SCL0
T3IO
PC8
PC8
SDA0
T4IO
PC9
T8IO
PC9
CLKO
PC10
PC10
nRESET*
PC11
PC11/BOOT*
PC12
PC12
PC13
PC13
(2)
(2)
(2)
(2)
(2)
T8IO(2)
XIN
XOUT
PC14
PC14
RXD0
MISO0
(2)
PC15
PC15
TXD0
MOSI0
(2)
nd
11
(2)
PC0
*:2
PS034603-0617
00
function
PRELIMINARY
70
Z32F3841 Product Specification
PCD.MR
Port Control Unit
Port D Pin Mux Register
The Port D Pin Mux register is the PD port mode select register. This register and the PERx and PCERx
registers must be configured correctly before using the port to guarantee its functionality. The PERx enables
the port and PCERx enables the clock to the port.
PCD.MR=0x4000_1300
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
9
8
7
PD4
6
PD3
5
4
PD2
3
2
PD1
1
0
PD0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
SELECTION BIT
PORT
01
10
11
PD0
PD0
SS1
SXIN
PD1
PD1
SCK1
SXOUT
PD2
PD2
MOSI1
PD3
PD3
MISO1
PD4
PD4
SCL1
AN16
PD5
PD5
SDA1
AN17
PD6
PD6
TXD2
AN18
PD7
PD7
RXD2
AN19
PD8
PD8
T6IO
WDTO
PD9
PD9
T7IO
STBO
PD10
PD10
AD0SOC
T0IO
PD11
PD11
AD0EOC
T1IO
PD12
PD12
AD1SOC
T2IO
PD13
PD13
AD1EOC
T3IO
PD14
PD14
SS0*
PD15
PD15
SCK0*
*:2
PS034603-0617
00
nd
function
PRELIMINARY
71
Z32F3841 Product Specification
PCE.MR
Port Control Unit
Port E Pin Mux Register
The Port E Pin Mux register is the PE port mode select register. This register and the PERx and PCERx
registers must be configured properly before using the port to guarantee its functionality. The PERx enables
the port and PCERx enables the clock to the port.
PCE.MR=0x4000_1400
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
PE7
PE6
PE5
9
8
PE4
7
6
PE3
5
4
PE2
3
2
PE1
1
0
PE0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
SELECTION BIT
PORT
00
01
10
PE0
PE0
TXD1
PE1
PE1
RXD1
PE2
PE2
T4I(3)/T3O(5)
PE3
PE3
SCL0*
PE4
PE4
SDA0*
PE5
PE5
T5IO
PE6
PE6
T5IO
PE7
PE7
T6IO
PE8
PE8
T7IO
PE9
PE9
T8IO
PE10
PE10
T9IO
PE11
PE11
PE12
PE13
(2)
(2)
(2)
(2)
(2)
PE12
PE13
T0IO
(2)
SCL1*
T1IO
(2)
SDA1*
T2IO
(2)
TXD2*
RXD2*
PE14
PE14
T3IO
(2)
PE15
PE15
T4IO
(2)
nd
11
rd
* : 2 function , ** : 3 function
PS034603-0617
PRELIMINARY
72
Z32F3841 Product Specification
PCF.MR
Port Control Unit
Port F Pin Mux Register
The Port F Pin Mux register is the PF port mode select register. This register and the PERx and PCERx
registers must be configured correctly before using the port to guarantee its functionality. The PERx enables
the port and PCERx enables the clock to the port.
PCF.MR=0x4000_1500
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PF5
00
00
00
00
00
00
00
00
00
8
PF4
7
6
PF3
5
4
PF2
3
2
PF1
1
0
PF0
00
00
00
00
00
00
RW
RW
RW
RW
RW
RW
SELECTION BIT
PORT
PS034603-0617
00
9
00
01
10
11
PF0
PF0
PF1
PF1
PF2
PF2
AN20
PF3
PF3
AN21
PF4
PF4
PF5
PF5
PRELIMINARY
73
Z32F3841 Product Specification
PCn.CR
Port Control Unit
Port n Pin Control Register (Except for PCC.CR)
The Port n Pin Control register handles the input or output control of each port pin. Each pin can be
configured as input pin, output pin, or open-drain pin.
PCA.CR=0x4000_1004, PCB.CR=0x4000_1104
PCD.CR=0x4000_1304, PCE.CR=0x4000_1404, PCF.CR=0x4000_1504
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Pn
5.1.1
Port control
00 Push-pull output
01 Open-drain output
10 Input
11 Analog
PCC.CR
Port C Pin Control Register
The Port C Pin Control register handles the input or output control of each port pin. Each pin can be
configured as input pin, output pin, or open-drain pin.
PCC.CR=0x4000_1204
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
9
8
P4
7
6
P3
5
4
P2
3
2
P1
1
0
P0
11
11
11
11
10
10
11
11
11
11
11
10
10
00
10
10
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Pn
PCn.PCR
Port control
00 Push-pull output
01 Open-drain output
10 Input
11 Analog
Port n Pull-up Resistor Control Register
Every pin in the port has on-chip pull-up resistors which can be configured by the Port n Pull-up Resistor
Control registers.
PUE14
PUE13
PUE12
PUE11
PUE10
PUE9
PUE8
7
6
5
4
3
2
1
0
PUE0
8
PUE1
9
PUE2
10
PUE3
11
PUE4
12
PUE5
13
PUE6
14
PUE7
15
PUE15
PCA.PCR=0x4000_1008, PCB.PCR=0x4000_1108, PCC.PCR=0x4000_1208
PCD.PCR=0x4000_1308, PCE.PCR=0x4000_1408, PCF.PCR=0x4000_1508
0000
R/W
n
PS034603-0617
PUEn
Port pull-up control
PRELIMINARY
74
Z32F3841 Product Specification
0
1
PCn.DER
Port Control Unit
Disable pull-up resistor
Enable pull-up resister
Port n Debounce Enable Register
Every pin in the port has a digital debounce filter which can be configured by the Port n Debounce Enable
registers. The Debounce clock can be configured in the DBCLKx registers in the SCU.
PDE14
PDE13
PDE12
PDE11
PDE10
PDE9
PDE8
7
6
5
4
3
2
1
0
PDE0
8
PDE1
9
PDE2
10
PDE3
11
PDE4
12
PDE5
13
PDE6
14
PDE7
15
PDE15
PCA.DER=0x4000_100C, PCB.DER=0x4000_110C, PCC.DER=0x4000_120C
PCD.DER=0x4000_130C, PCE.DER=0x4000_140C, PCF.DER=0x4000_150C
0000
RW
n
PS034603-0617
PDEn
Pin debounce enable
0
Disable debounce filter
1
Enable debounce filter
PRELIMINARY
75
Z32F3841 Product Specification
PCn.IER
Port Control Unit
Port n Interrupt Enable Register
Each individual pin can be an external interrupt source. Edge trigger interrupt and level trigger interrupt are
both supported. Interrupt mode can be configured by setting the Port n Interrupt Enable registers
PCA.IER=0x4000_1010, PCB.IER=0x4000_1110, PCC.IER=0x4000_1210
PCD.IER=0x4000_1310, PCE.IER=0x4000_1410, PCF.IER=0x4000_1510
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
PIE15
PIE14
PIE13
PIE12
PIE11
PIE10
PIE9
PIE8
PIE7
PIE6
PIE5
PIE4
PIE3
PIE2
PIE1
PIE0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PIEn
PCn.ISR
8
7
6
5
4
3
2
1
0
Pin interrupt enable
00 Interrupt disabled
01 Enable interrupt as level trigger mode
10 Reserved
11 Enable interrupt as edge trigger mode
Port n Interrupt Status Register
When an interrupt is delivered to the CPU, the interrupt status can be detected by reading the Port n Interrupt
Status register. This register reports a source pin of interrupt and a type of interrupt.
PCA.ISR=0x4000_1014, PCB.ISR=0x4000_1114, PCC.ISR=0x4000_1214
PCD.ISR=0x4000_1314, PCE.ISR=0x4000_1414, PCF.ISR=0x4000_1514
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
PIS15
PIS14
PIS13
PIS12
PIS11
PIS10
PIS9
PIS8
PIS7
PIS6
PIS5
PIS4
PIS3
PIS2
PIS1
PIS0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PISn
PS034603-0617
8
7
6
5
4
3
2
1
0
Pin interrupt status
00 No interrupt event
01 Low level interrupt or Falling edge interrupt event is
present
10 High level interrupt or rising edge interrupt event is
present
11 Both of rising and falling edge interrupt event is present
in edge trigger interrupt mode.
Not available in level trigger interrupt mode
PRELIMINARY
76
Z32F3841 Product Specification
PCn.ICR
Port Control Unit
Port n Interrupt Control Register
The Port n Interrupt Control register is the interrupt mode control register. Edge interrupt produces a pulsed interrupt
while a level interrupt maintains the interrupt as long as the pin is in the defined state (low or high).
PCA.ICR=0x4000_1018, PCB.ICR=0x4000_1118, PCC.ICR=0x4000_1218
PCD.ICR=0x4000_1318, PCE.ICR=0x4000_1418, PCF.ICR=0x4000_1518
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
PIC15 PIC14
8
7
6
5
4
3
2
1
0
PIC13
PIC12
PIC11
PIC10
PIC9
PIC8
PIC7
PIC6
PIC5
PIC4
PIC3
PIC2
PIC1
PIC0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PICn
PORTEN
Pin interrupt mode
00 Prohibit external interrupt
01 Low level interrupt or Falling edge interrupt mode
10 High level interrupt or rising edge interrupt mode
11 Both of rising and falling edge interrupt mode.
Not support for level trigger mode
Port Access Enable
The Port Access Enable register enables register writing permission of all PCU registers.
PORTEN=0x4000_1FF0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PORTEN
0
0
0
0
0
0
0
0
-WO
7
0
PS034603-0617
PORTEN
Writing the sequence of 0x15 and 0x51 in this register
enables writing to PCU registers, and writing other values
protects all PCU registers from writing.
PRELIMINARY
77
Z32F3841 Product Specification
Port Control Unit
Functional Description
All the GPIO pins can be configured for different operations, inputs, outputs, triggered interrupts (both level
and edge) through the PCU. The system is also able to disable ports by setting the PER1 and PCER1
registers in the SCU. By default, all pins are disabled (except for UART0/SPI0) so the developer must enable
these to operate.
All configuration parameters are protected by the Port Access Enable register. You must write the sequence in
order (0x15, 0x51) to the PORTEN register to configure any pin(s). After the configuration is complete, write
any other value to the PORTEN register to lock it.
Note: Do not read in between the sequence, that will prevent the configuration registers from being unlocked.
PS034603-0617
PRELIMINARY
78
Z32F3841 Product Specification
General Purpose I/O
6. General Purpose I/O
Overview
Most of the pins except the dedicated function pins can be used as general I/O ports. General input/output
ports are controlled by the GPIO block.
Output signal level (H/L) select
GPIO Port
PSEL
PnSRR
DOUT[31:0]
PnODR
PCU
DIN[31:0]
PINs
PnIDR
Figure 6.1. Block Diagram
PS034603-0617
PRELIMINARY
79
Z32F3841 Product Specification
General Purpose I/O
Pin Description
Table 6.1. External Signal
PIN NAME
TYPE
PA
IO
PA0 - PA15
DESCRIPTION
PB
IO
PB0 - PB15
PC
IO
PC0 - PC15
PD
IO
PD0 - PD15
PE
IO
PE0 – PE15
PF
IO
PF0 – PF5
Registers
The base address of GPIO is 0x4000_2000 and the register map is described in Tables 6.2 and 6.3.
Table 6.2. Base Address of Each Port
PORT
Address
PA PORT
0x4000_2000
PB PORT
0x4000_2100
PC PORT
0x4000_2200
PD PORT
0x4000_2300
PE PORT
0x4000_2400
PF PORT
0x4000_2500
Table 6.3. GPIO Register Map
PS034603-0617
Name
Offset
R/W
Description
Reset
Pn.ODR
0x--00
R/W
Port n Output data register
0x00000000
0x00000000
Pn.IDR
0x--04
RO
Port n Input data register
Pn.BSR
0x--08
WO
Port n Pin set register
0x00000000
Pn.BCR
0x—0C
WO
Port n Pin clear register
0x00000000
PRELIMINARY
80
Z32F3841 Product Specification
Pn.ODR
General Purpose I/O
Port n Output Data Register
When the pin is set to output and GPIO mode, the pin output level is defined by the Port n Output Data
registers.
PA.ODR=0x4000_2000, PB.ODR=0x4000_2100, PC.ODR=0x4000_2200
PD.ODR=0x4000_2300, PE.ODR=0x4000_2400, PF.ODR=0x4000_2500
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ODR
0000
R/W
ODR
Pn.IDR
Pin output level
0
Output low level
1
Output high level
Port n Input Data Register
Each pin level status can be read in the Port n Input Data register. Even if the pin is in alternative mode except
analog mode, the pin level can be detected in this register.
PA.IDR=0x4000_2004, PB.IDR=0x4000_2104, PC.IDR=0x4000_2204
PD.IDR=0x4000_2304, PE.IDR=0x4000_2404, PF.IDR=0x4000_2504
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PnIDR
0000
Read Only
IDR
Pn.BSR
Pin current level
0
The pin is low level
1
The pin is high level
Port n Bit Set Register
The Port n Bit Set register controls each bit of of the Port n Output Data register (PnODR). When you write “1”
to a specific bit, the corresponding bit in the PnODR register is set.
PA.BSR=0x4000_2008, PB.BSR=0x4000_2108, PC.BSR=0x4000_2208
PD.BSR=0x4000_2308, PE.BSR=0x4000_2408, PF.BSR=0x4000_2508
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BSR
0000
Write Only
BSR
PS034603-0617
Pin current level
0
Not effect
1
Set correspondent bit in PnODR register
PRELIMINARY
81
Z32F3841 Product Specification
Pn.BCR
General Purpose I/O
Port n Bit Clear Register
The Port n Bit Clear register controls each bit of the Port n Output Data register (PnODR). When you write “1”
to a specific bit, the corresponding bit in the PnODR register is cleared.
PA.BCR=0x4000_200C, PB.BCR=0x4000_210C, PC.BCR=0x4000_220C
PD.BCR=0x4000_230C, PE.BCR=0x4000_240C, PF.BCR=0x4000_250C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BCR
0000
Write Only
BCR
Pin current level
0
Not effect
1
Clear correspondent bit in PnODR register
Functional Description
The GPIO registers provide the input/output condition of the GPIO pins. The input data registers give the
states of the pins of the ports. The output data register is for setting the port pins. The Set and Clear registers
control the pins at the individual level.
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Z32F3841 Product Specification
Flash Memory Controller
7. Flash Memory Controller
Introduction
Flash Memory Controller is an internal Flash memory interface controller with the following features:
384KB Flash code memory
32-bit data bus width
Code cache block for fast access mode
256-byte page size
Supports page erase and macro erase
256-byte unit program
Description
Item
Size
384KB
Start Address
0x0000_0000
End Address
0x0005_FFFF
Page Size
256-byte
Total Page Count
1,536 pages
PGM Unit
256-byte
Erase Unit
256-byte
AHB BUS
Read CACHE
APB BUS
Register file
B
U
S
C
O
N
T
R
O
L
CODE
FlashROM
128KB
(32K x 32bit)
M
U
X
Figure 7.1. Block Diagram
PS034603-0617
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Z32F3841 Product Specification
Flash Memory Controller
Pin Description
There are no external interface pins for this peripheral.
Registers
The base address of the Flash Memory Controller is shown in Table 7.1.
Table 7.1. Flash Memory Controller Base Address
Address
Flash Controller
0x4000_0100
Table 7.2 shows the register memory map.
Table 7.2. Flash Memory Controller Register Map
Name
Offset
R/W
FM.MR
0x0004
R/W
Flash Memory Mode Select register
0x01000000
FM.CR
0x0008
R/W
Flash Memory Control register
0x82000000
FM.AR
0x000C
R/W
Flash Memory Address register
0x00000000
FM.DR
0x0010
R/W
Flash Memory Data register
0x00000000
FM.TMR
0x0014
R/W
Flash Memory Timer register
0x000000bb
FM.DRTY
0x0018
R/W
Flash Memory Dirty bit
FM.TICK
0x001C
RO
Flash Memory Tick Timer
FM.CRC
0x0020
RO
Flash Memory Read CRC Value
FM.CFG
0x0030
R/W
Flash Memory config value register
0x00000000
FM.OTPCR
0x0034
R/W
Flash OTP control register
0x00000000
FM.BOOTCR
0x0074
R/W
Boot ROM Remap Clear register
0x00000000
FM.PROT
0x0078
R/W
Flash Page protection register
0x00000000
FM.JTAGEN
0x007C
R/W
Jtag protection register
0x00000001
PS034603-0617
Description
PRELIMINARY
Reset
0x00000000
84
Z32F3841 Product Specification
FM.MR
Flash Memory Controller
Flash Memory Mode Register
The Internal Flash Memory Mode register is a 32-bit register.
FM.MR=0x4000_0104
PS034603-0617
31
BOOT
24
IDLE
23
VERIFY
22
AMBAEN
17
TRMEN
16
TRM
9
FEMOD
8
FMOD
7
0
ACODE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5A A5
A5 5A
81 28
0
0
0
0
0
0
4
3
ACODE
0
5
0
0
0x00
RW
0
6
FMOD
0
7
R
0
8
FEMOD
0
9
R
0
TRM
0
R
0
TRMEN
1
R
0
AMBAEN
0
RW
0
VERIFY
0
RW
0
IDLE
0
R
0
R
BOOT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
2
1
0
Boot mode enable status(read only)
Boot mode enable status(read only)
Flash Verify mode enable status(read only)
AMBA mode disable
AMBA mode enable (can change wait state and etc)
Trim mode entry status(read only)
Trim mode status(read only)
Flash mode entry status(read only)
Flash mode status(read only)
Flash mode
Trim mode
AMBA mode
PRELIMINARY
85
Z32F3841 Product Specification
FM.CR
Flash Memory Controller
Flash Memory Control Register
The Internal Flash Memory Control register is shown below.
20
TIMER
17
16
TEST[1:0]
15
14
13
12
11
10
9
VPPOUT
EVER
PVER
RESERVED
RESERVED
RESERVED
PPGM
8
5
4
3
2
1
AE
PMODE
WE
PBLD
PGM
ERS
0
PBR
1
0
1
00
01
01
10
11
0
1
ERS
PBR
0
0
0
0
0
0
RW
RW
0
RW
RW
PGM
RO
0
RW
RW
PBLD
AE
0
RW
PPGM
0
5
WE
RESERVED
0
6
RW
RESERVED
0
0
7
PMOD
PVER
RESERVED
0
0
0
8
0
0
RW
0
EVER
0
RW
0
VPPOUT
0
R
0
TEST0
RW
0
RW
RW
0
TEST1
RW
0
RW
RW
PS034603-0617
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
TIMER
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
RW
FM.CR=0x4000_0108
4
3
2
1
0
Program/Erase timer enable
(timer can be enable by PGM or ERS bit)
Normal operation
(read) Row voltage mode
(write) ODD Row program
Even Row program
All Row program
Enable charge-pump Vpp output
Set erase verify mode
Set program verify mode
Reserved
Reserved
Reserved
Pre PGM enable
Page buffer set automatically
All erase enable
PMODE enable(Address path changing)
Write enable
Page buffer load (PMODE should be set)
Program enable
Program mode enable
Erase mode enable
Page buffer reset
PRELIMINARY
86
Z32F3841 Product Specification
FM.AR
Flash Memory Controller
Flash Memory Address Register
The Flash Memory Address register is the internal Flash Memory program/erase address register.
FM.AR=0x4000_010C
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FADDR
0
0x0000
RW
16
0
FM.DR
FADDR
96K words address (one word = 4 bytes)
Flash Memory Data Register
The Internal Flash Memory Data register is shown below.
FM.DR=0x4000_0110
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
FDATA
0x0000_0000
RW
31
0
FM.TMR
FDATA
Flash PGM data (32-bit)
Flash Memory Timer Register
In the internal Flash Memory Timer value register (16-bit), the Erase/Program timer runs up to {TMR[15:0}.
FM.TMR=0x4000_0114
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TMR
0x09C4
RW
15
0
PS034603-0617
TMR
Erase/PGM timer (default, 0x09C4)
Timer counts up to TMR[15:0] by int. OSC clock or External
OSC clock. It can be selected in TMRCK bit.
PRELIMINARY
87
Z32F3841 Product Specification
FM.DRTY
Flash Memory Controller
Flash Memory Dirty Bit Register
The internal Flash Memory Dirty Bit clear register is shown below.
FM.DRTY=0x4000_0118
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
FDRTY
Write Only
31
0
FM.TICK
FDRTY
Write any value here, cache line fill flag will be cleared.
Flash Memory Tick Timer Register
The Flash Memory Tick Timer register is the internal Flash Memory Burst Mode channel selection register.
FM.TICK=0x4000_011C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
FTICK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00000
RW
17
0
FM.CRC
FTICK
TICK goes to 0x3FFFF from written TICK value while TRM
runs by PCLK clock
Flash Memory CRC Value Register
The Flash Memory CRC Value register shows the CRC value resulting from read accesses on internal Flash
memory.
FM.CRC=0x4000_0120
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CRC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xFFFF
RO
15
0
PS034603-0617
CRC
CRC16 value
PRELIMINARY
88
Z32F3841 Product Specification
FM.CFG
Flash Memory Controller
Flash Memory Config Value Register
The Flash Memory Config Value register is the Flash Trim value register.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
8
0
1
1
7
6
CRCEN
0
9
WAIT
WRITE KEY
TMRCK
HRESPD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CRCINIT
FM.CFG=0x4000_0130
5
0
0
4
3
2
1
0
TRIM
0
R/W
FM.BOOTCR
31
15
15
WRITE KEY
KEY Value : 0x7858
HRESPD
12
TMRCK
10
8
WAIT
7
CRCINIT
6
CRCEN
3
0
TRIM
Disable HRESP(error response function) of Data or System
bus
(HRESP is AMBA AHB signal)
PGM/ERASE timer source is 20MHz INTOSC
PRM/ERASE timer source is External Clock
No wait access for flash memory
1-wait inserted for flash access
2-wait inserted for flash access
3-wait inserted for flash access
4-wait inserted for flash access
5-wait inserted for flash access
CRC register winll be initialized. It should be reset again
before read flash to generate CRC16 calculation
(Initial value of FMCRC is 0xFFFF)
CRC16 enable
CRC value will be calculated at every flash read timing
FLASH TRIM Value (trim_mode_entry)
0
1
000
001
010
011
100
101
0
1
0
1
Boot ROM Remap Clear Register
The Boot ROM Remap Clear register is an 8-bit register.
FM.BOOTCR=0x4000_0174
7
6
5
4
3
2
1
0
BOOTROM
0
0
0
0
0
0
0
1
R
0
PS034603-0617
BOOTROM
Boot Mode (only can be written in boot loader mode)
This bit is used to clear boot loader mode at end of boot
code (when BOOTROM low, external BOOT pin signal is
masked)
PRELIMINARY
89
Z32F3841 Product Specification
FM.JTAGEN
Flash Memory Controller
JTAG Protection Control Register
The JTAG Protection Control register is the debug access control register.
FM.JTAGEN=0x4000_017C
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
JTAGEN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
WRITE_KEY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
0
0
JTAGEN
FM.PROT
0
1
Debug access port is disabled, write access code is 0xC7
Debug access port is enabled
Write Protection Control Register
The Write Protection Control register is the internal Flash memory control register. The PAS selects the area
to protect and the WP bits specify the section within the area.
FM.PROTECT=0x4000_0178
23
PS034603-0617
WP10
WP9
WP8
WP7
WP6
WP5
WP4
WP3
WP2
WP1
WP0
0x0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
RW
0
WP11
0
RW
0
APR
18
16
PAS
15
14
13
12
11
10
9
8
7
6
5
4
WP15
WP14
WP13
WP12
WP11
WP10
WP9
WP8
WP7
WP6
WP5
WP4
0
WP12
0
1
RW
0
2
WP13
0
3
RW
0
4
WP14
0
5
RW
0
6
WP15
0
7
R/w
0
RW
0
RW
WRITE_KEY
8
PAS
APR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
All protection removed, write_key is 0xA9
0x0 : protection enabled (default)
0x1 : removed All protection , WP15~0 will be set as APR
set
Protection Area Selction, write_key is 0x98
0x0 :
protection area < 64KB
0x1 : 64KB < protection area < 128KB
0x2 : 128KB < protection area < 192KB
0x3 : 192KB < protection area < 256KB
0x4 : 256KB < protection area < 320KB
0x5 : 320KB < protection area < 384KB
0xF000 ~ 0xFFFF, write_key is 0x87 or 0x98
0xE000 ~ 0xEFFF, write_key is 0x87 or 0x98
0xD000 ~ 0xDFFF, write_key is 0x87 or 0x98
0xC000 ~ 0xCFFF, write_key is 0x87 or 0x98
0xB000 ~ 0xBFFF, write_key is 0x87 or 0x98
0xA000 ~ 0xAFFF, write_key is 0x87 or 0x98
0x9000 ~ 0x9FFF, write_key is 0x87 or 0x98
0x8000 ~ 0x8FFF, write_key is 0x87 or 0x98
0x7000 ~ 0x7FFF, write_key is 0x87 or 0x98
0x6000 ~ 0x6FFF, write_key is 0x87 or 0x98
0x5000 ~ 0x5FFF, write_key is 0x87 or 0x98
0x4000 ~ 0x4FFF, write_key is 0x87 or 0x98
PRELIMINARY
90
Z32F3841 Product Specification
3
2
1
0
WP3
WP2
WP1
WP0
Flash Memory Controller
0x3000 ~ 0x3FFF, write_key is 0x87 or 0x98
0x2000 ~ 0x2FFF, write_key is 0x87 or 0x98
0x1000 ~ 0x1FFF, write_key is 0x87 or 0x98
0x0000 ~ 0x0FFF, write_key is 0x97 or 0x98
0x0 : Protected (default)
0x1 : PGM/ERASE enabled
Functional Description
The Flash area can be read from directly via the memory address. Writing of Flash memory can be done
through the Boot mode or In-application programming. The execution for the writing of Flash must occur from
the RAM area (or from Boot ROM). The Flash controller cannot read Flash memory (including instructions)
once the program bit has been set.
Caution: If the vector table is not placed in RAM, you MUST disable interrupts to prevent reading the interrupt
service routine in Flash memory.
PS034603-0617
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91
Z32F3841 Product Specification
Internal SRAM
8. Internal SRAM
Overview
The Z32F3841 MCU implements zero-wait on the chip’s SRAM. The size of the SRAM is 16 KB. The SRAM
base address is 0x2000_0000.
0x0000_0000
Code Flash
(384KB)
0x0005_FFFF
0x2000_0000
SRAM (16KB)
0x2000_3FFF
Figure 8.1. SRAM Block Diagram
PS034603-0617
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92
Z32F3841 Product Specification
Direct Memory Access Contoller
9. Direct Memory Access Contoller
Introduction
The Direct Memory Access (DMA) controller has the following features:
8 channels
Single transfer only
Supports 8-/16-/32-bit data size
Supports multiple buffers with same size
Interrupt condition is transferred through peripheral interrupt
Figure 9.1. Block Diagram
PS034603-0617
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93
Z32F3841 Product Specification
Direct Memory Access Contoller
Pin Description
There are no external interface pins.
Registers
The base addresses of the DMA controller are shown in Table 9.1.
Table 9.1. DMA Controller Base Addresses
Ch. No.
Base Address
DMACH0
0x4000_0400
DMACH1
0x4000_0410
DMACH2
0x4000_0420
DMACH3
0x4000_0430
DMACH4
0x4000_0440
DMACH5
0x4000_0450
DMACH6
0x4000_0460
DMACH7
0x4000_0470
Assigned Peripheral
Table 9.2 shows the register map of the DMA controller.
Table 9.2. DMAC Register Map
Name
Offset
R/W
Description
Reset
DCn.CR
0x0000
R/W
DMA Channel n Control Register
0x0000_0000
DCn.SR
0x0004
R/W
DMA Channel n Status Register
0x0000_0000
DCn.PAR
0x0008
R
DMA Channel n Peripheral Address
0x0000_0000
DCn.MAR
0x000C
R/W
DMA Channel n Memory Address
0x2000_0000
PS034603-0617
PRELIMINARY
94
Z32F3841 Product Specification
DCn.CR
Direct Memory Access Contoller
DMA Controller Configuration Register
The DMA operation control register is a 32-bit register.
DC0.CR=0x4000_0400 , DC1.CR=0x4000_0410
DC2.CR=0x4000_0420 , DC3.CR=0x4000_0430
DC4.CR=0x4000_0440 , DC5.CR=0x4000_0450
DC6.CR=0x4000_0460 , DC7.CR=0x4000_0470
TRANSCNT
0
0
0
0
0x000
9
0
0
0
0
0
RW
TRANSCNT
11
8
PERISEL
3
2
SIZE
1
DIR
7
6
5
4
PERISEL
RW
27
16
8
0
0
0
0
3
2
1
SIZE
DIR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
00
0
RW
R/W
0
0
Number of DMA transfer remained
Required transfer number should be written before enable
DMA transfer.
0
DMA transfer is done.
N
N transfers are remained
Peripheral selction
N
Associated peripheral selection.
Refer to DMA Peripheral connection table
Bus transfer size.
00 DMA transfer is byte size transfer
01 DMA transfer is half word size transfer
10 DMA transfer is word size transfer
11 Reserved
Select transfer direction.
0
Transfer direction is from memory to peripheral. (TX)
1
Transfer direction is from peripheral to memory (RX)
A DMA channel is connected with the selected peripheral.
Table 9.3 sTable 9.3. DMAC PERISEL Selectionhows peripheral selection numbers. The PERISEL field
should be set with the correct number of the peripheral which will be connected with the DMA interface.
PS034603-0617
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95
Z32F3841 Product Specification
Direct Memory Access Contoller
Table 9.3. DMAC PERISEL Selection
PERISEL[3:0]
Associated Peripheral
0
CHANNEL IDLE
1
UART0 RX
2
UART0 TX
3
UART1 RX
4
UART1 TX
5
UART2 RX
6
UART2 TX
7
UART3 RX
8
UART3 TX
9
SPI0 RX
10
SPI0 TX
11
SPI1 RX
12
SPI1 TX
13
ADC0 RX
14
ADC1 RX
PERISEL cannot have the same value in different channels. If the same PERISEL value is wriiten in more
than one channel, proper operation is not guaranteed.
Unused channels should contain a CHANNEL IDLE value in the PERISEL bit postions.
DCn.SR
DMA Controller Status Register
The DMA Controller Status register is an 8-bit register. This register represents the current status of DMA
Controller and enables DMA function.
DC0.SR=0x4000_0404 , DC1.SR=0x4000_0414
DC2.SR=0x4000_0424 , DC3.SR=0x4000_0434
DC4.SR=0x4000_0444 , DC5.SR=0x4000_0454
DC6.SR=0x4000_0464 , DC7.SR=0x4000_0474
7
6
5
4
3
2
1
EOT
1
DMAEN
0
0
0
0
0
RO
PS034603-0617
0
0
0
R/W
7
EOT
0
DMAEN
End of transfer.
0
Data to be transferred is existing.
TRANSCNT shows non zero value
1
All data is transferred.
TRANSCNT shows now 0
DMA Enable
0
DMA is in stop or hold state
1
DMA is running or enabled
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Z32F3841 Product Specification
DCn.PAR
Direct Memory Access Contoller
DMA Controller Peripheral Address Register
The DMA Controller Peripheral Address register represents the peripheral address.
DC0.PAR=0x4000_0408 , DC1.PAR=0x4000_0418
DC2.PAR=0x4000_0428 , DC3.PAR=0x4000_0438
DC4.PAR=0x4000_0448 , DC5.PAR=0x4000_0458
DC6.PAR=0x4000_0468 , DC7.PAR=0x4000_0478
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
Peripheral BASE OFFSET
PAR
0x4000
0x0000
RO
RW
31
0
DCn.MAR
9
PAR
6
5
4
3
2
1
0
Target Peripheral address of transmit buffer or receive buffer.
User must set exact target peripheral buffer address in this
field.
If DIR is “0” this address is destination address of data
transfer.
If DIR is “1”, this address is source address of data transfer.
DMA Controller Memory Address Register
The DMA Controller Memory Address register represents the memory address.
DC0.MAR=0x4000_040C , DC1.MAR=0x4000_041C
DC2.MAR=0x4000_042C , DC3.MAR=0x4000_043C
DC4.MAR=0x4000_044C , DC5.MAR=0x4000_045C
DC6.MAR=0x4000_046C , DC7.MAR=0x4000_047C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MAR
0x2000
0x0000
RO
RW
31
0
PS034603-0617
MAR
Target memory address of data transfer.
Address is automatically incremented according to SIZE bits
when each transfer is done.
If DIR is “0” this address is source address of data transfer.
If DIR is “1”, this address is destination address of data
transfer.
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Z32F3841 Product Specification
Direct Memory Access Contoller
Functional Description
The DMA controller performs direct memory transfer by sharing the system bus with the CPU core. The
system bus is shared by two AHB masters following the round-robin priority strategy. Therefore, the DMA
controller can share half of the system bandwidth.
The DMA controller can be triggered only by a peripheral request. When a peripheral requests a transfer to
the DMA controller, the related channel is activated and accesses the bus to transfer the requested data from
memory to the peripheral data buffer or vice versa.
The transfer process involves the following steps:
1. User sets the peripheral and memory addresses.
2. User configures DMA operation mode and transfer count.
3. User enables the DMA channel.
4. Peripheral generates a DMA request.
5. DMA activates the channel that was requested
6. DMA reads data from the source address and saves it to the internal buffer.
7. DMA writes the buffered data to the destination address.
8. Transfer count number is decreased by 1.
9. When the transfer count is 0, the EOT flag is set and notice is sent to the peripheral to issue the
interrupt.
10. DMA does not have an interrupt source; the interrupt-related DMA status can be shown from the
assigned peripheral interrupt.
Figure 9.2. Block Diagram
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Z32F3841 Product Specification
Direct Memory Access Contoller
Figure 9.3The figure shows the functional timing diagram of the DMA controller. The transfer request from the
peripheral is pended internally and it invokes source data read transfer on the AHB bus. The read data from
the source address is stored in the internal buffer. This data is transferred to the destination address when the
AHB bus is available.
The timing diagram for a DMA transfer from the peripheral to memory is shown in Figure 9.3. A 4-clock cycle
latency exists when accessing the peripheral. If the bus is occupied by a different bus master, the number of
bus waiting cycles increase until the bus is available.
Figure 9.3. DMA Transfer from Peripheral to Memory
The timing diagram for a DMA transfer from memory to the peripheral is shown in Figure 9.4. A 4-clock cycle
latency exists when accessing the peripheral. If the bus is occupied by a different bus master, the number of
bus waiting cycles increase until the bus is available.
Figure 9.4. DMA Transfer from Memory to Peripheral
Figure 9.5 is an example of N data transfers with the DMA. The DMA transfer is started when DCnSR.DMAEN
is set and cleared when all the transfers are completed.
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Z32F3841 Product Specification
Direct Memory Access Contoller
Figure 9.5. Example of N DMA Transfer
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100
Z32F3841 Product Specification
Watch-Dog Timer
10. Watch-Dog Timer
Overview
The Watchdog Timer can monitor the system and generate an interrupt or a reset. It has a 32-bit downcounter. Miscellaneous Clock Control Register 3 provides base clock options with clock dividers to drive the
WDT clock. This can be selected in the WDTCON register. To prevent the WDT from firing, reload the LR
register with the appropriate value before the WDT times out.
32-bit down counter (WDTCNT)
Select reset or periodic interrupt
Count clock selection
Dedicated pre-scaler
Watchdog overflow output signal
Figure 10.1. Block Diagram
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Z32F3841 Product Specification
Watch-Dog Timer
Registers
The base address of the watchdog timer is 0x4000_0200 and the register map is listed in Table 10.1. Initial
watchdog time-out period is set to 2000-miliseconds.
Table 10.1. Watchdog Timer Register Map
WDT.LR
Name
Offset
R/W
Description
Reset
WDT.LR
0x0000
W
WDT Load register
0x00000000
WDT.CNT
0x0004
R
WDT Current counter register
0x0000FFFF
WDT.CON
0x0008
R/W
WDT Control register
0x0000805C
Watchdog Timer Load Register
The Watchdog Timer Load register is used to update the WDTCNT register. To update the WDTCNT register,
the WEN bit of WDTCON should be set to 1 and written into the WDTLR register with a target value of
WDTCNT.
WDT.LR=0x4000_0200
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
WDTLR
0x0000_0000
RW
31
0
WDT.CNT
WDTLR
Watchdog timer load value register
Keeping WEN bit as ‘1’, write WDTLR register will update
WDTCNT value with written value
Watchdog Timer Current Counter Register
The Watchdog Timer Current Counter register represents the current count value of the 32-bit down
counter .When the counter value reaches 0, the interrupt or reset is awoken.
WDT.CNT=0x4000_0204
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
WDTCNT
0x0000_FFFF
RW
31
0
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WDTCNT
Watchdog timer current counter register
32-bit down counter will run from the written value.
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Z32F3841 Product Specification
WDT.CON
Watch-Dog Timer
Watchdog Timer Control Register
The timer module should be correctly configured before running. When the target purpose is defined, the timer
can be configured in the TnCON register.
11
10
9
8
WDTIE
WDTRE
1
0
0
0
0
0
0
0
0
1
RW
RW
RW
RW
PS034603-0617
15
WDBG
8
WUF
7
WDTIE
6
WDTRE
4
WDTEN
3
CKSEL
2
0
WPRS[2:0]
7
6
5
4
WPRS
12
CKSEL
13
WDTEN
14
WDBG
15
WUF
WDT.CON=0x4000_0208
3
2
1
0
1
1
100
RW
RW
RW
0
Watchdog operation control in debug mode
0
Watchdog counter running when debug mode
1
Watchdog counter stopped when debug mode
Watchdog timer underflow flag
0
No underflow
1
Underflow is pending
Watchdog timer counter underflow interrupt enable
0
Disable interrupt
1
Enable interrupt
Watchdog timer counter underflow interrupt enable
0
Disable reset
1
Enable reset
Watchdog Counter enable
0
Watch dog counter disabled
1
Watch dog counter enabled
WDTCLKIN clock source select
0
PCLK
1
External clock (Configured in MCCR3)
Counter clock prescaler
WDTCLK = WDTCLKIN/WPRS
000
WDTCLKIN / 1
001
WDTCLKIN / 4
010
WDTCLKIN / 8
011
WDTCLKIN / 16
100
WDTCLKIN / 32
101
WDTCLKIN / 64
110
WDTCLKIN / 128
111
WDTCLKIN / 256
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103
Z32F3841 Product Specification
Watch-Dog Timer
Functional Description
The MCCR3 register must be configured to enable the clock source and divider for the Watch Dog Timer
(WDT) to run. To prevent the WDT from resetting or interrupting, load a new value into the WDTLR register
before the WDTCNT reaches 0.
The watchdog timer count is enabled by setting WDTEN (WDT.CON[4]) to 1. When the watchdog timer is
enabled, the down counter starts counting from the load value. If WDTRE (WDT.CON[6]) is set to 1, WDT
reset is asserted when the WDT counter value reaches 0 (underflow event) from the WDTLR value. Before
the WDT counter goes down to 0, the software can write a certain value to the WDTLR register to reload the
WDT counter.
Timing Diagram
Figure 10.2. Timing Diagram in Interrupt Mode Operation when WDT Clock is External Clock
In WDT interrupt mode, after the WDT underflow occurs, a certain count value is reloaded to prevent the next
WDT interrupt in a short time period. This reloading action can only be activated when the watchdog timer
counter is set to Interrupt mode (set WDTIE of WDT.CON). It takes up to 5 cycles from the load value to the
CNT value. The WDT interrupt signal and CNT value data might be delayed by a maximum of 2 system bus
clocks in synchronous logic.
Prescale Table
The WDT includes a 32-bit down counter with programmable prescaler to define different time-out intervals.
The clock sources of the watchdog timer can include the peripheral clock (PCLK) or one of 3 external clock
sources. An external clock source can be enabled by CKSEL (WDT.CON[3]) set to ‘1’ and external clock
source chosen in MCCR3 register of the System Control Unit block.
To make the WDT counter base clock, users can control the 3-bit prescaler WPRS [2:0] in the WDT.CON
register and the maximum prescaled value is “clock source frequency/256”. The prescaled WDT counter clock
frequency values are listed in Table 10.2.
Selectable clock source (40 kHz ~ 16 MHz) and the time out interval when 1 count
Time out period = {(Load Value) * (1/pre-scaled WDT counter clock frequency) + max 5T ext} + max 4Tclk
*Time out period (time out period from load Value to interrupt set ‘1’)
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Z32F3841 Product Specification
Watch-Dog Timer
Table 10.2. Prescaled WDT Counter Clock Frequency
Clock
Source
WDTCLKIN
WDTCL
KIN/4
WDTCLKI
N/8
WDTCL
KIN/16
WDTCLKI
N/32
WDTCLKI
N/64
WDTCLKI
N/128
WDTCLKI
N/256
Ring OSC
1MHz
250kHz
125kHz
62.5kHz
31.25kHz
15.625kHz
7.8125kHz
3.90625k
Hz
MCLK
MCLK
(BUS CLK)
MCLK/4
MCLK/8
MCLK/16
MCLK/32
MCLK/64
MCLK/128
MCLK/256
IOSC20
20MHz
5MHz
2.5MHz
1.25MHz
625kHz
312.5kHz
156.25kHz
78.125kHz
EOSC
XTAL
XTAL/4
XTAL/8
XTAL/16
XTAL/32
XTAL/64
XTAL/128
XTAL/256
SubOSC
32.768kHz
8.192kHz
4.096kHz
2.048kHz
1.024kHz
512Hz
256Hz
128Hz
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Z32F3841 Product Specification
16-Bit Timer
11. 16-Bit Timer
Overview
The Timer block consists of 10 channels of 16-bit general-purpose timers. They can support periodic timer,
PWM pulse, one-shot timer, and capture mode.
16-bit up-counter
Periodic timer mode
One-shot timer mode
PWM pulse mode
Capture mode
10-bit prescaler
Multi-channel synchronization function
Figure 11.1. Block Diagram
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Z32F3841 Product Specification
16-Bit Timer
Pin Description
Table 11.1. External Pin
PIN NAME
TYPE
TnC
I
External clock / capture input
DESCRIPTION
TnO
O
Timer output
Registers
The base address of the TIMER is 0x4000_3000 and the register map is described in Table.11.2 and 11.3.
Table 11.2. Base Address of Each Channel
CHANNEL
Address
T0
0x4000_3000
T1
0x4000_3020
T2
0x4000_3040
T3
0x4000_3060
T4
0x4000_3080
T5
0x4000_30A0
T6
0x4000_30C0
T7
0x4000_30E0
T8
0x4000_3100
T9
0x4000_3120
Table 11.3. Timer Register Map
Name
Offset
R/W
Description
Reset
Tn.CR1
0x-000
R/W
Timer control register 1
0x00000000
Tn.CR2
0x-004
R/W
Timer control register 2
0x00000000
Tn.PRS
0x-008
R/W
Timer prescaler register
0x00000000
Tn.GRA
0x-00C
R/W
Timer general data register A
0x00000000
Tn.GRB
0x-010
R/W
Timer general data register B
0x00000000
Tn.CNT
0x-014
R/W
Timer counter register
0x00000000
Tn.SR
0x-018
R/W
Timer status register
0x00000000
TnI.ER
0x-01C
R/W
Timer interrupt enable register
0x00000000
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Z32F3841 Product Specification
16-Bit Timer
Tn.CR1 Timer n Control Register 1
The Timer Control Register 1 is a 16-bit register.
The timer module should be correctly configured before running. When the target purpose is defined, the timer
can be configured in the TnCR1 register.
0
R/W
R/W
R/W
R/W
PS034603-0617
8
7
0
0
0
0
0
R/W
15
SSYNC
14
CSYNC
13
UAO
12
OUTPOL
8
ADCTRGEN
7
STARTLVL
6
4
CKSEL[2:0]
3
2
CLRMD
1
0
MODE[1:0]
6
5
4
3
2
1
0
MODE
0
9
CLRMOD
0
10
CKSEL
0
11
STARTLVL
OUTPOL
12
UAO
13
CSYNC
14
SSYNC
15
ADCTRGEN
T0.CR1=0x4000_3000, T1.CR1=0x4000_3020
T2.CR1=0x4000_3040, T3.CR1=0x4000_3060
T4.CR1=0x4000_3080, T5.CR1=0x4000_30A0
T6.CR1=0x4000_30C0, T7.CR1=0x4000_30E0
T8.CR1=0x4000_3100, T9.CR1=0x4000_3120
000
00
00
R/W
R/W
R/W
Synchronize start counter with other synchronized timers
0
Single counter mode
1
Synchronized counter start mode
Synchronize clear counter with other synchronized timers
0
Single counter mode
1
Synchronized counter clear mode
Select GRA, GRB update mode
0
Writing GRA or GRB takes effect after current period
1
Writing GRA or GRB takes effect in current period
Timer output polarity
0
Normal output
1
Negated output
ADC Trigger enable control
0
Disable adc trigger
1
Enable adc trigger
Timer output polarity control
0
Default output level is HIGH
1
Defulat output level is LOW
Counter clock source select
000
PCLK/2
001
PCLK/4
010
PCLK/16
011
PCLK/64
10X
EXT0 (MCCR3)
11X
TnC pin input
Clear select when capture mode
00
Rising edge clear mode
01
Falling edge clear mode
10
Both edge clear mode
11
None clear mode
Timer operation mode control
00
Normal periodic operation mode
01
PWM mode
10
One shot mode
11
Capture mode
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Z32F3841 Product Specification
16-Bit Timer
Tn.CR2 Timer n Control Register 2
The Timer Control Register 2 is an 8-bit register.
T0.CR2=0x4000_3004, T1.CR2=0x4000_3024
T2.CR2=0x4000_3044, T3.CR2=0x4000_3064
T4.CR2=0x4000_3084, T5.CR2=0x4000_30A4
T6.CR2=0x4000_30C4, T7.CR2=0x4000_30E4
T8.CR2=0x4000_3104, T9.CR2=0x4000_3124
7
6
5
4
3
2
1
0
TCLR
TEN
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R/W
R/W
1
TCLR
0
TEN
Timer register clear
0
No
1
Clear count register (This bit will be cleared after next
timer clock)
Timer enable bit
0
Stop Timer Counting
1
Start Timer Counting
It is recommended to start the timer with the TCLR bit set to '1'.
Tn.PRS
Timer n Prescaler Register
The Timer Prescaler Register is a 16-bit register to prescale the counter input clock.
T0.PRS=0x4000_3008, T1.PRS=0x4000_3028
T2.PRS =0x4000_3048, T3.PRS=0x4000_3068
T4.PRS=0x4000_3088, T5.PRS=0x4000_30A8
T6.PRS =0x4000_30C8, T7.PRS=0x4000_30E8
T8.PRS=0x4000_3108, T9.PRS=0x4000_3128
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PRS
0
0
0
0
0
0
000
R/W
9
0
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PRS
Pre-scale value of count clock
TCLK = PCLK/(PRS+1)
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Z32F3841 Product Specification
Tn.GRA
16-Bit Timer
Timer n General Register A
The Timer General Register A is a 16-bit register. The GRA register is the duty register. This register controls
the TxIO pin.
T0.GRA=0x4000_300C, T1.GRA=0x4000_302C
T2.GRA =0x4000_304C, T3.GRA=0x4000_306C
T4.GRA=0x4000_308C, T5.GRA=0x4000_30AC
T6.GRA =0x4000_30CC, T7.GRA=0x4000_30EC
T8.GRA=0x4000_310C, T9.GRA=0x4000_312C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GRA
0x0000
R/W
15
0
Tn.GRB
GRA
Timer n General Register A (Duty/Interrupt Register)
Periodic mode / PWM / One-shot mode
- Duty count value
- When the counter value is matched with this value, GRA
Match interrupt is requested
Capture mode
- Falling edge of TnC port will capture the count value when
rising edge clear mode
- Rising edge of TnC port will capture the count value when
falling edge clear mode
Timer n General Register B
Timer General Register B is a 16-bit register. The GRB register is the period match counter. It does not toggle
the TxIO pins and is required in most modes as the period.
T0.GRB=0x4000_3010, T1.GRB=0x4000_3030
T2.GRB=0x4000_3050, T3.GRB=0x4000_3070
T4.GRB=0x4000_3090, T5.GRB=0x4000_30B0
T6.GRB=0x4000_30D0, T7.GRB=0x4000_30F0
T8.GRB=0x4000_3110, T9.GRB=0x4000_3130
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GRB
0x0000
R/W
15
0
PS034603-0617
GRB
Timer n General Register A (Period/Interrupt register)
Periodic mode / PWM / One-shot mode
- In periodic mode or PWM mode, this register is used as
Period value. The counter will count up to (GRB-1) value.
- When the counter value is matched with this value, GRB
Match interrupt is requested only in PWM and one-shot
modes.
Capture mode
- Rising edge of TnC port will capture the count value when
rising edge clear mode
- Falling edge of TnC port will capture the count value when
falling edge clear mode
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Z32F3841 Product Specification
Tn.CNT
16-Bit Timer
Timer n Counter Register
The Timer Counter Register is a 16-bit register.
T0.CNT=0x4000_3014, T1.CNT=0x4000_3034
T2.CNT=0x4000_3054, T3.CNT=0x4000_3074
T4.CNT=0x4000_3094, T5.CNT=0x4000_30B4
T6.CNT=0x4000_30D4, T7.CNT=0x4000_30F4
T8.CNT=0x4000_3114, T9.CNT=0x4000_3134
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CNT
0x0000
R/W
15
0
CNT
Timer count value
Tn.SR Timer n Status Register
The Timer Status Register is an 8-bit register. This register indicates the current status of the timer module.
T0.SR=0x4000_3018, T1.SR=0x4000_3038
T2.SR=0x4000_3058, T3.SR=0x4000_3078
T4.SR=0x4000_3098, T5.SR=0x4000_30D8
T6.SR=0x4000_30F8, T7.SR=0x4000_30F8
T8.SR=0x4000_3118, T9.SR=0x4000_3138
7
6
5
4
3
0
0
0
0
0
R/W
R/W
PS034603-0617
2
MFA
1
MFB
0
OVF
2
1
0
MFA
MFB
OVF
0
0
0
R/W
R/W
R/W
GRA Match flag (Duty Match)
0
No direction change
1
Match flag with GRA
GRB Match flag (Period Match)
0
No direction change
1
Match flag with GRB
Counter overflow flag (Only occurs when counter rolls over
at 0xFFFF)
0
No direction change
1
Counter overflow flag
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Z32F3841 Product Specification
16-Bit Timer
Tn.IER Timer n Interrupt Enable Register
The Timer Interrupt Enable Register is an 8-bit register. Each status flag of the timer block can issue the
interrupt. To enable the interrupt, write “1” in the corresponding bit in the TnIER register.
T0.IER=0x4000_301C, T1.IER=0x4000_303C
T2 .IER=0x4000_305C, T3.IER=0x4000_307C
T4.IER=0x4000_309C, T5.IER=0x4000_30BC
T6.IER=0x4000_30DC, T7.IER=0x4000_30FC
T8.IER=0x4000_311C, T9.IER=0x4000_313C
7
6
5
4
3
0
0
0
0
0
R/W
R/W
R/W
PS034603-0617
2
MAIE
1
MBIE
0
OVIE
2
1
0
MAIE
MBIE
OVIE
0
0
0
W
R/W
W
GRA Match interrupt enable
0
Not effect
1
Enable match register A interrupt
GRB Match interrupt enable
0
Not effect
1
Enable match register B interrupt
Counter overflow interrupt enable
0
Not effect
1
Enable counter overflow interrupt
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Z32F3841 Product Specification
16-Bit Timer
Functional Description
Basic Operation of Timer
In Figure 11.2, TMCLK is a reference clock for operation of the timer. This clock is divided by the prescaler
setting and the counting clock will work. The following images show the starting point of the counter and the
ending of the period point of the counter in normal periodic mode.
(a) Timer initialization is done by TCLR command and the timer will be started by TEN command.
Timer will be resT1TT0.CTT1IO
oTT0.CNT
put
Figure 11.2. Basic Start and Match Operation
The period of
NC=0)
event of TimeT1.CNT
timer
count can be calculated as shown in the following
NC=‘1’)
(b) tching GRB timing and again counting from 00.
RA
equation:
The period = TMCLK Period * Tn.GRB value
Match A interrupt time = TMCLK Period * Tn.GRA value
If the Tn.CR1.UAO bit is “0”, the Tn.CR2.TCLR command will initialize all the registers in the timer block and
load the GRA and GRB value into the Data0 and Data1 buffers. When you change the timer setting and
restart the timer with the new setting, write the CR2.TCLR command before the CR2.TEN command.
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16-Bit Timer
The update timing of the Data0 and Data1 buffers in dynamic operation is different in each operating mode
and depends on the Tn.CR1.UAO bit.
Normal Periodic Mode
Figure 11.3 shows the timing diagram in normal periodic mode. The Tn.GRB value decides the timer period.
An additional comparison point is provided with the Tn.GRA register value.
Figure 11.3. Normal Periodic Mode Operation
The period of the timer count can be calculated as shown in the following equation:
The period = TMCLK Period * Tn.GRB value
Match A interrupt time = TMCLK Period * Tn.GRA value
If Tn.GRB = 0, the timer cannot be started even if TnCR2.TEN is “1”, because the period is “0”.
The value in Tn.GRA and Tn.GRB is loaded into the internal compare data buffers 0 and 1 when the loading
condition occurs. In this periodic mode with TnCR1.UAO =0, the Tn.CR2.TCLR write operation and the GRB
match event will load the compare data buffers.
When TnCR1.UAO is 1, the internal compare data buffer is updated when the Tn.GRA or Tn.GRB data is
updated.
The TnIO output signal is toggled at the time of every Match A condition. If the value of TnGRA is 0, the TnIO
output does not change its previous level. If TnGRA is the same as TnGRB, the TnIO ouput toggles at the
same time as the counter start time. The initial level of the TnIO signal is decided by the TnCR1.STARTLVL
value.
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Z32F3841 Product Specification
16-Bit Timer
One Shot Mode
Figure 11.4 shows the timing diagram in One Shot mode. The Tn.GRB value decides the one shot period. An
additional comparison point is provided with the Tn.GRA register value.
Figure 11.4. One Shot Mode Operation
The period of one shot count can be calculated as shown in the following equation:
The period = TMCLK Period * Tn.GRB value
Match A interrupt time = TMCLK Period * Tn.GRA value
If Tn.GRB = 0, the timer cannot be started even if TnCR2.TEN is “1” because the period is “0”.
The value in Tn.GRA and Tn.GRB is loaded into the internal compare data buffers 0 and 1 when the loading
condition occurs. In this periodic mode with TnCR1.UAO =0, the Tn.CR2.TCLR write operation and the GRB
match event will load the compare data buffers.
When TnCR1.UAO is 1, the internal compare data buffer is updated when the Tn.GRA or Tn.GRB data is
updated.
The TnIO output signal format is the same as in PWM mode. The Tn.GRB value defines the output pulse
period and the Tn.GRA value defines the pulse width of one shot pulse.
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Z32F3841 Product Specification
16-Bit Timer
PWM Timer Output
Figure 11.5 shows the timing diagram in PWM output mode. The Tn.GRB value decides the PWM pulse
period. An additional comparison point is provided with the Tn.GRA register value which defines the pulse
width of PWM output.
Figure 11.5. PWM Output Operation
The period of PWM pulse can be calculated as shown in the following equation:
The period = TMCLK Period * Tn.GRB value
Match A interrupt time = TMCLK Period * Tn.GRA value
If Tn.GRB = 0, the timer cannot be started even if TnCR2.TEN is “1” because the period is “0”.
The value in Tn.GRA and Tn.GRB is loaded into the internal compare data buffer 0 and 1 when the loading
condition occurs. In this periodic mode with TnCR1.UAO =0, the Tn.CR2.TCLR write operation and the GRB
match event will load the compare data buffers.
When TnCR1.UAO is 1, the internal compare data buffer is updated when the Tn.GRA or Tn.GRB data is
updated.
The TnIO output signal generates a PWM pulse. The Tn.GRB value defines the output pulse period and the
Tn.GRA value defines the pulse width of one shot pulse.The active level of the PWM pulse can be controlled
by the Tn.CR1.STARTLVL bit value.
ADC Trigger generation is available at Match A interrupt time.
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Z32F3841 Product Specification
16-Bit Timer
PWM Synchronization Function
2 PWM outputs are usually used as synchronous PWM signal control. This function is provided with a
synchronous start function.
T0.GRB
T0.GRA
T0.CNT
Timer0 was cleared
by start event of
Timer1
(SSYNC=‘1’)
Timer0 starts
Timer0 restarts
T1.GRB
T1.CNT
T1.GRA
Timer1 starts
T0IO
output
T1IO
output
T0.CR2
TEN=1
(SSYNC=0)
T1.CR2
TEN=1
(SSYNC=1)
T0.CNT=T0.GRA
T1.CNT=T1.GRA
Figure 11.6 shows the synchronous PWM generation function.
Figure 11.6. An Example of the Timer Synchronization Function (SSYNC=’0’)
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Z32F3841 Product Specification
16-Bit Timer
Figure 11.7. An Example of the Timer Synchronization Function (CSYNC=’1’)
The TnCR1.SSYNC bit controls start synchronization with other timer blocks. The TnCR1.CSYCN bit controls
clear sync with other timer blocks. The SSYNC and CSYNC bits are only effective when used with tow or
more timers.
For example, timer0 and timer1 set the SSYNC and CCSYNC bits in each CR1 register; both timers are
started when one of them is enabled. Both timers are cleared with a short period match value. However,
others are not affected by these 2 timers, and they can be operated independently because their SYNC
control bit is 0.
Capture Mode
Figure 11.8 shows the timing diagram in Capture mode operation. The TnIO input signal is used for the
capture pulse. Both rising and falling edges can capture the counter value in each capture condition.
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Z32F3841 Product Specification
16-Bit Timer
Figure 11.8. Capture Mode Operation
A 5 PCLK clock cycle is required internally. Therefore, the actual capture point is after 5 PCLK clock cycles
from the rising or falling edge of the TnIO input signal.
The internal counter can be cleared in various modes. The TnCR1.CLRMD field controls the counter
clear mode. Rising Edge clear mode, Falling Edge clear mode, Both Edges clear mode, and None clear mode
are supported.
Figure 11.8 displays the rising edge clear mode.
ADC Trigger Function
The timer module can generate ADC start trigger signals. One timer can be one trigger source of the ADC
block. Trigger source control is performed by the ADC control register.
Figure 11.9 shows the ADC trigger function.
The conversion rate must be shorter than the timer period. If this is not true, an overrun situation can occur.
ADC acknowledge is not required because the trigger signal will be cleared automatically after 3 PCLK clock
pulses.
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Z32F3841 Product Specification
16-Bit Timer
Figure 11.9. ADC Trigger Function Timing Diagram
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Z32F3841 Product Specification
32-Bit Free Run
Timer
12. 32-Bit Free Run Timer
Overview
The FRT block is a 32-bit Free Run Timer. It can be used in power down mode.
32-bit up-counter with SUB OSC
Matched interrupt
Registers
The base address of FRT is 0x4000_30E0 and the register map is described in Tables 12.1 and 12.2.
Table 12.1. Base Address of Each Channel
Channel
FRT
Address
0x4000_0600
Table 12.2. Timer Register Map
Name
Offset
R/W
FRT.MR
0x0000
R/W
FRT mode register
0x00000000
FRT.CR
0x0004
R/W
FRT control register
0x00000000
FRT.PER
0x0008
R/W
FRT period register
0x00000000
FRT.CNT
0x000C
RO
FRT counter register
0x00000000
FRT.SR
0x0010
R/W
FRT status register
0x00000000
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Reset
121
Z32F3841 Product Specification
32-Bit Free Run
Timer
FRT.MR
FRT Mode Register
FRT is a 32-bit up counter. It can be used in power down mode. The SUB OSC clock is directly connected to
FRT. The clock is uncontrollable in the SCU block. The FRT Mode Register is an 8-bit register.
FRTMR=0x4000_0600
7
0
6
5
0
FRT.CR
4
0
3
2
CLKSEL
1
MCD
1
OVIE
0
MIE
3
2
1
0
CLKSEL
MCD
OVIE
MIE
00
0
0
0
RW
RW
RW
RW
FRT counter clock source control
0
Internal Oscillator clock divided by 16
1
External Oscillator clock divided by 16
2
Sub Oscillator clock
3
Reserved
Counter Match Clear Disable bit
0
Counter Match Clear function is enabled.
Whenever the counter matches FRT.PER, the counter
will be set zero and waiting for MF to be cleared.
1
Counter Match Clear function is disabled.
The counter will keep countering without set zero
Overflow Interrupt Enable bit
0
Not effect
1
Interrupt enabled
Match Interrupt Enable bit
0
Not effect
1
Interrupt enabled
FRT Control Register
The FRT Control register is an 8-bit register.
FRTCR=0x4000_3E04
7
0
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6
5
0
4
0
0
3
CNTREQ
2
FCLR
1
FHOLD
0
FEN
3
2
1
0
CNTREQ
FCLR
FHOLD
FEN
0
0
0
0
RW
WO
R/W
R/W
FRT Counter read request bit
0
No
1
Request to read FCNT (cleared when CNTACK(FSR[1])
is high)
FRT Counter register clear bit
0
No
1
Clear the counter
FRT Counter register hold bit
0
No
1
Hold the counter
FRT enable bit
0
FRT Disabled
1
FRT Enabled
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Z32F3841 Product Specification
32-Bit Free Run
Timer
FRT.PER
FRT Period Match Register
The FRT Period Match register is a 32-bit register.
FRTPER=0x4000_3E08
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DATA
0x0000_0000
R/W
32
0
FRT.CNT
DATA
FRT match data
FRT Counter Register
The FRT Counter Register is a 32-bit register.
FRTCNT=0x4000_3E0C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CNT
0x0000_0000
RO
32
0
CNT
FRT Counter
FRT.SR FRT Status Register
FRT Status Register is an 8-bit register.FRTSR=0x4000_0610
7
0
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6
5
0
4
0
0
2
RACK
1
OVIF
0
MIF
3
0
2
1
0
RACK
OVIF
MIF
0
0
0
WC1
WC1
WC1
Read Counter Acknowledge bit
0
Not ready to read CNT value
1
Ready to read CNT value
Overflow interrupt flag bit
0
Overflow interrupt did not occur
1
Overflow interrupt occurred
Match interrupt flag bit
0
Match interrupt did not occur.
1
Match Interrupt occurred
In Counter Match Clear mode, this bit should be cleared
for restarting the counter.
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Z32F3841 Product Specification
32-Bit Free Run
Timer
Functional Description
FRT has two types of interrupt:
Match interrupt
Overflow interrupt
Match Interrupt Operation
The match interrupt timing diagram is shown in
Figure 12.1. FRT.MR.MIE should be set as ‘1’ for using match-interrupt.
The FRT clock starts the FRT counter after FRT.CR.EN is ‘1’. Interrupt and wakeup signals occur when the
counter is matched with the value of FRT.PER. The ‘interrupt’ signal might be delayed in a maximum of 2
system clocks and ‘wakeup’ signal might be delayed in a maximum of (1 clk + 2 frt_clk).
Figure 12.1. Match Interrupt Operation Timing Diagram
Overflow Interrupt Operation
The overflow interrupt timing diagram is shown in
Figure 12.2. The overflow-interrupt operation is similar to the match-interrupt operation. The overflow-interrupt
is started to set when the FRT counter matches 0xFFFFFFFF.
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Z32F3841 Product Specification
32-Bit Free Run
Timer
Figure 12.2. Overflow Interrupt Operation Timing Diagram
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Z32F3841 Product Specification
UART
13. UART
Overview
4-Channel Universal Asynchronous Receiver/Transmitter (UART) modules are provided. There is dedicated
DMA support to data transfer between the memory buffer and the transmit or receive buffer of the UART block.
The UART operation status, including error status, can be read from the status register. The prescaler, which
generates the correct baud rate, exists for each UART channel. The prescaler can divide the UART clock
source, PCLK/2, from 1 to 65535. The baud rate is generated by the clock which is internally divided by 16 of
the prescaled clock and 8-bit precision clock tuning function.
The programmable interrupt generation function helps control communication via the UART channel.
Features
Compatible with 16450
Supports DMA transfer
Standard asynchronous control bit (start, stop, and parity) configurable
Programmable 16-bit fractional baud generator
Programmable serial communication
5-, 6-, 7- or 8- bit data transfer
Even, odd, or no-parity bit insertion and detection
1-, 1.5- or 2-stop bit-insertion and detection
16-bit baud rate generation with 8-bit fraction control
Hardware inter-frame delay function
Stop bit error detection
Detail status register
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UART
SELECT
RECEIVER
BUFFER
RECEIVER
SHIFT
REGISTER
RECEIVER
BUFFER
REGISTER
LINE
CONTROL
REGISTER
DATA[7:0]
RxD
RECEIVER
TIMING
&
CONTROL
ADDR[4:2]
BDR
PSEL
PWRIT
E
PENABLE
PCLK
APB I/F
&
CONTROL
LOGIC
BFR
(Fration)
BAUD
GENERATOR
TRNASMITTER
TIMING
&
CONTROL
LINE
STATUS
REGISTER
TRANSMITTER
BUFFER
nRESET
INTERRUPT
ENABLE
REGISTER
SELECT
TRANSMITTER
HOLDING
REGISTER
INTERRUPT
CONTROL
LOGIC
TRANSMITTER
SHIFTER
REGISTER
TxD
INTERRUPT
INTERRUPT
ID
REGISTER
Figure 13.1. Block Diagram
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UART
Pin Description
Table 13.1. External Signal
PIN NAME
TYPE
DESCRIPTION
TXD0
O
UART Channel 0 transmit output
RXD0
I
UART Channel 0 receive input
TXD1
O
UART Channel 1 transmit output
RXD1
I
UART Channel 1 receive input
TXD2
O
UART Channel 2 transmit output
RXD2
I
UART Channel 2 receive input
TXD3
O
UART Channel 3 transmit output
RXD3
I
UART Channel 3 receive input
Registers
The base address of UART is 0x4000_8000 and the register map is described in Tables 13.2 and 13.3.
Table 13.2. Base Address of Each Port
UART Channel
Address
UART0
0x4000_8000
UART1
0x4000_8100
UART2
0x4000_8200
UART3
0x4000_8300
Table 13.3. UART Register Map
PS034603-0617
Name
Offset
R/W
Un.RBR
0x00
R
Receive data buffer register
Description
Reset
0x00
Un.THR
0x00
W
Transmit data hold register
0x00
Un.IER
0x04
R/W
Interrupt enable register
0x00
Un.IIR
0x08
R
Interrupt ID register
0x01
Un.LCR
0x0C
R/W
Line control register
0x00
Un.DCR
0x10
R/W
Data Control Register
Un.LSR
0x14
R
Line status register
0x00
Un.SCR
0x1C
R/W
Scratch pad register
0x00
Un.BDR
0x20
R/W
Baud rate Divisor Latch Register
Un.BFR
0x24
R/W
Baud rate Fractional Counter Value
0x00
Un.IDTR
0x30
R/W
Inter-frame Delay Time Register
0x00
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Z32F3841 Product Specification
Un.RBR
UART
Receive Buffer Register
The UART Receive Buffer Register is an 8-bit read-only register.
U0.RBR=0x4000_8000, U1.RBR=0x4000_8100
U2.RBR=0x4000_8200, U3.RBR=0x4000_8300
7
6
5
4
3
2
1
0
RBR[7:0]
RO
7
0
Un.THR
RBR
Receive Buffer Register
Transmit Data Hold Register
The UART Transmit Data Hold Register is an 8-bit write-only register.
U0.THR=0x4000_8000, U1.THR=0x4000_8100
U2.THR=0x4000_8200, U3.THR=0x4000_8300
7
6
5
4
3
2
1
0
THR
WO
7
0
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THR
Transmit Data Hold Register
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Z32F3841 Product Specification
UART
Un.IER UART Interrupt Enable Register
The UART Interrupt Enable Register is an 8-bit register.
U0.IER=0x4000_8004, U1.IER=0x4000_8104
U2.IER=0x4000_8204, U3.IER=0x4000_8304
7
6
5
4
3
2
1
0
-
-
DTXIEN
DRXIEN
TXEIE
RLSIE
THREIE
DRIE
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
PS034603-0617
5
DTXIEN
4
DRXIEN
3
TXEIE
2
RLSIE
1
THREIE
0
DRIE
DMA transmit done interrupt enable
0
Receive line status interrupt is disabled
1
Receive line status interrupt is enabled
DMA receive done interrupt enable
0
DMA receive done interrupt is disabled
1
DMA receive done interrupt is enabled
End-of-transmit interrupt enable
0 End-of-transmit interrupt is disabled
1 End-of-transmit interrupt is enabled
Receiver line status interrupt enable
0
Receive line status interrupt is disabled
1
Receive line status interrupt is enabled
Transmit holding register empty interrupt enable
0
Transmit holding register empty interrupt is disabled
1
Transmit holding register empty interrupt is enabled
Data receive interrupt enable
0
Data receive interrupt is disabled
1
Data receive interrupt is enabled
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Z32F384 Product Specification
UART
Un.IIR UART Interrupt ID Register
The UART Interrupt ID Register is an 8-bit register. Reading this register will clear the interrupts.
U0.IIR=0x4000_8008, U1.IIR=0x4000_8108
U2.IIR=0x4000_8208, U3.IIR=0x4000_8308
7
6
0
5
0
4
TXE
3
1
0
IID
2
1
0
TXE
IID
IPEN
0
000
0
R
R
R
0
4
3
Interrupt source ID
See interrupt source ID table
Interrupt source ID
See interrupt source ID table
Interrupt pending bit
0
Interrupt is pending
1
No interrupt is pending.
IPEN
The UART supports 3-priority interrupt generation and the Interrupt Source ID register shows one interrupt
source which has the highest priority amongst pending interrupts. The priority is defined as follows:
Receive line status interrupt
Receive data ready interrupt/ character timeout interrupt
Transmit hold register empty interrupt
Tx/Rx DMA complete interrupt
Priority TXE
DMA
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
0
0
0
0
1
None
-
-
1
0
0
1
1
0
Receiver
Line Status
Overrun, Parity,
Framing or Break
Error
Read LSR register
2
0
0
1
0
0
Receiver
Data Available
Receive data is
available.
Read receive
register or read IIR
register
3
0
0
0
1
0
Transmitter
Holding Register
Empty
Transmit buffer
empty
Write transmit hold
register or read IIR
register
4
1
X
X
X
X
Transmitter
Register Empty
Transmit register
empty
Write transmit hold
register or read IIR
register
5
0
1
1
0
0
Rx DMA done
Rx DMA completed.
Read IIR register
6
0
1
0
1
0
Tx DMA done
Tx DMA completed.
Read IIR register
7
1
X
X
X
X
Transmitter
register
Empty
and DMA done
Transmitter regiser
Empty and Tx DMA
completed.
Read IIR register
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IID
IPEN
Interrupt sources
Interrupt
PRELIMINARY
Interrupt condition
Interrupt clear
131
Z32F3841 Product Specification
Un.LCR
UART
UART
Line Control Register
The UART Line Control Register is an 8-bit register.
U0.LCR=0x4000_800C, U1.LCR=0x4000_810C
U2.LCR=0x4000_820C, U3.LCR=0x4000_830C
7
0
6
5
4
3
2
BREAK
STICKP
PARITY
PEN
STOPBIT
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6
BREAK
5
STICKP
4
PARITY
3
PEN
2
STOPBIT
1
0
DLEN
1
0
DLEN
When this bit is set, TxD pin will be driven at low state in order to
notice the alert to the receiver.
0
Normal transfer mode
1
Break transmit mode
Force parity and it will be effective when PEN bit is set.
0
Parity stuck is disabled
1
Parity stuck is enabled and parity always the bit of PARITY.
Parity mode selection bit and stuck parity select bit
0
Odd parity mode
1
Even parity mode
Parity bit transfer enable
0
The parity bit disabled
1
The parity bit enabled
The number of stop bit followed by data bits.
0
1 stop bit
1
1.5 / 2 stop bit
In case of 5 bit data case, 1.5 stop bit is added. In case of 6,7 or
8 bit data, 2 stop bit is added
The data length in one transfer word.
00
5 bit data
01
6 bit data
10
7 bit data
11
8 bit data
The parity bit is generated according to bits 3,4,5 of the UnLCR register. Table 13.4 shows the variation of
parity bit generation.
Table 13.4. Parity Bit Generation
PS034603-0617
STICKP
PARITY
PEN
Parity
X
X
0
No Parity
0
0
1
Odd Parity
0
1
1
Even Parity
1
0
1
Force parity as “1”
1
1
1
Force parity as “0”
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132
Z32F3841 Product Specification
Un.DCR
UART
UART
Data Control Register
The UART Data Control Register is an 8-bit register.
U0DCR=0x4000_8010, U1DCR=0x4000_8110
U2DCR=0x4000_8210, U3DCR=0x4000_8310
7
0
6
5
0
4
0
0
3
RXINV
2
TXINV
3
2
RXINV
TXINV
0
0
R/W
R/W
1
0
0
0
Rx Data Inversion Selection
0
Normal RxData Input
1
Inverted RxData Input
Tx Data Inversion Selection
0
Normal TxData Output
1
Inverted TxData Output
Figure 13.2. Data Inversion Diagram
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Z32F3841 Product Specification
Un.LSR
UART
UART Line Status Register
The UART Line Status Register is an 8-bit register.
U0LSR=0x4000_8014, U1LSR=0x4000_8114
U2LSR=0x4000_8214, U3LSR=0x4000_8314
7
6
5
4
3
2
1
0
-
TEMT
THRE
BI
FE
PE
OE
DR
0
1
1
0
0
0
0
0
R
R
R
R
R
R
R
6
TEMT
5
THRE
4
BI
3
FE
2
PE
1
OE
0
DR
Transmit empty.
0
Transmit register has the data is now transferring
1
Transmit register is empty.
Transmit holding empty.
0
Transmit holding register is not empty.
1
Transmit holding register empty
Break condition indication bit
0
Normal status
1
Break condition is detected
Frame Error.
0
No framing error.
1
Framing error. The receive character did not have a valid
stop bit
Parity Error
0
No parity error
1
Parity error. The receive character does not have correct
parity information.
Overrun error
0
No overrun error
1
Overrun error. Additional data arrives while the RHR is
full
Data received
0
No data in receive holding register.
1
Data has been received and is saved in the receive
holding register
This register provides the status of data transfers between the transmitter and receiver. Users can get line
status information from this register and can handle the next process. Bits 1,2,3,4 will arise the line status
interrupt when the RLSIE bit in the UnIEN register is set. Other bits can generate its interrupt when the
interrupt enable bit in the UnIEN register is set.
Un.BDR
Baud rate Divisor Latch Register
The UART Baud rate Divisor Latch Register is a 16-bit register.
U0.BDR=0x4000_8020, U1.BDR=0x4000_8120
U2.BDR=0x4000_8220, U3.BDR=0x4000_8320
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BDR
0x0000
R/W
15
0
PS034603-0617
BDR
Baud rate Divider latch value
PRELIMINARY
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Z32F3841 Product Specification
UART
To establish communication with the UART channel, the baud rate should be set correctly. The programmable
baud rate generation allows division from 1 to 65535. The 16 bit divider register (UnBDR) should be written for
the expected baud rate.
The baud rate calculation formula is shown in the following equation:
BDR =
𝑈𝐴𝑅𝑇𝑃𝐶𝐿𝐾
32 × 𝐵𝑎𝑢𝑑𝑅𝑎𝑡𝑒
For an 72 MHz UART_PCLK speed, the divider value and error rate is described in Table 13.5.
Table 13.5. Example of Baud Rate Calculation
UART_PCLK=72 MHz
PS034603-0617
Baud rate
Divider
Error (%)
1200
1875
0.00%
2400
937
0.05%
4800
468
0.16%
9600
234
0.16%
19200
117
0.16%
38400
58
1.02%
57600
39
0.16%
115200
19
2.79%
PRELIMINARY
135
Z32F3841 Product Specification
Un.BFR
UART
Baud rate Fraction Counter Register
The Baud rate Fraction Counter Register is an 8-bit register.
U0.BFR=0x4000_8024, U1.BFR=0x4000_8124
U2.BFR=0x4000_8224, U3.BFR=0x4000_8324
7
6
5
4
3
2
1
0
BFR
0x00
R/W
7
0
BFR
Fractions counter value.
0
Fraction counter is disabled
N
Fraction counter enabled. Fraction compensation mode
is operating. Fraction counter is incremented by FCNT.
Table 13.6 Example of Baud Rate Calculation
UART_PCLK=72 MHz
Baud rate
Divider
FCNT
Error (%)
1200
2400
1875
0
0.0%
937
128
0.0%
4800
468
192
0.0%
9600
234
96
0.0%
19200
117
48
0.0%
38400
58
152
0.0%
57600
39
16
0.0%
115200
19
136
0.0%
FCNT = Float ∗ 256
The 8-bit fractional counter will count up by the FCNT value every (baud rate)/16 period and when the
fractional counter overflow occurs, the divisor value increments by 1. Therefore. this period is compensated. In
the next period, the divisor value returns to the original set value.
For example, if 9600 bps,
PCLK / 2
72000000 / 2
=
16 x BaudRate
=
234.375
Divider = 234
Float=.375
16 x 9600
FCNT = Float x
256 = .375 x 256 = 96
BDR = 234, BFR = 96
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Z32F3841 Product Specification
Un.IDTR
UART
Inter-frame Delay Time Register
The UART Inter-frame Time Register is an 8-bit register. A dummy delay can be inserted between two
continuous transmits.
U0.IDTR=0x4000_8030, U1.IDTR=0x4000_8130
U2.IDTR=0x4000_8230, U3.IDTR=0x4000_8330
7
6
5
4
3
2
1
0
0
0
WAITVAL
0
0
0
000
RW
2
0
WAITVAL
Wait time is decided by this value
𝐖𝐚𝐢𝐭 𝐓𝐢𝐦𝐞 =
𝑾𝑨𝑰𝑻𝑽𝑨𝑳
𝑩𝑨𝑼𝑫𝑹𝑨𝑻𝑬
Functional Description
The UART module is compatible with the 16450 UART. Additionally, dedicated DMA channels and fractional
baud rate compensation logic are provided. The UART does not have an internal FIFO block. Therefore, data
transfers are established interactively or with DMA support.
Two DMA channels are provided for each UART module – one channel for TX transfer and the other channel
for RX transfer. Each channel has a 32-bit memory address register and a 16-bit transfer counter register.
Prior to the DMA operation, the DMA memory address register and transfer count register should be
configured. For the RX operation, the memory address is the destination memory address and for the TX
operation, the memory address is the source memory address.
The transfer counter register stores the number of data transfers. When a single transfer is done, the counter
is decremented by 1. When the counter reaches zero, the DMA done flag is delivered to the UART control
block. If the interrupt is enabled, this flag generates the interrupt.
Receiver Sampling Timing
The UART operates per the following timing:
If the falling edge is on the receive line, the UART judges it as the start bit. From the start timing, the UART
oversamples 16 times of 1-bit and detects the bit value at the 7th sample of 16 samples.
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Z32F3841 Product Specification
UART
START bit
UnRXD
STOP bit
0
1
0
0
Bit 0
Bit 1
Bit 2
0
0
0
1
0
Bit 6
Bit 7
Bit Samples
Start bit
Bit
3
Bit
4
Bit
5
Stop bit
UnRXD
SubSample
0
1
2 3
4
5
6
10 1 12 13 14 1
5
1
Bit Sampling Position (7/16)
7
8
9
Figure 13.3 The Sampling Timing of UART Receiver
Note: Zilog recommends enabling debounce settings in the PCU block to reinforce the immunity of external
glitch noise.
Transmitter
The transmitter’s function is to transmit data. The start bit, data bits, optional parity bit, and stop bit are serially
shifted with the least significant bit first. The number of data bits is selected in the DLAN[1:0] field in the
Un.LCR register.
The parity bit is set according to the PARITY and PEN bit field in the Un.LCR register. If the parity type is even,
then the parity bit depends on the one bit sum of all data bits. For odd parity, the parity bit is the inverted sum
of all data bits.
The number of stop bits is selected in the STOPBIT field in the Un.LCR register.
An example of transmit data format is shown in Figure 13.4.
Figure 13.4. Transmit Data Format Example
Inter-frame Delay Transmission
The Inter-frame Delay function allows the transmitter to insert an idle state on the TXD line between two
characters. The width of the idle state is defined in the WAITVAL field in the Un.IDTR register. When this field
is set to 0, no time-delay is generated. Otherwise, the transmitter holds a high level on TXD after each
transmitted character during the number of bit periods defined in the WATIVAL field.
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Z32F3841 Product Specification
UART
Figure 13.5. Inter-frame Delay Timing Diagram
Transmit Interrupt
The transmit operation generates interrupt flags. When the transmitter holding register is empty, the THRE
interrupt flag is set. Whe the transmitter shifter register is empty, the TXE interrupt flag is set. Users can select
which interrupt timing is best for the application.
Figure 13.6. Transmit Interrupt Timing Diagram
DMA Transfers
The UART supports the DMA interface function (optionally provided, depending on the device). The start
memory address for transfer data and the length of transfer data are programmd in the registers in the DMA
block.
The end of transfer is notified via the related transfer done flag.
Transmit with DMA operation invokes the DTX.UnIIR DMA TX done flag and sets the DMA TX done interrupt
ID when all the transmit data are written to the transmit holding register. Two transmit data values remain in
the registers of the UART block after the DMA transfer done interrupt.
Receive with DMA operation invokes the RXT.UnIIR DMA RX done flag and sets the DMA RX done interrupt
ID when all the receive data are written to the destination memory. Therefore, the UART RXD signal is already
in IDLE state when the DMA RX done interrupt is issued.
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Z32F3841 Product Specification
Serial Peripheral Interface
14. Serial Peripheral Interface
Overview
2-channel serial interfaces are provided for synchronous serial communications with external peripherals. The
SPI block supports the master and slave modes. Four signals are used for SPI communication – SS, SCK,
MOSI, and MISO.
Master or Slave operation
Programmable clock polarity and phase
8,9,16,17-bit wide transmit/receive register
8,9,16,17-bit wide data frame
Loop-back mode
Programmable start, burst, and stop delay time
DMA handshake operation
PRESET
TxSData[16:0]
TxData[16:0]
Tx Data
PSEL
Tx
Shifter
Register
SS
PENABLE
PWRITE
PADDR
PWDATA[31:0]
SCK
Transmit/
Register
Receive
block
MOSI
MISO
logic
RxSData[16:0]
RxData[16:0]
R
Rx Data
PRDATA[31:0]
xShifter
Register
PENABLE
PENABLE
DMA req
( Tx & Rx)
Clock
SPICLKDIV
divider
SSDET
TRDY
DMA en (Tx & Rx)
DMA ack ( Tx & Rx)
DMA done (Tx & Rx)
RRDY
Interrupt
SPIIRQ
generator
DMA Tx/Rx done Interrupt
Figure 14.1. SPI Block Diagram
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Z32F3841 Product Specification
Serial Peripheral Interface
Pin Description
Table 14.1. External Pins
PIN NAME
TYPE
DESCRIPTION
SS0
I/O
SPI0 Slave select input / output
SCK0
I/O
SPI0 Serial clock input / output
MOSI0
I/O
SPI0 Serial data ( Master output, Slave input )
MISO0
I/O
SPI0 Serial data ( Master input, Slave output )
SS1
I/O
SPI1 Slave select input / output
SCK1
I/O
SPI1 Serial clock input / output
MOSI1
I/O
SPI1 Serial data ( Master output, Slave input )
MISO1
I/O
SPI1 Serial data ( Master input, Slave output )
Registers
The base address of SPI is 0x4000_9000 and the register map is described in Tables 14.2 and 14.3.
Table 14.2. SPI Base Address
Channel
Base address
SPI0
0x4000_9000
SPI1
0x4000_9100
Table 14.3 SPI Register Map
PS034603-0617
Name
Offset
TYPE
Description
SPn.TDR
0x--00
W
SPI n Transmit Data Register
-
SPn.RDR
0x--00
R
SPI n Receive Data Register
0x000000
SPn.CR
0x--04
R/W
SPI n Control Register
0x001020
SPn.SR
0x--08
R/W
SPI n Status Register
0x000006
SPn.BR
0x--0C
R/W
SPI n Baud rate Register
0x0000FF
SPn.EN
0x--10
R/W
SPI n Enable register
0x000000
SPn.LR
0x--14
R/W
SPI n delay Length Register
0x010101
PRELIMINARY
Reset
141
Z32F3841 Product Specification
SPn.CR
Serial Peripheral Interface
SPI n Control Register
SPnCR is a 20-bit read/write register and can be set to configure SPI operation mode.
TXBC
19
RXBC
18
DTXIE
17
DRXIE
16
SSCIE
15
TXIE
14
RXIE
13
SSMOD
12
SSOUT
11
LBE
10
SSMASK
9
SSMO
8
SSPOL
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
BITSZ
1
0
0
1
0
0
0
00
RW
SSPOL
0
CPOL
SSMO
0
CPHA
SSMASK
0
RW
LBE
0
RW
SSOUT
0
5
MSBF
SSMOD
0
6
RW
RXIE
0
7
MS
TXIE
0
RW
0
SSCIE
0
RW
0
20
7
6
PS034603-0617
0
DTXIE
0
DRXIE
0
RW
0
RW
0
RXBC
0
RW
0
8
TXBC
0
9
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
SP0.CR=0x4000_9004, SP1.CR=0x4000_9104
4
3
2
1
0
Tx buffer clear bit.
0
No action
1
Clear Tx buffer
Rx buffer clear bit
0
No action
1
Clear Rx buffer
DMA Tx Done Interrupt Enable bit.
0
DMA Tx Done Interrupt is disabled.
1
DMA Tx Done Interrupt is enabled.
DMA Rx Done Interrupt Enable bit.
0
DMA Rx Done Interrupt is disabled.
1
DMA Rx Done Interrupt is enabled.
nSS Edge Change Interrupt Enable bit.
0
nSS interrupt is disabled.
1
nSS interrupt is enabled for both edges (LH, HL)
Transmit Interrupt Enable bit.
0
Transmit Interrupt is disabled.
1
Transmit Interrupt is enabled.
Receive Interrupt Enable bit..
0
Receive Interrupt is disabled.
1
Receive Interrupt is enabled.
SS Auto/Manual output select bit.
0
SS output is not set by SSOUT (SPnCR[12]).
- SS signal is in normal operation mode.
1
SS output signal is set by SSOUT.
SS output signal select bit.
0
SS output is ‘L.’
1
SS output is ‘H’.
Loop-back mode select bit in master mode.
0
Loop-back mode is disabled.
1
Loop-back mode is enabled.
SS signal masking bit in slave mode.
0
SS signal masking is disabled.
- Receive data when SS signal is active.
1
SS signal masking is enabled.
- Receive data at SCLK edges. SS signal is ignored.
SS output signal select bit.
0
SS output signal is disabled.
1
SS output signal is enabled.
SS signal Polarity select bit.
0
SS signal is Active-Low.
1
SS signal is Active-High.
Reserved
PRELIMINARY
142
Z32F3841 Product Specification
5
MS
4
MSBF
3
CPHA
2
CPOL
1
BITSZ
0
Serial Peripheral Interface
Master/Slave select bit.
0
SPI is in Slave mode.
1
SPI is in Master mode.
MSB/LSB Transmit select bit.
0
LSB is transferred first.
1
MSB is transferred first.
SPI Clock Phase bit.
0
Sampling of data occurs at odd edges (1,3,5,…,15).
1
Sampling of data occurs at even edges (2,4,6,…,16).
SPI Clock Polarity bit.
0
Active-high clocks selected.
1
Active-low clocks selected.
Transmit/Receive Data Bits select bit.
00 8 bits
01 9 bits
10 16 bits
11 17 bits
CPOL=0, CPHA=0 : data sampling at rising edge, data changing at falling edge
CPOL=0, CPHA=1 : data sampling at falling edge, data changing at rising edge
CPOL=1, CPHA=0 : data sampling at falling edge, data changing at rising edge
CPOL=1, CPHA=1 : data sampling at rising edge, data changing at falling edge
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Z32F3841 Product Specification
SPn.SR
Serial Peripheral Interface
SPI n Status Register
SPnSR is a 10-bits read/write register. It contains the status of SPI interface.
14
13
12
11
10
9
TXDMAF
RXDMAF
SBUSY
SSDET
SSON
OVRF
UDRF
SRDY
TRDY
RRDY
SP0.SR=0x4000_9008, SP1.SR=0x4000_9108
15
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
RC1
RC1
R
RC1
RC1
RC1
RC1
R
R
R
PS034603-0617
9
TXDMAF
8
RXDMAF
8
SBUSY
6
SSDET
5
SSON
4
OVRF
3
UDRF
2
SRDY
1
TRDY
0
RRDY
8
7
6
5
4
3
2
1
0
DMA Transmit Operation Complete flag. (DMA to SPI)
0
DMA Transmit Op is working or is disabled.
1
DMA Transmit Op is done.
DMA Receive Operation Complete flag. (SPI to DMA )
0
DMA Receive Operation is working or is disabled.
1
DMA Transmit Op is done.
Transmit/Receive Operation flag
0
SPI is in IDLE state
1
SPI is operating
The rising or falling edge of SS signal Detect flag.
0
SS edge is not detected.
1
SS edge is detected.
- The bit is cleared when it is written as “0”.
SS signal Status flag.
0
SS signal is inactive.
1
SS signal is active.
Receive Overrun Error flag.
0
Receive Overrun error is not detected.
1
Receive Overrun error is detected.
- This bit is cleared by writing or reading SPnRDR.
Transmit Underrun Error flag.
0
Transmit Underrun is not occurred.
1
Transmit Underrun is occurred.
- This bit is cleared by writing or reading SPnTDR.
Shift register Empty flag.
0
Shift register is busy.
1
Shift register is ready.
- This bit is cleared by writing SPnTDR to Shift rgister and is TRDY’s
complement when SSON is active.
Transmit buffer Empty flag.
0
Transmit buffer is busy.
1
Transmit buffer is ready.
- This bit is cleared by writing data to SPnTDR.
Receive buffer Ready flag.
0
Receive buffer has no data.
1
Receive buffer has data.
- This bit is cleared by writing data to SPnRDR.
PRELIMINARY
144
Z32F3841 Product Specification
SPn.TDR
Serial Peripheral Interface
SPI n Transmit Data Register
SPnTDR is a 17-bit read/write register. It contains serial transmit data.
SP0.TDR=0x4000_9000, SP1.TDR=0x4000_9100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TDR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00000
RW
16
0
TDR
SPn.RDR
Transmit Data Register
SPI n Receive Data Register
SPnRDR is a 17-bit read/write register. It contains serial receive data.
SP0.RDR=0x4000_9000, SP1.RDR=0x4000_9100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RDR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00000
RW
16
0
RDR
SPn.BR
Receive Data Register
SPI n Baud Rate Register
SPnBR is an16-bit read/write register. Baud rate can be set by writing to this register.
SP0.BR=0x4000_900C, SP1.BR=0x4000_910C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BR
0x00FF
RW
15
0
PS034603-0617
BR
Baud rate setting bits
- Baud Rate = PCLK / (BR + 1).
(BR must be bigger than “0”, BR >= 2 )
PRELIMINARY
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Z32F3841 Product Specification
SPn.EN
Serial Peripheral Interface
SPI n Enable Register
SPnEN is a single-bit read/write register. It contains SPI enable bit.
SP0.EN=0x4000_9010, SP1.EN=0x4000_9110
7
6
5
4
3
2
1
0
ENABLE
0
0
0
0
0
0
0
0
RW
0
ENABLE
SPI Enable bit
0 SPI is disabled.
- SPnSR is initialized by writing “0” to this bit but other registers aren’t
initialized.
1 SPI is enabled.
- When this bit is written as “1”, the dummy data of transmit buffer will be
shifted. To prevent this, write data to SPTDR before this bit is active.
Note: When in SPI Slave mode, be sure to disable the SPI prior to loading the TDR register, then enable it to
prevent an extra byte from being sent.
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146
Z32F3841 Product Specification
SPn.LR
Serial Peripheral Interface
SPI n delay Length Register
SPnLR is a 24-bit read/write register. It contains start, burst, and stop length value.
SP0.CR=0x4000_9014, SP1.CR=0x4000_9114
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
0
0
0
0
0
0
0
23
16
15
SPL
STL
6
5
4
3
STL
0x01
0x01
0x01
RW
RW
RW
2
1
0
StoPLength value
(SPL >= 1)
BursTLength value
(BTL >= 1)
STart Length value
0x01 ~ 0xFF : 1 ~ 255 SCLKs.
0
7
BTL
0x01 ~ 0xFF : 1 ~ 255 SCLKs.
8
7
8
SPL
0x01 ~ 0xFF : 1 ~ 255 SCLKs.
BTL
9
(STL >= 1)
SS
STL
SPL
SCLK
BTL
MISO
MISO
MISO
MOSI
MOSI
MOSI
Figure14.1. SPI Waveform (STL, BTL, and SPL)
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Z32F3841 Product Specification
Serial Peripheral Interface
Functional Description
The SPI Transmit and Receive blocks share Clock Gen Block but they are independent of each other. The
Transmit and Receive blocks have double buffers and SPI is available for back-to-back transfer operation.
SPI Timing
The SPI has four modes of operation. These modes essentially control the way data is clocked in or out of an
SPI device. The configuration is done by two bits in the SPI control register (SPnCR). The clock polarity is
specified by the CPOL control bit, which selects an active high or active low clock. The clock phase (CPHA)
control bit selects one of the two fundamentally different transfer formats. To ensure effective communication
between master and slave, both devices have to run in the same mode. This can require a reconfiguration of
the master to match the requirements of different peripheral slaves.
The clock polarity has no significant effect on the transfer format. Switching this bit causes the clock signal to
be inverted (active high becomes active low and idle low becomes idle high). The settings of the clock phase,
however, select one of the two different transfer timings, which are described in the next two chapters. Since
the MOSI and MISO lines of the master and the slave are directly connected to each other, the diagrams
show the timing of both devices, master and slave. The nSS line is the slave select input of the slave. The
nSS pin of the master is not shown in the diagrams. It has to be inactive by a high level on this pin (if
configured as input pin) or by configuring it as an output pin.
The timing of a SPI transfer where CPHA is zero is shown in Figures 10.3 and 10.4. Two wave forms are shown for the
SCK signal – one where CPOL equals zero and another where CPOL equals one.
When the SPI is configured as a slave, the transmission starts with the falling edge of the /SS line. This
activates the SPI of the slave and the MSB of the byte stored in its data register (SPnTDR) is output on the
MISO line. The actual transfer is started by a software write to the SPnTDR of the master. This causes the
clock signal to be generated. If the CPHA equals zero, the SCLK signal remains zero for the first half of the
first SCLK cycle. This ensures that the data is stable on the input lines of both the master and the slave. The
data on the input lines is read with the edge of the SCLK line from its inactive to its active. The edge of the
SCLK line from its active to its inactive state (falling edge if CPOL equals zero and rising edge if CPOL equals
one) causes the data to be shifted one bit further so that the next bit is output on the MOSI and MISO lines.
SS
SCK
MOSI
D0
D1
D2
D3
D4
D5
D6
D7
MISO
D0
D1
D2
D3
D4
D5
D6
D7
Figure 14.2.SPI Transfer Timing 1/4 (CPHA=0, CPOL=0, MSBF=0)
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Z32F3841 Product Specification
Serial Peripheral Interface
SS
SCK
MOSI
D7
D6
D5
D4
D3
D2
D1
D0
MISO
D7
D6
D5
D4
D3
D2
D1
D0
Figure 14.3.SPI Transfer Timing 2/4 (CPHA=0, CPOL=1, MSBF=1)
The timing of a SPI transfer where CPHA is one is shown in Figure 10.5 and 10.6. Two wave forms are shown for the
SCLK signal – one when CPOL equals zero and another when CPOL equals one.
Similar to the pevious case, the falling edge of the nSS lines selects and activates the slave. Compared to the
previous case, where CPHA equals zero, the transmission is not started and the MSB is not output by the
slave at this stage. The actual transfer is started by a software write to the SPnTDR of the master that causes
the clock signal to be generated. The first edge of the SCLK signal from its inactive to its active state (rising
edge if CPOL equals zero and falling edge if CPOL equals one) causes both the master and the slave to
output the MSB of the byte in the SPnTDR.
As shown in Figures 14.3 and 14.4, there is no delay of half a SCLK-cycle. The SCLK line changes its level
immediately at the beginning of the first SCLK-cycle. The data on the input lines is read with the edge of the
SCLK line from its active to its inactive state (falling edge if CPOL equals zero and rising edge if CPOL equals
one). After eight clock pulses the transmission is completed.
SS
SCK
MOSI
D0
D1
D2
D3
D4
D5
D6
D7
MISO
D0
D1
D2
D3
D4
D5
D6
D7
Figure 14.4.SPI Transfer Timing 3/4 (CPHA=1, CPOL=0, MSBF=0)
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Serial Peripheral Interface
SS
SCK
MOSI
D7
D6
D5
D4
D3
D2
D1
D0
MISO
D7
D6
D5
D4
D3
D2
D1
D0
Figure 14.5.SPI Transfer Timing 4/4 (CPHA=1, CPOL=1, MSBF=1)
DMA Handshake
SPI supports DMA handshaking operation. In order to operate DMA handshake, DMA registers should be set
first. (See Chapter 9. Direct Memory Access Contoller). SPI0 has 2 channels of DMA, channel 8 for receiver
and channel 9 for transmitter. SPI1 has channel 10 for receiver and channel 11 for transmitter. Because the
transmitter and receiver are independent of each other, SPI can operate the two channels at the same time.
After the DMA channel for receiver is enabled and the receive buffer is filled, SPI sends Rx request to DMA to
empty the buffer and waits for an ACK signal from DMA. If the Receive buffer is filled again after ACK signal,
SPI sends an Rx request. If DMA Rx DONE becomes high, RXDMAF (SPnSR[8]) goes “1” and an interrupt is
serviced when RXDIE (SPnCR[17]) is set.
Similarly, if the transmit buffer is empty after the DMA channel for transmitter is enabled, SPI sends a Tx
request to DMA to fill the buffer and waits for an ACK signal from DMA. If the transmit buffer is empty again
after the ACK signal, SPI sends a Tx request. If DMA Tx DONE becomes high, TXDMAF(SPnSR[9]) goes “1”
and an interrupt is serviced when TXDIE(SPnCR[18]) is set.
The slave transmitter sends dummy data at the first transfer (8~17 SCLKs) in DMA handshake mode.
DMA EN
IDLE
Rx or Tx
Req
(to DMA)
DONE
INT gen
SPnSR[9] or [8] set
DMA DONE
DMA ACK
WAIT
Figure 14.6.DMA Handshake Flowchart
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I2C Interface
15. I2C Interface
Overview
2
2
The Inter-Integrated Circuit (I C) bus serves as an interface between the microcontroller and the serial I C bus.
It provides two wires and a serial bus interface to a large number of popular devices and allows parallel-bus
2
systems to communicate bidirectionally with the I C-bus.
Master and slave operation
Programmable communication speed
Multi-master bus configuration
7-bit addressing mode
Standard data rate of 100/400 kbps
STOP signal generation and detection
START signal generation
ACK bit generation and detection
Slave Addr. Register
(I2CSAR)
Debounce
Slave Addr. Register1
(I2CSAR1)
enable
SDA
Noise
Canceller
(debounce)
1
SDAIN
F/F
8-bit Shift Register
(SHFTR)
SDA
Out Controller
Data Out Register
(I2CDR)
0
SDAOUT
Debounce
SCL High Period Register
(I2CSCLHR)
enable
SCLIN
SCL
Noise
Canceller
(debounce)
SCL
Out Controller
1
0
SCL Low Period Register
(I2CSCLLR)
SDAHoldTimeRegister
(I2CDAHR)
I
n
t
e
r
n
a
l
B
u
s
L
i
n
e
SCLOUT
2
Figure 15.1. I C Block Diagram
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I2C Interface
Pin Description
2
Table 15.1. I C Interface External Pins
PIN NAME
TYPE
DESCRIPTION
2
SCL0
I/O
I C channel 0 Serial clock bus line (open-drain)
SDA0
I/O
I C channel 0 Serial data bus line (open-drain)
SCL1
I/O
I C channel 1 Serial clock bus line (open-drain)
SDA1
I/O
I C channel 1 Serial data bus line (open-drain)
2
2
2
Registers
2
2
The base address of I C0 is 0x4000_A000 and the base address of I C1 is 0x4000_A100. The register map
is described in Tables 15.2 and 15.3.
2
Table 15.2. I C Interface Base Address
Channel
Base address
2
0x4000_A000
2
0x4000_A100
I C0
I C1
2
Table 15.3. I C Register Map
Name
Offset
R/W
IC0.DR
0xA000
R/W
IC0.SR
0xA008
R, R/W
0xFF
2
0x00
2
0x00
2
0x00
2
0xFFFF
2
0xFFFF
2
0x7F
2
0xFF
2
0x00
2
0x00
2
0x00
2
0xFFFF
2
0xFFFF
2
0x007F
I C0 Status Register
0xA00C
R/W
I C0 Slave Address Register
IC0.CR
0xA014
R/W
I C0 Control Register
IC0.SCLL
0xA018
R/W
I C0 SCL LOW duration Register
IC0.SCLH
0xA01C
R/W
I C0 SCL HIGH duration Register
IC0.SDH
0xA020
R/W
I C0 SDA Hold Register
IC1.DR
0xA100
R/W
I C1 Data Register
0xA108
R, R/W
Reset
2
I C0 Data Register
IC0.SAR
IC1.SR
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Description
I C1 Status Register
IC1.SAR
0xA10C
R/W
I C1 Slave Address Register
IC1.CR
0xA114
R/W
I C1 Control Register
IC1.SCLL
0xA118
R/W
I C1 SCL LOW duration Register
IC1.SCLH
0xA11C
R/W
I C1 SCL HIGH duration Register
IC1.SDH
0xA120
R/W
I C1 SDA Hold Register
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I2C Interface
ICn.DR I2C Data Register
ICnDR is an 8-bit read/write register. It contains a byte of serial data to be transmitted or a byte which has just
been received.
IC0.DR=0x4000_A000, IC1.DR=0x4000_A100,
7
6
5
4
3
2
1
0
ICDR
0xFF
RW
7
0
ICDR
The most recently received data or data to be transmitted.
ICn.SR I2C Status Register
2
ICnSR is an 8-bit read/write register. It contains the status of I C bus interface. Writing to the register clears
the status bits except for IMASTER.
IC0.SR=0x4000_A008, IC1.SR=0x4000_A008
7
6
5
4
3
2
1
0
GCALL
TEND
STOP
SSEL
MLOST
BUSY
TMODE
RXACK
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
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GCALL
6
TEND
5
STOP
4
SSEL
3
MLOST
2
BUSY
1
TMODE
0
RXACK
General call flag
0
General call is not detected.
1
General call detected.
1 Byte transmission complete flag
0
The transmission is working or not completed.
1
The transmission is completed.
STOP flag
0
STOP is not detected.
1
STOP is detected.
Slave flag (Start condition received)
0
Slave is not selected.
1
Slave is selected.
Mastership lost flag
0
Mastership is not lost.
1
Mastership is lost.
BUSY flag
2
0
I C bus is in IDLE state.
2
1
I C bus is busy.
Transmitter/Receiver mode flag
0
Receiver mode.
1
Transmitter mode.
Rx ACK flag
0
Rx ACK is not received.
1
Rx ACK is received.
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I2C Interface
I2C Slave Address Register
ICn.SAR
ICnSAR is an 8-bit read/write register. It shows the address in slave mode.
IC0.SAR=0x4000_A00C, IC1.SAR=0x4000_A10C
7
6
5
4
3
SVAD
7
1
0
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1
0
GCEN
0x00
0
RW
RW
SVAD
7-bit Slave Address
GCEN
General call enable bit
0
General call is disabled.
1
General call is enabled.
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Z32F3841 Product Specification
I2C Interface
ICn.CR I2C Control Register
2
ICnCR is an 8-bit read/write register. The register can be set to configure I C operation mode and
2
simultaneously allows for I C transactions to be kicked off.
0
0
0
0
0
9
8
INTDEL
7
IIF
6
I2CEN
5
SOFTRST
4
INTEN
3
ACKEN
1
STOP
0
START
8
7
6
5
4
3
00
0
0
0
0
0
RW
R
RW
RW
RW
RW
2
1
0
START
0
9
ACKEN
10
INTEN
11
SOFTRST
12
I2CEN
13
IIF
14
INTDEL
15
STOP
IC0CR=0x4000_A014, IC1CR=0x4000_A114
0
0
0
RW
RW
Interval delay value between address and data transfer (or DATA and DATA)
0
1 * ICnSCLL
1
2 * ICnSCLL
2
4 * ICnSCLL
3
8 * ICnSCLL
Interrupt status bit
0
Interrupt is inactive
1
Interrupt is active
I2C enable bit
0
I2C disabled
1
I2C enabled
Soft Reset enable bit.
0
Soft Reset is disabled.
1
Soft Reset is enabled..
Interrupt enabled bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
ACK enable bit in Receiver mode.
0
ACK is not sent after receiving data.
1
ACK is sent after receiving data.
Stop enable bit. When this bit is set as “1” in transmitter mode, next
transmission will be stopped even though ACK signal has been received.
0
Stop is disabled.
1
Stop is enabled. When this bit is set, transmission will be stopped.
Transmission start bit in master mode.
0
Waits in slave mode.
1
Starts transmission in master mode.
Figure15.1. INTDEL in Master Mode
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I2C Interface
I2C SCL LOW Duration Register
ICn.SCLL
ICnSCLL is a 16-bit read/write register. The SCL LOW time is set by writing this register in master mode.
IC0.SDLL=0x4000_A018, IC1.SDLL=0x4000_A118
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCLL
0xFFFF
RW
15
0
SCLL
SCL LOW duration value.
SCLL = ( PCLK * SCLL[15:0] ) + 2*PCLKs
Default value is 0xFFFF.
SCLL
SCL
Figure 15.2. SCL LOW Timing
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I2C Interface
I2C SCL HIGH Duration Register
ICn.SCLH
ICnSCLH is a 16-bit read/write register. The SCL HIGH time is set by writing this register in master mode.
IC0.SDLH=0x4000_A01C, IC1.SDLH=0x4000_A11C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCLH
0xFFFF
RW
15
0
SCLH
SCL HIGH duration value.
SCLH = ( PCLK * SCLH[15:0] ) + 3 PCLKs
Default value is 0xFFFF.
SCLH
SCL
Figure 15.3.SCL HIGH Timing
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ICn.SDH
I2C Interface
SDA Hold Register
ICnSDH is a 15-bit read/write register. The SDA HOLD time is set by writing this register in master mode.
IC0.SDH=0x4000_A020, IC1.SDH=0x4000_A120
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SDH
0x007F
RW
14
SDH
0
SDA HOLD time setting value.
SDH = ( PCLK * SDH[14:0] ) + 4 PCLKs
Default value is 0x3FFF.
SDH
SDA
SCL
Figure 15.4.SDA HOLD Timing
Functional Description
I2C Bit Transfer
The data on the SDA line must be stable during the “H” period of the clock. The “H” or “L” state of the data line
can only change when the clock signal on the SCL line is “L” as shown in Figure 15.5.
SDA
SCL
Data line Stable:
Data valid
exept S, Sr, P
Change of Data
allowed
2
Figure 15.5. I C Bus Bit Transfer
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I2C Interface
START/Repeated START/STOP
2
Within the procedure of the I C-bus, unique situations arise which are defined as START(S) and STOP(P)
conditions (see Figure 15.6.).
An “H” to “L” transition on the SDA line while SCL is “H” is one such unique case. This situation indicates a
START condition.
An “L” to “H” transition on the SDA line while SCL is “H” defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered to be busy after the
START condition. The bus is considered to be free again a certain time after the STOP condition.
The bus is busy if a repeated START(Sr) is generated instead of a STOP condition. In this respect, the
START(S) and repeated START(Sr) conditions are functionally identical. Therefore, for the remainder of this
document, the S symbol will be used as a generic term to represent both the START and repeated START
conditions, unless Sr is particularly relevant.
Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the
necessary interfacing hardware. However, microcontrollers with no such interface have to sample the SDA
line at least twice per clock period to sense the transition.
SDA
SCL
S
P
START Condition
STOP Condition
Figure 15.6. START and STOP Condition
Data Transfer
Every byte put on the SDA line must be 8-bit long. The number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant
bit (MSB) first (see Figure 15.7). If a slave cannot receive or transmit another complete byte of data until it has
performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL “L” to
force the master into a wait state. Data transfer then continues when the slave is ready for another byte of
data and releases clock line SCL.
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I2C Interface
A message which starts with such an address can be terminated by generation of a STOP conditions, even
during the transmission of a byte. In this case, no acknowledge is generated.
P
SDA
MSB
Acknowledgement
Acknowledgement
Signal form Slave
Byte Complete,
Signal form Slave
Clock line held low while
Interrupt within Device
SCL
S
or
Sr
1
Sr
interrupts are served.
9
1
ACK
9
ACK
Sr
or
P
START or Repeated
STOPor Repeated
START Condition
START Condition
2
Figure 15.7. I C Bus Data Transfer
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I2C Interface
Acknowledge
Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse.
The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable “L”
during the “H” period of this clock pulse (see Figure 15.8). Additionally, set-up and hold times must also be
taken into account.
When a slave doesn’t acknowledge the slave address (for example, it’s unable to receive or transmit because
it’s performing some real-time function), the data line must be left “H” by the slave. The master can then
generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer.
If a slave-receiver acknowledges the slave address, but later in the transfer cannot receive any more data
bytes, the master must again abort the transfer. This is indicated by the slave generating the not-acknowledge
on the first byte to follow. The slave leaves the data line “H” and the master generates a STOP or a repeated
START condition.
If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not
generating an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must
release the data line to allow the master to generate a STOP or repeated START condition.
Data Output
By Transmitter
NACK
Data Output
By Receiver
ACK
1
SCL From MASTER
2
8
9
Clock pulse for ACK
2
Figure 15.8. I C Bus Acknowledge
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I2C Interface
Synchronization
2
All masters generate their own clock on the SCL line to transfer messages on the I C-bus. Data is only valid
during the “H” period of the clock. A defined clock is therefore needed for the bit-by-bit arbitration procedure to
take place.
2
Clock synchronization is performed using the wired-AND connection of I C interfaces to the SCL line. This
means that an “H” to “L” transition on the SCL line will cause the devices to start counting off their “L” period
and, after a device clock has gone “L”, it will hold the SCL line in that state until the clock “H” state is reached
(see Figure 15.9). However, the “L” to “H” transition of this clock may not change the state of the SCL line if
another clock is still within its “L” by the device with the longest “L” period. Devices with shorter “L” periods
enter an “H” wait-state during this time.
When all devices have counted off their “L” period, the clock line will be released and go “H”. There will then
be no difference between the device clocks and the state of the SCL line, and the devices will start counting
their “H” periods. The first device to complete its “H” period will again pull the SCL line “L”.
Wait High
Start High
Counting
Counting
Fast Device
SCLOUT
High Counter
Slow Device
SCLOUT
Reset
SCL
Figure 15.9.Clock Synchronization During the Arbitration Procedure
Arbitration
A master may start a transfer only if the bus is free. Two or more masters may generate a START condition
within the minimum hold time of the START condition which results in a defined START condition to the bus.
Arbitration takes place on the SDA line, while the SCL line is at the “H” level, in such a way that the master
which transmits “H” level, while another master is transmitting a “L” level will switch off its DATA output stage
because the level on the bus doesn’t correspond to its own level.
Arbitration can continue for many bits. Its first stage is comparison of the address bits. If the masters are each
trying to address the same device, arbitration continues with comparison of the data-bits if they are master2
transmitter, or acknowledge-bits if they are master-receiver. Because address and data information on the I Cbus is determined by the winning master, no information is lost during the arbitration process.
A master that loses the arbitration can generate clock pulses until the end of the byte in which it loses the
arbitration.
If a master also incorporates a slave function and it loses arbitration during the addressing stage, it is possible
that the winning master is trying to address it. The losing master must therefore switch over immediately to its
slave mode.
Figure 15.10 shows the arbitration procedure for two masters. There may be additional masters involved,
depending on how many masters are connected to the bus. As soon as there is a difference between the
internal data level of the master generating Device1 Dataout and the actual level on the SDA line, its data
output is switched off, which means that an “H” output level is then connected to the bus. This will not affect
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I2C Interface
the data transfer initiated by the winning master.
Arbitration Process not adapted
Device 1 loses Arbitration
Device1 outputs High
Device1
DataOut
Device2
DataOut
SDA on BUS
SCL on BUS
S
Figure 15.10. Arbitration Procedure of Two Masters
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I2C Interface
I2C OPERATION
2
I C supports interrupt operation. After the interrupt is serviced, the IIF(ICnSR[10]) flag is set. ICnSR shows
2
I C-bus status information and the SCL line stays “L” before the register is written as a certain value. The
status register can be cleared by writing any value to the status register.
Master Transmitter
The master transmitter shows the flow of the transmitter in Master mode as shown in Figure 15.11.
IDLE
Master
Receiver
SLA+R
S or Sr
SLA+W
ACK
N
STOP
P
Y
LOST
DATA
ACK
Rs
N
STOP
LOST
Cont?
Lost?
LOST&
STOP
Y
Y
LOST
P
Other master continues
Y
From master to slave /
Master command or Data Write
N
From slave to master
STOP
ACK
Interrupt, SCL line is held low
P
Interrupt after stop command
LOST&
Arbitration lost as master and
addressed as slave
P
Figure 15.11. Transmitter Flowchart in Master Mode
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Master Receiver
The master receiver shows the flow of the receiver in Master mode as shown in Figure 15.12.
IDLE
Master
Transmitter
SLA+W
S or Sr
SLA+R
N
ACK
STOP
P
Y
LOST
DATA
Rs
LOST
LOST&
Sr
ACK
N
STOP
P
Y
LOST
Other master continues
From master to slave /
Master command or Data Write
ACK
From slave to master
ACK
Interrupt, SCL line is held low
P
Interrupt after stop command
LOST&
Arbitration lost as master and
addressed as slave
Figure 15.12. Receiver Flowchart in Master Mode
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Slave Transmitter
The slave transmitter shows the flow of the transmitter in Slave mode, as shown in Figure 15.13.
IDLE
S or Sr
SLA+R
GCALL
ACK
LOST&
Y
DATA
Y
ACK
N
STOP
P
Y
IDLE
From master to slave /
Master command or Data Write
From slave to master
ACK
Interrupt, SCL line is held low
P
Interrupt after stop command
LOST&
Arbitration lost as master and
addressed as slave
GCALL
General Call Address
Figure 15.13. Transmitter Flowchart in Slave Mode
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Slave Receiver
The slave receiver shows the flow of the receiver in Slave mode, as shown in Figure 15.14.
IDLE
S or Sr
SLA+W
ACK
LOST&
GCALL
N
Y
DATA
Y
ACK
N
STOP
P
Y
IDLE
From master to slave /
Master command or Data Write
From slave to master
ACK
Interrupt, SCL line is held low
P
Interrupt after stop command
LOST&
Arbitration lost as master and
addressed as slave
GCALL
General Call Address
Figure 15.14. Receiver Flowchart in Slave Mode
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Motor Pulse-Width-Modulator
16. Motor Pulse-Width-Modulator
Introduction
The Motor Pulse Width Modulator (MPWM) is a programmable motor controller which is optimized for 3-phase
inverter control applications. It can be used in several other applications that require timing, counting, and
comparison.
MPWM includes three channels, each of which controls a pair of outputs that in turn can control an AC or DC
motor through an inverter bridge. Features include:
6 channel outputs for motor control
Dead- time zone support
Protection event and over voltage event handling
6 trigger outputs for ADC
Interval interrupt mode
Up-down count mode
Over voltage
detection
Protection event
PWM CONTROL
POLVH
Dead
time
generator
POLVL
POLWH
Over Voltage control
POLUL
Protection control
Dead time
UH
Force Mode Control
Period
Duty UH
Duty UL
Duty VH
Duty VL
Duty WH
Duty WL
POLUH
POLWL
UL
VH
VL
WH
WL
APB I/F
Main Counter
ADC Trigger5
PWM port
Control
Port Hi-Z
control
Over voltage IRQ
ADC Trigger4
ADC Trigger3
Protection IRQ
ADC Trigger2
Interrupt
&
Status
PWM IRQ
ADC Trigger1
Trigger 0
Trigger 1
Trigger 2
Trigger 3
Trigger 4
Trigger 5
ADC Trigger0
Figure 16.1. Block Diagram
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Pin Description
Table16.1. External Signals
PIN NAME
TYPE
MP0UH
O
MPWM 0 Phase-U H-side output
DESCRIPTION
MP0UL
O
MPWM 0 Phase-ULH-side output
MP0VH
O
MPWM 0 Phase-V H-side output
MP0VL
O
MPWM 0 Phase-V L-side output
MP0WH
O
MPWM 0 Phase-W L-side output
MP0WL
O
MPWM 0 Phase-W L-side output
MP1UH
O
MPWM 1 Phase-U H-side output
MP1UL
O
MPWM 1 Phase-U L-side output
MP1VH
O
MPWM 1 Phase-V H-side output
MP1VL
O
MPWM 1 Phase-V L-side output
MP1WH
O
MPWM 1 Phase-W L-side output
MP1WL
O
MPWM 1 Phase-W L-side output
PRTIN0
I
MPWM 0 Protection Input
OVIN0
I
MPWM 0 Over-voltage Input
PRTIN1
I
MPWM 1 Protection Input
OVIN1
I
MPWM 1 Over-voltage Input
Registers
The base address of MPWM is Table 16.2.
Table16.2. MPWM Base Address
BASE ADDRESS
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0x4000_4000
MPWM0
0x4000_5000
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Table 16.3 shows the register memory map.
Table16.3. MPWM Register Map
Name
Offset
R/W
MPn.MR
0x0000
R/W
PWM Mode register
Description
0x0000_0000
Reset
MPn.OLR
0x0004
R/W
PWM Output Level register
0x0000_0000
MPn.FOR
0x0008
R/W
PWM Force Output register
0x0000_0000
MPn.PRD
0x000C
R/W
PWM Period register
0x0000_0002
MPn.DUH
0x0010
R/W
PWM Duty UH register
0x0000_0001
MPn.DVH
0x0014
R/W
PWM Duty VH register
0x0000_0001
MPn.DWH
0x0018
R/W
PWM Duty WH register
0x0000_0001
MPn.DUL
0x001C
R/W
PWM Duty UL register
0x0000_0001
MPn.DVL
0x0020
R/W
PWM Duty VL register
0x0000_0001
MPn.DWL
0x0024
R/W
PWM Duty WL register
0x0000_0001
MPn.CR1
0x0028
R/W
PWM Control register 1
0x0000_0000
MPn.CR2
0x002C
R/W
PWM Control register 2
0x0000_0000
MPn.SR
0x0030
R
PWM Status register
0x0000_0000
MPn.IER
0x0034
R/W
PWM Interrupt Enable
0x0000_0000
MPn.CNT
0x0038
R
PWM counter register
0x0000_0001
MPn.DTR
0x003C
R/W
PWM dead time control
0x0000_0000
MPn.PCR0
0x0040
R/W
PWM protection 0 control register
0x0000_0000
MPn.PSR0
0x0044
R/W
PWM protection 0 status register
0x0000_0080
MPn.PCR1
0x0048
R/W
PWM protection 1 control register
0x0000_0000
MPn.PSR1
0x004C
R/W
PWM protection 1 status register
0x0000_0000
-
0x0054
-
MPn.ATR1
0x0058
R/W
PWM ADC Trigger reg1
0x0000_0000
MPn.ATR2
0x005C
R/W
PWM ADC Trigger reg2
0x0000_0000
MPn.ATR3
0x0060
R/W
PWM ADC Trigger reg3
0x0000_0000
MPn.ATR4
0x0064
R/W
PWM ADC Trigger reg4
0x0000_0000
MPn.ATR5
0x0068
R/W
PWM ADC Trigger reg5
0x0000_0000
MPn.ATR6
0x006C
R/W
PWM ADC Trigger reg6
0x0000_0000
PS034603-0617
Reserved
PRELIMINARY
-
170
Z32F3841 Product Specification
MPn.MR
Motor Pulse-Width-Modulator
MPWM Mode Register
The PWM operation Mode register is a 16-bit register.
MP0.MR=0x4000_4000, MP1.MR=0x4000_5000
10
9
8
UAO
7
0
R/W
R/W
15
MOTORB
7
UAO
5
TUP
4
BUP
2
1
MCHMOD
0
1
0
1
0
1
0
1
00
01
10
0
UPDOWN
11
0
1
6
5
4
3
2
1
0
UPDOWN
11
MCHMOD
12
BUP
13
TUP
14
MOTORB
15
0
0
00
0
R/W
R/W
RW
R/W
Set PWM Mode
Motor Mode
Normal (PWM) mode
Update will be executed at designated timing.
Update all duty, period register at once.
When UPDATE set, Duty and Period registers are updated after
two PWM clocks
Period, duty values are not updated at every period match.
Period, duty values are updated at every period match.
Period, duty values are not updated at every bottom match
Period, duty values are updated at every bottom match
2 channels symmetric mode
Duty H decides toggle high/low time of H-ch
Duty L decides toggle high/low time of L-ch
1 channel asymmetric mode
Duty H decides toggle high time of H-ch
Duty L decides toggle low time of H-ch
L channel become the inversion of H channel
1 channel symmetric mode
Duty H decides toggle high/low time of H-ch
L channel become the inversion of H channel
Not valid (same with 00)
PWM Up count mode (only in Normal mode)
PWM Up/Down count mode
After initial PWM period and duty setting is completed, the UAO bit should be set once for updating the setting
value into the internal operating registers. This action will help to transfer the setting data from the user
interface register to the internal operating register. The UAO bit should stay at the set state for at least 2-PWM
clock periods. Otherwise, the update command can be missed and internal registers will retain the previous
data.
MCHMOD in the MPn.MR field is only effective when MOTORB in MPn.MR is clear “0”. Otherwise, the
MCHMOD field value will be ignored internally and will keep the “00” value.
UPDOWN in the MPn.MR field is only effective when MOTORB in MPn.MR is set to “1”. Otherwise, the
UPDOWN field value will be ignored internally and will keep the “1” value. In the motor mode, the counter is
always updown count operation.
PS034603-0617
PRELIMINARY
171
Z32F3841 Product Specification
Motor Pulse-Width-Modulator
pwmclk
counter
01
02
FE
FF
01
02
FE
FF
FE
01
00
01
02
FE
FF
01
02
TOP
BOTTOM
UPDOWN
UP_COUNT
UPDOWN = 0
UPDOWN = 1
set
UPDOWN_int
MPn.OLR
UPDOWN = 1
UPDOWN = 0
UPDOWN = 0
clear
UPDOWN_int
MPWM Output Level Register
PWM Port Mode register is a 16-bit register.
MP0.OLR=0x4000_4004, MP1.OLR=0x4000_5004
7
0
6
0
5
4
3
2
1
0
WHL
VHL
UHL
WLL
VLL
ULL
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
WHL
VHL
UHL
WLL
VLL
ULL
PS034603-0617
0
1
0
1
0
1
0
1
0
1
0
1
Normal Output = L / Active Output = H
Normal Output = H / Active Output = L
Normal Output = L / Active Output = H
Normal Output = H / Active Output = L
Normal Output = L / Active Output = H
Normal Output = H / Active Output = L
Normal Output = L / Active Output = H
Normal Output = H / Active Output = L
Normal Output = L / Active Output = H
Normal Output = H / Active Output = L
Normal Output = L / Active Output = H
Normal Output = H / Active Output = L
PRELIMINARY
172
Z32F3841 Product Specification
Motor Pulse-Width-Modulator
Table 16.1. MPWM Register Map
PWM Output
WH
WL
VH
VL
UH
UL
Level
NORMAL mode
MOTOR mode
UP mode
UPDOWN mode
Default level
LOW
HIGH
LOW
Active level
HIGH
LOW
HIGH
Default level
LOW
LOW
HIGH
Active level
HIGH
HIGH
LOW
Default level
LOW
HIGH
LOW
Active level
HIGH
LOW
HIGH
Default level
LOW
LOW
HIGH
Active level
HIGH
HIGH
LOW
Default level
LOW
HIGH
LOW
Active level
HIGH
LOW
HIGH
Default level
LOW
LOW
HIGH
Active level
HIGH
HIGH
LOW
Figure 16.2 shows the polarity control block. This is an example of WH signal polarity control.
Figure 16.2 Polarity Control Block
MPn.FOR
MPWM Force Output Level Register
The PWM force output register is an 8-bit register. The PWM output level can be forced by an abnormal event
from an external or user-intended condition. When the forced condition occurs, each PWM output level which
is programmed in the FOLR register will be forced.
MP0.FOR=0x4000_4008, MP1.FOR=0x4000_5008,
7
6
0
0
PS034603-0617
5
4
3
2
1
0
WHFL
VHFL
UHFL
WLFL
VLFL
ULFL
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
5
WHFL
4
VHFL
3
UHFL
Select WH Output Force Level
0
Output Force Level is ‘L’
1
Output Force Level is ‘H’
Select VH Output Force Level
0
Output Force Level is ‘L’
1
Output Force Level is ‘H’
Select UH Output Force Level
0
Output Force Level is ‘L’
PRELIMINARY
173
Z32F3841 Product Specification
MPn.CR1
2
WLFL
1
VLFL
0
ULFL
Motor Pulse-Width-Modulator
1
Output Force Level is ‘H’
Select WL Output Force Level
0
Output Force Level is ‘L’
1
Output Force Level is ‘H’
Select VL Output Force Level
0
Output Force Level is ‘L’
1
Output Force Level is ‘H’
Select UL Output Force Level
0
Output Force Level is ‘L’
1
Output Force Level is ‘H’
MPWM Control Register 1
PWM Control Register 1 is a 16-bit register.
MP0.CR1=0x4000_4028, MP1.CR1=0x4000_5028
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
PWMEN
14
IRQN
15
000
RW
10
8
0
MPn.CR2
RW
IRQN
IRQ interval number
(Every 1~8th PRDIRQ,BOTIRQ,ATRn)
PWM enable
When this bit is set to 0, the PWM block stays in the reset
state but the user interface can be accessed. To operate the
PWM block, this bit should be set to 1.
PWMEN
MPWM Control Register 2
PWM Control Register 2 is an 8-bit register.
MP0.CR2=0x4000_402C, MP1.CR2=0x4000_502C,
7
6
5
4
3
2
1
HALT
0
0
PSTART
0
0
0
0
0
0
RW
0
RW
7
HALT
0
PSTART
PWM HALT (PWM counter stop but not reset)
PWM outputs keep previous state
0
PWM counter stop and clear
1
PWM counter start (will be resynced @PWM clock
twice)
PWMEN should be “1” to start PWM counter
PS034603-0617
PRELIMINARY
174
Z32F3841 Product Specification
MPn.PRD
Motor Pulse-Width-Modulator
MPWM Period Register
PWM Period Register is a 16-bit register.
MP0.PRD=0x4000400C, MP1.PRD=0x40000500C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PERIOD
0x0002
R/W
15:0
MPn.DUH
PERIOD
16-bit PWM period. It should be larger than 0x0010
(if Duty is 0x0000, PWM will not work)
MPWM Duty UH Register
PWM U channel duty register is an 16-bit register.
MP0DUH=0x4000_4010, MP1DUH=0x4000_5010
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DUTY UH
0x0001
R/W
15:0
MPn.DVH
DUTY UH
16-bit PWM Duty for UH output.
It should be larger than 0x0001
(if Duty is 0x0000, PWM will not work)
MPWM Duty VH Register
PWM V channel duty register is a 16-bit register.
MP0.DVH=0x4000_4014, MP1DVH=0x4000_5014
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DUTY VH
0x0001
R/W
15:0
PS034603-0617
DUTY VH
16-bit PWM Duty for VH output.
It should be larger than 0x0001
(if Duty is 0x0000, PWM will not work)
PRELIMINARY
175
Z32F3841 Product Specification
MPn.DWH
Motor Pulse-Width-Modulator
MPWM Duty WH Register
PWM W channel duty register is a 16-bit register.
MP0.DWH=0x4000_4018, MP1.DWH=0x4000_5018
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DUTY WH
0x0001
R/W
15:0
MPn.DUL
DUTY WH
16-bit PWM Duty for WH output.
It should be larger than 0x0001
(if Duty is 0x0000, PWM will not work)
MPWM Duty UL Register
PWM U channel duty register is a 16-bit register.
MP0.DUL=0x4000_401C, MP1.DUL=0x4000_501C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DUTY UL
0x0001
R/W
15:0
MPn.DVL
DUTY UL
16-bit PWM Duty for UL output.
It should be larger than 0x0001
(if Duty is 0x0000, PWM will not work)
MPWM Duty VL Register
PWM V channel duty register is a 16-bit register.
MP0.DVL=0x4000_4020, MP1.DVL=0x4000_5020
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DUTY VL
0x0001
R/W
15:0
PS034603-0617
DUTY VL
16-bit PWM Duty for VL output.
It should be larger than 0x0001
(if Duty is 0x0000, PWM will not work)
PRELIMINARY
176
Z32F3841 Product Specification
MPn.DWL
Motor Pulse-Width-Modulator
MPWM Duty WL Register
PWM W channel duty register is a 16-bit register.
MP0.DWL=0x4000_4024, MP1.DWL=0x4000_5024
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DUTY WL
0x0001
R/W
15:0
MPn.IER
DUTY WL
16-bit PWM Duty for WL output.
It should be larger than 0x0001
(if Duty is 0x0000, PWM will not work)
MPWM Interrupt Enable Register
PWM Interrupt Enable Register is an 8-bit register.
MP0.IER=0x4000_4034, MP1.IER=0x4000_5034,
7
6
5
4
3
2
1
0
PRDIEN
BOTIEN
WHIE
VHIE
UHIE
WLIE
VLIE
ULIE
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
7
PRDIEN
6
BOTIEN
5
WHIE
ATR6IE
4
VHIE
ATR5IE
3
UHIE
ATR4IE
2
WLIE
ATR3IE
1
VLIE
ATR2IE
0
ULIE
ATR1IE
PWM Counter Period Interrupt enable
0
interrupt disable
1
interrupt enable
PWM Counter Bottom Interrupt enable
0
interrupt disable
1
interrupt enable
WH Duty or ATR6 Match Interrupt enable
0
interrupt disable
1
interrupt enable
VH Duty or ATR5 Match Interrupt enable
0
interrupt disable
1
interrupt enable
UH Duty or ATR4 Match Interrupt enable
0
interrupt disable
1
interrupt enable
WL Duty or ATR3 Match Interrupt enable
0
interrupt disable
1
interrupt enable
VL Duty or ATR2 Match Interrupt enable
0
interrupt disable
1
interrupt enable
UL Duty or ATR1 Match Interrupt enable
0
interrupt disable
1
interrupt enable
MPn.IER[5:0] control bits are shared by the duty match interrupt event and ADC trigger match interrupt event.
When ADC trigger mode is disabled, the interrupt is generated by the duty match condition; else the interrupt
is generated by the ADC trigger counter match condition. The ADC trigger mode is selected by the ATMOD bit
field in the ATRm register.
PS034603-0617
PRELIMINARY
177
Z32F3841 Product Specification
MPn.SR
Motor Pulse-Width-Modulator
MPWM Status Register
PWM Status Register is a 16-bit register.
10
9
8
7
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DOWN
14
12
7
IRQCNT[2:0]
0
1
PRDIF
0
1
6
BOTIF
0
1
5
DWHIF
ATR6F
0
1
4
DVHIF
ATR5F
0
1
3
DUHIF
ATR4F
0
1
2
DWLIF
ATR3F
0
1
1
DVLIF
ATR2F
0
1
0
DULIF
ATR1F
0
1
PS034603-0617
1
0
DULIF
ATR1F
11
15
2
DVLIF
ATR2F
R/W
3
DWLIF
ATR3F
R/W
4
DUHIF
ATR4F
000
5
DVHIF
ATR5F
0
6
DWHIF
ATR6F
12
BOTIF
13
IRQCNT
DOWN
14
PRDIF
MP0.SR=0x4000_4030, MP1.SR=0x4000_5030
15
0
0
0
0
0
0
0
0
PWM Count Up
PWM Count Down
Interrupt count number of period match
(Interval PRDIRQ mode)
PWM Period Interrupt flag(write “1” to clear flag)
No interrupt occurred
Interrupt occurred
PWM Bottom Interrupt flag(write “1” to clear flag)
No interrupt occurred
Interrupt occurred
PWM duty WH interrupt flag(write “1” to clear flag)
(Duty interrupt is enabled if ATR6 was disabled)
No interrupt occurred
Interrupt occurred
PWM duty VH interrupt flag(write “1” to clear flag)
(Duty interrupt is enabled if ATR5 was disabled)
No interrupt occurred
Interrupt occurred
PWM duty UH interrupt flag(write “1” to clear flag)
(Duty interrupt is enabled if ATR4 was disabled)
No interrupt occurred
Interrupt occurred
PWM duty WL interrupt flag(write “1” to clear flag)
(Duty interrupt is enabled if ATR3 was disabled)
No interrupt occurred
Interrupt occurred
PWM duty VL interrupt flag(write “1” to clear flag)
(Duty interrupt is enabled if ATR2 was disabled)
No interrupt occurred
Interrupt occurred
PWM duty UL interrupt flag(write “1” to clear flag)
(Duty interrupt is enabled if ATR1 was disabled)
No interrupt occurred
Interrupt occurred
PRELIMINARY
178
Z32F3841 Product Specification
MPn.CNT
Motor Pulse-Width-Modulator
MPWM Counter Register
PWM Counter Register is a 16-bit Read-Only register.
MP0.CNT=0x4000_4038, MP1.CNT=0x4000_5038
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MPnCNT
0x0000
R/W
MPnCNT
MPn.DTR
PWM Counter Value
MPWM Dead Time Register
PWM Dead Time Register is a 16-bit register.
PSHRT
0
0
13
12
11
10
9
8
DT
DTEN
14
DTCLK
MP0.DTR=0x4000_403C, MP1.DTR=0x4000_503C
15
0
0
0
0
0
0
0x00
RW
RW
RW
DTEN
PSHRT
DTCLK
DT[7:0]
7
6
5
4
3
2
1
0
Dead-time function enable
0
Disable Dead-time function
1
Enable Dead-time function
Protect short condition
0
Protection disable
1
When H-side and L-side are active, disable both side
Dead-time prescaler
0
Dead time counter uses PWM CLK/4
1
Dead time counter uses PWM CLK/16
Dead Time value (Dead time setting makes output delay of
‘low to high transition’ in normal polarity)
0x01 ~0xFF : Dead time
Note: Protect short condtion is for only internal PWM level and not for external PWM level. When the internal
signal of H-side and L-side are the same high level, the protection short function works to force both H-side
and L-side to low level.
PS034603-0617
PRELIMINARY
179
Z32F3841 Product Specification
MPn.PCR0/1
Motor Pulse-Width-Modulator
MPWM Protection 0/1 Control Register
PWM Protection Control Register is a 16-bit register.
MP0.PCR=0x4000_4040, MP1.PCR=0x4000_5040
5
4
3
2
1
0
UPROTM
6
VPROTM
7
WLPROTM
8
UHPROTM
9
VHPROTM
10
WHPROTM
11
PROTIE
12
PROTD
13
PROTPOL
14
PROTEN
15
0
0
000
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PS034603-0617
15
14
PROT0EN
PROT0POL
10
8
PROTD
7
PROTIE
5
WHPROTM
4
VHPROTM
3
UHPROTM
2
WLPROTM
1
VLPROTM
0
ULPROTM
Enable Protection Input 0
Select Protection Input Polarity
0: Low-Active
1: High-Active
Protection Input debounce
0 – no debounce
1~7 – debounce by (MPWMCLK * PROTD[2:0])
Protection Interrupt enable
0
Disable protection interrupt
1
Enable protection interrupt
Activate W-phase H-side protection output
0
Disable Protection Output
1
Enable Protection Output with FOR value
Activate V-phase H-side protection output
0
Disable Protection Output
1
Enable Protection Output with FOR value
Activate U-phase H-side protection output
0
Disable Protection Output
1
Enable Protection Output with FOR value
Activate W-phase L-side protection output
0
Disable Protection Output
1
Enable Protection Output with FOR value
Activate V-phase L-side protection output
0
Disable Protection Output
1
Enable Protection Output with FOR value
Activate U-phase L-side protection output
0
Disable Protection Output
1
Enable Protection Output with FOR value
PRELIMINARY
180
Z32F3841 Product Specification
MPn.PSR0/1
Motor Pulse-Width-Modulator
MPWM Protection 0/1 Status Register
PWM Protection Status Register is a 16-bit register. This register indicates which outputs are disabled and
users can set the output masks manually. Without writing PROTKEY when writing any value, the written
values are ignored.
MP0.PSR=0x4000_4044, MP1.PSR=0x4000_5044
8
7
6
5
4
3
2
1
0
UPROTF
9
VPROTF
10
WLPROTF
11
UHPROTF
12
VHPROTF
13
WHPROTF
14
PROTIF
15
-
0
0
0
0
0
0
0
WO
RC
RW
RW
RW
RW
RW
RW
PROTKEY
15
8
PROTKEY
7
PROTIF
5
WHPROT
4
VHPROT
3
UHPROT
2
WLPROT
1
VLPROT
0
ULPROT
Protection Clear Access Key
To clear flags, write 0xCA with protection flag
(PSR0 key is 0xCA and PSR1 key is 0xAC)
Writing without PROTKEY prohibited.
Protection Interrupt status
0
No Protection Interrupt
1
Protection Interrupt occurred
Activate W-phase H-side protection flag
0
Protection not occurred.
1
Protection occurred or protection output enabled
Activate V-phase H-side protection flag
0
Protection not occurred.
1
Protection occurred or protection output enabled
Activate U-phase H-side protection flag
0
Protection not occurred.
1
Protection occurred or protection output enabled
Activate W-phase L-side protection flag
0
Protection not occurred.
1
Protection occurred or protection output enabled
Activate V-phase L-side protection flag
0
Protection not occurred.
1
Protection occurred or protection output enabled
Activate U-phase L-side protection flag
0
Protection not occurred.
1
Protection occurred or protection output enabled
Note: MPn.PCR0 is related to the PRTINn pin and MPn.PCR1 is related to OVINn.
PS034603-0617
PRELIMINARY
181
Z32F3841 Product Specification
MPn.ATRm
Motor Pulse-Width-Modulator
MPWMn ADC Trigger Counter m Register
MPn.ATR1
MPn.ATR2
MPn.ATR3
MPn.ATR4
MPn.ATR5
MPn.ATR6
MPWM ADC Trigger Counter 1 Register
MPWM ADC Trigger Counter 2 Register
MPWM ADC Trigger Counter 3 Register
MPWM ADC Trigger Counter 4 Register
MPWM ADC Trigger Counter 5 Register
MPWM ADC Trigger Counter 6 Register
The PWM ADC Trigger Counter Register is a 32-bit register.
MP0.ATR1=0x4000_4058, MP1.ATR1=0x4000_5058
MP0.ATR2=0x4000_405C, MP1.ATR2=0x4000_505C
MP0.ATR3=0x4000_4060, MP1.ATR3=0x4000_5060
MP0.ATR4=0x4000_4064, MP1.ATR4=0x4000_5064
MP0.ATR5=0x4000_4068, MP1.ATR5=0x4000_5068
MP0.ATR6=0x4000_406C, MP1.ATR6=0x4000_506C
0
0
0
0
0
0
0
0
0
0
0
PS034603-0617
19
ATUDT
17
16
ATMOD
15
0
ATCNT
0
8
7
ATMOD
0
RW
0
9
ATCNT
0
0x0000
RW
ATUDT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
6
5
4
3
2
1
0
Trigger register update mode
0
ADC trigger value applied at period match event
(at the same time with period and duty registers update)
1
Trigger register update mode
When this bit set, written Trigger register values are sent to
trigger compare block after two PWM clocks (through
synchronization logic)
ADC trigger Mode register
00 ADC trigger Disable
01 Trigger out when up count match
10 Trigger out when down count match
00 Trigger out when up-down count match
ADC Trigger counter
(it should be less than PWM period)
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Functional Description
The PWMx module allows users to configure the PWM for different types of modulation schemes described in
the previous section. The PER2 and PCER2 registers must be configured to enable the PWMx peripheral and
the PWMx peripheral clock.
Setting or resetting the MOTOR bit in the MPnMR register allows users to operate the motor in Independent
or Complementary PWM modes. For more information about operating modes, refer to the diagrams in the
following section.
Figure 16.3 shows the diagram for generating a PWM output signal.
Figure 16.3 PWM Output Generation Chain
Normal PWM Up Count Mode Timing
In normal PWM mode, each channel runs independently. 6 PWM outputs can be generated. An example
waveform is shown in Figure 16.4. Before PSTART is activated, the PWM output stay at the default value L.
When PSTART is enabled, the period counter starts up count until the MP0.PRD count value. In the first
period, the MPWM does not generate a PWM pulse.
The PWM pulse is generated from the second period. The active level is derived at the start of the counter
value during duty value time.
MP.CNT
MP.PRD
MP.DU/V/WH
MP.DU/V/WL
Period =
MMMP0UH
MP0VH
MMP.DUH/V/W
MMP0UH
MP0VH
MMP.DUH/V/W
MP0WH
MP0UH
MP0VH
MP0WH
MP0UL
MP0VH
MP0WH
Figure 16.4. Up Count Mode Waveform (MOTORB=1, UPDOWN=0)
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Normal PWM Up/Down Count Mode Timing
The basic operation of the Up/Down count mode is the same as the Up count mode except that one up/down
period is twice as long as an UP count mode period. The default active level is opposite in a pair PWM output.
This output polarity can be controlled by the MP0.OLR register.
Figure 16.5. Up/Down Count Mode Waveform (MOTORB=0, MCHMOD=0, UPDOWN=1)
Motor PWM 2-Channel Symmetric Mode Timing
The motor PWM operation has three types of operating mode:
2-Channel symmetric mode
1-Channel symmetric mode
1-Channel asymmetric mode
Figure 16.6 shows a 2-channel symmetric mode waveform.
Figure 16.6. 2-Channel Symmetric Mode Wave Form (MOTORB=0,MCHMOD=00)
The default start level of both H-side and L-side is low. For the H-side, the PWM ouput level is changed to
active level when the duty level is matched in the up count period and is returned to the default level when the
duty level is matched in the down count period.
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The symmetrical feature appears in each channel which is controlled by the corresponding DUTY register
value.
Motor PWM 1-Channel Asymmetric Mode Timing
The 1 channel asymmetric mode generates asymmetric duration pulses which are defined by the H-side and
L-side DUTY register. Therefore, the L-side signal is always the negative signal of H-side. During the up count
period, the H-side DUTY register matching condition generates the active level pulse and during the down
count period, the L-side DUTY register matiching condition generates the default level pulse.
Figure 16.7. 1-Channel Asymmetric Mode Waveform (MOTORB=0,MCHMOD=01)
The default start level of both H-side and L-side is low. For the H-side, PWM ouput level is changed to active
level when the H-side duty level is matched in up count period and is returned to default level when the L-side
duty level is matched in down count period.
When the PSTART is set, the L-side PWM output is changed to the active level then the L-side PWM output is
inverse output of H-side output.
Motor PWM 1-Channel Symmetric Mode Timing
The 1-channel symmetric mode generates a symmetric duration pulse which is defined by the H-side DUTY
register. Therefore, the L-side signal is always the negative of the H-side signal. During up count period, the
H-side DUTY register matching condition creates the active level pulse and during down count period, the Hside DUTY register matiching condition also generates the default level pulse.
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Figure 16.8. 1-Channel Symmetric Mode Waveform (MOTORB=0,MCHMOD=10)
The default start level of both H-side and L-side is low. For the H-side, PWM ouput level is changed to active
level when the H-side duty level is matched in up count period and is returned to the default level when the Hside duty level is matched again in down count period.
When PSTART is set, the L-side PWM output is changed to the active level, then the L-side PWM output is
inverse output of H-side output.
PWM Dead-time Operation
To prevent external short conditions, the MPWM provides dead time functionality. This function is only
available for motor PWM mode. When one of H-sdie or L-side output changes to active level, the amount of
dead time is inserted if the DTEN.MP.DTR bit is enabled.
The duration of dead time is decided by the value in the DT.MP.DTR[7:0] field.
When DTCLK = 0, the dead time duration = DT[7:0] * (PWM clock period * 4)
When DTCLK = 1, the dead time duration = DT[7:0] * (PWM clock period * 16)
When the PWM counter reaches the duty value, the PWM output is masked and the dead time counter starts
to run. When the dead time counter reaches the value in the DT[7:0] register, the output mask is disabled.
Figure 16.9 is an example of dead time operation in 1-channel symmetric mode.
MP.CNT
MP.DUH/V/W
MP.DTR
MP0UH
MP0VH
MP0WH
MP.DTR
MP0UH
MP0VH
MP0WH
Figure 16.9. PWM Dead-time Operation Timing Diagram (Symmetric Mode)
Figure 16.10 is an example of dead time operation in 1-channel asymmetric mode
MP.CNT
MP.DUL/V/W
MP.DUH/V/W
MP.DTR
MP0UH
MP0VH
MP0WH
MP.DTR
MP0UH
MP0VH
MP0WH
Figure 16.10. PWM Dead-time Operation Timing Diagram (Asymmetric Mode)
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The dead time function is not available for 2-channel symmetric mode. Therefore, the dead condition is
generated by each channel’s duty control.
MPWM Dead-time Timing Examples
The following images show how the dead-time operates. In normal situations, the dead time masking is
activated at duty match time and the dead time counter runs. When the dead time counter reaches the dead
time value, the mask is disabled.
Figure 16.11. Normal Dead-time Operation (TDUTY>TDT)
The following figures show the dead time configuration in special situations.
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MP.CNT
2 x TDUTY
MP.PRD
MP.DUH/V/W
DT-Rising
Mask
DT-Falling
Mask
MASKED
MASKED
TDT-Risng
MP0UH
MP0VH
MP0WH
TDT-Falling
MP0UH
MP0VH
MP0WH
Figure 16.12. Minimum H-side Pulse Timing (TDUTY
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