Z51F3221ARX

Z8051 Series 8-Bit Microcontrollers Z51F3221 Product Specification PS030002-0212 PRELIMINARY Copyright ©2012 Zilog®, Inc. All rights reserved. www.zilog.com Z51F3221 Product Specification ii Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2012 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8051 is a trademark or registered trademark of Zilog, Inc. All other product or service names are the property of their respective owners. PS030002-0212 PRELIMINARY Z51F3221 Product Specification iii Revision History Each instance in this document’s revision history reflects a change from its previous edition. For more details, refer to the corresponding page(s) or appropriate links furnished in the table below. Revision Level Description Page Feb 2012 02 Removed references to 80-pin MQFP package. All Jan 2012 01 Original Zilog issue. All Date PS030002-0212 PRELIMINARY Revision History Z51F3221 Product Specification Table of Contents 1. Overview ................................................................................................................................................................. 9 1.1 Description ....................................................................................................................................................... 9 1.2 Features ......................................................................................................................................................... 10 1.3 Ordering Information ...................................................................................................................................... 11 1.4 Development Tools ........................................................................................................................................ 12 2. Block Diagram ...................................................................................................................................................... 14 3. Pin Assignment ..................................................................................................................................................... 15 4. Package Diagram ................................................................................................................................................. 17 5. Pin Description...................................................................................................................................................... 19 6. Port Structures ...................................................................................................................................................... 23 6.1 General Purpose I/O Port .............................................................................................................................. 23 6.2 External Interrupt I/O Port .............................................................................................................................. 24 7. Electrical Characteristics ...................................................................................................................................... 25 7.1 Absolute Maximum Ratings ........................................................................................................................... 25 7.2 Recommended Operating Conditions ........................................................................................................... 25 7.3 A/D Converter Characteristics ....................................................................................................................... 26 7.4 Power-On Reset Characteristics ................................................................................................................... 26 7.5 Low Voltage Reset and Low Voltage Indicator Characteristics .................................................................... 27 7.6 Internal RC Oscillator Characteristics ........................................................................................................... 28 7.7 Internal Watch-Dog Timer RC Oscillator Characteristics .............................................................................. 28 7.8 DC Characteristics ......................................................................................................................................... 29 7.9 Serial I/O Characteristics ............................................................................................................................... 31 7.10 UART Characteristics .................................................................................................................................. 32 7.11 Data Retention Voltage in Stop Mode ......................................................................................................... 34 7.12 Internal Flash Rom Characteristics ............................................................................................................. 35 7.13 Input/Output Capacitance ............................................................................................................................ 35 7.14 Main Clock Oscillator Characteristics .......................................................................................................... 36 7.15 Sub Clock Oscillator Characteristics ........................................................................................................... 37 7.16 Main Oscillation Stabilization Characteristics ............................................................................................. 38 7.17 Sub Oscillation Characteristics .................................................................................................................... 38 7.18 Operating Voltage Range ............................................................................................................................ 39 7.19 Recommended Circuit and Layout .............................................................................................................. 40 7.20 Typical Characteristics ................................................................................................................................ 41 8. Memory ................................................................................................................................................................. 44 8.1 Program Memory ........................................................................................................................................... 44 8.2 Data Memory ................................................................................................................................................. 46 8.3 XRAM Memory .............................................................................................................................................. 48 8.4 SFR Map ........................................................................................................................................................ 49 9. I/O Ports ................................................................................................................................................................ 56 9.1 I/O Ports ......................................................................................................................................................... 56 9.2 Port Register .................................................................................................................................................. 56 9.3 P0 Port ........................................................................................................................................................... 60 9.4 P1 Port ........................................................................................................................................................... 62 9.5 P2 Port ........................................................................................................................................................... 64 9.6 P3 Port ........................................................................................................................................................... 65 9.7 P4 Port ........................................................................................................................................................... 66 9.8 P5 Port ........................................................................................................................................................... 67 9.9 P6 Port ........................................................................................................................................................... 68 PS030002-0212 PRELIMINARY 1 Z51F3221 Product Specification 9.10 P7 Port ......................................................................................................................................................... 69 9.11 P8 Port ......................................................................................................................................................... 70 9.12 P9 Port ......................................................................................................................................................... 71 9.13 Port Function ............................................................................................................................................... 72 10. Interrupt Controller .............................................................................................................................................. 81 10.1 Overview ...................................................................................................................................................... 81 10.2 External Interrupt ......................................................................................................................................... 82 10.3 Block Diagram ............................................................................................................................................. 83 10.4 Interrupt Vector Table .................................................................................................................................. 84 10.5 Interrupt Sequence ...................................................................................................................................... 84 10.6 Effective Timing after Controlling Interrupt Bit ............................................................................................ 86 10.7 Multi Interrupt ............................................................................................................................................... 87 10.8 Interrupt Enable Accept Timing ................................................................................................................... 88 10.9 Interrupt Service Routine Address .............................................................................................................. 88 10.10 Saving/Restore General-Purpose Registers ............................................................................................. 88 10.11 Interrupt Timing.......................................................................................................................................... 89 10.12 Interrupt Register Overview ....................................................................................................................... 89 10.13 Interrupt Register Description .................................................................................................................... 91 11. Peripheral Hardware ........................................................................................................................................... 97 11.1 Clock Generator........................................................................................................................................... 97 11.2 Basic Interval Timer ................................................................................................................................... 100 11.3 Watch Dog Timer ....................................................................................................................................... 102 11.4 Watch Timer............................................................................................................................................... 105 11.5 Timer 0 ....................................................................................................................................................... 108 11.6 Timer 1 ....................................................................................................................................................... 118 11.7 Timer 2 ....................................................................................................................................................... 127 11.8 Timer 3 ....................................................................................................................................................... 130 11.9 Buzzer Driver ............................................................................................................................................. 138 11.10 SIO ........................................................................................................................................................... 140 11.11 12-Bit A/D Converter ............................................................................................................................... 145 11.12 UART ....................................................................................................................................................... 150 11.13 LCD Driver ............................................................................................................................................... 165 12. Power Down Operation .................................................................................................................................... 175 12.1 Overview .................................................................................................................................................... 175 12.2 Peripheral Operation in IDLE/STOP Mode ............................................................................................... 175 12.3 IDLE Mode ................................................................................................................................................. 176 12.4 STOP Mode ............................................................................................................................................... 177 12.5 Release Operation of STOP Mode............................................................................................................ 178 13. RESET .............................................................................................................................................................. 180 13.1 Overview .................................................................................................................................................... 180 13.2 Reset Source ............................................................................................................................................. 180 13.3 RESET Block Diagram .............................................................................................................................. 180 13.4 RESET Noise Canceller ............................................................................................................................ 180 13.5 Power On RESET ...................................................................................................................................... 181 13.6 External RESETB Input ............................................................................................................................. 184 13.7 Brown Out Detector Processor .................................................................................................................. 185 13.8 LVI Block Diagram ..................................................................................................................................... 186 14. On-chip Debug System .................................................................................................................................... 190 14.1 Overview .................................................................................................................................................... 190 14.2 Two-Pin External Interface ........................................................................................................................ 191 15. Flash Memory ................................................................................................................................................... 196 15.1 Overview .................................................................................................................................................... 196 16. Configure Option .............................................................................................................................................. 207 PS030002-0212 PRELIMINARY 2 Z51F3221 Product Specification 16.1 Configure Option Control ........................................................................................................................... 207 17. APPENDIX ........................................................................................................................................................ 208 PS030002-0212 PRELIMINARY 3 Z51F3221 Product Specification List of Figures Figure 1.1 StandAlone Gang8 (for Mass Production) ............................................................................... 13 Figure 2.1 Block Diagram .......................................................................................................................... 14 Figure 3.1 Z51F3221 80LQFP-1212 Pin Assignment ............................................................................... 15 Figure 3.2 Z51F3221 64LQFP-1010 Pin Assignment ............................................................................... 16 Figure 4.1 80-Pin LQFP Package .............................................................................................................. 17 Figure 4.2 64-Pin LQFP Package .............................................................................................................. 18 Figure 6.1 General Purpose I/O Port ......................................................................................................... 23 Figure 6.2 External Interrupt I/O Port ........................................................................................................ 24 Figure 7.1 Input Timing for External Interrupts .......................................................................................... 31 Figure 7.2 Input Timing for RESETB ......................................................................................................... 31 Figure 7.3 Serial Interface Data Transfer Timing ...................................................................................... 32 Figure 7.4 Waveform for UART Timing Characteristics ............................................................................ 33 Figure 7.5 Timing Waveform for the UART Module .................................................................................. 33 Figure 7.6 Stop Mode Release Timing when Initiated by an Interrupt ...................................................... 34 Figure 7.7 Stop Mode Release Timing when Initiated by RESETB .......................................................... 34 Figure 7.8 Crystal/Ceramic Oscillator ........................................................................................................ 36 Figure 7.9 External Clock........................................................................................................................... 36 Figure 7.10 Crystal Oscillator .................................................................................................................... 37 Figure 7.11 External Clock......................................................................................................................... 37 Figure 7.12 Clock Timing Measurement at XIN ........................................................................................ 38 Figure 7.13 Clock Timing Measurement at SXIN ...................................................................................... 38 Figure 7.14 Operating Voltage Range ....................................................................................................... 39 Figure 7.15 Recommended Circuit and Layout ......................................................................................... 40 Figure 7.16 RUN (IDD1 ) Current .............................................................................................................. 41 Figure 7.17 IDLE (IDD2) Current ............................................................................................................... 41 Figure 7.18 SUB RUN (IDD3) Current....................................................................................................... 42 Figure 7.19 SUB IDLE (IDD4) Current ...................................................................................................... 42 Figure 7.20 STOP (IDD5) Current ............................................................................................................. 43 Figure 8.1 Program Memory ...................................................................................................................... 45 Figure 8.2 Data Memory Map .................................................................................................................... 46 Figure 8.3 Lower 128 Bytes RAM .............................................................................................................. 47 Figure 8.4 XDATA Memory Area ............................................................................................................... 48 Figure 10.1 External Interrupt Description ................................................................................................. 82 Figure 10.2 Block Diagram of Interrupt...................................................................................................... 83 Figure 10.3 Interrupt Vector Address Table .............................................................................................. 85 Figure 10.4 Effective Timing of Interrupt Enable Register ....................................................................... 86 Figure 10.5 Effective Timing of Interrupt Flag Register............................................................................. 86 Figure 10.6 Effective Timing of Interrupt ................................................................................................... 87 Figure 10.7 Interrupt Response Timing Diagram ...................................................................................... 88 Figure 10.8 Correspondence between Vector Table Address and the Entry Address of ISP .................. 88 Figure 10.9 Saving/Restore Process Diagram and Sample Source ......................................................... 88 Figure 10.10 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction ............................... 89 Figure 11.1 Clock Generator Block Diagram ............................................................................................. 97 Figure 11.2 Basic Interval Timer Block Diagram ..................................................................................... 100 Figure 11.3 Watch Dog Timer Interrupt Timing Waveform ..................................................................... 102 PS030002-0212 PRELIMINARY 4 Z51F3221 Product Specification Figure 11.4 Watch Dog Timer Block Diagram ......................................................................................... 103 Figure 11.5 Watch Timer Block Diagram................................................................................................. 105 Figure 11.6 8-Bit Timer/Counter Mode for Timer 0 ................................................................................. 109 Figure 11.7 8-Bit Timer/Counter 0 Example ............................................................................................ 110 Figure 11.8 8-Bit PWM Mode for Timer 0 ................................................................................................ 111 Figure 11.9 PWM Output Waveforms in PWM Mode for Timer 0 ........................................................... 112 Figure 11.10 8-Bit Capture Mode for Timer 0 .......................................................................................... 113 Figure 11.11 Input Capture Mode Operation for Timer 0 ........................................................................ 114 Figure 11.12 Express Timer Overflow in Capture Mode ......................................................................... 114 Figure 11.13 8-Bit Timer 0 Block Diagram .............................................................................................. 115 Figure 11.14 8-Bit Timer/Counter Mode for Timer 1 ............................................................................... 119 Figure 11.15 8-Bit Timer/Counter 1 Example .......................................................................................... 120 Figure 11.16 8-Bit Timer/Counter 1 Counter Operation .......................................................................... 120 Figure 11.17 Carrier Mode for Timer 1 .................................................................................................... 121 Figure 11.18 Carrier Output Waveforms in Repeat Mode for Timer 1 .................................................... 123 Figure 11.19 8-Bit Timer 1 Block Diagram .............................................................................................. 124 Figure 11.20 16-Bit Timer/Counter Mode for Timer 2 and Block Diagram ............................................. 127 Figure 11.21 16-Bit Timer/Counter Mode for Timer 3 ............................................................................. 131 Figure 11.22 16-Bit PWM Mode for Timer 3 ............................................................................................ 132 Figure 11.23 16-Bit Capture Mode for Timer 3........................................................................................ 133 Figure 11.24 16-Bit Timer 3 Block Diagram ............................................................................................ 134 Figure 11.25 Buzzer Driver Block Diagram ............................................................................................. 138 Figure 11.26 SIO Block Diagram ............................................................................................................. 140 Figure 11.27 SIO Pre-Scaler Register (SIOPS) ...................................................................................... 141 Figure 11.28 SIO Timing Diagram at SEDGE=0 ..................................................................................... 142 Figure 11.29 SIO Timing Diagram at SEDGE=1 ..................................................................................... 142 Figure 11.30 12-bit ADC Block Diagram ................................................................................................. 145 Figure 11.31 A/D Analog Input Pin with Capacitor .................................................................................. 146 Figure 11.32 A/D Power (AVDD) Pin with Capacitor .............................................................................. 146 Figure 11.33 ADC Operation for Align Bit................................................................................................ 146 Figure 11.34 A/D Converter Operation Flow ........................................................................................... 147 Figure 11.35 UART Block Diagram ......................................................................................................... 151 Figure 11.36 Clock Generation Block Diagram ....................................................................................... 152 Figure 11.37 Synchronous Mode ACK Timing ........................................................................................ 153 Figure 11.38 Frame Format ..................................................................................................................... 154 Figure 11.39 Start Bit Sampling ............................................................................................................... 158 Figure 11.40 Sampling of Data and Parity Bit ......................................................................................... 158 Figure 11.41 Stop Bit Sampling and Next Start Bit Sampling ................................................................. 159 Figure 11.42 LCD Circuit Block Diagram................................................................................................. 166 Figure 11.43 LCD Signal Waveforms (1/2Duty, 1/2Bias) ........................................................................ 167 Figure 11.44 LCD Signal Waveforms (1/3Duty, 1/3Bias) ........................................................................ 168 Figure 11.45 LCD Signal Waveforms (1/4Duty, 1/3Bias) ........................................................................ 169 Figure 11.46 LCD Signal Waveforms (1/8Duty, 1/4Bias) ........................................................................ 170 Figure 11.47 Internal Resistor Bias Connection ...................................................................................... 171 Figure 11.48 External Resistor Bias Connection..................................................................................... 171 Figure 11.49 LCD Circuit Block Diagram................................................................................................. 172 Figure 12.1 IDLE Mode Release Timing by External Interrupt ............................................................... 176 Figure 12.2 STOP Mode Release Timing by External Interrupt.............................................................. 177 Figure 12.3 STOP Mode Release Flow ................................................................................................... 178 PS030002-0212 PRELIMINARY 5 Z51F3221 Product Specification Figure 13.1 RESET Block Diagram ......................................................................................................... 180 Figure 13.2 Reset noise canceller timer diagram .................................................................................... 181 Figure 13.3 Fast VDD Rising Time .......................................................................................................... 181 Figure 13.4 Internal RESET Release Timing On Power-Up ................................................................... 181 Figure 13.5 Configuration Timing when Power-on .................................................................................. 182 Figure 13.6 Boot Process WaveForm ..................................................................................................... 182 Figure 13.7 Timing Diagram after RESET ............................................................................................... 184 Figure 13.8 Oscillator generating waveform example ............................................................................. 184 Figure 13.9 Block Diagram of BOD ......................................................................................................... 185 Figure 13.10 Internal Reset at the power fail situation ............................................................................ 185 Figure 13.11 Configuration timing when BOD RESET............................................................................ 186 Figure 13.12 LVI Diagram ........................................................................................................................ 186 Figure 14.1 Block Diagram of On-Chip Debug System........................................................................... 191 Figure 14.2 10-bit Transmission Packet .................................................................................................. 192 Figure 14.3 Data Transfer on the Twin Bus ............................................................................................ 192 Figure 14.4 Bit Transfer on the Serial Bus .............................................................................................. 192 Figure 14.5 Start and Stop Condition ...................................................................................................... 193 Figure 14.6 Acknowledge on the Serial Bus ........................................................................................... 193 Figure 14.7 Clock Synchronization during Wait Procedure .................................................................... 194 Figure 14.8 Connection of Transmission ................................................................................................. 195 Figure 15.1 Flash Program ROM Structure ............................................................................................. 197 PS030002-0212 PRELIMINARY 6 Z51F3221 Product Specification List of Tables Table 1-1 Ordering Information for the Z51F3221 MCU ........................................................................... 11 Table 5-1 Normal pin description ............................................................................................................... 19 Table 7-1 Absolute Maximum Ratings....................................................................................................... 25 Table 7-2 Recommended Operating Conditions ....................................................................................... 25 Table 7-3 A/D Converter Characteristics ................................................................................................... 26 Table 7-4 Power-On Reset Characteristics ............................................................................................... 26 Table 7-5 LVR and LVI Characteristics ..................................................................................................... 27 Table 7-6 Internal RC Oscillator Characteristics ....................................................................................... 28 Table 7-7 Internal WDTRC Oscillator Characteristics ............................................................................... 28 Table 7-8 DC Characteristics ..................................................................................................................... 29 Table 7-9 Serial I/O Characteristics ........................................................................................................... 31 Table 7-10 UART Characteristics .............................................................................................................. 32 Table 7-11 Data Retention Voltage in Stop ModeR .................................................................................. 34 Table 7-12 Internal Flash Rom Characteristics ......................................................................................... 35 Table 7-13 Input/Output Capacitance ........................................................................................................ 35 Table 7-14 Main Clock Oscillator Characteristics...................................................................................... 36 Table 7-15 Sub Clock Oscillator Characteristics ....................................................................................... 37 Table 7-16 Main Oscillation Stabilization Characteristics ......................................................................... 38 Table 7-17 Sub Oscillation Stabilization Characteristics ........................................................................... 38 Table 8-1 SFR Map Summary ................................................................................................................... 49 Table 8-2 SFR Map .................................................................................................................................... 50 Table 9-1 Port Register Map ...................................................................................................................... 58 Table 10-1 Interrupt Group Priority Level .................................................................................................. 81 Table 10-2 Interrupt Vector Address Table ............................................................................................... 84 Table 10-3 Interrupt Register Map ............................................................................................................. 91 Table 11-1 Clock Generator Register Map ................................................................................................ 97 Table 11-2 Basic Interval Timer Register Map ........................................................................................ 101 Table 11-3 Watch Dog Timer Register Map ............................................................................................ 103 Table 11-4 Watch Timer Register Map .................................................................................................... 106 Table 11-5 Timer 0 Operating Modes ...................................................................................................... 108 Table 11-6 Timer 0 Register Map ............................................................................................................ 116 Table 11-7 Timer 1 Operating Modes ...................................................................................................... 118 Table 11-8 Timer 1 Register Map ............................................................................................................ 124 Table 11-9 Timer 2 Register Map ............................................................................................................ 127 Table 11-10 Timer 3 Operating Modes .................................................................................................... 130 Table 11-11 Timer 3 Register Map .......................................................................................................... 134 Table 11-12 Buzzer Frequency at 8 MHz ................................................................................................ 138 Table 11-13 Buzzer Driver Register Map ................................................................................................ 139 Table 11-14 SIO Register Map ................................................................................................................ 143 Table 11-15 ADC Register Map............................................................................................................... 147 Table 11-16 Equations for Calculating Baud Rate Register Setting ....................................................... 152 Table 11-17 UART Register Map ............................................................................................................ 159 Table 11-18 Examples of UARTBD Settings for Commonly Used Oscillator Frequencies .................... 164 Table 11-19 LCD Register Map ............................................................................................................... 172 PS030002-0212 PRELIMINARY 7 Z51F3221 Product Specification Table 12-1 Peripheral Operation during Power Down Mode .................................................................. 175 Table 12-2 Power Down Operation Register Map ................................................................................. 179 Table 13-1 Reset State ............................................................................................................................ 180 Table 13-2 Boot Process Description ...................................................................................................... 183 Table 13-3 Reset Operation Register Map .............................................................................................. 187 Table 15-1Flash Memory Register Map .................................................................................................. 198 PS030002-0212 PRELIMINARY 8 Z51F3221 Product Specification Z51F3221 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 12-BIT A/D CONVERTER 1. Overview 1.1 Description The Z51F3221 MCU is advanced CMOS 8-bit microcontroller with 32k bytes of Flash. This is powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. This provides the following features : 32k bytes of Flash, 256 bytes of IRAM, 1k bytes of XRAM , general purpose I/O, basic interval timer, watchdog timer, 8/16-bit timer/counter, carrier generation, 8/16-bit PWM output, watch timer, buzzer driving port, SIO, UART, 12-bit A/D converter, LCD driver, on-chip POR, LVR, LVI, on-chip oscillator and clock circuitry. The Z51F3221 MCU also supports power saving modes to reduce power consumption. Device Name Flash XRAM IRAM Z51F3221 32KB 1KB 256 bytes PS030002-0212 ADC I/O PORT Package 8 channel 70 80-pin LQFP 5 channel 54 64-pin LQFP PRELIMINARY 9 Z51F3221 Product Specification 1.2 Features • CPU - Reset release level (1.4V) • Low Voltage Reset - 8 Bit CISC Core (8051 Compatible) • ROM (Flash) Capacity - 14 level detect (1.60V/ 2.00V/ 2.10V/ 2.20V/ 2.32V/ 2.44V/ 2.59V/ 2.75V/ 2.93V/ 3.14V/ 3.38V/ 3.67V/ 4.00V/ 4.40V) - 32k Bytes - Flash with self read/write capability - On chip debug and In-system programming (ISP) • Low Voltage Indicator • 256 Bytes IRAM - 13 level detect (2.00V/ 2.10V/ 2.20V/ 2.32V/ 2.44V/ 2.59V/ 2.75V/ 2.93V/ 3.14V/ 3.38V/ 3.67V/ 4.00V/ 4.40V) • 1k Bytes XRAM - External reference detect - Endurance : 100,000 times • Interrupt Sources - (40 Bytes including LCD display RAM) - External Interrupts • General Purpose I/O (GPIO) (EXINT0~7, EINT10, EINT13) (10) - Normal I/O : 24 Ports - Timer( 0/1/2/3) (6) (P0, P1[6:0], P2, P92) - WDT (1) - LCD shared I/O : 46 Ports - BIT (1) (P3[6:1], P4, P5, P6, P7, P8) - WT (1) • Basic Interval Timer (BIT) - 8Bit × 1ch - SIO (1) - Watch Dog Timer (WDT) - UART(TX/RX) (2) - ADC (1) - 8Bit × 1ch • Internal RC Oscillator - 6kHz internal RC oscillator - Internal RC frequency: 8MHz ± 10% (TA= -40°C ~ +85°C) • Timer/ Counter - 8Bit × 2ch (T0/T1), 16Bit x 2ch (T2/T3) • Power Down Mode • Carrier Generation - Carrier Generation (by T1), T2 Clock source • Operating Voltage and Frequency • PWM - 1.8V ~ 5.5V (@1.0 ~ 4.2MHz) - 8Bit × 1ch (by T0), 16Bit × 1ch (by T3) - 2.7V ~ 5.5V (@1.0 ~ 10.0MHz) • Watch Timer (WT) - 3.91mS/0.25S/0.5S/1S/1M interval at 32.768kHz • Buzzer - 8Bit × 1ch • SIO - 8Bit × 1ch • UART - 8Bit × 1ch • 12 Bit A/D Converter - 8 Input channels • LCD Driver - 34 Segments and 8 Common terminals - STOP, IDLE mode - 3.0V ~ 5.5V (@1.0 ~ 12.0MHz) • Minimum Instruction Execution Time - 167nS (@ 12MHz main clock) - 61μS (@t 32.768kHz sub clock) • Operating Temperature: – 40 ~ + 85℃ • Oscillator Type - 1.0-12MHz Crystal or Ceramic for main clock - 32.768kHz Crystal for sub clock • Package Type - 80 LQFP-1212 - 64 LQFP-1010 - Internal or external resistor bias - 2, 3, 4, 5, 6 and 8 common selectable - Bias selectable (1/2, 1/3, 1/4) • Power On Reset PS030002-0212 PRELIMINARY 10 Z51F3221 Product Specification 1.3 Ordering Information Table 1-1 Ordering Information for the Z51F3221 MCU Device Name Z51F3221ATX Z51F3221ARX ROM Size IRAM Size XRAM Size 32KB Flash 256 bytes 1k bytes Package 80-pin LQFP 64-pin LQFP 1.3.1 Part Number Suffix Designation Zilog part numbers consist of a number of components, as indicated in the following example. Example: Part number Z51F3221ARX is an 8-bit MCU with 32 KB of Flash memory and 1.25 KB of RAM in a 64pin LQFP package and operating within a –40°C to +85°C temperature range. In accordance with RoHS standards, this device has been built using lead-free solder. Z51 F 32 21 A R X Temperature Range X = –40°C to +85°C Pin Count R = 64 pins T = 80 pins Package A = LQFP Device Type Flash Memory Size 32 = 32 KB Flash Flash Memory F = General-Purpose Flash Device Family Z51 = Z8051 8-Bit Core MCU PS030002-0212 PRELIMINARY 11 Z51F3221 Product Specification 1.4 Development Tools 1.4.1 Compiler We do not provide the compiler. Please contact the third parties. The core of the Z51F3221 MCU is Mentor 8051. And, device ROM size is smaller than 64k bytes. Developer can use all kinds of third party’s standard 8051 compiler. 1.4.2 OCD emulator and debugger The OCD (On Chip Debug) emulator supports Zilog’s 8051 series MCU emulation. The OCD interface uses two-wire interfacing between PC and MCU which is attached to user’s system. The OCD can read or change the value of MCU internal memory and I/O peripherals. And the OCD also controls MCU internal debugging logic, it means OCD controls emulation, step run, monitoring, etc. The OCD Debugger program works on Microsoft-Windows NT, 2000, XP, Vista (32bit) operating system. If you want to see more details, please refer to OCD debugger manual. You can download debugger S/W and manual from our web-site. Connection: - SCLK (Z51F3221 P10 port) - SDATA (Z51F3221 P11 port) PS030002-0212 PRELIMINARY 12 Z51F3221 Product Specification 1.4.3 Programmer Single programmer: PGMplus USB: It programs MCU device directly. StandAlone PGMplus: It programs MCU device directly. OCD emulator: It can write code in MCU device too, because OCD debugging supports ISP (In System Programming). It does not require additional H/W, except developer’s target system. Gang programmer: It programs 8 MCU devices at once. So, it is mainly used in mass production line. Gang programmer is standalone type, it means it does not require host PC, after a program is downloaded from host PC to Gang programmer. Figure 1.1 StandAlone Gang8 (for Mass Production) PS030002-0212 PRELIMINARY 13 Z51F3221 Product Specification 2. Block Diagram DSDA AN0 -AN6/P20 -P26 AN7/P27 /LVIREF AVREF AVSS 12 – Bit A/D Converter DSCL Low Voltage Indicator On-Chip Debug SIO T0O/PWM0 O/SEG 35/P83 EC0/SEG 36/P84 EINT10/ACK/SEG 37/P85 T0O /PWM0O/SEG27 /P 73 EC0/SEG28 /P 74 EINT10 /ACK/SEG29 /P 75 8 – Bit Timer 0 REM/SEG34 /P82 REM/SEG26 /P72 8 – Bit Timer 1 M8051 Core UART 32K Bytes Flash 16 – Bit Timer 2 T3 O/PWM3O/EINT13 /P12 EC3/BUZO/P13 EC3/BUZO/EINT5/P05 16 – Bit Timer 3 BUZO/EC3/P13 BUZO/EC3/EINT5/P05 Buzzer P00 -P04/EINT0-EINT4 P05 /EINT5 /EC3/BUZO P06 -P07/EINT6-EINT7 P0 Port P10 /DSCL P11 /DSDA P12 /EINT13 /T3O/PWM3O P 13/EC3 /BUZO P14/SO P15/SCK P16 /SI P1 Port P20-P26/AN0-AN6 P 27/AN7 /LVIREF P2 Port P 31-P34/VLC0-VLC 3 P35 -P36/COM0-COM1 P3 Port P40-P45/SEG0- SEG5/COM2-COM7 P46-P47/SEG 6-SEG7 P4 Port P50 -P57/SEG8 -SEG15 P5 Port P60-P67/SEG16 -SEG23 P6 Port XRAM (1K Bytes) IRAM (256 Bytes) Basic Interval Timer LCD Driver/ Controller COM0-COM1/P35-P 36 COM2-COM7/SEG0 -SEG5/P40 -P45 SEG 6-SEG7/P46-P47 SEG 8-SEG15/P50-P 57 SEG16- SEG23/P60 -P67 SEG24- SEG31/P70 -P77 SEG32- SEG39/P80 -P87 VLC0-VLC3/P31-P34 P8 Port P80- P81/SEG32 -SEG33 P82/SEG 34/REM P83 /SEG 35/T0O /PWM0O P84 /SEG 36/EC0 P85 /SEG 37/ACK/EINT10 P86 /SEG 38/TXD P87 /SEG 39/RXD P7 Port P 70-P71/SEG24-SEG25 P 72/SEG 26/REM P 73/SEG 27/T0O/PWM0O P 74/SEG28 /EC0 P 75/SEG29 /ACK/EINT10 P76/SEG30 /TXD P77/SEG31 /RXD Watch Timer VDD ACK/SEG37 /EINT10 /P85 TXD/SEG38 /P86 RXD/SEG39 /P87 ACK/SEG29/EINT10/P75 TXD/SEG30 /P76 RXD/SEG31 /P77 P 92 Watchdog Timer 6KHz INT-RC OSC Voltage Down Converter SCK /P15 SO/P 14 SI/P16 P9 Port Power On Reset INT-RC OSC 8MHz LVIREF/AN7/P27 CLOCK/ SYSTEM CONTROL RESETB VREG SXOUT SXIN XIN XOUT VSS Figure 2.1 Block Diagram NOTE) 1. The P06–P07, P13, P25–P27, P70–P71, P75–P77, and P80–P84 are only in the 80-pin package. 2. The P06–P07, P13, P25–P27, P70–P71, P75–P77, and P80–P84 should be selected as push-pull or open-drain output by software control when the 64-pin package is used. PS030002-0212 PRELIMINARY 14 Z51F3221 Product Specification 3. Pin Assignment TXD/S EG3 0/P 76 ACK/EINT1 0/SEG2 9/P 75 EC0/SEG2 8/P 74 T0O /P WM0 O/S EG2 7/P 73 REM/S EG2 6/P 72 S EG2 5/P 71 S EG2 4/P 70 S EG2 3/P 67 S EG2 2/P 66 S EG2 1/P 65 S EG2 0/P 64 S EG1 9/P 63 S EG1 8/P 62 S EG1 7/P 61 S EG1 6/P 60 S EG1 5/P 57 S EG1 4/P 56 S EG1 3/P 55 S EG1 2/P 54 S EG1 1/P 53 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RXD/SEG 31 /P 77 1 60 P52 /SEG10 SEG 32 /P 80 2 59 P51 /SEG9 SEG 33 /P 81 3 58 P50 /SEG8 REM/SEG 34 /P 82 4 57 P47 /SEG7 T0O /PWM0 O/SEG 35 /P 83 5 56 P46 /SEG6 EC0/SEG 36 /P 84 6 55 P45 /COM7 /SEG 5 ACK/EINT10 /SEG 37 /P 85 7 54 P44 /COM6 /SEG 4 TXD/SEG 38 /P 86 8 53 P43 /COM5 /SEG 3 RXD/SEG 39 /P 87 9 52 P42 /COM4 /SEG 2 51 P41 /COM3 /SEG 1 VDD 10 VSS 11 XOUT 12 Z51F3221 (80LQFP-1212) 50 P40 /COM2 /SEG 0 49 P36 /COM1 XIN 13 48 P35 /COM0 P 92 14 47 P34 /VLC3 SXIN 15 46 P33 /VLC2 SXOUT 16 45 P32 /VLC1 RESETB 17 44 P31 /VLC0 VREG 18 43 AVSS EINT0/P 00 19 42 AVREF EINT1/P 01 20 41 P27 /AN7/LVIREF 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P0 3/EINT3 P0 4/EINT4 P0 5/EINT5/EC3/BUZO P0 6/EINT6 P0 7/EINT7 P1 0/DS CL P1 1/DS DA P1 2/EINT13/PWM3O/T3O P1 3/EC3/B UZO P1 4/SO P1 5/SCK P1 6/SI P2 0/AN0 P2 1/AN1 P2 2/AN2 P2 3/AN3 P2 4/AN4 P2 5/AN5 P2 6/AN6 P0 2/EINT2 22 21 Figure 3.1 Z51F3221 80LQFP-1212 Pin Assignment NOTE) On On-Chip Debugging, ISP uses P1[1:0] pin as DSDA, DSCL. PS030002-0212 PRELIMINARY 15 Z51F3221 Product Specification T0O /P WM0 O/S EG27 /P 73 RE M/SE G26/P7 2 SE G23/P6 7 SE G22/P66 SE G21/P65 SE G20/P64 SE G19/P63 SE G18/P62 SE G17/P61 SE G16/P60 SE G15/P57 SE G14/P56 SE G13/P55 SE G12/P54 SE G11/P53 SE G10/P52 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 EC0 /SEG 28 /P74 1 48 P51/SEG 9 ACK/EINT10 /SEG 37 /P85 2 47 P50/SEG 8 TXD/SEG 38 /P86 3 46 P47/SEG 7 RXD/SEG 39 /P87 4 45 P46/SEG 6 VDD 5 44 P 45/COM7/SEG5 VSS 6 43 P 44/COM6/SEG4 XOUT 7 42 P 43/COM5/SEG3 XIN 8 41 P 42/COM4/SEG2 P92 9 40 P 41/COM3/SEG1 SXIN 10 39 P 40/COM2/SEG0 SXOUT 11 38 P 36/COM1 RESETB 12 37 P 35/COM0 VREG 13 36 P 34/VLC3 EINT0 /P00 14 35 P 33/VLC2 EINT1 /P01 15 34 P 32/VLC1 EINT2 /P02 16 33 P31/VLC0 Z51F3221 (64LQFP-1010) 31 32 A VREF A VSS P 22/AN2 P 23/AN3 P 21/AN1 P 24/AN4 28 P 20/AN0 30 27 P 16/SI 29 26 P 15/SCK P 11/DS DA 25 P 10/DS CL P 14/SO 21 P 05/EINT5/EC3/BUZO 24 20 P 04/EINT4 P 12/EINT13/PWM3O /T3O 19 P 03/EINT3 23 18 22 17 Figure 3.2 Z51F3221 64LQFP-1010 Pin Assignment NOTES) 1. The P06–P07, P13, P25–P27, P70–P71, P75–P77 and P80–P84 are only in the 80-pin package. 2. The P06–P07, P13, P25–P27, P70–P71, P75–P77 and P80–P84 should be selected as push-pull or open-drain output by software control when the 64-pin package is used. 3. On On-Chip Debugging, ISP uses P1[1:0] pin as DSDA, DSCL. PS030002-0212 PRELIMINARY 16 Z51F3221 Product Specification 4. Package Diagram Figure 4.1 80-Pin LQFP Package PS030002-0212 PRELIMINARY 17 Z51F3221 Product Specification Figure 4.2 64-Pin LQFP Package PS030002-0212 PRELIMINARY 18 Z51F3221 Product Specification 5. Pin Description Table 5-1 Normal pin description PIN Name I/O Function @RESET Shared with P00 I/O Port 0 is a bit-programmable I/O port which can be configured as a schmitt-trigger input, a push-pull output, or an open-drain output. Input EINT0 P01 P02 EINT1 EINT2 A pull-up resistor can be specified in 1-bit unit. P03 EINT3 The P06 – P07 are only in the 80-pin package. P04 EINT4 P05 EINT5/EC3/BUZO P06 Output P07 P10 EINT7 I/O P11 P12 Port 1 is a bit-programmable I/O port which can be configured as a schmitt-trigger input, a push-pull output, or an open-drain output. A pull-up resistor can be specified in 1-bit unit. P13 The P13 is only in the 80-pin package P14 Input DSCL DSDA EINT13/PWM3O/T3O Output Input P15 EC3/BUZO SO SCK P16 P20 EINT6 SI I/O P21 P22 Port 2 is a bit-programmable I/O port which can be configured as an input, a push-pull output, or an opendrain output. A pull-up resistor can be specified in 1-bit unit. P23 The P25 – P27 are only in the 80-pin package. P24 Input AN0 AN1 AN2 Output AN3 AN4 P25 AN5 P26 AN6 P27 AN7/LVIREF P31 I/O P32 P33 Port 3 is a bit-programmable I/O port which can be configured as an input, a push-pull output, or an opendrain output. Input VLC1 VLC2 A pull-up resistor can be specified in 1-bit unit. P34 VLC3 P35 COM0 P36 P40 P41 P42 VLC0 COM1 I/O Port 4 is a bit-programmable I/O port which can be configured as an input, a push-pull output, or an opendrain output. A pull-up resistor can be specified in 1-bit unit. Input COM2/SEG0 COM3/SEG1 COM4/SEG2 P43 COM5/SEG3 P44 COM6/SEG4 P45 COM7/SEG5 P46 SEG6 P47 SEG7 PS030002-0212 PRELIMINARY 19 Z51F3221 Product Specification Table 5-1 Normal pin description (Continued) PIN Name I/O P50 I/O P51 P52 Function Port 5 is a bit-programmable I/O port which can be configured as an input, a push-pull output, or an opendrain output. @RESET Shared with Input SEG8 SEG9 SEG10 A pull-up resistor can be specified in 1-bit unit. P53 SEG11 P54 SEG12 P55 SEG13 P56 SEG14 P57 P60 SEG15 I/O P61 P62 Port 6 is a bit-programmable I/O port which can be configured as an input, a push-pull output, or an opendrain output. Input SEG17 SEG18 A pull-up resistor can be specified in 1-bit unit. P63 SEG16 SEG19 P64 SEG20 P65 SEG21 P66 SEG22 P67 SEG23 P70 I/O P71 P72 Port 7 is a bit-programmable I/O port which can be configured as an input (P75: schmitt-trigger input), a push-pull output, or an open-drain output. Input SEG25 SEG26/REM A pull-up resistor can be specified in 1-bit unit. P73 SEG27/T0O/PWM0O The P70 – P71 and P75 – P77 are only in the 80-pin package. P74 SEG24 SEG28/EC0 P75 SEG29/EINT10/ACK P76 SEG30/TXD P77 SEG31/RXD P80 I/O P81 P82 Port 8 is a bit-programmable I/O port which can be configured as an input (P85: schmitt-trigger input), a push-pull output, or an open-drain output. Output SEG34/REM A pull-up resistor can be specified in 1-bit unit P83 SEG35/T0O/PWM0O The P80 – P84 are only in the 80-pin package. P84 SEG32 SEG33 SEG36/EC0 P85 SEG37/EIINT10/ACK P86 SEG38/TXD P87 P92 SEG39/RXD I/O Port 9 is a bit-programmable I/O port which can be configured as an input, a push-pull output, or an opendrain output. Input – A pull-up resistor can be specified in 1-bit unit PS030002-0212 PRELIMINARY 20 Z51F3221 Product Specification Table 5-1 Normal pin description (Continued) PIN Name EINT10 I/O I/O Function External interrupt input and Timer 0 capture input @RESET Shared with Output P85/SEG37/ACK Input P75/SEG29/ACK EINT13 I/O External interrupt input and Timer 3 capture input Input P12/PWM3O/T3O EINT0 I/O External interrupt inputs Input P00 EINT1 P01 EINT2 P02 EINT3 P03 EINT4 P04 EINT5 P05/EC3/BUZO EINT6 Output P06 EINT7 T0O I/O Timer 0 interval output Output P83/SEG35/PWM0O Input P73/SEG27/PWM0O PWM0O I/O Timer 0 PWM output Output P83/SEG35/T0O Input P73/SEG27/T0O EC0 I/O Timer 0 event count input Output P84/SEG36 Input P74/SEG28 REM I/O Carrier generation output Output P82/SEG34 T3O I/O Timer 3 clock output PWM3O EC3 I/O Timer 3 PWM output I/O Timer 3 event count input Input P05/EINT5/BUZO BUZO I/O Buzzer signal output Output P13/EC3 Input P05/EC3/EINT5 SCK I/O Serial clock input/output Input P15 SI I/O Serial data input Input P16 SO TXD I/O Serial data output Input P14 I/O UART data output Output P86/SEG38 Input P76/SEG30 Output P87/SEG39 Input P77/SEG31 Output P85/SEG37/EINT10 Input P75/SEG29/EINT10 RXD ACK P07 I/O I/O UART data input UART clock Input P72/SEG26 Input P12/PWM3O/EINT13 Input P12/T3O/EINT13 Output P13/BUZO LVIREF I/O Low Voltage Indicator reference voltage Output P27/AN7 VLC0– VLC3 I/O LCD bias voltage pins Input P31–P34 COM0– COM1 I/O LCD common signal output Input P35–P36 COM2– COM7 PS030002-0212 P40/SEG0–P45/SEG5 PRELIMINARY 21 Z51F3221 Product Specification Table 5-1 Normal pin description (Continued) PIN Name SEG0– SEG5 I/O I/O Function LCD segment signal output @RESET Shared with Input P40/COM2– P47/COM7 SEG6– SEG7 P46–P47 SEG8– SEG15 P50–P57 SEG16– SEG23 P60–P67 SEG24– SEG25 P70–P71 SEG26 SEG27 P72/REM P73/T0O/PWM0O SEG28 P74/EC0 SEG29 P75/EINT10/ACK SEG30 P76/TXD SEG31 SEG32– SEG33 P77/RXD Output P80–P81 SEG34 P82/REM SEG35 P83/T0O/PWM0O SEG36 P84/EC0 SEG37 P85/EINT10/ACK SEG38 P86/TXD SEG39 AN0– AN3 P87/RXD I/O A/D converter analog input channels AN4– AN6 Input P20–P23 Output P24–P26 AN7 RESET P27/LVIREF I System reset pin (NOTE1, 2) DATA I/O On chip debugger data input/output DSCL XIN, XOUT I/O On chip debugger clock input (NOTE1, 2) SXIN, SXOUT VREG – – Input P11 Input P10 – Main oscillator pins – – – Sub oscillator pins – – – – – Regulator voltage output for sub clock 0.1μF capacitor needed AVREF – A/D converter reference voltage – – AVSS VDD, VSS – A/D converter ground – – – Power input pins – – NOTES) 1. If the P10/DSCL and P11/DSDA pins are connected to an emulator during reset or power-on reset, the pins are automatically configured as the debugger pins. 2. The P10/DSCL and P11/DSDA pins are configured as inputs with internal pull-up resistor only during the reset or power-on reset. 3. The P06–P07, P13, P25–P27, P70–P71, P75–P77 and P80–P84 are only in the 80-pin package. 4. The P06–P07, P13, P25–P27, P70–P71, P75–P77 and P80–P84 should be selected as push-pull or open-drain output by software control when the 64-pin package is used. PS030002-0212 PRELIMINARY 22 Z51F3221 Product Specification 6. Port Structures 6.1 General Purpose I/O Port Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V) VDD PULL-UP REGISTER VDD OPEN DRAIN REGISTER DATA REGISTER 0 MUX SUB-FUNC DATA OUTPUT VDD PAD 1 SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER 1 MUX 0 CMOS or Schmitt Level Input PORTx INPUT SUB-FUNC DATA INPUT ANALOG CHANNEL ENABLE ANALOG INPUT Figure 6.1 General Purpose I/O Port PS030002-0212 PRELIMINARY 23 Z51F3221 Product Specification 6.2 External Interrupt I/O Port Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V) VDD PULL-UP REGISTER VDD OPEN DRAIN REGISTER DATA REGISTER 0 MUX SUB-FUNC DATA OUTPUT VDD PAD 1 SUB-FUNC ENABLE SUB-FUNC DIRECTION 1 MUX DIRECTION REGISTER 0 0 VDD MUX EXTERNAL INTERRUPT 1 INTERRUPT ENABLE EDGE REG. Q D POLARITY REG. CP r FLAG CLEAR CMOS or Schmitt Level Input 0 PORTx INPUT MUX 1 D CP r SUB-FUNC DATA INPUT ANALOG CHANNEL ENABLE Q DEBOUNCE CLK DEBOUNCE ENABLE ANALOG INPUT Figure 6.2 External Interrupt I/O Port PS030002-0212 PRELIMINARY 24 Z51F3221 Product Specification 7. Electrical Characteristics 7.1 Absolute Maximum Ratings Table 7-1 Absolute Maximum Ratings Parameter Supply Voltage Normal Voltage Pin Total Power Dissipation Storage Temperature Symbol Rating Unit Note VDD -0.3 ~ +6.0 V – VI -0.3 ~ VDD+0.3 V VO -0.3 ~ VDD+0.3 V IOH -10 mA Maximum current output sourced by (IOH per I/O pin) ∑IOH -80 mA Maximum current (∑IOH) IOL 60 mA Maximum current sunk by (IOL per I/O pin) ∑IOL 120 mA Maximum current (∑IOL) PT 600 mW – TSTG -65 ~ +150 °C – Voltage on any pin with respect to VSS NOTE) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7.2 Recommended Operating Conditions Table 7-2 Recommended Operating Conditions Parameter Symbol (TA= -40°C ~ +85°C) Conditions fX= 32 ~ 35kHz Supply Voltage VDD fX= 1.0 ~ 4.2MHz fX= 1.0 ~ 10.0MHz fX= 1.0 ~ 12.0MHz Operating Temperature PS030002-0212 TOPR SX-tal X-tal, Internal RC VDD= 1.8 ~ 5.5V PRELIMINARY MIN TYP MAX 1.8 – 5.5 1.8 – 5.5 2.7 – 5.5 3.0 – 5.5 -40 – 85 Unit V °C 25 Z51F3221 Product Specification 7.3 A/D Converter Characteristics Table 7-3 A/D Converter Characteristics Parameter (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Symbol Conditions MIN TYP MAX Unit – –- 12 – bit – – ±2 – – ±1 – – ±3 – – ±3 20 – – Resolution Integral Linear Error ILE Differential Linearity Error DLE Zero Offset Error ZOE Full Scale Error FSE Conversion Time tCON Analog Input Voltage VAN – AVSS – AVREF AVREF – 1.8 – VDD AVSS – VSS – VSS+0.3 Analog Input Leakage Current IAN AVREF= 5.12V – – 10 μA ADC Operating Current IADC – 1 2 mA – – 0.1 μA Analog Reference Voltage Analog Ground Voltage AVREF= 2.7V – 5.5V fx= 8MHz 12bit resolution, 8MHz Enable VDD= 5.12V Disable LSB μS V NOTES) 1. Zero offset error is the difference between 0000000000 and the converted output for zero input voltage (VSS). 2. Full scale error is the difference between 1111111111 and the converted output for full-scale input voltage (AVREF). 7.4 Power-On Reset Characteristics Table 7-4 Power-On Reset Characteristics Parameter RESET Release Level VDD Voltage Rising Time POR Current PS030002-0212 (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Symbol Conditions VPOR tR IPOR MIN TYP – – 1.4 – V – – 0.05 – – 0.2 – – V/mS μA PRELIMINARY MAX Unit 26 Z51F3221 Product Specification 7.5 Low Voltage Reset and Low Voltage Indicator Characteristics Table 7-5 LVR and LVI Characteristics Parameter Detection Level Symbol VLVR VLVI (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Conditions The LVR can select all levels but LVI can select other levels except 1.60V. MIN TYP MAX – 1.60 1.75 1.85 2.00 2.15 1.95 2.10 2.25 2.05 2.20 2.35 2.17 2.32 2.47 2.29 2.44 2.59 2.39 2.59 2.79 2.55 2.75 2.95 2.73 2.93 3.13 2.94 3.14 3.34 3.18 3.38 3.58 3.37 3.67 3.97 3.70 4.00 4.30 4.10 4.40 4.70 Unit V Hysteresis △V – – 10 100 mV Minimum Pulse Width tLW – 100 – – μS LVR and LVI Current IBL Enable (Both) Enable (One of two) VDD= 3V Disable (Both) PS030002-0212 PRELIMINARY – 6.5 13.0 – 5.0 10.0 – – 0.1 μA 27 Z51F3221 Product Specification 7.6 Internal RC Oscillator Characteristics Table 7-6 Internal RC Oscillator Characteristics Parameter Frequency Tolerance Symbol fIRC – Clock Duty Ratio TOD Stabilization Time tWDTS IRC Current IIRC (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Conditions TA= 25°C TA = -40°C to +85°C – MIN TYP MAX Unit – 8.0 – MHz -10 – +10 % 40 50 60 % TA= 25°C – – 100 μS Enable – 0.5 – mA Disable – – 0.1 μA 7.7 Internal Watch-Dog Timer RC Oscillator Characteristics Table 7-7 Internal WDTRC Oscillator Characteristics Parameter (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Symbol Conditions Frequency fWDTRC – 3 Stabilization Time tWDTS – – WDTRC Current IWDTRC Enable – 1 – Disable – – 0.1 PS030002-0212 PRELIMINARY MIN TYP MAX Unit 6 9 kHz – 1 mS μA 28 Z51F3221 Product Specification 7.8 DC Characteristics Table 7-8 DC Characteristics Parameter Input High Voltage Input Low Voltage Output High Voltage (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, fXIN= 12MHz) Symbol MIN TYP MAX Unit VIH1 P0x, P1x, P75, P85, RESETB 0.8VDD – VDD V VIH2 All input pins except VIH1 0.7VDD – VDD V VIL1 P0x, P1x, P75, P85, RESETB – – 0.2VDD V VIL2 All input pins except VIL1 – – 0.3VDD V VOH1 All output ports; IOH= -2mA, VDD= 4.5V VDD-1.0 – – V VOL1 P1x, P2x; IOL= 15mA, VDD= 4.5V – – 1.0 VOL2 All output ports except VOL1; IOL= 10mA, VDD=4.5V – – 1.0 V Output Low Voltage Conditions Input High Leakage Current IIH All input ports – – 1 μA Input Low Leakage Current IIL All input ports -1 – – μA RPU1 VI=0V, TA= 25°C All Input ports VDD=5.0V 25 50 100 VDD=3.0V 50 100 200 RPU2 VI=0V, TA= 25°C RESETB VDD=5.0V 150 250 400 VDD=3.0V 300 500 700 Pull-Up Resistor kΩ kΩ RX1 XIN= VDD, XOUT= VSS TA= 25°C, VDD= 5V 600 1200 2000 RX2 SXIN=VDD, SXOUT=VSS TA= 25 °C ,VDD=5V 1750 3500 7000 LCD Voltage Dividing Resistor RLCD TA= 25 °C 25 50 80 kΩ Common Driver Voltage Drop VDC VDD= 2.7V to 5.5V, |VLCD-COMi|, (i=0-7) -15uA per common pin – – 120 mV Segment Driver Voltage Drop VDS VDD= 2.7V to 5.5V, |VLCD-SEGx|, (x=0-39) -15uA per common pin – – 120 mV 0.75VDD0.2 0.75VDD 0.75VDD+ 0.2 0.50VDD0.2 0.5VDD 0.50VDD+ 0.2 0.25VDD0.2 0.25VDD 0.25VDD+ 0.2 OSC feedback resistor VLC1 Middle Output Voltage (NOTE) VLC2 VDD= 2.7V to 5.5V, 1/4 bias LCD clock= 0Hz, VLC0=VDD VLC3 kΩ V NOTE) It is middle output voltage when the VDD and the VLC0 node are connected. PS030002-0212 PRELIMINARY 29 Z51F3221 Product Specification Table 7-8 DC Characteristics (Continued) Parameter Symbol IDD1 (RUN) IDD2 Supply Current (IDLE) IDD3 (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, fXIN= 12MHz) Condition MIN TYP MAX Unit fXIN= 12MHz, VDD= 5V±10% – 3.0 6.0 fXIN= 10MHz, VDD= 3V±10% – 2.2 4.4 fXIN= 4.2MHz, VDD= 3V±10% – 1.6 3.2 fXIN= 12MHz, VDD= 5V±10% – 2.0 4.0 fXIN= 10MHz, VDD= 3V±10% – 1.3 2.6 fXIN= 4.2MHz, VDD= 3V±10% – 0.7 1.4 Sub RUN – 50.0 80.0 μA mA mA IDD4 fXIN= 32.768kHz VDD= 3V±10% TA= 25°C,PSAVE=1 Sub IDLE – 4.0 8.0 μA IDD5 STOP, VDD= 5V±10%, TA= 25°C – 0.5 3.0 μA NOTES) 1. Where the fXIN is an external main oscillator, fSUB is an external sub oscillator, the fIRC is an internal RC oscillator, and the fx is the selected system clock. 2. All supply current items don’t include the current of an internal Watch-dog timer RC (WDTRC) oscillator and a peripheral block. 3. All supply current items include the current of the power-on reset (POR) block. PS030002-0212 PRELIMINARY 30 Z51F3221 Product Specification 7.9 Serial I/O Characteristics Table 7-9 Serial I/O Characteristics (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Parameter SCK cycle time SCK high, low width Symbol Conditions MIN TYP External SCK source 1,000 Internal SCK source 1,000 tKH, External SCK source 500 tKL Internal SCK source tKCY/2-50 tKCY SI setup time to SCK high tSIK SI hold time to SCK high tKSI Output delay for SCK to SO tKSO Interrupt input high, low width tINTH, RESETB input low width tRSL tINTL External SCK source 250 Internal SCK source 250 External SCK source 400 Internal SCK source 400 External SCK source MAX Unit nS nS – – nS nS 300 – – All interrupt, VDD= 5V 200 – – nS Input, VDD= 5V 10 – – μS Internal SCK source nS t INTH t INTL External Interrupt 250 0.8 VDD 0.2 VDD Figure 7.1 Input Timing for External Interrupts t RSL RESETB 0.2 VDD Figure 7.2 Input Timing for RESETB PS030002-0212 PRELIMINARY 31 Z51F3221 Product Specification t KH t KL SCK 0.8 VDD 0.2 VDD t SIK t KSI 0.8 VDD SI 0.2 VDD t KSO SO Output Data Figure 7.3 Serial Interface Data Transfer Timing 7.10 UART Characteristics Table 7-10 UART Characteristics Parameter (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, fXIN=11.1MHz) Symbol MIN TYP MAX Unit Serial port clock cycle time tSCK 1250 tCPU x 16 1650 nS Output data setup to clock rising edge tS1 590 tCPU x 13 – nS Clock rising edge to input data valid tS2 – – 590 nS Output data hold after clock rising edge tH1 tCPU - 50 tCPU – nS Input data hold after clock rising edge tH2 0 – – nS Serial port clock High, Low level width tHIGH, tLOW 470 tCPU x 8 970 nS PS030002-0212 PRELIMINARY 32 Z51F3221 Product Specification t SCK t HIGH t LOW Figure 7.4 Waveform for UART Timing Characteristics t SCK Shift Clock tS 1 Data Out tH1 D0 D1 D2 tS2 Data In Valid D3 D4 D5 D6 D7 t H2 Valid Valid Valid Valid Valid Valid Valid Figure 7.5 Timing Waveform for the UART Module PS030002-0212 PRELIMINARY 33 Z51F3221 Product Specification 7.11 Data Retention Voltage in Stop Mode Table 7-11 Data Retention Voltage in Stop ModeR Parameter (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Symbol Conditions MIN TYP MAX Unit Data retention supply voltage VDDDR – 1.8 – 5.5 V Data retention supply current IDDDR – – 1 μA VDDR= 1.8V, (TA= 25°C), Stop mode ~ ~ Idle Mode (Watchdog Timer Active) Stop Mode Normal Operating Mode Data Retention ~ V DD VDDDR Execution of STOP Instruction 0.8VDD INT Request t WAIT NOTE: tWAIT is the same as (the selected bit overflow of BIT) X 1/(BIT Clock) Figure 7.6 Stop Mode Release Timing when Initiated by an Interrupt RESET Occurs ~ Oscillation Stabillization Time Stop Mode Normal Operating Mode Data Retention ~ ~ VDD V DDDR RESETB Execution of STOP Instruction 0.8 VDD 0.2 VDD TWAIT NOTE : tWAIT is the same as (4096 X 4 X 1/fx) (16.4mS @ 1MHz) Figure 7.7 Stop Mode Release Timing when Initiated by RESETB PS030002-0212 PRELIMINARY 34 Z51F3221 Product Specification 7.12 Internal Flash Rom Characteristics Table 7-12 Internal Flash Rom Characteristics Parameter (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Symbol Condition MIN TYP MAX Sector Write Time tFSW – – 2.5 2.7 Sector Erase Time tFSE – – 2.5 2.7 Hard-Lock Time tFHL – – 2.7 Page Buffer Reset Time tFBR – – 2.5 – fPGM – 1 – – MHz NFWE – – – 100,000 Times Flash Programming Frequency Endurance of Write/Erase 5 Unit mS μS NOTE) During a flash operation, SCLK[1:0] of SCCR must be set to “00” or “01” (INT-RC OSC or Main X-TAL for system clock). 7.13 Input/Output Capacitance Table 7-13 Input/Output Capacitance Parameter Input Capacitance Output Capacitance I/O Capacitance PS030002-0212 Symbol CIN COUT CIO (TA= -40°C ~ +85°C, VDD= 0V) Condition fx= 1MHz Unmeasured pins are connected to VSS PRELIMINARY MIN TYP MAX Unit – – 10 pF 35 Z51F3221 Product Specification 7.14 Main Clock Oscillator Characteristics Table 7-14 Main Clock Oscillator Characteristics Oscillator Parameter Crystal Main oscillation frequency External Clock XIN Condition Main oscillation frequency Ceramic Oscillator XIN input frequency (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) MIN TYP MAX 1.8V – 5.5V 1.0 – 4.2 2.7V – 5.5V 1.0 – 10.0 3.0V – 5.5V 1.0 – 12.0 1.8V – 5.5V 1.0 – 4.2 2.7V – 5.5V 1.0 – 10.0 3.0V – 5.5V 1.0 – 12.0 1.8V – 5.5V 1.0 – 4.2 2.7V – 5.5V 1.0 – 10.0 3.0V – 5.5V 1.0 – 12.0 Unit MHz MHz MHz XOUT C2 C1 Figure 7.8 Crystal/Ceramic Oscillator XIN XOUT External Clock Source Open Figure 7.9 External Clock PS030002-0212 PRELIMINARY 36 Z51F3221 Product Specification 7.15 Sub Clock Oscillator Characteristics Table 7-15 Sub Clock Oscillator Characteristics Oscillator Crystal Parameter Sub oscillation frequency External Clock SXIN input frequency SXIN (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Condition 1.8V – 5.5V MIN TYP MAX 32 32.768 35 Unit kHz 32 – 100 kHz SXOUT VREG 0.1uF C2 C1 Figure 7.10 Crystal Oscillator SXIN SXOUT External Clock Source Open Figure 7.11 External Clock PS030002-0212 PRELIMINARY 37 Z51F3221 Product Specification 7.16 Main Oscillation Stabilization Characteristics Table 7-16 Main Oscillation Stabilization Characteristics Oscillator Crystal Ceramic External Clock (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Parameter MIN TYP MAX Unit fx > 1MHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. – – 60 mS – – 10 mS fXIN = 1 to 12MHz XIN input high and low width (tXH, tXL) 42 – 500 nS 1/f XIN t XL tXH 0.8VDD XIN 0.2VDD Figure 7.12 Clock Timing Measurement at XIN 7.17 Sub Oscillation Characteristics Table 7-17 Sub Oscillation Stabilization Characteristics Oscillator Crystal External Clock (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Parameter – SXIN input high and low width (tXH, tXL) MIN – TYP – MAX 10 Unit S 5 – 15 μS 1/fSUB t XL tXH 0.8VDD SXIN 0.2VDD Figure 7.13 Clock Timing Measurement at SXIN PS030002-0212 PRELIMINARY 38 Z51F3221 Product Specification 7.18 Operating Voltage Range (Main OSC frequency) (Sub OSC frequency) 12.0MHz 32.768KHz 10.0MHz 4.2MHz 1.0MHz 1.8 2.7 3.0 5.5 1.8 5.5 Supply voltage (V) Supply voltage (V) Figure 7.14 Operating Voltage Range PS030002-0212 PRELIMINARY 39 Z51F3221 Product Specification 7.19 Recommended Circuit and Layout { } This 0.1uF capacitor should be within 1cm from the VDD pin of MCU on the PCB layout. VDD VCC MC96F6832/F6632 High-Current Part { Infrared LED, FND(7-Segment), ,,,,, etc VCC + 0.1uF 0.1uF VSS VDD } { DC Power The MCU power line(VDD and VSS) should be separated from the high current part at a DC power node on the PCB layout. } I/O 0.01uF { XIN X-tal C1 C2 SXOUT 32.768kHz VREG } The main and sub crystal should be as close by the MCU as possible. XOUT SXIN This 0.01uF capacitor is alternatively for noise immunity. The load capacitors of the sub clock - C1, C2: CL x 2 ± 15% - CL = (C1 x C2)/(C1 + C2) - Cstray - CL: the specific capacitor value of crystal - Cstray: the parasitic capacitor of a PCB (1pF – 1.5pF) 0.1uF The VREG pin is the output of an internal regulator for sub oscillator . So, this 0.1uF capacitor is needed and should be as close by the MCU as possible if the sub clock is used for system. Figure 7.15 Recommended Circuit and Layout PS030002-0212 PRELIMINARY 40 Z51F3221 Product Specification 7.20 Typical Characteristics These graphs and tables provided in this section are only for design guidance and are not tested or guaranteed. In graphs or tables some data are out of specified operating range (e.g. out of specified VDD range). This is only for information and devices are guaranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean - 3σ) respectively where σ is standard deviation. mA 3.00 2.50 2.00 4.19MHz -40℃ 1.50 4.19MHz +25℃ 4.19MHz +85℃ 1.00 0.50 0.00 2.7V 3.0V 3.3V 4.5V 5.0V 5.5V Figure 7.16 RUN (IDD1 ) Current mA 1.60 1.40 1.20 1.00 4.19MHz -40℃ 0.80 4.19MHz +25℃ 0.60 4.19MHz +85℃ 0.40 0.20 0.00 2.7V 3.0V 3.3V 4.5V 5.0V 5.5V Figure 7.17 IDLE (IDD2) Current PS030002-0212 PRELIMINARY 41 Z51F3221 Product Specification uA 70.0 60.0 50.0 40.0 -40℃ 30.0 +25℃ +85℃ 20.0 10.0 0.0 2.7V 3.0V 3.3V 4.5V 5.0V 5.5V Figure 7.18 SUB RUN (IDD3) Current uA 6.00 5.00 4.00 -40℃ 3.00 +25℃ +85℃ 2.00 1.00 0.00 2.7V 3.0V 3.3V 4.5V 5.0V 5.5V Figure 7.19 SUB IDLE (IDD4) Current PS030002-0212 PRELIMINARY 42 Z51F3221 Product Specification uA 2.50 2.00 1.50 -40℃ +25℃ 1.00 +85℃ 0.50 0.00 2.7V 3.0V 3.3V 4.5V 5.0V 5.5V Figure 7.20 STOP (IDD5) Current PS030002-0212 PRELIMINARY 43 Z51F3221 Product Specification 8. Memory The Z51F3221 MCU addresses two separate address memory stores: Program memory and Data memory. The logical separation of Program and Data memory allows Data memory to be accessed by 8-bit addresses, which makes the 8-bit CPU access the data memory more rapidly. Nevertheless, 16-bit Data memory addresses can also be generated through the DPTR register. The Z51F3221 MCU provides on-chip 32k bytes of the ISP type flash program memory, which can be read and written to. Internal data memory (IRAM) is 256 bytes and it includes the stack area. External data memory (XRAM) is 1k bytes and it includes 40 bytes of LCD display RAM. 8.1 Program Memory A 16-bit program counter is capable of addressing up to 64k bytes, but this device has just 32k bytes program memory space. Figure 8-1 shows the map of the lower part of the program memory. After reset, the CPU begins execution from location 0000H. Each interrupt is assigned a fixed location in program memory. The interrupt causes the CPU to jump to that location, where it commences execution of the service routine. External interrupt 10, for example, is assigned to location 000BH. If external interrupt 10 is going to be used, its service routine must begin at location 000BH. If the interrupt is not going to be used, its service location is available as general purpose program memory. If an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8 byte interval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use. PS030002-0212 PRELIMINARY 44 Z51F3221 Product Specification FFFFH 7FFFH 32k Bytes 0000H Figure 8.1 Program Memory - 32k Bytes Including Interrupt Vector Region PS030002-0212 PRELIMINARY 45 Z51F3221 Product Specification 8.2 Data Memory Figure 8-2 shows the internal data memory space available. FFH FFH Upper 128 Bytes Internal RAM (Indirect Addressing ) 80H Special Function Registers 128 Bytes (Direct Addressing) 80H 7FH Lower 128 Bytes Internal RAM (Direct or Indirect Addressing ) 00H Figure 8.2 Data Memory Map The internal data memory space is divided into three blocks, which are generally referred to as the lower 128 bytes, upper 128 bytes, and SFR space. Internal data memory addresses are always one byte wide, which implies an address space of only 256 bytes. However, in fact the addressing modes for internal RAM can accommodate up to 384 bytes by using a simple trick. Direct addresses higher than 7FH access one memory space and indirect addresses higher than 7FH access a different memory space. Thus Figure 8-2 shows the upper 128 bytes and SFR space occupying the same block of addresses, 80H through FFH, although they are physically separate entities. The lower 128 bytes of RAM are present in all 8051 devices as mapped in Figure 8-3. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers as R0 through R7. Two bits in the Program Status Word select which register bank is in use. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing. The next 16 bytes above the register banks form a block of bit-addressable memory space. The 8051 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00H through 7FH. All of the bytes in the lower 128 bytes can be accessed by either direct or indirect addressing. The upper 128 bytes RAM can only be accessed by indirect addressing. These spaces are used for data RAM and stack. PS030002-0212 PRELIMINARY 46 Z51F3221 Product Specification 7FH General Purpose Register 80 Bytes 30H 2FH 16 Bytes (128 bits) Bit Addressable 20H 1FH 8 Bytes 18H 17H 8 Bytes 10H 0FH 8 Bytes 08H 07H 8 Bytes 00H Register Bank 3 (8 Bytes) 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 Register Bank 2 (8 Bytes) Register Bank 1 (8 Bytes) Register Bank 0 (8 Bytes) R7 R6 R5 R4 R3 R2 R1 R0 Figure 8.3 Lower 128 Bytes RAM PS030002-0212 PRELIMINARY 47 Z51F3221 Product Specification 8.3 XRAM Memory The Z51F3221 MCU features 1k bytes XRAM. This area has no relation with RAM/Flash. It can be read and written to through SFR with 8-bit unit. 03FFH External RAM 1k Bytes (Indirect Addressing ) 0028 H 0027 H 0000 H LCD Display RAM Figure 8.4 XDATA Memory Area PS030002-0212 PRELIMINARY 48 Z51F3221 Product Specification 8.4 SFR Map 8.4.1 SFR Map Summary Table 8-1 SFR Map Summary - Reserved M8051 compatible (1) 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH 0F8H IP1 – FSADRH FSADRM FSADRL FIDR FMCR – 0F0H B PFSR3 PFSR4 PFSR5 PFSR6 PFSR7 PFSR8 LVRCR 0E8H P9CDR P0DB P1DB LCDCRL LCDCRH PFSR0 PFSR1 PFSR2 0E0H ACC LVICR UARTCR1 UARTCR2 UARTCR3 UARTST UARTBD UARTDR 0D8H P8 OSCCR P4PU P5PU P6PU P7PU P8PU – 0D0H PSW P8IO P8OD – P0PU P1PU P2PU P3PU 0C8H P7 P7IO T1CR T1CNT T1DRL T1DRH CARCR P7OD 0C0H P6 P6IO T3CR TIFR T3CNTL T3CNTH T3DRL/ T3CDRL T3DRH/ T3CDRH 0B8H IP P5IO T2CR P6OD T2CNTL T2CNTH T2DRL T2DRH 0B0H P5 P4IO T0CR T0CNT T0DR/ T0CDR SIOCR SIODR SIOPS 0A8H IE IE1 IE2 IE3 EIENAB0 EIFLAG0 EIEDGE0 EIPOL0 0A0H P4 P3IO EO EIENAB1 EIFLAG1 EIEDGE1 EIPOL1 P5OD 98H P3 P2IO ADCCRL ADCDRL ADCDRH ADCCRH WTCR WTDR/ WTCNT 90H P2 P1IO P0OD P1OD P2OD P3OD P4OD BUZCR 88H P1 P0IO SCCR BITCR BITCNT WDTCR WDTDR/ WDTCNT BUZDR 80H P0 SP DPL DPH DPL1 DPH1 RSTFR PCON NOTE) These registers are bit-addressable. PS030002-0212 PRELIMINARY 49 Z51F3221 Product Specification 8.4.2 SFR Map Table 8-2 SFR Map Address 80H Function P0 Data Register 81H Stack Pointer 82H Data Pointer Register Low Symbol R/W P0 @Reset R/W 7 1 6 1 5 0 4 0 3 0 2 0 1 0 0 0 SP R/W 0 0 0 0 0 1 1 1 DPL R/W 0 0 0 0 0 0 0 0 0 83H Data Pointer Register High DPH R/W 0 0 0 0 0 0 0 84H Data Pointer Register Low 1 DPL1 R/W 0 0 0 0 0 0 0 0 85H Data Pointer Register High 1 DPH1 R/W 0 0 0 0 0 0 0 0 86H Reset Flag Register RSTFR R/W 1 x 0 0 1 – – – 87H Power Control Register PCON R/W 0 – – – 0 0 0 0 P1 R/W – 0 0 0 1 0 0 0 P0IO R/W 1 1 0 0 0 0 0 0 88H P1 Data Register 89H P0 Direction Register 8AH System and Clock Control Register SCCR R/W 0 0 – – – – 0 0 8BH Basic Interval Timer Control Register BITCR R/W 0 – – – 0 0 0 1 8CH Basic Interval Timer Counter Register BITCNT R 0 0 0 0 0 0 0 0 8DH Watch Dog Timer Control Register WDTCR R/W 0 0 0 – – – – 0 Watch Dog Timer Data Register WDTDR W 1 1 1 1 1 1 1 1 8EH 8FH Watch Dog Timer Counter Register BUZZER Data Register WDTCNT R 0 0 0 0 0 0 0 0 BUZDR R/W 1 1 1 1 1 1 1 1 90H P2 Data Register P2 R/W 1 1 1 1 1 0 0 0 91H P1 Direction Register P1IO R/W – 0 0 0 1 0 0 0 92H P0 Open-drain Selection Register P0OD R/W 1 1 0 0 0 0 0 0 93H P1 Open-drain Selection Register P1OD R/W – 0 0 0 1 0 0 0 94H P2 Open-drain Selection Register P2OD R/W 1 1 1 1 1 0 0 0 95H P3 Open-drain Selection Register P3OD R/W – 0 0 0 0 0 0 – 96H P4 Open-drain Selection Register P4OD R/W 0 0 0 0 0 0 0 0 97H BUZZER Control Register BUZCR R/W – – – – – 0 0 0 98H P3 Data Register P3 R/W – 0 0 0 0 0 0 – 99H P2 Direction Register P2IO R/W 1 1 1 1 1 0 0 0 9AH A/D Converter Control Low Register ADCCRL R/W 0 0 0 0 0 0 0 0 9BH A/D Converter Data Low Register ADCDRL R x x x x x x x x 9CH A/D Converter Data High Register ADCDRH R x x x x x x x x 9DH A/D Converter Control High Register ADCCRH R/W 0 – – – – 0 0 0 9EH Watch Timer Control Register WTCR R/W 0 – – 0 0 0 0 0 Watch Timer Data Register WTDR W 0 1 1 1 1 1 1 1 WTCNT R – 0 0 0 0 0 0 0 9FH Watch Timer Counter Register PS030002-0212 PRELIMINARY 50 Z51F3221 Product Specification Table 8-2 SFR Map (Continued) Address A0H Function P4 Data Register @Reset Symbol R/W P4 R/W 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 P3IO R/W – 0 0 0 0 0 0 – EO R/W – – – 0 – 0 0 0 A1H P3 Direction Register A2H Extended Operation Register A3H External Interrupt Enable Register 1 EIENAB1 R/W – – – – – – 0 0 A4H External Interrupt Flag Register 1 EIFLAG1 R/W – – – – – – 0 0 A5H External Interrupt Edge Register 1 EIEDGE1 R/W – – – – – – 0 0 A6H External Interrupt Polarity Register 1 EIPOL1 R/W – – – – – – 0 0 A7H P5 Open-drain Selection Register P5OD R/W 0 0 0 0 0 0 0 0 A8H Interrupt Enable Register IE R/W 0 – 0 – – 0 0 – A9H Interrupt Enable Register 1 IE1 R/W – – 0 0 0 – – – AAH Interrupt Enable Register 2 IE2 R/W – – 0 0 0 0 0 0 ABH Interrupt Enable Register 3 IE3 R/W – – – 0 0 0 – 0 ACH External Interrupt Enable Register 0 EIENAB0 R/W 0 0 0 0 0 0 0 0 ADH External Interrupt Flag Register 0 EIFLAG0 R/W 0 0 0 0 0 0 0 0 AEH External Interrupt Edge Register 0 EIEDGE0 R/W 0 0 0 0 0 0 0 0 AFH External Interrupt Polarity Register 0 EIPOL0 R/W 0 0 0 0 0 0 0 0 B0H P5 Data Register P5 R/W 0 0 0 0 0 0 0 0 B1H P4 Direction Register P4IO R/W 0 0 0 0 0 0 0 0 B2H Timer 0 Control Register T0CR R/W 0 0 0 0 0 0 0 0 B3H Timer 0 Counter Register T0CNT R 0 0 0 0 0 0 0 0 T0DR R/W 1 1 1 1 1 1 1 1 B4H Timer 0 Data Register Timer 0 Capture Data Register T0CDR R 0 0 0 0 0 0 0 0 B5H SIO Control Register SIOCR R/W 0 0 0 0 0 0 0 0 B6H SIO Data Register SIODR R/W 0 0 0 0 0 0 0 0 B7H SIO Pre-scaler Register SIOPS R/W 0 0 0 0 0 0 0 0 B8H Interrupt Priority Register IP R/W – – 0 0 0 0 0 0 B9H P5 Direction Register P5IO R/W 0 0 0 0 0 0 0 0 BAH Timer 2 Control Register T2CR R/W 0 – – 0 0 0 0 0 BBH P6 Open-drain Selection Register P6OD R/W 0 0 0 0 0 0 0 0 BCH Timer 2 Counter Low Register T2CNTL R 0 0 0 0 0 0 0 0 BDH Timer 2 Counter High Register T2CNTH R 0 0 0 0 0 0 0 0 BEH Timer 2 Data Low Register T2DRL R/W 1 1 1 1 1 1 1 1 BFH Timer 2 Data High Register T2DRH R/W 1 1 1 1 1 1 1 1 PS030002-0212 PRELIMINARY 51 Z51F3221 Product Specification Table 8-2 SFR Map (Continued) Address C0H Function P6 Data Register @Reset Symbol R/W P6 R/W 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 C1H P6 Direction Register P6IO R/W 0 0 0 0 0 0 0 0 C2H Timer 3 Control Register T3CR R/W 0 0 0 0 0 0 0 0 C3H Timer Interrupt Flag Register TIFR R/W 0 – 0 0 0 0 0 0 C4H Timer 3 Counter Low Register T3CNTL R 0 0 0 0 0 0 0 0 Timer 3 Counter High Register T3CNTH R 0 0 0 0 0 0 0 0 T3DRL R/W 1 1 1 1 1 1 1 1 0 C5H C6H C7H Timer 3 Data Low Register Timer 3 Capture Data Low Register T3CDRL R 0 0 0 0 0 0 0 Timer 3 Data High Register T3DRH R/W 1 1 1 1 1 1 1 1 T3CDRH R 0 0 0 0 0 0 0 0 Timer 3 Capture Data High Register C8H P7 Data Register C9H P7 Direction Register P7 R/W 0 0 0 0 0 0 0 0 P7IO R/W 0 0 0 0 0 0 0 0 CAH CBH Timer 1 Control Register T1CR R/W 0 – 0 0 0 0 0 0 Timer 1 Counter Register T1CNT R 0 0 0 0 0 0 0 0 CCH CDH Timer 1 Data Low Register T1DRL R/W 1 1 1 1 1 1 1 1 Timer 1 Data High Register T1DRH R/W 1 1 1 1 1 1 1 1 CEH Carrier Control Register CARCR R/W – – 0 0 – – 0 0 CFH P7 Open-drain Selection Register P7OD R/W 0 0 0 0 0 0 0 0 D0H Program Status Word Register PSW R/W 0 0 0 0 0 0 0 0 D1H P8 Direction Register P8IO R/W 1 1 1 1 1 1 1 1 D2H P8 Open-drain Selection Register P8OD R/W 1 1 1 1 1 1 1 1 D3H Reserved – – D4H P0 Pull-up Resistor Selection Register P0PU R/W 0 0 0 0 0 0 0 0 D5H P1 Pull-up Resistor Selection Register P1PU R/W – 0 0 0 0 0 0 0 D6H P2 Pull-up Resistor Selection Register P2PU R/W 0 0 0 0 0 0 0 0 D7H P3 Pull-up Resistor Selection Register P3PU R/W – 0 0 0 0 0 0 – D8H P8 Data Register D9H Oscillator Control Register DAH DBH – P8 R/W 1 1 1 1 1 1 1 1 OSCCR R/W – – – 0 0 0 0 0 P4 Pull-up Resistor Selection Register P4PU R/W 0 0 0 0 0 0 0 0 P5 Pull-up Resistor Selection Register P5PU R/W 0 0 0 0 0 0 0 0 DCH P6 Pull-up Resistor Selection Register P6PU R/W 0 0 0 0 0 0 0 0 DDH P7 Pull-up Resistor Selection Register P7PU R/W 0 0 0 0 0 0 0 0 P8PU – R/W 0 0 0 0 0 0 0 0 DEH DFH P8 Pull-up Resistor Selection Register Reserved PS030002-0212 PRELIMINARY – – 52 Z51F3221 Product Specification Table 8-2 SFR Map (Continued) Address Function @Reset Symbol R/W ACC R/W 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 E0H Accumulator Register E1H Low Voltage Indicator Control Register LVICR R/W 0 – 0 0 0 0 0 0 E2H UART Control Register 1 UARTCR1 R/W – 0 0 0 0 0 0 0 E3H UART Control Register 2 UARTCR2 R/W 0 0 0 0 0 0 0 0 E4H UART Control Register 3 UARTCR3 R/W 0 0 0 – – 0 0 0 E5H UART Status Register UARTST R/W 1 0 0 0 0 0 0 0 E6H UART Baud Rate Generation Register UARTBD R/W 1 1 1 1 1 1 1 1 E7H UART Data Register UARTDR R/W 0 0 0 0 0 0 0 0 E8H P9 Control and Data Register P9CDR R/W 0 – – – 0 0 0 0 E9H P0 Debounce Enable Register P0DB R/W 0 0 0 0 0 0 0 0 EAH P1 Debounce Enable Register P1DB R/W 0 0 0 0 – 0 – – EBH LCD Driver Control Low Register LCDCRL R/W – – – – – – 0 0 ECH LCD Driver Control High Register LCDCRH R/W 0 0 0 0 0 0 0 0 EDH Port Function Selection Register 0 PFSR0 R/W 0 0 0 0 0 0 0 0 EEH Port Function Selection Register 1 PFSR1 R/W – 0 0 0 0 0 0 0 EFH Port Function Selection Register 2 PFSR2 R/W 0 0 0 0 0 0 0 0 F0H B Register B R/W 0 0 0 0 0 0 0 0 F1H Port Function Selection Register 3 PFSR3 R/W 0 0 0 0 0 0 0 0 F2H Port Function Selection Register 4 PFSR4 R/W 0 0 0 0 0 0 0 0 F3H Port Function Selection Register 5 PFSR5 R/W 0 0 0 0 0 0 0 0 F4H Port Function Selection Register 6 PFSR6 R/W 0 0 0 0 0 0 0 0 F5H Port Function Selection Register 7 PFSR7 R/W 0 0 0 0 0 0 0 0 F6H Port Function Selection Register 8 PFSR8 R/W 0 0 0 0 0 0 0 0 F7H Low Voltage Reset Control Register LVRCR R/W 0 – – 0 0 0 0 0 IP1 R/W – – 0 0 0 0 0 0 – – F8H Interrupt Priority Register 1 F9H Reserved FAH Flash Sector Address High Register FSADRH R/W – – – – 0 0 0 0 FBH Flash Sector Address Middle Register FSADRM R/W 0 0 0 0 0 0 0 0 FCH Flash Sector Address Low Register FSADRL R/W 0 0 0 0 0 0 0 0 FDH Flash Identification Register FIDR R/W 0 0 0 0 0 0 0 0 FEH Flash Mode Control Register FMCR R/W 0 – – – – 0 0 0 FFH Reserved – – PS030002-0212 PRELIMINARY – – 53 Z51F3221 Product Specification 8.4.3 Compiler Compatible SFR ACC (Accumulator Register) : E0H 7 6 5 4 R/W R/W R/W R/W 3 2 1 R/W R/W R/W 3 2 1 R/W R/W R/W 3 2 1 R/W R/W R/W 3 2 1 R/W R/W R/W 3 2 1 R/W R/W R/W 0 ACC ACC R/W Initial value : 00H Accumulator B (B Register) : F0H 7 6 5 4 R/W R/W R/W R/W 0 B B R/W Initial value : 00H B Register SP (Stack Pointer) : 81H 7 6 5 4 0 SP R/W R/W R/W SP R/W R/W Initial value : 07H Stack Pointer DPL (Data Pointer Register Low) : 82H 7 6 5 4 0 DPL R/W R/W R/W DPL R/W R/W Initial value : 00H Data Pointer Low DPH (Data Pointer Register High) : 83H 7 6 5 4 R/W R/W R/W R/W 0 DPH DPH PS030002-0212 R/W Initial value : 00H Data Pointer High PRELIMINARY 54 Z51F3221 Product Specification DPL1 (Data Pointer Register Low 1) : 84H 7 6 5 4 3 2 1 R/W R/W R/W 3 2 1 R/W R/W R/W 2 1 0 DPL1 R/W R/W R/W DPL1 R/W R/W Initial value : 00H Data Pointer Low 1 DPH1 (Data Pointer Register High 1) : 85H 7 6 5 4 0 DPH1 R/W R/W R/W DPH1 R/W R/W Initial value : 00H Data Pointer High 1 PSW (Program Status Word Register) : D0H 7 6 5 4 3 CY AC F0 RS1 RS0 OV F1 R/W R/W R/W R/W R/W R/W R/W 0 P R/W Initial value : 00H CY Carry Flag AC Auxiliary Carry Flag F0 General Purpose User-Definable Flag RS1 Register Bank Select bit 1 RS0 Register Bank Select bit 0 OV Overflow Flag F1 User-Definable Flag P Parity Flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of ‘1’ bits in the accumulator EO (Extended Operation Register) : A2H 7 6 5 4 3 2 1 0 – – – TRAP_EN – DPSEL2 DPSEL1 DPSEL0 – – – R/W – R/W R/W TRAP_EN DPSEL[2:0] R/W Initial value : 00H Select the Instruction (Keep always ‘0’). 0 Select Software TRAP Instruction 1 Select MOVC @(DPTR++), A Select Banked Data Pointer Register DPSEL2 DPSEL1 SPSEL0 Description 0 0 0 DPTR0 0 0 1 DPTR1 Reserved PS030002-0212 PRELIMINARY 55 Z51F3221 Product Specification 9. I/O Ports 9.1 I/O Ports The Z51F3221 MCU features ten groups of I/O ports (P0 ~ P9). Each port can be easily configured by software as I/O pin, internal pull up and open-drain pin to meet various system configurations and design requirements. Also P0 includes function that can generate interrupt according to change of state of the pin. 9.2 Port Register 9.2.1 Data Register (Px) Data Register is a bidirectional I/O port. If ports are configured as output ports, data can be written to the corresponding bit of the Px. If ports are configured as input ports, the data can be read from the corresponding bit of the Px. 9.2.2 Direction Register (PxIO) Each I/O pin can be independently used as an input or an output through the PxIO register. Bits cleared in this register will make the corresponding pin of Px to input mode. Set bits of this register will make the pin to output mode. Almost bits are cleared by a system reset, but some bits are set by a system reset. 9.2.3 Pull-up Resistor Selection Register (PxPU) The on-chip pull-up resistor can be connected to I/O ports individually with a pull-up resistor selection register (PxPU). The pull-up register selection controls the pull-up resister enable/disable of each port. When the corresponding bit is 1, the pull-up resister of the pin is enabled. When 0, the pull-up resister is disabled. All bits are cleared by a system reset. 9.2.4 Open-drain Selection Register (PxOD) There are internally open-drain selection registers (PxOD) for P0 ~ P8 and a bit for P9. The open-drain selection register controls the open-drain enable/disable of each port. Almost ports become push-pull by a system reset, but some ports become open-drain by a system reset. 9.2.5 Debounce Enable Register (PxDB) P0[7:0], P12, P75, and P85 support debounce function. Debounce clocks of each ports are fx/1, fx/4, and fx/4096. PS030002-0212 PRELIMINARY 56 Z51F3221 Product Specification 9.2.6 P9 Control and Data Register (P9CDR) P9 I/O pin can be independently used as an input or an output through the P92IO. Clearing the bit will make the pin in P92 to input mode, setting the bit will make the pin to output mode. P92 is a bidirectional I/O port. If P92 port is configured as an output port, data can be written to the corresponding bit of the P92. If P92 port is configured as an input port, the data can be read from the corresponding bit of the P92. The P92PU controls the pull-up resister enable/disable of P92 port. The P92OD controls the open-drain enable/disable of P92 port. All bits in the P9CDR register are cleared by a system reset. 9.2.7 Port Function Selection Register (PFSRx) These registers define alternative functions of ports. Please remember that these registers should be set properly for alternative port function. A reset clears the PFSRx register to ‘00H’, which makes all pins to normal I/O ports. PS030002-0212 PRELIMINARY 57 Z51F3221 Product Specification 9.2.8 Register Map Table 9-1 Port Register Map Name Address Dir Default Description P0 80H R/W C0H P0 Data Register P0IO 89H R/W C0H P0 Direction Register P0PU D4H R/W 00H P0 Pull-up Resistor Selection Register P0OD 92H R/W C0H P0 Open-drain Selection Register P0DB E9H R/W 00H P0 Debounce Enable Register P1 88H R/W 08H P1 Data Register P1IO 91H R/W 08H P1 Direction Register P1PU D5H R/W 00H P1 Pull-up Resistor Selection Register P1OD 93H R/W 08H P1 Open-drain Selection Register P1DB EAH R/W 00H P1 Debounce Enable Register P2 90H R/W F8H P2 Data Register P2IO 99H R/W F8H P2 Direction Register P2PU D6H R/W 00H P2 Pull-up Resistor Selection Register P2OD 94H R/W F8H P2 Open-drain Selection Register P3 98H R/W 00H P3 Data Register P3IO A1H R/W 00H P3 Direction Register P3PU D7H R/W 00H P3 Pull-up Resistor Selection Register P3OD 95H R/W 00H P3 Open-drain Selection Register P4 A0H R/W 00H P4 Data Register P4IO B1H R/W 00H P4 Direction Register P4PU DAH R/W 00H P4 Pull-up Resistor Selection Register P4OD 96H R/W 00H P4 Open-drain Selection Register P5 B0H R/W 00H P5 Data Register P5IO B9H R/W 00H P5 Direction Register P5PU DBH R/W 00H P5 Pull-up Resistor Selection Register P5OD A7H R/W 00H P5 Open-drain Selection Register P6 C0H R/W 00H P6 Data Register P6IO C1H R/W 00H P6 Direction Register P6PU DCH R/W 00H P6 Pull-up Resistor Selection Register P6OD BBH R/W 00H P6 Open-drain Selection Register PS030002-0212 PRELIMINARY 58 Z51F3221 Product Specification Table 9-1 Register Map (Continued) Name Address Dir Default Description P7 C8H R/W 00H P7 Data Register P7IO C9H R/W 00H P7 Direction Register P7PU DDH R/W 00H P7 Pull-up Resistor Selection Register P7OD CFH R/W 00H P7 Open-drain Selection Register P8 D8H R/W FFH P8 Data Register P8IO D1H R/W FFH P8 Direction Register P8PU DEH R/W 00H P8 Pull-up Resistor Selection Register P8OD D2H R/W FFH P8 Open-drain Selection Register P9CDR E8H R/W 00H P9 Control and Data Register PFSR0 EDH R/W 00H Port Function Selection Register 0 PFSR1 EEH R/W 00H Port Function Selection Register 1 PFSR2 EFH R/W 00H Port Function Selection Register 2 PFSR3 F1H R/W 00H Port Function Selection Register 3 PFSR4 F2H R/W 00H Port Function Selection Register 4 PFSR5 F3H R/W 00H Port Function Selection Register 5 PFSR6 F4H R/W 00H Port Function Selection Register 6 PFSR7 F5H R/W 00H Port Function Selection Register 7 PFSR8 F6H R/W 00H Port Function Selection Register 8 PS030002-0212 PRELIMINARY 59 Z51F3221 Product Specification 9.3 P0 Port 9.3.1 P0 Port Description P0 is 8-bit I/O port. P0 control registers consist of P0 data register (P0), P0 direction register (P0IO), debounce enable register (P0DB), P0 pull-up resistor selection register (P0PU), and P0 open-drain selection register (P0OD). The P05 function can be selected by the PFSR0[1:0] bits of the PFSR0 register. Refer to the port function selection registers. 9.3.2 Register description for P0 P0 (P0 Data Register) : 80H 7 6 5 4 3 2 1 0 P07 P06 P05 P04 P03 P02 P01 P00 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : C0H P0[7:0] I/O Data P0IO (P0 Direction Register) : 89H 7 6 5 4 3 2 1 0 P07IO P06IO P05IO P04IO P03IO P02IO P01IO P00IO R/W R/W R/W R/W R/W R/W R/W R/W Initial value : C0H P0IO[7:0] P0 Data I/O Direction. 0 Input 1 Output NOTE: EINT0 ~ EINT7 function possible when input P0PU (P0 Pull-up Resistor Selection Register) : D4H 7 6 5 4 3 2 1 0 P07PU P06PU P05PU P04PU P03PU P02PU P01PU P00PU R/W R/W R/W R/W R/W R/W R/W P0PU[7:0] R/W Initial value : 00H Configure Pull-up Resistor of P0 Port 0 Disable 1 Enable P0OD (P0 Open-drain Selection Register) : 92H 7 6 5 4 3 2 1 0 P07OD P06OD P05OD P04OD P03OD P02OD P01OD P00OD R/W R/W R/W R/W R/W R/W R/W R/W Initial value : C0H P0OD[7:0] PS030002-0212 Configure Open-drain of P0 Port 0 Push-pull output 1 Open-drain output PRELIMINARY 60 Z51F3221 Product Specification P0DB (P0 Debounce Enable Register): E9H 7 6 5 4 3 2 1 0 P07DB P06DB P05DB P04DB P03DB P02DB P01DB P00DB R/W R/W R/W R/W R/W R/W R/W P0DB[7:0] R/W Initial value: 00H Configure Debounce of P0 Port 0 Disable 1 Enable NOTES) 1. If the same level is not detected on enabled pin three or four times in a row at the sampling clock, the signal is eliminated as noise. 2. A pulse level should be input for the duration of 3 clock or more to be actually detected as a valid edge. 3. The port debounce is automatically disabled at stop mode and recovered after stop mode release. 4. Refer to the port 1 debounce enable register (P1DB) for the debounce clock of port 0. PS030002-0212 PRELIMINARY 61 Z51F3221 Product Specification 9.4 P1 Port 9.4.1 P1 Port Description P1 is 7-bit I/O port. P1 control registers consist of P1 data register (P1), P1 direction register (P1IO), debounce enable register (P1DB), P1 pull-up resistor selection register (P1PU), and P1 open-drain selection register (P1OD) . Refer to the port function selection registers for the P1 function selection. 9.4.2 Register description for P1 P1 (P1 Data Register) : 88H 7 6 5 4 3 2 1 0 – P16 P15 P14 P13 P12 P11 P10 – R/W R/W R/W R/W R/W R/W P1[6:0] R/W Initial value : 08H I/O Data P1IO (P1 Direction Register) : 91H 7 6 5 4 3 2 1 0 – P16IO P15IO P14IO P13IO P12IO P11IO P10IO – R/W R/W R/W R/W R/W R/W P1IO[6:0] R/W Initial value : 08H P1 Data I/O Direction 0 Input 1 Output NOTE: EINT13 function possible when input P1PU (P1 Pull-up Resistor Selection Register) : D5H 7 6 5 4 3 2 1 0 – P16PU P15PU P14PU P13PU P12PU P11PU P10PU – R/W R/W R/W R/W R/W R/W P1PU[6:0] R/W Initial value : 00H Configure Pull-up Resistor of P1 Port 0 Disable 1 Enable P1OD (P1 Open-drain Selection Register) : 93H 7 6 5 4 3 2 1 0 – P16OD P15OD P14OD P13OD P12OD P11OD P10OD – R/W R/W R/W R/W R/W R/W P1OD[6:0] PS030002-0212 R/W Initial value : 08H Configure Open-drain of P1 Port 0 Push-pull output 1 Open-drain output PRELIMINARY 62 Z51F3221 Product Specification P1DB (P1 Debounce Enable Register) : EAH 7 6 5 4 3 2 1 0 DBCLK1 DBCLK0 P85DB P75DB – P12DB – – R/W R/W R/W R/W – R/W – DBCLK[1:0] – Initial value : 00H Configure Debounce Clock of Port DBCLK1 DBCLK0 Description P85DB P75DB P12DB 0 0 fx/1 0 1 fx/4 1 0 fx/4096 1 1 Reserved Configure Debounce of P85 Port 0 Disable 1 Enable Configure Debounce of P75 Port 0 Disable 1 Enable Configure Debounce of P12 Port 0 Disable 1 Enable NOTES) 1. If the same level is not detected on enabled pin three or four times in a row at the sampling clock, the signal is eliminated as noise. 2. A pulse level should be input for the duration of 3 clock or more to be actually detected as a valid edge. 3. The port debounce is automatically disabled at stop mode and recovered after stop mode release. PS030002-0212 PRELIMINARY 63 Z51F3221 Product Specification 9.5 P2 Port 9.5.1 P2 Port Description P2 is 8-bit I/O port. P2 control registers consist of P2 data register (P2), P2 direction register (P2IO), P2 pull-up resistor selection register (P2PU) and P2 open-drain selection register (P2OD). Refer to the port function selection registers for the P2 function selection. 9.5.2 Register description for P2 P2 (P2 Data Register) : 90H 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : F8H P2[7:0] I/O Data P2IO (P2 Direction Register) : 99H 7 6 5 4 3 2 1 0 P27IO P26IO P25IO P24IO P23IO P22IO P21IO P20IO R/W R/W R/W R/W R/W R/W R/W R/W Initial value : F8H P2IO[7:0] P2 Data I/O Direction 0 Input 1 Output P2PU (P2 Pull-up Resistor Selection Register) : D6H 7 6 5 4 3 2 1 0 P27PU P26PU P25PU P24PU P23PU P22PU P21PU P20PU R/W R/W R/W R/W R/W R/W R/W P2PU[7:0] R/W Initial value : 00H Configure Pull-up Resistor of P2 Port 0 Disable 1 Enable P2OD (P2 Open-drain Selection Register) : 94H 7 6 5 4 3 2 1 0 P27OD P26OD P25OD P24OD P23OD P22OD P21OD P20OD R/W R/W R/W R/W R/W R/W R/W P2OD[7:0] PS030002-0212 R/W Initial value : F8H Configure Open-drain of P2 Port 0 Push-pull output 1 Open-drain output PRELIMINARY 64 Z51F3221 Product Specification 9.6 P3 Port 9.6.1 P3 Port Description P3 is 6-bit I/O port. P3 control registers consist of P3 data register (P3), P3 direction register (P3IO), P3 pull-up resistor selection register (P3PU) and P3 open-drain selection register (P3OD). Refer to the port function selection registers for the P3 function selection. 9.6.2 Register description for P3 P3 (P3 Data Register) : 98H 7 6 5 4 3 2 1 0 – P36 P35 P34 P33 P32 P31 – – R/W R/W R/W R/W R/W R/W P3[6:1] – Initial value : 00H I/O Data P3IO (P3 Direction Register) : A1H 7 6 5 4 3 2 1 0 – P36IO P35IO P34IO P33IO P32IO P31IO – – R/W R/W R/W R/W R/W R/W P3IO[6:1] – Initial value : 00H P3 Data I/O Direction 0 Input 1 Output P3PU (P3 Pull-up Resistor Selection Register) : D7H 7 6 5 4 3 2 1 0 – P36PU P35PU P34PU P33PU P32PU P31PU – – R/W R/W R/W R/W R/W R/W P3PU[6:1] – Initial value : 00H Configure Pull-up Resistor of P3 Port 0 Disable 1 Enable P3OD (P3 Open-drain Selection Register) : 95H 7 6 5 4 3 2 1 0 – P36OD P35OD P34OD P33OD P32OD P31OD – – R/W R/W R/W R/W R/W R/W P3OD[6:1] PS030002-0212 – Initial value : 00H Configure Open-drain of P3 Port 0 Push-pull output 1 Open-drain output PRELIMINARY 65 Z51F3221 Product Specification 9.7 P4 Port 9.7.1 P4 Port Description P4 is 8-bit I/O port. P4 control registers consist of P4 data register (P4), P4 direction register (P4IO), P4 pull-up resistor selection register (P4PU) and P4 open-drain selection register (P4OD). Refer to the port function selection registers for the P4 function selection. 9.7.2 Register description for P4 P4 (P4 Data Register) : A0H 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 R/W R/W R/W R/W R/W R/W R/W P4[7:0] R/W Initial value : 00H I/O Data P4IO (P4 Direction Register) : B1H 7 6 5 4 3 2 1 0 P47IO P46IO P45IO P44IO P43IO P42IO P41IO P40IO R/W R/W R/W R/W R/W R/W R/W P4IO[7:0] R/W Initial value : 00H P4 Data I/O Direction 0 Input 1 Output P4PU (P4 Pull-up Resistor Selection Register) : DAH 7 6 5 4 3 2 1 0 P47PU P46PU P45PU P44PU P43PU P42PU P41PU P40PU R/W R/W R/W R/W R/W R/W R/W P4PU[7:0] R/W Initial value : 00H Configure Pull-up Resistor of P4 Port 0 Disable 1 Enable P4OD (P4 Open-drain Selection Register) : 96H 7 6 5 4 3 2 1 0 P47OD P46OD P45OD P44OD P43OD P42OD P41OD P40OD R/W R/W R/W R/W R/W R/W R/W P4OD[7:0] PS030002-0212 R/W Initial value : 00H Configure Open-drain of P4 Port 0 Push-pull output 1 Open-drain output PRELIMINARY 66 Z51F3221 Product Specification 9.8 P5 Port 9.8.1 P5 Port Description P5 is 8-bit I/O port. P5 control registers consist of P5 data register (P5), P5 direction register (P5IO), P5 pull-up resistor selection register (P5PU) and P5 open-drain selection register (P5OD). Refer to the port function selection registers for the P5 function selection. 9.8.2 Register description for P5 P5 (P5 Data Register) : B0H 7 6 5 4 3 2 1 0 P57 P56 P55 P54 P53 P52 P51 P50 R/W R/W R/W R/W R/W R/W R/W P5[7:0] R/W Initial value : 00H I/O Data P5IO (P5 Direction Register) : B9H 7 6 5 4 3 2 1 0 P57IO P56IO P55IO P54IO P53IO P52IO P51IO P50IO R/W R/W R/W R/W R/W R/W R/W P5IO[7:0] R/W Initial value : 00H P5 Data I/O Direction 0 Input 1 Output P5PU (P5 Pull-up Resistor Selection Register) : DBH 7 6 5 4 3 2 1 0 P57PU P56PU P55PU P54PU P53PU P52PU P51PU P50PU R/W R/W R/W R/W R/W R/W R/W P5PU[7:0] R/W Initial value : 00H Configure Pull-up Resistor of P5 Port 0 Disable 1 Enable P5OD (P5 Open-drain Selection Register) : A7H 7 6 5 4 3 2 1 0 P57OD P56OD P55OD P54OD P53OD P52OD P51OD P50OD R/W R/W R/W R/W R/W R/W R/W P5OD[7:0] PS030002-0212 R/W Initial value : 00H Configure Open-drain of P5 Port 0 Push-pull output 1 Open-drain output PRELIMINARY 67 Z51F3221 Product Specification 9.9 P6 Port 9.9.1 P6 Port Description P6 is 8-bit I/O port. P6 control registers consist of P6 data register (P6), P6 direction register (P6IO), P6 pull-up resistor selection register (P6PU) and P6 open-drain selection register (P6OD). Refer to the port function selection registers for the P6 function selection. 9.9.2 Register description for P6 P6 (P6 Data Register) : C0H 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 R/W R/W R/W R/W R/W R/W R/W P6[7:0] R/W Initial value : 00H I/O Data P6IO (P6 Direction Register) : C1H 7 6 5 4 3 2 1 0 P67IO P66IO P65IO P64IO P63IO P62IO P61IO P60IO R/W R/W R/W R/W R/W R/W R/W P6IO[7:0] R/W Initial value : 00H P6 Data I/O Direction 0 Input 1 Output P6PU (P6 Pull-up Resistor Selection Register) : DCH 7 6 5 4 3 2 1 0 P67PU P66PU P65PU P64PU P63PU P62PU P61PU P60PU R/W R/W R/W R/W R/W R/W R/W P6PU[7:0] R/W Initial value : 00H Configure Pull-up Resistor of P6 Port 0 Disable 1 Enable P6OD (P6 Open-drain Selection Register) : BBH 7 6 5 4 3 2 1 0 P67OD P66OD P65OD P64OD P63OD P62OD P61OD P60OD R/W R/W R/W R/W R/W R/W R/W P6OD[7:0] PS030002-0212 R/W Initial value : 00H Configure Open-drain of P6 Port 0 Push-pull output 1 Open-drain output PRELIMINARY 68 Z51F3221 Product Specification 9.10 P7 Port 9.10.1 P7 Port Description P7 is 8-bit I/O port. P7 control registers consist of P7 data register (P7), P7 direction register (P7IO), P7 pull-up resistor selection register (P7PU) and P7 open-drain selection register (P7OD). Refer to the port function selection registers for the P7 function selection. 9.10.2 Register description for P7 P7 (P7 Data Register) : C8H 7 6 5 4 3 2 1 0 P77 P76 P75 P74 P73 P72 P71 P70 R/W R/W R/W R/W R/W R/W R/W P7[7:0] R/W Initial value : 00H I/O Data P7IO (P7 Direction Register) : C9H 7 6 5 4 3 2 1 0 P77IO P76IO P75IO P74IO P73IO P72IO P71IO P70IO R/W R/W R/W R/W R/W R/W R/W P7IO[7:0] R/W Initial value : 00H P7 Data I/O Direction 0 Input 1 Output NOTE: EINT10 function possible when input P7PU (P7 Pull-up Resistor Selection Register) : DDH 7 6 5 4 3 2 1 0 P77PU P76PU P75PU P74PU P73PU P72PU P71PU P70PU R/W R/W R/W R/W R/W R/W R/W P7PU[7:0] R/W Initial value : 00H Configure Pull-up Resistor of P7 Port 0 Disable 1 Enable P7OD (P7 Open-drain Selection Register) : CFH 7 6 5 4 3 2 1 0 P77OD P76OD P75OD P74OD P73OD P72OD P71OD P70OD R/W R/W R/W R/W R/W R/W R/W P7OD[7:0] PS030002-0212 R/W Initial value : 00H Configure Open-drain of P7 Port 0 Push-pull output 1 Open-drain output PRELIMINARY 69 Z51F3221 Product Specification 9.11 P8 Port 9.11.1 P8 Port Description P8 is 8-bit I/O port. P8 control registers consist of P8 data register (P8), P8 direction register (P8IO), P8 pull-up resistor selection register (P8PU) and P8 open-drain selection register (P8OD). Refer to the port function selection registers for the P8 function selection. 9.11.2 Register description for P8 P8 (P8 Data Register) : D8H 7 6 5 4 3 2 1 0 P87 P86 P85 P84 P83 P82 P81 P80 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH P8[7:0] I/O Data P8IO (P8 Direction Register) : D1H 7 6 5 4 3 2 1 0 P87IO P86IO P85IO P84IO P83IO P82IO P81IO P80IO R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH P8IO[7:0] P8 Data I/O Direction 0 Input 1 Output NOTE: EINT10 function possible when input P8PU (P8 Pull-up Resistor Selection Register) : DEH 7 6 5 4 3 2 1 0 P87PU P86PU P85PU P84PU P83PU P82PU P81PU P80PU R/W R/W R/W R/W R/W R/W R/W P8PU[7:0] R/W Initial value : 00H Configure Pull-up Resistor of P8 Port 0 Disable 1 Enable P8OD (P8 Open-drain Selection Register) : D2H 7 6 5 4 3 2 1 0 P87OD P86OD P85OD P84OD P83OD P82OD P81OD P80OD R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH P8OD[7:0] PS030002-0212 Configure Open-drain of P8 Port 0 Push-pull output 1 Open-drain output PRELIMINARY 70 Z51F3221 Product Specification 9.12 P9 Port 9.12.1 P9 Port Description P9 is 1-bit I/O port. P9 control registers consist of P9 control and data register (P9CDR). 9.12.2 Register description for P9 P9CDR (P9 Control and Data Register) : E8H 7 6 5 4 3 2 1 0 PFSR90 – – – P92OD P92PU P92IO P92 R/W – – – R/W R/W R/W PFSR90 P92OD P92PU P92IO P92 PS030002-0212 R/W Initial value : 00H EINT10 Position Select 0 P75 1 P85 Configure Open-drain of P9 Port 0 Disable 1 Enable Configure Pull-up Resistor of P9 Port 0 Disable 1 Enable P9 Data I/O Direction 0 Input 1 Output I/O Data PRELIMINARY 71 Z51F3221 Product Specification 9.13 Port Function 9.13.1 Port Function Description Port function control registers consist of Port function selection register 0 ~ 8. (PFSR0 ~ PFSR8). 9.13.2 Register description for PFSR0 ~ PFSR8 PFSR0 (Port Function Selection Register 0) : EDH 7 6 5 4 3 2 1 0 PFSR07 PFSR06 PFSR05 PFSR04 PFSR03 PFSR02 PFSR01 PFSR00 R/W R/W R/W R/W R/W R/W R/W PFSR0[7:6] R/W Initial value : 00H P15 Function Select PFSR07 PFSR06 Description 0 PFSR05 PFSR0[4:3] 0 Port 0 1 SCK-in Function 1 0 SCK-out Function 1 1 Not used P14 Function select 0 Port 1 SO Function P13 Function Select PFSR04 PFSR03 Description PFSR02 PFSR0[1:0] 0 0 0 1 Port BUZO Function 1 0 EC3 Function 1 1 Not used P12 Function Select 0 Port (EINT13 function possible when input) 1 PWM3O/T3O Function P05 Function Select PFSR01 PFSR00 Description PS030002-0212 0 0 Port 0 1 BUZO Function 1 0 EC3 Function 1 1 Not used PRELIMINARY 72 Z51F3221 Product Specification PFSR1 (Port Function Selection Register 1) : EEH 7 6 5 4 3 2 1 0 PFSR17 PFSR16 PFSR15 PFSR14 PFSR13 PFSR12 PFSR11 PFSR10 R/W R/W R/W R/W R/W R/W R/W PFSR17 PFSR16 PFSR15 PFSR14 PFSR13 PFSR12 PFSR11 PFSR10 PS030002-0212 R/W Initial value : 00H P26 Function select 0 Port 1 AN6 Function P25 Function Select 0 Port 1 AN5 Function P24 Function select 0 Port 1 AN4 Function P23 Function Select 0 Port 1 AN3 Function P22 Function select 0 Port 1 AN2 Function P21 Function Select 0 Port 1 AN1 Function P20 Function select 0 Port 1 AN0 Function P16 Function Select 0 Port 1 SI Function PRELIMINARY 73 Z51F3221 Product Specification PFSR2 (Port Function Selection Register 2) : EFH 7 6 5 4 3 2 1 0 PFSR27 PFSR26 PFSR25 PFSR24 PFSR23 PFSR22 PFSR21 PFSR20 R/W R/W R/W R/W R/W R/W R/W PFSR27 PFSR26 PFSR25 PFSR24 PFSR23 PFSR22 PFSR2[1:0] R/W Initial value : 00H P43 Function select 0 Port 1 COM5/SEG3 Function P42 Function Select 0 Port 1 COM4/SEG2 Function P41 Function select 0 Port 1 COM3/SEG1 Function P40 Function Select 0 Port 1 COM2/SEG0 Function P36 Function select 0 Port 1 COM1 Function P35 Function Select 0 Port 1 COM0 Function P27 Function Select PFSR21 PFSR20 Description 0 PS030002-0212 0 Port 0 1 AN7 Function 1 0 LVIREF Function 1 1 Not used PRELIMINARY 74 Z51F3221 Product Specification PFSR3 (Port Function Selection Register 3) : F1H 7 6 5 4 3 2 1 0 PFSR37 PFSR36 PFSR35 PFSR34 PFSR33 PFSR32 PFSR31 PFSR30 R/W R/W R/W R/W R/W R/W R/W PFSR37 PFSR36 PFSR35 PFSR34 PFSR33 PFSR32 PFSR31 PFSR30 PS030002-0212 R/W Initial value : 00H P53 Function select 0 Port 1 SEG11 Function P52 Function Select 0 Port 1 SEG10 Function P51 Function select 0 Port 1 SEG9 Function P50 Function Select 0 Port 1 SEG8 Function P47 Function select 0 Port 1 SEG7 Function P46 Function Select 0 Port 1 SEG6 Function P45 Function select 0 Port 1 COM7/SEG5 Function P44 Function Select 0 Port 1 COM6/SEG4 Function PRELIMINARY 75 Z51F3221 Product Specification PFSR4 (Port Function Selection Register 4) : F2H 7 6 5 4 3 2 1 0 PFSR47 PFSR46 PFSR45 PFSR44 PFSR43 PFSR42 PFSR41 PFSR40 R/W R/W R/W R/W R/W R/W R/W PFSR47 PFSR46 PFSR45 PFSR44 PFSR43 PFSR42 PFSR41 PFSR40 PS030002-0212 R/W Initial value : 00H P63 Function select 0 Port 1 SEG19 Function P62 Function Select 0 Port 1 SEG18 Function P61 Function select 0 Port 1 SEG17 Function P60 Function Select 0 Port 1 SEG16 Function P57 Function select 0 Port 1 SEG15 Function P56 Function Select 0 Port 1 SEG14 Function P55 Function select 0 Port 1 SEG13 Function P54 Function Select 0 Port 1 SEG12 Function PRELIMINARY 76 Z51F3221 Product Specification PFSR5 (Port Function Selection Register 5) : F3H 7 6 5 4 3 2 1 0 PFSR57 PFSR56 PFSR55 PFSR54 PFSR53 PFSR52 PFSR51 PFSR50 R/W R/W R/W R/W R/W R/W R/W PFSR5[7:6] R/W Initial value : 00H P72 Function Select PFSR57 PFSR56 Description PFSR55 PFSR54 PFSR53 PFSR52 PFSR51 PFSR50 PS030002-0212 0 0 Port 0 1 SEG26 Function 1 0 REM Function 1 1 Not used P71 Function select 0 Port 1 SEG25 Function P70 Function Select 0 Port 1 SEG24 Function P67 Function select 0 Port 1 SEG23 Function P66 Function Select 0 Port 1 SEG22 Function P65 Function select 0 Port 1 SEG21 Function P64 Function Select 0 Port 1 SEG20 Function PRELIMINARY 77 Z51F3221 Product Specification PFSR6 (Port Function Selection Register 6) : F4H 7 6 5 4 3 2 1 0 PFSR67 PFSR66 PFSR65 PFSR64 PFSR63 PFSR62 PFSR61 PFSR60 R/W R/W R/W R/W R/W R/W R/W PFSR6[7:6] R/W Initial value : 00H P76 Function Select PFSR67 PFSR66 Description PFSR6[5:4] 0 0 Port 0 1 SEG30 Function 1 0 TXD Function 1 1 Not used P75 Function Select PFSR65 PFSR64 Description PFSR6[3:2] 0 0 Port (EINT10 function possible when input) 0 1 SEG29 Function 1 0 ACK-in Function 1 1 ACK-out Function P74 Function Select PFSR63 PFSR62 Description PFSR6[1:0] 0 0 Port 0 1 SEG28 Function 1 0 EC0 Function 1 1 Not used P73 Function Select PFSR61 PFSR60 Description 0 PS030002-0212 0 Port 0 1 SEG27 Function 1 0 T0O/PWM0O Function 1 1 Not used PRELIMINARY 78 Z51F3221 Product Specification PFSR7 (Port Function Selection Register 7) : F5H 7 6 5 4 3 2 1 0 PFSR77 PFSR76 PFSR75 PFSR74 PFSR73 PFSR72 PFSR71 PFSR70 R/W R/W R/W R/W R/W R/W R/W PFSR7[7:6] R/W Initial value : 00H P83 Function Select PFSR77 PFSR76 Description PFSR7[5:4] 0 0 Port 0 1 SEG35 Function 1 0 T0O/PWM0O Function 1 1 Not used P82 Function Select PFSR75 PFSR74 Description PFSR73 PFSR72 PFSR7[1:0] 0 0 Port 0 1 SEG34 Function 1 0 REM Function 1 1 Not used P81 Function Select 0 Port 1 SEG33 P80 Function Select 0 Port 1 SEG32 P77 Function Select PFSR71 PFSR70 Description PS030002-0212 0 0 Port 0 1 SEG31 Function 1 0 RXD Function 1 1 Not used PRELIMINARY 79 Z51F3221 Product Specification PFSR8 (Port Function Selection Register 8) : F6H 7 6 5 4 3 2 1 0 PFSR87 PFSR86 PFSR85 PFSR84 PFSR83 PFSR82 PFSR81 PFSR80 R/W R/W R/W R/W R/W R/W R/W PFSR8[7:6] R/W Initial value : 00H P87 Function Select PFSR87 PFSR86 Description PFSR8[5:4] 0 0 Port 0 1 SEG39 Function 1 0 RXD Function 1 1 Not used P86 Function Select PFSR85 PFSR84 Description PFSR8[3:2] 0 0 Port 0 1 SEG38 Function 1 0 TXD Function 1 1 Not used P85 Function Select PFSR83 PFSR82 Description PFSR8[1:0] 0 0 Port (EINT10 function possible when input) 0 1 SEG37 Function 1 0 ACK-in Function 1 1 ACK-out Function P84 Function Select PFSR81 PFSR80 Description PS030002-0212 0 0 Port 0 1 SEG36 Function 1 0 EC0 Function 1 1 Not used PRELIMINARY 80 Z51F3221 Product Specification 10. Interrupt Controller 10.1 Overview The Z51F3221 MCU supports up to 23 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. They can also have four levels of priority assigned to them. The non-maskable interrupt source is always enabled with a higher priority than any other interrupt source, and is not controllable by software. The interrupt controller has following features: - Receive the request from 23 interrupt source - 6 group priority - 4 priority levels - Multi Interrupt possibility - If the requests of different priority levels are received simultaneously, the request of higher priority level is served first. - Each interrupt source can be controlled by EA bit and each IEx bit - Interrupt latency: 3~9 machine cycles in single interrupt system The non-maskable interrupt is always enabled. The maskable interrupts are enabled through four pair of interrupt enable registers (IE, IE1, IE2, IE3). Each bit of IE, IE1, IE2, IE3 register individually enables/disables the corresponding interrupt source. Overall control is provided by bit 7 of IE (EA). When EA is set to ‘0’, all interrupts are disabled: when EA is set to ‘1’, interrupts are individually enabled or disabled through the other bits of the interrupt enable registers. The EA bit is always cleared to ‘0’ jumping to an interrupt service vector and set to ‘1’ executing the [RETI] instruction. The Z51F3221 MCU supports a four-level priority scheme. Each maskable interrupt is individually assigned to one of four priority levels according to IP and IP1. Default interrupt mode is level-trigger mode basically, but if needed, it is possible to change to edge-trigger mode. Table 10-1 shows the Interrupt Group Priority Level that is available for sharing interrupt priority. Priority of a group is set by two bits of interrupt priority registers (one bit from IP, another one from IP1). Interrupt service routine serves higher priority interrupt first. If two requests of different priority levels are received simultaneously, the request of higher priority level is served prior to the lower one. Table 10-1 Interrupt Group Priority Level Interrupt Group Highest 0 (Bit0) Interrupt 0 Interrupt 6 Interrupt 12 Interrupt 18 1 (Bit1) Interrupt 1 Interrupt 7 Interrupt 13 Interrupt 19 2 (Bit2) Interrupt 2 Interrupt 8 Interrupt 14 Interrupt 20 3 (Bit3) Interrupt 3 Interrupt 9 Interrupt 15 Interrupt 21 4 (Bit4) Interrupt 4 Interrupt 10 Interrupt 16 Interrupt 22 5 (Bit5) Interrupt 5 Interrupt 11 Interrupt 17 Interrupt 23 PS030002-0212 Lowest PRELIMINARY Highest Lowest 81 Z51F3221 Product Specification 10.2 External Interrupt The external interrupt on INT1, INT2 and INT5 pins receive various interrupt request depending on the external interrupt edge register 0 (EIEDGE0), external interrupt edge register 1 (EIEDGE1), external interrupt polarity register 0 (EIPOL0) and external interrupt polarity register 1 (EIPOL1) as shown in Figure 10.1. Also each external interrupt source has enable/disable bits. The External interrupt flag register 0 (EIFLAG0) and external interrupt flag register 1 (EIFLAG1) provides the status of external interrupts. EINT10 Pin FLAG10 INT1 Interrupt FLAG13 INT2 Interrupt 2 EINT13 Pin 2 EIEDGE1, EIPOL1 EINT0 Pin EINT1 Pin EINT2 Pin EINT3 Pin EINT4 Pin EINT5 Pin EINT6 Pin EINT7 Pin FLAG0 2 FLAG1 2 FLAG2 2 FLAG3 2 FLAG4 2 INT5 Interrupt FLAG5 2 FLAG6 2 FLAG7 2 EIEDGE0, EIPOL0 Figure 10.1 External Interrupt Description PS030002-0212 PRELIMINARY 82 Z51F3221 Product Specification 10.3 Block Diagram EIEDGE1 EINT10 EINT13 IE FLAG10 EIFLAG1.0 EIENAB 1.0 FLAG13 EIFLAG1.1 EIENAB 1.1 EINT0 FLAG0 EIFLAG0.0 EIENAB 0.0 EINT1 FLAG1 EIFLAG0.1 EIENAB 0.1 FLAG2 EIFLAG0.2 EIENAB 0.2 EINT3 FLAG3 EIFLAG0.3 EIENAB 0.3 EINT4 FLAG4 EIFLAG0.4 EIENAB 0.4 EINT5 FLAG5 EIFLAG0.5 EIENAB 0.5 EINT6 FLAG6 EIFLAG0.6 EIENAB 0.6 EINT7 FLAG 7 EIFLAG0.7 EIENAB 0.7 EINT2 IP IP1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 IE1 8 EIEDGE0 UART Rx 9 UART Tx 10 SIO 11 SIOIFR 8 9 10 11 IE2 Timer 0 Overflow T0OVIFR 12 Timer 0 T0IFR 13 Timer 1 T1IFR 14 Timer 2 T2IFR 15 Timer 3 T3IFR 16 T3OVIFR 17 Timer 3 Overflow IE3 ADC 18 ADCIFR 19 WT WDT BIT WTIFR 20 WDTIFR 21 BITIFR 22 23 12 13 14 15 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 Priority High 1 2 3 4 5 6 7 8 9 10 11 Level0 Level1 Level2 Level3 Release Stop/Sleep 12 13 EA 14 15 16 17 18 19 20 21 22 23 Priority Low Figure 10.2 Block Diagram of Interrupt NOTES) 1. The release signal for stop/idle mode may be generated by all interrupt sources which are enabled without reference to the priority level. 2. An interrupt request is delayed while data are written to IE, IE1, IE2, IE3, IP, IP1, and PCON register. PS030002-0212 PRELIMINARY 83 Z51F3221 Product Specification 10.4 Interrupt Vector Table The interrupt controller supports 24 interrupt sources as shown in the Table 10-2. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their own priority order. Table 10-2 Interrupt Vector Address Table Interrupt Source Symbol Hardware Reset External Interrupt 10 External Interrupt 13 External Interrupt 0 - 7 UART Rx Interrupt UART Tx Interrupt SIO Interrupt T0 Overflow Interrupt T0 Match Interrupt T1 Match Interrupt T2 Match Interrupt T3 Match Interrupt T3 Overflow Interrupt ADC Interrupt WT Interrupt WDT Interrupt BIT Interrupt - RESETB INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT8 INT9 INT10 INT11 INT12 INT13 INT14 INT15 INT16 INT17 INT18 INT19 INT20 INT21 INT22 INT23 Interrupt Enable Bit 0 0 IE.0 IE.1 IE.2 IE.3 IE.4 IE.5 IE1.0 IE1.1 IE1.2 IE1.3 IE1.4 IE1.5 IE2.0 IE2.1 IE2.2 IE2.3 IE2.4 IE2.5 IE3.0 IE3.1 IE3.2 IE3.3 IE3.4 IE3.5 Polarity Mask Vector Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Non-Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable 0000H 0003H 000BH 0013H 001BH 0023H 002BH 0033H 003BH 0043H 004BH 0053H 005BH 0063H 006BH 0073H 007BH 0083H 008BH 0093H 009BH 00A3H 00ABH 00B3H 00BBH For maskable interrupt execution, EA bit must set ‘1’ and specific interrupt must be enabled by writing ‘1’ to associated bit in the IEx. If an interrupt request is received, the specific interrupt request flag is set to ‘1’. And it remains ‘1’ until CPU accepts interrupt. If the interrupt is served, the interrupt request flag will be cleared automatically. 10.5 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the PC at stack. For the interrupt service routine, the interrupt controller gives the address of LJMP instruction to CPU. Since the end of the execution of current instruction, it needs 3~9 machine cycles to go to the interrupt service routine. The interrupt service task is terminated by the interrupt return instruction [RETI]. Once an interrupt request is generated, the following process is performed. PS030002-0212 PRELIMINARY 84 Z51F3221 Product Specification 1 IE.EA Flag  0 2 Program Counter low Byte SP  SP + 1 M(SP)  (PCL) Saves PC value in order to continue process again after executing ISR 3 Program Counter high Byte SP  SP + 1 M(SP)  (PCH) 4 Interrupt Vector Address occurrence (Interrupt Vector Address) 5 ISR(Interrupt Service Routine) move, execute 6 Return from ISR RETI 7 Program Counter high Byte recovery (PCH)  (SP-1) 8 Program Counter low Byte recovery (PCL)  (SP-1) 9 IE.EA Flag  1 10 Main Program execution Figure 10.3 Interrupt Vector Address Table PS030002-0212 PRELIMINARY 85 Z51F3221 Product Specification 10.6 Effective Timing after Controlling Interrupt Bit Case a) Control Interrupt Enable Register (IE, IE1, IE2, IE3) Interrupt Enable Register command After executing IE set/clear, enable register is effective. Next Instruction Next Instruction Figure 10.4 Effective Timing of Interrupt Enable Register Case b) Interrupt flag Register Interrupt Flag Register Command Next Instruction After executing next instruction, interrupt flag result is effective. Next Instruction Figure 10.5 Effective Timing of Interrupt Flag Register PS030002-0212 PRELIMINARY 86 Z51F3221 Product Specification 10.7 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is served first. If more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware. However, for special features, multi-interrupt processing can be executed by software. Main Program Service INT1 ISR INT0 ISR Occur INT1 Interrupt Occur INT0 Interrupt RETI RETI Figure 10.6 Effective Timing of Interrupt Figure 10.6 shows an example of multi-interrupt processing. While INT1 is served, INT0 which has higher priority than INT1 is occurred. Then INT0 is served immediately and then the remain part of INT1 service routine is executed. If the priority level of INT0 is same or lower than INT1, INT0 will be served after the INT1 service has completed. An interrupt service routine may be only interrupted by an interrupt of higher priority and, if two interrupts of different priority occur at the same time, the higher level interrupt will be served first. An interrupt cannot be interrupted by another interrupt of the same or a lower priority level. If two interrupts of the same priority level occur simultaneously, the service order for those interrupts is determined by the scan order. PS030002-0212 PRELIMINARY 87 Z51F3221 Product Specification 10.8 Interrupt Enable Accept Timing Max. 4 Machine Cycle 4 Machine Cycle System Clock Interrupt goes Active Interrupt Latched Interrupt Processing : LCALL & LJMP Interrupt Routine Figure 10.7 Interrupt Response Timing Diagram 10.9 Interrupt Service Routine Address Basic Interval Timer Vector Table Address Basic Interval Timer Service Routine Address 00B3H 01H 0125H 0EH 00B4H 25H 0126H 2EH Figure 10.8 Correspondence between Vector Table Address and the Entry Address of ISP 10.10 Saving/Restore General-Purpose Registers INTxx : PUSH PUSH PUSH PUSH PUSH · · PSW DPL DPH B ACC Main Task Interrupt Service Task Saving Register Interrupt_Processing: ∙ ∙ POP POP POP POP POP RETI Restoring Register ACC B DPH DPL PSW Figure 10.9 Saving/Restore Process Diagram and Sample Source PS030002-0212 PRELIMINARY 88 Z51F3221 Product Specification 10.11 Interrupt Timing Interrupt sampled here CLP2 CLP1 CLP2 C1P1 C1P2 C2P1 C2P2 SCLK INT_SRC INTR_ACK LAST_CYC INTR_LCALL 8-Bit interrupt Vector INT_VEC {8’h00, INT_VEC} PROGA Figure 10.10 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction Interrupt sources are sampled at the last cycle of a command. If an interrupt source is detected the lower 8-bit of interrupt vector (INT_VEC) is decided. M8051W core makes interrupt acknowledge at the first cycle of a command, and executes long call to jump to interrupt service routine. st st NOTE) command cycle CLPx: L=Last cycle, 1=1 cycle or 1 phase, 2=2 nd cycle or 2 nd phase 10.12 Interrupt Register Overview 10.12.1 Interrupt Enable Register (IE, IE1, IE2, IE3) Interrupt enable register consists of global interrupt control bit (EA) and peripheral interrupt control bits. Total 24 peripherals are able to control interrupt. 10.12.2 Interrupt Priority Register (IP, IP1) The 24 interrupts are divided into 6 groups which have each 4 interrupt sources. A group can be assigned 4 levels interrupt priority using interrupt priority register. Level 3 is the highest priority, while level 0 is the lowest priority. After a reset IP and IP1 are cleared to ‘00H’. If interrupts have the same priority level, lower number interrupt is served first. PS030002-0212 PRELIMINARY 89 Z51F3221 Product Specification 10.12.3 External Interrupt Flag Register (EIFLAG0, EIFLAG1) The external interrupt flag register 0 (EIFLAG0) and external interrupt flag register 1 (EIFLAG1) are set to ‘1’ when the external interrupt generating condition is satisfied. The flag is cleared when the interrupt service routine is executed. Alternatively, the flag can be cleared by writing ‘0’ to it. 10.12.4 External Interrupt Edge Register (EIEDGE0, EIEDGE1) The external interrupt edge register 0 (EIEDGE0) and external interrupt edge register 1 (EIEDGE1) determine which type of interrupt will be used, edge sensitive or level sensitive. Initially, default value sets level sensitive interrupt. For level sensitive interrupt, write ‘0’ to the related bit. For edge sensitive interrupt, write ‘1’ to the related bit. 10.12.5 External Interrupt Polarity Register (EIPOL0, EIPOL1) According to EIEDGE0 and EIEDGE1 registers, the external interrupt polarity register 0 (EIPOL0 ) and external interrupt polarity register 1 (EIPOL1) have different meaning. If level sensitive interrupt is selected, EIPOL0 and EIPOL1 determine the level of interrupt (high or low level). If edge sensitive interrupt is selected, EIPOL0 and EIPOL1 determine the edge of interrupt (rising or falling edge). 10.12.6 External Interrupt Enable Register (EIENAB0, EIENAB1) When the external interrupt enable register 0 (EIENAB0) and external interrupt enable register 1 (EIENAB1) register are written to ‘1’, the corresponding external pin interrupt is enabled. PS030002-0212 PRELIMINARY 90 Z51F3221 Product Specification 10.12.7 Register Map Table 10-3 Interrupt Register Map Name Address Dir Default Description IE A8H R/W 00H Interrupt Enable Register IE1 A9H R/W 00H Interrupt Enable Register 1 IE2 AAH R/W 00H Interrupt Enable Register 2 IE3 ABH R/W 00H Interrupt Enable Register 3 IP B8H R/W 00H Interrupt Polarity Register IP1 F8H R/W 00H Interrupt Polarity Register 1 EIFLAG0 ADH R/W 00H External Interrupt Flag Register 0 EIEDGE0 AEH R/W 00H External Interrupt Edge Register 0 EIPOL0 AFH R/W 00H External Interrupt Polarity Register 0 EIENAB0 ACH R/W 00H External Interrupt Enable Register 0 EIFLAG1 A4H R/W 00H External Interrupt Flag Register 1 EIEDGE1 A5H R/W 00H External Interrupt Edge Register 1 EIPOL1 A6H R/W 00H External Interrupt Polarity Register 1 EIENAB1 A3H R/W 00H External Interrupt Enable Register 1 10.13 Interrupt Register Description The interrupt register is used for controlling interrupt functions. Also it has external interrupt control registers. The interrupt register consists of interrupt enable register (IE), interrupt enable register 1 (IE1), interrupt enable register 2 (IE2) and interrupt enable register 3 (IE3). For external interrupt, it consists of external interrupt flag register 0 (EIFLAG0), external interrupt edge register 0 (EIEDGE0), external interrupt polarity register 0 (EIPOL0), external interrupt enable register 0 (EIENAB0), external interrupt flag register 1 (EIFLAG1), external interrupt edge register 1 (EIEDGE1), external interrupt polarity register 1 (EIPOL1) and external interrupt enable register 1 (EIENAB1). PS030002-0212 PRELIMINARY 91 Z51F3221 Product Specification 10.13.1 Register Description for Interrupt IE (Interrupt Enable Register) : A8H 7 6 5 4 3 2 1 0 EA – INT5E – – INT2E INT1E – R/W – R/W – – R/W R/W EA – Initial value : 00H Enable or Disable All Interrupt bits INT5E 0 All Interrupt disable 1 All Interrupt enable Enable or Disable External Interrupt 0 ~ 7 (EINT0 ~ EINT7) INT2E 0 Disable 1 Enable Enable or Disable External Interrupt 13 (EINT13) INT1E 0 Disable 1 Enable Enable or Disable External Interrupt 10 (EINT10) 0 Disable 1 Enable IE1 (Interrupt Enable Register 1): A9H 7 6 5 4 3 2 1 0 – – INT11E INT10E INT9E – – – – – R/W R/W R/W – – INT11E INT10E INT9E PS030002-0212 – Initial value: 00H Enable or Disable SIO Interrupt 0 Disable 1 Enable Enable or Disable UART Tx Interrupt 0 Disable 1 Enable Enable or Disable UART Rx Interrupt 0 Disable 1 Enable PRELIMINARY 92 Z51F3221 Product Specification IE2 (Interrupt Enable Register 2) : AAH 7 6 5 4 3 2 1 0 – – INT17E INT16E INT15E INT14E INT13E INT12E – – R/W R/W R/W R/W R/W INT17E R/W Initial value : 00H Enable or Disable Timer 3 Overflow Interrupt INT16E 0 Disable 1 Enable Enable or Disable Timer 3 Interrupt INT15E 0 Disable 1 Enable Enable or Disable Timer 2 Interrupt INT14E 0 Disable 1 Enable Enable or Disable Timer 1 Interrupt INT13E 0 Disable 1 Enable Enable or Disable Timer 0 Interrupt INT12E 0 Disable 1 Enable Enable or Disable Timer 0 Overflow Interrupt 0 Disable 1 Enable IE3 (Interrupt Enable Register 3) : ABH 7 6 5 4 3 2 1 0 – – – INT22E INT21E INT20E – INT18E – – – R/W R/W R/W – INT22E INT21E INT20E INT18E PS030002-0212 R/W Initial value : 00H Enable or Disable BIT Interrupt 0 Disable 1 Enable Enable or Disable WDT Interrupt 0 Disable 1 Enable Enable or Disable WT Interrupt 0 Disable 1 Enable Enable or Disable ADC Interrupt 0 Disable 1 Enable PRELIMINARY 93 Z51F3221 Product Specification IP (Interrupt Priority Register) : B8H 7 6 5 4 3 2 1 0 – – IP5 IP4 IP3 IP2 IP1 IP0 – – R/W R/W R/W R/W R/W R/W Initial value : 00H IP1 (Interrupt Priority Register 1) : F8H 7 6 5 4 3 2 1 0 – – IP15 IP14 IP13 IP12 IP11 IP10 – – R/W R/W R/W R/W R/W IP[5:0], IP1[5:0] R/W Initial value : 00H Select Interrupt Group Priority IP1x IPx Description 0 0 level 0 (lowest) 0 1 level 1 1 0 level 2 1 1 level 3 (highest) EIFLAG0 (External Interrupt Flag Register 0) : ADH 7 6 5 4 3 2 1 0 FLAG7 FLAG6 FLAG5 FLAG4 FLAG3 FLAG2 FLAG1 FLAG0 R/W R/W R/W R/W R/W R/W R/W EIFLAG0[7:0] R/W Initial value : 00H When an External Interrupt is occurred, the flag becomes ‘1’. The flag is cleared only by writing ‘0’ to the bit. So, the flag should be cleared by software. 0 External Interrupt 0 ~ 7 not occurred 1 External Interrupt 0 ~ 7 occurred EIEDGE0 (External Interrupt Edge Register 0): AEH 7 6 5 4 3 2 1 0 EDGE7 EDGE6 EDGE5 EDGE4 EDGE3 EDGE2 EDGE1 EDGE0 R/W- R/W- R/W R/W R/W R/W R/W EIEDGE0[7:0] PS030002-0212 R/W Initial value : 00H Determines which type of interrupt will be used; edge sensitive or level sensitive. 0 Level (default) 1 Edge PRELIMINARY 94 Z51F3221 Product Specification EIPOL0 (External Interrupt Polarity Register 0): AFH 7 6 5 4 3 2 1 0 POL7 POL6 POL5 POL4 POL3 POL2 POL1 POL0 R/W R/W R/W R/W R/W R/W R/W EIPOL0[7:0] R/W Initial value: 00H According to EIEDGE0, external interrupt polarity register has different meaning. If EIEDGE0 is set to select level sensitive interrupt, EIPOL0 determines high or low level interrupt. If EIEDGE0 is set to select edge sensitive interrupt, EIPOL0 determines rising or falling edge interrupt. Level case: 0 When High level, Interrupt occurred (Default) 1 When Low level, Interrupt occurred Edge case: 0 When Rising edge, Interrupt occurred (Default) 1 When Falling edge, Interrupt occurred EIENAB0 (External Interrupt Enable Register 0) : ACH 7 6 5 4 3 2 1 0 ENAB7 ENAB6 ENAB5 ENAB4 ENAB3 ENAB2 ENAB1 ENAB0 R/W- R/W R/W R/W R/W R/W R/W EIENAB0[7:0] R/W Initial value : 00H Control External Interrupt 0~7 (P0[7:0]) 0 Disable (Default) 1 Enable EIFLAG1 (External Interrupt Flag Register 1) : A4H 7 6 5 4 3 2 1 0 – – – – – – FLAG13 FLAG10 – – – – – – R/W EIFLAG1[1:0] R/W Initial value : 00H When an External Interrupt is occurred, the flag becomes ‘1’. The flag is cleared only by writing ‘0’ to the bit or automatically cleared by INT_ACK signal. 0 External Interrupt 10 and 13 not occurred 1 External Interrupt 10 and 13 occurred EIEDGE1 (External Interrupt Edge Register 1) : A5H 7 6 5 4 3 2 1 0 – – – – – – EDGE13 EDGE10 – – – – – – R/W EIEDGE1[1:0] PS030002-0212 R/W Initial value : 00H Determines which type of interrupt will be used; edge sensitive or level sensitive. 0 Level (default) 1 Edge PRELIMINARY 95 Z51F3221 Product Specification EIPOL1 (External Interrupt Polarity Register 1) : A6H 7 6 5 4 3 2 1 0 – – – – – – POL13 POL10 – – – – – – R/W EIPOL1[1:0] R/W Initial value : 00H According to EIEDGE1, external interrupt polarity register has different meaning. If EIEDGE1 is set to select level sensitive interrupt, EIPOL1 determines high or low level interrupt. If EIEDGE1 is set to select edge sensitive interrupt, EIPOL1 determines rising or falling edge interrupt. Level case: 0 When High level, Interrupt occurred (Default) 1 When Low level, Interrupt occurred Edge case: 0 When Rising edge, Interrupt occurred (Default) 1 When Falling edge, Interrupt occurred EIENAB1 (External Interrupt Enable Register 1) : A3H 7 6 5 4 3 2 1 0 – – – – – – ENAB13 ENAB10 – – – – – – R/W EIENAB1[1:0] PS030002-0212 R/W Initial value : 00H Control External Interrupt 10 and 13 (P85/P75, P12) 0 Disable (Default) 1 Enable PRELIMINARY 96 Z51F3221 Product Specification 11. Peripheral Hardware 11.1 Clock Generator 11.1.1 Overview As shown in Figure 11.1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains main/sub-frequency clock oscillator. The main/sub clock operation can be easily obtained by attaching a crystal between the XIN/SXIN and XOUT/SXOUT pin, respectively. The main/sub clock can be also obtained from the external oscillator. In this case, it is necessary to put the external clock signal into the XIN/SXIN pin and open the XOUT/SXOUT pin. The default system clock is 1MHz INT-RC Oscillator and the default division rate is eight. In order to stabilize system internally, it is used 1MHz INT-RC oscillator on POR. - Calibrated Internal RC Oscillator (8 MHz ) . INT-RC OSC/1 (8 MHz) . INT-RC OSC/2 (4 MHz) . INT-RC OSC/4 (2 MHz) . INT-RC OSC/8 (1 MHz, Default system clock) - Main Crystal Oscillator (1~12 MHz) - Sub Crystal Oscillator (32.768 kHz) - Internal WDTRC Oscillator (6 kHz) 11.1.2 Block Diagram XIN XOUT fXIN Main OSC STOP Mode XCLKE DCLK Internal RC OSC (8MHz) STOP Mode IRCE SXIN SXOUT 1 /1 1 /2 1 /4 1 /8 M U X f IRC System Clock Gen. Clock Change /4096 2 BIT clock IRCS[1:0] Stabilization Time Generation BIT overflow fSUB Sub OSC SCLK (fx) (Core, System, Peripheral ) WDT clock BIT STOP Mode SCLKE M U X 2 SCLK [1:0] WT WDTRC OSC (6kHz) /256 WDT fWDTRC STOP Mode WONS Figure 11.1 Clock Generator Block Diagram 11.1.3 Register Map Table 11-1 Clock Generator Register Map Name PS030002-0212 Address Dir Default Description PRELIMINARY 97 Z51F3221 Product Specification SCCR 8AH R/W 00H System and Clock Control Register OSCCR D9H R/W 00H Oscillator Control Register 11.1.4 Clock Generator Register Description The clock generator register uses clock control for system operation. The clock generation consists of System and clock control register and oscillator control register. 11.1.5 Register Description for Clock Generator SCCR (System and Clock Control Register) : 8AH 7 6 5 4 3 2 1 0 WONS PSAVE – – – – SCLK1 SCLK0 R/W R/W – – – – R/W WONS R/W Initial value : 00H Control the Operation of WDT RC-Oscillation during STOP mode 0 WDTRC-Oscillator is disabled at STOP mode 1 WDTRC-Oscillator is enabled at STOP mode NOTES) 1. When this bit is “1”, the WDTRC oscillator (6kHz) is oscillated and selected as the clock source of the WDT block in the STOP mode, but the WDTRC stops and the BIT overflow clock is the clock source for the WDT block at normal mode. 2. When this bit is “0”, the WDTRC is always stopped and the BIT overflow clock is selected as the clock source for the WDT block PSAVE Power Save Mode Control Bit 0 Normal circuit for sub oscillator 1 Power saving circuit for sub oscillator NOTES) 1. A capacitor (0.1μF) should be connected between VREG and VSS when the sub oscillator is used to power saving mode. 2. The PSAVE automatically cleared to ‘0’ when the sub oscillator is stopped by SCLKE or CPU is entered into STOP mode in sub operating mode. SCLK [1:0] System Clock Selection Bit SCLK1 SCLK0 Description 0 0 INT RC OSC for system clock 0 1 External Main OSC (fXIN) for system clock 1 x External Sub OSC (fSUB) for system clock Where x is “don’t care.” PS030002-0212 PRELIMINARY 98 Z51F3221 Product Specification OSCCR (Oscillator Control Register) : D9H 7 6 5 4 3 2 1 0 – – – IRCS1 IRCS0 IRCE XCLKE SCLKE – – – R/W R/W R/W R/W IRCS[1:0] Internal RC Oscillator Post-divider Selection IRCS1 IRCS0 IRCE XCLKE SCLKE PS030002-0212 R/W Initial value : 00H Description 0 0 INT-RC/8 (1MHz) 0 1 INT-RC/4 (2MHz) 1 0 INT-RC/2 (4MHz) 1 1 INT-RC/1 (8MHz) Control the Operation of the Internal RC Oscillator 0 Enable operation of INT-RC OSC 1 Disable operation of INT-RC OSC Control the Operation of the External Main Oscillator 0 Disable operation of X-TAL 1 Enable operation of X-TAL Control the Operation of the External Sub Oscillator 0 Disable operation of SX-TAL 1 Enable operation of SX-TAL PRELIMINARY 99 Z51F3221 Product Specification 11.2 Basic Interval Timer 11.2.1 Overview The Z51F3221 MCU features one 8-bit basic interval timer that is free-run and can’t stop. Block diagram is shown in Figure 11.2. In addition, the basic interval timer generates the time base for watchdog timer counting. It also provides a basic interval timer interrupt (BITIFR). The Z51F3221 MCU has these basic interval timer (BIT) features: - During Power On, BIT gives a stable clock generation time - On exiting Stop mode, BIT gives a stable clock generation time - As timer function, timer interrupt occurrence 11.2.2 Block Diagram BCK[2:0] Start CPU BIT Clock selected bit overflow 8 -Bit Up Counter BITCNT BCLR To interrupt block clear clear RESET STOP BITIFR WDT INT_ ACK Figure 11.2 Basic Interval Timer Block Diagram PS030002-0212 PRELIMINARY 100 Z51F3221 Product Specification 11.2.3 Register Map Table 11-2 Basic Interval Timer Register Map Name Address Dir Default Description BITCNT 8CH R 00H Basic Interval Timer Counter Register BITCR 8BH R/W 01H Basic Interval Timer Control Register 11.2.4 Basic Interval Timer Register Description The basic interval timer register consists of basic interval timer counter register (BITCNT) and basic interval timer control register (BITCR). If BCLR bit is set to ‘1’, BITCNT becomes ‘0’ and then counts up. After 1 machine cycle, BCLR bit is cleared to ‘0’ automatically. 11.2.5 Register Description for Basic Interval Timer BITCNT (Basic Interval Timer Counter Register) : 8CH 7 6 5 4 3 2 1 0 BITCNT7 BITCNT6 BITCNT5 BITCNT4 BITCNT3 BITCNT2 BITCNT1 BITCNT0 R R R R R R R BITCNT[7:0] R Initial value : 00H BIT Counter BITCR (Basic Interval Timer Control Register) : 8BH 7 6 5 4 3 2 1 0 BITIFR – – – BCLR BCK2 BCK1 BCK0 R/W – – – R/W R/W R/W BITIFR BCLR BCK[2:0] PS030002-0212 R/W Initial value : 01H When BIT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 BIT interrupt no generation 1 BIT interrupt generation If this bit is written to ‘1’, BIT Counter is cleared to ‘0’ 0 Free Running 1 Clear Counter Select BIT overflow period BCK2 BCK1 BCK0 Description 0 0 0 Bit 0 overflow (BIT Clock * 2) 0 0 1 Bit 1 overflow (BIT Clock * 4) (default) 0 1 0 Bit 2 overflow (BIT Clock * 8) 0 1 1 Bit 3 overflow (BIT Clock * 16) 1 0 0 Bit 4 overflow (BIT Clock * 32) 1 0 1 Bit 5 overflow (BIT Clock * 64) 1 1 0 Bit 6 overflow (BIT Clock * 128) 1 1 1 Bit 7 overflow (BIT Clock * 256) PRELIMINARY 101 Z51F3221 Product Specification 11.3 Watch Dog Timer 11.3.1 Overview The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or something like that, and resumes the CPU to the normal state. The watchdog timer signal for malfunction detection can be used as either a CPU reset or an interrupt request. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. It is possible to use free running 8bit timer mode (WDTRSON=’0’) or watch dog timer mode (WDTRSON=’1’) as setting WDTCR[6] bit. If WDTCR[5] is written to ‘1’, WDT counter value is cleared and counts up. After 1 machine cycle, this bit is cleared to ‘0’ automatically. The watchdog timer consists of 8-bit binary counter and the watchdog timer data register. When the value of 8-bit binary counter is equal to the 8 bits of WDTCNT, the interrupt request flag is generated. This can be used as Watchdog timer interrupt or reset of CPU in accordance with the bit WDTRSON. The input clock source of watch dog timer is the BIT overflow. The interval of watchdog timer interrupt is decided by BIT overflow period and WDTDR set value. The equation can be described as WDT Interrupt Interval = (BIT Interrupt Interval) X (WDTDR Value+1) 11.3.2 WDT Interrupt Timing Waveform Source Clock BIT Overflow WDTCNT[7:0] 0 1 2 3 0 1 2 3 0 1 2 Counter Clear WDTDR[7:0] WDTIFR Interrupt n 3 WDTCL Occur WDTDR  0000_0011b WDTRESETB Match Detect RESET Figure 11.3 Watch Dog Timer Interrupt Timing Waveform PS030002-0212 PRELIMINARY 102 Z51F3221 Product Specification 11.3.3 Block Diagram WDT Clock WDTCNT clear To RESET Circuit WDTEN WDTIFR To interrupt block clear WDTDR INT_ACK WDTCL WDTRSON WDTCR Figure 11.4 Watch Dog Timer Block Diagram 11.3.4 Register Map Table 11-3 Watch Dog Timer Register Map Name Address Dir Default Description WDTCNT 8EH R 00H Watch Dog Timer Counter Register WDTDR 8EH W FFH Watch Dog Timer Data Register WDTCR 8DH R/W 00H Watch Dog Timer Control Register 11.3.5 Watch Dog Timer Register Description The watch dog timer register consists of watch dog timer counter register (WDTCNT), watch dog timer data register (WDTDR) and watch dog timer control register (WDTCR). PS030002-0212 PRELIMINARY 103 Z51F3221 Product Specification 11.3.6 Register Description for Watch Dog Timer WDTCNT (Watch Dog Timer Counter Register: Read Case) : 8EH 7 6 5 4 3 2 1 0 WDTCNT 7 WDTCNT 6 WDTCNT 5 WDTCNT 4 WDTCNT3 WDTCNT 2 WDTCNT 1 WDTCNT 0 R R R R R R R WDTCNT[7:0] R Initial value : 00H WDT Counter WDTDR (Watch Dog Timer Data Register: Write Case) : 8EH 7 6 5 4 3 2 1 0 WDTDR7 WDTDR 6 WDTDR 5 WDTDR 4 WDTDR 3 WDTDR 2 WDTDR 1 WDTDR 0 W W W W W W W W Initial value : FFH WDTDR[7:0] Set a period WDT Interrupt Interval=(BIT Interrupt Interval) x(WDTDR Value+1) NOTE) Do not write “0” in the WDTDR register. WDTCR (Watch Dog Timer Control Register) : 8DH 7 6 5 4 3 2 1 0 WDTEN WDTRSON WDTCL – – – – WDTIFR R/W R/W R/W – – – – WDTEN WDTRSON WDTCL WDTIFR PS030002-0212 R/W Initial value : 00H Control WDT Operation 0 Disable 1 Enable Control WDT RESET Operation 0 Free Running 8-bit timer 1 Watch Dog Timer RESET ON Clear WDT Counter 0 Free Run 1 Clear WDT Counter (auto clear after 1 Cycle) When WDT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 WDT Interrupt no generation 1 WDT Interrupt generation PRELIMINARY 104 Z51F3221 Product Specification 11.4 Watch Timer 11.4.1 Overview The watch timer has the function for RTC (Real Time Clock) operation. It is generally used for RTC design. The internal structure of the watch timer consists of the clock source select circuit, timer counter circuit, output select circuit, and watch timer control register. To operate the watch timer, determine the input clock source, output interval, and set WTEN to ‘1’ in watch timer control register (WTCR). It is able to execute simultaneously or individually. To stop or reset WT, clear the WTEN bit in WTCR register. Even if CPU is STOP mode, sub clock is able to be so alive that WT can continue the operation. The watch timer counter circuits may be composed of 21bit counter which contains low 14-bit with binary counter and high 7-bit counter in order to raise resolution. In WTDR, it can control WT clear and set interval value at write time, and it can read 7-bit WT counter value at read time. The watch timer supplies the clock frequency for the LCD driver (fLCD). Therefore, if the watch timer is disabled, the LCD driver controller does not operate. 11.4.2 Block Diagram f S UB fx P r e s c a l e r f LCD =1024 Hz M U X fx/64 fx/128 f WCK 14Bit Binary Counter 14 f WCK /2 WTCL match fx/256 Match Clear Timer counter 14 f WCK /(2 X (7 bit WTDR Value +1)) Comparator f WCK /214 13 f WCK /2 7 f WCK /2 WTIFR MUX To interrupt block Clear 2 WTCR WTEN - - INT_ACK WTIFR WTIN1 WTIN0 WTCK1 WTCK0 Reload Match WTCL WTDR Write case WTCL WTCNT Read case - WTDR6 WTDR5 WTDR4 WTDR3 WTDR2 WTDR1 WTDR0 WTCNT6 WTCNT5 WTCNT4 WTCNT3 WTCNT2 WTCNT1 WTCNT0 Figure 11.5 Watch Timer Block Diagram PS030002-0212 PRELIMINARY 105 Z51F3221 Product Specification 11.4.3 Register Map Table 11-4 Watch Timer Register Map Name Address Dir Default Description WTCNT 9FH R 00H Watch Timer Counter Register WTDR 9FH W 7FH Watch Timer Data Register WTCR 9EH R/W 00H Watch Timer Control Register 11.4.4 Watch Timer Register Description The watch timer register consists of watch timer counter register (WTCNT), watch timer data register (WTDR), and watch timer control register (WTCR). As WTCR is 6-bit writable/ readable register, WTCR can control the clock source (WTCK[1:0]), interrupt interval (WTIN[1:0]), and function enable/disable (WTEN). Also there is WT interrupt flag bit (WTIFR). 11.4.5 Register Description for Watch Timer WTCNT (Watch Timer Counter Register: Read Case) : 9FH 7 6 5 4 3 2 1 0 – WTCNT 6 WTCNT 5 WTCNT 4 WTCNT 3 WTCNT 2 WTCNT 1 WTCNT0 – R R R R R R WTCNT[6:0] R Initial value : 00H WT Counter WTDR (Watch Timer Data Register: Write Case) : 9FH 7 6 5 4 3 2 1 0 WTCL WTDR 6 WTDR 5 WTDR 4 WTDR 3 WTDR 2 WTDR 1 WTDR 0 R/W W W W W W W WTCL WTDR[6:0] W Initial value : 7FH Clear WT Counter 0 Free Run 1 Clear WT Counter (auto clear after 1 Cycle) Set WT period WT Interrupt Interval=fwck/(2^14 x(7bit WTDR Value+1)) NOTE) Do not write “0” in the WTDR register. PS030002-0212 PRELIMINARY 106 Z51F3221 Product Specification WTCR (Watch Timer Control Register) : 9EH 7 6 5 4 3 2 1 0 WTEN – – WTIFR WTIN1 WTIN0 WTCK1 WTCK0 R/W – – R/W R/W R/W R/W WTEN WTIFR WTIN[1:0] WTCK[1:0] R/W Initial value : 00H Control Watch Timer 0 Disable 1 Enable When WT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 WT Interrupt no generation 1 WT Interrupt generation Determine interrupt interval WTIN1 WTIN0 Description 0 0 fWCK/2^7 0 1 fWCK/2^13 1 0 fWCK/2^14 1 1 fWCK/(2^14 x (7bit WTDR Value+1)) Determine Source Clock WTCK1 WTCK0 Description 0 0 fSUB 0 1 fX/256 1 0 fX/128 1 1 fX/64 NOTE) fX – System clock frequency (Where fx= 4.19MHz) fSUB – Sub clock oscillator frequency (32.768kHz) fWCK – Selected Watch timer clock fLCD – LCD frequency (Where fX= 4.19MHz, WTCK[1:0]=’10’; fLCD= 1024Hz) PS030002-0212 PRELIMINARY 107 Z51F3221 Product Specification 11.5 Timer 0 11.5.1 Overview The 8-bit timer 0 consists of multiplexer, timer 0 counter register, timer 0 data register, timer 0 capture data register and timer 0 control register (T0CNT, T0DR, T0CDR, T0CR). It has three operating modes: - 8-bit timer/counter mode - 8-bit PWM output mode - 8-bit capture mode The timer/counter 0 can be clocked by an internal or an external clock source (EC0). The clock source is selected by clock selection logic which is controlled by the clock selection bits (T0CK[2:0]). - TIMER0 clock source: fX/2, 4, 8, 32, 128, 512, 2048, EC0 In the capture mode, by EINT10, the data is captured into input capture data register (T0CDR). In timer/counter mode, whenever counter value is equal to T0DR, T0O port toggles. Also the timer 0 outputs PWM waveform through PWM0O port in the PWM mode. Table 11-5 Timer 0 Operating Modes PS030002-0212 T0EN T0_PE T0MS[1:0] T0CK[2:0] Timer 0 1 1 00 XXX 8 Bit Timer/Counter Mode 1 1 01 XXX 8 Bit PWM Mode 1 0 1X XXX 8 Bit Capture Mode PRELIMINARY 108 Z51F3221 Product Specification 11.5.2 8-Bit Timer/Counter Mode The 8-bit timer/counter mode is selected by control register as shown in Figure 11.6. The 8-bit timer have counter and data register. The counter register is increased by internal or external clock input. Timer 0 can use the input clock with one of 2, 4, 8, 32, 128, 512 and 2048 prescaler division rates (T0CK[2:0]). When the value of T0CNT and T0DR is identical in timer 0, a match signal is generated and the interrupt of Timer 0 occurs. T0CNT value is automatically cleared by match signal. It can be also cleared by software (T0CC). The external clock (EC0) counts up the timer at the rising edge. If the EC0 is selected as a clock source by T0CK[2:0], EC0 port should be set to EC0 function by PFSR6[3:2] or PFSR8[1:0] bits. T0CR T0EN T0 _PE T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC 1 x 0 0 x x x x ADDRESS : B2 H INITIAL VALUE: 0000 _0000B EC0 fx P r e s c a l e r fx/4 fx/8 fx/32 T0CC Clear fx/2 Match signal 8-bit Timer 0 Counter M U X INT_ACK T0CNT(8Bit) Clear fx/128 fx/512 Match T0 EN fx/2048 MUX T0IFR To interrupt block Comparator 3 T0CK[2:0 ] 2 T0DR(8Bit) T0MS[1:0] 8-bit Timer 0 Data Register F/F T0O/PWM0O T0 _PE Figure 11.6 8-Bit Timer/Counter Mode for Timer 0 PS030002-0212 PRELIMINARY 109 Z51F3221 Product Specification Match with T0DR n T0CNT Value n-1 n-2 Count Pulse Period PCP 6 Up-count 5 4 3 2 1 0 TIME Interrupt Period = PCP x (n+1) Timer 0 (T0IFR) Interrupt Occur Interrupt Occur Interrupt Occur Interrupt Figure 11.7 8-Bit Timer/Counter 0 Example PS030002-0212 PRELIMINARY 110 Z51F3221 Product Specification 11.5.3 8-Bit PWM Mode The timer 0 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, T0O/PWM0O pin outputs up to 8-bit resolution PWM output. This pin should be configured as a PWM output by setting T0_PE to ‘1’ and the T0O/PWM0O function by PFSR6[1:0] or PFSR7[7:6] bits. In the 8-bit timer/counter mode, a match signal is generated when the counter value is identical to the value of T0DR. When the value of T0CNT and T0DR is identical in timer 0, a match signal is generated and the interrupt of timer 0 occurs. In PWM mode, the match signal does not clear the counter. Instead, it runs continuously, overflowing at “FFH”, and then continues incrementing from “00H”. The timer 0 overflow interrupt is generated whenever a counter overflow occurs. T0CNT value is cleared by software (T0CC) bit. T0CR T0EN T0 _PE T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC 1 x 0 1 x x x x ADDRESS : B2 H INITIAL VALUE: 0000 _0000B INT_ACK Clear To interrupt block T0OVIFR EC0 fx P r e s c a l e r Clear fx/2 fx/4 fx/8 fx/32 T0CC 8-bit Timer 0 Counter M U X INT_ACK T0CNT(8Bit) Clear fx/128 fx/512 Match T0 EN fx/2048 MUX T0IFR To interrupt block Comparator 3 T0CK[2:0 ] 2 T0DR(8Bit) T0MS[1:0] 8-bit Timer 0 Data Register F/F T0O/PWM0O T0 _PE Figure 11.8 8-Bit PWM Mode for Timer 0 PS030002-0212 PRELIMINARY 111 Z51F3221 Product Specification PWM Mode (T0MS = 01b) Set T0EN Timer 0 clock T0CNT XX 00H 01H 02H 4AH FEH FFH 00H T0DR T0 Overflow Interrupt 1. T0DR = 4AH T0PWM T0 Match Interrupt 2. T0DR = 00H T0PWM T0 Match Interrupt 3. T0DR = FFH T0PWM T0 Match Interrupt Figure 11.9 PWM Output Waveforms in PWM Mode for Timer 0 PS030002-0212 PRELIMINARY 112 Z51F3221 Product Specification 11.5.4 8-Bit Capture Mode The timer 0 capture mode is set by T0MS[1:0] as ‘1x’. The clock source can use the internal/external clock. Basically, it has the same function as the 8-bit timer/counter mode and the interrupt occurs when T0CNT is equal to T0DR. T0CNT value is automatically cleared by match signal and it can be also cleared by software (T0CC). This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer. The capture result is loaded into T0CDR. In the timer 0 capture mode, timer 0 output (T0O) waveform is not available. According to EIEDGE1 and EIPOL1 registers setting, the external interrupt EINT10 function is chosen. Of cource, the EINT10 pin must be set to an input port. T0CDR and T0DR are in the same address. In the capture mode, reading operation reads T0CDR, not T0DR and writing operation will update T0DR. T0CR T0EN T0_ PE T0MS1 T0MS0 T0 CK2 T0CK1 T0CK0 T0CC 1 x 1 x x x x x ADDRESS : B2H INITIAL VALUE: 0000 _0000B EC0 fx fx/4 fx/8 fx/32 T0CC Clear fx/2 P r e s c a l e r Match signal 8-bit Timer 0 Counter M U X INT_ACK T0CNT(8Bit) Clear fx/128 fx/512 Clear Match T0EN fx/2048 MUX T0IFR To interrupt block Comparator 2 3 T0DR(8Bit) T0MS[1:0 ] T0CK[2 :0] 8-bit Timer 0 Data Register T0 CDR(8Bit) EINT10 INT_ACK 2 Clear T0MS[1:0] FLAG10 (EIFLAG1 .0) EIEDGE1.0 To interrupt block Figure 11.10 8-Bit Capture Mode for Timer 0 PS030002-0212 PRELIMINARY 113 Z51F3221 Product Specification T0CDR Load n T0CNT Value n-1 n-2 Count Pulse Period PCP 6 Up-count 5 4 3 2 1 0 TIME Ext. EINT10 PIN Interrupt Request (FLAG10) Interrupt Interval Period Figure 11.11 Input Capture Mode Operation for Timer 0 FFH FFH XXH T0CNT YYH 00H 00H 00H 00H 00H Interrupt Request (T0IFR) Ext. EINT10 PIN Interrupt Request (FLAG10) Interrupt Interval Period = FFH+01H+FFH +01H+YYH+01H Figure 11.12 Express Timer Overflow in Capture Mode PS030002-0212 PRELIMINARY 114 Z51F3221 Product Specification 11.5.5 Block Diagram INT_ACK Clear To interrupt block T0OVIFR EC0 fx P r e s c a l e r Clear fx/2 fx/4 fx/8 fx/32 T0CC Match signal 8-bit Timer Counter M U X INT_ACK T0CNT(8Bit) Clear fx/128 fx/512 Clear Match T0EN fx/2048 MUX T0IFR Comparator To interrupt block 2 3 T0DR(8Bit) T0MS[1:0 ] T0CK[2:0] 8-bit Timer Data Register F/F T0CDR(8Bit) EINT10 T0O/PWM0O T0_ PE INT_ACK 2 Clear T0MS[1:0] FLAG10 (EIFLAG1.0) EIEDGE1.0 To interrupt block Figure 11.13 8-Bit Timer 0 Block Diagram PS030002-0212 PRELIMINARY 115 Z51F3221 Product Specification 11.5.6 Register Map Table 11-6 Timer 0 Register Map Name Address Dir Default Description T0CNT B3H R 00H Timer 0 Counter Register T0DR B4H R/W FFH Timer 0 Data Register T0CDR B4H R 00H Timer 0 Capture Data Register T0CR B2H R/W 00H Timer 0 Control Register 11.5.6.1 Timer/Counter 0 Register Description The timer/counter 0 register consists of timer 0 counter register (T0CNT), timer 0 data register (T0DR), timer 0 capture data register (T0CDR), and timer 0 control register (T0CR). T0IFR and T0OVIFR bits are in the timer interrupt flag register (TIFR). 11.5.6.2 Register Description for Timer/Counter 0 T0CNT (Timer 0 Counter Register) : B3H 7 6 5 4 3 2 1 0 T0CNT7 T0CNT6 T0CNT5 T0CNT4 T0CNT3 T0CNT2 T0CNT1 T0CNT0 R R R R R R R T0CNT[7:0] R Initial value : 00H T0 Counter T0DR (Timer 0 Data Register) : B4H 7 6 5 4 3 2 1 0 T0DR7 T0DR6 T0DR5 T0DR4 T0DR3 T0DR2 T0DR1 T0DR0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH T0DR[7:0] T0 Data T0CDR (Timer 0 Capture Data Register: Read Case, Capture mode only) : B4H 7 6 5 4 3 2 1 0 T0CDR7 T0CDR6 T0CDR5 T0CDR4 T0CDR3 T0CDR2 T0CDR1 T0CDR0 R R R R R R R T0CDR[7:0] PS030002-0212 R Initial value : 00H T0 Capture PRELIMINARY 116 Z51F3221 Product Specification T0CR (Timer 0 Control Register) : B2H 7 6 5 4 3 2 1 0 T0EN T0_PE T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC R/W R/W R/W R/W R/W R/W R/W T0EN T0_PE T0MS[1:0] T0CK[2:0] T0CC R/W Initial value : 00H Control Timer 0 0 Timer 0 disable 1 Timer 0 enable Control T0O/PWM0O Output port 0 T0O/PWM0O Output disable 1 T0O/PWM0O Output enable Control Timer 0 Operation Mode T0MS1 T0MS0 Description 0 0 Timer/counter mode 0 1 PWM mode 1 x Capture mode Select Timer 0 clock source. fx is a system clock frequency T0CK2 T0CK1 T0CK0 Description 0 0 0 fx/2 0 0 1 fx/4 0 1 0 fx/8 0 1 1 fx/32 1 0 0 fx/128 1 0 1 fx/512 1 1 0 fx/2048 1 1 1 External Clock (EC0) Clear timer 0 Counter 0 No effect 1 Clear the Timer 0 counter (When write, automatically cleared “0” after being cleared counter) NOTE) Match Interrupt is generated in Capture mode. PS030002-0212 PRELIMINARY 117 Z51F3221 Product Specification 11.6 Timer 1 11.6.1 Overview The 8-bit timer 1 consists of multiplexer, timer 1 counter register, timer 1 data high/low register, and timer 1 control register (T1CNT, T1DRH, T1DRL, T1CR) . For carrier mode, it has the carrier control register (CARCR). It has two operating modes: - 8-bit timer/counter mode - 8-bit carrier mode The timer/counter 1 can be clocked by an internal clock source. The clock source is selected by clock selection logic which is controlled by the clock selection bits (T1CK[1:0]). - TIMER1 clock source: fX/1, fx/2, fx/4, fx/8 In the carrier mode, Timer 1 can be used to generate the carrier frequency or a remote controller signal. Timer 1 can output the comparison result between T1CNT & T1DRH/L and carrier frequency through REM port. T1CNT value is cleared by hardware. Table 11-7 Timer 1 Operating Modes T1EN REM_PE CAR1 T1CK[1:0] CMOD Timer 1 1 1 0 XXX 0 8 Bit Timer/Counter 1 1 1 XXX 0 8 Bit Carrier (One-shot) 1 1 1 XXX 1 8 Bit Carrier (Repeat) PS030002-0212 PRELIMINARY 118 Z51F3221 Product Specification 11.6.2 8-Bit Timer/Counter 1 Mode The 8-bit timer/counter mode is selected by control register as shown in Figure 11.13. The 8-bit timer have counter and data register. The counter register is increased by internal clock source. Timer 1 can use the input clock with one of 1, 2, 4 and 8 prescaler division rates (T1CK[1:0]). When the value of T1CNT and T1DRH is identical in Timer 1, a match signal is generated and the interrupt of Timer 1 occurs. The match signal generates a timer 1 interrupt and clear the counter. The timer 1 interval can be output through REM port. T1CR T1EN - REM_PE CAR1 T1CK1 T1CK0 T1CN T1 ST 1 - x 0 x x x x ADDRESS : CAH INITIAL VALUE: 0000 _0000B T1ST fx/1 fx Pre scaler fx/2 fx/4 8-bit Timer 1 Counter M U X Clear T1CNT (8Bit) INT_ ACK Clear fx/8 Match T1EN T1IFR 2 To interrupt block Comparator T1CK[1:0] T1DRH (8 Bit) REMO F/F T1M (T2 clock source) REM_ PE REM 8-bit Timer 1 Data high Register Figure 11.14 8-Bit Timer/Counter Mode for Timer 1 PS030001-0212 PRELIMINARY 122 Z51F3221 Product Specification Match with T1DR n T1CNT Value n-1 n-2 Count Pulse Period PCP 6 Up-count 5 4 3 2 1 0 TIME Interrupt Period = PCP x (n+1) Timer 1 (T1IFR) Interrupt Occur Interrupt Occur Interrupt Occur Interrupt Figure 11.15 8-Bit Timer/Counter 1 Example Match with T1DR T1CNT Value Disable Enable Clear&Start STOP Up-count TIME Timer 1 (T1IFR) Interrupt T1ST Start&Stop Occur Interrupt Occur Interrupt T1ST = 1 T1ST = 1 T1ST = 0 T1CN Control count T1CN = 1 T1CN = 1 T1CN = 0 Figure 11.16 8-Bit Timer/Counter 1 Counter Operation PS030002-0212 PRELIMINARY 120 Z51F3221 Product Specification 11.6.3 8-Bit Timer 1 Carrier Frequency Mode. The carrier frequency and the pulse of data are calculated by the formula in the following sheet .The Figure 11.16 shows the block diagram of Timer 1 for carrier frequency mode. T1CR T1EN - 1 - REM_ PE CAR1 x Pre scaler fx/2 fx/4 fx/8 T1CK1 T1CK0 T1CN T1ST x x x x ADDRESS : CAH INITIAL VALUE: 0000_0000 B T1ST T1EN fx/1 fx 1 8-bit Timer 1 Counter M U X T1CNT (8Bit) Clear T1M (T2 clock source) REM_PE REMO F/F Match 2 T1CK[1:0] REM Comparator CMOD MUX T1IT T1 IFR T1DRL ( 8Bit) To interrupt block Clear INT_ACK T1DRH (8 Bit) Figure 11.17 Carrier Mode for Timer 1 NOTE) When one of T1DRH and T1DRL values is “00H”, the carrier frequency generator (REM) output always becomes a “High” or “Low”. At that time, Timer 1 Interrupt Flag Bit (T1IFR) is not set. PS030002-0212 PRELIMINARY 121 Z51F3221 Product Specification 11.6.4 Carrier Output Pulse Width Calculatins t LOW t HIGH t LOW To generate the above repeated waveform consisted of low period time (tLOW), and high period time (tHIGH). When REMO = 0, tLOW = (T1DRL + 1) x 1/fT1, 0H < T1DRL < 100H, where fT1 = The selected clock. tHIGH = (T1DRH + 1) x 1/fT1, 0H < T1DRH < 100H, where fT1 = The selected clock. When REMO = 1, tLOW = (T1DRH + 1) x 1/fT1, 0H < T1DRH < 100H, where fT1 = The selected clock. tHIGH = (T1DRL + 1) x 1/fT1, 0H < T1DRL < 100H, where fT1 = The selected clock. To make tLOW = 24 us and tHIGH = 15 us. fX = 4 MHz, fT1 = 4 MHz/4 = 1 MHz When REMO = 0, tLOW = 24 us = (T1DRL + 1) /fT1 = (T1DRL + 1) x 1us, T1DRL = 22. tHIGH = 15 us = (T1DRH + 1) /fT1 = (T1DRH + 1) x 1us, T1DRH = 13. When REMO = 1, tLOW = 24 us = (T1DRH + 1) / fT1 = (T1DRH + 1) x 1us, T1DRH = 22. tHIGH = 15 us = (T1DRL + 1) / fT1 = (T1DRL + 1) x 1us, T1DRL = 13. PS030002-0212 PRELIMINARY 122 Z51F3221 Product Specification 0H Timer 1 Clock (T1CK[1:0]) REMO = '0' T1DRL = 00H T1DRH = 00H Low REMO = '0' T1DRL = 00H T1DRH = 01-FFH High REMO = '0' T1DRL = 01-FFH T1DRH = 00H Low REMO = '1' T1DRL = 00H T1DRH = 00H High REMO = '1' T1DRL = 00H T1DRH = 01-FFH Low REMO = '1' T1DRL = 01-FFH T1DRH = 00H High 0H 100H 200H Timer 1 Clock (T1CK[1:0]) REMO = '1' T1DRL = DFH T1DRH = 1FH E0H REMO = '0' T1DRL = DFH T1DRH = 1FH E0H REMO = '1' T1DRL = 7FH T1DRH = 7FH REMO = '0' T1DRL = 7FH T1DRH = 7FH 20H 20H 80H 80H 80H 80H Figure 11.18 Carrier Output Waveforms in Repeat Mode for Timer 1 PS030002-0212 PRELIMINARY 123 Z51F3221 Product Specification 11.6.5 Block Diagram T1ST fx/1 fx Pre scaler 8-bit Timer 1 Counter fx/2 M U X fx/4 fx/8 Clear T1CNT (8Bit) INT_ ACK Clear Match T1EN 2 T1IFR To interrupt block Comparator T1CK[1:0] T1DRH (8 Bit) REMO F/F T1M (T2 clock source) REM_ PE REM 8-bit Timer 1 Data high Register Figure 11.19 8-Bit Timer 1 Block Diagram 11.6.6 Register Map Table 11-8 Timer 1 Register Map Name Address Dir Default Description T1CNT CBH R 00H Timer 1 Counter Register T1DRH CDH R/W FFH Timer 1 Data High Register T1DRL CCH R/W FFH Timer 1 Data Low Register T1CR CAH R/W 00H Timer 1 Control Register CARCR CEH R/W 00H Carrier Control Register 11.6.6.1 Timer/Counter 1 Register Description The timer/counter 1 register consists of timer 1 counter register (T1CNT), timer 1 data high register (T1DRH), timer 1 data low register (T1DRL), timer 1 control register (T1CR) and carrier control register (CARCR). T1IFR bit is in the timer interrupt flag register (TIFR). PS030002-0212 PRELIMINARY 124 Z51F3221 Product Specification 11.6.6.2 Register description for Timer/Counter 1 T1CNT (Timer 1 Counter Register) : CBH 7 6 5 4 3 2 1 0 T1CNT7 T1CNT6 T1CNT5 T1CNT4 T1CNT3 T1CNT2 T1CNT1 T1CNT0 R R R R R R R T1CNT[7:0] R Initial value : 00H T1 Counter T1DRH (Timer 1 Data High Register) : CDH 7 6 5 4 3 2 1 0 T1DRH7 T1DRH6 T1DRH5 T1DRH4 T1DRH3 T1DRH2 T1DRH1 T1DRH0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH T1DRH[7:0] T1 Data High T1DRL (Timer 1 Data Low Register: Carrier mode only) : CCH 7 6 5 4 3 2 1 0 T1DRL7 T1DRL6 T1DRL5 T1DRL4 T1DRL3 T1DRL2 T1DRL1 T1DRL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH T1DRL[7:0] PS030002-0212 T1 Data Low PRELIMINARY 125 Z51F3221 Product Specification T1CR (Timer 1 Control Register) : CAH 7 6 5 4 3 2 1 0 T1EN – REM_PE CAR1 T1CK1 T1CK0 T1CN T1ST R/W – R/W R/W R/W R/W R/W T1EN R/W Initial value : 00H Control Timer 1 REM_PE 0 Timer 1 disable 1 Timer 1 enable REM Output Port CAR1 0 REM output disable 1 REM output enable Control Timer 1 Operation mode T1CK[1:0] T1CN 0 Timer/counter mode 1 Carrier mode Select Timer 1 clock source. fx is system clock frequency T1CK1 T1CK0 Description 0 0 fx/1 0 1 fx/2 1 0 fx/4 1 1 fx/8 Control Timer 1 Counter pause/continue T1ST 0 Temporary count stop 1 Continue count Control Timer 1 start/stop 0 Counter stop 1 Clear counter and start CARCR (Carrier Control Register: Carrier mode only) : CEH 7 6 5 4 3 2 1 0 – – T1IT1 T1IT0 – – CMOD REMO – – R/W R/W – – R/W T1IT[1:0] CMOD REMO PS030002-0212 R/W Initial value : 00H T1 Interrupt Time Select T1IT1 T1IT0 Description 0 0 Elapsed time for low data value 0 1 Elapsed time for high data value 1 0 Elapsed time for low and high data value 1 1 Not available Carrier Frequency Mode Select 0 One-shot mode 1 Repeating mode REM Output Control 0 T1DRL→ Low width, T1DRH→ High width 1 T1DRL→ High width, T1DRH→ Low width PRELIMINARY 126 Z51F3221 Product Specification 11.7 Timer 2 11.7.1.1 Overview The 16-bit timer 2 consists of multiplexer, timer 2 counter register high/low, timer 2 data register high/low, and timer 2 control register (T2CNTH, T2CNTL, T2DRH, T2DRL, T2CR). It can be used as an internal 16-bit timer/ counter 2 without a port output function. The 16-bit timer 2 is able to use the divided clock of the system clock selected from prescaler output. T1M (timer 1 match signal) can be also used as the clock source of Timer 2. 11.7.2 Block Diagram T2CR T2EN - - T2CK2 T2 CK1 T2CK0 T2CN T2ST 1 - - x x x x x ADDRESS : BAH INITIAL VALUE: 0000_ 0000B T1M fx P r e s c a l e r T2ST fx/1 fx/4 16-bit Counter M U X fx/8 fx/32 T2CNTH (8Bit) fx/64 T2CNTL (8Bit) MSB fx/256 Clear INT_ ACK Clear LSB T2EN T2IFR fx/1024 To interrupt block Comparator T2DRH (8Bit) 3 T2CK[2:0] T2DRL (8Bit) MSB LSB 16-bit Data Register Figure 11.20 16-Bit Timer/Counter Mode for Timer 2 and Block Diagram 11.7.3 Register Map Table 11-9 Timer 2 Register Map Name Address Dir Default Description T2CNTH BDH R 00H Timer 2 Counter High Register T2CNTL BCH R 00H Timer 2 Counter Low Register T2DRH BFH R/W FFH Timer 2 Data High Register T2DRL BEH R/W FFH Timer 2 Data Low Register T2CR BAH R/W 00H Timer 2 Control Register 11.7.3.1 Timer/Counter 2 Register Description The timer/counter 2 register consists of timer 2 counter high register (T2CNTH), timer 2 counter low register (T2CNTL), timer 2 data high register (T2DRH), timer 2 data low register (T2DRL), and timer 2 control register (T2CR). T2IFR bit is in the timer interrupt flag register (TIFR). PS030002-0212 PRELIMINARY 127 Z51F3221 Product Specification 11.7.3.2 Register Description for Timer/Counter 2 T2CNTH (Timer 2 Counter High Register) : BDH 7 6 5 4 3 2 1 0 T2CNTH7 T2CNTH6 T2CNTH5 T2CNTH4 T2CNTH3 T2CNTH2 T2CNTH1 T2CNTH0 R R R R R R R T2CNTH[7:0] R Initial value : 00H T2 Counter High T2CNTL (Timer 2 Counter Low Register) : BCH 7 6 5 4 3 2 1 0 T2CNTL7 T2CNTL6 T2CNTL5 T2CNTL4 T2CNTL3 T2CNTL2 T2CNTL1 T2CNTL0 R R R R R R R T2CNTL[7:0] R Initial value : 00H T2 Counter Low T2DRH (Timer 2 Data High Register) : BFH 7 6 5 4 3 2 1 0 T2DRH7 T2DRH6 T2DRH5 T2DRH4 T2DRH3 T2DRH2 T2DRH1 T2DRH0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH T2DRH[7:0] T2 Data High T2DRL (Timer 2 Data Low Register) : BEH 7 6 5 4 3 2 1 0 T2DRL7 T2DRL6 T2DRL5 T2DRL4 T2DRL3 T2DRL2 T2DRL1 T2DRL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH T2DRL[7:0] PS030002-0212 T2 Data Low PRELIMINARY 128 Z51F3221 Product Specification T2CR (Timer 2 Control Register) : BAH 7 6 5 4 3 2 1 0 T2EN – – T2CK2 T2CK1 T2CK0 T2CN T2ST R/W – – R/W R/W R/W R/W T2EN T2CK[2:0] T2CN T2ST PS030002-0212 R/W Initial value : 00H Control Timer 2 0 Timer 2 disable 1 Timer 2 enable Select Timer 2 clock source. fx is main system clock frequency T2CK2 T2CK1 T2CK0 Description 0 0 0 T1M 0 0 1 fx/1 0 1 0 fx/4 0 1 1 fx/8 1 0 0 fx/32 1 0 1 fx/64 1 1 0 fx/256 1 1 1 fx/1024 Control Timer 2 Counter pause/continue 0 Temporary count stop 1 Continue count Control Timer 2 start/stop 0 Counter stop 1 Clear counter and start PRELIMINARY 129 Z51F3221 Product Specification 11.8 Timer 3 11.8.1 Overview The 16-bit timer 3 consists of multiplexer, timer 3 counter high/low register, timer 3 data high/low register, timer 3 capture data high/low register, and timer 3 control register (T3CNTH, T3CNTL, T3DRH, T3DRL, T3CDRH, T3CDRL, T3CR). It has three operating modes: - 16-bit timer/counter mode - 16-bit PWM output mode - 16-bit capture mode The timer/counter can be clocked by an internal or an external clock source (EC3). The clock source is selected by clock selection logic which is controlled by the clock selection bits (T3CK[2:0]). - TIMER3 clock source: fX/1, 2, 16, 64, 256, 512, 1024 and EC3 In the capture mode, by EINT13, the data is captured into input capture data high/low register (T3CDRH, T3CDRL). Timer 3 outputs the comparison result between counter and data register through T3O port in 16-bit timer/counter mode. AlsoTimer 3 outputs PWM waveform through PWM3O port in the PWM mode. Table 11-10 Timer 3 Operating Modes PS030002-0212 T3EN T3_PE T3MS[1:0] T3CK[2:0] Timer 3 1 1 00 XXX 16 Bit Timer/Counter Mode 1 1 01 XXX 16 Bit PWM Mode 1 0 1X XXX 16 Bit Capture Mode PRELIMINARY 130 Z51F3221 Product Specification 11.8.2 16-Bit Timer/Counter Mode The 16-bit timer/counter mode is selected by control register as shown in Figure 11.20. The 16-bit timer have counter and data register. The counter register is increased by internal or external clock input. Timer 3 can use the input clock with one of 1, 2, 16, 64, 256, 512 and 1024 prescaler division rates (T3CK[2:0]). A 16-bit timer/counter register T3CNTH, T3CNTL are incremented from 0000H to FFFFH until it matches T3DRH, T3DRL and then cleared to 0000H. The match signal output generates the Timer 3 Interrupt. The T3CNTH, T3CNTL value is automatically cleared by match signal. It can be also cleared by software (T3CC). The external clock (EC3) counts up the timer at the rising edge. If the EC3 is selected as a clock source by T3CK[2:0], EC3 port should be set to the EC3 function by PFSR0[1:0] or PFSR0[4:3] bits. Figure 11.21 16-Bit Timer/Counter Mode for Timer 3 PS030002-0212 PRELIMINARY 131 Z51F3221 Product Specification 11.8.3 16-Bit PWM Mode The 16-bit timer 3 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, T3O/PWM3O pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by setting T3_PE to ‘1’ and the T3O/PWM3O function by PFSR02 bit. As in the 16-bit timer/counter mode, a match signal is generated when the counter value is identical to the value of T3DRH/L. When the value of T3CNTH, T3CNTL and the value of T3DRH, T3DRL are identical in Timer 3 respectively, a match signal isgenerated and the interrupt of Timer 3 occurs. In PWM mode, the match signal does not clear the counter. Instead, it runs continuously, overflowing at “FFFFH”, and then continues incementing from “0000H”. The timer 3 overflow interrupt is generated whenever a counter overflow occurs. The T3CNTH, T3CNTL values are cleared by software (T3CC) bit. Figure 11.22 16-Bit PWM Mode for Timer 3 PS030002-0212 PRELIMINARY 132 Z51F3221 Product Specification 11.8.4 16-Bit Capture Mode The 16-bit timer 3 capture mode is set by T3MS[1:0] as ‘1X’. The clock source can use the internal/external clock. Basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when T3CNTH/L is equal to T3DRH/L. The T3CNTH, T3CNTL values are automatically cleared by match signal. It can be also cleared by software (T3CC). This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer. The capture result is loaded into T3CDRH, T3CDRL. According to the EIEDGE1 and EIPOL1 register setting, the external interrupt EINT13 function is chosen. T3CDRH, T3CDRL and T3DRH, T3DRL are in same address respectively. In the capture mode, reading operation reads the T3CDRH, T3CDRL, not T3DRH, T3DRL and writing operation will update T3DRH and T3DRL. T3CR T3EN T3 _PE T3MS1 T3MS0 T3CK2 T3CK1 T3CK0 T3CC 1 x 1 x x x x x ADDRESS : C2H INITIAL VALUE: 0000 _0000B EC3 fx Clear fx/1 P r e s c a l e r fx/2 fx/16 fx/64 T3CC Match signal 16-bit Timer 3 Counter M U X Clear fx/256 fx/512 T3 CNTH (8Bit) MSB T3CNTL (8Bit) INT_ACK Clear LSB Match T3EN fx/1024 MUX T3IFR To interrupt block Comparator 3 T3DRH (8Bit) T3CK[2:0] T3DRL (8Bit) 16-bit Timer 3 Data Register MSB LSB T3CDRH (8Bit) MSB 2 T3 MS[1 :0] T3 CDRL (8Bit) LSB EINT13 INT_ACK Clear 2 T3 MS[1:0] FLAG13 (EIFLAG1 .1) EIEDGE1.1 To interrupt block Figure 11.23 16-Bit Capture Mode for Timer 3 PS030002-0212 PRELIMINARY 133 Z51F3221 Product Specification 11.8.5 Block Diagram INT_ACK Clear T3 OVIFR To interrupt block EC3 fx P r e s c a l e r Clear fx/1 fx/2 T3CC Match signal 16-bit Timer 3 Counter M U X fx/16 fx/64 Clear fx/256 fx/512 T3 CNTH (8Bit) T3CNTL (8Bit) MSB INT_ACK Clear LSB Match T3EN fx/1024 MUX T3IFR To interrupt block Comparator 3 T3DRH (8Bit) T3CK[2:0] 2 T3DRL (8Bit) 16-bit Timer 3 Data Register MSB LSB T3CDRH (8Bit) T3 MS[1 :0] F/F T3 CDRL (8Bit) MSB T3O/PWM3O T3_PE LSB EINT13 INT_ACK Clear 2 T3MS[1:0] FLAG13 (EIFLAG1 .1) EIEDGE1.1 To interrupt block Figure 11.24 16-Bit Timer 3 Block Diagram 11.8.6 Register Map Table 11-11 Timer 3 Register Map Name T3CNTH Address Dir Default 00H Description C5H R Timer 3 Counter High Register T3CNTL C4H R 00H Timer 3 Counter Low Register T3DRH C7H R/W FFH Timer 3 Data High Register T3DRL C6H R/W FFH Timer 3 Data Low Register T3CDRH C7H R 00H Timer 3 Capture Data High Register T3CDRL C6H R 00H Timer 3 Capture Data Low Register T3CR C2H R/W 00H Timer 3 Control Register TIFR C3H R/W 00H Timer Interrupt Flag Register PS030002-0212 PRELIMINARY 134 Z51F3221 Product Specification 11.8.6.1 Timer/Counter 3 Register Description The timer/counter 3 register consists of timer 3 counter high register (T3CNTH), timer 3 counter low register (T3CNTL), timer 3 data high register (T3DRH), timer 3 data low register (T3DRL), timer 3 capture data high register (T3CDRH), timer 3 capture data low register (T3CDRL), timer 3 control register (T3CR), and timer interrupt flag register (TIFR). 11.8.6.2 Register Description for Timer/Counter 3 T3CNTH (Timer 3 Counter High Register) : C5H 7 6 5 4 3 2 1 0 T3CNTH7 T3CNTH6 T3CNTH5 T3CNTH4 T3CNTH3 T3CNTH2 T3CNTH1 T3CNTH0 R R R R R R R T3CNTH[7:0] R Initial value : 00H T3 Counter High T3CNTL (Timer 3 Counter Low Register) : C4H 7 6 5 4 3 2 1 0 T3CNTL7 T3CNTL6 T3CNTL5 T3CNTL4 T3CNTL3 T3CNTL2 T3CNTL1 T3CNTL0 R R R R R R R T3CNTL[7:0] R Initial value : 00H T3 Counter Low T3DRH (Timer 3 Data High Register) : C7H 7 6 5 4 3 2 1 0 T3DRH7 T3DRH6 T3DRH5 T3DRH4 T3DRH3 T3DRH2 T3DRH1 T3DRH0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH T3DRH[7:0] T3 Data High T3DRL (Timer 3 Data Low Register) : C6H 7 6 5 4 3 2 1 0 T3DRL7 T3DRL6 T3DRL5 T3DRL4 T3DRL3 T3DRL2 T3DRL1 T3DRL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH T3DRL[7:0] PS030002-0212 T3 Data Low PRELIMINARY 135 Z51F3221 Product Specification T3CDRH (Timer 3 Capture Data High Register: Read Case, 16-bit Capture mode only) : C7H 7 6 5 4 3 2 1 0 T3CDRH7 T3CDRH6 T3CDRH5 T3CDRH4 T3CDRH3 T3CDRH2 T3CDRH1 T3CDRH0 R R R R R R R T3CDRH[7:0] R Initial value : 00H T3 Capture Data High T3CDRL (Timer 3 Capture Data Low Register: Read Case, 16-bit Capture mode only) : C6H 7 6 5 4 3 2 1 0 T3CDRL7 T3CDRL6 T3CDRL5 T3CDRL4 T3CDRL3 T3CDRL2 T3CDRL1 T3CDRL0 R R R R R R R T3CDRL[7:0] R Initial value : 00H T3 Capture Data Low T3CR (Timer 3 Control Register) : C2H 7 6 5 4 3 2 1 0 T3EN T3_PE T3MS1 T3MS0 T3CK2 T3CK1 T3CK0 T3CC R/W R/W R/W R/W R/W R/W R/W T3EN T3_PE T3MS[1:0] T3CK[2:0] T3CC R/W Initial value : 00H Control Timer 3 0 Timer 3 disable 1 Timer 3 enable Control T3O/PWM3O Output port 0 T3O/PWM3O Output disable 1 T3O/PWM3O Output enable Control Timer 3 Operation Mode T3MS1 T3MS0 Description 0 0 Timer/counter mode 0 1 PWM mode 1 x Capture mode Select Timer 3 clock source. fx is main system clock frequency T3CK2 T3CK1 T3CK0 Description 0 0 0 fx/1 0 0 1 fx/2 0 1 0 fx/16 0 1 1 fx/64 1 0 0 fx/256 1 0 1 fx/512 1 1 0 fx/1024 1 1 1 External Clock (EC3) Clear Timer 3 Counter 0 No effect 1 Clear the Timer 3 counter (When write, automatically cleared “0” after being cleared counter) NOTE) Match Interrupt is generated in Capture mode. PS030002-0212 PRELIMINARY 136 Z51F3221 Product Specification TIFR (Timer Interrupt Flag Register) : C3H 7 6 5 4 3 2 1 0 SIOIFR – T3OVIFR T0OVIFR T3IFR T2IFR T1IFR T0IFR R/W – R/W R/W R/W R/W R/W SIOIFR T3OVIFR T0OVIFR T3IFR T2IFR T1IFR T0IFR PS030002-0212 R/W Initial value : 00H When SIO interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 SIO Interrupt no generation 1 SIO Interrupt generation When T3 Overflow interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 T3 Overflow Interrupt no generation 1 T3 Overflow Interrupt generation When T0 Overflow interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 T0 Overflow Interrupt no generation 1 T0 Overflow Interrupt generation When T3 interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 T3 Interrupt no generation 1 T3 Interrupt generation When T2 interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 T2 Interrupt no generation 1 T2 Interrupt generation When T1 interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 T1 Interrupt no generation 1 T1 Interrupt generation When T0 interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 T0 Interrupt no generation 1 T0 Interrupt generation PRELIMINARY 137 Z51F3221 Product Specification 11.9 Buzzer Driver 11.9.1 Overview The Buzzer consists of 8 bit counter, buzzer data register (BUZDR), and buzzer control register (BUZCR). The Square Wave (61.035Hz~125.0 kHz @8MHz) is outputted through P13/EC3/BUZO or P05/EINT5/EC3/BUZO pin. The buzzer data register (BUZDR) controls the bsuzzer frequency (look at the following expression). In buzzer control register (BUZCR), BUCK[1:0] selects source clock divided by prescaler. f BUZ (Hz)  Oscillator Frequency 2  Prescaler Ratio  (BUZDR  1) Table 11-12 Buzzer Frequency at 8 MHz BUZDR[7:0] Buzzer Frequency (kHz) BUZCR[2:1]=00 BUZCR[2:1]=01 BUZCR[2:1]=10 BUZCR[2:1]=11 0000_0000 125kHz 62.5kHz 31.25kHz 15.625kHz 0000_0001 62.5kHz 31.25kHz 15.625kHz 7.812kHz … … … … … 1111_1101 492.126Hz 246.063Hz 123.031Hz 61.515Hz 1111_1110 490.196Hz 245.098Hz 122.549Hz 61.274Hz 1111_1111 488.281Hz 244.141Hz 122.07Hz 61.035Hz 11.9.2 Block Diagram BUZEN fx/32 fx Pre scaler 8-bit Up-Counter fx/64 fx/128 MUX Clear Counter fx/256 F/F 2 BUCK[1:0] BUZO Comparator BUZDR Figure 11.25 Buzzer Driver Block Diagram PS030002-0212 PRELIMINARY 138 Z51F3221 Product Specification 11.9.3 Register Map Table 11-13 Buzzer Driver Register Map Name Address Dir Default Description BUZDR 8FH R/W FFH Buzzer Data Register BUZCR 96H R/W 00H Buzzer Control Register 11.9.4 Buzzer Driver Register Description Buzzer driver consists of buzzer data register (BUZDR), buzzer control register (BUZCR). 11.9.5 Register Description for Buzzer Driver BUZDR (Buzzer Data Register) : 8FH 7 6 5 4 3 2 1 0 BUZDR7 BUZDR6 BUZDR5 BUZDR4 BUZDR3 BUZDR2 BUZDR1 BUZDR0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH BUZDR[7:0] This bits control the Buzzer frequency Its resolution is 00H ~ FFH BUZCR (Buzzer Control Register) : 97H 7 6 5 4 3 2 1 0 – – – – – BUCK1 BUCK0 BUZEN – – – – – R/W R/W BUCK[1:0] BUZEN R/W Initial value : 00H Buzzer Driver Source Clock Selection BUCK1 BUCK0 Description 0 0 fx/32 0 1 fx/64 1 0 fx/128 1 1 fx/256 Buzzer Driver Operation Control 0 Buzzer Driver disable 1 Buzzer Driver enable NOTE) fx: System clock oscillation frequency. PS030002-0212 PRELIMINARY 139 Z51F3221 Product Specification 11.10 SIO 11.10.1 Overview The serial input/output is used to transmit/receive 8-bit data serially. The serial input/output(SIO) module is a useful serial interface to communicate with other peripheral of microcontroller devices. This SIO is 8-bit clock synchronous type and consists of SIO pre-scaler register, SIO data register, SIO control register, and control circuit as illustrated in Figure 11.25. The SO pin is designed to input and output. So SIO can operate with two pins minimally. Pin P14/SO, P15/SCK and P16/SI pins are controlled by the SIO control register (SIOCR) and port function selection control registers (PFSR05, PFSR0[7:6], and PFSR10). The contents of the SIO data register can be written into or read out by software. The data in the SIO data register can be shifted synchronously with the transfer clock signal. SIO data register (SIODR) is an 8 bit shift register. MSB-first and LSB-first transfers are possible. 11.10.2 Block Diagram INT_ACK Clear 3-Bit Counter Clear CLK CCLR CSEL SEDGE SIOP SIOM[1 :0] SCK fx To interrupt block SIOIFR Pre fx/4 scaler SIOPS M U X CLK 8-Bit SIO shift buffer (SIODR) SO DAT CSEL 1 SO 0 SI IOSW SIOM[1:0] Figure 11.26 SIO Block Diagram NOTE) The system clock should be greater than the SIO input clock. So, take care of using the external clock. PS030002-0212 PRELIMINARY 140 Z51F3221 Product Specification 11.10.3 SIO Pre-Scaler Register (SIOPS) SIOPS contains the SIO pre-scaler value. The SIO clock rate (baud rate) is calculated by the following fomula. Baud rate = Input clock (fx/4)/(Pre-scaler value + 1) or SCK input clock, where the input clock is fx/4 MSB SIOPS SIOPS7 R/W LSB SIOPS6 SIOPS5 R/W R/W SIOPS4 SIOPS3 SIOPS2 SIOPS 1 SIOPS0 R/W R/W R/W R/W R/W ADDRESS : B7H INITIAL VALUE: 0000 _0000 B Baud rate = (fx/4)/(SIOPS + 1) Figure 11.27 SIO Pre-Scaler Register (SIOPS) 11.10.4 The usage of SIO 1. Select transmitter/receiver mode. 2. In transmitter mode, write data to be sent to SIODR. 3. Set CCLR to “1” to clear SIO counter and start shifting. 4. If Tx or Rx is completed, the SiO interrupt is generated and SIOIFR is set to “1”. 5. In receiver mode, the received data can be acquired by reading SIODR. PS030002-0212 PRELIMINARY 141 Z51F3221 Product Specification 11.10.5 SIO Timing Diagram SCK [SEDGE=0] SO[P14] D7 D6 D5 D4 D3 D2 D1 D0 SI[P16] (IOSW = 0) D7 D6 D5 D4 D3 D2 D1 D0 IOSWIN [P14] (IOSW = 1) D7 D6 D5 D4 D3 D2 D1 D0 SIOIFR (SIO Int . Req) SIO status (CCLR = 1) Transmit Complete Figure 11.28 SIO Timing Diagram at SEDGE=0 SCK [SEDGE=1] SO[P14] D7 D6 D5 D4 D3 D2 D1 D0 SI[P16] (IOSW = 0) D7 D6 D5 D4 D3 D2 D1 D0 IOSWIN [P14] (IOSW = 1) D7 D6 D5 D4 D3 D2 D1 D0 SIOIFR (SIO Int . Req) SIO status (CCLR = 1) Transmit Complete Figure 11.29 SIO Timing Diagram at SEDGE=1 PS030002-0212 PRELIMINARY 142 Z51F3221 Product Specification 11.10.6 Register Map Table 11-14 SIO Register Map Name Address Dir Default Description SIOPS B7H R/W 00H SIO Pre-scaler Register SIODR B6H R/W 00H SPI Data Register SIOCR B5H R/W 00H SIO Control Register 11.10.7 SIO Register Description The SIO register consists of SIO pre-scaler register (SIOPS), SIO sata Register (SIODR), and SIO control register (SIOCR). The SIOIFR bit is in the timer interrupt flag register (TIFR). 11.10.8 Register Description for SIO SIOPS (SIO Pre-scaler Register) : B7H 7 6 5 4 3 2 1 0 SIOPS7 SIOPS6 SIOPS5 SIOPS4 SIOPS3 SIOPS2 SIOPS1 SIOPS0 R/W R/W R/W R/W R/W R/W R/W SIOPS [7:0] R/W Initial value : 00H SIO Pre-scaler Baud Rate = (fx/4)/(SIOPS+1) SIODR (SIO Data Register) : B6H 7 6 5 4 3 2 1 0 SIODR7 SIODR6 SIODR5 SIODR4 SIODR3 SIODR2 SIODR1 SIODR0 R/W R/W R/W R/W R/W R/W R/W SIODR [7:0] PS030002-0212 R/W Initial value : 00H SIO Data PRELIMINARY 143 Z51F3221 Product Specification SIOCR (SIO Control Register) : B5H 7 6 5 4 3 2 1 0 CSEL DAT SIOP IOSW SIOM1 SIOM0 CCLR SEDGE R/W R/W R/W R/W R/W R/W R/W CSEL DAT SIOP IOSW R/W Initial value : 00H SIO Shift Clock Selection 0 Internal clock (P.S clock) 1 External clock (SCK) Data Direction Control 0 MSB first mode 1 LSB first mode SIO Shift Operation Enable 0 Disable shifter and clock counter 1 Enable shifter and clock counter Serial Input Pin Selection Bit 0 SI pin selection 1 SO pin selection NOTE) If SO pin is selected for a serial data input, SO pin should be set to an input and port. So, the SIOM, PFSR05, and P14IO bits should be set to ‘01b’, ‘0b’ and ‘0b’ respectively. Refer to the P1IO and PFSR0 register for setting SIOM[1:0] CCLR SEDGE SIO Mode Selection SIOM1 SIOM0 Description 0 0 Transmit mode 0 1 Receive mode 1 x Transmit/Receive mode SIO Counter Clear and Shift Start 0 No action 1 Clear 3-bit counter and start shifting SIO Clock Edge Selection 0 Tx at falling edges, Rx at rising edges 1 Tx at rising edge, Rx at falling edges NOTE) The serial I/O interrupt flag (SIOIFR bit) is in the timer interrupt flag register (TIFR register). PS030002-0212 PRELIMINARY 144 Z51F3221 Product Specification 11.11 12-Bit A/D Converter 11.11.1 Overview The analog-to-digital converter (A/D) allows conversion of an analog input signal to corresponding 12-bit digital value. The A/D module has eight analog inputs. The output of the multiplexer is the input into the converter which generates the result through successive approximation. The A/D module has four registers which are the A/D converter control high register (ADCCRH), A/D converter control low register (ADCCRL), A/D converter data high register (ADCDRH), and A/D converter data low register (ADCDRL). The channels to be converted are selected by setting ADSEL[3:0]. To execute A/D conversion, ADST bit should be set to ‘1’. The register ADCDRH and ADCDRL contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCDRH and ADCDRL, the A/D conversion status bit AFLAG is set to ‘1’, and the A/D interrupt is set. During A/D conversion, AFLAG bit is read as ‘0’. 11.11.2 Conversion Timing The A/D converstion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set up A/D conversion. Therefore, total of 58 clocks are required to complete a 12-bit conversion: When fxx/8 is selected for conversion clock with a 12MHz fxx clock frequency, one clock cycle is 0.66 μs. Each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit × 12 bits + set-up time = 58 clocks, 58 clock × 0.66 μs = 38.28 μs at 1.5 MHz (12 MHz/8) NOTE : The A/D converter needs at least 20 μs for conversion time. So you must set the conversion time more than 20 μs. 11.11.3 Block Diagram ADSEL[3:0] (Select one input pin of the assigned pins) Clock Selector ADCLK AN0 AN1 AN2 Input Pins AN6 AN7 ADST Clear AFLAG M U X + - Comparator Control Logic ADCIFR To interrupt block Clear INT_ACK Reference Voltage ADCDRH (R), ADCDRL (R) AVREF/VDD AVSS Figure 11.30 12-bit ADC Block Diagram PS030002-0212 PRELIMINARY 145 Z51F3221 Product Specification AN0~ AN7 Analog Input Analog Power Input 0~1000pF AVREF 22uF Figure 11.31 A/D Analog Input Pin with Capacitor Figure 11.32 A/D Power (AVDD) Pin with Capacitor 11.11.4 ADC Operation Align bit set“0” ADCO11 ADCO10 ADCDRH7 ADCDRH6 ADCO9 ADCO8 ADCDRH5 ADCDRH4 ADCO7 ADCO6 ADCDRH3 ADCDRH2 ADCO5 ADCO4 ADCDRH1 ADCDRH0 ADCO3 ADCO2 ADCO1 ADCO0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRH[7:0] ADCDRL[7:4 ] ADCDRL[3 :0] bits are “0 ” Align bit set“1” ADCO11 ADCO10 ADCDRH3 ADCDRH2 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRL3 ADCDRL2 ADCDRL1 ADCDRL0 ADCDRL[7:0] ADCDRL[3:0] ADCDRL[7:4] bits are “0” Figure 11.33 ADC Operation for Align Bit PS030002-0212 PRELIMINARY 146 Z51F3221 Product Specification SET ADCCRH Select ADC Clock and Data Align Bit. SET ADCCRL ADC enable & Select AN Input Channel. Converting START N Start ADC Conversion. If Conversion is completed, AFLAG is set “1” and ADC interrupt is occurred. AFLAG = 1? Y After Conversion is completed, read ADCDRH and ADCDRL. READ ADCDRH/L ADC END Figure 11.34 A/D Converter Operation Flow 11.11.5 Register Map Table 11-15 ADC Register Map Name Address Dir Default Description ADCDRH 9CH R xxH A/D Converter Data High Register ADCDRL 9BH R xxH A/D Converter Data Low Register ADCCRH 9DH R/W 00H A/D Converter Control High Register ADCCRL 9AH R/W 00H A/D Converter Control Low Register 11.11.6 ADC Register Description The ADC register consists of A/D converter data high register (ADCDRH), A/D converter data low register (ADCDRL), A/D converter control high register (ADCCRH), and A/D converter control low register (ADCCRL). 11.11.7 Register Description for ADC ADCDRH (A/D Converter Data High Register) : 9CH 7 PS030002-0212 6 5 4 3 PRELIMINARY 2 1 0 147 Z51F3221 Product Specification ADDM11 ADDM10 ADDM9 ADDM8 ADDM7 ADDL11 ADDM6 ADDL10 ADDM5 ADDL9 R R R R R R R ADDM[11:4] MSB align, A/D Converter High Data (8-bit) ADDL[11:8] LSB align, A/D Converter High Data (4-bit) ADDM4 ADDL8 R Initial value : xxH ADCDRL (A/D Converter Data Low Register) : 9BH 7 6 5 4 3 2 1 0 ADDM3 ADDL7 ADDM2 ADDL6 ADDM1 ADDL5 ADDM0 ADDL4 ADDL3 ADDL2 ADDL1 ADDL0 R R R R R- R R ADDM[3:0] MSB align, A/D Converter Low Data (4-bit) ADDL[7:0] LSB align, A/D Converter Low Data (8-bit) R Initial value : xxH ADCCRH (A/D Converter High Register) : 9DH 7 6 5 4 3 2 1 0 ADCIFR – – – – ALIGN CKSEL1 CKSEL0 R/W – – – – R/W R/W ADCIFR ALIGN CKSEL[1:0] PS030002-0212 R/W Initial value : 00H When ADC interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 ADC Interrupt no generation 1 ADC Interrupt generation A/D Converter data align selection. 0 MSB align (ADCDRH[7:0], ADCDRL[7:4]) 1 LSB align (ADCRDH[3:0], ADCDRL[7:0]) A/D Converter Clock selection CKSEL1 CKSEL0 Description 0 0 fx/1 0 1 fx/2 1 0 fx/4 1 1 fx/8 PRELIMINARY 148 Z51F3221 Product Specification ADCCRL (A/D Converter Counter Low Register) : 9AH 7 6 5 4 3 2 1 0 STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 R/W R/W R/W R R/W R/W R/W STBY ADST REFSEL AFLAG ADSEL[3:0] R/W Initial value : 00H Control Operation of A/D (The ADC module is automatically disabled at stop mode) 0 ADC module disable 1 ADC module enable Control A/D Conversion stop/start. 0 No effect 1 ADC Conversion Start and auto clear A/D Converter Reference Selection 0 Internal Reference (VDD) 1 External Reference (AVREF) A/D Converter Operation State (This bit is cleared to ‘0’ when the STBY bit is set to ‘0’ or when the CPU is at STOP mode) 0 During A/D Conversion 1 A/D Conversion finished A/D Converter input selection ADSEL3 ADSEL2 ADSEL1 ADSEL0 Description 0 0 0 0 AN0 0 0 0 1 AN1 0 0 1 0 AN2 0 0 1 1 AN3 0 1 0 0 AN4 0 1 0 1 AN5 0 1 1 0 AN6 0 1 1 1 AN7 Other values: Not available PS030002-0212 PRELIMINARY 149 Z51F3221 Product Specification 11.12 UART 11.12.1 Overview The universal synchronous and asynchronous serial receiver and transmitter (UART) is a highly flexible serial communication device. The main features are listed below. - Full Duplex Operation (Independent Serial Receive and Transmit Registers) - Asynchronous or Synchronous Operation - Baud Rate Generator - Supports Serial Frames with 5,6,7,8, or 9 Data Bits and 1 or 2 Stop Bits - Odd or Even Parity Generation and Parity Check Supported by Hardware - Data OverRun Detection - Framing Error Detection - Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete UART has two main parts of clock generator, transmitter and receiver. The clock generation logic consists of synchronization logic for external clock input used by synchronous operation, and the baud rate generator for asynchronous or master synchronous operation. The Transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats. The write buffer allows continuous transfer of data without any delay between frames. The receiver is the most complex part of the UART module due to its clock and data recovery units. The recovery unit is used for asynchronous data reception. In addition to the recovery unit, the receiver includes a parity checker, a shift register, a two-level receive FIFO (UARTDR) and control logic. The receiver supports the same frame formats as the transmitter and can detect frame error, data overrun and parity errors. PS030002-0212 PRELIMINARY 150 Z51F3221 Product Specification 11.12.2 Block Diagram Master ACK Control ACK UARTBD UMSEL[6 ] SCLK To interrupt block WAKEIE WAKE Baud Rate Generator RXCIE At Stop mode Low level detector RXD Clock Sync Logic RXC M U X Rx Control Clock Recovery LOOPS Stop bit Generator Tx Control TXD INT_ACK Clear TXC TXCIE Data Recovery Receive Shift Register (RXSR) M U X DOR/PE/FE Checker UARTDR[0] (Rx) UMSEL[6] UARTDR[1] (Rx) UPM0 I N T E R N A L B U S L I N E UMSEL[6] Parity Generator M U X Transmit Shift Register (TXSR) UPM1 M U X Empty signal UDRE UARTDR(Tx) UDRIE To interrupt block Figure 11.35 UART Block Diagram PS030002-0212 PRELIMINARY 151 Z51F3221 Product Specification 11.12.3 Clock Generation UARTBD fSCLK Prescaling Up-Counter (UBAUD+1) /8 /2 taclk SCLK MASTER Sync Generator UMSEL ACK /2 raclk Figure 11.36 Clock Generation Block Diagram The clock generation logic generates the base clock for the transmitter and receiver. The UART supports three modes of clock operation and those are asynchronous, master synchronous and slave synchronous mode. The UMSEL bit in UARTCR1 register selects asynchronous or synchronous operation. The MASTER bit in UARTCR3 register controls whether the clock source is internal (master mode, output pin) or external (slave mode, input pin). The ACK pin is active only when the UART operates in synchronous mode. Following table shows the equations for calculating the baud rate (in bps). Table 11-16 Equations for Calculating Baud Rate Register Setting Operating Mode Equation for Calculating Baud Rate Asynchronous Normal Mode Baud Rate fx 16 UARTBD 1 Synchronous Master Mode Baud Rate fx 2 UARTBD 1 11.12.4 External Clock (ACK) External clocking is used in the synchronous mode of operation. External clock input from the ACK pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver. This process introduces two CPU clock period delay. The maximum frequency of the external ACK pin is limited up-to 1MHz. PS030002-0212 PRELIMINARY 152 Z51F3221 Product Specification 11.12.5 Synchronous mode operation When synchronous mode is used, the ACK pin will be used as either clock input (slave) or clock output (master). Data sampling and transmitter is issued on the different edge of ACK clock each other. For example, if data input on RXD pin is sampled on the rising edge of ACK clock, data output on TXD pin is altered on the falling edge. The UCPOL bit in UARTCR1 register selects which ACK clock edge is used for data sampling and which is used for data change. As shown in the figure below, when UCPOL is zero, the data will be changed at rising ACK edge and sampled at falling ACK edge. UCPOL = 1 ACK TXD/RXD Sample UCPOL = 0 ACK TXD/RXD Sample Figure 11.37 Synchronous Mode ACK Timing PS030002-0212 PRELIMINARY 153 Z51F3221 Product Specification 11.12.6 Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error detection. The UART supports all 30 combinations of the following as valid frame formats. - 1 start bit - 5, 6, 7, 8 or 9 data bits - no, even or odd parity bit - 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit (LSB). Then the next data bits, up to nine, are succeeding, ending with the most significant bit (MSB). If parity function is enabled, the parity bit is inserted between the last data bit and the stop bit. A high-to-low transition on data pin is considered as start bit. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle state. The idle means high state of data pin. The following figure shows the possible combinations of the frame formats. Bits inside brackets are optional. 1 data frame Idle St D0 D1 D2 D3 D4 [D5] [D6] [D7] [D8] [P] Sp1 [Sp2] Idle / St Character bits Figure 11.38 Frame Format 1 data frame consists of the following bits • Idle No communication on communication line (TxD/RxD) • St Start bit (Low) • Dn Data bits (0~8) • Parity bit ------------ Even parity, Odd parity, No parity • Stop bit(s) ---------- 1 bit or 2 bits The frame format used by the UART is set by the USIZE[2:0], UPM[1:0] and USBS bits in UARTCR1 and UARTCR3 register. The Transmitter and Receiver use the same setting. 11.12.7 Parity bit The parity bit is calculated by doing an exclusive-OR of all the data bits. If odd parity is used, the result of the exclusive-O is inverted. The parity bit is located between the MSB and first stop bit of a serial frame. Peven = Dn-1 ^ … ^ D3 ^ D2 ^ D1 ^ D0 ^ 0 Podd = Dn-1 ^ … ^ D3 ^ D2 ^ D1 ^ D0 ^ 1 Peven : Parity bit using even parity Podd : Parity bit using odd parity Dn : Data bit n of the character PS030002-0212 PRELIMINARY 154 Z51F3221 Product Specification 11.12.8 UART Transmitter The UART transmitter is enabled by setting the TXE bit in UARTCR2 register. When the Transmitter is enabled, the TXD pin should be set to TXD function for the serial output pin of UART by the PFSR6[7:6] or PFSR8[5:4]. The baud-rate, operation mode and frame format must be setup once before doing any transmission. In synchronous operation mode, the ACK pin is used as transmission clock, so it should be selected to do ACK function by PFSR6[5:4] or PFSR8[3:2]. 11.12.8.1 Sending Tx data A data transmission is initiated by loading the transmit buffer (UARTDR register I/O location) with the data to be transmitted. The data written in transmit buffer is moved to the shift register when the shift register is ready to send a new frame. The shift register is loaded with the new data if it is in idle state or immediately after the last stop bit of the previous frame is transmitted. When the shift register is loaded with new data, it will transfer one complete frame according to the settings of control registers. If the 9-bit characters are used in asynchronous or synchronous operation mode, the ninth bit must be written to the TX8 bit in UARTCR3 register before it is loaded to the transmit buffer (UARTDR register). 11.12.8.2 Transmitter flag and interrupt The UART transmitter has 2 flags which indicate its state. One is UART data register empty flag (UDRE) and the other is transmit complete flag (TXC). Both flags can be interrupt sources. UDRE flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty and cleared when the transmit buffer contains data to be transmitted but has not yet been moved into the shift register. And also this flag can be cleared by writing ‘0’ to this bit position. Writing ‘1’ to this bit position is prevented. When the data register empty interrupt enable (UDRIE) bit in UARTCR2 register is set and the global interrupt is enabled, UARTST data register empty interrupt is generated while UDRE flag is set. The transmit complete (TXC) flag bit is set when the entire frame in the transmit shift register has been shifted out and there is no more data in the transmit buffer. The TXC flag is automatically cleared when the transmit complete interrupt service routine is executed, or it can be cleared by writing ‘0’ to TXC bit in UARTST register. When the transmit complete interrupt enable (TXCIE) bit in UARTCR2 register is set and the global interrupt is enabled, UART transmit complete interrupt is generated while TXC flag is set. PS030002-0212 PRELIMINARY 155 Z51F3221 Product Specification 11.12.8.3 Parity Generator The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled (UPM[1]=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the frame to be sent. 11.12.8.4 Disabling Transmitter Disabling the transmitter by clearing the TXE bit will not become effective until ongoing transmission is completed. When the Transmitter is disabled, the TXD pin can be used as a normal general purpose I/O (GPIO). 11.12.9 UART Receiver The UART receiver is enabled by setting the RXE bit in the UARTCR2 register. When the receiver is enabled, the RXD pin should be set to RXD function for the serial input pin of UART by PFSR7[1:0] or PFSR8[7:6]. The baud-rate, mode of operation and frame format must be set before serial reception. In synchronous operation mode the ACK pin is used as transfer clock, so it should be selected to do ACK function by PFSR6[5:4] or PFSR8[3:2]. 11.12.9.1 Receiving Rx data When UART is in synchronous or asynchronous operation mode, the receiver starts data reception when it detects a valid start bit (LOW) on RXD pin. Each bit after start bit is sampled at pre-defined baud-rate (asynchronous) or sampling edge of ACK (synchronous), and shifted into the receive shift register until the first stop bit of a frame is received. Even if there’s 2nd stop bit in the frame, the 2nd stop bit is ignored by the receiver. That is, receiving the first stop bit means that a complete serial frame is present in the receiver shift register and contents of the shift register are to be moved into the receive buffer. The receive buffer is read by reading the UARTDR register. If 9-bit characters are used (USIZE[2:0] = “111”), the ninth bit is stored in the RX8 bit position in the UARTCR3 th register. The 9 bit must be read from the RX8 bit before reading the low 8 bits from the UARTDR register. Likewise, the error flags FE, DOR, PE must be read before reading the data from UARTDR register. It’s because the error flags are stored in the same FIFO position of the receive buffer. PS030002-0212 PRELIMINARY 156 Z51F3221 Product Specification 11.12.9.2 Receiver Flag and Interrupt The UART receiver has one flag that indicates the receiver state. The receive complete (RXC) flag indicates whether there are unread data in the receive buffer. This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty. If the receiver is disabled (RXE=0), the receiver buffer is flushed and the RXC flag is cleared. When the receive complete interrupt enable (RXCIE) bit in the UARTCR2 register is set and global interrupt is enabled, the UART receiver complete interrupt is generated while RXC flag is set. The UART receiver has three error flags which are frame error (FE), data overrun (DOR) and parity error (PE). These error flags can be read from the UARTST register. As received data are stored in the 2-level receive buffer, these error flags are also stored in the same position of receive buffer. So, before reading received data from UARTDR register, read the UARTST register first which contains error flags. The frame error (FE) flag indicates the state of the first stop bit. The FE flag is ‘0’ when the stop bit was correctly detected as “1”, and the FE flag is “1” when the stop bit was incorrect, i.e. detected as “0”. This flag can be used for detecting out-of-sync conditions between data frames. The data overrun (DOR) flag indicates data loss due to a receive buffer full condition. DOR occurs when the receive buffer is full, and another new data is present in the receive shift register which are to be stored into the receive buffer. After the DOR flag is set, all the incoming data are lost. To prevent data loss or clear this flag, read the receive buffer. The parity error (PE) flag indicates that the frame in the receive buffer had a parity error when received. If parity check function is not enabled (UPM[1]=0), the PE bit is always read “0”. 11.12.9.3 Parity Checker If parity bit is enabled (UPM[1]=1), the Parity Checker calculates the parity of the data bits in incoming frame and compares the result with the parity bit from the received serial frame. 11.12.9.4 Disabling Receiver In contrast to transmitter, disabling the Receiver by clearing RXE bit makes the Receiver inactive immediately. When the receiver is disabled, the receiver flushes the receive buffer, the remaining data in the buffer is all reset, and the RXD pin can be used as a normal general purpose I/O (GPIO). PS030002-0212 PRELIMINARY 157 Z51F3221 Product Specification 11.12.9.5 Asynchronous Data Reception To receive asynchronous data frame, the UART includes a clock and data recovery unit. The clock recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the RXD pin. The data recovery logic samples and low pass filters the incoming bits, and this removes the noise of RXD pin. The next figure illustrates the sampling process of the start bit of an incoming frame. The sampling rate is 16 times of the baud-rate in normal mode. The horizontal arrows show the synchronization variation due to the asynchronous sampling process. RXD START IDLE BIT0 Sample 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Figure 11.39 Start Bit Sampling When the receiver is enabled (RXE=1), the clock recovery logic tries to find a high-to-low transition on the RXD line, the start bit condition. After detecting high to low transition on RXD line, the clock recovery logic uses samples 8,9, and 10 for normal mode to decide if a valid start bit is received. If more than 2 samples have logical low level, it is considered that a valid start bit is detected and the internally generated clock is synchronized to the incoming data frame. And the data recovery can begin. The synchronization process is repeated for each start bit. As described above, when the receiver clock is synchronized to the start bit, the data recovery can begin. Data recovery process is almost similar to the clock recovery process. The data recovery logic samples 16 times for each incoming bits, and uses sample 8, 9, and 10 to decide data value. If more than 2 samples have low levels, the received bit is considered to a logic ‘0’ and if more than 2 samples have high levels, the received bit is considered to a logic ‘1’. The data recovery process is then repeated until a complete frame is received including the first stop bit. The decided bit value is stored in the receive shift register in order. Note that the Receiver only uses the first stop bit of a frame. Internally, after receiving the first stop bit, the Receiver is in idle state and waiting to find start bit. BIT n RXD Sample 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 Figure 11.40 Sampling of Data and Parity Bit PS030002-0212 PRELIMINARY 158 Z51F3221 Product Specification The process for detecting stop bit is like clock and data recovery process. That is, if 2 or more samples of 3 center values have high level, correct stop bit is detected, else a frame error (FE) flag is set. After deciding whether the first stop bit is valid or not, the Receiver goes to idle state and monitors the RXD line to check a valid high to low transition is detected (start bit detection). STOP RXD (A) (B) (C) Sample 1 2 3 4 5 6 7 8 9 10 11 12 13 Figure 11.41 Stop Bit Sampling and Next Start Bit Sampling 11.12.10 Register Map Table 11-17 UART Register Map Name Address Dir Default Description UARTBD E6H R/W FFH UART Baud Rate Generation Register UARTDR E7H R/W 00H UART Data Register UARTCR1 E2H R/W 00H UART Control Register 1 UARTCR2 E3H R/W 00H UART Control Register 2 UARTCR3 E4H R/W 00H UART Control Register 3 UARTST E5H R/W 80H UART Status Register 11.12.11 UART Register Description UART module consists of UART baud rate generation register (UARTBD), UART data register (UARTDR), UART control register 1 (UARTCR1), UART control register 2 (UARTCR2) ,UART control register 3 (UARTCR3), and UART status register (UARTST). 11.12.12 Register Description for UART UARTBD (UART Baud Rate Generation Register) : E6H 7 6 5 4 3 2 1 0 UARTBD7 UARTBD6 UARTBD5 UARTBD4 UARTBD3 UARTBD2 UARTBD1 UARTBD0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH UARTBD [7:0] The value in this register is used to generate internal baud rate in asynchronous mode. To prevent malfunction, do not write ‘0’ in asynchronous mode. PS030002-0212 PRELIMINARY 159 Z51F3221 Product Specification UARTDR (UART Data Register) : E7H 7 6 5 4 3 2 1 0 UARTDR7 UARTDR6 UARTDR5 UARTDR4 UARTDR3 UARTDR2 UARTDR1 UARTDR0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 00H UARTDR [7:0] The UART Transmit Buffer and Receive Buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the UARTDR register. Reading the UDATA register returns the contents of the Receive Buffer. Write this register only when the UDRE flag is set. UARTCR1 (UART Control Register 1) : E2H 7 6 5 4 3 2 1 0 – UMSEL UPM1 UPM0 USIZE2 USIZE1 USIZE0 UCPOL – R/W R/W R/W R/W R/W R/W UMSEL UPM[1:0] USIZE[2:0] UCPOL PS030002-0212 R/W Initial value : 00H Selects Operation Mode of UART 0 Asynchronous Mode 1 Synchronous Mode Selects Parity Generation and Check methods UPM1 UPM0 Parity 0 0 No Parity 0 1 Reserved 1 0 Even Parity 1 1 Odd Parity Selects the Length of Data Bits in Frame USIZE2 USIZE1 USIZE0 Data Length 0 0 0 5 bit 0 0 1 6 bit 0 1 0 7 bit 0 1 1 8 bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9 bit Selects Polarity of ACK in Synchronous Mode 0 TXD change @Rising Edge, RXD change @Falling Edge 1 TXD change @Falling Edge, RXD change @Rising Edge PRELIMINARY 160 Z51F3221 Product Specification UARTCR2 (UART Control Register 2) : E3H 7 6 5 4 3 2 1 0 UDRIE TXCIE RXCIE WAKEIE TXE RXE UARTEN U2X R/W R/W R/W R/W R/W R/W R/W UDRIE TXCIE RXCIE WAKEIE TXE RXE UARTEN U2X PS030002-0212 R/W Initial value : 00H Interrupt enable bit for UART Data Register Empty 0 Interrupt from UDRE is inhibited (use polling) 1 When UDRE is set, request an interrupt Interrupt enable bit for Transmit Complete 0 Interrupt from TXC is inhibited (use polling) 1 When TXC is set, request an interrupt Interrupt enable bit for Receive Complete 0 Interrupt from RXC is inhibited (use polling) 1 When RXC is set, request an interrupt Interrupt enable bit for Asynchronous Wake in STOP mode. When device is in stop mode, if RXD goes to LOW level an interrupt can be requested to wake-up system. At that time the UDRIE bit and UARTST register value should be set to ‘0b’ and “00H”, respectively. 0 Interrupt from Wake is inhibited 1 When WAKE is set, request an interrupt Enables the transmitter unit 0 Transmitter is disabled 1 Transmitter is enabled Enables the receiver unit 0 Receiver is disabled 1 Receiver is enabled Activate UART module by supplying clock. When one of TXE and RXE values is “1”, the UARTEN bit always set to “1”. 0 USART is disabled (clock is halted) 1 USART is enabled This bit only has effect for the asynchronous operation and selects receiver sampling rate. 0 Normal asynchronous operation 1 Double Speed asynchronous operation PRELIMINARY 161 Z51F3221 Product Specification UARTCR3 (UART Control Register 3) : E4H 7 6 5 4 3 2 1 0 MASTER LOOPS DISACK – – USBS TX8 RX8 R/W R/W R/W – – R/W R/W MASTER LOOPS DISACK USBS TX8 RX8 PS030002-0212 R Initial value : 00H Selects master or slave in Synchronous mode operation and controls the direction of ACK pin 0 Slave mode operation and ACK is input pin. 1 Master mode operation and ACK is output pin Controls the Loop Back Mode of UART, for test mode 0 Normal operation 1 Loop Back mode In Synchronous mode of operation, selects the waveform of ACK output 0 ACK is free-running while UART is enabled in synchronous master mode 1 ACK is active while any frame is on transferring Selects the length of stop bit. 0 1 Stop Bit 1 2 Stop Bit The ninth bit of data frame in UART. Write this bit first before loading the UARTDR register th 0 MSB (9 bit) to be transmitted is ‘0’ 1 MSB (9 bit) to be transmitted is ‘1’ th The ninth bit of data frame in UART. Read this bit first before reading the receive buffer 0 MSB (9th bit) received is ‘0’ 1 MSB (9th bit) received is ‘1’ PRELIMINARY 162 Z51F3221 Product Specification UARTST (UART Status Register) : E5H 7 6 5 4 3 2 UDRE TXC RXC WAKE SOFTRST DOR FE R/W R/W R R/W R/W R R/W UDRE TXC RXC WAKE SOFTRST DOR FE PE PS030002-0212 1 0 PE R/W Initial value : 80H The UDRE flag indicates if the transmit buffer (UARTDR) is ready to receive new data. If UDRE is ‘1’, the buffer is empty and ready to be written. This flag can generate a UDRE interrupt. 0 Transmit buffer is not empty. 1 Transmit buffer is empty. This flag is set when the entire frame in the transmit shift register has been shifted out and there is no new data currently present in the transmit buffer. This flag is automatically cleared when the interrupt service routine of a TXC interrupt is executed. This flag can generate a TXC interrupt. This bit is automatically cleared. 0 Transmission is ongoing. 1 Transmit buffer is empty and the data in transmit shift register are shifted out completely. This flag is set when there are unread data in the receive buffer and cleared when all the data in the receive buffer are read. The RXC flag can be used to generate a RXC interrupt. 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer This flag is set when the RX pin is detected low while the CPU is in stop mode. This flag can be used to generate a WAKE interrupt. This bit is set only when in asynchronous mode of operation. This bit should be cleared by program software. 0 No WAKE interrupt is generated. 1 WAKE interrupt is generated This is an internal reset and only has effect on UART. Writing ‘1’ to this bit initializes the internal logic of UART and this bit is automatically cleared. 0 No operation 1 Reset UART This bit is set if a Data OverRun occurs. While this bit is set, the incoming data frame is ignored. This flag is valid until the receive buffer is read. 0 No Data OverRun 1 Data OverRun detected This bit is set if the first stop bit of next character in the receive buffer is detected as ‘0’. This bit is valid until the receive buffer is read. 0 No Frame Error 1 Frame Error detected This bit is set if the next character in the receive buffer has a Parity Error to be received while Parity Checking is enabled. This bit is valid until the receive buffer is read. 0 No Parity Error 1 Parity Error detected PRELIMINARY 163 Z51F3221 Product Specification 11.12.13 Baud Rate setting (example) Table 11-18 Examples of UARTBD Settings for Commonly Used Oscillator Frequencies fx=1.00MHz fx=1.8432MHz fx=2.00MHz Baud Rate UARTBD ERROR UARTBD ERROR UARTBD ERROR 2400 25 0.2% 47 0.0% 51 0.2% 4800 12 0.2% 23 0.0% 25 0.2% 9600 6 -7.0% 11 0.0% 12 0.2% 14.4k 3 8.5% 7 0.0% 8 -3.5% 19.2k 2 8.5% 5 0.0% 6 -7.0% 28.8k 1 8.5% 3 0.0% 3 8.5% 38.4k 1 -18.6% 2 0.0% 2 8.5% 57.6k - - 1 -25.0% 1 8.5% 76.8k - - 1 0.0% 1 -18.6% 115.2k - - - - - - 230.4k - - - - - - (continued) fx=3.6864MHz fx=4.00MHz fx=7.3728MHz Baud Rate UARTBD ERROR UARTBD ERROR UARTBD ERROR 2400 95 0.0% 103 0.2% 191 0.0% 4800 47 0.0% 51 0.2% 95 0.0% 9600 23 0.0% 25 0.2% 47 0.0% 14.4k 15 0.0% 16 2.1% 31 0.0% 19.2k 11 0.0% 12 0.2% 23 0.0% 28.8k 7 0.0% 8 -3.5% 15 0.0% 38.4k 5 0.0% 6 -7.0% 11 0.0% 57.6k 3 0.0% 3 8.5% 7 0.0% 76.8k 2 0.0% 2 8.5% 5 0.0% 115.2k 1 0.0% 1 8.5% 3 0.0% 230.4k - - - - 1 0.0% 250k - - - - 1 -7.8% 0.5M - - - - - - (continued) fx=8.00MHz fx=11.0592MHz Baud Rate UARTBD ERROR UARTBD 2400 207 0.2% - - 4800 103 0.2% 143 0.0% ERROR 9600 51 0.2% 71 0.0% 14.4k 34 -0.8% 47 0.0% 19.2k 25 0.2% 35 0.0% 28.8k 16 2.1% 23 0.0% 38.4k 12 0.2% 17 0.0% 57.6k 8 -3.5% 11 0.0% 76.8k 6 -7.0% 8 0.0% 115.2k 3 8.5% 5 0.0% 230.4k 1 8.5% 2 0.0% 250k 1 0.0% 2 -7.8% 0.5M - - - - 1M - - - - PS030002-0212 PRELIMINARY 164 Z51F3221 Product Specification 11.13 LCD Driver 11.13.1 Overview The LCD driver is controlled by the LCD Control Register (LCDCRH/L). The LCLK[1:0] determines the frequency of COM signal scanning of each segment output. A RESET clears the LCD control register LCDCRH and LCDCRL values to logic ‘0’. The LCD display can continue operating during IDLE and STOP modes if a sub-frequency clock is used as system clock source. The clock and duty for LCD driver is automatically initialized by hardware, whenever LCDCRH register data value is rewritten. So, don’t rewrite LCDCRH frequently. PS030002-0212 PRELIMINARY 165 Z51F3221 Product Specification 11.13.2 LCD Display RAM Organization Display data are stored to the display data area in the external data memory. The display data which stored to the display external data area (address 0000H-0027H) are read automatically and sent to the LCD driver by the hardware. The LCD driver generates the segment signals and common signals in accordance with the display data and drive method. Therefore, display patterns can be changed by only overwriting the contents of the display external data area with a program. Figure 11-41 shows the correspondence between the display external data area and the COM/SEG pins. The LCD is turned on when the display data is “1” and turned off when “0”. SEG 39 0027 H SEG38 0026 H SEG37 0025 H SEG36 0024 H SEG35 0023 H SEG34 0022 H SEG33 0021 H SEG32 0020 H SEG 7 0007 H SEG 6 0006 H SEG 5 0005 H SEG 4 0004 H SEG 3 0003 H SEG 2 0002 H SEG 1 0001 H SEG 0 0000 H bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 C O M 0 C O M 1 C O M 2 C O M 3 C O M 4 C O M 5 C O M 6 C O M 7 Figure 11.42 LCD Circuit Block Diagram PS030002-0212 PRELIMINARY 166 Z51F3221 Product Specification 11.13.3 LCD Signal Waveform COM0 0 1 0 1 VDD SEG0 VSS 1 Frame COM1 VLC0 COM0 VLC2 VSS SEG1 SEG2 SEG3 VLC0 COM1 VLC2 VSS VLC0 SEG0 VLC2 VSS VLC0 VLC2 SEG1 VSS +VLC0 +VLC2 VSS COM0-SEG0 -VLC2 -VLC0 Figure 11.43 LCD Signal Waveforms (1/2Duty, 1/2Bias) PS030002-0212 PRELIMINARY 167 Z51F3221 Product Specification SEG3 SEG2 SEG1 0 1 2 0 1 2 VDD VSS COM0 1 Frame VLC0 COM1 VLC1 COM0 VLC2(VLC3) VSS COM2 VLC0 VLC1 COM1 VLC2(VLC3) VSS VLC0 VLC1 COM2 VLC2(VLC3) VSS VLC0 VLC1 SEG1 VLC2(VLC3) VSS VLC0 VLC1 SEG2 VLC2(VLC3) VSS +VLC0 +VLC1 +VLC2(VLC3) COM0-SEG1 VSS -VLC2(VLC3) -VLC1 -VLC0 Figure 11.44 LCD Signal Waveforms (1/3Duty, 1/3Bias) PS030002-0212 PRELIMINARY 168 Z51F3221 Product Specification SEG3 SEG2 0 1 2 3 0 1 2 3 VDD VSS COM0 1 Frame COM1 COM2 VLC0 VLC1 COM0 VLC2(VLC3) VSS COM3 VLC0 VLC1 COM1 VLC2(VLC3) VSS VLC0 VLC1 COM2 VLC2(VLC3) VSS VLC0 VLC1 SEG2 VLC2(VLC3) VSS VLC0 VLC1 SEG3 VLC2(VLC3) VSS +VLC0 +VLC1 +VLC2(VLC3) COM0-SEG2 VSS -VLC2(VLC3) -VLC1 -VLC0 Figure 11.45 LCD Signal Waveforms (1/4Duty, 1/3Bias) PS030002-0212 PRELIMINARY 169 Z51F3221 Product Specification COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 VDD VSS 1 Frame S E G 6 S E G 7 S E G 8 S E G 9 S E G 1 0 COM0 VLC0 VLC1 VLC2 VLC3 VSS COM1 VLC0 VLC1 VLC2 VLC3 VSS COM2 VLC0 VLC1 VLC2 VLC3 VSS SEG6 VLC0 VLC1 VLC2 VLC3 VSS SEG7 VLC0 VLC1 VLC2 VLC3 VSS +VLC0 +VLC1 +VLC2 +VLC3 VSS -VLC3 -VLC2 -VLC1 -VLC0 COM0-SEG6 Figure 11.46 LCD Signal Waveforms (1/8Duty, 1/4Bias) PS030002-0212 PRELIMINARY 170 Z51F3221 Product Specification 11.13.4 LCD Voltage Dividing Resistor Connection Figure 11.47 Internal Resistor Bias Connection (1/2 BIAS) (1/3 BIAS) VLCD VLCD 2R 2R DISP LBRS DISP LBRS VLC0 VLC1 VLC2 VLC3 VLC0 VLC1 R R R R VSS VLC2 VLC3 R VSS (1/4 BIAS ) VLCD 2R DISP LBRS VLC0 VLC1 VLC 2 VLC3 R R R R VSS Figure 11.48 External Resistor Bias Connection PS030002-0212 PRELIMINARY 171 Z51F3221 Product Specification 11.13.5 Block Diagram Port Latch SEG/Port Driver LCD Display RAM COM/Port Driver fLCD Timing Controller LCDCRL VLC 0 LCD Voltage Controller LCDCRH VLC 1 VLC 2 VLC 3 Figure 11.49 LCD Circuit Block Diagram NOTE) The clock and duty for LCD driver is automatically initialized by hardware, whenever LCDCRH register data value is rewritten. So, don’t rewrite LCDCRH frequently 11.13.6 Register Map Table 11-19 LCD Register Map Name Address Dir Default Description LCDCRH ECH R/W 00H LCD Driver Control High Register LCDCRL EBH R/W 00H LCD Driver Control Low Register 11.13.7 LCD Driver Register Description LCD driver register has two control registers, LCD driver control high register (LCDCRH) and LCD driver control low register (LCDCRL). PS030002-0212 PRELIMINARY 172 Z51F3221 Product Specification 11.13.8 Register Description for LCD Driver LCDCRH (LCD Driver Control High Register) : ECH 7 6 5 4 3 2 1 0 LCDDR LD_B3 LD_B2 LD_B1 LD_B0 LCLK1 LCLK0 DISP R/W R/W R./W R/W R/W R/W R/W LCDDR LD_B[3:0] LCLK[1:0] R/W Initial value : 00H LCD Driving Resistor for Bias Select 0 Internal LCD driving resistors for bias 1 External LCD driving resistor for bias LCD Duty and Bias Select (NOTE) LD_B3 LD_B2 LD_B1 0 0 0 LD_B0 Description 0 1/2Duty, 1/2Bias (100k ohm) 0 0 0 1 1/2Duty, 1/2Bias (50k ohm) 0 0 1 0 1/2Duty, 1/3Bias (50k ohm) 0 0 1 1 1/3Duty, 1/2Bias (100k ohm) 0 1 0 0 1/3Duty, 1/2Bias (50k ohm) 0 1 0 1 1/3Duty, 1/3Bias (50k ohm) 0 1 1 0 1/4Duty, 1/2Bias (100k ohm) 0 1 1 1 1/4Duty, 1/2Bias (50k ohm) 1 0 0 0 1/4Duty, 1/3Bias (50k ohm) 1 0 0 1 Not available 1 0 1 0 Not available 1 0 1 1 1/5Duty, 1/3Bias (50k ohm) 1 1 0 0 1/6Duty, 1/3Bias (50k ohm) 1 1 0 1 1/6Duty, 1/4Bias (50k ohm) 1 1 1 0 1/8Duty, 1/3Bias (50k ohm) 1 1 1 1 1/8Duty, 1/4Bias (50k ohm) LCD Clock Select (When fWCK(Watch timer clock)= 32.768 kHz) LCLK1 LCLK0 Description 0 0 fLCD = 128Hz 0 1 fLCD = 256Hz 1 0 fLCD = 512Hz 1 1 fLCD = 1024Hz NOTE) The LCD clock is generated by watch timer clock (fWCK). So the watch timer should be enabled when the LCD display is turned on. DISP LCD Display Control 0 Display off 1 Normal display on NOTES) 1. When 1/2 bias is selected, the bias levels are set as VLC0, VLC2, and VSS 2. When 1/3 bias is selected, the bias levels are set as VLC0, VLC1, VLC2 (=VLC3), and VSS 3. When 1/4 bias is selected, the bias levels are set as VLC0, VLC1, VLC2, VLC3, and VSS 4. The bias levels are automatically set with appropriate bias circuit when internal bias resistors are used. 5. A bias circuit is connected like the “11.13.4 LCD Voltage Dividing Resistor Connection” and should be selected as an appropriate value for “LD_B[3:0]”. PS030002-0212 PRELIMINARY 173 Z51F3221 Product Specification LCDCRL (LCD Driver Control Low Register) : EBH 7 6 5 4 3 2 1 0 – – – – – – LBRS VLC_PE – -– – – – – R/W LBRS VLC_PE PS030002-0212 R/W Initial value : 00H LCD Bias Resistor Select 0 Not select 2R 1 Select 2R VLC[3:0] Port Control 0 Normal Port 1 VLCD[3:0] pin PRELIMINARY 174 Z51F3221 Product Specification 12. Power Down Operation 12.1 Overview The Z51F3221 MCU features two power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. The device provides three kinds of power saving functions, Main-IDLE, Sub-IDLE and STOP mode. In three modes, program is stopped. 12.2 Peripheral Operation in IDLE/STOP Mode Table 12-1 Peripheral Operation during Power Down Mode Peripheral CPU RAM IDLE Mode ALL CPU Operation are Disable STOP Mode ALL CPU Operation are Disable Retain Retain Basic Interval Timer Operates Continuously Stop Watch Dog Timer Operates Continuously Stop (Can be operated with WDTRC OSC) Watch Timer Operates Continuously Stop (Can be operated with sub clock) Timer0~3 Operates Continuously Halted (Only when the Event Counter Mode is Enabled, Timer operates Normally) ADC Operates Continuously Stop BUZ Operates Continuously Stop Only operate with external clock SIO Operates Continuously UART Operates Continuously Stop LCD Controller Operates Continuously Stop (Can be operated with sub clock) Internal OSC (8MHz) Oscillation Stop when the system clock (fx) is fIRC WDTRC OSC (6kHz) Stop Can be operated with setting value Main OSC (1~12MHz) Oscillation Stop when fx = fXIN Sub OSC (32.768kHz) Oscillation Stop when fx = fSUB I/O Port Retain Retain Control Register Retain Retain Address Data Bus Retain Retain By RESET, Timer Interrupt (EC0,EC3), SIO (External clock), External Interrupt, UART by ACK, WT (sub clock), WDT Release Method PS030002-0212 By RESET, all Interrupts PRELIMINARY 175 Z51F3221 Product Specification 12.3 IDLE Mode The power control register is set to ‘01h’ to enter the IDLE Mode. In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally but CPU stops. It is released by reset or interrupt. To be released by interrupt, interrupt should be enabled before IDLE mode. If using reset, because the device becomes initialized state, the registers have reset value. OSC CPU Clock External Interrupt Release Normal Operation Stand-by Mode Normal Operation Figure 12.1 IDLE Mode Release Timing by External Interrupt PS030002-0212 PRELIMINARY 176 Z51F3221 Product Specification 12.4 STOP Mode The power control register is set to ‘03H’ to enter the STOP Mode. In the stop mode, the selected oscillator, system clock and peripheral clock is stopped, but watch timer can be continued to operate with sub clock. With the clock frozen, all functions are stopped, but the on-chip RAM and control registers are held. For example, If the internal RC oscillator (fIRC) is selected for the system clock and the sub clock (fSUB) is oscillated, the internal RC oscillator stops oscillation and the sub clock is continuously oscillated in stop mode. At that time, the watch timer and LCD controller can be operated with the sub clock. The source for exit from STOP mode is hardware reset and interrupts. The reset re-defines all the control registers. When exit from STOP mode, enough oscillation stabilization time is required to normal operation. Figure 12.2 shows the timing diagram. When released from STOP mode, the Basic interval timer is activated on wake-up. Therefore, before STOP instruction, user must be set its relevant prescale divide ratio to have long enough time. This guarantees that oscillator has started and stabilized. OSC CPU Clock Release External Interrupt STOP Instruction Execute BIT Counter n n+1 n+2 n+3 0 1 2 FE FF 0 1 Clear & Start Normal Operation By Software setting STOP Operation Normal Operation Before executed STOP instruction, BIT must be set properly by software to get stabilization. Figure 12.2 STOP Mode Release Timing by External Interrupt PS030002-0212 PRELIMINARY 177 Z51F3221 Product Specification 12.5 Release Operation of STOP Mode After STOP mode is released, the operation begins according to content of related interrupt register just before STOP mode start (Figure 12.3). If the global interrupt Enable Flag (IE.EA) is set to `1`, the STOP mode is released by the interrupt which each interrupt enable flag = `1` and the CPU jumps to the relevant interrupt service routine. Even if the IE.EA bit is cleared to ‘0’, the STOP mode is released by the interrupt of which the interrupt enable flag is set to ‘1’. SET PCON[7:0] SET IEx.b STOP Mode Interrupt Request Corresponding Interrupt Enable Bit(IE, IE1, IE2, IE3) IEx.b==1 ? N Y STOP Mode Release Interrupt Service Routine Next Instruction Figure 12.3 STOP Mode Release Flow PS030002-0212 PRELIMINARY 178 Z51F3221 Product Specification 12.5.1 Register Map Table 12-2 Power Down Operation Register Map Name Address PCON Dir 87H Default R/W Description 00H Power Control Register 12.5.2 Power Down Operation Register Description The power down operation register consists of the power control register (PCON). 12.5.3 Register Description for Power Down Operation PCON (Power Control Register) : 87H 7 6 5 4 3 2 1 0 PCON7 – – – PCON3 PCON2 PCON1 PCON0 R/W – – – R/W R/W R/W PCON[7:0] R/W Initial value : 00H Power Control 01H IDLE mode enable 03H STOP mode enable NOTES) 1. To enter IDLE mode, PCON must be set to ‘01H’. 2. To enter STOP mode, PCON must be set to ‘03H’. 3. The PCON register is automatically cleared by a release signal in STOP/IDLE mode. 4. Three or more NOP instructions must immediately follow the instruction that make the device enter STOP/IDLE mode. Refer to the following examples. Ex1) MOV NOP NOP NOP • • • PS030002-0212 PCON, #01H ; IDLE mode Ex2) PRELIMINARY MOV NOP NOP NOP • • • PCON, #03H ; STOP mode 179 Z51F3221 Product Specification 13. RESET 13.1 Overview The following is the hardware setting value. Table 13-1 Reset State On Chip Hardware Initial Value Program Counter (PC) 0000h Accumulator 00h Stack Pointer (SP) 07h Peripheral Clock On Control Register Refer to the Peripheral Registers 13.2 Reset Source The Z51F3221 MCU features five types of reset sources. The following is the reset sources. - External RESETB - Power ON RESET (POR) - WDT Overflow Reset (In the case of WDTEN = `1`) - Low Voltage Reset (In the case of LVREN = `0 `) - OCD Reset 13.3 RESET Block Diagram Ext RESET Disable by FUSE RESET Noise Canceller LVR LVR Enable RESET Noise Canceller POR RST S WDT RST WDT RSTEN R Q Internal Reset IFBIT (BIT Overflow) OCD RST OCD RSTEN Figure 13.1 RESET Block Diagram 13.4 RESET Noise Canceller The Figure 13.2 is the noise canceller diagram for noise cancellation of RESET. It has the noise cancellation value of about 2us (@VDD=5V) to the low input of system reset. PS030002-0212 PRELIMINARY 180 Z51F3221 Product Specification t < TRNC t < TRNC A t > TRNC t > TRNC t > TRNC A’ Figure 13.2 Reset noise canceller timer diagram 13.5 Power On RESET When rising device power, the POR (Power On Reset) has a function to reset the device. If POR is used, it executes the device RESET function instead of the RESET IC or the RESET circuits. Fast VDD Rise Time VDD nPOR (Internal Signal) BIT Overflows BIT Starts Internal RESETB Oscillation Figure 13.3 Fast VDD Rising Time Slow VDD Rise Time, min. 0.15V/mS VPOR=1.4V (Typ) VDD nPOR (Internal Signal) BIT Overflows BIT Starts Internal RESETB Oscillation Figure 13.4 Internal RESET Release Timing On Power-Up PS030002-0212 PRELIMINARY 181 Z51F3221 Product Specification Counting for config read start after POR is released VDD Internal nPOR PAD RESETB “H” LVR_RESETB BIT (for Config) 00 00 01 02 03 BIT (for Reset) 00 .. 27 28 01 F1 02 01 00 03 04 00 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms RESET_SYSB INT-OSC (8MHz) INT-OSC 8MHz/8 INT-OSC 8MHz / 8 = 1MHz (1us) Figure 13.5 Configuration Timing when Power-on :VDD Input :Internal OSC ⑥ ④ Reset Release Config Read ② POR ① ③ ⑤ ⑦ Figure 13.6 Boot Process WaveForm PS030002-0212 PRELIMINARY 182 Z51F3221 Product Specification Table 13-2 Boot Process Description Process Description ① -No Operation ② -1st POR level Detection Remarks -about 1.4V - (INT-OSC 8MHz/8)x256x28h Delay section (=10ms) ③ -VDD input voltage must rise over than flash operating voltage for Config read ④ - Config read point ⑤ - Rising section to Reset Release Level -Slew Rate 0.15V/ms -about 1.5V ~ 1.6V -Config Value is determined by Writing Option -16ms point after POR or Ext_reset release - Reset Release section (BIT overflow) ⑥ i) after16ms, after External Reset Release (External reset) - BIT is used for Peripheral stability ii) 16ms point after POR (POR only) ⑦ -Normal operation PS030002-0212 PRELIMINARY 183 Z51F3221 Product Specification 13.6 External RESETB Input The External RESETB is the input to a Schmitt trigger. If RESETB pin is held with low for at least 10us over within the operating voltage range and stable oscillation, it is applied and the internal state is initialized. After reset state becomes ‘1’, it needs the stabilization time with 16ms and after the stable state, the internal RESET becomes ‘1’. The Reset process step needs 5 oscillator clocks. And the program execution starts at the vector address stored at address 0000H. 1 2 3 4 5 OSC RESETB Release Internal RESETB Release ADDRESS BUS ? CORE BUS ? ? Stabilization Time TST = 16.4ms 00 ? ? 02 01 02 ? ? ? ? RESET Process Step Main Program Figure 13.7 Timing Diagram after RESET PRESCALER COUNT START VDD OSC START TIMING Figure 13.8 Oscillator generating waveform example NOTE) As shown Figure 13.8, the stable generating time is not included in the start-up time. The RESETB pin has a Pull-up register by H/W. PS030002-0212 PRELIMINARY 184 Z51F3221 Product Specification 13.7 Brown Out Detector Processor The Z51F3221 MCU features an On-chip brown-out detection circuit (BOD) for monitoring the VDD level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by LVRVS[3:0] bit to be 1.60V, 2.00V, 2.10V, 2.20V,2.32V, 2.44V, 2.59V, 2.75V, 2.93V, 3.14V, 3.38V, 3.67V, 4.00V, 4.40V. In the STOP mode, this will contribute significantly to the total current consumption. So to minimize the current consumption, the LVREN bit is set to off by software. External VDD LVRVS[3:0] Brown Out Detector (BOD) RESET_BODB LVREN CPU Write SCLK (System CLK) D Q CP LVRF (Low Voltage Reset Flag) r nPOR Figure 13.9 Block Diagram of BOD VDD VBODMAX VBODMIN 16ms Internal RESETB VDD VBODMAX VBODMIN t < 16ms 16ms Internal RESETB Figure 13.10 Internal Reset at the power fail situation PS030002-0212 PRELIMINARY 185 Z51F3221 Product Specification “H” VDD Internal nPOR “H” “H” PAD RESETB LVR_RESETB BIT (for Config) BIT (for Reset) .. 27 28 00 01 02 .. .. F1 00 01 F1 03 02 04 00 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms RESET_SYSB Main OSC Off INT-OSC (8MHz) INT-OSC 8MHz/8 INT-OSC 8MHz / 8 = 1MHz (1us) Figure 13.11 Configuration timing when BOD RESET 13.8 LVI Block Diagram VDD Reference Voltage Generator 2.00V 2.10V 2.20V 2.32V 2.44V 2.59V 2.75V 2.93V 3.14V 3.38V 3.67V 4.00V 4.40V M U X LVI Circuit LVIF LVIEN LVIREF 4 LVILS[3:0 ] Figure 13.12 LVI Diagram PS030002-0212 PRELIMINARY 186 Z51F3221 Product Specification 13.8.1 Register Map Table 13-3 Reset Operation Register Map Name Address Dir Default Description RSTFR 86H R/W 88H Reset Flag Register LVRCR F7H R/W 00H Low Voltage Reset Control Register LVICR E1H R/W 00H Low Voltage Indicator Control Register 13.8.2 Reset Operation Register Description The reset control register consists of the reset flag register (RSTFR), low voltage reset control register (LVRCR), and low voltage indicator control register (LVICR). 13.8.3 Register Description for Reset Operation RSTFR (Reset Flag Register) : 86H 7 6 5 4 3 2 1 0 PORF EXTRF WDTRF OCDRF LVRF – – – R/W R/W R/W R/W R/W – – PORF EXTRF WDTRF OCDRF LVRF – Initial value : 88H Power-On Reset flag bit. The bit is reset by writing ‘0’ to this bit. 0 No detection 1 Detection External Reset (RESETB) flag bit. The bit is reset by writing ‘0’ to this bit or by Power-On Reset. 0 No detection 1 Detection Watch Dog Reset flag bit. The bit is reset by writing ‘0’ to this bit or by Power-On Reset. 0 No detection 1 Detection On-Chip Debug Reset flag bit. The bit is reset by writing ‘0’ to this bit or by Power-On Reset. 0 No detection 1 Detection Low Voltage Reset flag bit. The bit is reset by writing ‘0’ to this bit or by Power-On Reset. 0 No detection 1 Detection NOTES) 1. When the Power-On Reset occurs, the PORF and LVRF bits are only set to “1”, the other flag (WDTRF and OCDRF) bits are all cleared to “0”. 2. When the Power-On Reset occurs, the EXTRF bit is unknown, At that time, the EXTRF bit can be set to “1” when External Reset (RESETB) occurs. 3. When a reset except the POR occurs, the corresponding flag bit is only set to “1”, the other flag bits are kept in the previous values. PS030002-0212 PRELIMINARY 187 Z51F3221 Product Specification LVRCR (Low Voltage Reset Control Register) : F7H 7 6 5 4 3 2 1 0 LVRST – – LVRVS3 LVRVS2 LVRVS1 LVRVS0 LVREN R/W – – R/W R/W R/W R/W LVRST R/W Initial value : 00H LVR Enable when Stop Release 0 Not effect at stop release 1 LVR enable at stop release NOTES) 1. When this bit is ‘1’, the LVREN bit is cleared to ‘0’ by stop mode to release. (LVR enable) 2. When this bit is ‘0’, the LVREN bit is not effect by stop mode to release. LVRVS[3:0] LVREN LVR Voltage Select LVRVS3 LVRVS2 LVRVS1 LVRVS0 Description 0 0 0 0 1.60V 0 0 0 1 2.00V 0 0 1 0 2.10V 0 0 1 1 2.20V 0 1 0 0 2.32V 0 1 0 1 2.44V 0 1 1 0 2.59V 0 1 1 1 2.75V 1 0 0 0 2.93V 1 0 0 1 3.14V 1 0 1 0 3.38V 1 0 1 1 3.67V 1 1 0 0 4.00V 1 1 0 1 4.40V 1 1 1 0 Not available 1 1 1 1 Not available LVR Operation 0 LVR Enable 1 LVR Disable NOTES) 1. The LVRVS[3:0] bits are cleared by a power-on reset but are retained by other reset signals. 2. The LVRVS[3:0] bits should be set to ‘0000b’ while LVREN bit is “1”. PS030002-0212 PRELIMINARY 188 Z51F3221 Product Specification LVICR (Low Voltage Indicator Control Register) : E1H 7 6 5 4 3 2 1 0 – – LVIF LVIEN LVILS3 LVILS2 LVILS1 LVILS0 – – R/W R/W R/W R/W R/W LVIF LVIEN LVILS[3:0] PS030002-0212 R/W Initial value : 00H Low Voltage Indicator Flag Bit 0 No detection 1 Detection LVI Enable/Disable 0 Disable 1 Enable LVI Level Select LVILS3 LVILS2 LVILS1 LVILS0 Description 0 0 0 0 2.00V 0 0 0 1 2.10V 0 0 1 0 2.20V 0 0 1 1 2.32V 0 1 0 0 2.44V 0 1 0 1 2.59V 0 1 1 0 2.75V 0 1 1 1 2.93V 1 0 0 0 3.14V 1 0 0 1 3.38V 1 0 1 0 3.67V 1 0 1 1 4.00V 1 1 0 0 4.40V 1 1 0 1 Ext. Reference (LVIREF) 1 1 1 0 Not available 1 1 1 1 Not available PRELIMINARY 189 Z51F3221 Product Specification 14. On-chip Debug System 14.1 Overview 14.1.1 Description On-chip debug system (OCD) of the Z51F3221 MCU can be used for programming the non-volatile memories and on-chip debugging. Detail descriptions for programming via the OCD interface can be found in the following chapter. Figure 14.1 shows a block diagram of the OCD interface and the On-chip Debug system. 14.1.2 Feature • Two-wire external interface: 1-wire serial clock input, 1-wire bi-directional serial data bus • Debugger Access to: − All Internal Peripheral Units − Internal data RAM − Program Counter − Flash and Data EEPROM Memories • Extensive On-chip Debug Support for Break Conditions, Including − Break Instruction − Single Step Break − Program Memory Break Points on Single Address − Programming of Flash, EEPROM, Fuses, and Lock Bits through the two-wire Interface − On-chip Debugging Supported by Dr.Choice® • Operating frequency Supports the maximum frequency of the target MCU Target MCU internal circuit Format converter DSCL USB DSDA BDC CPU DBG Control DBG Register Address bus Internal data bus User I/O Code memory - SRAM - Flash - EEPROM PS030002-0212 PRELIMINARY Data memory Peripheral 190 Z51F3221 Product Specification Figure 14.1 Block Diagram of On-Chip Debug System 14.2 Two-Pin External Interface 14.2.1 Basic Transmission Packet • 10-bit packet transmission using two-pin interface. • 1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge. • Parity is even of ‘1’ for 8-bit data in transmitter. • Receiver generates acknowledge bit as ‘0’ when transmission for 8-bit data and its parity has no error. • When transmitter has no acknowledge (Acknowledge bit is ‘1’ at tenth clock), error process is executed in transmitter. • When acknowledge error is generated, host PC makes stop condition and transmits command which has error again. • Background debugger command is composed of a bundle of packet. • Start condition and stop condition notify the start and the stop of background debugger command respectively. PS030002-0212 PRELIMINARY 191 Z51F3221 Product Specification Figure 14.2 10-bit Transmission Packet 14.2.2 Packet Transmission Timing 14.2.2.1 Data Transfer DSDA LSB acknowledgement signal from receiver LSB acknowledgement signal from receiver DSCL St 1 1 10 ACK 10 Sp ACK START STOP Figure 14.3 Data Transfer on the Twin Bus 14.2.2.2 Bit Transfer DSDA DSCL data line stable: data valid except Start and Stop change of data allowed Figure 14.4 Bit Transfer on the Serial Bus PS030002-0212 PRELIMINARY 192 Z51F3221 Product Specification 14.2.2.3 Start and Stop Condition DSDA DSDA DSCL DSCL St Sp STOP condition START condition Figure 14.5 Start and Stop Condition 14.2.2.4 Acknowledge Bit Data output by transmitter no acknowledge Data output By receiver acknowledge DSCL from master 1 2 9 10 clock pulse for acknowledgement Figure 14.6 Acknowledge on the Serial Bus Acknowledge bit transmission Acknowledge bit transmission Minimum 500ns wait HIGH start HIGH Host PC DSCL OUT Start wait Target Device DSCL OUT Maximum 5 TSCLK minimum 1 TSCLK for next byte transmission DSCL Internal Operation PS030002-0212 PRELIMINARY 193 Z51F3221 Product Specification Figure 14.7 Clock Synchronization during Wait Procedure PS030002-0212 PRELIMINARY 194 Z51F3221 Product Specification 14.2.3 Connection of Transmission Two-pin interface connection uses open-drain (wire-AND bidirectional I/O). VDD pull -up resistors Rp Rp DSDA(Debugger Serial Data Line) DSCL(Debugger Serial Clock Line) VDD DSCL OUT DSCL IN DSDA OUT DSDA IN VDD DSCL OUT DSDA OUT DSDA IN DSCL IN Target Device(Slave) Host Machine(Master) Current source for DSCL to fast 0 to 1 transition in high speed mode Figure 14.8 Connection of Transmission PS030002-0212 PRELIMINARY 195 Z51F3221 Product Specification 15. Flash Memory 15.1 Overview 15.1.1 Description The Z51F3221 MCU incorporates flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory can be read by ‘MOVC’ instruction and it can be programmed in OCD, serial ISP mode or user program mode. • Flash Size : 32kbytes • Single power supply program and erase • Command interface for fast program and erase operation • Up to 100,000 program/erase cycles at typical voltage and temperature for flash memory PS030002-0212 PRELIMINARY 196 Z51F3221 Product Specification 15.1.2 Flash Program ROM Structure 07FFFH Sector 511 07FC0H 07FBFH 07FC0H Sector 510 07F80H 07F7FH 07F80H Sector 509 07F40H 07F40H 07F3FH Sector 508 Flash Sector Address ROM Address Sector 2 00080H 00080H 0007FH Sector 1 00040H 0003FH 00040H Sector 0 00000H 00000H 64bytes Accessed by MOVX instruction only Flash Page Buffer (External Data Memory, 64bytes) Flash Controller 803FH 8000H Page(Sector) Buffer Address FSADRH/M/L FIDR FMCR Figure 15.1 Flash Program ROM Structure PS030002-0212 PRELIMINARY 197 Z51F3221 Product Specification 15.1.3 Register Map Table 15-1Flash Memory Register Map Name Address Dir Default Description FSADRH FAH R/W 00H Flash Sector Address High Register FSADRM FBH R/W 00H Flash Sector Address Middle Register FSADRL FCH R/W 00H Flash Sector Address Low Register FIDR FDH R/W 00H Flash Identification Register FMCR FEH R/W 00H Flash Mode Control Register 15.1.4 Register Description for Flash Memory Control and Status Flash control register consists of the flash sector address high register (FSADRH), flash sector address middle register (FSADRM), flash sector address low register (FSADRL), flash identification register (FIDR), and flash mode control register (FMCR). They are mapped to SFR area and can be accessed only in programming mode. PS030002-0212 PRELIMINARY 198 Z51F3221 Product Specification 15.1.5 Register Description for Flash FSADRH (Flash Sector Address High Register) : FAH 7 6 5 4 3 2 1 0 – – – – FSADRH3 FSADRH 2 FSADRH1 FSADRH0 – – – – R/W R/W R/W FSADRH[3:0] R/W Initial value : 00H Flash Sector Address High FSADRM (Flash Sector Address Middle Register) : FBH 7 6 5 4 3 2 1 0 FSADRM7 FSADRM6 FSADRM5 FSADRM4 FSADRM3 FSADRM2 FSADRM1 FSADRM0 R/W R/W R/W R/W R/W R/W R/W FSADRM[7:0] R/W Initial value : 00H Flash Sector Address Middle FSADRL (Flash Sector Address Low Register) : FCH 7 6 5 4 3 2 1 0 FSADRL7 FSADRL6 FSADRL5 FSADRL4 FSADRL3 FSADRL2 FSADRL1 FSADRL0 R/W R/W R/W R/W R/W R/W R/W FSADRL[7:0] R/W Initial value : 00H Flash Sector Address Low FIDR (Flash Identification Register) : FDH 7 6 5 4 3 2 1 0 FIDR7 FIDR6 FIDR5 FIDR4 FIDR3 FIDR2 FIDR1 FIDR0 R/W R/W R/W R/W R/W R/W R/W FIDR[7:0] R/W Initial value : 00H Flash Identification Others No identification value 10100101 Identification value for a flash mode (These bits are automatically cleared to logic ‘00H’ immediately after one time operation) PS030002-0212 PRELIMINARY 199 Z51F3221 Product Specification FMCR (Flash Mode Control Register) : FEH 7 6 5 4 3 2 1 0 FMBUSY – – – – FMCR2 FMCR1 FMCR0 R – – – – R/W R/W R/W Initial value : 00H FMBUSY FMCR[2:0] Flash Mode Busy Bit. This bit will be used for only debugger. 0 No effect when “1” is written 1 Busy Flash Mode Control Bits. During a flash mode operation, the CPU is hold and the global interrupt is on disable state regardless of the IE.7 (EA) bit. FMCR2 FMCR1 FMCR0 Description 0 0 1 Select flash page buffer reset mode and start regardless of the FIDR value (Clear all 64bytes to ‘0’) 0 1 0 Select flash sector erase mode and start operation when the FIDR=”10100101b’ 0 1 1 Select flash sector write mode and start operation when the FIDR=”10100101b’ 1 0 0 Select flash sector hard lock and start operation when the FIDR=”10100101b’ Others Values: No operation (These bits are automatically cleared to logic ‘00H’ immediately after one time operation) PS030002-0212 PRELIMINARY 200 Z51F3221 Product Specification 15.1.6 Serial In-System Program (ISP) Mode Serial in-system program uses the interface of debugger which uses two wires. Refer to chapter 14 in details about debugger 15.1.7 Protection Area (User program mode) The Z51F3221 MCU can program its own flash memory (protection area). The protection area can not be erased or programmed. The protection areas are available only when the PAEN bit is cleared to ‘0’, that is, enable protection area at the configure option 2 if it is needed. If the protection area isn’t enabled (PAEN =’1’), this area can be used as a normal program memory. The size of protection area can be varied by setting of configure option 2. Table 15-2 Protection Area size Protection Area Size Select Size of Protection Area Address of Protection Area 0100H – 0FFFH PASS1 PASS0 0 0 3.8k Bytes 0 1 1.7k Bytes 0100H – 07FFH 1 0 768 Bytes 0100H – 03FFH 1 1 256 Bytes 0100H – 01FFH NOTE) Refer to chapter 16 in configure option control. PS030002-0212 PRELIMINARY 201 Z51F3221 Product Specification 15.1.8 Erase Mode The sector erase program procedure in user program mode 1. Page buffer clear (FMCR=0x01) 2. Write ‘0’ to page buffer 3. Set flash sector address register (FSADRH/FSADRM/FSADRL). 4. Set flash identification register (FIDR). 5. Set flash mode control register (FMCR). 6. Erase verify Program Tip – sector erase Pgbuf_clr: MOV NOP NOP NOP FMCR,#0x01 MOV MOV MOV MOV A,#0 R0,#64 DPH,#0x80 DPL,#0 MOVX INC @DPTR,A DPTR DJNZ R0, Pgbuf_clr MOV MOV MOV MOV MOV NOP NOP NOP FSADRH,#0x00 FSADRM,#0x7F FSADRL,#0x40 FIDR,#0xA5 FMCR,#0x02 MOV MOV MOV MOV MOV A,#0 R0,#64 R1,#0 DPH,#0x7F DPL,#0x40 ;page buffer clear ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Sector size is 64bytes ;Write ‘0’ to all page buffer ;Select sector 509 ;Identification value ;Start flash erase mode ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;erase verify ;Sector size is 64bytes Erase_verify: MOVC A,@A+DPTR SUBB A,R1 JNZ Verify_error INC DPTR DJNZ R0, Erase_verify Verify_error: PS030002-0212 PRELIMINARY 202 Z51F3221 Product Specification The Byte erase program procedure in user program mode 1. Page buffer clear (FMCR=0x01) 2. Write ‘0’ to page buffer 3. Set flash sector address register (FSADRH/FSADRM/FSADRL). 4. Set flash identification register (FIDR). 5. Set flash mode control register (FMCR). 6. Erase verify Program Tip – byte erase MOV NOP NOP NOP FMCR,#0x01 MOV MOV MOV MOVX A,#0 DPH,#0x80 DPL,#0 @DPTR,A MOV MOV DPH,#0x80 DPL,#0x05 MOVX @DPTR,A MOV MOV MOV MOV MOV NOP NOP NOP FSADRH,#0x00 FSADRM,#0x7F FSADRL,#0x40 FIDR,#0xA5 FMCR,#0x02 MOV A,#0 MOV R1,#0 MOV DPH,#0x7F MOV DPL,#0x40 MOVC A,@A+DPTR SUBB A,R1 JNZ Verify_error MOV A,#0 MOV R1,#0 MOV DPH,#0x7F MOV DPL,#0x45 MOVC A,@A+DPTR SUBB A,R1 JNZ Verify_error ;page buffer clear ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Write ‘0’ to page buffer ;Select sector 509 ;Identification value ;Start flash erase mode ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;erase verify ;0x7F40 = 0 ? ;0x7F45 = 0 ? Verify_error: PS030002-0212 PRELIMINARY 203 Z51F3221 Product Specification 15.1.9 Write Mode The sector Write program procedure in user program mode 1. Page buffer clear (FMCR=0x01) 2. Write data to page buffer 3. Set flash sector address register (FSADRH/FSADRM/FSADRL). 4. Set flash identification register (FIDR). 5. Set flash mode control register (FMCR). 6. Erase verify Program Tip – sector write MOV NOP NOP NOP FMCR,#0x01 MOV MOV MOV MOV A,#0 R0,#64 DPH,#0x80 DPL,#0 Pgbuf_WR: MOVX INC INC DJNZ @DPTR,A A DPTR R0, Pgbuf_WR MOV MOV MOV MOV MOV NOP NOP NOP FSADRH,#0x00 FSADRM,#0x7F FSADRL,#0x40 FIDR,#0xA5 FMCR,#0x03 MOV MOV MOV MOV MOV A,#0 R0,#64 R1,#0 DPH,#0x7F DPL,#0x40 ;page buffer clear ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Sector size is 64bytes ;Write data to all page buffer ;Select sector 509 ;Identification value ;Start flash write mode ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;write verify ;Sector size is 64bytes Write_verify: MOVC A,@A+DPTR SUBB A,R1 JNZ Verify_error INC R1 INC DPTR DJNZ R0, Write_verify Verify_error: PS030002-0212 PRELIMINARY 204 Z51F3221 Product Specification The Byte Write program procedure in user program mode 1. Page buffer clear (FMCR=0x01) 2. Write data to page buffer 3. Set flash sector address register (FSADRH/FSADRM/FSADRL). 4. Set flash identification register (FIDR). 5. Set flash mode control register (FMCR). 6. Erase verify Program Tip – byte write MOV NOP NOP NOP FMCR,#0x01 MOV MOV MOV MOVX A,#5 DPH,#0x80 DPL,#0 @DPTR,A ;Write data to page buffer MOV MOV MOV MOVX A,#6 DPH,#0x80 DPL,#0x05 @DPTR,A ;Write data to page buffer MOV MOV MOV MOV MOV NOP NOP NOP FSADRH,#0x00 FSADRM,#0x7F FSADRL,#0x40 FIDR,#0xA5 FMCR,#0x03 MOV A,#0 MOV R1,#5 MOV DPH,#0x7F MOV DPL,#0x40 MOVC A,@A+DPTR SUBB A,R1 JNZ Verify_error MOV A,#0 MOV R1,#6 MOV DPH,#0x7F MOV DPL,#0x45 MOVC A,@A+DPTR SUBB A,R1 JNZ Verify_error ;page buffer clear ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Select sector 509 ;Identification value ;Start flash write mode ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;write verify ;0x7F40 = 5 ? ;0x7F45 = 6 ? Verify_error: PS030002-0212 PRELIMINARY 205 Z51F3221 Product Specification 15.1.10 Read Mode The Reading program procedure in user program mode 1. Load receive data from flash memory on MOVC instruction by indirectly addressing mode. Program Tip – reading MOV MOV MOV A,#0 DPH,#0x7F DPL,#0x40 ;flash memory address MOVC A,@A+DPTR ;read data from flash memory 15.1.11 Hard Lock Mode The Reading program procedure in user program mode 1. Set flash identification register (FIDR). 2. Set flash mode control register (FMCR). Program Tip – reading MOV MOV NOP NOP NOP PS030002-0212 FIDR,#0xA5 FMCR,#0x04 ;Identification value ;Start flash hard lock mode ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. PRELIMINARY 206 Z51F3221 Product Specification 16. Configure Option 16.1 Configure Option Control The data for configure option should be written in the configure option area (003EH – 003FH) by programmer (Writer tools). CONFIGURE OPTION 1 : ROM Address 003FH 7 6 5 4 3 2 1 R_P HL – – – – – R_P 0 – Initial value : 00H Read Protection HL 0 Disable “Read protection” 1 Enable “Read protection” Hard-Lock 0 Disable “Hard-lock” 1 Enable “Hard-lock” CONFIGURE OPTION 2: ROM Address 003EH 7 6 5 4 3 2 1 0 – – – – – PAEN PASS1 PASS0 Initial value : 00H PAEN PASS [1:0] Protection Area Enable/Disable 0 Disable Protection (Erasable by instruction) 1 Enable Protection (Not erasable by instruction) Protection Area Size Select PASS1 PS030002-0212 PASS0 Description 0 0 3.8k Bytes (Address 0100H – 0FFFH) 0 1 1.7k Bytes (Address 0100H – 07FFH) 1 0 768 Bytes (Address 0100H – 03FFH) 1 1 256 Bytes (Address 0100H – 01FFH) PRELIMINARY 207 Z51F3221 Product Specification 17. APPENDIX A. Instruction Table Instructions are either 1, 2 or 3 bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles. Mnemonic ADD A,Rn ADD A,dir ADD A,@Ri ADD A,#data ADDC A,Rn ADDC A,dir ADDC A,@Ri ADDC A,#data SUBB A,Rn SUBB A,dir SUBB A,@Ri SUBB A,#data INC A INC Rn INC dir INC @Ri DEC A DEC Rn DEC dir DEC @Ri INC DPTR MUL AB DIV AB DA A Mnemonic ANL A,Rn ANL A,dir ANL A,@Ri ANL A,#data ANL dir,A ANL dir,#data ORL A,Rn ORL A,dir ORL A,@Ri ORL A,#data ORL dir,A ORL dir,#data XRL A,Rn XRL A,dir XRL A, @Ri PS030002-0212 ARITHMETIC Description Add register to A Add direct byte to A Add indirect memory to A Add immediate to A Add register to A with carry Add direct byte to A with carry Add indirect memory to A with carry Add immediate to A with carry Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect memory from A with borrow Subtract immediate from A with borrow Increment A Increment register Increment direct byte Increment indirect memory Decrement A Decrement register Decrement direct byte Decrement indirect memory Increment data pointer Multiply A by B Divide A by B Decimal Adjust A LOGICAL Description AND register to A AND direct byte to A AND indirect memory to A AND immediate to A AND A to direct byte AND immediate to direct byte OR register to A OR direct byte to A OR indirect memory to A OR immediate to A OR A to direct byte OR immediate to direct byte Exclusive-OR register to A Exclusive-OR direct byte to A Exclusive-OR indirect memory to A PRELIMINARY Bytes 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 Hex code Bytes 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 Cycles 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 Hex code 28-2F 25 26-27 24 38-3F 35 36-37 34 98-9F 95 96-97 94 04 08-0F 05 06-07 14 18-1F 15 16-17 A3 A4 84 D4 58-5F 55 56-57 54 52 53 48-4F 45 46-47 44 42 43 68-6F 65 66-67 208 Z51F3221 Product Specification XRL A,#data XRL dir,A XRL dir,#data CLR A CPL A SWAP A RL A RLC A RR A RRC A Mnemonic MOV A,Rn MOV A,dir MOV A,@Ri MOV A,#data MOV Rn,A MOV Rn,dir MOV Rn,#data MOV dir,A MOV dir,Rn MOV dir,dir MOV dir,@Ri MOV dir,#data MOV @Ri,A MOV @Ri,dir MOV @Ri,#data MOV DPTR,#data MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri MOVX A,@DPTR MOVX @Ri,A MOVX @DPTR,A PUSH dir POP dir XCH A,Rn XCH A,dir XCH A,@Ri XCHD A,@Ri Mnemonic CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit PS030002-0212 Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR immediate to direct byte Clear A Complement A Swap Nibbles of A Rotate A left Rotate A left through carry Rotate A right Rotate A right through carry DATA TRANSFER Description Move register to A Move direct byte to A Move indirect memory to A Move immediate to A Move A to register Move direct byte to register Move immediate to register Move A to direct byte Move register to direct byte Move direct byte to direct byte Move indirect memory to direct byte Move immediate to direct byte Move A to indirect memory Move direct byte to indirect memory Move immediate to indirect memory Move immediate to data pointer Move code byte relative DPTR to A Move code byte relative PC to A Move external data(A8) to A Move external data(A16) to A Move A to external data(A8) Move A to external data(A16) Push direct byte onto stack Pop direct byte from stack Exchange A and register Exchange A and direct byte Exchange A and indirect memory Exchange A and indirect memory nibble BOOLEAN Description Clear carry Clear direct bit Set carry Set direct bit Complement carry Complement direct bit AND direct bit to carry AND direct bit inverse to carry PRELIMINARY 2 2 3 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 64 62 63 E4 F4 C4 23 33 03 13 Bytes 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 Cycles 1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 Hex code E8-EF E5 E6-E7 74 F8-FF A8-AF 78-7F F5 88-8F 85 86-87 75 F6-F7 A6-A7 76-77 90 93 83 E2-E3 E0 F2-F3 F0 C0 D0 C8-CF C5 C6-C7 D6-D7 Bytes 1 2 1 2 1 2 2 2 Cycles 1 1 1 1 1 1 2 2 Hex code C3 C2 D3 D2 B3 B2 82 B0 209 Z51F3221 Product Specification ORL C,bit ORL C,/bit MOV C,bit MOV bit,C OR direct bit to carry OR direct bit inverse to carry Move direct bit to carry Move carry to direct bit BRANCHING Description Mnemonic ACALL addr 11 LCALL addr 16 RET RETI AJMP addr 11 LJMP addr 16 SJMP rel JC rel JNC rel JB bit,rel JNB bit,rel JBC bit,rel JMP @A+DPTR JZ rel JNZ rel CJNE A,dir,rel CJNE A,#d,rel CJNE Rn,#d,rel CJNE @Ri,#d,rel DJNZ Rn,rel DJNZ dir,rel Absolute jump to subroutine Long jump to subroutine Return from subroutine Return from interrupt Absolute jump unconditional Long jump unconditional Short jump (relative address) Jump on carry = 1 Jump on carry = 0 Jump on direct bit = 1 Jump on direct bit = 0 Jump on direct bit = 1 and clear Jump indirect relative DPTR Jump on accumulator = 0 Jump on accumulator ≠ 0 Compare A,direct jne relative Compare A,immediate jne relative Compare register, immediate jne relative Compare indirect, immediate jne relative Decrement register, jnz relative Decrement direct byte, jnz relative MISCELLANEOUS Description Mnemonic NOP No operation Mnemonic MOVC @(DPTR++),A TRAP 2 2 2 2 2 2 1 2 72 A0 A2 92 Bytes 2 3 1 1 2 3 2 2 2 3 3 3 1 2 2 3 3 3 3 3 3 Cycles 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Hex code Bytes 1 Cycles 1 Hex code ADDITIONAL INSTRUCTIONS (selected through EO[7:4]) Description Bytes M8051W/M8051EW-specific instruction supporting 1 software download into program memory 1 Software break command 11→F1 12 22 32 01→E1 02 80 40 50 20 30 10 73 60 70 B5 B4 B8-BF B6-B7 D8-DF D5 00 Cycles Hex code 2 A5 1 A5 In the above table, an entry such as E8-EF indicates a continuous block of hex opcodes used for 8 different registers, the register numbers of which are defined by the lowest three bits of the corresponding code. Noncontinuous blocks of codes, shown as 11→F1 (for example), are used for absolute jumps and calls, with the top 3 bits of the code being used to store the top three bits of the destination address. The CJNE instructions use the abbreviation #d for immediate data; other instructions use #data. PS030002-0212 PRELIMINARY 210 Z51F3221 Product Specification B. Instructions on how to use the input port.  Error occur status  Using compare jump instructions with input port, it could cause error due to the timing conflict inside the MCU. Compare jump Instructions which cause potential error used with input port condition:  JB bit, rel ; jump on direct bit=1 JNB bit, rel ; jump on direct bit=0 JBC bit, rel ; jump on direct bit=1 and clear CJNE A, dir, rel ; compare A, direct jne relative DJNZ dir, rel  It is only related with Input port. Internal parameters, SFRs and output bit ports don’t cause any error by using compare jump instructions. If input signal is fixed, there is no error in using compare jump instructions.   ; decrement direct byte, jnz relative Error status example while(1){ zzz: 080.0, xxx ; it possible to be error SETB 088.0 else { P10=0; } SJMP yyy P11^=1; } xxx: CLR yyy: MOV 088.0 C,088.1 CPL C MOV 088.1,C SJMP zzz unsigned char ret_bit_err(void) MOV R7, #000 { JB return !P00; }  JNB if (P00==1){ P10=1; } 080.0, xxx ; it possible to be error MOV R7, #001 xxx: RET Preventative measures (2 cases)  Do not use input bit port for bit operation but for byte operation. Using byte operation instead of bit oper ation will not cause any error in using compare jump instructions for input port. MOV A, 080 if ((P0&0x01)==0x01){ P10=1; } JNB 0E0.0, xxx else { P10=0; } SETB 088.0 SJMP yyy xxx: CLR 088.0 yyy: MOV C,088.1 CPL C MOV 088.1,C SJMP zzz while(1){ zzz: P11^=1; } PS030001-0212 PRELIMINARY ; read as byte ; compare 214 Z51F3221 Product Specification  If you use input bit port for compare jump instruction, you have to copy the input port as internal paramet er or carry bit and then use compare jump instruction. bit tt; zzz: while(1){ MOV C,080.0 ; input port use internal parameter MOV 020.0, C ; move 020.0, xxx ; compare tt=P00; JB if (tt==0){ P10=1;} SETB SJMP yyy xxx: CLR 088.0 yyy: MOV C,088.1 CPL C MOV 088.1,C SJMP zzz else {P10=0;} P11^=1; } PS030001-0212 088.0 PRELIMINARY 215 Z51F3221 Product Specification 216 Customer Support To share comments, get your technical questions answered, or report issues you may be experiencing with our products, please visit Zilog’s Technical Support page at  http://support.zilog.com. To learn more about this product, find additional documentation, or to discover other facets about Zilog product offerings, please visit the Zilog Knowledge Base or consider participating in the Zilog Forum. This publication is subject to replacement by a later edition. To determine whether a later edition exists, please visit the Zilog website at http://www.zilog.com. PS030002-0212 PRELIMINARY Customer Support