Z51F6412ATX

Z8051 Series 8-Bit Microcontrollers Z51F6412 Product Specification PS030302-0212 PRELIMINARY Copyright ©2012 Zilog®, Inc. All rights reserved. www.zilog.com Z51F6412 Product Specification ii Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2012 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8051 is a trademark or registered trademark of Zilog, Inc. All other product or service names are the property of their respective owners. PS030302-0212 PRELIMINARY Z51F6412 Product Specification iii Revision History Each instance in this document’s revision history reflects a change from its previous edition. For more details, refer to the corresponding page(s) or appropriate links furnished in the table below. Revision Level Description Page Feb 2012 02 Removed references to 14 mm x 14 mm 64-pin LQFP package. All Jan 2012 01 Original Zilog issue. All Date PS030302-0212 PRELIMINARY Revision History Z51F6412 Product Specification Table of Contents 1. Overview ................................................................................................................................................................ 8 1.1 Description ...................................................................................................................................................... 8 1.2 Features ........................................................................................................................................................... 8 1.3 Ordering Information ...................................................................................................................................... 9 1.4 Development Tools ....................................................................................................................................... 10 2. Block Diagram ..................................................................................................................................................... 13 3. Pin Assignmnet .................................................................................................................................................... 14 4. Package Diagram ................................................................................................................................................. 16 5. Pin Description ..................................................................................................................................................... 18 6. Port Structures ...................................................................................................................................................... 21 6.1 General Purpose I/O Port .............................................................................................................................. 21 6.2 External Interrupt I/O Port ............................................................................................................................ 22 7. Electrical Characteristics ..................................................................................................................................... 23 7.1 Absolute Maximum Ratings ......................................................................................................................... 23 7.2 Recommended Operating Conditions ........................................................................................................... 23 7.3 A/D Converter Characteristics ...................................................................................................................... 24 7.4 Voltage Dropout Converter Characteristics ................................................................................................. 24 7.5 Power-On Reset Characteristics ................................................................................................................... 25 7.6 Brown Out Detector Characteristics ............................................................................................................. 25 7.7 Internal RC Oscillator Characteristics .......................................................................................................... 25 7.8 Ring-Oscillator Characteristics ..................................................................................................................... 26 7.9 PLL Characteristics ....................................................................................................................................... 26 7.10 DC Characteristics ...................................................................................................................................... 27 7.11 AC Characteristics ...................................................................................................................................... 28 7.12 SPI Characteristics ...................................................................................................................................... 29 7.13 Typical Characteristics ................................................................................................................................ 30 8. Memory ................................................................................................................................................................ 31 8.1 Program Memory .......................................................................................................................................... 31 8.2 Data Memory................................................................................................................................................. 32 8.3 XSRAM Memory .......................................................................................................................................... 33 8.4 SFR Map........................................................................................................................................................ 34 9. I/O Ports ............................................................................................................................................................... 37 9.1 I/O Ports ........................................................................................................................................................ 37 9.2 Port Register .................................................................................................................................................. 37 9.3 Px Port ........................................................................................................................................................... 39 10. Interrupt Controller ............................................................................................................................................ 42 10.1 Overview ..................................................................................................................................................... 42 10.2 External Interrupt ........................................................................................................................................ 43 10.3 Block Diagram ............................................................................................................................................ 44 10.4 Interrupt Vector Table ................................................................................................................................. 45 10.5 Interrupt Sequence ...................................................................................................................................... 46 10.6 Effective Timing after Controlling Interrupt bit......................................................................................... 47 10.7 Multi Interrupt ............................................................................................................................................. 48 10.8 Interrupt Enable Accept Timing ................................................................................................................. 49 PS030302-0212 PRELIMINARY 1 Z51F6412 Product Specification 10.9 Interrupt Service Routine Address.............................................................................................................. 49 10.10 Saving/Restore General-Purpose Registers .............................................................................................. 49 10.11 Interrupt Timing ........................................................................................................................................ 50 10.12 Interrupt Register Overview ..................................................................................................................... 51 10.13 Interrupt Register Description .................................................................................................................. 52 11. Peripheral Hardware .......................................................................................................................................... 58 11.1 Clock Generator .......................................................................................................................................... 58 11.2 BIT ............................................................................................................................................................... 62 11.3 WDT ............................................................................................................................................................ 64 11.4 WT ............................................................................................................................................................... 67 11.5 Timer/PWM ................................................................................................................................................ 70 11.6 Buzzer Driver .............................................................................................................................................. 92 11.7 USART ........................................................................................................................................................ 94 11.8 SPI ............................................................................................................................................................. 112 11.9 I2C .............................................................................................................................................................. 117 11.10 12-Bit A/D Converter.............................................................................................................................. 134 11.11 CALCULATOR_AI................................................................................................................................ 140 12. Power Down Operation.................................................................................................................................... 145 12.1 Overview ................................................................................................................................................... 145 12.2 Peripheral Operation in IDLE/STOP Mode ............................................................................................. 145 12.3 IDLE mode ................................................................................................................................................ 146 12.4 STOP mode ............................................................................................................................................... 147 12.5 Release Operation of STOP1, 2 Mode ..................................................................................................... 148 13. RESET .............................................................................................................................................................. 150 13.1 Overview ................................................................................................................................................... 150 13.2 Reset source............................................................................................................................................... 150 13.3 Block Diagram .......................................................................................................................................... 150 13.4 RESET Noise Canceller ............................................................................................................................ 151 13.5 Power ON RESET..................................................................................................................................... 151 13.6 External RESETB Input ............................................................................................................................ 154 13.7 Brown Out Detector Processor ................................................................................................................. 155 14. On-chip Debug System .................................................................................................................................... 158 14.1 Overview ................................................................................................................................................... 158 14.2 Two-pin external interface ........................................................................................................................ 159 15. Memory Programming ..................................................................................................................................... 163 15.1 Overview ................................................................................................................................................... 163 15.2 Flash Control and status register............................................................................................................... 163 15.3 Memory map ............................................................................................................................................. 167 15.4 Serial In-System Program Mode............................................................................................................... 169 15.5 Parallel Mode ............................................................................................................................................ 174 15.6 Mode entrance method of ISP and byte-parallel mode ............................................................................ 177 15.7 Security ...................................................................................................................................................... 178 16. Configure option .............................................................................................................................................. 179 16.1 Configure option Control Register ........................................................................................................... 179 17. APPENDIX ...................................................................................................................................................... 180 PS030302-0212 PRELIMINARY 2 Z51F6412 Product Specification List Of Figures Figure 1-2 Single Programmer ................................................................................................................ 12 Figure 1-3 Gang Programmer .................................................................................................................. 12 Figure 2-1 Z51F6412 block diagram....................................................................................................... 13 Figure 3-1 Z51GF64 80-Pin LQFP assignment ...................................................................................... 14 Figure 3-2 Z51GF64A 64 pin LQFP assignment.................................................................................... 15 Figure 4-1 80 pin LQFP package ............................................................................................................ 16 Figure 4-2 64 pin LQFP package ............................................................................................................ 17 Figure 6-1 General Purpose I/O Port ....................................................................................................... 21 Figure 6-2 External Interrupt I/O Port ..................................................................................................... 22 Figure 7-1 AC Timing ............................................................................................................................. 28 Figure 7-2 SPI Timing ............................................................................................................................. 29 Figure 8-1 Program memory ................................................................................................................... 31 Figure 8-2 Data memory map .................................................................................................................. 32 Figure 8-3 Lower 128 bytes RAM .......................................................................................................... 33 Figure 8-4 XDATA memory area ........................................................................................................... 33 Figure 10-1 External Interrupt Description ............................................................................................. 43 Figure 10-2 Block Diagram of Interrupt ................................................................................................. 44 Figure 10-3 Interrupt Vector Address Table ........................................................................................... 46 Figure 10-4 Effective time of interrupt request after setting IEx registers............................................. 47 Figure 10-5 Execution of Multi Interrupt ................................................................................................ 48 Figure 10-6 Interrupt Response Timing Diagram ................................................................................... 49 Figure 10-7 Correspondence between vector Table address and the entry address of ISP.................... 49 Figure 10-8 Saving/Restore Process Diagram & Sample Source ........................................................... 49 Figure 10-9 Timing chart of Interrupt Acceptance and Interrupt Return Instruction ............................ 50 Figure 11-1 Clock Generator Block Diagram ......................................................................................... 58 Figure 11-2 BIT Block Diagram ............................................................................................................. 62 Figure 11-3 WDT Block Diagram ........................................................................................................... 64 Figure 11-4 WDT Interrupt Timing Waveform ...................................................................................... 66 Figure 11-5 Watch Timer Block Diagram .............................................................................................. 67 Figure 11-6 Bit Timer/Event Counter2, 3 Block Diagram ..................................................................... 71 Figure 11-7 Timer/Event Counter0, 1 Example ...................................................................................... 72 Figure 11-8 Operation Example of Timer/Event Counter0, 1 ................................................................ 72 Figure 11-9 16 Bit Timer/Event Counter0, 1 Block Diagram ................................................................ 73 Figure 11-10 8-bit Capture Mode for Timer0, 1 ..................................................................................... 74 Figure 11-11 Input Capture Mode Operation of Timer 0, 1 ................................................................... 75 Figure 11-12 Express Timer Overflow in Capture Mode ....................................................................... 75 Figure 11-13 16-bit Capture Mode of Timer 0, 1 ................................................................................... 76 Figure 11-14 PWM Mode........................................................................................................................ 77 Figure 11-15 Example of PWM at 4MHz ............................................................................................... 78 Figure 11-16 Example of Changing the Period in Absolute Duty Cycle at 4Mhz................................. 78 Figure 11-17 Timer4 16-bit Mode Block Diagram ................................................................................. 83 Figure 11-18 16-bit Capture Mode of Timer x ....................................................................................... 84 Figure 11-19 PWM Mode........................................................................................................................ 85 PS030302-0212 PRELIMINARY 3 Z51F6412 Product Specification Figure 11-20 Example of PWM at 8MHz ............................................................................................... 86 Figure 11-21 Buzzer Driver Block Diagram ........................................................................................... 92 Figure 11-22 USART Block Diagram..................................................................................................... 95 Figure 11-23 Clock Generation Block Diagram ..................................................................................... 96 Figure 11-24 Synchronous Mode XCKn Timing.................................................................................... 97 Figure 11-25 frame format....................................................................................................................... 98 Figure 11-26 Start Bit Sampling............................................................................................................ 102 Figure 11-27 Sampling of Data and Parity Bit...................................................................................... 102 Figure 11-28 Stop Bit Sampling and Next Start Bit Sampling ............................................................. 103 Figure 11-29 SPI Clock Formats when UCPHA=0 .............................................................................. 104 Figure 11-30 SPI Clock Formats when UCPHA=1 .............................................................................. 105 Figure 11-31 SPI Block Diagram .......................................................................................................... 112 Figure 11-32 SPI Transmit/Receive Timing Diagram at CPHA = 0 .................................................... 114 Figure 11-33 SPI Transmit/Receive Timing Diagram at CPHA = 1 .................................................... 114 Figure 11-34 I2C Block Diagram .......................................................................................................... 117 Figure 11-35 Bit Transfer on the I2C-Bus ............................................................................................. 118 Figure 11-36 START and STOP Condition .......................................................................................... 118 Figure 11-37 Data Transfer on the I2C-Bus .......................................................................................... 119 Figure 11-38 Acknowledge on the I2C-Bus .......................................................................................... 119 Figure 11-39 Clock Synchronization during Arbitration Procedure .................................................... 120 Figure 11-40 Arbitration Procedure of Two Masters............................................................................ 120 Figure 11-41 Formats and States in the Master Transmitter Mode ...................................................... 123 Figure 11-42 Formats and States in the Master Receiver Mode .......................................................... 125 Figure 11-43 Formats and States in the Slave Transmitter Mode ........................................................ 127 Figure 11-44 Formats and States in the Slave Receiver Mode ............................................................. 129 Figure 11-45 ADC Block Diagram ....................................................................................................... 134 Figure 11-46 A/D Analog Input Pin Connecting Capacitor ................................................................. 135 Figure 11-47 A/D Power(AVDD) Pin Connecting Capacitor .............................................................. 135 Figure 11-48 ADC Operation for Align bit ........................................................................................... 135 Figure 11-49 Converter Operation Flow ............................................................................................... 136 Figure 11-50 Calculator Block Diagram ............................................................................................... 140 Figure 12-1 IDLE Mode Release Timing by External Interrupt .......................................................... 146 Figure 12-2 IDLE Mode Release Timing by /RESET .......................................................................... 146 Figure 12-3 STOP Mode Release Timing by External Interrupt .......................................................... 147 Figure 12-4 Mode Release Timing by /RESET .................................................................................... 147 Figure 12-5 STOP1, 2 Mode Release Flow .......................................................................................... 148 Figure 13-1 RESET Block Diagram ..................................................................................................... 150 Figure 13-2 Reset noise canceller time diagram ................................................................................... 151 Figure 13-3 Fast VDD rising time ......................................................................................................... 151 Figure 13-4 Internal RESET Release Timing On Power-Up ............................................................... 152 Figure 13-5 Configuration timing when Power-on ............................................................................... 152 Figure 13-6 Boot Process Waveform .................................................................................................... 153 Figure 13-7 Timing Diagram after RESET ........................................................................................... 154 Figure 13-8 Oscillator generating waveform example ......................................................................... 154 Figure 13-9 Block Diagram of BOD ..................................................................................................... 155 PS030302-0212 PRELIMINARY 4 Z51F6412 Product Specification Figure 13-10 Internal Reset at the power fail situation......................................................................... 155 Figure 13-11 Configuration timing when BOD RESET....................................................................... 156 Figure 14-1 Block Diagram of On-chip Debug System ....................................................................... 159 Figure 14-2 10-bit transmission packet ................................................................................................. 160 Figure 14-3 Data transfer on the twin bus ............................................................................................. 160 Figure 14-4 Bit transfer on the serial bus .............................................................................................. 161 Figure 14-5 Start and stop condition ..................................................................................................... 161 Figure 14-6 Acknowledge on the serial bus .......................................................................................... 161 Figure 14-7 Clock synchronization during wait procedure .................................................................. 162 Figure 14-8 Connection of transmission ............................................................................................... 162 Figure 15-1 Flash Memory Map............................................................................................................ 167 Figure 15-2 Address configuration of Flash memory ........................................................................... 168 Figure 15-3 The sequence of page program and erase of Flash memory ............................................. 169 Figure 15-4 The sequence of bulk erase of Flash memory ................................................................... 170 Figure 15-5 Pin diagram for parallel programming .............................................................................. 174 Figure 15-6 Parallel Byte Read Timing of Program Memory .............................................................. 175 Figure 15-7 Parallel Byte Write Timing of Program Memory ............................................................. 176 Figure 15-8 ISP mode ............................................................................................................................ 177 Figure 15-9 Byte-parallel mode............................................................................................................. 177 PS030302-0212 PRELIMINARY 5 Z51F6412 Product Specification List Of Tables Table 1-1 Ordering Information for the Z51F6412 MCU ........................................................................ 9 Table 5-1 Normal Pin description ........................................................................................................... 18 Table 7-1 Absolute Maximum Ratings ................................................................................................... 23 Table 7-2 Recommended Operation Conditions ..................................................................................... 23 Table 7-3 A/D Converter Characteristics ................................................................................................ 24 Table 7-4 Voltage Dropout Converter Characteristics ........................................................................... 24 Table 7-5 Power-On Reset Characteristics ............................................................................................. 25 Table 7-6 Brown Out Detector Characteristics ....................................................................................... 25 Table 7-7 Internal RC Oscillator Characteristics .................................................................................... 25 Table 7-8 Ring-Oscillator Characteristics ............................................................................................... 26 Table 7-9 PLL Characteristics ................................................................................................................. 26 Table 7-10 DC Characteristics ................................................................................................................ 27 Table 7-11 AC Characteristics ................................................................................................................ 28 Table 7-12 SPI Characteristics ................................................................................................................ 29 Table 8-1 SFR Map Summary ................................................................................................................. 34 Table 9-1 Register Map ........................................................................................................................... 38 Table 10-1 Interrupt Group Priority Level .............................................................................................. 42 Table 10-2 Interrupt Vector Address Table ............................................................................................ 45 Table 10-3 Register Map ......................................................................................................................... 52 Table 11-1 Register Map ......................................................................................................................... 59 Table 11-2 VDC current consumption .................................................................................................... 61 Table 11-3 Register Map ......................................................................................................................... 62 Table 11-4 Register Map ......................................................................................................................... 64 Table 11-5 Register Map ......................................................................................................................... 67 Table 11-6 Operating Modes of Timer.................................................................................................... 70 Table 11-7 PWM Frequency vs. Resolution at 8 Mhz............................................................................ 77 Table 11-8 Register Map ......................................................................................................................... 79 Table 11-9 PWM Frequency vs. Resolution at 8 Mhz............................................................................ 85 Table 11-10 Register Map ....................................................................................................................... 86 Table 11-11 Buzzer Frequency at 16MHz .............................................................................................. 92 Table 11-12 Register Map ....................................................................................................................... 93 Table 11-13 Equations for Calculating Baud Rate Register Setting ...................................................... 96 Table 11-14 CPOL Funtionality ............................................................................................................ 103 Table 11-15 Register Map ..................................................................................................................... 105 Table 11-16 Examples of UBAUD Settings for Commonly Used Oscillator Frequencies ................. 111 Table 11-17 Register Map ..................................................................................................................... 114 Table 12-1 Peripheral Operation during Power Down Mode. .............................................................. 145 Table 12-2 Register Map ....................................................................................................................... 149 Table 13-1 Reset state ............................................................................................................................ 150 Table 13-2 Boot Process Description .................................................................................................... 153 Table 13-3 Register Map ....................................................................................................................... 156 Table 15-1 Register Map ....................................................................................................................... 163 Table 15-2 Program/erase Time ............................................................................................................ 165 PS030302-0212 PRELIMINARY 6 Z51F6412 Product Specification Table 15-3 Operation Mode .................................................................................................................. 173 Table 15-4 The selection of memory type by ADDRH[7:4] ................................................................ 174 Table 15-5 Security policy using lock-bits ........................................................................................... 178 PS030302-0212 PRELIMINARY 7 Z51F6412 Product Specification Z51F6412 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 12-BIT A/D CONVERTER 1. Overview 1.1 Description The Z51F6412 MCU is advanced CMOS 8-bit microcontroller with 64K bytes of Flash. This is powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. This provides the following features : 64K bytes of Flash, 256 bytes of SRAM, 3K bytes of XRAM, general purpose I/O, 8/16-bit timer/counter, watchdog timer, watch timer, SPI, USART, I2C, Calculator, on-chip POR and BOD, 12-bit A/D converter, buzzer driving port, 16-bit PWM output, on-chip oscillator, and clock circuitry. The Z51F6412 MCU also supports power saving modes to reduce power consumption. Device Name Flash XRAM SRAM ADC Z51F6412ATX Package 80-pin LQFP 64KB 3KB 256 bytes 15 channel Z51F6412ARX 64-pin LQFP 1.2 Features • CPU • Basic Interval Timer - 8 Bit CISC Core (8051 Compatible,2 clock per cycle) • 64K Bytes On-chip Flash - 8Bit×2ch(16Bit×1ch) + 16Bit×4ch • One 10-bit PWM (using Timer1) - Endurance : 100,000 times • Four 16-bit PWMs (using Timer2,3,4,5) - Retention : 10 years • Watch Dog Timer • 256 Bytes SRAM(IRAM) • Watch Timer • 3K Bytes XRAM • 2 SPIs • General Purpose I/Os - 66 Ports (P0[7:0], P1[7:0], P2[7:0], P3[7:0], P4[7:0], P5[7:0], P6[7:0], P7[7:0], P8[1:0]) : 80 Pin - 52 Ports (P0[7:0], P1[7:0], P2[7:0], P3[7:0], P4[7:0], P5[7:0], P6[3:0]) : 64 Pin - Support TTL compatible PADs (P3[7:0], SPI0, USART1) PS030302-0212 • Six Timers/Counters • 4 USARTs • I2C • Buzzer Driving Port • Calculator - Multiplier mode : 16bits x 16bits - Divider mode : 32bits / 16bits • 12 Bit A/D Converter PRELIMINARY 8 Z51F6412 Product Specification - 15 Input channels - 1.6V / 2.5V / 3.6V / 4.2V • Interrupt Sources • Minimum Instruction Execution Time - External (8) - 125ns (@16MHz, NOP Instruction) • Power down mode - Pin Change Interrupt (P0, P7) (2) - USART (8) - IDLE, STOP1, STOP2 mode • Sub-Active mode - SPI (2) - Timer (6) - System used external 32.768KHz crystal • Operating Frequency - I2C (1) - ADC (1) - 1MHz ~ 10MHz (crystal oscillator) - WDT (1) - 2, 4, 8, 16MHz (internal RC oscillator) - WT (1) - 1.38MHz ~ 14.75MHz (PLL) • Operating Voltage - BIT (1) - NVM(Flash) (1) - 3.0V ~ 5.5V (@ 1 ~ 16 MHz) • On-Chip RC-Oscillator - 2.0V ~ 5.5V (@ 1 ~ 10 MHz) • Operating Temperature : -40 ~ +85℃ - 16MHz (±2% after tuning) • On-Chip PLL • Package Type - 1.38MHz to 14.75MHz (max) - 80 LQFP • Power On Reset - 64 LQFP - 1.4V - Pb free package • Programmable Brown-Out Detector 1.3 Ordering Information Table 1-1 Ordering Information for the Z51F6412 MCU Device Name ROM Size SRAM Size XRAM Size Z51F6412ATX 80-pin LQFP 64KB Flash 256 bytes Z51F6412ARX PS030302-0212 Package 3KB 64-pin LQFP PRELIMINARY 9 Z51F6412 Product Specification 1.3.1 Part Number Suffix Designation Zilog part numbers consist of a number of components, as indicated in the following example. Example: Part number Z51F6412ATX is an 8-bit MCU with 64 KB of Flash memory and 3.25 KB of RAM in an 80-pin LQFP package and operating within a –40°C to +85°C temperature range. In accordance with RoHS standards, this device has been built using lead-free solder. Z51 F 64 12 A T X Temperature Range X = –40°C to +85°C Pin Count R = 64 pins T = 80 pins Package A = LQFP Device Type Flash Memory Size 64 = 64 KB Flash Flash Memory F = General-Purpose Flash Device Family Z51 = Z8051 8-Bit Core MCU 1.4 Development Tools 1.4.1 Compiler We do not provide the compiler. Please contact third parties. The Z51F6412 MCU core is Mentor 8051. Device ROM size of standard 8051 is smaller than 64KB. Developer can use all kinds of third party’s standard 8051 compiler. 1.4.2 OCD emulator and debugger The OCD (On Chip Debug) emulator supports Zilog’s 8051 series MCU emulation. The OCD interface uses two wires interfacing between PC and MCU which is attached to user’s system. The OCD can read or change the value of MCU internal memory and I/O peripherals. And also the OCD controls MCU internal debugging logic, it means OCD controls emulation, step run, monitoring, etc. PS030302-0212 PRELIMINARY 10 Z51F6412 Product Specification The OCD Debugger program works on Microsoft-Windows NT, 2000, XP, Vista (32bit) operating system. If you want to see more details, please refer OCD debugger manual. You can download debugger S/W and manual from our web-site. Connection: - SCLK (Z51F6412 DSCL pin) - SDATA (Z51F6412 DSDA pin) PS030302-0212 PRELIMINARY 11 Z51F6412 Product Specification 1.4.3 Programmer Single programmer: PGMplus USB: It programs MCU device directly. Figure 1-1 Single Programmer OCD emulator: It can write code in MCU device too. Because of, OCD debugging supports ISP (In System Programming). It does not require additional H/W, except developer’s target system. Gang programmer: It programs 8 MCU devices at once. So, it is mainly used in mass production line. Gang programmer is standalone type, it means it does not require host PC. Figure 1-2 Gang Programmer PS030302-0212 PRELIMINARY 12 Z51F6412 Product Specification 2. Block Diagram nTEST DSCL / DSDA P36/AN14 P35/AN13 P34/AN12 P33/AN11 P32/AN10 P31/AN9 P30/AN8 P27/AN7 P26/AN6 P25/AN5 P24/AN4 P23/AN3 P22/AN2 P21/AN1 P20/AVREF/AN0 P51/EC0 P60/EC2 P61/EC3 P64/EC4 P65/EC5 P52/T0 P53/T1(PWM1) P54/T2(PWM2) P55/T3(PWM3) P56/T4(PWM4) P57/T5(PWM5) P37/MISO0 P36/MOSI0 P35/SCK0 P34/SSS0 P47/MISO1 P46/MOSI1 P45/SCK1 P44/SSS1 P03/RxD0 P02/TxD0 P01/ACK0 P00/USS0 P33/RxD1 P32/TxD1 P31/ACK1 P30/USS1 P43/RxD2 P42/TxD2 P41/ACK2 P40/USS2 P26/RxD3 P26/TxD3 P25/ACK3 P24/USS3 P07/SDA P06/SCL P0 PORT P1 PORT P2 PORT P3 PORT P4 PORT P5 PORT On –Chip Debug 12-BIT ADC M8051 CORE SRAM (256B) SFRs TIMER & PWM Flash (64K byte) P6 * PORT P7 * PORT P8 * PORT P07~P00 P17~P10 P27~P20 P37~P30 P47~P40 P57~P50 P67~P60 P77~P70 P81~P80 XRAM (3KB) Power on Reset BUZZER SPI0 P50/BUZ Calculator BIT SPI1 Brown Out Detector USART0 PLL 14.75MHz USART1 INT-RC OSC 16MHz USART2 WDT WT Interrupt Controller Voltage Down Convertor USART3 P00 ~ P07/ PCI0 P70 ~ P77/ PCI7 * P10/INT0 P11/INT1 P12/INT2 P13/INT3 P14/INT4 P15/INT5 P16/INT6 P17/INT7 SUBXIN/P04 CLOCK/ SYSTEM CON I2C SUBXOUT/P05 XIN/P62 XOUT/P63 nRESET VDD18 VDD VSS “*” means that the function is not included in Z51F6412A. Check APPENDIX B. Figure 2-1 Z51F6412 block diagram PS030302-0212 PRELIMINARY 13 Z51F6412 Product Specification 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 P54/T2(PWM2) P56/T4(PWM4) P55/T3(PWM3) P57/T5(PWM5) P60/EC2 nRESET P61/EC3 P65/EC5 P64/EC4 P66 P62/XIN P67 P63/XOUT LPF VSS DSCL VDD nTEST DSDA VDD18 3. Pin Assignmnet 63 62 61 60 P53/T1(PWM1) 59 58 P52/T0 P51/EC0 5 57 56 P50/BUZ P47/MISO1 P05/PCI05/SUBXOUT 6 P06/PCI06/SCL 7 P07/PCI07/SDA 8 55 54 P46/MOSI1 P45/SCK1 53 52 P44/SSS1 VDD 51 50 VSS P81 49 48 47 46 P80 P43/RxD2 P42/TxD2 P41/ACK2 45 P40/USS2 44 P37/MISO0 P36/MOSI0/AN14 P35/SCK0/AN13 P34/SSS0/AN12 P00/PCI00/USS0 1 P01/PCI01/ACK0 2 P02/PCI02/TxD0 3 P03/PCI03/RxD0 4 P70/PCI70 9 Z51F6412 38 39 40 43 42 41 P33/RxD1/AN11 P27/RxD3/AN7 P30/USS1/AN8 P26/TxD3/AN6 VDD VSS P77/PCI77 P75/PCI75 P76/PCI76 P74/PCI74 P25/ACK3/AN5 P23/AN3 P21/AN1 P22/AN2 P17/INT7 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 P20/AN0/AVREF 21 P16/INT6 P10/INT0 13 P11/INT1 14 P12/INT2 15 P13/INT3 16 P14/INT4 17 P15/INT5 18 VSS 19 VDD 20 P32/TxD1/AN10 P72/PCI72 11 P73/PCI73 12 P31/ACK1/AN9 P71/PCI71 10 P24/USS3/AN4 P04/PCI04/SUBXIN Figure 3-1 Z51GF64 80-Pin LQFP assignment PS030302-0212 PRELIMINARY 14 LPF VSS P63/XOUT P62/XIN nRESET P61/EC3 P60/EC2 P57/T5(PWM5) 61 60 59 58 57 56 55 54 53 52 P54/T2(PWM2) VDD 62 P56/T4(PWM4) DSCL 63 P55/T3(PWM3) nTEST 64 DSDA VDD18 Z51F6412 Product Specification 51 50 49 P00/PCI00/USS0 1 P01/PCI01/ACK0 2 P02/PCI02/TxD0 3 P03/PCI03/RxD0 4 48 P53/T1(PWM1) 47 P52/T0 46 P51/EC0 45 P50/BUZ 44 P47/MISO1 43 P46/MOSI1 42 P45/SCK1 41 P44/SSS1 40 P43/RxD2 39 P42/TxD2 38 P41/ACK2 P04/PCI04/SUBXIN 5 P05/PCI05/SUBXOUT 6 P06/PCI06/SCL 7 P07/PCI07/SDA 8 P10/INT0 9 P11/INT1 10 P12/INT2 11 P13/INT3 12 37 P40/USS2 13 36 P37/MISO0 P15/INT5 14 35 P36/MOSI0/AN14 VSS 15 34 P35/SCK0/AN13 VDD 16 33 P34/SSS0/AN12 20 21 22 23 24 25 26 27 28 29 30 31 32 P22/AN2 P23/AN3 P24/USS3/AN4 P25/ACK3/AN5 VSS VDD P26/TxD3/AN6 P27/RxD3/AN7 P30/USS1/AN8 P31/ACK1/AN9 P32/TxD1/AN10 P33/RxD1/AN11 P17/INT7 19 P21/AN1 18 P20/AN0/AVREF 17 P16/INT6 P14/INT4 Z51F6412 Figure 3-2 Z51GF64A 64 pin LQFP assignment PS030302-0212 PRELIMINARY 15 Z51F6412 Product Specification 4. Package Diagram Figure 4-1 80 pin LQFP package PS030302-0212 PRELIMINARY 16 Z51F6412 Product Specification Figure 4-2 64 pin LQFP package PS030302-0212 PRELIMINARY 17 Z51F6412 Product Specification 5. Pin Description Table 5-1 Normal Pin description PIN Name I/O Function @RESET Shared with P00 Port P0 USS0/PCI0 P01 8-Bit I/O Port ACK0/PCI0 P02 Can be set in input or output mode in 1-bit units TxD0/PCI0 P03 I/O P04 Internal pull-up register can be used via software when this port is used as input port RxD0/PCI0 Input SUBXIN/PCI0 Open Drain enable register can be used via software when this port is used as output port P05 SUBXOUT/PCI0 P06 SCL/PCI0 P07 SDA/PCI0 P10 Port P1 INT0 P11 8-Bit I/O Port INT1 P12 Can be set in input or output mode in 1-bit units INT2 P13 I/O P14 Internal pull-up register can be used via software when this port is used as input port INT3 Input INT4 Open Drain enable register can be used via software when this port is used as output port P15 INT5 P16 INT6 P17 INT7 P20 Port P2 P21 8-Bit I/O Port AN1 P22 Can be set in input or output mode in 1-bit units AN2 P23 I/O P24 AN0/AVREF Internal pull-up register can be used via software when this port is used as input port AN3 Input AN4/USS3 Open Drain enable register can be used via software when this port is used as output port P25 AN5/ACK3 P26 AN6/TxD3 P27 AN7/RxD3 P30 Port P3 (TTL compatible input, PAD) AN8/USS1 P31 8-Bit I/O Port AN9/ACK1 P32 Can be set in input or output mode in 1-bit units P33 I/O P34 Internal pull-up register can be used via software when this port is used as input port AN10/TxD1 Input AN11/RxD1 AN12/SSS0 P35 Open Drain enable register can be used via software when this port is used as output port AN13/SCK0 P36 AN0~AN7 can be selected by ADCM register AN14/MOSI0 PS030302-0212 PRELIMINARY 18 Z51F6412 Product Specification P37 MISO0 P40 Port P4 USS2 P41 8-Bit I/O Port ACK2 P42 Can be set in input or output mode in 1-bit units TxD2 P43 I/O P44 Internal pull-up register can be used via software when this port is used as input port RxD2 Input SSS1 Open Drain enable register can be used via software when this port is used as output port P45 SCK1 AN8~AN13 can be selected by ADCM register P46 MOSI1 P47 MISO1 P50 Port P5 BUZ P51 8-Bit I/O Port EC0 P52 Can be set in input or output mode in 1-bit units P53 I/O P54 Internal pull-up register can be used via software when this port is used as input port T0 T1(PWM1) Input T2(PWM2) Open Drain enable register can be used via software when this port is used as output port P55 T3(PWM3) P56 T4(PWM4) P57 T5(PWM5) P60 Port P6 EC2 P61 6-Bit I/O Port EC3 P62 Can be set in input or output mode in 1-bit units XIN P63 I/O P64 Internal pull-up register can be used via software when this port is used as input port XOUT Input EC4 Open Drain enable register can be used via software when this port is used as output port P65 EC5 P66 - P67 - P70 Port P7 PCI70 P71 8-Bit I/O Port PCI71 P72 Can be set in input or output mode in 1-bit units P73 I/O P74 Internal pull-up register can be used via software when this port is used as input port PCI72 Input PCI73 PCI74 Open Drain enable register can be used via software when this port is used as output port P75 PCI75 P76 PCI76 P77 PCI77 P80 Port P8 I/O P81 PS030302-0212 Input 8-Bit I/O Port PRELIMINARY 19 Z51F6412 Product Specification Can be set in input or output mode in 1-bit units - Internal pull-up register can be used via software when this port is used as input port - Open Drain enable register can be used via software when this port is used as output port - LPF is loop pass filter for PLL. LPF A nRESET I XOUT O Main Oscillator output - XIN I Main Oscillator input - VSS P Ground VDD P Power SUBXOUT O Sub Oscillator output - SUBXIN I Sub Oscillator input - DSDA I/O DSCL I If it doesn’t use PLL, it doesn’t need filter circuit and it connects to GND Analog Input OCD Data input/output Input OCD clock input Input TEST mode enable nTEST I nTEST is the same function like internal POR except remaining port configuration setting value. Input nTEST needs about 1k pull-up resistor VDD18 P PS030302-0212 Internal 1.8V VDD Power PRELIMINARY 20 Z51F6412 Product Specification 6. Port Structures 6.1 General Purpose I/O Port LevelShift ( 1.8V to ExtVDD) LevelShift (ExtVDD to 1.8V) VDD PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER VDD 0 PAD MUX SUB-FUNC DATA OUTPUT VDD 1 SUB-FUNC ENABLE DIRECTION REGISTER 0 MUX SUB-FUNC DIRECTION 1 R(400Ω) PORTx INPUT MUX 0 1 0 MUX 1 SUB-FUNC DATA INPUT Q CMOS or SchmittLevel Input D r CP DEBOUNCE CLK DEBOUNCE ENABLE ANALOG CHANNEL ENABLE ANALOG INPUT ANALOG INPUT (without Resistor) Figure 6-1 General Purpose I/O Port PS030302-0212 PRELIMINARY 21 Z51F6412 Product Specification 6.2 External Interrupt I/O Port LevelShift ( 1.8V to ExtVDD) LevelShift (ExtVDD to 1.8V) VDD PULL-UP REGISTER OPEN DRAIN REGISTER VDD DATA REGISTER VDD 0 PAD MUX SUB-FUNC DATA OUTPUT 1 SUB-FUNC ENABLE DIRECTION REGISTER 0 MUX SUB-FUNC DIRECTION EXTERNAL INTERRUPT 1 INTERRUPT ENABLE EDGE REG R(400Ω) MUX 0 1 VDD D Q r POLARITY REG CP FLAG CLEAR PORTx INPUT MUX 0 1 0 MUX 1 SUB-FUNC DATA INPUT Q CMOS or SchmittLevel Input D r CP DEBOUNCE CLK DEBOUNCE ENABLE ANALOG CHANNEL ENABLE ANALOG INPUT Figure 6-2 External Interrupt I/O Port PS030302-0212 PRELIMINARY 22 Z51F6412 Product Specification 7. Electrical Characteristics 7.1 Absolute Maximum Ratings Table 7-1 Absolute Maximum Ratings Parameter Symbol Supply Voltage Normal Voltage Pin Total Power Dissipation Storage Temperature Rating Unit VDD -0.3~+6.5 V VSS -0.3~+0.3 V VI -0.3~VDD+0.3 V VO -0.3~VDD+0.3 V IOH 10 mA ∑IOH 80 mA IOL 20 mA ∑IOL 160 mA PT 600 mW TSTG -45~+125 ℃ Note) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7.2 Recommended Operating Conditions Table 7-2 Recommended Operation Conditions Parameter Supply Voltage Operating Temperature Operating Frequency Symbol VDD Condition fXIN=1~10MHz fSUB=32.768KHz MIN TYP MAX Unit 2.0 - 5.5 V TOPR VDD=2.0~5.5V -40 - 85 ℃ FOPR fXIN 1 - 10 MHz fSUB - 32.768 - KHz Internal RC-OSC - 16 - MHz Internal Ring-OSC PLL PS030302-0212 PRELIMINARY 1 1.38 MHz 14.75 MHz 23 Z51F6412 Product Specification 7.3 A/D Converter Characteristics Table 7-3 A/D Converter Characteristics Parameter Symbol (TA=-40℃ ~ +85℃, VDD=AVDD=2.7V ~ 5.5V, VSS=0V) Condition MIN TYP - - Resolution MAX Unit 12 - bits - ±3 lsb - - ±2 lsb - - ±2 lsb - ±3 lsb - ±3 lsb 60 - cycle Total Accuracy Integral Linear Error INL Differential Linearity Error DLE Zero Offset Error ZOE Full Scale Error FSE Conversion Time tCON AVDD=VDD=5.12V fXIN=4MHz 12bit conversion - max 3MHz Analog Input Voltage VAN - VSS - AVDD=VDD V Analog Power Voltage AVDD - - *AVDD=VDD - V Analog Reference Voltage AVREF - 2.7 - 5.5 V AVSS - - VSS - V AVDD=VDD=5.12V - - 10 uA - 1 3 mA - - 1 uA Analog Ground Voltage Analog Input Leakage Current ADC Operating Current IDD SIDD AVDD=VDD=5.12V 7.4 Voltage Dropout Converter Characteristics Table 7-4 Voltage Dropout Converter Characteristics Parameter Symbol Condition MIN TYP MAX Unit Operating Voltage - 1.8 - 5.5 V Operating Temperature - -40 - +85 ℃ Regulation Voltage - 1.62 1.8 1.98 V Drop-out Voltage - - - 0.02 V RUN/IDLE - 20 - mA SUB-ACTIVE - 1 - mA STOP1 - 50 - uA STOP2 - 10 - uA IDD1 RUN/IDLE - - 1 mA IDD2 SUB-ACTIVE - - 0.1 mA SIDD1 STOP1 - - 5 uA SIDD2 STOP2 - - 0.1 uA TRAN1 SUB to RUN - - 1 uS TRAN2 STOP to RUN - - 200 uS Current Drivability Operating Current Drivability Transition Time Note) -STOP1: WDT running - STOP2: WDT disable PS030302-0212 PRELIMINARY 24 Z51F6412 Product Specification 7.5 Power-On Reset Characteristics Table 7-5 Power-On Reset Characteristics Parameter Symbol Condition MIN TYP MAX Unit Operating Voltage - 1.6 - 5.5 V Operating Temperature - -40 - +85 ℃ RESET Release Level - 1.3 1.4 1.5 V IDD - - - 10 uA SIDD - - - 1 uA Operating Current 7.6 Brown Out Detector Characteristics Table 7-6 Brown Out Detector Characteristics Condition MIN TYP MAX Unit Operating Voltage Parameter Symbol - VSS - 5.5 V Operating Temperature - -40 - +85 ℃ 4.2V - 4.0 4.4 V 3.6V - 3.4 3.8 V 2.5V - 2.3 2.7 V 1.6V - 1.4 1.8 V - - 50 - mV IDD - - - 50 uA SIDD - - - 1 uA Detection Level Hysteresis Operating Current 7.7 Internal RC Oscillator Characteristics Table 7-7 Internal RC Oscillator Characteristics Condition MIN TYP MAX Unit Operating Voltage Parameter - 1.8 - 5.5 V Operating Temperature - -40 - +85 ℃ Frequency - - 16 - MHz Hysteresis - - - 10 mS IDD - - 200 300 uA SIDD - - - 1 uA Operating Current PS030302-0212 Symbol PRELIMINARY 25 Z51F6412 Product Specification 7.8 Ring-Oscillator Characteristics Table 7-8 Ring-Oscillator Characteristics Parameter Symbol Condition MIN TYP MAX Unit Operating Voltage - 1.8 - 5.5 V Operating Temperature - -40 - +85 ℃ Frequency - - 1 - MHz Stabilization Time - - - - mS IDD - - - - uA SIDD - - - 1 uA Operating Current 7.9 PLL Characteristics Table 7-9 PLL Characteristics (TA=-40℃ ~ +85℃, VDD18=1.8V ~ 2.0V, VSS=0V) Parameter Symbol Min. Typ. Max. Units PLL current IPLL – 1.5 TBD mA Input clock frequency fxin – 32.768 – KHz Output clock frequency fout 1.38 – 14.75 MHz Output clock duty – 45 – 55 % Setting time tD – 1 TBD mS Accuracy – – 2 TBD % PS030302-0212 PRELIMINARY Conditions 26 Z51F6412 Product Specification 7.10 DC Characteristics Table 7-10 DC Characteristics Parameter Input Low Voltage Input High Voltage (VDD =2.7~5.5V, VSS =0V, fXIN=10.0MHz, TA=-40~+85℃) Symbol Condition MIN TYP MAX Unit VIL1 nTEST, nRESET, DSCL, DSDA -0.5 - 0.2VDD V VIL2 P0,P1,P2,P4,P5,P6,P7,P8 -0.5 - 0.2VDD V VIL3 P3 (VDD=4.0~5.5V) -0.5 - 0.1VDD+0.4 V VIL4 P3 (VDD=2.7~4.0V) -0.5 - 0.2VDD V VIH1 nTEST, nRESET, DSCL, DSDA 0.8VDD - VDD V VIH2 P0,P1,P2,P4,P5,P6,P7,P8 0.7VDD - VDD V VIH3 P3 0.3VDD+0.7 - VDD V Output Low Voltage VOL1 ALL I/O (IOL=20mA, VDD=4.5V) - - 1 V Output High Voltage VOH1 ALL I/O (IOH=-8.57mA, VDD=4.5V) 3.5 - - V Input High Leakage Current IIH ALL PAD - - 1 uA Input Low Leakage Current IIL ALL PAD -1 - - uA Pull-Up Resister RPU ALL PAD (except DSCL, DSDA) 20 - 50 kΩ Power Supply Current IDD1 Run Mode, fXIN=10MHz @5V - *2.7 15 mA IDD2 Idle Mode, fXIN=10MHz @5V - *1.8 10 mA IDD3 Sub Active Mode, fSUBXIN=32.768KHz @5V (PLL enable) - *0.3 1 mA IDD4 Sub Active Mode, fSUBXIN=32.768KHz @5V (PLL disable) - *112 500 uA IDD5 STOP1 Mode, WDT Active @5V (BOD enable) - *60 150 uA IDD6 STOP1 Mode, WDT Active @5V (BOD disable) - *30 50 uA IDD7 STOP2 Mode, WDT Disable @5V (BOD enable), Room Temp(25℃) - *32 110 uA IDD8 STOP2 Mode, WDT Disable @5V (BOD disable), Room Temp(25℃) - *1 10 uA Note) - STOP1: WDT running, STOP2: WDT disable. - (*) typical test condition : VDD=5V, Internal RC-OSC=8MHz, ROOM TEMP, all PORT output LOW, Timer0 Active, 1PORT toggling. PS030302-0212 PRELIMINARY 27 Z51F6412 Product Specification 7.11 AC Characteristics Table 7-11 AC Characteristics (VDD=5.0V±10%, VSS=0V, TA=-40~+85℃) Parameter Symbol PIN Operating Frequency fMCP XIN 1 System Clock Cycle Time tSYS - 100 tMST1 XIN, XOUT - - Oscillation Stabilization Time (16MHz) External Clock “H” or “L” Pulse Width MIN TYP MAX Unit - 16 MHz - 1000 ns 10 ms tCPW XIN 90 - - ns tRCP,tFCP XIN - - 10 ns tIW INT0~INTx 2 - - tSYS External Interrupt Transition Time tFI,tRI INT0~INTx 1 us nRESET Input Pulse “L” Width tRST nRESET 8 - - tSYS External Counter Input “H” or “L” Pulse Width tECW EC0,EC1 2 - - tSYS tREC,tFEC EC0,EC1 - - 20 ns External Clock Transition Time Interrupt Input Width Event Counter Transition Time 1/fMCP tCPW tCPW 0.9VDD XIN 0.1VDD tRCP tFCP tIW INT0 INT1 INT2 INTx tIW 0.8VDD 0.2VDD tRI tFI tRST nRESET 0.2VDD tECW tECW EC0 0.8VDD ECx 0.2VDD tREC tFEC Figure 7-1 AC Timing PS030302-0212 PRELIMINARY 28 Z51F6412 Product Specification 7.12 SPI Characteristics Table 7-12 SPI Characteristics (VDD=5.0V±10%, VSS=0V, TA=-40~+85℃) Parameter Symbol PIN MIN TYP MAX Output Clock Pulse Period tSCK SCK - SPI clock mode - Input Clock Pulse Period tSCK SCK 2• tSYS Unit ns - - ns 50% duty - ns Input Clock “H” or “L” Pulse Width tSCKL, tSCKH SCK Input Clock Pulse Transition Time tFSCK,tRSCK SCK - - 30 ns Output Clock “H” or “L” Pulse Width tSCKL, tSCKH SCK tSYS-30 - - ns Output Clock Pulse Transition Time tFSCK,tRSCK SCK - - 30 ns tFOD OUTPUT tDS OUTPUT - - 100 ns - 30 ns - ns - ns First Output Clock Delays Time Output Clock Delay Time Input Pulse Transition Time tFSIN,tRSIN INPUT - Input Setup Time tDIS INPUT 100 Input Hold Time tDIH INPUT tSYS+70 - /SS (Output/Input) tFOD tSCK 0.8VDD SCK (CPOL=0) (Output/Input) 0.2VDD tSCKL tSCKH SCK (CPOL=1) (Output/Input) tDIS MISO/MOSI (Data Input) tFSCK tDIH MSB tRSCK LSB tRSIN tFSIN tDS MOSI/MISO (Data Output) MSB LSB Figure 7-2 SPI Timing PS030302-0212 PRELIMINARY 29 Z51F6412 Product Specification 7.13 Typical Characteristics These graphs and tables provided in this section are for design guidance only and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean - 3σ) respectively where σ is standard deviation. PS030302-0212 PRELIMINARY 30 Z51F6412 Product Specification 8. Memory The Z51F6412 MCU addresses two separate address memory stores: Program memory and Data memory. The logical separation of Program and Data memory allows Data memory to be assessed by 8-bit addresses, which can be more quickly stored and manipulated by 8-bit CPU. Nevertheless, 16bit Data memory addresses can also be generated through the DPTR register. Program memory can only be read, not written to. There can be up to 64K bytes of Program memory in a bank. In the Z51F6412 Flash version of these devices the 64K bytes of Program memory are provided on-chip. Data memory can be read and written to up to 256 bytes internal memory (DATA) including the stack area and 3K bytes of external data memory(XRAM). 8.1 Program Memory A 16-bit program counter is capable of addressing up to 64K bytes for one bank of memory space. Figure 8-1 shows a map of the lower part of the program memory. After reset, the CPU begins execution from location 0000H. Each interrupt is assigned a fixed location in program memory. The interrupt causes the CPU to jump to that location, where it commences execution of the service routine. External interrupt 0, for example, is assigned to location 0003H. If external interrupt 0 is going to be used, its service routine must begin at location 0003H. If the interrupt is not going to be used, its service location is available as general purpose program memory. If an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8 byte interval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use. FFFFH Total 64K Bytes Flash 64K Bytes Bank 0 0000H - Figure 8-1 Program memory User Function Mode: 64KBytes Included Interrupt Vector Region - Non-volatile and reprogramming memory: Flash memory PS030302-0212 PRELIMINARY 31 Z51F6412 Product Specification 8.2 Data Memory Figure 8-2 shows the internal Data memory space available. FFh FFh Upper 128 Bytes Special Function Registers Internal RAM 128 Bytes 80h (Indirect Addressing) 7Fh Lower (Direct Addressing) 80h 128 Bytes Internal RAM (Direct or Indirect Addressing) 00h Figure 8-2 Data memory map The internal memory space is divided into three blocks, which are generally referred to as the lower 128, upper 128, and SFR space. Internal Data memory addresses are always one byte wide, which implies an address space of only 256 bytes. However, the addressing modes for internal RAM can in fact accommodate 384 bytes, using a simple trick. Direct addresses higher than 7FH access one memory space and indirect addresses higher than 7FH access a different memory space. Thus Fig 8-2 shows the upper 128 and SFR space occupying the same block of addresses, 80H through FFH, although they are physically separate entities. The lower 128 bytes of RAM are present in all 8051 devices as mapped in Figure 8-3. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers as R0 through R7. Two bits in the Program Status Word select which register bank is in use. This allows more efficient used of code space, since register instructions are shorter than instructions that use direct addressing. The next 16 bytes above the register banks form a block of bit-addressable memory space. The 8051 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00H through 7FH. All of the bytes in the lower 128 can be accessed by either direct or indirect addressing. The upper 128 bytes RAM can only be accessed by indirect addressing. These spaces are used for user RAM and stack pointer. PS030302-0212 PRELIMINARY 32 Z51F6412 Product Specification 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 7FH 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58 57 56 55 54 53 52 51 50 4F 4E 4D 4C 4B 4A 49 48 General purpose register 80 bytes 47 46 45 44 43 42 41 40 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A 29 28 30H 2FH 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 16 bytes (128bits) 20H 1FH 8 bytes 8 bytes 8 bytes 17 16 15 14 13 12 11 10 Bit addressable 18H 17H 10H 0FH 08H 07H 8 bytes 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 Register bank 3 (8 bytes) Register bank 2 (8 bytes) R7 Register bank 1 (8 bytes) R6 Register bank 0 (8 bytes) R4 R5 R3 00H R2 R1 R0 Figure 8-3 Lower 128 bytes RAM 8.3 XSRAM Memory The Z51F6412 MCU use 3K bytes of XSRAM. FFFFH 2FFFH 2F00H 0BFFH 0000H XSFR XSRAM total 3K Bytes (000H~BFFH) Bank0 Figure 8-4 XDATA memory area PS030302-0212 PRELIMINARY 33 Z51F6412 Product Specification 8.4 SFR Map 8.4.1 SFR Map Summary Table 8-1 SFR Map Summary 0H/8H 1H/9H 2H/AH 3H/BH 4H/CH 5H/DH 6H/EH 7H/FH 2F58H - FUSE_PKG FUSE_CAL2 PUSE_CAL1 FUSE_CAL0 FUSE_CONF TEST_B TEST_A 2F50H PSR0 PSR1 - - - - - - 2F48H - - - - - - - - 2F40H - - - - - - - - 2F38H T5CR T5CR1 T5L T5H T5DRL T5DRH - - 2F30H UCTRL31 UCTRL32 UCTRL33 USTAT3 UBAUD3 UDATA3 - - 2F28H UCTRL21 UCTRL22 UCTRL23 USTAT2 UBAUD2 UDATA2 - - 2F20H P8DB - - - - - - - 2F18H P0DB P1DB P2DB P3DB P4DB P5DB P6DB P7DB 2F10H P4OD P5OD P6OD P7OD P8OD - - - 2F08H P8PU - - - P0OD P1OD P2OD P3OD 2F00H P0PU P1PU P2PU P3PU P4PU P5PU P6PU P7PU 34 F8H IP1 - UCTRL11 UCTRL12 UCTRL13 USTAT1 UBAUD1 UDATA1 F0H B SPISR1 FEARH FEARM FEARL FEDR FECR CAL_CNTR E8H - - FEMR FESR FETCR - CAL_ADDR CAL_DATA E0H ACC - UCTRL01 UCTRL02 UCTRL03 USTAT0 UBAUD0 UDATA0 D8H P8 PLLCR I2CMR I2CSR I2CSCLLR I2CSCLHR I2CSDAHR I2CDR D0H PSW P8IO SPICR0 SPIDR0 SPISR0 TMISR I2CSAR1 I2CSAR C8H P7 P7IO T4CR T4CR1 T4L T4H T4DRL T4DRH C0H P6 P6IO T3CR T3CR1 T3L T3H T3DRL T3DRH B8H IP P5IO T2CR T2CR1 T2L T2H T2DRL T2DRH B0H P5 P4IO T0CR T0DR T1CR T1DR T1PWDR T1PWHR A8H IE IE1 IE2 IE3 IE4 IE5 PCI0 PCI7 A0H P4 P3IO EO EIENAB EIFLAG EIEDGE EIPOLA EIBOTH 98H P3 P2IO ADCM ADCRH ADCRL WTMR WTR BUZCR 90H P2 P1IO SPICR1 SPIDR1 - - - - 88H P1 P0IO SCCR BCCR BITR WDTMR WDTR BUZDR 80H P0 SP DPL DPH DPL1 DPH1 BODR PCON PS030302-0212 PRELIMINARY 34 Z51F6412 Product Specification 8.4.2 Compiler Compatible SFR ACC (Accumulator) : E0H 7 6 5 4 3 2 1 R/W R/W R/W 3 2 1 R/W R/W R/W 3 2 1 R/W R/W R/W 3 2 1 R/W R/W R/W 3 2 1 R/W R/W R/W 3 2 1 R/W R/W R/W 0 ACC R/W R/W R/W ACC R/W R/W Initial value : 00H Accumulator B (B Register) : F0H 7 6 5 4 R/W R/W R/W R/W 0 B B R/W Initial value : 00H B Register SP (Stack Pointer) : 81H 7 6 5 4 R/W R/W R/W R/W 0 SP SP R/W Initial value : 07H Stack Pointer DPL (Data Pointer Low Byte) : 82H 7 6 5 4 0 DPL R/W R/W R/W DPL R/W R/W Initial value : 00H Data Pointer Low Byte DPH (Data Pointer High Byte) : 83H 7 6 5 4 0 DPH R/W R/W R/W DPH R/W R/W Initial value : 00H Data Pointer High Byte DPL1 (Data Pointer Low 1 Byte) : 84H 7 6 5 4 R/W R/W R/W R/W 0 DPL1 DPL1 R/W Initial value : 00H Data Pointer Low 1 Byte DPH1 (Data Pointer High 1 Byte) : 85H PS030302-0212 PRELIMINARY 35 Z51F6412 Product Specification 7 6 5 4 3 2 1 R/W R/W R/W 0 DPH1 R/W R/W R/W DPH1 R/W R/W Initial value : 00H Data Pointer High 1 Byte PSW (Program Status Word) : D0H 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P R/W R/W R/W R/W R/W R/W R/W CY Carry Flag AC Auxiliary Carry Flag F0 General Purpose User-Definable Flag R/W Initial value : 00H RS1 Register Bank Select bit 1 RS0 Register Bank Select bit 0 OV Overflow Flag F1 User-Definable Flag P Parity Flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of ‘1’ bits in the accumulator EO (Extended Operation Register) : A2H 7 6 5 4 3 2 1 0 DPSEL.0 - - - TRAP_EN - DPSEL.2 DPSEL.1 R R R R/W R R/W R/W TRAP_EN DPSEL[2:0] Select the instruction 0 Select MOVC @(DPTR++), A 1 Select Software TRAP instruction Select Banked Data Point Register DPSEL2 DPSEL1 DPSEL0 0 0 0 0 0 1 Reserved PS030302-0212 R/W Initial value : 00H PRELIMINARY DPTR0 DPTR1 - 36 Z51F6412 Product Specification 9. I/O Ports 9.1 I/O Ports The Z51F6412 MCU features nine I/O ports (P0 ~ P8). Each port can be easily configured by software as I/O pin, internal pull up and open drain pin to meet various system configurations and design requirements. Also P0, P7 include function that can generate interrupt according to change of state of the pin. 9.2 Port Register 9.2.1 Data Register (Px) Data Register is a bidirectional I/O port. If ports are configured as output ports, data can be written to the corresponding bit of the Px. If ports are configured as input ports, the data can be read from the corresponding bit of the Px. 9.2.2 Direction Register (PxIO) Each I/O pin can independently used as an input or an output through the PxIO register. Bits cleared in this read/write register will select the corresponding pin in Px to become an input, setting a bit sets the pin to output. All bits are cleared by a system reset. 9.2.3 Pull-up Resistor Selection Register (PxPU) The on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up resistor selection register (PxPU). The pull-up register selection controls the pull-up resister enable/disable of each port. When the corresponding bit is 1, the pull-up resister of the pin is enabled. When 0, the pull-up resister is disabled. All bits are cleared by a system reset. Pull-up operation is only enable in input mode. 9.2.4 Open-drain Selection Register (PxOD) There is internally open-drain selection register (PxOD) in P0 ~ P8. The open-drain selection register controls the open-drain enable/disable of each port. Ports become push-pull by a system reset. You should connect an external resistor in open-drain output mode. 9.2.5 Debounce Enable Register (PxDB) P0 ~ P8 support debounce function. Debounce time of each ports has 5us 9.2.6 Pin Change Interrupt Enable Register (PCIx) The P0, P7 can support Pin Change Interrupt function. Pin Change Interrupts PCI will trigger if any enabled P0[7:0], P7[7:0] pin toggles. The PCIx Register control which pins contribute to the pin change interrupts. PS030302-0212 PRELIMINARY 37 Z51F6412 Product Specification 9.2.7 Port Selection Register (PSRx) PSRx registers prevent the input leakage current when ports are connected to analog inputs. If the bit of PSRx is ‘1’, the dynamic current path of the schmitt OR gate of the port is cut off and the digital input of the corresponding port is always ‘0’. 9.2.8 Register Map Table 9-1 Register Map Name Address Dir Default Description P0 80H R/W 00H P0 Data Register P0IO 89H R/W 00H P0 Direction Register P0PU 2F00H R/W 00H P0 Pull-up Resistor Selection Register P0OD 2F0CH R/W 00H P0 Open-drain Selection Register P0DB 2F18H R/W 00H P0 Debounce Enable Register PCI0 AEH R/W 00H P0 Pin Change Interrupt Enable Register P1 88H R/W 00H P1 Data Register P1IO 91H R/W 00H P1 Direction Register P1PU 2F01H R/W 00H P1 Pull-up Resistor Selection Register P1OD 2F0DH R/W 00H P1 Open-drain Selection Register P1DB 2F19H R/W 00H P1 Debounce Enable Register P2 90H R/W 00H P2 Data Register P2IO 99H R/W 00H P2 Direction Register P2PU 2F02H R/W 00H P2 Pull-up Resistor Selection Register P2OD 2F0EH R/W 00H P2 Open-drain Selection Register P2DB 2F1AH R/W 00H P2 Debounce Enable Register P3 98H R/W 00H P3 Data Register P3IO A1H R/W 00H P3 Direction Register P3PU 2F03H R/W 00H P3 Pull-up Resistor Selection Register P3OD 2F0FH R/W 00H P3 Open-drain Selection Register P3DB 2F1BH R/W 00H P3 Debounce Enable Register P4 A0H R/W 00H P4 Data Register P4IO B1H R/W 00H P4 Direction Register P4PU 2F04H R/W 00H P4 Pull-up Resistor Selection Register P4OD 2F10H R/W 00H P4 Open-drain Selection Register P4DB 2F1CH R/W 00H P4 Debounce Enable Register P5 B0H R/W 00H P5 Data Register P5IO B9H R/W 00H P5 Direction Register P5PU 2F05H R/W 00H P5 Pull-up Resistor Selection Register P5OD 2F11H R/W 00H P5 Open-drain Selection Register P5DB 2F1DH R/W 00H P5 Debounce Enable Register P6 C0H R/W 00H P6 Data Register P6IO C1H R/W 00H P6 Direction Register P6PU 2F06H R/W 0CH P6 Pull-up Resistor Selection Register PS030302-0212 PRELIMINARY 38 Z51F6412 Product Specification P6OD 2F12H R/W 00H P6 Open-drain Selection Register P6DB 2F1EH R/W 00H P6 Debounce Enable Register P7 C8H R/W 00H P7 Data Register P7IO C9H R/W 00H P7 Direction Register P7PU 2F07H R/W 00H P7 Pull-up Resistor Selection Register P7OD 2F13H R/W 00H P7 Open-drain Selection Register P7DB 2F1FH R/W 00H P7 Debounce Enable Register PCI7 AFH R/W 00H P7 Pin Change Interrupt Enable Register P8 D8H R/W 00H P8 Data Register P8IO D1H R/W 00H P8 Direction Register P8PU 2F08H R/W 00H P8 Pull-up Resistor Selection Register P8OD 2F14H R/W 00H P8 Open-drain Selection Register P8DB 2F20H R/W 00H P8 Debounce Enable Register PSR0 2F50H R/W 00H Port Selection Register 0 PSR1 2F51H R/W 00H Port Selection Register 1 9.3 Px Port 9.3.1 Px Port Description Px ports are 8-bit General purpose I/O ports except P8. Px control registers consist of Data register (Px), direction register (PxIO), debounce enable register (PxDB), pull-up register selection register (PxPU), open-drain selection register (PxOD), pin change interrupt register (PCI0, PCI7). 9.3.2 Register description for Px Px (Px Data Register) : 80H, 88H, 90H, 98H, A0H, B0H, C0H, C8H, D8H 7 6 5 4 3 2 1 Px7 Px6 Px5 Px4 Px3 Px2 Px1 R/W R/W R/W R/W R/W R/W R/W Px[7:0] 0 Px0 R/W Initial value : 00H I/O Data PxIO (Px Direction Register) : 89H, 91H, 99H, A1H, B1H, B9H, C1H, C9H, D1H 7 6 5 4 3 2 1 0 Px7IO Px6IO Px5IO Px4IO Px3IO Px2IO Px1IO Px0IO R/W R/W R/W R/W R/W R/W R/W PxIO[7:0] R/W Initial value : 00H Px data I/O direction. 0 Input 1 Output PxPU (P0~P7 Pull-up Resistor Selection Register) : 2F00H ~ 2F07H 7 6 5 4 3 2 1 0 Px7PU Px6PU Px5PU Px4PU Px3PU Px2PU Px1PU Px0PU PS030302-0212 PRELIMINARY 39 Z51F6412 Product Specification R/W R/W R/W PxPU[7:0] R/W R/W R/W R/W R/W Initial value : 00H Configure pull-up resistor of Px port 0 Disable 1 Enable Note) P6PU initial value : 0CH . P8PU[7:2] : Not used, P8PU[1:0] : Only used. PxOD (Px Open-drain Selection Register) : 2F0CH ~ 2F14H 7 6 5 4 3 2 1 0 Px7OD Px6OD Px5OD Px4OD Px3OD Px2OD Px1OD Px0OD R/W R/W R/W R/W R/W R/W R/W PxOD[7:0] R/W Initial value : 00H Configure open-drain of Px port 0 Disable 1 Enable PxDB (Px Debounce Enable Register) : 2F18H ~ 2F20H 7 6 5 4 3 2 1 0 Px7DB Px6DB Px5DB Px4DB Px3DB Px2DB Px1DB Px0DB R/W R/W R/W R/W R/W R/W R/W PxDB[7:0] PS030302-0212 R/W Initial value : 00H Configure debounce of Px port 0 Disable 1 Enable PRELIMINARY 40 Z51F6412 Product Specification PCI0 (P0 Pin Change Interrupt Enable Register) : AEH 7 6 5 4 3 2 1 0 PCI07 PCI06 PCI05 PCI04 PCI03 PCI02 PCI01 PCI00 R/W R/W R/W R/W R/W R/W R/W PCI0[7:0] R/W Initial value : 00H Configure Pin Change Interrupt of P0 port 0 Disable 1 Enable PCI7 (P7 Pin Change Interrupt Enable Register) : AFH 7 6 5 4 3 2 1 0 PCI77 PCI76 PCI75 PCI74 PCI73 PCI72 PCI71 PCI70 R/W R/W R/W R/W R/W R/W R/W PCI7[7:0] R/W Initial value : 00H Configure Pin Change Interrupt of P7port 0 Disable 1 Enable PSR0 (Port Selection Register 0) : 92H 7 6 5 4 3 2 1 0 PSR07 PSR06 PSR05 PSR04 PSR03 PSR02 PSR01 PSR00 R/W R/W R/W R/W R/W R/W R/W PSR0[7:0] R/W Initial value : 00H P20~P27 port selection register 0 Disable analog channel AN[7:0]. 1 Enable analog channel AN[7:0]. PSR1 (Port Selection Register 1) : 93H 7 6 5 4 3 2 1 0 - PSR16 PSR15 PSR14 PSR13 PSR12 PSR11 PSR10 - R/W R/W R/W R/W R/W R/W PSR1[6:0] PS030302-0212 R/W Initial value : 00H P30~P36 port selection register 0 Disable analog channel AN[14:8]. 1 Enable analog channel AN[14:8]. PRELIMINARY 41 Z51F6412 Product Specification 10. Interrupt Controller 10.1 Overview The Z51F6412 MCU supports up to 32 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. They can also have four levels of priority assigned to them. The non-maskable interrupt source is always enabled with a higher priority than any other interrupt source, and is not controllable by software. The interrupt controller has following features: - receive the request from 32 interrupt source - 8 group priority - 4 priority levels - Multi Interrupt possibility - If the requests of different priority levels are received simultaneously, the request of higher priority level is serviced - Each interrupt source can control by EA bit and each IEx bit - Interrupt latency: 5~8 machine cycles in single interrupt system The non-maskable interrupt is always enabled. The maskable interrupts are enabled through five pair of interrupt enable registers (IE, IE1, IE2, IE3, IE4, IE5). Bits of IE, IE1, IE2, IE3, IE4, IE5 register each individually enable/disable a particular interrupt source. Overall control is provided by bit 7 of IE (EA). When EA is set to ‘0’, all interrupts are disabled: when EA is set to ‘1’, interrupts are individually enabled or disabled through the other bits of the interrupt enable registers. The Z51F6412 MCU supports a four-level priority scheme. Each maskable interrupt is individually assigned to one of four priority levels by writing to IP or IP1. Interrupt default mode is level-trigger basically but if needed, it is able to change edge-trigger mode. Table 10-1 shows the Interrupt Group Priority Level that is available for sharing interrupt priority. Priority sets two bit which is to IP and IP1 register about group. Interrupt service routine services higher priority. If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If the request of same or lower priority level is received, that request is not serviced. Table 10-1 Interrupt Group Priority Level Interrupt Group Highest 0 (Bit0) Interrupt0 Interrupt8 Interrupt16 Interrupt24 1 (Bit1) Interrupt1 Interrupt9 Interrupt17 Interrupt25 2 (Bit2) Interrupt2 Interrupt10 Interrupt18 Interrupt26 3 (Bit3) Interrupt3 Interrupt11 Interrupt19 Interrupt27 4 (Bit4) Interrupt4 Interrupt12 Interrupt20 Interrupt28 5 (Bit5) Interrupt5 Interrupt13 Interrupt21 Interrupt29 6 (Bit6) Interrupt6 Interrupt14 Interrupt22 Interrupt30 7 (Bit7) Interrupt7 Interrupt15 Interrupt23 Interrupt31 PS030302-0212 Lowest PRELIMINARY Highest Lowest 42 Z51F6412 Product Specification 10.2 External Interrupt The external interrupt on INT0, INT1, INT2, INT3, INT4, INT5, INT6 and INT7 pins receive various interrupt request depending on the edge selection register EIEDGE (External Interrupt Edge register) and EIPOLA (External Interrupt Polarity register) as shown in Figure 10-1. Also each external interrupt source has control setting bits. The EIFLAG (External interrupt flag register) register provides the status of external interrupts. INT0 Pin FLAG0 INT0 Interrupt FLAG1 INT1 Interrupt FLAG6 INT30 Interrupt FLAG7 INT31 Interrupt 2 INT1 Pin 2 INT6 Pin 2 INT7 Pin 2 EIEDGE, EIPOLA [0xA5]External Interrupt Edge Register [0xA6]External Interrupt Polarity Register Figure 10-1 External Interrupt Description PS030302-0212 PRELIMINARY 43 Z51F6412 Product Specification 10.3 Block Diagram IEDS0 IE[A8H] IP[B8H] IP1[F8H] 0 0 EIFLAG.0[A4H] INT0 FLAG0 INT1 FLAG1 0 0 1 Priority High EIFLAG.1[A4H] 1 2 1 1 EIFLAG.2[A4H] 2 FLAG2 INT2 3 2 2 EIFLAG.3[A4H] INT3 3 FLAG3 4 INT5 5 3 3 4 PCI (P0) 4 4 5 IE1[A9H] 5 5 USTAT0.5 [E5H] USART0 Rx RXC 6 USTAT0.6 [E5H] USART0 Tx TXC 7 6 8 7 6 SPISR.7 [D4H] SPI TCIR I2C IIF 9 8 8 10 9 RXC1 9 USTAT1.6 [FDH] USART1 Tx 7 8 USTAT1.5 [FDH] USART1 Rx 6 7 I2CMR.7 [DAH] 9 11 10 TXC1 10 10 11 11 Release Stop/Sleep 11 EA(IE.7[A8H]) IE5[ADH] EIFLAG 6[A4H] INT6 FLAG6 INT7 FLAG7 30 EIFLAG 7[A4H] 30 30 31 30 31 31 31 Priority Low Figure 10-2 Block Diagram of Interrupt PS030302-0212 PRELIMINARY 44 Z51F6412 Product Specification 10.4 Interrupt Vector Table The interrupt controller supports 32 interrupt sources as shown in the Table 10-2 below. When interrupt becomes service, long call instruction (LCALL) is executed in the vector address. Interrupt request 32 has a decided priority order. Table 10-2 Interrupt Vector Address Table Interrupt Source Symbol Hardware Reset External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 Pin Change Interrupt (P0) Pin Change Interrupt (P7) USART0 Rx USART0Tx SPI0 I2C USART1 Rx USART1 Tx T0 T1 T2 T3 T4 T5 ADC EEPROM WT WDT BIT SPI1 USART2 Rx USART2 Tx USART3 Rx USART3 Tx External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 RESETB INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT8 INT9 INT10 INT11 INT12 INT13 INT14 INT15 INT16 INT17 INT18 INT19 INT20 INT21 INT22 INT23 INT24 INT25 INT26 INT27 INT28 INT29 INT30 INT31 Interrupt Enable Bit 0 IE0.0 IE0.1 IE0.2 IE0.3 IE0.4 IE0.5 IE1.0 IE1.1 IE1.2 IE1.3 IE1.4 IE1.5 IE2.0 IE2.1 IE2.2 IE2.3 IE2.4 IE2.5 IE3.0 IE3.1 IE3.2 IE3.3 IE3.4 IE3.5 IE4.0 IE4.1 IE4.2 IE4.3 IE4.4 IE4.5 IE5.0 IE5.1 Priority Mask Vector Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Non-Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable 0000H 0003H 000BH 0013H 001BH 0023H 002BH 0033H 003BH 0043H 004BH 0053H 005BH 0063H 006BH 0073H 007BH 0083H 008BH 0093H 009BH 00A3H 00ABH 00B3H 00BBH 00C3H 00CBH 00D3H 00DBH 00E3H 00EBH 00F3H 00FBH For maskable interrupt execution, first EA bit must set ‘1’ and specific interrupt source must set ‘1’ by writing a ‘1’ to associated bit in the IEx. If interrupt request is received, specific interrupt request flag set ‘1’. And it remains ‘1’ until CPU accepts interrupt. After that, interrupt request flag will be cleared automatically. PS030302-0212 PRELIMINARY 45 Z51F6412 Product Specification 10.5 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the PC stack. For the interrupt service routine, the interrupt controller gives the address of LJMP instruction to CPU. After finishing the current instruction, at the next instruction to go interrupt service routine needs 5~8 machine cycle and the interrupt service task is terminated upon execution of an interrupt return instruction [RETI]. After generating interrupt, to go to interrupt service routine, the following process is progressed 1 IE.EA Flag  1 IEx.y  1 2 Program Counter low Byte SP  SP + 1 M(SP)  (PCL) Saves PC value in order to continue process again after executing ISR 3 Program Counter high Byte SP  SP + 1 M(SP)  (PCH) 4 Interrupt Vector Address occurrence (Interrupt Vector Address) 5 ISR(Interrupt Service Routine) move, execute 6 Return from ISR RETI 7 Program Counter high Byte recovery (PCL)  (SP+1) 8 Program Counter low Byte recovery (PCL)  (SP-1) 9 Main Program execution Figure 10-3 Interrupt Vector Address Table PS030302-0212 PRELIMINARY 46 Z51F6412 Product Specification 10.6 Effective Timing after Controlling Interrupt bit EA & INTnE set Next Instruction Setting both EA bit and individual interrupt enable bit INTnE makes the pending interrupt active after executing the next instruction. Next Instruction Figure 10-4 Effective time of interrupt request after setting IEx registers PS030302-0212 PRELIMINARY 47 Z51F6412 Product Specification 10.7 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time simultaneously, an interrupt polling sequence determines by hardware which request is serviced. However, multiple processing through software for special features is possible. Main Program Service INT1 ISR INT0 ISR Enable INT0 Disable others EA Occur INT1 Interrupt Occur INT0 Interrupt Enable INT0 Enable others RETI RETI Figure 10-5 Execution of Multi Interrupt Following example is shown to service INT0 routine during INT1 routine in Figure 10-5. In this example, INT0 interrupt priority is higher than INT1 interrupt priority. If some interrupt is lower than INT1 priority, it can’t service its interrupt routine. Example) Software Multi Interrupt: INT1: MOV IE, #01H ; Enable INT0 only MOV IE1, #00H ; Disable others SETB EA ; Enable global interrupt (necessary for multi interrupt) MOV IE, #03FH ; Enable all Interrupts MOV IE1, #03FH : RETI PS030302-0212 PRELIMINARY 48 Z51F6412 Product Specification 10.8 Interrupt Enable Accept Timing Max. 4 Machine Cycle 4 Machine Cycle System Clock Interrupt goes Active Interrupt Latched Interrupt Processing : LCALL & LJMP Interrupt Routine Figure 10-6 Interrupt Response Timing Diagram 10.9 Interrupt Service Routine Address Basic Interval Timer Vector Table Address Basic Interval Timer Service Routine Address 00B3H 01H 0125H 0EH 00B4H 25H 0126H 2EH Figure 10-7 Correspondence between vector Table address and the entry address of ISP 10.10 Saving/Restore General-Purpose Registers INTxx : PUSH PUSH PUSH PUSH PUSH · · PSW DPL DPH B ACC Main Task Interrupt Service Task Saving Register Interrupt_Processing: ∙ ∙ POP POP POP POP POP RETI Restoring Register ACC B DPH DPL PSW Figure 10-8 Saving/Restore Process Diagram & Sample Source PS030302-0212 PRELIMINARY 49 Z51F6412 Product Specification 10.11 Interrupt Timing Interrupt sampled here CLP2 CLP1 CLP2 C1P1 C1P2 C2P1 C2P2 SCLK INT_SRC INTR_ACK LAST_CYC INTR_LCALL 8-Bit interrupt Vector INT_VEC {8’h00, INT_VEC} PROGA Figure 10-9 Timing chart of Interrupt Acceptance and Interrupt Return Instruction Interrupt source sampled at last cycle of the command. When sampling interrupt source, it is decided to low 8-bit of interrupt vector. M8051W core makes interrupt acknowledge at first cycle of command, executes long call to jump interrupt routine as INT_VEC. Note) command cycle C?P?: L=Last cycle, 1=1st cycle or 1st phase, 2=2nd cycle or 2nd phase PS030302-0212 PRELIMINARY 50 Z51F6412 Product Specification 10.12 Interrupt Register Overview 10.12.1 Interrupt Enable Register (IE, IE1, IE2, IE3, IE4, IE5) Interrupt enable register consists of Global interrupt control bit (EA) and peripheral interrupt control bits. Totally 32 peripheral are able to control interrupt. 10.12.2 Interrupt Priority Register (IP, IP1) The 32 interrupt divides 8 groups which have each 4 interrupt sources. A group can decide 4 levels interrupt priority using interrupt priority register. Level 3 is the high priority, while level 0 is the low priority. Initially, IP, IP1 reset value is ‘0’. At that initialization, low interrupt number has a higher priority than high interrupt number. If decided the priority, low interrupt number has a higher priority than high interrupt number in that group. 10.12.3 External Interrupt Flag Register (EIFLAG) The external interrupt flag register is set to ‘1’ when the external interrupt generating condition is satisfied. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a ‘0’ to it. 10.12.4 External Interrupt Edge Register (EIEDGE) The External interrupt edge register determines which type of edge or level sensitive interrupt. Initially, default value is level. For level, write ‘0’ to related bit. For edge, write ‘1’ to related bit. 10.12.5 External Interrupt Polarity Register (EIPOLA) According to EIEDGE register, the external interrupt polarity (EIPOLA) register has a different meaning. If EIEDGE is level type, EIPOLA is able to have Low/High level value. If EIEGDE is edge type, EIPOLA is able to have rising/falling edge value. 10.12.6 External Interrupt Both Edge Enable Register (EIBOTH) When the external interrupt both edge enable register is written to ‘1’, the corresponding external pin interrupt is enabled by both edges. Initially, default value is disabled. 10.12.7 External Interrupt Enable Register (EIENAB) When the external interrupt enable register is written to ‘1’, the corresponding external pin interrupt is enabled. The EIEDGE and EIPOLA register defines whether the external interrupt is activated on rising or falling edge or level sensed. PS030302-0212 PRELIMINARY 51 Z51F6412 Product Specification 10.12.8 Register Map Table 10-3 Register Map Name Address Dir Default Description IE A8H R/W 00H Interrupt Enable Register IE1 A9H R/W 00H Interrupt Enable Register 1 IE2 AAH R/W 00H Interrupt Enable Register 2 IE3 ABH R/W 00H Interrupt Enable Register 3 IE4 ACH R/W 00H Interrupt Enable Register 4 IE5 ADH R/W 00H Interrupt Enable Register 5 IP B8H R/W 00H Interrupt Priority Register IP1 F8H R/W 00H Interrupt Priority Register 1 EIFLAG A4H R/W 00H External Interrupt Flag Register EIEDGE A5H R/W 00H External Interrupt Edge Register EIPOLA A6H R/W 00H External Interrupt Polarity Register EIBOTH A7H R/W 00H External Interrupt Both Edge Register EIENAB A3H R/W 00H External Interrupt Enable Register 10.13 Interrupt Register Description The Interrupt Register is used for controlling interrupt functions. Also it has External interrupt control registers. The interrupt register consists of Interrupt Enable Register (IE), Interrupt Enable Register 1 (IE1), Interrupt Enable Register 2 (IE2), Interrupt Enable Register 3 (IE3), Interrupt Enable Register 4 (IE4) and Interrupt Enable Register 5 (IE5). For external interrupt, it consists of External Interrupt Flag Register (EIFLAG), External Interrupt Edge Register (EIEDGE), External Interrupt Polarity Register (EIPOLA) and External Interrupt Enable Register (EIENAB). 10.13.1 Register description for Interrupt IE (Interrupt Enable Register) : A8H 7 6 5 4 3 2 1 0 EA - INT5E INT4E INT3E INT2E INT1E INT0E R/W - R/W R/W R/W R/W R/W EA INT5E INT4E INT3E INT2E PS030302-0212 R/W Initial value : 00H Enable or disable all interrupt bits 0 All Interrupt disable 1 All Interrupt enable Enable or disable Pin Change Interrupt 1 (Port 7) 0 Disable 1 Enable Enable or disable Pin Change Interrupt 0 (Port 0) 0 Disable 1 Enable Enable or disable External Interrupt 3 0 Disable 1 Enable Enable or disable External Interrupt 2 PRELIMINARY 52 Z51F6412 Product Specification INT1E INT0E 0 Disable 1 Enable Enable or disable External Interrupt 1 0 Disable 1 Enable Enable or disable External Interrupt 0 0 Disable 1 Enable IE1 (Interrupt Enable Register 1) : A9H 7 6 5 4 3 2 1 0 - - INT11E INT10E INT9E INT8E INT7E INT6E - - R/W R/W R/W R/W R/W INT11E INT10E INT9E INT8E INT7E INT6E R/W Initial value : 00H Enable or disable USART1 Tx Interrupt 0 Disable 1 Enable Enable or disable USART1 Rx Interrupt 0 Disable 1 Enable Enable or disable I2C Interrupt 0 Disable 1 Enable Enable or disable SPI0 Interrupt 0 Disable 1 Enable Enable or disable USART0 Tx Interrupt 0 Disable 1 Enable Enable or disable USART0 Rx Interrupt 0 Disable 1 Enable IE2 (Interrupt Enable Register 2) : AAH 7 6 5 4 3 2 1 0 - - INT17E INT16E INT15E INT14E INT13E INT12E - - R/W R/W R/W R/W R/W INT17E INT16E INT15E PS030302-0212 R/W Initial value : 00H Enable or disable Timer 5 Interrupt 0 Disable 1 Enable Enable or disable Timer 4 Interrupt 0 Disable 1 Enable Enable or disable Timer 3 Interrupt 0 Disable 1 Enable PRELIMINARY 53 Z51F6412 Product Specification INT14E INT13E INT12E Enable or disable Timer 2 Interrupt 0 Disable 1 Enable Enable or disable Timer 1 Interrupt 0 Disable 1 Enable Enable or disable Timer 0 Interrupt 0 Disable 1 Enable IE3 (Interrupt Enable Register 3) : ABH 7 6 5 4 3 2 1 0 - - INT23E INT22E INT21E INT20E INT19E INT18E R R R/W R/W R/W R/W R/W INT23E INT22E INT21E INT20E INT19E INT18E R/W Initial value : 00H Enable or disable SPI1 Interrupt 0 Disable 1 Enable Enable or disable BIT Interrupt 0 Disable 1 Enable Enable or disable WDT Interrupt 0 Disable 1 Enable Enable or disable WT Interrupt 0 Disable 1 Enable Enable or disable EEPROM Interrupt 0 Disable 1 Enable Enable or disable ADC Interrupt 0 Disable 1 Enable IE4 (Interrupt Enable Register 4) : ACH 7 6 5 4 3 2 1 0 - - INT29E INT28E INT27E INT26E INT25E INT24E R R R/W R/W R/W R/W R/W INT29E INT28E INT27E Enable or disable External Interrupt 5 0 Disable 1 Enable Enable or disable External Interrupt 4 0 Disable 1 Enable Enable or disable USART3 Tx Interrupt 0 PS030302-0212 R/W Initial value : 00H Disable PRELIMINARY 54 Z51F6412 Product Specification 1 INT26E INT25E INT24E Enable Enable or disable USART3 Rx Interrupt 0 Disable 1 Enable Enable or disable USART2 Tx Interrupt 0 Disable 1 Enable Enable or disable USART2 Rx Interrupt 0 Disable 1 Enable IE5 (Interrupt Enable Register 5) : ADH 7 6 5 4 3 2 1 0 - - INT35E INT34E INT33E INT32E INT31E INT30E R R R/W R/W R/W R/W R/W INT35E INT34E INT33E INT32E INT31E INT30E R/W Initial value : 00H Reserved 0 Disable 1 Enable Reserved 0 Disable 1 Enable Reserved 0 Disable 1 Enable Reserved 0 Disable 1 Enable Enable or disable External Interrupt 7 0 Disable 1 Enable Enable or disable External Interrupt 6 0 Disable 1 enable IP (Interrupt Priority Register) : B8H 7 6 5 4 3 2 1 IP7 IP6 IP5 IP4 IP3 IP2 IP1 R/W R/W R/W R/W R/W R/W R/W 0 IP0 R/W Initial value : 00H IP1 (Interrupt Priority Register 1) : F8H 7 6 5 4 3 2 1 0 IP17 IP16 IP15 IP14 IP13 IP12 IP11 IP10 R/W R/W R/W R/W R/W R/W R/W IP[7:0], PS030302-0212 R/W Initial value : 00H Select Interrupt Group Priority PRELIMINARY 55 Z51F6412 Product Specification IP1[7:0] IP1x IPx Description 0 0 level 0 (lowest) 0 1 level 1 1 0 level 2 1 1 level 3 (highest) EIFLAG (External Interrupt Flag Register) : A4H 7 6 5 4 3 2 1 0 FLAG7 FLAG6 FLAG5 FLAG4 FLAG3 FLAG2 FLAG1 FLAG0 R/W R/W R/W R/W R/W R/W R/W FLAG[7:0] R/W Initial value : 00H If External Interrupt is occurred, the flag becomes ‘1’. The flag can be cleared by writing a ‘0’ to bit 0 External Interrupt not occurred 1 External Interrupt occurred EIEDGE (External Interrupt Edge Register) : A5H 7 6 5 4 3 2 1 0 EDGE7 EDGE6 EDGE5 EDGE4 EDGE3 EDGE2 EDGE1 EDGE0 R/W R/W R/W R/W R/W R/W R/W EDGE[7:0] R/W Initial value : 00H Determines which type of edge or level sensitive interrupt may occ ur. 0 Level (default) 1 Edge EIPOLA (External Interrupt Polarity Register) : A6H 7 6 5 4 3 2 1 0 POLA7 POLA6 POLA5 POLA4 POLA3 POLA2 POLA1 POLA0 R/W R/W R/W R/W R/W R/W R/W POLA[7:0] R/W Initial value : 00H According to EIEDGE, External interrupt polarity register has a different means. If EIEDGE is level type, external interrupt polarity is able to have Low/High level value. If EIEGDE is edge type, external interrupt polarity is able to have rising/ falling edge value. Level case: 0 When High level, Interrupt occurred (default) 1 When Low level, Interrupt occurred 0 When Rising edge, Interrupt occurred (default) 1 When Falling edge, Interrupt occurred Edge case: EIBOTH (External Interrupt Both Edge Enable Register) : A7H 7 6 5 4 3 2 1 0 BOTH7 BOTH 6 BOTH 5 BOTH 4 BOTH 3 BOTH 2 BOTH 1 BOTH 0 R/W R/W R/W R/W R/W R/W R/W PS030302-0212 PRELIMINARY R/W Initial value : 00H 56 Z51F6412 Product Specification BOTH[7:0] Determines which type of interrupt may occur, EIBOTH or EIEDGE+EIPOLA. if EIBOTH is enable, EIEDGE and EIPOLA r egister value don’t matter 0 Disable (default) 1 Enable EIENAB (External Interrupt Enable Register) : A3H 7 6 5 4 3 2 1 0 ENAB7 ENAB6 ENAB5 ENAB4 ENAB3 ENAB2 ENAB1 ENAB0 R/W R/W R/W R/W R/W R/W R/W ENAB[7:0] PS030302-0212 R/W Initial value : 00H Control External Interrupt 0 Disable (default) 1 Enable PRELIMINARY 57 Z51F6412 Product Specification 11. Peripheral Hardware 11.1 Clock Generator 11.1.1 Overview As shown in Figure 11-1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains main-frequency clock oscillator. The system clock operation can be easily obtained by attaching a crystal between the XIN and XOUT pin, respectively. The system clock can also be obtained from the external oscillator. In this case, it is necessary to put the external clock signal into the XIN pin and open the XOUT pin. The default system clock is INT-RC Oscillator and the default division rate is two. In order to stabilize system internally, use 1MHz RING oscillator for BIT, WDT and ports de-bounce. - Calibrated Internal RC Oscillator (16 MHz / ±2%) . INT-RC OSC/1 (16 MHz) . INT-RC OSC/2 (8 MHz, Default system clock) . INT-RC OSC/4 (4 MHz) . INT-RC OSC/8 (2 MHz) - Crystal Oscillator (1~10 MHz) - Sub-Clock Crystal Oscillator (32.768 KHz) - PLL output (14.75 MHz) 11.1.2 Block Diagram PDOWN XIN XOUT SUBXIN SUBXOUT Main OSC SUB OSC fXIN PLL fINTRC WT DCLK fSUB / fPLL 1/1 1/2 DIV 1/4 INT-RC 1/8 OSC fRING System ClockGen. Clock Change (16MHz) System Clock Masking Control PDOWN WONS RING-OSC (1MHz) SCLK (Core, System, Peripherals) DIV/8 BIT Overflow BIT WDT Figure 11-1 Clock Generator Block Diagram PS030302-0212 PRELIMINARY 58 Z51F6412 Product Specification 11.1.3 Register Map Table 11-1 Register Map Name Address Dir Default Description SCCR 8AH R/W 24H System and Clock Control Register PLLCR D9H R/W 00H PLL Control Register 11.1.4 Clock Generator Register description The Clock Generation Register uses clock control for system operation. The clock generation consists of System and Clock register. 11.1.5 Register description for Clock Generator SCCR (System and Clock Control Register) : 8AH 7 6 5 4 3 2 1 0 STOP1 DIV1 DIV0 CBYS ISTOP XSTOP CS1 CS0 R/W R/W R/W R/W R/W R/W R/W STOP1 DIV[1:0] CBYS ISTOP XSTOP PS030302-0212 R/W Initial value : 24H Control the STOP Mode. Note) when PCON=0x03, It is applied. But when PCON=0x01, don’t set this bit. 0 STOP2 Mode (at PCON=0x03) (default) 1 STOP1 Mode (at PCON=0x03) When using fINTRC as system clock, determine division rate. Note) when using fINTRC as system clock, only division rate come into effect. Note) To change by software, CBYS set to ‘1’ DIV1 DIV0 description 0 0 fINTRC/1 (16MHz) 0 1 fINTRC/2 (8MHz) (default) 1 0 fINTRC/4 (4MHz) 1 1 fINTRC/8 (2MHz) Control the scheme of clock change. If this bit set to ‘0’, clock change is controlled by hardware. But if this set to ‘1’, clock change is controlled by software. Ex) when setting CS[1:0], if CBYS bit set to ‘0’, it is not changed right now, CPU goes to STOP mode and then when wake-up, it applies to clock change. Note) when clear this bit, keep other bits in SCCR. 0 Clock changed by hardware during stop mode (default) 1 Clock changed by software Control the operation of INT-RC Oscillation Note) when CBYS=’1’, It is applied 0 RC-Oscillation enable (default) 1 RC-Oscillation disable Control the operation of X-Tal Oscillation Note1) when CBYS=’1’, It is applied Note2) if XINENA bit in FUSE_CONF to ‘0’, XSTOP is fixed to ‘1’ 0 X-Tal Oscillation enable 1 X-Tal Oscillation disable (default) PRELIMINARY 59 Z51F6412 Product Specification CS[1:0] Determine System Clock Note) by CBYS bit, reflection point is decided CS1 CS0 Description 0 0 fINTRC INTRC (16 MHz) 0 1 fXIN Main Clock (1~10 MHz) 1 0 fSUB / fPLL (32.768 KHz, 14.75MHz) 1 1 fRING (125 KHz) PLLCR (Phase Locked Loop Control Register) : D9H 7 6 5 PLLSTAT PLLCKS VDConSUB R R/W R/W PLLSTAT PLLCKS VDConSUB PLLFB[1:0] PLLPD[1:0] PLLEN 4 3 2 R/W R/W PLLFB R/W 1 0 PLLPD PLLEN R/W R/W Initial value : 00H PLL Status flag (read only bit) 0 PLL output is Fvcoin (32.768KHz bypass) 1 PLL output is Fpll PLL output clock selection control PLLEN should be set “1” to use bypass control. PLL VCO would not stop in the case of PLLCKS is “0” (32KHz). In addition, this bit automatically set by interrupt event on sub-active or power down. 0 PLL output is Fvcoin (32.768KHz bypass, default) 1 PLL output is Fpll Normal Power Selection for PLLCKS control 0 Limited VDC power when PLLCKS is “0” (32.768KHz) - Limited VDC consumes about 0.1mA to drive 1mA (default) - In this mode, user must care about power consumption 1 Normal VDC power when PLLCKS is “0” (32.768KHz) - Normal VDC consumes about 1mA to drive about 10mA PLL Feedback Divider control PLLFB1 PLLFB0 description 0 0 FBdiv = 674 (Not valid) 0 1 FBdiv = 562 (Not valid) 1 0 FBdiv = 450 1 1 FBdiv = 338 PLL Post Divider Control PLLPD1 PLLPD0 description 0 0 M=1 0 1 M=2 1 0 M=4 1 1 M=8 PLL Enable control 0 PLL disable (2 SUB-OSC clock need for disable, default) 1 PLL enable Fvco = Fvcoin * FBdiv Fpll = Fvco / M PS030302-0212 PRELIMINARY 60 Z51F6412 Product Specification Fvco = (32.768 KHz * 450) = 14.7456 MHz Fvco = (32.768 KHz * 338) = 11.075584 MHz 11.1.6 Power control for 32.768KHz Clock operation The Z51F6412 MCU features two different way to use 32.768KHz operation. First, user can select 32.768KHz clock on PLL disable as a low power operation(Sub-active mode, CS[1:0] = 0x2 of SCCR, PLLCKS = ”0” and PLLEN = “0” of PLLCR). In this mode, user also has to care about power consumption of whole chip. Because, to achieve lower power consumption in subactive mode, The Z51F6412 MCU has a smaller SUB-ACTIVE VDC(voltage Down Converter) which is automatically enable in sub-active mode and has only 1mA current capability while main VDC(for normal operation) is off. Second, if user wanted to use 32.768KHz on PLL enable(CS[1:0] = 0x2 of SCCR, PLLCKS = “0” and PLLEN = “1” of PLLCR), in this case PLL VCO block would not stop so need more power than the first case. In this case, user can select VDC mode with VDConSUB bit of PLLCR. If VDConSUB = “0”, then main 10mA VDC is off and only SUB_ACTIVE VDC of 1mA is available. If user set VDConSUB = “1”, main VDC, which has 10mA of current drive capability for 1.8V output, will work for 32.768KHz and main VDC itself will consume about 1mA current to operate while SUB_ACTIVE VDC consume 0.1mA. Table 11-2 VDC current consumption PLLEN@PLLCR VDConSUB@PLLCR MAIN SUB VDC current (PLLCKS = 0) (PLLCKS = 0) VDC VDC capability VDC current consumption 1 ON OFF 20mA@1.8V 1mA 0 OFF ON 1mA@1.8V 0.1mA X (don’t care) OFF ON 1mA@1.8V 0.1mA 1 0 PS030302-0212 PRELIMINARY 61 Z51F6412 Product Specification 11.2 BIT 11.2.1 Overview The Z51F6412 MCU features one 8-bit Basic Interval Timer that is free-run and can’t stop. Block diagram is shown in Figure 11-2. In addition, the Basic Interval Timer generates the time base for watchdog timer counting. It also provides a Basic interval timer interrupt (BITF). The Z51F6412 MCU features these Basic Interval Timer (BIT) features: - During Power On, BIT gives a stable clock generation time - On exiting Stop mode, BIT gives a stable clock generation time - As clock function, time interrupt occurrence 11.2.2 Block Diagram RING-OSC (1MHz) ÷8 BIT Interrupt Generator ÷ 32 BIT_CLK 1MHz ÷ 8 ÷ 32 BIT Interrupt Flag BITR (8-bit COUNT) 3.91KHz BIT Out Generator BIT_OUT (WDT clock source) BCK[2:0] = 001b BIT_CLK BITR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BIT_Int_Flag BIT_Out Figure 11-2 BIT Block Diagram 11.2.3 Register Map Table 11-3 Register Map Name Address Dir Default Description BCCR 8BH R/W 05H BIT Clock Control Register BITR 8CH R 00H Basic Interval Timer Register PS030302-0212 PRELIMINARY 62 Z51F6412 Product Specification 11.2.4 Bit Interval Timer Register description The Bit Interval Timer Register consists of BIT Clock control register (BCCR) and Basic Interval Timer register (BITR). If BCLR bit set to ‘1’, BITR becomes ‘0’ and then counts up. After 1 machine cycle, BCLR bit is cleared as ‘0’ automatically. 11.2.5 Register description for Bit Interval Timer BCCR (BIT Clock Control Register) : 8BH 7 6 5 BITF - - R/W R R BITF 4 3 2 1 0 BCLR BCK2 BCK1 BCK0 R/W R/W R/W R R/W Initial value : 05H When BIT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit. BCLR BCK[2:0] 0 no generation 1 generation If BCLK Bit is written to ‘1’, BIT Counter is cleared as ‘0’ 0 Free Running 1 Clear Counter Select BIT overflow period (BIT Clock ≒3.9 KHz) BCK2 BCK1 BCK0 0 0 0 0.512msec (BIT Clock * 2) 0 0 1 1.024msec 0 1 0 2.048msec 0 1 1 4.096msec 1 0 0 8.192msec 1 0 1 16.384msec (default) 1 1 0 32.768msec 1 1 1 65.536msec BITR (Basic Interval Timer Register) : 8CH 7 6 5 4 3 2 1 0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 R R R R R R R BIT[7:0] PS030302-0212 R Initial value : 00H BIT Counter PRELIMINARY 63 Z51F6412 Product Specification 11.3 WDT 11.3.1 Overview The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or an interrupt request. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. It is possible to use free running 8-bit timer mode (WDTRSON=’0’) or watch dog timer mode (WDTRSON=’1’) as setting WDTMR[6] bit. If writing WDTMR[5] to ‘1’, WDT counter value is cleared and counts up. After 1 machine cycle, this bit has ‘0’ automatically. The watchdog timer consists of 8bit binary counter and the watchdog timer data register. When the value of 8-bit binary counter is equal to the 8 bits of WDTR, the interrupt request flag is generated. This can be used as Watchdog timer interrupt or reset the CPU in accordance with the bit WDTRSON. The clock source of Watch Dog Timer is BIT overflow output. The interval of watchdog timer interrupt is decided by BIT overflow period and WDTR set value. The equation is as below WDT Interrupt Interval = (BIT Interrupt Interval) X (WDTR Value+1) 11.3.2 Block Diagram Watchdog Timer Counter Register BIT Overflow WDTEN WDTCR Clear To Reset Circuit [8EH] WDTIFR Watchdog Timer Register Clear INT_ACK WDTIF WDTR [8EH] WDTCL WDTRSON WDTMR Figure 11-3 WDT Block Diagram 11.3.3 Register Map Table 11-4 Register Map Name Address Dir Default Description WDTR 8EH W FFH Watch Dog Timer Register WDTCR 8EH R 00H Watch Dog Timer Counter Register WDTMR 8DH R/W 00H Watch Dog Timer Mode Register PS030302-0212 PRELIMINARY 64 Z51F6412 Product Specification 11.3.4 Watch Dog Timer Register description The Watch dog timer (WDT) Register consists of Watch Dog Timer Register (WDTR), Watch Dog Timer Counter Register (WDTCR) and Watch Dog Timer Mode Register (WDTMR). 11.3.5 Register description for Watch Dog Timer WDTR (Watch Dog Timer Register: Write Case) : 8EH 7 6 5 4 3 2 1 0 WDTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0 W W W W W W W W Initial value : FFH WDTR[7:0] Set a period WDT Interrupt Interval=(BIT Interrupt Interval) x(WDTR Value+1) Note) To guarantee proper operation, the data should be greater than 01H. WDTCR (Watch Dog Timer Counter Register: Read Case) : 8EH 7 6 5 4 3 2 1 0 WDTCR7 WDTCR6 WDTCR5 WDTCR4 WDTCR3 WDTCR2 WDTCR1 WDTCR0 R R R R R R R WDTCR[7:0] R Initial value : 00H WDT Counter WDTMR (Watch Dog Timer Mode Register) : 8DH 7 6 5 4 3 2 1 0 WDTEN WDTRSON WDTCL - - - - WDTIFR R/W R/W R/W - - - - WDTEN WDTRSON WDTCL WDTIFR PS030302-0212 R/W Initial value : 00H Control WDT operation 0 disable 1 enable Control WDT Reset operation 0 Free Running 8-bit timer 1 Watch Dog Timer Reset ON Clear WDT Counter 0 Free Run 1 Clear WDT Counter (auto clear after 1 Cycle) When WDT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 WDT Interrupt no generation 1 WDT Interrupt generation PRELIMINARY 65 Z51F6412 Product Specification 11.3.6 WDT Interrupt Timing Waveform Source Clock BIT Overflow WDTCR[7:0] 0 1 2 3 0 1 2 3 0 1 2 Counter Clear WDTR[7:0] WDTIF Interrupt n 3 WDTCL Occur WDTR  0000_0011b Match Detect WDTRESETB RESET Figure 11-4 WDT Interrupt Timing Waveform PS030302-0212 PRELIMINARY 66 Z51F6412 Product Specification 11.4 WT 11.4.1 Overview The watch timer has the function for RTC (Real Time Clock) operation. It is generally used for RTC design. The internal structure of the watch timer consists of the clock source select circuit, timer counter circuit, output select circuit and watch timer mode register. To operate the watch timer, determine the input clock source, output interval and set WTEN to ‘1’ in watch timer mode register (WTMR). It is able to execute simultaneously or individually. To stop or reset WT, clear the WTEN bit in WTMR register. Even if CPU is STOP mode, sub clock is able to be alive so WT can continue the operation. The watch timer counter circuits may be composed of 21-bit counter which is low 14-bit with binary counter and high 7-bit with auto reload counter in order to raise resolution. In WTR, it can control WT clear and set Interval value at write time, and it can read 7-bit WT counter value at read time. 11.4.2 Block Diagram fSUB (32.768kHz) P r e s c a l e r fx ÷64 fWCK MUX ÷128 fWCK / 214 14Bit Binary Counter Timer Counter (7bit auto reload counter) fWCK / 214 x (7bit WTR Value +1) ÷256 7 fWCK/214 fWCK/213 MUX fWCK/211 WTMR WTEN - - WTIFR WTIN1 WTIFR WTIF Clear WTIN0 WTCK1 WTCK0 2 WTR WTR Write WTCR WTR Read WTCL - WTR6 WTR5 WTR4 WTR2 WTR2 WTR1 INT_ACK WTR0 WTCR6 WTCR5 WTCR4 WTCR2 WTCR2 WTCR1 WTCR0 Figure 11-5 Watch Timer Block Diagram 11.4.3 Register Map Table 11-5 Register Map Name WTMR Address 9DH Dir Default R/W 00H Description Watch Timer Mode Register WTR 9EH W 7FH Watch Timer Register WTCR 9EH R 00H Watch Timer Counter Register PS030302-0212 PRELIMINARY 67 Z51F6412 Product Specification 11.4.4 Watch Timer Register description The watch timer register (WT) consists of Watch Timer Mode Register (WTMR), Watch Timer Counter Register (WTCR) and Watch Timer Register (WTR). As WTMR is 6-bit writable/readable register, WTMR can control the clock source (WTCK), interrupt interval (WTIN) and function enable/disable (WTEN). Also there is WT interrupt flag bit (WTIFR). 11.4.5 Register description for Watch Timer WTMR (Watch Timer Mode Register) : 9DH 7 6 5 4 3 2 1 0 WTEN - - WTIFR WTIN1 WTIN0 WTCK1 WTCK0 R/W - - R/W R/W R/W R/W WTEN WTIFR WTIN[1:0] WTCK[1:0] R/W Initial value : 00H Control Watch Timer 0 disable 1 enable When WT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 WT Interrupt no generation 1 WT Interrupt generation Determine interrupt interval WTIN1 WTIN0 description 0 0 fwck/2048 0 1 fwck/8192 1 0 fwck/16384 1 1 fwck/16384 x (7bit WT Value) Determine Source Clock WTCK1 WTCK0 description 0 0 fsub 0 1 fx/256 1 0 fx/128 1 1 fx/64 Remark: fx– Main system clock oscillation frequency fsub- Sub clock oscillation frequency fwck- selected Watch Timer clock PS030302-0212 PRELIMINARY 68 Z51F6412 Product Specification WTR (Watch Timer Register: Write Case) : 9EH 7 6 5 4 3 2 1 0 WTCL WTR6 WTR5 WTR4 WTR3 WTR2 WTR1 WTR0 W W W W W W W W Initial value : 7FH WTCL WTR[6:0] Clear WT Counter 0 Free Run 1 Clear WT Counter (auto clear after 1 Cycle) Set WT period WT Interrupt Interval=(fwck/2^14) x(7bit WT Value+1) Note) To guarantee proper operation, it is greater than 01H to write WTR. WTCR (Watch Timer Counter Register: Read Case) : 9EH 7 6 5 4 3 2 1 0 WTCR 6 WTCR 5 WTCR 4 WTCR 3 WTCR 2 WTCR 1 WTCR 0 R R R R R R - WTCR[6:0] PS030302-0212 R Initial value : 00H WT Counter PRELIMINARY 69 Z51F6412 Product Specification 11.5 Timer/PWM 11.5.1 8-bit Timer/Event Counter 0, 1 11.5.1.1 Overview Timer 0 and timer 1 can be used either two 8-bit timer/counter or one 16-bit timer/counter with combine them. Each 8-bit timer/event counter module has multiplexer, 8-bit timer data register, 8-bit counter register, mode register, input capture register, comparator. For PWM, it has PWM register (T1PPR, T1PDR, T1PWHR). It has seven operating modes: - 8 Bit Timer/Counter Mode - 8 Bit Capture Mode - 8 Bit Compare Output Mode - 16 Bit Timer/Counter Mode - 16 Bit Capture Mode - 16 Bit Compare Output Mode - PWM Mode Note> TxDR must be set to higher than 0x03 for guaranteeing operation. The timer/counter can be clocked by an internal or external clock source (external EC0). The clock source is selected by clock select logic which is controlled by the clock select (T0CK[2:0], T1CK[1:0]). - TIMER0 clock source : fX/2, 4, 16, 64, 256, 1024, 4096, EC0 - TIMER1 clock source : fX/1, 2, 16, T0CK In the capture mode, by INT0, INT1, the data is captured into Input Capture Register. The TIMER 0 outputs the compare result to T0 port in 8/16-bit mode. Also the timer 1 outputs the result T1 port in the timer mode and the PWM waveform to PWM3 in the PWM mode. Table 11-6 Operating Modes of Timer 16 Bit CAP0 CAP1 PWM1E T0CK[2:0] T1CK[1:0] T0/1_PE TIMER 0 Timer 1 0 0 0 0 XXX XX 00 8 Bit Timer 8 Bit Timer 0 0 1 0 111 XX 00 8 Bit Event Counter 8 Bit Capture 0 1 0 0 XXX XX 01 8 Bit Capture 8 Bit Compare Output 0 0 0 1 XXX XX 11 8 Bit Timer/Counter 10 Bit PWM 1 0 0 0 XXX 11 00 16 Bit Timer 1 0 0 0 111 11 00 16 Bit Event Counter 1 1 1 0 XXX 11 00 16 Bit Capture 1 0 0 0 XXX 11 01 16 Bit Compare Output PS030302-0212 PRELIMINARY 70 Z51F6412 Product Specification 11.5.1.2 8 Bit Timer/Counter Mode The 8-bit Timer/Counter Mode is selected by control registers as shown in Figure 11-6. T0CR T1CR T0EN T0PE CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST 1 X 0 X X X X X POL1 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST X 0 0 0 X X X X EC0 SCLK T0EN P r e s c a l e r ÷2 ÷64 ADDRESS : B4H INITIAL VALUE : 0000_0000B T0ST 8-bit Timer0 Counter ÷4 ÷16 ADDRESS : B2H INITIAL VALUE : 0000_0000B MUX T0(8-bit) ÷256 Clear [B3H] ÷1024 T0IF ÷4096 [B3H] 3 Comparator T0DR(8-bit) T0CK[2:0] F/F Timer0 Interrup t P52/T0 8-bit Timer2 Data Register T1CN T1ST 8-bit Timer1 Counter ÷1 ÷2 MUX T1(8-bit) ÷16 Clear [B6H] T1IF 2 T1CK[1:0] [B5H] Timer1 Interrupt Comparator T1DR(8-bit) F/F P53/T1 8-bit Timer1 Data Register Figure 11-6 Bit Timer/Event Counter2, 3 Block Diagram The two 8-bit timers have each counter and data register. The counter register is increased by internal or external clock input. The timer 0 can use the input clock with 2, 4, 8, 32, 128, 512, 2048 prescaler division rates (T0CK[2:0]). The timer 1 can use the input clock with 1, 2, 8 and timer 0 overflow clock (T1CK[1:0]). When the value of T0, 1value and the value of T0DR, T1DR are respectively identical in Timer 0, 1, the interrupt of timer P2, 3 occurs. The external clock (EC0) counts up the timer at the rising edge. If EC0 is selected from T0CK[2:0], EC0 port becomes input port. The timer 1 can’t use the external EC0 clock. PS030302-0212 PRELIMINARY 71 Z51F6412 Product Specification Match with T0DR/T1DR n T0DR/T1DR Value n-1 n-2 Count Pulse Period PCP 6 Up-count 5 4 3 2 1 0 Interrupt Period = PCP x (n+1) Timer 0, 1 (T0IF, T1IF) Interrupt Occur Interrupt TIME Occur Interrupt Occur Interrupt Figure 11-7 Timer/Event Counter0, 1 Example T0DR/T1DR Value Disable Enable Clear&Start STOP Up-count TIME Timer 0, 1 (T0IF, T1IF) Interrupt T0ST, T1ST Start&Stop Occur Interrupt Occur Interrupt T0ST,T1ST = 1 T0ST,T1ST = 1 T0ST,T1ST = 0 T0CN, T1CN Control count T0CN,T1CN = 1 T0CN,T1CN = 1 T0CN,T1CN = 0 Figure 11-8 Operation Example of Timer/Event Counter0, 1 PS030302-0212 PRELIMINARY 72 Z51F6412 Product Specification 11.5.1.3 16 Bit Timer/Counter Mode The timer register is being run with all 16bits. A 16-bit timer/counter register T0, T1 are incremented from 0003H to FFFFH until it matches T0DR, T1DR and then resets to 0000H. the match output generates the Timer 0 interrupt ( no timer 1 interrupt). The clock source is selected from T0CK[2:0] and T1CK[1:0] must set 11b and 16BIT bit must set to ‘1’. The timer 0 is LSB 8-bit, the timer 1 is MSB 8-bit. T0DR must not be 0x00(0x01~0xFF). The 16-bit mode setting is shown as Figure 11-19. T0CR T1CR T0EN T0PE CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST 1 X 0 X X X X X POL1 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST X 1 0 0 1 1 X X EC0 SCLK T0EN P r e s c a l e r ÷2 ÷64 ADDRESS : B4H INITIAL VALUE : 0000_0000B T0ST 16-bit Counter ÷4 ÷16 ADDRESS : B2H INITIAL VALUE : 0000_0000B T1 (8-bit) MUX ÷256 T0 (8-bit) [B3H] [B6H] ÷1024 Clear T0IF ÷4096 [B5H] 3 T0CK[2:0] T1DR (8-bit) Comparator T0DR (8-bit) [B3H] F/F Timer0 Interrup t P52/T0 PIN 16-bit Data Register Figure 11-9 16 Bit Timer/Event Counter0, 1 Block Diagram 11.5.1.4 8-Bit Capture Mode The timer 0, 1 capture mode is set by CAP0, CAP1 as ‘1’. The clock source can use the internal/external clock. Basically, it has the same function of the 8-bit timer/counter mode and the interrupt occurs at T0, 1 and T0DR, T1DR matching time, respectively. The capture result is loaded into CDR0, CDR1. The T0, T1 value is automatically cleared by hardware and restarts counter. This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer. As the EIEDGE and EIPOLA register setting, the external interrupt INT0, INT1 function is chosen. The CDR0, T0 and T0DR are in same address. In the capture mode, reading operation is read the CDR0, not T0DR because path is opened to the CDR0. The CDR1 has the same function. PS030302-0212 PRELIMINARY 73 Z51F6412 Product Specification T0CR T1CR T0EN T0PE CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST 1 X 1 X X X X X POL1 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST X 0 0 1 X X X X EC0 fx T0CN P r e s c a l e r ADDRESS : B2H INITIAL VALUE : 0000_0000B ADDRESS : B4H INITIAL VALUE : 0000_0000B T0ST 8-bit Timer0 Counter ÷2 ÷4 ÷16 ÷64 MUX Clear T0(8Bit) ÷256 Timer0 Interrupt [B3H] Clear ÷1024 T0IF ÷4096 [B3H] Comparator [B3H] 3 CDR0 (8Bit) T0CK[2:0] EIEDGE.0 T0DR (8Bit) 8-bit Timer0 Data Register INT0 INT0 Interrupt INT0IF T1CN T1ST 8-bit Timer1 Counter Clear ÷1 ÷2 T1(8Bit) MUX ÷16 Timer1 Interrupt [B6H] Clear T1IF 2 T1CK[1:0] [B6H] EIEDGE.1 CDR1 (8Bit) [B5H] Comparator T1DR (8Bit) 8-bit Timer1 Data Register INT1 INT1IF INT1 Interrupt Figure 11-10 8-bit Capture Mode for Timer0, 1 PS030302-0212 PRELIMINARY 74 Z51F6412 Product Specification CDR0, CDR1 Load n T0/T1 Value n-1 n-2 Count Pulse Period PCP 6 Up-count 5 4 3 2 1 0 TIME Ext. INT0,1PIN Interrupt Request (INT0F,INT1F) Interrupt Interval Period Figure 11-11 Input Capture Mode Operation of Timer 0, 1 FFH FFH XXH T0, T1 YYH 00H 00H 00H 00H 00H Interrupt Request (T0IF,T1IF) Ext. INT0,1 PIN Interrupt Request (INT0F,INT1F) Interrupt Interval Period = FFH+01H+FFH+01H+YYH +01H Figure 11-12 Express Timer Overflow in Capture Mode PS030302-0212 PRELIMINARY 75 Z51F6412 Product Specification 11.5.1.5 16 Bit Capture Mode The 16-bit capture mode is the same operation as 8-bit capture mode, except that the timer register uses 16 bits. The clock source is selected from T0CK[2:0] and T1CK[1:0] must set 11b and 16BIT2 bit must set to ‘1’. The 16-bit mode setting is shown as Figure 11-13 T0CR T1CR T0EN T0PE CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST 1 X 1 X X X X X POL1 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST X 1 0 1 1 1 X X EC0 fx T0CN P r e s c a l e r ADDRESS : B2H INITIAL VALUE : 0000_0000B ADDRESS : B4H INITIAL VALUE : 0000_0000B T0ST 16-bit Counter ÷2 [B6H:B3H] ÷4 ÷16 MUX ÷64 T1(8Bit) MSB ÷256 T0(8Bit) LSB Clear Timer0 Interrupt Clear ÷1024 T1IF ÷4096 Comparator 3 CDR1(8Bit) +CDR0(8BIT) T0CK[2:0] EIEDGE.0 [B6H:B3H] T1DR(8Bit) +T0DR(8Bit) 16-bit Data Register INT0 INT0IF [B5H:B3H] INT0 Interrupt Figure 11-13 16-bit Capture Mode of Timer 0, 1 11.5.1.6 PWM Mode The timer 1 has a PWM (pulse Width Modulation) function. In PWM mode, the T1/PWM1 output pin outputs up to 10-bit resolution PWM output. This pin should be configured as a PWM output by set T1_PE to ‘1’. The period of the PWM output is determined by the T1PPR (PWM period register) + T1PWHR[3:2] + T1PWHR[1:0] PWM Period = [ T1PWHR[3:2]T1PPR ] X Source Clock PWM Duty = [ T1PWHR[1:0] T1PDR ] X Source Clock Note> T1PPR must be set to higher than T1PDR for guaranteeing operation. PS030302-0212 PRELIMINARY 76 Z51F6412 Product Specification Table 11-7 PWM Frequency vs. Resolution at 8 Mhz Resolution Frequency T1CK[1:0]=00 (125ns) T1CK[1:0]=01 (250ns) T1CK[1:0]=10 (2us) 10 Bit 7.8KHz 3.9KHz 0.49KHz 9 Bit 15.6KHz 7.8KHz 0.98KHz 8 Bit 31.2KHz 15.6KHz 1.95KHz 7 Bit 62.4KHz 31.2KHz 3.91KHz The POL bit of T1CR register decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM output is determined by the bit POL (1: High, 0: Low). And if the duty value is set to "00H", the PWM output is determined by the bit POL (1: Low, 0: High). T1CR T1PWHR POL1 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST X 0 1 0 X X X X T1_PE - - - 1 - - - ADDRESS : B4H INITIAL VALUE : 0000_0000B ADDRESS : B7H INITIAL VALUE : 0---_0000B PW1H3 PW1H2 PW1H1 PW1H0 X X X Period High X Duty High 8-bit Timer1 PWM Period Register T1PPR (8 Bit) T1PWHR[1:0] T1_PE [B7H] fx P r e s c a l e r T1ST T1CN ÷2 ÷16 MUX 2 Bit 8-bit Timer1 Counter + 2-bit 2 T1CK[1:0] T0 Clock Source S Comparator ÷1 T1 (8 Bit) Clear [B6H] Q PWM1 R POL Comparator Slave T1PDR (8 Bit) [B6H] T1PWHR[3:2] Master T1PDR (8 Bit) [B6H] Figure 11-14 PWM Mode PS030302-0212 PRELIMINARY 77 Z51F6412 Product Specification Source Clock (fX) T1 00 01 02 03 04 7F 80 81 82 3FF 00 01 02 T1/PWM1 POL = 1 T1/PWM1 POL = 0 Duty Cycle(1+80H)X250ns = 32.25us Period Cycle(1+3FFH)X250ns = 256us  3.9kHz T1CR[1:0] = 00H(fXIN) T1PWHR = 03H T1PPR = FFH T1PDR = 80H PW1H3 PW1H2 T1PPR(8 Bit) 1 1 FFH PW1H1 PW1H0 T1PDR(8 Bit) 0 0 80H Figure 11-15 Example of PWM at 4MHz T1CR[1:0] = 10H(2us) T1PWHR = 00H T1PPR = 0EH T1PDR = 05H Write 0AH to T3PPR Source Clock (fX) T3 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 00 01 02 03 04 05 06 07 08 09 0A 00 01 02 03 04 05 06 T1/PWM1 POL = 1 Duty Cycle (1+05H)X2us = 12us Duty Cycle (1+05H)X2us = 12us Period Cycle (1+0EH)X2us = 32us  31.25kHz Duty Cycle (1+05H)X2us = 12us Period Cycle (1+0AH)X2us = 22us  45.5kHz Figure 11-16 Example of Changing the Period in Absolute Duty Cycle at 4Mhz PS030302-0212 PRELIMINARY 78 Z51F6412 Product Specification 11.5.1.7 8-Bit (16 Bit) Compare Output Mode If the T1 (T0+T1) value and the T1DR (T0DR+T1DR) value are matched, T1/PWM1 port outputs. The output is 50:50 of duty square wave, the frequency is following f COMP  Oscillator Frequency 2  Prescaler Value  (TDR  1) To export the compare output as T1/PWM1, the T1_PE bit in the T1PWHR register must set to ‘1’. 11.5.1.8 Register Map Table 11-8 Register Map Name Address Dir T0CR B2 R/W T0 B3 T0DR B3 CDR0 B3 T1CR B4 T1DR T1PPR Default Description 00H Timer 0 Mode Control Register R 00H Timer 0 Register W FFH Timer 0 Data Register R 00H Capture 0 Data Register R/W 00H Timer 1 Mode Control Register B5 W FFH Timer 1 Data Register B5 W FFH Timer 1 PWM Period Register T1 B6 R 00H Timer 1 Register T1PDR B6 R/W 00H Timer 1 PWM Duty Register CDR1 B6 R 00H Capture 1 Data Register T1PWHR B7 W 00H Timer 1 PWM High Register 11.5.1.9 Timer/Counter 0, 1 Register description The Timer/Counter 0, 1 Register consists of Timer 0 Mode Control Register (T0CR), Timer 0 Register (T0), Timer 0 Data Register (T0DR), Capture 0 Data Register (CDR0), Timer 1 Mode Control Register (T1CR), Timer 1 Data Register (T1DR), Timer 1 PWM Period Register (T1PPR), Timer 1 Register (T1), Timer 1 PWM Duty Register (T1PPR), Capture 1 Data Register (CDR1) and Timer 1 PWM High Register (T1PWHR). 11.5.1.10 Register description for Timer/Counter 0, 1 T0CR (Timer 0 Mode Control Register) : B2H 7 6 5 4 3 2 1 0 T0EN T0_PE CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST R/W R/W R/W R/W R/W R/W R/W T0EN PS030302-0212 R/W Initial value : 00H Control Timer 0 PRELIMINARY 79 Z51F6412 Product Specification T0_PE CAP0 T0CK[2:0] 0 Timer 0 disable 1 Timer 0 enable Control Timer 0 Output port 0 Timer 0 Output disable 1 Timer 0 Output enable Control Timer 0 operation mode 0 Timer/Counter mode 1 Capture mode Select Timer 0 clock source. Fx is main system clock frequency T0CK2 T0CN T0ST T0CK1 T0CK0 Description 0 0 0 fx/2 0 0 1 fx/4 0 1 0 fx/16 0 1 1 fx/64 1 0 0 fx/256 1 0 1 fx/1024 1 1 0 fx/4096 1 1 1 External Clock (EC0) Control Timer 0 Count pause/continue 0 Temporary count stop 1 Continue count Control Timer 0 start/stop 0 Counter stop 1 Clear counter and start T0 (Timer 0 Register: Read Case) : B3H 7 6 5 4 3 2 1 0 T07 T06 T05 T04 T03 T02 T01 T00 R R R R R R R T0[7:0] R Initial value : 00H T0 Counter data T0DR (Timer 0 Data Register: Write Case) : B3H 7 6 5 4 3 2 1 0 T0D7 T0D6 T0D5 T0D4 T0D3 T0D2 T0D1 T0D0 W W W W W W W W Initial value : FFH T0D[7:0] T0 Compare data CDR0 (Capture 0 Data Register: Read Case) : B3H 7 6 5 4 3 2 1 0 CDR07 CDR06 CDR05 CDR04 CDR03 CDR02 CDR01 CDR00 R R R R R R R CDR0[7:0] PS030302-0212 R Initial value : 00H T0 Capture data PRELIMINARY 80 Z51F6412 Product Specification T1CR (Timer 1 Mode Count Register) : B4H 7 6 5 4 3 2 1 0 POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST R/W R/W R/W R/W R/W R/W R/W POL R/W Initial value : 00H Configure PWM polarity 16BIT PWM1E CAP1 T1CK[1:0] T1CN T1ST 0 Negative (Duty Match: Clear) 1 Positive (Duty Match: Set) Select Timer 1 8/16Bit 0 8 Bit 1 16 Bit Control PWM enable 0 PWM disable 1 PWM enable Control Timer 1 mode 0 Timer/Counter mode 1 Capture mode Select clock source of Timer 1. Fx is the frequency of main system. T1CK1 T1CK0 description 0 0 fx 0 1 fx/2 1 0 fx/16 1 1 Use Timer 0 Clock Control Timer 1 Count pause/continue 0 Temporary count stop 1 Continue count Control Timer 1 start/stop 0 Counter stop 1 Clear counter and start T1DR (Timer 1 Data Register: Write Case) : B5H 7 6 5 4 3 2 1 0 T1D7 T1D6 T1D5 T1D4 T1D3 T1D2 T1D1 T1D0 W W W W W W W W Initial value : FFH T1D[7:0] T1 Compare data T1PPR (Timer 1 PWM Period Register: Write Case PWM mode only) : B5H 7 6 5 4 3 2 1 0 T1PP7 T1PP6 T1PP5 T1PP4 T1PP3 T1PP2 T1PP1 T1PP0 W W W W W W W W Initial value : FFH T1PP[7:0] T1 PWM Period data T1 (Timer 1 Register: Read Case) : B6H PS030302-0212 PRELIMINARY 81 Z51F6412 Product Specification 7 6 5 4 3 2 1 0 T17 T16 T15 T14 T13 T12 T11 T10 R R R R R R R T1[7:0] R Initial value : 00H T1 Counter Period data T1PDR (Timer 1 PWM Duty Register) : B6H 7 6 5 4 3 2 1 0 T1PD7 T1PD6 T1PD5 T1PD4 T1PD3 T1PD2 T1PD1 T1PD0 R/W R/W R/W R/W R/W R/W R/W T1PD[7:0] R/W Initial value : 00H T1 PWM Duty data Note) only write, when PWM3E ‘1’ CDR1 (Capture 1 Data Register: Read Case) : B6H 7 6 5 4 3 2 1 0 CDR17 CDR16 CDR15 CDR14 CDR13 CDR12 CDR11 CDR10 R R R R R R R CDR3[7:0] R Initial value : 00H T1 Capture data T1PWHR (Timer 1 PWM High Register) : B7H 7 6 5 4 3 2 1 0 T1_PE - - - PW1H3 PW1H2 PW1H1 PW1H0 R/W - - - R/W R/W R/W T1_PE Control Timer 1 Output port operation Note) only writable Bit. Be careful 0 Timer 1 Output disable 1 Timer 1 Output enable PW1H[3:2] PWM period High value (Bit [9:8]) PW1H[1:0] PWM duty High value (Bit [9:8]) PERIOD: DUTY: PS030302-0212 R/W Initial value : 00H PW1H3 PW1H1 PW1H2 PW1H0 T1PPR[7:0] T1PDR[7:0] PRELIMINARY 82 Z51F6412 Product Specification 11.5.2 16-bit Timer/Event Counter 2, 3, 4, 5 11.5.2.1 Overview The 16-bit timer x(2~5) consists of Multiplexer, Timer Data Register High/Low, Timer Register High/Low, Timer Mode Control Register, PWM Duty High/Low, PWM Period High/Low Register It is able to use internal 16-bit timer/ counter without a port output function. The 16-bit timer x is able to use the divided clock of the main clock selected from prescaler output. 11.5.2.2 16-Bit Timer/Counter Mode In the 16-bit Timer/Counter Mode, If the TxH + TxL value and the TxDRH + TxDRL value are matched, T3/PWM3 port outputs. The output is 50:50 of duty square wave, the frequency is following f  COMP Timer Clock Frequency 2  PrescalerValue (TxDR  1) fCOMP is timer output frequency and TxDR is the 16 bits value of TxDRH and TxDRL. To export the compare output as Tx/PWMx, the Tx_PE bit in the TxCR1 register must set to ‘1’. The 16-bit Timer/Counter Mode is selected by control registers as shown in Figure 11-17 TxCR TxCR1 TxEN PWMx E CAPx TxCK2 TxCK1 TxCK0 TxCN TxST 1 - 0 X X X X X - - - - - ECEN Tx_PE POL - - - - - X X X ÷1 SCLK P r e s c a l e r TxEN ÷4 ADDRESS : BAH, C2H, CAH, 2F38H INITIAL VALUE : 0--0_0000B ADDRESS : BBH, C3H, CBH, 2F39H INITIAL VALUE : ----_-000B TxST 16-bit Timer3 Counter ÷8 ÷16 TxH (8-bit) MUX ÷64 ÷256 TxL (8-bit) Clear ÷1024 ÷2048 TxIF 3 TxCK[2:0] Timerx Interrupt Comparator TxDRH (8-bit) TxDRL (8-bit) 16-bit Timer3 Data Register Figure 11-17 Timer4 16-bit Mode Block Diagram PS030302-0212 PRELIMINARY 83 Z51F6412 Product Specification 11.5.2.3 16-Bit Capture Mode The timer X(2~5) capture mode is set by CAPx as ‘1’ in TxCR register. The clock is same source as Output Compare mode. The interrupt occurs at TxH, TxL and TxDRH, TxDRL matching time. The capture result is loaded into CDRxH, CDRxL. The TxH, TxL value is automatically cleared(0000H) by hardware and restarts counter. This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer. As the EIEDGE and EIPOLA register setting, the external interrupt INTx function is chosen. The CDRxH, PWMxHDR and TxH are in same address. In the capture mode, reading operation is read the CDRxH, not TxH because path is opened to the CDRxH. PWMxHDR will be changed in writing operation. The PWMxLDR, TxL, CDRxL has the same function. TxCR TxEN PWMxE CAPx TxCK2 TxCK1 TxCK0 TxCN TxST ADDRESS : BAH, C2H , CAH , 2F38H INITIAL VALUE : 0000 _0000 b TxCR1 - - - - - ECEN TxPE POL ADDRESS : BBH , C3H, CBH , 2F39H INITIAL VALUE : ---- _-000 b SCLK P R E S C A L E R ÷1 ÷4 ÷8 ÷ 16 ÷ 64 ÷ 256 ÷ 1024 ÷ 2048 TxST TxEN MUX 16-bit Counter TxH(8-bit) TxL(8-bit) clear TxIF comparator ECx CDRxH(8-bit) 4 EIEDGE[5:2] ECTN,TxCK[2:0] CDRxL(8-bit) 16-bit Capture Register TxDRH(8-bit) TxDRL(8-bit) 16-bit Timer Data Register INTxIF INTx Timerx Interrupt INTx Interrupt Figure 11-18 16-bit Capture Mode of Timer x 11.5.2.4 PWM Mode The timer X(2~5) has a PWM (pulse Width Modulation) function. In PWM mode, the TX/PWMX output pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by set TX_PE to ‘1’. The PWM output mode is determined by the PWMxHPR, PWMxLPR, PWMxHDR and PWMxLDR. And you should configure PWMxE bit to “1” in TxCR register PWM Period = [ PWMxHPR, PWMxLPR ] X Source Clock PWM Duty = [ PWMxHDR, PWMxLDR ] X Source Clock PS030302-0212 PRELIMINARY 84 Z51F6412 Product Specification Table 11-9 PWM Frequency vs. Resolution at 8 Mhz Frequency Resolution TxCK[2:0]=000 (125ns) TxCK[2:0]=010 (500ns) TxCK[2:0]=011 (1us) 16-bit 122.070Hz 30.469Hz 15.259Hz 15-bit 244.141Hz 60.938Hz 30.518Hz 10-bit 7.8125KHz 1.95KHz 976.563Hz 9-bit 15.625KHz 3.9KHz 1.953KHz 8-bit 31.25KHz 7.8KHz 3.906KHz The POL bit of TxCR register decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM output is determined by the bit POL (1: High, 0: Low). And if the duty value is set to "00H", the PWM output is determined by the bit POL (1: Low, 0: High). TxCR TxEN PWMxE CAPx TxCK2 TxCK1 TxCK0 TxCN TxST ADDRESS : BAH, C2H , CA H, 2F38 H INITIAL VALUE : 0000 _0000 b TxCR1 - - - - - ECEN TxPE POL ADDRESS : BBH, C3H, CBH, 2F39 H INITIAL VALUE : ---- _-000 b 16-bit Timerx PWM Period Register SCLK P R E S C A L E R PWMxHPR (8-bit) ÷1 ÷4 ÷8 ÷ 16 ÷ 64 ÷ 256 ÷ 1024 ÷ 2048 TxEN S TxH(8-bit) TxL(8-bit) Timerx Interrupt TxPE TxST MUX TxIF PWMxLPR (8-bit) clear R Q POL Px / PWMx 16-bit Counter comparator ECx Slave PWMxHDR (8-bit) PWMxLDR (8-bit) Master PWMxHDR (8-bit) PWMxLDR (8-bit) 3 TxCK[2:0] Figure 11-19 PWM Mode PS030302-0212 PRELIMINARY 85 Z51F6412 Product Specification Source Clock (fSCLK) Tx 00 01 02 03 7F 04 80 81 82 3FF 00 01 02 Tx/PWMx POL0 = 1 Tx/PWMx POL0 = 0 Duty Cycle(1+0080H)X500ns = 64.50us Period Cycle(1+03FFH)X500ns = 512us  1.95kHz TxCK[2:0] = 01H(fPCLK/4) PWMxHPR = 03H PWMxLPR = FFH PWMxHDR = 00H PWMxLDR = 80H PWMxHPR(8-bit) PWMxLPR(8-bit) 03H FFH PWMxHDR(8-bit) PWMxLDR(8-bit) 00H 80H Figure 11-20 Example of PWM at 8MHz 11.5.2.5 Register Map Table 11-10 Register Map Name Address Dir Default Description T2CR BAH R/W 00H Timer 2 Mode Control Register T2CR1 BBH R/W 00H Timer 2 Mode Control Register 1 T2L BCH R 00H Timer 2 Low Register PWM2LDR BCH R/W 00H PWM 2 Duty Low Register CDR2L BCH R 00H Timer 2 Capture Data Low Register T2H BDH R 00H Timer 2 High Register PWM2HDR BDH R/W 00H PWM 2 Duty High Register CDR2H BDH R 00H Timer 2 Capture Data High Register T2DRL BEH W FFH Timer 2 Data Register Low PWM2LPR BEH W FFH PWM 2 Period Low Register T2DRH BFH W FFH Timer 2 Data Register High PWM2HPR BFH W FFH PWM 2 Period High Data Register T3CR C2H R/W 00H Timer 3 Mode Control Register T3CR1 C3H R/W 00H Timer 3 Mode Control Register 1 T3L C4H R 00H Timer 3 Low Register PWM3LDR C4H R/W 00H PWM 3 Duty Low Register CDR3L C4H R 00H Timer 3 Capture Data Low Register T3H C5H R 00H Timer 3 High Register PWM3HDR C5H R/W 00H PWM 3 Duty High Register CDR3H C5H R 00H Timer 3 Capture Data High Register T3DRL C6H W FFH Timer 3 Data Register Low PWM3LPR C6H W FFH PWM 3 Period Low Register T3DRH C7H W FFH Timer 3 Data Register High PS030302-0212 PRELIMINARY 86 Z51F6412 Product Specification PWM3HPR C7H W FFH PWM 3 Period High Data Register T4CR CAH R/W 00H Timer 4 Mode Control Register T4CR1 CBH R/W 00H Timer 4 Mode Control Register 1 T4L CCH R 00H Timer 4 Low Register PWM4LDR CCH R/W 00H PWM 4 Duty Low Register CDR4 L CCH R 00H Timer 4 Capture Data Low Register T4 H CDH R 00H Timer 4 High Register PWM4 HDR CDH R/W 00H PWM 4 Duty High Register CDR4 H CDH R 00H Timer 4 Capture Data High Register T4 DRL CEH W FFH Timer 4 Data Register Low PWM4 LPR CEH W FFH PWM 4 Period Low Register T4 DRH CFH W FFH Timer 4 Data Register High PWM4 HPR CFH W FFH PWM 4 Period High Data Register T5CR 2F38H R/W 00H Timer 5 Mode Control Register T5CR1 2F39H R/W 00H Timer 5 Mode Control Register 1 T5L 2F3AH R 00H Timer 5 Low Register PWM5LDR 2F3AH R/W 00H PWM 5 Duty Low Register CDR5L 2F3AH R 00H Timer 5 Capture Data Low Register T5H 2F3BH R 00H Timer 5 High Register PWM5HDR 2F3BH R/W 00H PWM 5 Duty High Register CDR5H 2F3BH R 00H Timer 5 Capture Data High Register T5DRL 2F3CH W FFH Timer 5 Data Register Low PWM5LPR 2F3CH W FFH PWM 5 Period Low Register T5DRH 2F3DH W FFH Timer 5 Data Register High PWM5HPR 2F3DH W FFH PWM 5 Period High Data Register 11.5.2.6 Timer/Counter x Register description The Timer 2~5 Register consists of Timer 2~5 Mode Control Register (T2CR), (T3CR), (T4CR), (T5CR), Timer 2~5 Mode Control Register 1 (T2CR1), (T3CR1), (T4CR1), (T5CR1), Timer 2~5 Low Register (T2L), (T3L), (T4L), (T5L), Timer 2~5 Data Register Low (T2DRL), (T3DRL), (T4DRL), (T5DRL), Timer 2~5 High Register (T2H), (T3H), (T4H), (T5H), Timer 2~5 Data Register High (T2DRH), (T3DRH), (T4DRH), (T5DRH), Timer 2~5 Capture Data Low Register (CDR2L), (CDR3L), (CDR4L), (CDR5L), Timer 2~5 Capture Data High Register (CDR2H), (CDR3H), (CDR4H), (CDR5H), PWM2~5 Low Duty Register (PWM2LDR), (PWM3LDR), (PWM4LDR), (PWM5LDR), PWM2~5 High Duty Register (PWM2HDR), (PWM3HDR), (PWM4HDR), (PWM5HDR), PWM2~5 Low Period Register (PWM2LPR), (PWM3LPR), (PWM4LPR), (PWM5LPR), PWM2~5 High Period Register (PWM2HPR), (PWM3HPR), (PWM4HPR), (PWM5HPR). PS030302-0212 PRELIMINARY 87 Z51F6412 Product Specification 11.5.2.7 Register description for Timer/Counter 2~5 T2CR, T3CR, T4CR, T5CR (Timer 2~5 Mode Control Register): BAH, C2H, CAH, 2F38H 7 6 5 4 3 2 1 0 TxEN PWMxE CAPx TxCK2 TxCK1 TxCK0 TxCN TxST R/W R/W R/W R/W R/W R/W R/W TxEN R/W Initial value : 00H Control Timer X PWMxE CAPx 0 0 1 Timer X enable Control PWM enable 0 PWM disable 1 PWM enable Control Timer X capture mode. TxCK[2:0] 0 Timer/Counter mode 1 Capture mode Select clock source of Timer X. Fx is the frequency of main system TxCK2 TxCN TxCK1 TxCK0 description 0 0 0 fSCLK 0 0 1 fSCLK/4 0 1 0 fSCLK/8 0 1 1 fSCLK/16 1 0 0 fSCLK/64 1 0 1 fSCLK/256 1 1 0 fSCLK/1024 1 1 1 fSCLK/2048 Control Timer X Count pause/continue. TxST 0 Temporary count stop 1 Continue count Control Timer X start/stop 0 Counter stop 1 Clear counter and start T2CR1, T3CR1, T4CR1, T5CR1 (Timer 2~5 Mode Control Register 1) : BBH, C3H, CBH, 2F39H 7 6 5 4 3 2 1 0 - - - - - ECEN Tx_PE POL - - - - - R/W R/W ECEN Tx_PE POL PS030302-0212 R/W Initial value : 00H Control Timer X External Clock 0 Timer X External Clock disable 1 Timer X External Clock enable Control Timer X Output port 0 Timer X Output disable 1 Timer X Output enable Configure PWM polarity PRELIMINARY 88 Z51F6412 Product Specification 0 Negative (Duty Match: Clear) 1 Positive (Duty Match: Set) T2L, T3L, T4L, T5L (Timer 2~5 Low Register, Read Case) : BCH, C4H, CCH, 2F3AH 7 6 5 4 3 2 1 0 TxL7 TxL6 TxL5 TxL4 TxL3 TxL2 TxL1 TxL0 R R R R R R R TxL[7:0] R Initial value : 00H TxL Counter Period Low data. CDR2L, CDR3L, CDR4L, CDR5L (Capture 2~5 Data Low Register, Read Case) : BCH, C4H, CCH, 2F3AH 7 6 5 4 3 2 1 0 CDRxL07 CDRxL06 CDRxL05 CDRxL04 CDRxL03 CDRxL02 CDRxL01 CDRxL00 R R R R R R R CDRxL[7:0] R Initial value : 00H Tx Capture Low data. PWM2LDR, PWM3LDR, PWM4LDR, PWM5LDR (PWM 2~5 Low Duty Register, Write Case) : BCH, C4H, CCH, 2F3AH 7 6 5 4 3 2 1 0 PWMxLD7 PWMxLD6 PWMxLD5 PWMxLD4 PWMxLD3 PWMxLD2 PWMxLD1 PWMxLD0 W W W W W W W PWMxLD[7:0] W Initial value : 00H Tx PWM Duty Low data Note) only write, when PWMxE ‘1’ T2H, T3H, T4H, T5H (Timer 2~5 High Register, Read Case) : BDH, C5H, CDH, 2F3BH 7 6 5 4 3 2 1 0 TxH7 TxH6 TxH5 TxH4 TxH3 TxH2 TxH1 TxH0 R R R R R R R TxH[7:0] R Initial value : 00H TxH Counter Period High data. CDR2H, CDR3H, CDR4H, CDR5H (Capture 2~5 Data High Register, Read Case) : BDH, C5H, CDH, 2F3BH 7 6 5 4 3 2 1 0 CDRxH07 CDRxH06 CDRxH05 CDRxH04 CDRxH03 CDRxH02 CDRxH01 CDRxH00 R R R R R R R CDRxH[7:0] PS030302-0212 R Initial value : 00H Tx Capture High data PRELIMINARY 89 Z51F6412 Product Specification PWM2HDR, PWM3HDR, PWM4HDR, PWM5HDR (PWM 2~5 High Duty Register, Write Case) : BDH, C5H, CDH, 2F3BH 7 6 5 4 3 2 1 0 PWMxHD7 PWMxHD6 PWMxHD5 PWMxHD4 PWMxHD3 PWMxHD2 PWMxHD1 PWMxHD0 W W W W W W W PWMxHD[7:0] W Initial value : 00H Tx PWM Duty High data Note) only write, when PWM3E ‘1’ T2DRL, T3DRL, T4DRL, T5DRL (Timer 2~5 Data Register Low, Write Case) : BEH, C6H, CEH, 2F3CH 7 6 5 4 3 2 1 0 TxLD7 TxLD6 TxLD5 TxLD4 TxLD3 TxLD2 TxLD1 TxLD0 W W W W W W W TxLD[7:0] W Initial value : FFH TxL Compare Low data PWM2LPR, PWM3LPR, PWM4LPR, PWM5LPR (PWM 2~5 Low Period Register, Write Case) : BEH, C6H, CEH, 2F3CH 7 6 5 4 3 2 1 0 PWMxLP7 PWMxLP6 PWMxLP5 PWMxLP4 PWMxLP3 PWMxLP2 PWMxLP1 PWMxLP0 W W W W W W W PWMxLP[7:0] W Initial value : FFH Tx PWM Duty Low data Note) only write, when PWM3E ‘1’ T2DRH, T3DRH, T4DRH, T5DRH (Timer 2~5 Data Register High, Write Case) : BFH, C7H, CFH, 2F3DH 7 6 5 4 3 2 1 0 TxHD7 TxHD6 TxHD5 TxHD4 TxHD3 TxHD2 TxHD1 TxHD0 W W W W W W W TxHD[7:0] W Initial value : FFH TxH Compare High data PWM2HPR, PWM3HPR, PWM4HPR, PWM5HPR (PWM 2~5 High Period Register, Write Case) : BFH, C7H, CFH, 2F3DH 7 6 5 4 3 2 1 0 PWMxHP7 PWMxHP6 PWMxHP5 PWMxHP4 PWMxHP3 PWMxHP2 PWMxHP1 PWMxHP0 W W W W W W W PWMxHP[7:0] PS030302-0212 W Initial value : FFH Tx PWM Duty High data Note) only write, when PWM3E ‘1’. PRELIMINARY 90 Z51F6412 Product Specification 11.5.3 Timer Interrupt Status Register (TMISR) 11.5.3.1 Register description for TMISR TMISR (Timer Interrupt Status Register) : D5H 7 6 5 4 3 2 1 0 - - TMIF5 TMIF4 TMIF3 TMIF2 TMIF1 TMIF0 - - R R R R R TMIF5 TMIF4 TMIF3 TMIF2 TMIF1 TMIF0 R Initial value : 00H Timer 5 Interrupt Flag 0 No Timer 5 interrupt 1 Timer 5 interrupt occurred, write “1” to clear interrupt flag Timer 4 Interrupt Flag 0 No Timer 4 interrupt 1 Timer 4 interrupt occurred, write “1” to clear interrupt flag Timer 3 Interrupt Flag 0 No Timer 3 interrupt 1 Timer 3 interrupt occurred, write “1” to clear interrupt flag Timer 2 Interrupt Flag 0 No Timer 2 interrupt 1 Timer 2 interrupt occurred, write “1” to clear interrupt flag Timer 1 Interrupt Flag 0 No Timer 1 interrupt 1 Timer 1 interrupt occurred, write “1” to clear interrupt flag Timer 0 Interrupt Flag 0 No Timer 0 interrupt 1 Timer 0 interrupt occurred, write “1” to clear interrupt flag Note) The Timer Interrupt Status Register contains interrupt information of each timers. Even if user disabled timer interrupt at IE2, user could check timer interrupt condition from this register. PS030302-0212 PRELIMINARY 91 Z51F6412 Product Specification 11.6 Buzzer Driver 11.6.1 Overview The Buzzer consists of 8 Bit Counter and BUZDR (Buzzer Data Register), BUZCR (Buzzer Control Register). The Square Wave (122.07Hz~250 KHz, @16MHz) gets out of P12/BUZ pin. BUZDR (Buzzer Data Register) controls the Buzzer frequency (look at the following expression). In the BUZCR (Buzzer Control Register), BUCK[1:0] selects source clock divided from prescaler. f BUZ (Hz)  Oscillator Frequency 2  Prescaler Ratio  (BUZDR  1) Table 11-11 Buzzer Frequency at 16MHz Buzzer Frequency (kHz) BUZDR[7:0] BUZCR[2:1]=00 BUZCR[2:1]=01 BUZCR[2:1]=10 BUZCR[2:1]=11 0000_0000 250kHz 125kHz 62.5kHz 31.25kHz 0000_0001 125kHz 62.5kHz 31.25kHz 15.624kHz … … … … … 1111_1101 984.252Hz 492.126Hz 246.062Hz 123.03Hz 1111_1110 980.392Hz 490.196Hz 245.098Hz 122.548Hz 1111_1111 976.562Hz 488.282Hz 244.140Hz 122.07Hz 11.6.2 Block Diagram 8-bit Up-counter ÷32 Pre scaler fx ÷64 ÷128 MUX Counter Overflow BUZCR[0] ÷256 F/F BUZCR[2:1] Selection Input Clock BUZO PIN 2 Counter Writing to BUZDR RESET Buzzer Control Register [9FH] BUZCR BUZDR Buzzer Data Register [8FH] Figure 11-21 Buzzer Driver Block Diagram PS030302-0212 PRELIMINARY 92 Z51F6412 Product Specification 11.6.3 Register Map Table 11-12 Register Map Name Address Dir Default Description BUZDR 8FH R/W FFH Buzzer Data Register BUZCR 9FH R/W 00H Buzzer Control Register 11.6.4 Buzzer Driver Register description Buzzer Driver consists of Buzzer Data Register (BUZDR), Buzzer Control Register (BUZCR). 11.6.5 Register description for Buzzer Driver BUZDR (Buzzer Data Register) : 8FH 7 6 5 4 3 2 1 0 BUZDR7 BUZDR6 BUZDR5 BUZDR4 BUZDR3 BUZDR2 BUZDR1 BUZDR0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH BUZDR[7:0] This bits control the Buzzer frequency Its resolution is 00H ~ FFH BUZCR (Buzzer Control Register) : 9FH 7 6 5 4 3 2 1 0 - - - - - BUCK1 BUCK0 BUZEN - - - - - R/W R/W BUCK[1:0] BUZEN R/W Initial value : 00H Buzzer Driver Source Clock Selection BUCK1 BUCK0 Source Clock 0 0 fx/32 0 1 fx/64 1 0 fx/128 1 1 fx/256 Buzzer Driver Operation Control 0 Buzzer Driver disable 1 Buzzer Driver enable Note) fx: Main system clock oscillation frequency PS030302-0212 PRELIMINARY 93 Z51F6412 Product Specification 11.7 USART 11.7.1 Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are listed below. - Full Duplex Operation (Independent Serial Receive and Transmit Registers) - Asynchronous or Synchronous Operation - Master or Slave Clocked Synchronous and SPI Operation - Supports all four SPI Modes of Operation (Mode 0, 1, 2, 3) - LSB First or MSB First Data Transfer @SPI mode - High Resolution Baud Rate Generator - Supports Serial Frames with 5,6,7,8, or 9 Data Bits and 1 or 2 Stop Bits - Odd or Even Parity Generation and Parity Check Supported by Hardware - Data OverRun Detection - Framing Error Detection - Digital Low Pass Filter - Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete - Double Speed Asynchronous Communication Mode USART has three main parts of Clock Generator, Transmitter and Receiver. The Clock Generation logic consists of synchronization logic for external clock input used by synchronous or SPI slave operation, and the baud rate generator for asynchronous or master (synchronous or SPI) operation. The Transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats. The write buffer allows a continuous transfer of data without any delay between frames. The receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery unit is used for asynchronous data reception. In addition to the recovery unit, the Receiver includes a parity checker, a shift register, a two level receive FIFO (UDATAx) and control logic. The Receiver supports the same frame formats as the Transmitter and can detect Frame Error, Data OverRun and Parity Errors. PS030302-0212 PRELIMINARY 94 Z51F6412 Product Specification 11.7.2 Block Diagram UBAUD SCLK Baud Rate Generator Master Clock Sync Logic XCK Control XCK UMSEL[1:0] RXD/ MISO RXC M U X M U X Rx Interrupt Rx Control Clock Recovery Data Recovery Receive Shift Register (RXSR) DOR/PE/FE Checker UDATA[0] (Rx) M U X UMSEL1&UMSEL0 Master Stop bit Generator D E P TXD/ MOSI D E P UMSEL0 Transmit Shift Register (TXSR) M U X B u s L i n e Parity Generator M U X Tx Control UDATA[1] (Rx) UPM0 I n t e r n a l UPM1 UDATA(Tx) SS Control SS TXC Rx Interrupt ADDRESS : E2H , FAH, 2F28H, 2F30H INITIAL VALUE : 0000_0000B UCTRLx1 UMSEL1 UMSEL0 UPM1 UPM0 UCTRLx2 UDRIE RXCIE WAKEIE TXE RXE USARTEN U2X ADDRESS : E3H, FBH ,2F29H , 2F31H INITIAL VALUE : 0000_0000B UCTRLx3 MASTER LOOPS DISXCK SPISS - USBS TX8 RX8 ADDRESS : E4H, FCH, 2F2AH, 2F32H, INITIAL VALUE : 0000_-000B UDRE WAKE SOFTRST DOR FE PE ADDRESS : E5H., FDH 2F2BH , 2F33H, INITIAL VALUE : 1000_0000B USTATx TXCIE TXC RXC USIZE2 USIZE1 USIZE0 UCPOL Figure 11-22 USART Block Diagram PS030302-0212 PRELIMINARY 95 Z51F6412 Product Specification 11.7.3 Clock Generation UBAUD U2X fSCLK Prescaling Up-Counter (UBAUD+1) /8 /2 SCLK M U X M U X txclk MASTER Sync Register Edge Detector UCPOL XCK M U X /2 UMSEL0 M U X rxclk Figure 11-23 Clock Generation Block Diagram The Clock generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation and those are Normal Asynchronous, Double Speed Asynchronous, Master Synchronous and Slave Synchronous. The clock generation scheme for Master SPI and Slave SPI mode is the same as Master Synchronous and Slave Synchronous operation mode. The UMSELn bit in UCTRLx1 register selects between asynchronous and synchronous operation. Asynchronous Double Speed mode is controlled by the U2X bit in the UCTRLx2 register. The MASTER bit in UCTRLx2 register controls whether the clock source is internal (Master mode, output port) or external (Slave mode, input port). The XCK pin is only active when the USART operates in Synchronous or SPI mode. Table below contains equations for calculating the baud rate (in bps). Table 11-13 Equations for Calculating Baud Rate Register Setting Operating Mode Equation for Calculating Baud Rate Asynchronous Normal Mode (U2X=0) Baud Rate fSCLK 16 UBAUDx 1 Asynchronous Double Speed Mode (U2X=1) Baud Rate fSCLK 8 UBAUDx 1 Synchronous or SPI Master Mode Baud Rate fSCLK 2 UBAUDx 1 PS030302-0212 PRELIMINARY 96 Z51F6412 Product Specification 11.7.4 External Clock (XCK) External clocking is used by the synchronous or spi slave modes of operation. External clock input from the XCK pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must then pass through an edge detector before it can be used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the maximum frequency of the external XCK pin is limited by the following equation. fXCK fSCLK 4 where fXCK is the frequency of XCK and fSCLK is the frequency of main system clock (SCLK). 11.7.5 Synchronous mode Operation When synchronous or spi mode is used, the XCK pin will be used as either clock input (slave) or clock output (master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input on RXD (MISO in spi mode) pin is sampled at the opposite XCK clock edge of the edge in the data output on TXD (MOSI in spi mode) pin is changed. The UCPOL bit in UCTRLx1 register selects which XCK clock edge is used for data sampling and which is used for data change. As shown in the figure below, when UCPOL is zero the data will be changed at rising XCK edge and sampled at falling XCK edge. UCPOL = 1 XCK TXD/RXD Sample UCPOL = 0 XCK TXD/RXD Sample Figure 11-24 Synchronous Mode XCKn Timing PS030302-0212 PRELIMINARY 97 Z51F6412 Product Specification 11.7.6 Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART supports all 30 combinations of the following as valid frame formats. - 1 start bit - 5, 6, 7, 8 or 9 data bits - no, even or odd parity bit - 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit (LSB). Then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit (MSB). If enabled the parity bit is inserted after the data bits, before the stop bits. A high to low transition on data pin is considered as start bit. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle state. The idle means high state of data pin. The next figure shows the possible combinations of the frame formats. Bits inside brackets are optional. 1 data frame Idle St D0 D1 D2 D3 D4 [D5] [D6] [D7] [D8] [P] Sp1 [Sp2] Idle / St Character bits Figure 11-25 frame format 1 data frame consists of the following bits • Idle No communication on communication line (TxD/RxD) • St Start bit (Low) • Dn Data bits (0~8) • Parity bit ------------ Even parity, Odd parity, No parity • Stop bit(s) ---------- 1 bit or 2 bits The frame format used by the USART is set by the USIZE[2:0], UPM[1:0] and USBS bits in UCTRLx1 register. The Transmitter and Receiver use the same setting. 11.7.7 Parity bit The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive-or is inverted. The parity bit is located between the MSB and first stop bit of a serial frame. PS030302-0212 PRELIMINARY 98 Z51F6412 Product Specification Peven = Dn-1 ^ … ^ D3 ^ D2 ^ D1 ^ D0 ^ 0 Podd = Dn-1 ^ … ^ D3 ^ D2 ^ D1 ^ D0 ^ 1 Peven : Parity bit using even parity Podd : Parity bit using odd parity Dn : Data bit n of the character 11.7.8 USART Transmitter The USART Transmitter is enabled by setting the TXE bit in UCTRLx1 register. When the Transmitter is enabled, the normal port operation of the TXD pin is overridden by the serial output pin of USART. The baud-rate, operation mode and frame format must be setup once before doing any transmissions. If synchronous or spi operation is used, the clock on the XCK pin will be overridden and used as transmission clock. If USART operates in spi mode, SS pin is used as SS input pin in slave mode or can be configured as SS output pin in master mode. This can be done by setting SPISS bit in UCTRLx3 register. 11.7.8.1 Sending Tx data A data transmission is initiated by loading the transmit buffer (UDATAx register I/O location) with the data to be transmitted. The data written in transmit buffer is moved to the shift register when the shift register is ready to send a new frame. The shift register is loaded with the new data if it is in idle state or immediately after the last stop bit of the previous frame is transmitted. When the shift register is loaded with new data, it will transfer one complete frame at the settings of control registers. If the 9-bit characters are used in asynchronous or synchronous operation mode (USIZE[2:0]=7), the ninth bit must be written to the TX8 bit in UCTRLx3 register before loading transmit buffer (UDATA register). 11.7.8.2 Transmitter flag and interrupt The USART Transmitter has 2 flags which indicate its state. One is USART Data Register Empty (UDRE) and the other is Transmit Complete (TXC). Both flags can be interrupt sources. UDRE flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the shift register. And also this flag can be cleared by writing ‘0’ to this bit position. Writing ‘1’ to this bit position is prevented. When the Data Register Empty Interrupt Enable (UDRIE) bit in UCTRLx2 register is set and the Global Interrupt is enabled, USART Data Register Empty Interrupt is generated while UDRE flag is set. The Transmit Complete (TXC) flag bit is set when the entire frame in the transmit shift register has been shifted out and there are no more data in the transmit buffer. The TXC flag is automatically cleared when the Transmit Complete Interrupt service routine is executed, or it can be cleared by writing ‘0’ to TXC bit in UCTRLx2 register. When the Transmit Complete Interrupt Enable (TXCIE) bit in UCTRLx2 register is set and the Global Interrupt is enabled, USART Transmit Complete Interrupt is generated while TXC flag is set. PS030302-0212 PRELIMINARY 99 Z51F6412 Product Specification 11.7.8.3 Parity Generator The Parity Generator calculates the parity bit for the sending serial frame data. When parity bit is enabled (UPM[1]=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the sending frame. 11.7.8.4 Disabling Transmitter Disabling the Transmitter by clearing the TXE bit will not become effective until ongoing transmission is completed. When the Transmitter is disabled, the TXD pin is used as normal General Purpose I/O (GPIO) or primary function pin. 11.7.9 USART Receiver The USART Receiver is enabled by setting the RXE bit in the UCTRLx1 register. When the Receiver is enabled, the normal pin operation of the RXD pin is overridden by the USART as the serial input pin of the Receiver. The baud-rate, mode of operation and frame format must be set before serial reception. If synchronous or spi operation is used, the clock on the XCK pin will be used as transfer clock. If USART operates in spi mode, SS pin is used as SS input pin in slave mode or can be configured as SS output pin in master mode. This can be done by setting SPISS bit in UCTRLx3 register. 11.7.9.1 Receiving Rx data When USART is in synchronous or asynchronous operation mode, the Receiver starts data reception when it detects a valid start bit (LOW) on RXD pin. Each bit after start bit is sampled at predefined baud-rate (asynchronous) or sampling edge of XCK (synchronous), and shifted into the receive shift register until the first stop bit of a frame is received. Even if there’s 2nd stop bit in the frame, the 2nd stop bit is ignored by the Receiver. That is, receiving the first stop bit means that a complete serial frame is present in the receiver shift register and contents of the shift register are to be moved into the receive buffer. The receive buffer is read by reading the UDATAx register. If 9-bit characters are used (USIZE[2:0] = 7) the ninth bit is stored in the RX8 bit position in the UCTRLx3 register. The 9th bit must be read from the RX8 bit before reading the low 8 bits from the UDATAx register. Likewise, the error flags FE, DOR, PE must be read before reading the data from UDATAx register. This is because the error flags are stored in the same FIFO position of the receive buffer. 11.7.9.2 Receiver flag and interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) flag indicates whether there are unread data present in the receive buffer. This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty. If the Receiver is disabled (RXE=0), the receiver buffer is flushed and the RXC flag is cleared. When the Receive Complete Interrupt Enable (RXCIE) bit in the UCTRLx2 register is set and Global Interrupt is enabled, the USART Receiver Complete Interrupt is generated while RXC flag is set. PS030302-0212 PRELIMINARY 100 Z51F6412 Product Specification The USART Receiver has three error flags which are Frame Error (FE), Data OverRun (DOR) and Parity Error (PE). These error flags can be read from the USTATx register. As data received are stored in the 2-level receive buffer, these error flags are also stored in the same position of receive buffer. So, before reading received data from UDATAx register, read the USTATx register first which contains error flags. The Frame Error (FE) flag indicates the state of the first stop bit. The FE flag is zero when the stop bit was correctly detected as one, and the FE flag is one when the stop bit was incorrect, ie detected as zero. This flag can be used for detecting out-of-sync conditions between data frames. The Data OverRun (DOR) flag indicates data loss due to a receive buffer full condition. A DOR occurs when the receive buffer is full, and another new data is present in the receive shift register which are to be stored into the receive buffer. After the DOR flag is set, all the incoming data are lost. To prevent data loss or clear this flag, read the receive buffer. The Parity Error (PE) flag indicates that the frame in the receive buffer had a Parity Error when received. If Parity Check function is not enabled (UPM[1]=0), the PE bit is always read zero. Note) The error flags related to receive operation are not used when USART is in spi mode. 11.7.9.3 Parity Checker If Parity Bit is enabled (UPM[1]=1), the Parity Checker calculates the parity of the data bits in incoming frame and compares the result with the parity bit from the received serial frame. 11.7.9.4 Disabling Receiver In contrast to Transmitter, disabling the Receiver by clearing RXE bit makes the Receiver inactive immediately. When the Receiver is disabled the Receiver flushes the receive buffer and the remaining data in the buffer is all reset. The RXD pin is not overridden the function of USART, so RXD pin becomes normal GPIO or primary function pin. 11.7.9.5 Asynchronous Data Reception To receive asynchronous data frame, the USART includes a clock and data recovery unit. The Clock Recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the RXD pin. The Data recovery logic samples and low pass filters the incoming bits, and this removes the noise of RXD pin. The next figure illustrates the sampling process of the start bit of an incoming frame. The sampling rate is 16 times the baud-rate for normal mode, and 8 times the baud rate for Double Speed mode (U2X=1). The horizontal arrows show the synchronization variation due to the asynchronous sampling process. Note that larger time variation is shown when using the Double Speed mode. PS030302-0212 PRELIMINARY 101 Z51F6412 Product Specification RxD Sample (U2X = 0) START IDLE 0 0 1 2 34 5 2 3 6 7 8 9 10 BIT0 11 12 13 14 15 16 1 8 1 2 3 Sample (U2X = 1) 0 1 4 5 6 7 2 Figure 11-26 Start Bit Sampling When the Receiver is enabled (RXE=1), the clock recovery logic tries to find a high to low transition on the RXD line, the start bit condition. After detecting high to low transition on RXD line, the clock recovery logic uses samples 8,9, and 10 for Normal mode, and samples 4, 5, and 6 for Double Speed mode to decide if a valid start bit is received. If more than 2 samples have logical low level, it is considered that a valid start bit is detected and the internally generated clock is synchronized to the incoming data frame. And the data recovery can begin. The synchronization process is repeated for each start bit. As described above, when the Receiver clock is synchronized to the start bit, the data recovery can begin. Data recovery process is almost similar to the clock recovery process. The data recovery logic samples 16 times for each incoming bits for Normal mode and 8 times for Double Speed mode. And uses sample 8, 9, and 10 to decide data value for Normal mode, samples 4, 5, and 6 for Double Speed mode. If more than 2 samples have low levels, the received bit is considered to a logic 0 and more than 2 samples have high levels, the received bit is considered to a logic 1. The data recovery process is then repeated until a complete frame is received including the first stop bit. The decided bit value is stored in the receive shift register in order. Note that the Receiver only uses the first stop bit of a frame. Internally, after receiving the first stop bit, the Receiver is in idle state and waiting to find start bit. BIT n RxD Sample (U2X = 0) 1 2 34 5 2 3 6 7 8 9 10 11 12 13 14 15 16 1 8 1 Sample (U2X = 1) 1 4 5 6 7 Figure 11-27 Sampling of Data and Parity Bit The process for detecting stop bit is like clock and data recovery process. That is, if 2 or more samples of 3 center values have high level, correct stop bit is detected, else a Frame Error flag is set. After deciding first stop bit whether a valid stop bit is received or not, the Receiver goes idle state and monitors the RXD line to check a valid high to low transition is detected (start bit detection). PS030302-0212 PRELIMINARY 102 Z51F6412 Product Specification STOP 1 RxD Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 (A) 11 (B) 12 (C) 13 Sample (U2X = 1) 1 2 3 4 5 6 7 Figure 11-28 Stop Bit Sampling and Next Start Bit Sampling 11.7.10 SPI Mode The USART can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. - Full duplex, three-wire synchronous data transfer - Master or Slave operation - Supports all four SPI modes of operation (mode0, 1, 2, and 3) - Selectable LSB first or MSB first data transfer - Double buffered transmit and receive - Programmable transmit bit rate When SPI mode is enabled (UMSEL[1:0]=3), the Slave Select (SS) pin becomes active low input in slave mode operation, or can be output in master mode operation if SPISS bit is set. Note that during SPI mode of operation, the pin RXD is renamed as MISO and TXD is renamed as MOSI for compatibility to other SPI devices. 11.7.10.1 SPI Clock formats and timing To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the USART has a clock polarity bit (UCPOL) and a clock phase control bit (UCPHA) to select one of four clock formats for data transfers. UCPOL selectively insert an inverter in series with the clock. UCPHA chooses between two different clock phase relationships between the clock and data. Note that UCPHA and UCPOL bits in UCTRLx1 register have different meanings according to the UMSEL[1:0] bits which decides the operating mode of USART. Table below shows four combinations of UCPOL and UCPHA for SPI mode 0, 1, 2, and 3. Table 11-14 CPOL Funtionality SPI Mode PS030302-0212 UCPOL UCPHA Leading Edge Trailing Edge 0 0 0 Sample (Rising) Setup (Falling) 1 0 1 Setup (Rising) Sample (Falling) 2 1 0 Sample (Falling) Setup (Rising) 3 1 1 Setup (Falling) Sample (Rising) PRELIMINARY 103 Z51F6412 Product Specification XCK (UCPOL=0) XCK (UCPOL=1) SAMPLE MOSI MSB First LSB First BIT7 BIT0 BIT6 BIT1 … … BIT2 BIT5 BIT1 BIT6 BIT0 BIT7 MISO /SS OUT (MASTER) /SS IN (SLAVE) Figure 11-29 SPI Clock Formats when UCPHA=0 When UCPHA=0, the slave begins to drive its MISO output with the first data bit value when SS goes to active low. The first XCK edge causes both the master and the slave to sample the data bit value on their MISO and MOSI inputs, respectively. At the second XCK edge, the USART shifts the second data bit value out to the MOSI and MISO outputs of the master and slave, respectively. Unlike the case of UCPHA=1, when UCPHA=0, the slave’s SS input must go to its inactive high level between transfers. This is because the slave can prepare the first data bit when it detects falling edge of SS input. PS030302-0212 PRELIMINARY 104 Z51F6412 Product Specification XCK (UCPOL=0) XCK (UCPOL=1) SAMPLE MOSI MSB First LSB First BIT7 BIT0 BIT6 BIT1 … … BIT2 BIT5 BIT1 BIT6 BIT0 BIT7 MISO /SS OUT (MASTER) /SS IN (SLAVE) Figure 11-30 SPI Clock Formats when UCPHA=1 When UCPHA=1, the slave begins to drive its MISO output when SS goes active low, but the data is not defined until the first XCK edge. The first XCK edge shifts the first bit of data from the shifter onto the MOSI output of the master and the MISO output of the slave. The next XCK edge causes both the master and slave to sample the data bit value on their MISO and MOSI inputs, respectively. At the third XCK edge, the USART shifts the second data bit value out to the MOSI and MISO output of the master and slave respectively. When UCPHA=1, the slave’s SS input is not required to go to its inactive high level between transfers. Because the SPI logic reuses the USART resources, SPI mode of operation is similar to that of synchronous or asynchronous operation. An SPI transfer is initiated by checking for the USART Data Register Empty flag (UDRE=1) and then writing a byte of data to the UDATA Register. In master mode of operation, even if transmission is not enabled (TXE=0), writing data to the UDATA register is necessary because the clock XCK is generated from transmitter block. 11.7.11 Register Map Table 11-15 Register Map Name Address Dir Default Description UCTRL01 E2H R/W 00H USART Control 1 Register 0 UCTRL02 E3H R/W 00H USART Control 2 Register 0 UCTRL03 E4H R/W 00H USART Control 3 Register 0 USTAT0 E5H R 80H USART Status Register 0 UBAUD0 E6H R/W FFH USART Baud Rate Generation Register 0 UDATA0 E7H R/W 00H USART Data Register 0 UCTRL11 FAH R/W 00H USART Control 1 Register 1 PS030302-0212 PRELIMINARY 105 Z51F6412 Product Specification UCTRL12 FBH R/W 00H USART Control 2 Register 1 UCTRL13 FCH R/W 00H USART Control 3 Register 1 USTAT1 FDH R 80H USART Status Register 1 UBAUD1 FEH R/W FFH USART Baud Rate Generation Register 1 UDATA1 FFH R/W 00H USART Data Register 1 UCTRL21 2F28H R/W 00H USART Control 1 Register 2 UCTRL22 2F29H R/W 00H USART Control 2 Register 2 UCTRL23 2F2AH R/W 00H USART Control 3 Register 2 USTAT2 2F2BH R 80H USART Status Register 2 UBAUD2 2F2CH R/W FFH USART Baud Rate Generation Register 2 UDATA2 2F2DH R/W 00H USART Data Register 2 UCTRL31 2F30H R/W 00H USART Control 1 Register 3 UCTRL32 2F31H R/W 00H USART Control 2 Register 3 UCTRL33 2F32H R/W 00H USART Control 3 Register 3 USTAT3 2F33H R 80H USART Status Register 3 UBAUD3 2F34H R/W FFH USART Baud Rate Generation Register 3 UDATA3 2F35H R/W 00H USART Data Register 3 11.7.12 USART Register description USART module consists of USART Control 1 Register (UCTRLx1), USART Control 2 Register (UCTRLx2), USART Control 3 Register (UCTRLx3), USART Status Register (USTATx), USART Data Register (UDATAx), and USART Baud Rate Generation Register (UBAUDx). 11.7.13 Register description for USART UCTRLx1 (USART Control 1 Register) : E2H, FAH, 2F28H, 2F30H 7 6 5 4 3 2 1 0 UMSEL1 UMSEL0 UPM1 UPM0 USIZE2 USIZE1 UDORD USIZE0 UCPHA UCPOL R/W R/W R/W R/W R/W R/W R/W UMSEL[1:0] Selects operation mode of USART. UMSEL1 UPM[1:0] USIZE[2:0] UMSEL0 Operation Mode 0 0 Asynchronous Mode (Uart) 0 1 Synchronous Mode 1 0 Reserved 1 1 SPI Mode Selects Parity Generation and Check methods UPM1 UPM0 0 0 No Parity 0 1 Reserved Parity 1 0 Even Parity 1 1 Odd Parity When in asynchronous or synchronous mode of operation, selects the length of data bits in frame. USIZE2 PS030302-0212 R/W Initial value : 00H USIZE1 USIZE0 PRELIMINARY Data Length 106 Z51F6412 Product Specification UDORD UCPOL UCPHA 0 0 0 5 bit 0 0 1 6 bit 0 1 0 7 bit 0 1 1 8 bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9 bit This bit is in the same bit position with USIZE1. In SPI mode, when set to one the MSB of the data byte is transmitted first. When set to zero the LSB of the data byte is transmitted first. 0 LSB First 1 MSB First Selects polarity of XCK in synchronous or spi mode 0 TXD change @Rising Edge, RXD change @Falling Edge 1 TXD change @ Falling Edge, RXD change @ Rising Edge This bit is in the same bit position with USIZE0. In SPI mode, along with UCPOL bit, selects one of two clock formats for different kinds of synchronous serial peripherals. Leading edge means first XCK edge and trailing edge means 2nd or last clock edge of XCK in one XCK pulse. And Sample means detecting of incoming receive bit, Setup means preparing transmit data. UCPOL UCPHA Leading Edge Trailing Edge 0 0 Sample (Rising) Setup (Falling) 0 1 Setup (Rising) Sample (Falling) 1 0 Sample (Falling) Setup (Rising) 1 1 Setup (Falling) Sample (Rising) UCTRLx2 (USART Control 2 Register) : E3H, FBH, 2F29H, 2F31H 7 6 5 4 3 2 1 0 UDRIE TXCIE RXCIE WAKEIE TXE RXE USARTEN U2X R/W R/W R/W R/W R/W R/W R/W UDRIE TXCIE RXCIE WAKEIE TXE PS030302-0212 R/W Initial value : 00H Interrupt enable bit for USART Data Register Empty. 0 Interrupt from UDRE is inhibited (use polling) 1 When UDRE is set, request an interrupt Interrupt enable bit for Transmit Complete. 0 Interrupt from TXC is inhibited (use polling) 1 When TXC is set, request an interrupt Interrupt enable bit for Receive Complete 0 Interrupt from RXC is inhibited (use polling) 1 When RXC is set, request an interrupt Interrupt enable bit for Asynchronous Wake in STOP mode. When device is in stop mode, if RXD goes to LOW level an interrupt can be requested to wake-up system. 0 Interrupt from Wake is inhibited 1 When WAKE is set, request an interrupt Enables the transmitter unit. 0 Transmitter is disabled 1 Transmitter is enabled PRELIMINARY 107 Z51F6412 Product Specification RXE Enables the receiver unit. USARTEN U2X 0 Receiver is disabled 1 Receiver is enabled Activate USART module by supplying clock. 0 USART is disabled (clock is halted) 1 USART is enabled This bit only has effect for the asynchronous operation and selects receiver sampling rate. 0 Normal asynchronous operation 1 Double Speed asynchronous operation UCTRLx3 (USART Control 3 Register) : E4H, FCH, 2F2AH, 2F32H ,7 6 5 4 3 2 1 0 MASTER LOOPS DISXCK SPISS - USBS TX8 RX8 R/W R/W R/W R/W - R/W R/W MASTER LOOPS DISXCK SPISS USBS TX8 R/W Initial value : 00H Selects master or slave in SPI or Synchronous mode operation and controls the direction of XCK pin. 0 Slave mode operation and XCK is input pin. 1 Master mode operation and XCK is output pin Controls the Loop Back mode of USART, for test mode 0 Normal operation 1 Loop Back mode In Synchronous mode of operation, selects the waveform of XCK output. 0 XCK is free-running while USART is enabled in synchronous master mode. 1 XCK is active while any frame is on transferring. Controls the functionality of SS pin in master SPI mode. 0 SS pin is normal GPIO or other primary function 1 SS output to other slave device Selects the length of stop bit in Asynchronous or Synchronous mode of operation. 0 1 Stop Bit 1 2 Stop Bit The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write this bit first before loading the UDATA register. RX8 0 MSB (9th bit) to be transmitted is ‘0’ 1 MSB (9th bit) to be transmitted is ‘1’ The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read this bit first before reading the receive buffer. th 0 MSB (9 bit) received is ‘0’ 1 MSB (9th bit) received is ‘1’ USTATx (USART Status Register) : E5H, FDH, 2F2BH, 2F33H 7 6 5 4 3 2 1 0 UDRE TXC RXC WAKE SOFTRST DOR FE PE R/W R/W R/W R/W R/W R R PS030302-0212 PRELIMINARY R Initial value : 80H 108 Z51F6412 Product Specification UDRE TXC The UDRE flag indicates if the transmit buffer (UDATA) is ready to receive new data. If UDRE is ‘1’, the buffer is empty and ready to be written. This flag can generate a UDRE interrupt. 0 Transmit buffer is not empty. 1 Transmit buffer is empty. This flag is set when the entire frame in the transmit shift register has been shifted out and there is no new data currently present in the transmit buffer. This flag is automatically cleared when the interrupt service routine of a TXC interrupt is executed. This flag can generate a TXC interrupt. RXC 0 Transmission is ongoing. 1 Transmit buffer is empty and the data in transmit shift register are shifted out completely. This flag is set when there are unread data in the receive buffer and cleared when all the data in the receive buffer are read. The RXC flag can be used to generate a RXC interrupt. WAKE SOFTRST DOR 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer This flag is set when the RX pin is detected low while the CPU is in stop mode. This flag can be used to generate a WAKE interrupt. This bit is set only when in asynchronous mode of operation. 0 No WAKE interrupt is generated. 1 WAKE interrupt is generated This is an internal reset and only has effect on USART. Writing ‘1’ to this bit initializes the internal logic of USART and is auto cleared. 0 No operation 1 Reset USART This bit is set if a Data OverRun occurs. While this bit is set, the incoming data frame is ignored. This flag is valid until the receive buffer is read. FE 0 No Data OverRun 1 Data OverRun detected This bit is set if the first stop bit of next character in the receive buffer is detected as ‘0’. This bit is valid until the receive buffer is read. PE 0 No Frame Error 1 Frame Error detected This bit is set if the next character in the receive buffer has a Parity Error when received while Parity Checking is enabled. This bit is valid until the receive buffer is read. 0 No Parity Error 1 Parity Error detected UBAUDx(USART Baud-Rate Generation Register) : E6H, FEH, 2F2CH, 2F34H 7 6 5 4 3 2 1 0 UBAUD7 UBAUD6 UBAUD5 UBAUD4 UBAUD3 UBAUD2 UBAUD1 UBAUD0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH UBAUD [7:0] The value in this register is used to generate internal baud rate in asynchronous mode or to generate XCK clock in synchronous or spi mode. To prevent malfunction, do not write ‘0’ in asynchronous mode, and do not write ‘0’ or ‘1’ in synchronous or spi mode. UDATAx (USART Data Register) : E7H, FFH, 2F2DH, 2F35H PS030302-0212 PRELIMINARY 109 Z51F6412 Product Specification 7 6 5 4 3 2 1 0 UDATA7 UDATA6 UDATA5 UDATA4 UDATA3 UDATA2 UDATA1 UDATA0 R/W R/W R/W R/W R/W R/W R/W UDATA [7:0] PS030302-0212 R/W Initial value : 00H The USART Transmit Buffer and Receive Buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the UDATA register. Reading the UDATA register returns the contents of the Receive Buffer. Write this register only when the UDRE flag is set. In spi or synchronous master mode, write this register even if TX is not enabled to generate clock, XCK. PRELIMINARY 110 Z51F6412 Product Specification 11.7.14 Baud Rate setting (example) Table 11-16 Examples of UBAUD Settings for Commonly Used Oscillator Frequencies fOSC=1.00MHz Baud Rate U2X=0 fOSC=1.8432MHz U2X=1 U2X=0 fOSC=2.00MHz U2X=1 U2X=0 U2X=1 UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 ERROR 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4K 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2K 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8K 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4K 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6K - - 1 8.5% 1 -25.0% 3 0.0% 1 8.5% 3 8.5% 76.8K - - 1 -18.6% 1 0.0% 2 0.0% 1 -18.6% 2 8.5% 115.2 K - - - - - - 1 0.0% - - 1 8.5% 230.4 K - - - - - - - - - - - - fOSC=3.6864MHz Baud Rate U2X=0 fOSC=4.00MHz U2X=1 U2X=0 fOSC=7.3728MHz U2X=1 U2X=0 U2X=1 UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% - ERROR - 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4K 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2K 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.8K 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4K 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6K 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8K 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2K 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4K - - 1 0.0% - - 1 8.5% 1 0.0% 3 0.0% 250K - - 1 -7.8% - - 1 0.0% 1 -7.8% 3 -7.8% 0.5M - - - - - - - - - - 1 -7.8% fOSC=8.00MHz Baud Rate U2X=0 fOSC=11.0592MHz U2X=1 U2X=0 fOSC=14.7456MHz U2X=1 U2X=0 U2X=1 UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD 2400 207 0.2% - - - - - - - - - ERROR - 4800 103 0.2% 207 0.2% 143 0.0% - - 191 0.0% - - 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4K 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2K 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0% 28.8K 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0% 38.4K 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0% 57.6K 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0% 76.8K 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0% 115.2K 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0% 230.4K 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0% 250K 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3% 0.5M - - 1 0.0% - - 2 -7.8% 1 -7.8% 3 -7.8% 1M - - - - - - - - - - 1 -7.8% PS030302-0212 PRELIMINARY 111 Z51F6412 Product Specification 11.8 SPI 11.8.1 Overview There is Serial Peripheral Interface (SPI) one channel in the Z51F6412 MCU. The SPI allows synchronous serial data transfer between the external serial devices. It can do Full-duplex communication by 4-wire (MOSI, MISO, SCK, SS), support Master/Slave mode, can select serial clock (SCK) polarity, phase and whether LSB first data transfer or MSB first data transfer. 11.8.2 Block Diagram fSCLK ÷2 P r e s c a l e r SPIEN ÷4 ÷8 ÷16 MUX ÷32 Edge Detector MUX ÷64 SPI Control Circuit ÷128 CPOL CPHA TCIR MS 3 SPI Interrupt Clear SPICR[2:0] MS INT_ACK SCK Control SCK WCOL FLSB MISO 8bit Shift Register MUX MS SPIDR (8Bit) DEP SS Control SS 8 FLSB MOSI PxDA[x] MS PxIO[x] Internal Bus Line SPICRx SPIEN SPISRx TCIR FLSB MS WCOL SS_HIGH CPOL CPHA - - DSCR SCR1 SCR0 SSENA TXENA RXENA ADDRESS : D2H , 92H INITIAL VALUE : 0000_0000B ADDRESS : D4H , F1H INITIAL VALUE : 00--_-000B Figure 11-31 SPI Block Diagram PS030302-0212 PRELIMINARY 112 Z51F6412 Product Specification 11.8.3 Data Transmit / Receive Operation User can use SPI for serial data communication by following step 1. Select SPI operation mode(master/slave, polarity, phase) by control register SPICR. 2. When the SPI is configured as a Master, it selects a Slave by SS signal (active low). When the SPI is configured as a Slave, it is selected by SS signal incoming from Master 3. When the user writes a byte to the data register SPIDRx, SPI will start an operation. 4. In this time, if the SPI is configured as a Master, serial clock will come out of SCK pin. And Master shifts the eight bits into the Slave (transmit), Slave shifts the eight bits into the Master at the same time (receive). If the SPI is configured as a Slave, serial clock will come into SCK pin. And Slave shifts the eight bits into the Master (transmit), Master shifts the eight bits into the Slave at the same time (receive). 5. When transmit/receive is done, TCIR (Transmit Complete or Interrupt Request) bit will be set. If the SPI interrupt is enabled, an interrupt is requested. And TCIR bit is cleared by hardware when executing the corresponding interrupt. If SPI interrupt is disable, TCIR bit is cleared when user read the status register SPISRx, and then access (read/write) the data register SPIDR. Note) If you want to use both transmit and receive, set the TXENA, RXENA bit of SPISR, and if user want to use only either transmit or receive, clear the TXENA or RXENA. In this case, user can use disabled pin by GPIO freely. 11.8.4 SS pin function 1. When the SPI is configured as a Slave, the SS pin is always input. If LOW signal come into SS pin, the SPI logic is active. And if ‘HIGH’ signal come into SS pin, the SPI logic is stop. In this time, SPI logic will be reset, and invalidated any received data. 2. When the SPI is configured as a Master, the user can select the direction of the SS pin by port direction register (PxIO[x]). If the SS pin is configured as an output, user can use general GPIO output mode. If the SS pin is configured as an input, ‘HIGH’ signal must come into SS pin to guarantee Master operation. If ‘LOW’ signal come into SS pin, the SPI logic interprets this as another master selecting the SPI as a slave and starting to send data to it. To avoid bus contention, MS bit of SPICR will be cleared and the SPI becomes a Slave and then, TCIR bit of SPISR will be set, and if the SPI interrupt is enabled, an interrupt is requested. Note) - When the SS pin is configured as an output at Master mode, SS pin’s output value is defined by user’s software (PxDA[x]). Before SPICRx setting, the direction of SS pin must be defined - If you don’t need to use SS pin, clear the SSENA bit of SPISR. So, you can use disabled pin by GPIO freely. In this case, SS signal is driven by ‘HIGH’ or ‘LOW’ internally. In other words, master is ‘HIGH’, salve is ‘LOW’ - When SS pin is configured as input(master or slave), if ‘HIGH’ signal come into SS pin, this flag bit will be set at the SS rising time. And you can clear it by writing ‘0’. PS030302-0212 PRELIMINARY 113 Z51F6412 Product Specification 11.8.5 Timing Waveform SCKx (CPOL=0) SCKx (CPOL=1) MISOx/MOSIx (Output) D0 D1 D2 D3 D4 D5 D6 D7 MOSxI/MISOx (Input) D0 D1 D2 D3 D4 D5 D6 D7 SSx TCIR SS_HIGH Figure 11-32 SPI Transmit/Receive Timing Diagram at CPHA = 0 SCKx (CPOL=0) SCKx (CPOL=1) MISOx/MOSIx (Output) D0 D1 D2 D3 D4 D5 D6 D7 MOSIx/MISOx (Input) D0 D1 D2 D3 D4 D5 D6 D7 SSx TCIR SS_HIGH Figure 11-33 SPI Transmit/Receive Timing Diagram at CPHA = 1 11.8.6 Register Map Table 11-17 Register Map Name SPICR0 Address D2H Dir R/W Default 0H Description SPI Control Register 0 SPIDR0 D3H R/W 0H SPI Data Register 0 SPISR0 D4H - 0H SPI Status Register 0 SPICR1 92H R/W 0H SPI Control Register 1 SPIDR1 93H R/W 0H SPI Data Register 1 SPISR1 F1H - 0H SPI Status Register 1 PS030302-0212 PRELIMINARY 114 Z51F6412 Product Specification 11.8.7 SPI Register description The SPI Register consists of SPI Control Register (SPICRx), SPI Status Register (SPISRx) and SPI Data Register (SPIDRx) 11.8.8 Register description for SPI SPICRx (SPI Control Register) : D2H, 92H 7 6 5 4 3 2 1 0 SPIEN R/W FLSB MS CPOL CPHA DSCR SCR1 SCR0 R/W R/W R/W R/W R/W R/W SPIEN FLSB MS CPOL CPHA DSCR SCR[2:0] This bit controls the SPI operation 0 SPI Disable 1 SPI Enable This bit selects the data transmission sequence 0 MSB First 1 LSB First This bit selects whether Master or Slave mode 0 Slave mode 1 Master mode These two bits control the serial clock (SCK) mode Clock Polarity (CPOL) bit determine SCK’s value at idle mode Clock Phase (CPHA) bit determine if data is sampled on the leading or trailing edge of SCK. Refer to Figure 11-32, Figure 11-33 CPOL CPHA Leading Edge 0 0 Sample (Rising) Setup (Falling) 0 1 Setup (Rising) Sample (Falling) Trailing Edge 1 0 Sample (Falling) Setup (Rising) 1 1 Setup (Falling) Sample (Rising) These three bits select the SCK rate of the device configured as a Master. When DSCR bit is written one, SCK will be doubled in Master mode. fx– Main system clock oscillation frequency. DSCR PS030302-0212 R/W Initial value : 00H SCR1 SCR0 SCK frequency 0 0 0 fx/4 0 0 1 fx/16 0 1 0 fx/64 0 1 1 fx/128 1 0 0 fx/2 1 0 1 fx/8 1 1 0 fx/32 1 1 1 fx/64 PRELIMINARY 115 Z51F6412 Product Specification SPIDRx (SPI Data Register) : D3H, 93H 7 6 5 4 3 2 1 0 SPIDR7 SPIDR6 SPIDR5 SPIDR4 SPIDR3 SPIDR2 SPIDR1 SPIDR0 R/W R/W R/W R/W R/W R/W R/W SPIDR [7:0] R/W Initial value : 00H SPI data register. Although you only use reception, user must write any data in here to start the SPI operation. SPISRx (SPI Status Register) : D4H, F1H 7 6 5 4 3 2 1 0 TCIR WCOL SS_HIGH - - SSENA TXENA RXENA R R R/W - - R/W R/W TCIR WCOL SS_HIGH SSENA TXENA RXENA PS030302-0212 R/W Initial value : 00H When a serial data transmission is complete, the TCIR bit is set. If the SPI interrupt is enabled, an interrupt is requested. And TCIR bit is cleared by hardware when executing the corresponding interrupt. If SPI interrupt is disable, TCIR bit is cleared when user read the status register SPISR, and then access (read/write) the data register SPIDR. 0 Interrupt cleared 1 Transmission Complete and Interrupt Requested This bit is set if the data register SPIDR is written during a data transfer. This bit is cleared when user read the status register SPISR, and then access (read/write) the data register SPIDR. 0 No collision 1 Write Collision When SS pin is configured as input(master or slave), if ‘HIGH’ signal come into SS pin, this flag bit will be set at the SS rising time. And you can clear it by writing ‘0’. You can write only zero. 0 Flag is cleared 1 Flag is set This bit controls the SS pin operation 0 Disable 1 Enable This bit controls a data transfer operation 0 Disable 1 Enable This bit controls a data reception operation 0 Disable 1 Enable PRELIMINARY 116 Z51F6412 Product Specification 11.9 I2C 11.9.1 Overview The I2C is one of industrial standard serial communication protocols, and which uses 2 bus lines Serial Data Line (SDA) and Serial Clock Line (SCL) to exchange data. Because both SDA and SCL lines are open-drain output, each line needs pull-up resistor. The features are as shown below. - Compatible with I2C bus standard - Multi-master operation - Up to 400 KHz data transfer speed - 7 bit address - Support 2 slave addresses - Both master and slave operation - Bus busy detection 11.9.2 Block Diagram Slave Addr. Register (I2CSAR) Debounce enable SDA Noise Canceller (debounce) 1 Slave Addr. Register1 (I2CSAR1) SDAIN 0 SDAOUT Debounce enable SCL Noise Canceller (debounce) F/F 8-bit Shift Register (SHFTR) SDA Out Controller Data Out Register (I2CDR) SCL High Period Register (I2CSCLHR) SCLIN SCL Out Controller 1 0 SCL Low Period Register (I2CSCLLR) I n t e r n a l B u s L i n e SDA Hold Time Register (I2CDAHR) SCLOUT Figure 11-34 I2C Block Diagram 11.9.3 I2C Bit Transfer The data on the SDA line must be stable during HIGH period of the clock, SCL. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. The exceptions are START(S), repeated START(Sr) and STOP(P) condition where data line changes when clock line is high. PS030302-0212 PRELIMINARY 117 Z51F6412 Product Specification SDA SCL Data line Stable: Data valid exept S, Sr, P Change of Data allowed 2 Figure 11-35 Bit Transfer on the I C-Bus 11.9.4 Start / Repeated Start / Stop One master can issue a START (S) condition to notice other devices connected to the SCL, SDA lines that it will use the bus. A STOP (P) condition is generated by the master to release the bus lines so that other devices can use it. A high to low transition on the SDA line while SCL is high defines a START (S) condition. A low to high transition on the SDA line while SCL is high defines a STOP (P) condition. START and STOP conditions are always generated by the master. The bus is considered to be busy after START condition. The bus is considered to be free again after STOP condition, ie, the bus is busy between START and STOP condition. If a repeated START condition (Sr) is generated instead of STOP condition, the bus stays busy. So, the START and repeated START conditions are functionally identical. SDA SCL S P START Condition STOP Condition Figure 11-36 START and STOP Condition 11.9.5 Data Transfer Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unlimited. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. If a slave can’t receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL LOW to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL. PS030302-0212 PRELIMINARY 118 Z51F6412 Product Specification P SDA MSB Acknowledgement Signal form Slave S or Sr 1 Sr Clock line held low while interrupts are served. Byte Complete, Interrupt within Device SCL Acknowledgement Signal form Slave 9 1 ACK 9 Sr or P ACK START or Repeated START Condition STOP or Repeated START Condition Figure 11-37 Data Transfer on the I2C-Bus 11.9.6 Acknowledge The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. When a slave is addressed by a master (Address Packet), and if it is unable to receive or transmit because it’s performing some real time function, the data line must be left HIGH by the slave. And also, when a slave addressed by a master is unable to receive more data bits, the slave receiver must release the SDA line (Data Packet). The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. If a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave transmitter must release the data line to allow the master to generate a STOP or repeated START condition. Data Output By Transmitter NACK Data Output By Receiver SCL From MASTER ACK 1 2 8 9 Clock pulse for ACK 2 Figure 11-38 Acknowledge on the I C-Bus 11.9.7 Synchronization / Arbitration Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and it will hold the SCL line in that state until the clock HIGH state is reached. However the LOW to HIGH transition of this clock may not change the state of the SCL line if another clock is still within its LOW period. In this way, a synchronized SCL clock is generated PS030302-0212 PRELIMINARY 119 Z51F6412 Product Specification with its LOW period determined by the device with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period. A master may start a transfer only if the bus is free. Two or more masters may generate a START condition. Arbitration takes place on the SDA line, while the SCL line is at the HIGH level, in such a way that the master which transmits a HIGH level, while another master is transmitting a LOW level will switch off its DATA output state because the level on the bus doesn’t correspond to its own level. Arbitration continues for many bits until a winning master gets the ownership of I2C bus. Its first stage is comparison of the address bits. Wait High Counting Start High Counting Fast Device SCLOUT High Counter Reset Slow Device SCLOUT SCL Figure 11-39 Clock Synchronization during Arbitration Procedure Arbitration Process not adaped Device 1 loses Arbitration Device1 outputs High Device1 DataOut Device2 DataOut SDA on BUS SCL on BUS S Figure 11-40 Arbitration Procedure of Two Masters 11.9.8 Operation The I2C is byte-oriented and interrupt based. Interrupts are issued after all bus events except for a transmission of a START condition. Because the I2C is interrupt based, the application software is free to carry on other operations during a I2C byte transfer. Note that when a I2C interrupt is generated, IIF flag in I2CMR register is set, it is cleared by writing an arbitrary value to I2CSR. When I2C interrupt occurs, the SCL line is hold LOW until writing any PS030302-0212 PRELIMINARY 120 Z51F6412 Product Specification value to I2CSR. When the IIF flag is set, the I2CSR contains a value indicating the current state of the I2C bus. According to the value in I2CSR, software can decide what to do next. I2C can operate in 4 modes by configuring master/slave, transmitter/receiver. The operating mode is configured by a winning master. A more detailed explanation follows below. 11.9.8.1 Master Transmitter To operate I2C in master transmitter, follow the recommended steps below. 1. Enable I2C by setting IICEN bit in I2CMR. This provides main clock to the peripheral. 2. Load SLA+W into the I2CDR where SLA is address of slave device and W is transfer direction from the viewpoint of the master. For master transmitter, W is ‘0’. Note that I2CDR is used for both address and data. 3. Configure baud rate by writing desired value to both I2CSCLLR and I2CSCLHR for the Low and High period of SCL line. 4. Configure the I2CSDAHR to decide when SDA changes value from falling edge of SCL. If SDA should change in the middle of SCL LOW period, load half the value of I2CSCLLR to the I2CSDAHR. 5. Set the START bit in I2CMR. This transmits a START condition. And also configure how to handle interrupt and ACK signal. When the START bit is set, 8-bit data in I2CDR is transmitted out according to the baud-rate. 6. This is ACK signal processing stage for address packet transmitted by master. When 7-bit address and 1-bit transfer direction is transmitted to target slave device, the master can know whether the slave acknowledged or not in the 9th high period of SCL. If the master gains bus mastership, I2C generates GCALL interrupt regardless of the reception of ACK from the slave device. When I2C loses bus mastership during arbitration process, the MLOST bit in I2CSR is set, and I2C waits in idle state or can be operate as an addressed slave. To operate as a slave when the MLSOT bit in I2CSR is set, the ACKEN bit in I2CMR must be set and the received 7-bit address must equal to the SLA bits in I2CSAR. In this case I2C operates as a slave transmitter or a slave receiver (go to appropriate section). In this stage, I2C holds the SCL LOW. This is because to decide whether I2C continues serial transfer or stops communication. The following steps continue assuming that I2C does not lose mastership during first data transfer. I2C (Master) can choose one of the following cases regardless of the reception of ACK signal from slave. 1) Master receives ACK signal from slave, so continues data transfer because slave can receive more data from master. In this case, load data to transmit to I2CDR. 2) Master stops data transfer even if it receives ACK signal from slave. In this case, set the STOP bit in I2CMR. 3) Master transmits repeated START condition with not checking ACK signal. In this case, load SLA+R/W into the I2CDR and set START bit in I2CMR. After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of 3), move to step 6 after transmitting the data in I2CDR and if transfer direction bit is ‘1’ go to master receiver section. 7. 1-Byte of data is being transmitted. During data transfer, bus arbitration continues. 8. This is ACK signal processing stage for data packet transmitted by master. I2C holds the SCL LOW. When I2C loses bus mastership while transmitting data arbitrating other masters, the MLOST bit in I2CSR is set. If then, I2C waits in idle state. When the data in I2CDR is 2 transmitted completely, I C generates TEND interrupt. I2C can choose one of the following cases regardless of the reception of ACK signal from slave. PS030302-0212 PRELIMINARY 121 Z51F6412 Product Specification 1) Master receives ACK signal from slave, so continues data transfer because slave can receive more data from master. In this case, load data to transmit to I2CDR. 2) Master stops data transfer even if it receives ACK signal from slave. In this case, set the STOP bit in I2CMR. 3) Master transmits repeated START condition with not checking ACK signal. In this case, load SLA+R/W into the I2CDR and set the START bit in I2CMR. After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of 3), move to step 6 after transmitting the data in I2CDR, and if transfer direction bit is ‘1’ go to master receiver section. 9. This is the final step for master transmitter function of I2C, handling STOP interrupt. The STOP bit indicates that data transfer between master and slave is over. To clear I2CSR, write arbitrary value to I2CSR. After this, I2C enters idle state. PS030302-0212 PRELIMINARY 122 Z51F6412 Product Specification The next figure depicts above process for master transmitter operation of I2C. Master Receiver S or Sr SLA+R SLA+W ACK 0x87 DATA ACK Rs N Lost? Cont? 0x47 N STOP 0x46 P 0x0E Y STOP 0x22 LOST LOST LOST& 0x0F 0x1D 0x1F Slave Receiver (0x1D) or Transmitter (0x1F) 0x22 STOP P 0x0E Y Y 0x86 N LOST Other master continues Y From master to slave / Master command or Data Write 0x0F From slave to master STOP 0x22 P 0xxx Value of Status Register ACK Interrupt, SCL line is held low P Interrupt after stop command LOST& Arbitration lost as master and addressed as slave Figure 11-41 Formats and States in the Master Transmitter Mode PS030302-0212 PRELIMINARY 123 Z51F6412 Product Specification 11.9.8.2 Master Receiver To operate I2C in master receiver, follow the recommended steps below. 1. Enable I2C by setting IICEN bit in I2CMR. This provides main clock to the peripheral. 2. Load SLA+R into the I2CDR where SLA is address of slave device and R is transfer direction from the viewpoint of the master. For master receiver, R is ‘1’. Note that I2CDR is used for both address and data. 3. Configure baud rate by writing desired value to both I2CSCLLR and I2CSCLHR for the Low and High period of SCL line. 4. Configure the I2CSDAHR to decide when SDA changes value from falling edge of SCL. If SDA should change in the middle of SCL LOW period, load half the value of I2CSCLLR to the I2CSDAHR. 5. Set the START bit in I2CMR. This transmits a START condition. And also configure how to handle interrupt and ACK signal. When the START bit is set, 8-bit data in I2CDR is transmitted out according to the baud-rate. 6. This is ACK signal processing stage for address packet transmitted by master. When 7-bit address and 1-bit transfer direction is transmitted to target slave device, the master can know th whether the slave acknowledged or not in the 9 high period of SCL. If the master gains bus 2 mastership, I C generates GCALL interrupt regardless of the reception of ACK from the slave device. When I2C loses bus mastership during arbitration process, the MLOST bit in I2CSR is set, and I2C waits in idle state or can be operate as an addressed slave. To operate as a slave when the MLSOT bit in I2CSR is set, the ACKEN bit in I2CMR must be set and the received 7-bit address must equal to the SLA bits in I2CSAR. In this case I2C operates as a 2 slave transmitter or a slave receiver (go to appropriate section). In this stage, I C holds the 2 SCL LOW. This is because to decide whether I C continues serial transfer or stops communication. The following steps continue assuming that I2C does not lose mastership during first data transfer. I2C (Master) can choose one of the following cases according to the reception of ACK signal from slave. 1) Master receives ACK signal from slave, so continues data transfer because slave can prepare and transmit more data to master. Configure ACKEN bit in I2CMR to decide whether I2C ACKnowledges the next data to be received or not. 2) Master stops data transfer because it receives no ACK signal from slave. In this case, set the STOP bit in I2CMR. 3) Master transmits repeated START condition due to no ACK signal from slave. In this case, load SLA+R/W into the I2CDR and set START bit in I2CMR. After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of 3), move to step 6 after transmitting the data in I2CDR and if transfer direction bit is ‘0’ go to master transmitter section. 7. 1-Byte of data is being received. 8. This is ACK signal processing stage for data packet transmitted by slave. I2C holds the SCL LOW. When 1-Byte of data is received completely, I2C generates TEND interrupt. I2C can choose one of the following cases according to the RXACK flag in I2CSR. 1) Master continues receiving data from slave. To do this, set ACKEN bit in I2CMR to ACKnowledge the next data to be received. 2) Master wants to terminate data transfer when it receives next data by not generating ACK signal. This can be done by clearing ACKEN bit in I2CMR. 3) Because no ACK signal is detected, master terminates data transfer. In this case, set the STOP bit in I2CMR. 4) No ACK signal is detected, and master transmits repeated START condition. In this case, PS030302-0212 PRELIMINARY 124 Z51F6412 Product Specification load SLA+R/W into the I2CDR and set the START bit in I2CMR. After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In case of 1) and 2), move to step 7. In case of 3), move to step 9 to handle STOP interrupt. In case of 4), move to step 6 after transmitting the data in I2CDR, and if transfer direction bit is ‘0’ go to master transmitter section. 9. This is the final step for master receiver function of I2C, handling STOP interrupt. The STOP bit indicates that data transfer between master and slave is over. To clear I2CSR, write arbitrary value to I2CSR. After this, I2C enters idle state. The processes described above for master receiver operation of I2C can be depicted as the following figure. Master Transmitter S or Sr SLA+W SLA+R ACK 0x85 DATA 0x84 N 0x20 STOP P 0x0C Y LOST Rs LOST LOST& 0x0D 0x1D 0x1F Slave Receiver (0x1D) or Transmitter (0x1F) 0x44 Sr ACK 0x45 0xxx Y N 0x44 0x20 STOP P 0x0C LOST Other master continues From master to slave / Master command or Data Write ACK From slave to master ACK Value of Status Register Interrupt, SCL line is held low P Interrupt after stop command LOST& Arbitration lost as master and addressed as slave Figure 11-42 Formats and States in the Master Receiver Mode PS030302-0212 PRELIMINARY 125 Z51F6412 Product Specification 11.9.8.3 Slave Transmitter To operate I2C in slave transmitter, follow the recommended steps below. 1. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00 into I2CSDAHR to make SDA change within one system clock period from the falling edge of SCL. Note that the hold time of SDA is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from I2CSDAHR. When the hold time of SDA is longer than the period of SCLK, I2C (slave) cannot transmit serial data properly. 2. Enable I2C by setting IICEN bit and INTEN bit in I2CMR. This provides main clock to the peripheral. 3. When a START condition is detected, I2C receives one byte of data and compares it with SLA bits in I2CSAR. If the GCALLEN bit in I2CSAR is enabled, I2C compares the received data with value 0x00, the general call address. 4. If the received address does not equal to SLA bits in I2CSAR, I2C enters idle state ie, waits for another START condition. Else if the address equals to SLA bits and the ACKEN bit is enabled, I2C generates SSEL interrupt and the SCL line is held LOW. Note that even if the address equals to SLA bits, when the ACKEN bit is disabled, I2C enters idle state. When SSEL interrupt occurs, load transmit data to I2CDR and write arbitrary value to I2CSR to release SCL line. 5. 1-Byte of data is being transmitted. 6. In this step, I2C generates TEND interrupt and holds the SCL line LOW regardless of the reception of ACK signal from master. Slave can select one of the following cases. 2 1) No ACK signal is detected and I C waits STOP or repeated START condition. 2) ACK signal from master is detected. Load data to transmit into I2CDR. After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In case of 1) move to step 7 to terminate communication. In case of 2) move to step 5. In either case, a repeated START condition can be detected. For that case, move step 4. 7. This is the final step for slave transmitter function of I2C, handling STOP interrupt. The STOP bit indicates that data transfer between master and slave is over. To clear I2CSR, write arbitrary value to I2CSR. After this, I2C enters idle state. PS030302-0212 PRELIMINARY 126 Z51F6412 Product Specification The next figure shows flow chart for handling slave transmitter function of I2C. IDLE S or Sr SLA+R GCALL 0x97 0x1F ACK LOST& Y 0x17 DATA Y 0x47 ACK Y STOP P 0x46 From master to slave / Master command or Data Write From slave to master 0xxx 0x22 N Value of Status Register IDLE ACK Interrupt, SCL line is held low P Interrupt after stop command LOST& Arbitration lost as master and addressed as slave GCALL General Call Address Figure 11-43 Formats and States in the Slave Transmitter Mode PS030302-0212 PRELIMINARY 127 Z51F6412 Product Specification 11.9.8.4 Slave Receiver To operate I2C in slave receiver, follow the recommended steps below. 1. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00 into I2CSDAHR to make SDA change within one system clock period from the falling edge of SCL. Note that the hold time of SDA is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from I2CSDAHR. When the hold time of SDA is longer than the period of SCLK, I2C (slave) cannot transmit serial data properly. 2. Enable I2C by setting IICEN bit and INTEN bit in I2CMR. This provides main clock to the peripheral. 3. When a START condition is detected, I2C receives one byte of data and compares it with SLA bits in I2CSAR. If the GCALLEN bit in I2CSAR is enabled, I2C compares the received data with value 0x00, the general call address. 4. If the received address does not equal to SLA bits in I2CSAR, I2C enters idle state ie, waits for another START condition. Else if the address equals to SLA bits and the ACKEN bit is enabled, I2C generates SSEL interrupt and the SCL line is held LOW. Note that even if the address equals to SLA bits, when the ACKEN bit is disabled, I2C enters idle state. When SSEL interrupt occurs and I2C is ready to receive data, write arbitrary value to I2CSR to release SCL line. 5. 1-Byte of data is being received. 2 6. In this step, I C generates TEND interrupt and holds the SCL line LOW regardless of the reception of ACK signal from master. Slave can select one of the following cases. 2 1) No ACK signal is detected (ACKEN=0) and I C waits STOP or repeated START condition. 2) ACK signal is detected (ACKEN=1) and I2C can continue to receive data from master. After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In case of 1) move to step 7 to terminate communication. In case of 2) move to step 5. In either case, a repeated START condition can be detected. For that case, move step 4. 7. This is the final step for slave receiver function of I2C, handling STOP interrupt. The STOP bit indicates that data transfer between master and slave is over. To clear I2CSR, write arbitrary value to I2CSR. After this, I2C enters idle state. The process can be depicted as following figure when I2C operates in slave receiver mode. PS030302-0212 PRELIMINARY 128 Z51F6412 Product Specification IDLE S or Sr SLA+W GCALL 0x95 0x1D ACK LOST& N Y 0x15 DATA Y 0x45 ACK 0x20 N STOP 0x44 Y IDLE From master to slave / Master command or Data Write From slave to master 0xxx P Value of Status Register ACK Interrupt, SCL line is held low P Interrupt after stop command LOST& Arbitration lost as master and addressed as slave GCALL General Call Address Figure 11-44 Formats and States in the Slave Receiver Mode 11.9.9 Register Map Name Address Dir Default Description 2 I2CMR DAH R/W 00H I C Mode Control Register I2CSR DBH R 00H I C Status Register I2CSCLLR DCH R/W 3FH SCL Low Period Register 2 I2CSCLHR DDH R/W 3FH SCL High Period Register I2CSDAHR DEH R/W 01H SDA Hold Time Register I2CDR DFH R/W FFH I2C Data Register I2CSAR D7H R/W 00H I C Slave Address Register I2CSAR1 D6H R/W 00H I2C Slave Address Register 1 PS030302-0212 2 PRELIMINARY 129 Z51F6412 Product Specification 2 11.9.10 I C Register description I2C Registers are composed of I2C Mode Control Register (I2CMR), I2C Status Register (I2CSR), SCL Low Period Register (I2CSCLLR), SCL High Period Register (I2CSCLHR), SDA Hold Time Register (I2CSDAHR), I2C Data Register (I2CDR), and I2C Slave Address Register (I2CSAR). 11.9.11 Register description for I2C I2CMR (I2C Mode Control Register) : DAH 7 6 5 4 3 2 1 0 IIF IICEN RESET INTEN ACKEN MASTER STOP START R/W R/W R/W R/W R/W R R/W IIF This is interrupt flag bit. 0 No interrupt is generated or interrupt is cleared 1 IICEN RESET INTEN ACKEN MASTER STOP An interrupt is generated 2 Enable I C Function Block (by providing clock) 0 I2C is inactive 1 I2C is active 2 Initialize internal registers of I C. 0 No operation 1 Initialize I C, auto cleared 2 2 Enable interrupt generation of I C. 0 Disable interrupt, operates in polling mode 1 Enable interrupt Controls ACK signal generation at ninth SCL period. Note) ACK signal is output (SDA=0) for the following 3 cases. When received address packet equals to SLA bits in I2CSAR When received address packet equals to value 0x00 with GCALL enabled When I2C operates as a receiver (master or slave) 0 No ACK signal is generated (SDA=1) 1 ACK signal is generated (SDA=0) 2 Represent operating mode of I C 2 0 I C is in slave mode 1 I2C is in master mode When I2C is master, generates STOP condition. 0 No operation 1 START PS030302-0212 R/W Initial value : 00H STOP condition is to be generated 2 When I C is master, generates START condition. 0 No operation 1 START or repeated START condition is to be generated PRELIMINARY 130 Z51F6412 Product Specification 2 I2CSR (I C Status Register) : DBH 7 6 5 4 3 2 1 0 GCALL TEND STOP SSEL MLOST BUSY TMODE RXACK R R R R R R R GCALL 2 This bit has different meaning depending on whether I C is master or slave. Note 1) When I2C is a master, this bit represents whether it received AACK (Address ACK) from slave. When I2C is a slave, this bit is used to indicate general call. 0 TEND STOP SSEL MLOST BUSY TMODE RXACK R Initial value : 00H No AACK is received (Master mode) 1 AACK is received (Master mode) 0 Received address is not general call address (Slave mode) 1 General call address is detected (Slave mode) This bit is set when 1-Byte of data is transferred completely. Note 1) 0 1 byte of data is not completely transferred 1 1 byte of data is completely transferred This bit is set when STOP condition is detected. Note 1) 0 No STOP condition is detected 1 STOP condition is detected This bit is set when I2C is addressed by other master. Note 1) 2 0 I C is not selected as slave 1 I C is addressed by other master and acts as a slave 2 This bit represents the result of bus arbitration in master mode. Note 1) 2 0 I C maintains bus mastership 1 I2C has lost bus mastership during arbitration process This bit reflects bus status. 0 I2C bus is idle, so any master can issue a START condition 1 I C bus is busy 2 This bit is used to indicate whether I2C is transmitter or receiver. 2 0 I C is a receiver 1 I2C is a transmitter This bit shows the state of ACK signal. 0 No ACK is received 1 ACK is generated at ninth SCL period Note 1) These bits can be source of interrupt. 2 When an I C interrupt occurs except for STOP interrupt, the SCL line is hold LOW. To release SCL, write arbitrary value to I2CSR. When I2CSR is written, the TEND, STOP, SSEL, LOST, RXACK bits are cleared. PS030302-0212 PRELIMINARY 131 Z51F6412 Product Specification I2CSCLLR (SCL Low Period Register) : DCH 7 6 5 4 3 2 1 0 SCLL7 SCLL6 SCLL5 SCLL4 SCLL3 SCLL2 SCLL1 SCLL0 R/W R/W R/W R/W R/W R/W R/W SCLL[7:0] R/W Initial value : 3FH 2 This register defines the LOW period of SCL when I C operates in master mode. The base clock is SCLK, the system clock, and the period is calculated by the formula : tSCLK (4 SCLL + 1) where tSCLK is the period of SCLK. I2CSCLHR (SCL High Period Register) : DDH 7 6 5 4 3 2 1 0 SCLH7 SCLH6 SCLH5 SCLH4 SCLH3 SCLH2 SCLH1 SCLH0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 3FH SCLH[7:0] 2 This register defines the HIGH period of SCL when I C operates in master mode. The base clock is SCLK, the system clock, and the period is calculated by the formula : tSCLK (4 SCLH + 3) where tSCLK is the period of SCLK. So, the operating frequency of I2C in master mode (fI2C) is calculated by the following equation. 1 fI2C tSCLK 4 SCLL SCLH 4 I2CSDAHR (SDA Hold Time Register) : DEH 7 6 5 4 3 2 1 0 SDAH7 SDAH6 SDAH5 SDAH4 SDAH3 SDAH2 SDAH1 SDAH0 R/W R/W R/W R/W R/W R/W R/W SDAH[7:0] R/W Initial value : 01H This register is used to control SDA output timing from the falling edge of SCL. Note that SDA is changed after tSCLK SDAH. In master mode, load half the value of SCLL to this register to make SDA change in the middle of SCL. In slave mode, configure this register regarding the frequency of SCL from master. The SDA is changed after tSCLK (SDAH + 1). So, to insure normal operation in slave mode, the value tSCLK (SDAH + 1) must be smaller than the period of SCL. I2CDR (I2C Data Register) : DFH 7 6 5 4 3 2 1 0 ICD7 ICD6 ICD5 ICD4 ICD3 ICD2 ICD1 ICD0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH ICD[7:0] PS030302-0212 2 When I C is configured as a transmitter, load this register with data 2 to be transmitted. When I C is a receiver, the received data is stored into this register. PRELIMINARY 132 Z51F6412 Product Specification 2 I2CSAR (I C Slave Address Register) : D7H 7 6 5 4 3 2 1 0 SLA7 SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 GCALLEN R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 00H SLA[7:1] These bits configure the slave address of this I C module when I2C operates in slave mode. GCALLEN This bit decides whether I2C allows general call address or not when I2C operates in slave mode. 2 0 Ignore general call address 1 Allow general call address I2CSAR1 (I2C Slave Address Register 1) : D6H 7 6 5 4 3 2 1 0 SLA7 SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 GCALLEN R/W R/W R/W R/W R/W R/W R/W PS030302-0212 R/W Initial value : 00H SLA[7:1] These bits configure the slave address of this I2C module when I2C operates in slave mode. GCALLEN This bit decides whether I2C allows general call address or not when I2C operates in slave mode. 0 Ignore general call address 1 Allow general call address PRELIMINARY 133 Z51F6412 Product Specification 11.10 12-Bit A/D Converter 11.10.1 Overview The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 12-bit digital value. The A/D module has tenth analog inputs. The output of the multiplex is the input into the converter, which generates the result via successive approximation. The A/D module has four registers which are the control register ADCM (A/D Converter Mode Register), ADCM2 (A/D Converter Mode Register 2) and A/D result register ADCHR (A/D Converter Result High Register) and ADCLR (A/D Converter Result Low Register). It is selected for the corresponding channel to be converted by setting ADSEL[3:0]. To executing A/D conversion, ADST bit sets to ‘1’. The register ADCHR and ADCLR contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCHR and ADCLR, the A/D conversion status bit AFLAG is set to ‘1’, and the A/D interrupt is set. For processing A/D conversion, AFLAG bit is read as ‘0’. If using STBY (power down) bit, the ADC is disabled. Also internal timer, external generating event, comparator, the trigger of timer1pwm and etc. can start ADC regardless of interrupt occurrence. ADC Conversion Time = ADCLK * 60 cycles After STBY bit is reset (ADC power enable) and it is restarted, during some cycle, ADC conversion value may have an inaccurate value. 11.10.2 Block Diagram ÷2 SCLK Pre scaler ÷4 MUX ÷8 ÷32 12bit A/D Converter Data Register 2 CKSEL[1:0] ADCRH[7:0] (8bit) ADCLK ADCRL[7:4] (4bit) ADST VDD18 [9BH] AN14 Clear [9CH] AFLAG 12 AN13 AN12 MUX Comparator Successive Approximation Circuit ADIF ADC Interrupt AN1 AN0 4 ADS[3:0] REFSEL AN0 Resistor Ladder Circuit Figure 11-45 ADC Block Diagram PS030302-0212 PRELIMINARY 134 Z51F6412 Product Specification Analog Input Analog Power Input AN0 ~ AN14 0~1000pF AVDD 22uF Figure 11-46 A/D Analog Input Pin Connecting Capacitor Figure 11-47 A/D Power(AVDD) Pin Connecting Capacitor 11.10.3 ADC Operation Align bit set “0” ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCRH7 ADCRH6 ADCRH5 ADCRH4 ADCRH3 ADCRH2 ADCRH1 ADCRH0 ADCO3 ADCO2 ADCO1 ADCO0 ADCRL7 ADCRL6 ADCRL5 ADCRL4 ADCRL[7:4] ADCRH[7:0] ADCRL[3:0] bits are “0” Align bit set “1” ADCO11 ADCO10 ADCO9 ADCO8 ADCRH3 ADCRH2 ADCRH1 ADCRH0 ADCRH[4:0] ADCRH[7:4] bits are “0” ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 ADCRL7 ADCRL6 ADCRL5 ADCRL4 ADCRL3 ADCRL2 ADCRL1 ADCRL0 ADCRL[7:0] Figure 11-48 ADC Operation for Align bit PS030302-0212 PRELIMINARY 135 Z51F6412 Product Specification SET ADCM2 Select ADC Clock & Data Align Bit. SET ADCM ADC enable & Select AN Input Channel. Converting START N Start ADC Conversion. If Conversion is completed, AFLG is set “1” and ADC interrupt is occurred. AFLAG = 1? Y After Conversion is completed, read ADCRH and ADCRL. READ ADCRH/L ADC END Figure 11-49 Converter Operation Flow 11.10.4 Register Map Name Address Dir Default Description ADCM 9AH R/W 8FH ADCRH 9BH R - A/D Converter Mode Register A/D Converter Result High Register ADCRL 9CH R - A/D Converter Result Low Register ADCM2 9BH R/W 01H A/D Converter Mode 2 Register 11.10.5 ADC Register description The ADC Register consists of A/D Converter Mode Register (ADCM), A/D Converter Result High Register (ADCRH), A/D Converter Result Low Register (ADCRL), A/D Converter Mode 2 Register (ADCM2). Note) when STBY bit is set to ‘1’, ADCM2 can be read. If ADC enables, it is possible only to write ADCM2.When reading, ADCRH is read. PS030302-0212 PRELIMINARY 136 Z51F6412 Product Specification 11.10.6 Register description for ADC ADCM (A/D Converter Mode Register) : 9AH 7 6 5 4 3 2 1 0 STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 R/W R/W R/W R R/W R/W R/W STBY ADST REFSEL AFLAG ADSEL[3:0] PS030302-0212 R/W Initial value : 8FH Control operation of A/D standby (power down) 0 ADC module enable 1 ADC module disable (power down) Control A/D Conversion stop/start. 0 ADC Conversion Stop 1 ADC Conversion Start A/D Converter reference selection 0 Internal Reference (VDD) 1 External Reference(AVREF, AN0 disable) A/D Converter operation state 0 During A/D Conversion 1 A/D Conversion finished A/D Converter input selection ADSEL3 ADSEL 2 ADSEL 1 ADSEL 0 Description 0 0 0 0 Channel0(AN0) 0 0 0 1 Channel1(AN1) 0 0 1 0 Channel2(AN2) 0 0 1 1 Channel3(AN3) 0 1 0 0 Channel4(AN4) 0 1 0 1 Channel5(AN5) 0 1 1 0 Channel6(AN6) 0 1 1 1 Channel7(AN7) 1 0 0 0 Channel8(AN8) 1 0 0 1 Channel9(AN9) 1 0 1 0 Channel10(AN10) 1 0 1 1 Channel11(AN11) 1 1 0 0 Channel12(AN12) 1 1 0 1 Channel13(AN13) 1 1 1 0 Channel14(AN14) 1 1 1 1 Channel15(VDD18) PRELIMINARY 137 Z51F6412 Product Specification ADCRH (A/D Converter Result High Register) : 9BH 7 6 5 4 3 2 1 0 ADDM11 ADDM10 ADDM9 ADDM8 ADDM7 ADDL11 ADDM6 ADDL10 ADDM5 ADDL9 ADDM4 ADDL8 R R R R R R R ADDM[11:4] MSB align, A/D Converter High result (8-bit) ADDL[11:8] LSB align, A/D Converter High result (4-bit) R Initial value : xxH ADCRL (A/D Converter Result Low Register) : 9CH 7 6 5 4 3 2 1 0 ADDM3 ADDL7 ADDM2 ADDL6 ADDM1 ADDL5 ADDM0 ADDL4 ADDL3 ADDL2 ADDL1 ADDL0 R R R R R R R ADDM[3:0] MSB align, A/D Converter Low result (4-bit) ADDL[7:0] LSB align, A/D Converter Low result (8-bit) R Initial value : xxH ADCM2 (A/D Converter Mode Register) : 9BH 7 6 5 4 3 2 1 0 EXTRG TSEL2 TSEL1 TSEL0 ADCCK2 ALIGN CKSEL1 CKSEL0 R/W R/W R/W R/W R/W R/W R/W EXTRG TSEL[2:0] ADCCK2 ALIGN CKSEL[1:0] PS030302-0212 R/W Initial value : 01H A/D external Trigger 0 External Trigger disable 1 External Trigger enable A/D Trigger Source selection TSEL2 TSEL1 TSEL0 Description 0 0 0 Ext. Interrupt 0 0 0 1 Ext. Interrupt 1 0 1 0 Pin Change Interrupt 7 0 1 1 Timer0 interrupt event 1 0 0 Timer1 interrupt event 1 0 1 Timer2 interrupt event 1 1 0 Timer3 interrupt event 1 1 1 Timer4 interrupt event A/D Converter Clock selection 2 0 use SCLK(fx) as source of ADC clock selection 1 use (1/2 fx) as source of ADC clock selection with CKSEL This bit would be needed for higher SCLK frequency than 10MHz A/D Converter data align selection. 0 MSB align (ADCRH[7:0], ADCRL[7:4]) 1 LSB align (ADCRH[3:0], ADCRL[7:0]) A/D Converter Clock selection CKSEL1 CKSEL0 ADC Clock ADC VDD 0 0 fx/2 Test Only PRELIMINARY 138 Z51F6412 Product Specification 0 1 fx/4 3V~5V 1 0 fx/8 2.7V~3V 1 1 fx/32 2.4V~2.7V Note) 1. fx : system clock 2. ADC clock have to be used 3MHz under PS030302-0212 PRELIMINARY 139 Z51F6412 Product Specification 11.11 CALCULATOR_AI 11.11.1 Introduction The CALCULATOR_AI block is an integrated version of multiplier and divider data path block. All operation is performed with signed extension (signed multiplication, signed division). The multiplication needs only one clock cycle, but the division is performed during 32 clock cycles. You can use the EOD (End of Division) flag bit to control the division calculation flow. If divisor equals to 0, the DIV_BY_0 flag is 1 and the division result is filled with maximum value and the remainder is replaced with the dividend value. The registers for CALCULATOR_AI can be indirectly accessed via CAL_CNTR, CAL_ADDR, CAL_DATA to save the SFR area and to increase the code performance. The access address will be automatically incremented when you access to CAL_DATA (Read/Write). 0xF7 0xEE 0xEF User SFR CAL_CNTR CAL_ADDR CAL_DATA (1) Index Address (ex, 0) Indexed SFR Write/Read (3) Data (2) (4) Auto Incremented 0 MA[15:08] 1 MA[07:00] 2 MB[15:08] 3 MB[07:00] 4 MO[31:24] 5 MO[23:16] 6 MO[15:08] 7 MO[07:00] 8 DA[31:24] 9 DA[23:16] 10 DA[15:08] 11 DA[07:00] 12 DB[15:08] 13 DB[07:00] 14 MQ[31:24] 15 MQ[23:16] 16 MQ[15:08] 17 MQ[07:00] 18 MR[15:08] 19 MR[07:00] DA[31:0] DB[15:0] MA[15:0] MB[15:0] SOD EOD DIV_BY_0 1clock 32clock DQ[31:0], DR[15:0] MO[31:0] Figure 11-50 Calculator Block Diagram PS030302-0212 PRELIMINARY 140 Z51F6412 Product Specification 11.11.2 Calculator Registers map Name Address Dir Default Description CAL_CNTR F7H R/W 02H Calculator Control Register CAL_ADDR EEH R/W 00H Calculator Address Register CAL_DATA EFH R/W 00H Calculator Data Register 11.11.3 Calculator Registers description The Calculator Register consists of Calculator Control Register (CAL_CNTR), Calculator Address Register (CAL_ADDR), Calculator Data Register (CAL_DATA). 11.11.4 Calculator Registers CAL_CNTR (Calculator Control Register) : F7H 7 6 5 4 3 2 1 0 - - - - - DIV_BY_0 EOD SOD - - - - - R R DIV_BY_0 EOD SOD R/W Initial value : 02H Indicate if Divisor equals 0 0 Divisor is not 0 1 Divisor is 0 End of Division Note) Multiplication needs only one clock cycle. Note) Division needs 32 clock cycles 0 During Calculation 1 Idle or End of Calculation Start of Division Note) SOD bit will be automatically cleared after one clock cycle. 0 Idle 1 Start of Division (auto cleared) CAL_ADDR (Calculator Control Register) : EEH 7 6 5 4 3 2 1 0 CAL_ADDR7 CAL_ADDR6 CAL_ADDR5 CAL_ADDR4 CAL_ADDR3 CAL_ADDR2 CAL_ADDR1 CAL_ADDR0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 00H CAL_ADDR[7:0] Calculator Internal Register Current Address Index Value for Indirect Auto-Incremented Addressing Mode CAL_DATA (Calculator Control Register) : EFH 7 6 5 4 3 2 1 0 CAL_DATA7 CAL_DATA6 CAL_DATA5 CAL_DATA4 CAL_DATA3 CAL_DATA2 CAL_DATA1 CAL_DATA0 R/W R/W R/W R/W R/W R/W R/W PS030302-0212 PRELIMINARY R/W Initial value : 00H 141 Z51F6412 Product Specification CAL_DATA[7:0] Calculator Internal Register Current Value indexed by CAL_ADDR address index value PS030302-0212 PRELIMINARY 142 Z51F6412 Product Specification 11.11.5 Calculator Library 11.11.5.1 Signed Multiplication __sfr __at (0xF7) CAL_CNTR; __sfr __at (0xEE) CAL_ADDR; __sfr __at (0xEF) CAL_DATA; #define CAL_DIV_START 0x01 #define CAL_DIV_DONE 0x02 #define CAL_DIV_BY_0 0x04 long L_mul( short a, short b ) { long mul_o; mul_o = 0; CAL_ADDR = 0; // currently point to MA[15:8] CAL_DATA = a >> 8; // MA[15:08]