Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
PRELIMINARY PRODUCT SPECIFICATION
Z80181
SMART ACCESS CONTROLLER (SAC™)
FEATURES
■
Z80180 Compatible MPU Core with 1 Channel of
Z85C30 SCC, Z80 CTC, Two 8-Bit General-Purpose
Parallel Ports, and Two Chip Select Signals.
■
High Speed Operation (10 MHz)
■
Low Power Consumption in Two Operating Modes:
- (TBD) mA Typ. (Run Mode)
- (TBD) mA Typ. (STOP Mode)
■
Wide Operational Voltage Range (5V ± 10%)
■
TTL/CMOS Compatible
■
Clock Generator
■
One Channel of Z85C30 Serial Communication
Controller (SCC)
■
Z180 Compatible MPU Core Includes:
- Enhanced Z80 CPU Core
- Memory Management Unit (MMU) Enables Access
to 1MB of Memory
- Two Asynchronous Channels
- Two DMA Channels
- Two 16-Bit Timers
- Clocked Serial I/O Port
■
On-Board Z84C30 CTC
■
Two 8-Bit General-Purpose Parallel Ports
■
Memory Configurable RAM and ROM Chip Select Pins
■
100-Pin QFP Package
GENERAL DESCRIPTION
The Z80181 SAC ™ Smart Access Controller (hereinafter,
referred to as Z181 SAC) is a sophisticated 8-bit CMOS
microprocessor that combines a Z180-compatible MPU
(Z181 MPU), one channel of Z85C30 Serial Communication Controller (SCC), a Z80 CTC, two 8-bit general-purpose parallel ports, and two chip select signals, into a
single 100-pin Quad Flat Pack (QFP) package (Figures 1
and 2). Created using Zilog's patented Superintegration™
methodology of combining proprietary IC cores and cells,
this high-end intelligent peripheral controller is well-suited
for a broad range of intelligent communication control
applications such as terminals, printers, modems, and
slave communication processors for 8-, 16- and 32- bit
MPU based systems.
DS971800500
Information on enhancement/cost reductions of existing
hardware using Z80/Z180 with Z8530/Z85C30 applications is also included in this product specification.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
VCC
GND
VDD
VSS
PS009701-0301
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Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
GENERAL DESCRIPTION (Continued)
D7-D0
Control
A19-A0
Z80180
Compatible
Core
Tx Data
SCC
(1 Channel)
Rx Data
8
Modem/Control
Signals
8
Bit Programmable
Bi-directional I/O
or I/O Pins of CTC
CTC
Glue
Logic
A19-A12
/ROMCS
/RAMCS
Address
Decode
Logic
PIA1
PIA2
8
Bit Programmable
Bi-directional I/O
Z80181 = Z180 + SCC/2 + CTC + PIA
Figure 1. Z80181 Functional Block Diagram
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Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
/INT1
/INT2
1
100
90
95
/MREQ
/IORQ
/RFSH
+5V
/HALT
/M1
E
PHI
/RD
/WR
XTAL
GND
A17
EXTAL
/BUSREQ
/BUSACK
/WAIT
/NMI
/RESET
/INTO
PIN DESCRIPTION
85
80
ST
A0
A1
A2
CKS
RxS//CTS1
5
75
A3
A15
A4
A5
A6
A7
10
70
Z80181
100-Pin QFP
15
65
/RTS0
A18/TOUT
A19
GND
20
60
25
55
D5
D6
D7
IEI
/ROMCS
IEO
GND
/DCD
/CTS
/RTS
/DTR//REQ
TxD
/TRxC
RxD
/W//REQ
30
/SYNC
50
PIA26
PIA27
/RTxC
PIA24
PIA25
45
PIA21
PIA22
PIA23
PIA17
+5V
40
PIA12
PIA13
PAI14
PIA15
PIA16
PIA10
PIA11
35
GND
PIA20
/RAMCS
TxA1
CKA0//DREQ0
RxA0
TxA0
/DCD0
/CTS0
A12
GND
A13
A14
A16
D0
D1
D2
D3
D4
TxS
CKA1//TEND0
RxA1
TEST
A8
A9
A10
A11
/TEND1
/DREQ1
Figure 2. 100-Pin QFP Pin Configuration
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Z80181
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Zilog
CPU SIGNALS
Pin Name
Pin Number
Input/Output, Tri-State
Function
A19 - A0
4-17, 19-21,
64, 65, 91
I/O, Active 1
Address Bus. A19 - A0 form a 20-bit address bus which
specifies I/O and memory addresses to be accessed.
During the refresh period, addresses for refreshing are
output. The address bus enters a high-impedance state
during Reset and external bus acknowledge cycles. The
bus is an input when the external bus master is accessing
the on-chip peripherals. Address line A18 is multiplexed
with the output of PRT Channel 1 (TOUT, selected as address
output on Reset).
D0-D7
22-29
I/O, Active 1
8-Bit Bidirectional Data Bus. When the on-chip CPU is
accessing on-chip peripherals, these lines are outputs
and hold the data to/from the on-chip peripherals.
/RD
89
I/O, Active 0
Read Signal. CPU read signal for accepting data from
memory or I/O devices. When an external master is accessing the on-chip peripherals, it is an input signal.
/WR
88
I/O, Active 0
Write Signal. This signal is active when data to be stored
in a specified memory or peripheral device is on the MPU
data bus. When an external master is accessing the onchip peripherals, it is an input signal.
/MREQ
85
I/O, tri-state, Active 0
Memory Request Signal. When an effective address for
memory access is on the address bus, /MREQ is active.
This signal is analogous to the /ME signal of the Z64180.
/IORQ
84
I/O, tri-state, Active 0
I/O Request Signal. When addresses for I/O are on the
lower 8 bits (A7-A0) of the address bus in the I/O operation,
“0” is output. In addition, the /IORQ signal is output with the
/M1 signal during the interrupt acknowledge cycle to
inform peripheral devices that the interrupt response vector is on the data bus. This signal is analogous to the /IOE
signal of the Z64180.
/M1
87
I/O, tri-state, Active 0
Machine Cycle “1”. /MREQ and /M1 are active together
during the operation code fetch cycle. /M1 is output for
every opcode fetch when a two byte opcode is executed.
In the maskable interrupt acknowledge cycle, this signal is
output together with /IORQ. It is also used with
/HALT and ST signal to decode the status of the CPU
Machine cycle. This signal is analogous to the /LIR signal
of the Z64180.
/RFSH
83
Out, tri-state, Active 0
The Refresh Signal. When the dynamic memory
refresh address is on the low order 8-bits of the address
bus (A7 - A0), /RFSH is active along with the /MREQ signal.
This signal is analogous to the /REF signal of the Z64180.
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S MART A CCESS C ONTROLLER SAC™
Zilog
Pin Name
Pin Number
Input/Output, Tri-State
Function
/INT0
100
Wired-OR I/O, Active 0
Maskable Interrupt Request 0. Interrupt is generated by
peripheral devices. This signal is accepted if the interrupt
enable Flip-Flop (IFF) is set to “1”. Internally, the SCC and
CTC’s interrupt signals are connected to this line, and
require an external pull-up resistor.
/INT1,
/INT2
1, 2,
In, Active 0
Maskable Interrupt Request 1 and 2. This signal is
generated by external peripheral devices. The CPU honors these requests at the end of current instruction cycle as
long as the /NMI, /BUSREQ and /INT0 signals are inactive.
The CPU will acknowledge these interrupt requests with an
interrupt acknowledge cycle. Unlike the acknowledgment
for /INT0, during this cycle, neither /M1 or /IORQ will
become active.
/NMI
99
In, Active 0
Non-Maskable Interrupt Request Signal. This interrupt
request has a higher priority than the maskable interrupt
request and does not rely upon the state of the interrupt
enable Flip-Flop (IFF).
/HALT
81
Out, tri-state, Active 0
Halt Signal. This signal is asserted after the CPU has
executed either the HALT or SLP instruction, and is waiting
for either non-maskable interrupt maskable interrupt before operation can resume. It is also used with the /M1 and
ST signals to decode the status of the CPU machine cycle.
/BUSREQ
97
In, Active 0
BUS Request Signal. This signal is used by external
devices (such as a DMA controller) to request access to
the system bus. This request has higher priority than /NMI
and is always recognized at the end of the current machine
cycle. This signal will stop the CPU from executing further
instructions and place the address bus, data bus, /MREQ,
/IORQ, /RD and /WR signals into the high impedance state.
/BUSREQ is normally wired-OR and a pull-up resistor is
externally connected.
/BUSACK
96
Out, Active 0
Bus Acknowledge Signal. In response to /BUSREQ signal, /BUSACK informs a peripheral device that the address
bus, data bus, /MREQ, /IORQ, /RD and /WR signals have
been placed in the high impedance state.
/WAIT
95
Wired-OR I/O, Active 0
Wait Signal. /WAIT informs the CPU that the specified
memory or peripheral is not ready for a data transfer. As
long as /WAIT signal is active, the MPU is continuously kept
in the wait state. Internally, the /WAIT signal from the SCC
interface logic is connected to this line, and requires an
external pull-up resistor.
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Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
PERIPHERAL SIGNALS
Pin Name
Pin Number
Input/Output, Tri-State
Function
RXA0, RXA1
70, 74
In, Active 1
ASCI Receive Data 0 and 1. These signals are the receive
data to the ASCI channels.
TXA0, TXA1
69, 72
Out, Active 1
ASCI Transmit Data 0 and 1. These signals are the
receive data to the ASCI channels. Transmit data changes
are with respect to the falling edge of the transmit clock.
/RTS0
66
Out, Active 0
Request to Send 0. This is a programmable modem
control signal for ASCI channel 0.
/DCD0
68
In, Active 0
Data Carrier Detect 0. This is a programmable modem
control signal for ASCI channel 0.
/CTS0
67
In, Active 0
Clear To Send 0. This is a programmable modem control
signal for ASCI channel 0.
/CTS1/RXS
77
In, Active 0
Clear To Send 0/Clocked Serial Receive Data. This is a
programmable modem control signal for ASCI channel 0.
Also, this signal becomes receive data for the CSIO
channel under program control. On power-on Reset, this
pin is set as RxS.
CKA0//DREQ0
71
I/O, Active 1
Asynchronous Clock0/DMAC0 Request. This pin is the
transmit and receive clock for the Asynchronous channel
0. Also, under program control, this pin is used to request
a DMA transfer from DMA channel 0. DMA0 monitors this
input to determine when an external device is ready for a
read or write operation. On power-on Reset, this pin is
initialized as CKA0.
CKA1//TEND0
75
I/O, Active 1
Asynchronous Clock1/DMAC0 Transfer End. This pin is
the transmit and receive clock for the Asynchronous channel 1. Also, under program control, this pin becomes
/TEND0 and is asserted during the last write cycle of the
DMA0 operation and is used to indicate the end of the
block transfer. On power-on Reset, this pin initializes
as CKA1.
/TEND1
80
Out, Active 0
DMAC1 Transfer End. This pin is asserted during the last
write cycle of the DMA1 operation and is used to indicate
the end of the block transfer.
CKS
78
I/O, Active 1
CSIO Clock. This line is the clock for the CSIO channel.
TXS
76
Out, Active 1
CSI/O Tx Data. This line carries the transmit data from the
CSIO channel.
/DREQ1
79
In, Active 0
DMAC1 Request. This pin is used to request a DMA
transfer from DMA channel 1. DMA1 monitors this input to
determine when an external device is ready for a read or
write operation.
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Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
SCC SIGNALS
Pin Name
Pin Number
Input/Output, Tri-State
Function
/W//REQ
51
Active 0
Wait/Request. Open-drain when programmed for a Wait
function, driven “1” or “0” when programming for a Request function. Used as /WAIT or /REQUEST depending
upon SCC programming. When programmed as /WAIT,
this signal is asserted to alert the CPU that addressed
memory or I/O devices are not ready and that the CPU
should wait. When programmed as /REQUEST, this signal
is asserted when a peripheral device associated with a
DMA port is ready to read/write data. After reset, this pin
becomes “/WAIT”.
/SYNC
50
I/O, Active 0
Synchronization. This pin can act either as input, output,
or part of the crystal oscillator circuit. In asynchronous
receive mode (crystal oscillator option not selected), this
pin is an input similar to /CTS and /DCD. In this mode,
transitions on this line affect the state of the Sync/Hunt
status bit in Read Register 0 but has no other function.
In external sync mode with crystal oscillator option not
selected, this line also acts as an input. In this mode,
/SYNC must be driven “0” two receive clock cycles after
the last bit in the synchronous character is received.
Character assembly begins on the rising edge of the
receive clock immediately preceding the activation
of /SYNC.
In internal sync mode (Monosync and Bisync) with the
crystal oscillator option not selected, this line acts as
output and is active only during the part of the receive clock
cycle in which a synchronous character is recognized
(regardless of character boundaries). In SDLC mode, this
pin acts as an output and is valid on receipt of a flag.
RxD
52
In, Active 1
Receive Data. This input signal receives serial data at
standard TTL levels.
/RTxC
49
In, Active 0
Receive/Transmit Clock. This pin can be programmed in
several different modes of operation. /RTxC may supply
the receive clock, the transmit clock, the clock for the Baud
Rate Generator, or the clock for the Digital Phase-Locked
Loop. This pin can also be programmed for use with the
/SYNC pin as a crystal oscillator. The receive clocks can be
1, 16, 32, or 64 times the data transfer rate in Asynchronous
mode.
/TRxC
53
I/O, Active 0
Transmit/Receive Clock. This pin can be programmed in
several different modes of operation. /TRxC can supply the
receive clock or the transmit clock in the input mode. Also,
it can supply the output of the Digital Phase-Locked Loop,
the crystal oscillator, the Baud Rate Generator, or the
transmit clock in the output mode.
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SMART ACCESS CONTROLLER SAC™
Zilog
SCC SIGNALS (Continued)
Pin Name
Pin Number
Input/Output, Tri-State
Function
TxD
54
Out, Active 1
Transmit Data. This Output signal transmits serial data at
standard TTL level.
/DTR//REQ
55
Out, Active 0
Data Terminal Ready/Request. This output follows the
state programmed into the DTR bit. It can also be used as
general-purpose output or as Request line for a DMA
controller.
/RTS
56
Out, Active 0
Request To Send. When the RTS bit in Write Register 5 is
set, the /RTS signal goes low. When the RTS bit is reset in
Asynchronous mode and auto enable is on, the signal
goes high after the transmitter is empty. In synchronous
mode or in Asynchronous mode, with Auto Enable off, the
/RTS pin follows the state of the RTS bit. This pin can be
used as a general-purpose output.
/CTS
57
In, Active 0
Clear To Send. If this pin is programmed as auto enable,
a “0” on the input enables the transmitter. If not programmed as Auto Enable, it may be used as a generalpurpose input. This input is Schmitt-trigger buffered to
accommodate inputs with slow rise times. The SCC detects pulses on this input and can interrupt the CPU on both
logic level transitions.
/DCD
58
In, Active 0
Data Carrier Detect. This pin functions as receiver enable
if it is programmed for auto enable. Otherwise, it may be
used as a general-purpose input. This input is Schmitttrigger buffered to accommodate slow rise-time inputs.
The SCC detects pulses on this input and can interrupt the
CPU on both logic level transitions.
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Z80181
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Zilog
PIA/CTC SIGNALS
Pin Name
Pin Number
Input/Output, Tri-State
Function
PIA17-PIA14 35-38
I/O
Port 1 Data 7-Port 1 Data 4 or CTC ZC/TO3 - ZC/TO0.
These lines can be configured as inputs or outputs on a bit
-by-bit basis. Also, under program control, these bits
become Z80 CTC’s ZC/TO3 - ZC/TO0, and in either timer
or counter mode, pulses are output when the down counter
has reached zero. On reset, these signals function as
PIA17-14 and are inputs.
PIA13-PIA10 31-34
I/O
Port 1 Data 3-Port 1 Data 0 or CTC CLK/TRG3-0. These
lines can be configured as inputs or outputs on a bit by bit
basis. Also, under program control, these bits become Z80
CTC’s CLK/TRG3-CLK/TRG0, and correspond to four
Counter/Timer Channels. In the counter mode, each active
edge causes the downcounter to decrement by one. In
timer mode, an active edge starts the timer. It is program
selectable whether the active edge is rising or falling. On
reset, these signals are set to PIA13-10 as inputs.
PIA27-20
I/O
Port 2 Data. These lines are configured as inputs or
outputs on a bit-by-bit basis. On reset, they are inputs.
41-48
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SMART ACCESS CONTROLLER SAC™
Zilog
SYSTEM CONTROL SIGNALS
Pin Name
Pin Number
Input/Output, Tri-State
Function
ST
3
Out, Active 1
Status. This signal is used with the /M1 and /HALT output
to decode the status of the CPU machine cycle. Note that
the /M1 output is affected by the status of the M1E bit in the
OMCR register. The following table shows
the status while M1E=1.
2-10
ST
/HALT
/M1
Operation
0
1
0
1
1
0
1
1
1
0
0
1
X
0
0
1
0
1
CPU Operation
(1st Opcode fetch)
CPU Operation
(2nd and 3rd Opcode fetch)
CPU Operation
(MC other than Opcode fetch)
DMA operation
HALT mode
SLEEP mode
(Incl. System STOP mode)
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Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
Pin Name
Pin Number
Input/Output, Tri-State
Function
IEI
62
In, Active 1
Interrupt enable input signal. IEI is used with the IEO to
form a priority daisy chain when there is more than one
interrupt-driven peripheral.
IEO
60
Out, Active 1
The interrupt enable output signal. In the daisy-chain
interrupt control, IEO controls the interrupt of external
peripherals. IEO is active when IEI is “1” and the CPU is not
servicing an interrupt from the on-chip peripherals.
/ROMCS
61
Out, Active 0
ROM Chip select. Used to access ROM. Refer to “Functional Description” on chip select signals for further explanation.
/RAMCS
30
Out, Active 0
RAM Chip Select. Used to access RAM. Refer to “Functional Description” on chip select signals for further explanation.
/RESET
98
In, Active 0
Reset signal. /RESET signal is used for initializing the MPU
and other devices in the system. It must be kept in the
active state for a period of at least 3 system clock cycles.
EXTAL
94
In, Active 1
Crystal oscillator connecting terminal. A parallel resonant crystal is recommended. If an external clock source
is used as the input to the Z180 Clock Oscillator unit,
supply the clock into this terminal.
XTAL
93
Out
Crystal oscillator connecting terminal.
PHI
90
Out, Active 1
System Clock. Single-phase clock output from Z181
MPU.
E
86
Out, Active 1
Enable Clock. Synchronous Machine cycle clock output
during a bus transaction.
TEST
73
Out
Test pin. Used in the open state.
V CC
39, 82
Power Supply. +5 Volts
V SS
18, 40, 59,
63, 92
Power Supply. 0 Volts
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Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
FUNCTIONAL DESCRIPTION
TxS
RxS//CTS
CKS
/INT2
/INT1
/INT0
/NMI
ST
/RFSH
/BUSACK
/BUSREQ
/WAIT
/HALT
/IORQ
/MREQ
/M1
/WR
/RD
/RESET
E
Interrupt
CPU
16-Bit
Programmable
Reload Timers
(2)
DMACs
(2)
/DREQ1
/TEND
TxA0
Clocked
Serial I/O
Port
CKA0 /DREQ0
Data Bus (8-Bit)
A18 /TOUT
each discrete product for a detailed description of each
individual unit. The following subsections describe each
individual functional unit of the SAC.
Bus State Control
Timing
Generator
Address Bus (16-Bit)
Ø
EXTAL
XTAL
Functionally, the on-chip Z181 MPU, SCC, and CTC are
the same as the discrete devices (Figure 1). Therefore,
refer to the Product Specification/Technical Manual of
Asynchronous
SCI
(Channel 0)
RxA0
/RTS0
/CTS0
/DCD0
TxA1
Asynchronous
SCI
(Channel 1)
MMU
A19-A0
CKA1 /TEND0
RxA1
D7-D0
Figure 3. Z181 MPU Block Diagram
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Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
Z181 MPU
This unit provides all the capabilities and pins of the Zilog
Z180 MPU. Figure 3 shows the Z181 MPU block diagram.
This allows 100% software compatibility with existing Z180
(and Z80) software. Note that the on-chip I/O address
should not be relocated to the I/O address (from 0C0h to
0FFh) to avoid address conflicts. The following is an
overview of the major functional units of the Z181.
■
Maskable interrupt request operation
■
Trap and Non-Maskable interrupt request operation
■
HALT and low power modes of operation
■
Reset Operation
Z181 CPU
Memory Management Unit (MMU)
The Memory Management Unit (MMU) allows the user to
“map” the memory used by the CPU (64K bytes of logical
addressing space) into 1M bytes of physical addressing
space. The organization of the MMU allows object code
compatibility with the Z80 CPU while offering access to an
extended memory space. This is accomplished by using
an effective “common area-banked area” scheme.
The Z181 CPU has 100% software compatibility with the
Z80 CPU. In addition, the Z181 CPU has the following
features:
Faster execution speed. The Z181 CPU is “fine tuned”
making execution speed, on average, 10% to 20% faster
than the Z80 CPU.
Enhanced DRAM Refresh Circuit. Z181 CPU’s DRAM
refresh circuit does periodic refresh and generates an
8-bit refresh address. It can be disabled or the refresh
period adjusted, through software control.
Enhanced Instruction Set. The Z181 CPU has seven
additional instructions to those of the Z80 CPU which
include the MLT (Multiply) instruction.
HALT and Low Power Modes of Operation. The Z181
CPU has HALT and low power modes of operation, which
are ideal for the applications requiring low power consumption like battery operated portable terminals.
System Stop Mode. When the Z181 SAC is in SYSTEM
STOP mode, it is only the Z181 MPU which is in STOP
mode. The on-chip CTC and SCC continue their normal
operation.
Instruction Set. The instruction set of the Z181 CPU is
identical to the Z180. For more details about each transaction, please refer to the Data Sheet/Technical Manual for
the Z180/Z80 CPU.
Z181 CPU Basic Operation
Z181 CPU’s basic operation consists of the following
events. These are identical to the Z180 MPU. For more
details about each operation, please refer to the Data
Sheet/Technical manual for the Z180.
■
Operation code fetch cycle
■
Memory Read/Write operation
■
Input/Output operation
■
Bus request/acknowledge operation
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DMA Controller
The Z181 MPU has two DMA controllers. Each DMA
controller provides high-speed data transfers between
memory and I/O devices. Transfer operations supported
are memory to memory, memory to/from I/O, and I/O to
I/O. Transfer modes supported are request, burst, and
cycle steal. The DMA can access the full 1M bytes addressing range with a block length up to 64K bytes and can
cross over 64K boundaries.
Asynchronous Serial Communication Interface
(ASCI)
This unit provides two individual full-duplex UARTs. Each
channel includes a programmable baud rate generator
and modem control signals. The ASCI channels also
support a multiprocessor communication format.
Programmable Reload Timer (PRT)
The Z181 MPU has two separate Programmable Reload
Timers, each containing a 16-bit counter (timer) and count
reload register. The time base for the counters is system
clock divided by 20. PRT channel 1 provides an optional
output to allow for waveform generation.
Clocked Serial I/O (CSI/O)
The CSI/O channel provides a half-duplex serial transmitter and receiver. This channel can be used for simple highspeed data connection to another CPU or MPU.
Programmable Wait State Generator
To ease interfacing with slow memory and I/O devices, the
Z181 MPU unit has a programmable wait state generator.
By programming the DMA/WAIT Control Register (DCNTL),
up to three wait states are automatically inserted in memory and I/O cycles. This unit also inserts wait states during
on-chip DMA transactions.
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Zilog
FUNCTIONAL DESCRIPTION (Continued)
Baud Rate
Generator
} Serial Data
Channel
Internal
Control
Logic
10 X 19
Frame
Status
FIFO
Channel
Registers
} Channel Clocks
/SYNC
/Wait
Discrete
Control
& Status
Modem, DMA,
or Other
Controls
Internal BUS
Interrupt
Control
Lines
Interrupt
Control
Logic
Figure 4. SCC Block Diagram
Z85C30 Serial Communication Controller
Logic Unit
This logic unit provides the user with a multi-protocol serial
I/O channel that is completely compatible with the two
channel Z85C30 SCC with the following exceptions:
■
RR3 - Returns IP status (Ch.A side).
■
WR9 - Ch.B Software Reset command has no effect.
Their basic functions as serial-to-parallel and parallel-toserial converters can be programmed by the CPU for a
broad range of serial communications applications. This
logic unit is capable of supporting all common asynchronous and synchronous protocols (Monosync, Bisync, and
SDLC/HDLC, byte or bit oriented - Figure 4).
The PCLK for the SCC is connected to PHI (System clock),
the /INT signal is connected to /INT0 signal internally
(requires external pull-up resistor) and SCC is reset when
/RESET input becomes active. Interrupt from the SCC is
handled through Mode 2 interrupt. During the interrupt
acknowledge cycle, the on-chip SCC interface circuit
inserts two wait states automatically.
On the discrete version of the SCC (dual channel version),
there are two registers shared between channels A and B,
and two registers whose functions are different by channel. These are: WR2, WR9 (shared registers), and RR2 and
RR3 (different functionality).
Following are the differences in functionality:
■
RR2 - Returns Unmodified Vector or modified vector
depends on the status of “VIS” (Vector Include Status)
bit in WR9.
2-14
Z84C30 Counter/Timer Logic Unit
This logic unit provides the user with four individual 8-bit
Counter/Timer Channels that are compatible with the
Z84C30 CTC (Figure 5). The Counter/Timers are programmed by the CPU for a broad range of counting and
timing applications. Typical applications include event
counting, interrupt and interval counting, and serial baud
rate clock generation.
PS009701-0301
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Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
Each of the Counter/Timer Channels, designated Channels 0-3, have an 8-bit prescaler (when used in timer
mode) and its own 8-bit counter to provide a wide range of
count resolution. Each of the channels have their own
Clock/Trigger input to quantify the counting process and
an output to indicate zero crossing/timeout conditions.
These signals are multiplexed with the Parallel Interface
Adapter 1 (PIA1). With only one interrupt vector programmed into the logic unit, each channel can generate a
unique interrupt vector in response to the interrupt acknowledge cycle.
Internal
Control
Logic
Control
CPU
BUS
I/O
/INT
IEI
IEO
Interrupt
Logic
Internal Bus
Data
4
Counter/
Timer
Logic
ZC/TO
4
CLK/TRG
Mutiplexed
with PIA1
/RESET
Figure 5. CTC Block Diagram
Parallel Interface Adapter (PIA)
The SAC has two 8-bit Parallel Interface Adapter (PIA)
Ports. The ports are referred to as PIA1 and PIA2. Each port
has two associated control registers; a Data Register and
a register to determine each bit’s direction (input or output). PIA1 is multiplexed with the CTC I/O pins. When the
CTC I/O feature is selected, the CTC I/O functions override
the PIA1 feature. Mode Selection is made through the
System Configuration Register (Address: EDh; Bit D0).
PIA1 has Schmitt-triggered inputs to have a better noise
margin. These ports are inputs after reset.
C1
XTAL
Crystal
Inputs
C2
EXTAL
Figure 6. Circuit Configuration For Crystal
Clock Generator
The SAC uses the Z181 MPU’s on-chip clock generator to
supply system clock. The required clock is easily generated by connecting a crystal to the external terminals
(XTAL, EXTAL). The clock output runs at half the crystal
frequency. The system clock inputs of the SCC and the
CTC are internally connected to the PHI output of the Z181
MPU.
DS971800500
PS009701-0301
2-15
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Recommended characteristics of the crystal and the values for the capacitor are as follows (the values will change
with crystal frequency).
Type of crystal: Fundamental, parallel type crystal
(AT cut is recommended).
Frequency tolerance: Application dependent.
CL, Load capacitance: Approximately 22 pF
(acceptable range is 20-30 pF)
Rs, equivalent-series resistance: ≤ 30 Ohms
Drive level: 10 mW (for ≤ 10 MHz crystal) 5 mW
(for ≥ 10 MHz crystal)
These two signals are generated by decoding address
lines A19-A12. Note that glitches may be observed on the
/RAMCS and /ROMCS signals because the address decoding logic decodes only A19-A12, without any control
signals.
Bit D5 of the System Configuration Register allows the
option of disabling the /ROMCS signal. This feature is used
in systems which, for example, have a shadow RAM.
However, prior to disabling the /ROMCS signal, the ROMBR
and RAMLBR registers must be re-initialized from their
default values.
For more details, please refer to “Programming section”.
ROM Emulator Mode
CIN = COUT = 15 ~ 22 pF.
Chip Select Signals
The SAC has two chip select (/RAMCS, /ROMCS) pins.
/ROMCS is the chip select signal for ROM and /RAMCS is
the chip select signal for RAM. The boundary value for
each chip select signal is 8 bits wide allowing all memory
accesses with addresses less than or equal to this boundary value. This causes assertion of the corresponding /CS
pin. These features are controlled through the RAM upper
boundary address register (I/O address EAh), RAM lower
boundary address register (I/O address EBh) and ROM
upper boundary address register (I/O address ECh).
To ease development, the SAC has a mode to support
“ROM emulator” development systems. In this mode, a
read data from on-chip registers (except Z181 MPU onchip registers) are available (data bus direction set to
output) to make data visible from the outside, so that a
ROM Emulator/Logic Analyzer can monitor internal transactions. Otherwise, a read from an internal transaction is
not available to the outside (data bus direction set to Hi-Z
status). Mode selection is made through the D1 bit in the
System Configuration Register (I/O Address: EDh).
Programming
The following subsections explain and define the parameters for I/O Address assignments, I/O Control Register
Addresses and all pertinent Timing parameters.
I/O Address Assignment
The SAC has 78 internal 8-bit registers to control on-chip
peripherals and features. Sixty-four registers out of 78
registers are occupied by the Z181 MPU control registers;
2-16
two for SCC control registers, four for PIA control registers,
four for the Counter/Timer, three for RAM/ROM configuration (memory address boundaries) and one for SAC’s
system control. The SAC’s I/O addresses are listed in
Table 1. These registers are assigned in the SAC’s I/O
addressing space and the I/O addresses are fully decoded from A7-A0 and have no image.
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
PROGRAMMING (Continued)
Table 1. I/O Control Register Address
Address
Register
00h
to 3Fh
E0h
E1h
Z181 MPU Control Registers
(Relocatable to 040h-07Fh, or 080h-0BFh)
PIA1 Data Direction Register (P1DDR)
PIA1 Data Port (P1DP)
E2h
E3h
E4h
E5h
PIA2 Data Direction Register (P2DDR)
PIA2 Data Register (P2DP)
CTC Channel 0 Control Register (CTC0)
CTC Channel 1 Control Register (CTC1)
E6h
E7h
E8h
E9h
CTC Channel 2 Control Register (CTC2)
CTC Channel 3 Control Register (CTC3)
SCC Control Register (SCCCR)
SCC Data Register (SCCDR)
EAh
RAM Upper Boundary Address Register
(RAMUBR)
RAM Lower Boundary Address Register
(RAMLBR)
EBh
ECh
EDh
EEh
EFh
Z181 MPU Control Registers
The I/O address for these registers can be relocated in 64
byte boundaries by programming of the I/O Control Register (Address xx111111b).
Do not relocate these registers to address from 0C0h since
this will cause an overlap of the Z180 registers and the 16
registers of the Z181 (address 0E0h to 0EFh).
Also, the OMCR register (Address: xx111101b) must be
programmed as 0x0xxxxxb (x: don’t care) as a part of the
initialization procedure. The M1E bit (Bit D7) of this register
must be programmed as 0 or the interrupt daisy chain is
corrupted. The /IOC bit (Bit D5) of this register is programmed as 0 so that the timing of the /RD and /IORQ
signals are compatible with Z80 peripherals.
For detailed information, refer to the Z180 Technical Manual.
ROM Address Boundary Register (ROMBR)
System Configuration Register (SCR)
Reserved
Reserved
DS971800500
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2-17
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
ASCI CHANNELS CONTROL REGISTERS
CNTLA0
Bit
MPE
Upon RESET
R/W
Addr 00h
RE
TE
MPBR/
/RTS0 EFR MOD2 MOD1 MOD0
0
0
0
1
x
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
MODE Selection
Start + 7-Bit Data + 1 Stop
Start + 7-Bit Data + 2 Stop
Start + 7-Bit Data + Parity + 1 Stop
Start + 7-Bit Data + Parity + 2 Stop
Start + 8-Bit Data + 1 Stop
Start + 8-Bit Data + 2 Stop
Start + 8-Bit Data + Parity + 1 Stop
Start + 8-Bit Data + Parity + 2 Stop
Read - Multiprocessor Bit Receive
Write - Error Flag Reset
Request To Send
Transmit Enable
Receive Enable
Multiprocessor Enable
Figure 7. ASCI Control Register A (Ch. 0)
CNTLA1
Bit
Upon RESET
R/W
Addr 01h
CKA1D MPBR/ MOD2 MOD1 MOD0
EFR
MPE
RE
TE
0
0
0
1
x
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
MODE Selection
Start + 7-Bit Data + 1 Stop
Start + 7-Bit Data + 2 Stop
Start + 7-Bit Data + Parity + 1 Stop
Start + 7-Bit Data + Parity + 2 Stop
Start + 8-Bit Data + 1 Stop
Start + 8-Bit Data + 2 Stop
Start + 8-Bit Data + Parity + 1 Stop
Start + 8-Bit Data + Parity + 2 Stop
Read - Multiprocessor Bit Receive
Write - Error Flag Reset
CKA1 Disable
Transmit Enable
Receive Enable
Multiprocessor Enable
Figure 8. ASCI Control Register A (Ch. 1)
2-18
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
Addr 02h
CNTLB0
Bit
MPBT
MP
/CTS/
PS
PE0
DR
SS2
SS1
SS0
Upon Reset
Invalid
0
†
0
0
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Source and Speed Select
Divide Ratio
Parity Even or Odd
Clear To Send/Prescale
Multiprocessor
Multiprocessor Bit Transmit
† /CTS - Depending on the condition of /CTS pin.
PS - Cleared to 0.
General
Divide Ratio
SS, 2, 1, 0
PS = 0
(Divide Ratio = 10)
DR = 0 (x16)
000
001
010
011
100
101
110
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
111
External Clock (Frequency < Ø ÷ 40)
160
320
640
1280
2560
5120
10240
DR = 1 (x64)
PS = 1
(Divide Ratio = 30)
DR = 0 (x16)
DR = 1 (x64)
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
640
1280
2580
5120
10240
20480
40960
480
960
1920
3840
7680
15360
30720
1920
3840
7680
15360
30720
61440
122880
Figure 9. ASCI Control Register B (Ch. 0)
DS971800500
PS009701-0301
2-19
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
ASCI CHANNELS CONTROL REGISTERS (Continued)
CNTLB1
Addr 03h
Bit
MPBT
MP
/CTS/
PS
Upon Reset
Invalid
0
0
0
0
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PE0
DR
SS2
SS1
SS0
Clock Source and Speed Select
Divide Ratio
Parity Even or Odd
Read - Status of /CTS pin
Write - Select PS
Multiprocessor
Multiprocessor Bit Transmit
General
Divide Ratio
SS, 2, 1, 0
PS = 0
(Divide Ratio = 10)
DR = 0 (x16)
000
001
010
011
100
101
110
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
111
External Clock (Frequency < Ø ÷ 40)
160
320
640
1280
2560
5120
10240
DR = 1 (x64)
PS = 1
(Divide Ratio = 30)
DR = 0 (x16)
DR = 1 (x64)
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
Ø÷
640
1280
2580
5120
10240
20480
40960
480
960
1920
3840
7680
15360
30720
1920
3840
7680
15360
30720
61440
122880
Figure 10. ASCI Control Register B (Ch. 1)
2-20
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
STAT0
Bit
Addr 04h
PE
FE
RIE
Upon Reset
RDRF OVRN
0
0
0
0
0
/DCD0 TDRE
†
††
TIE
0
R/W
R
R
R
R
R/W
R
R
R/W
Transmit Interrupt Enable
Transmit Data Register
Empty
Data Carrier Detect
Receive Interrupt Enable
Framing Error
Parity Error
Over Run Error
Receive Data Register Full
† /DCD0 - Depending on the condition of /DCD0 Pin.
†† /CTS0 Pin
L
H
TDRE
1
0
Figure 11. ASCI Status Register
STAT1
Bit
Addr 05h
RDRF OVRN
CTS1E TDRE
PE
FE
RIE
Upon Reset
0
0
0
0
0
0
1
TIE
0
R/W
R
R
R
R
R/W
R/W
R
R/W
Transmit Interrupt Enable
Transmit Data Register
Empty
/CTS1 Enable
Receive Interrupt Enable
Framing Error
Parity Error
Over Run Error
Receive Data Register Full
Figure 12. ASCI Status Register (Ch. 1)
DS971800500
PS009701-0301
2-21
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
ASCI CHANNELS CONTROL REGISTERS (Continued)
TDR0
Write Only
7
6
5
TSR0
Read Only
Addr 06h
4
3
2
1
0
x
x
x
Addr 08h
x
x
x
x
x
Transmit Data
Received Data
Figure 13. ASCI Transmit Data Register (Ch. 0)
TDR1
Write Only
7
6
5
Figure 15. ASCI Receive Data Register (Ch. 0)
TSR1
Read Only
Addr 07h
4
3
2
1
0
x
x
x
Addr 09h
x
x
x
x
x
Transmit Data
Received Data
Figure 14. ASCI Transmit Data Register (Ch. 1)
Figure 16. ASCI Receive Data Register (Ch. 1)
CSI/O Registers
CNTR
Bit
Addr 0Ah
EF
EIE
RE
TE
-
SS2
SS1
SS0
Upon Reset
0
0
0
0
1
1
1
1
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Speed Select
Transmit Enable
Receive Enable
End Interrupt Enable
End Flag
SS2, 1, 0
Baud Rate
SS2, 1, 0
000
001
010
011
Ø÷
Ø÷
Ø÷
Ø÷
100
101
110
111
20
40
80
100
Baud Rate
Ø ÷ 320
Ø ÷ 640
Ø ÷ 1280
External Clock
(Frequency < Ø ÷ 20)
Figure 17. CSI/O Control Register
2-22
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
TRDR
Read/Write
7
6
5
Addr 0Bh
4
3
2
1
0
Read - Received Data
Write - Transmit Data
Figure 18. CSI/O Transmit/Receive Data Register
TIMER REGISTERS
Timer Data Registers
TMDR0L
Read/Write
7
6
5
TMDR0H
Read/Write
Addr 0Ch
4
3
2
1
Addr 0Dh
15 14 13 12 11 10 9
0
8
When Read, read Data Register L
before reading Data Register H.
Figure 19. Timer 0 Data Register L
Figure 21. Timer 0 Data Register H
TMDR1L
Read/Write
7
6
5
Addr 14h
4
3
2
1
0
TMDR1H
Read/Write
Addr 15h
15 14 13 12 11 10 9
Figure 20. Timer 1 Data Register L
8
When Read, read Data Register L
before reading Data Register H.
Figure 22. Timer 1 Data Register H
Timer Reload Registers
RLDR0L
Read/Write
7
6
5
RLDR1L
Read/Write
Addr 0Eh
4
3
2
1
7
0
Figure 23. Timer 0 Reload Register L
DS971800500
6
5
Addr 16h
4
3
2
1
0
Figure 24. Timer 1 Reload Register L
PS009701-0301
2-23
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
Timer Reload Registers (Continued)
RLDR0H
Read/Write
RLDR1H
Read/Write
Addr 0Fh
15 14 13 12 11 10 9
8
Addr 17h
15 14 13 12 11 10 9
Figure 25. Timer 0 Reload Register H
8
Figure 26. Timer 1 Reload Register H
Timer Control Register
TCR
Addr 10h
TIF1
TIF0
TIE1
TIE0
TOC1
Upon Reset
0
0
0
0
0
0
0
0
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Bit
TOC0 TDE1
TDE0
Timer Down Count Enable 1,0
Timer Output Control 1,0
Timer Interrupt Enable 1,0
Timer Interrupt Flag 1,0
TOC1,0
00
01
10
11
A15/TOUT
Inhibited
Toggle
0
1
Figure 27. Timer Control Register
Free Running Counter
FRC
Read Only
7
6
5
Addr 18h
4
3
2
1
0
Figure 28. Free Running Counter
2-24
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
DMA Registers
SAR0L
Read/Write
SA7
Addr 20h
SA0
DAR0L
Read/Write
DA7
Addr 23h
DA0
SAR0H
Read/Write
SA15
Addr 21h
SA8
DAR0H
Read/Write
DA15
Addr 24h
DA8
SAR0B
Read/Write
-
-
-
DAR0B
Read/Write
Addr 22h
SA19
SA16
DA19
-
-
Bits 0-2 (3) are used for SAR0B
A19, A18,
x
x
x
x
x
x
x
x
A17,
A16
0
0
1
1
0
1
0
1
-
-
Bits 0-2 (3) are used for DAR0B
DMA Transfer Request
/DREQ0 (external)
RDR0 (ASCI0)
TDR0 (ASCI1)
Not Used
A19, A18,
x
x
x
x
Figure 29. DMA 0 Source Address Registers
DS971800500
-
Addr 25h
DA16
A17,
A16
0
0
1
1
0
1
0
1
x
x
x
x
DMA Transfer Request
/DREQ0 (external)
RDR0 (ASCI0)
TDR0 (ASCI1)
Not Used
Figure 30. DMA 0 Destination Address Registers
PS009701-0301
2-25
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
DMA REGISTERS (Continued)
BCR0L
Read/Write
BC7
Addr 26h
BC0
IAR1L
Read/Write
IA7
Addr 2Bh
IA0
BCR0H
Read/Write
BC15
Addr 27h
BC8
IAR1H
Read/Write
IA15
Addr 2Ch
IA8
Figure 31. DMA 0 Byte Counter Registers
Figure 33. DMA 1 I/O Address Registers
MAR1L
Read/Write
MA7
Addr 28h
MA0
BCR1L
Read/Write
BC7
Addr 2Eh
BC0
MAR1H
Read/Write
MA15
Addr 29h
MA8
BCR1H
Read/Write
BC15
Addr 2Fh
BC8
MAR1B
Read/Write
-
-
-
Figure 34. DMA 1 Byte Count Registers
Addr 2Ah
MA19
MA16
-
Figure 32. DMA 1 Memory Address Registers
2-26
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
DSTAT
Bit
Upon Reset
R/W
Addr 30h
DE1
DE0
/DWE1 /DWE0 DIE1
0
0
1
1
R/W
R/W
W
W
DIE0
-
DIME
0
0
1
0
R/W
R/W
R
DMA Master Enable
DMA Interrupt Enable 1, 0
DMA Enable Bit Write Enable 1, 0
DMA Enable Ch 1, 0
Figure 35. DMA Status Register
DMODE
Addr 31h
Bit
-
-
DM1
DM0
SM1
SM0
MMOD
-
Upon Reset
1
1
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
Memory MODE Select
Ch 0 Source Mode 1, 0
Ch 0 Destination Mode 1, 0
DM1, 0
Destination
Address
SM1, 0
Source
Address
00
01
10
11
M
M
M
I/O
DAR0+1
DAR0-1
DAR0 Fixed
DAR0 Fixed
00
01
10
11
M
M
M
I/O
SAR0+1
SAR0-1
SAR0 Fixed
SAR0 Fixed
MMOD
Mode
0
1
Cycle Steal Mode
Burst Mode
Figure 36. DMA Mode Registers
DS971800500
PS009701-0301
2-27
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
DMA REGISTERS (Continued)
DCNTL
Bit
Upon Reset
R/W
Addr 32h
MWI1 MWI0
IWI1
IWI0
DMS1 DMS0
DIM1
DIM0
1
1
1
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DMA Ch 1 I/O Memory
Mode Select
/DREQi Select, i = 1, 0
I/0 Wait Insertion
Memory Wait Insertion
MWI1, 0
No. of Wait States
IWI1, 0
No. of Wait States
00
01
10
11
0
1
2
3
00
01
10
11
0
2
3
4
DMSi
Sense
1
0
Edge Sense
Level Sense
DM1, 0
Transfer Mode
00
01
10
11
M - I/O
M - I/O
I/O - M
I/O - M
Address Increment/Decrement
MAR1+1
MAR1-1
IAR1 Fixed
IAR1 Fixed
IAR1 Fixed
IAR1 Fixed
MAR1+1
MAR1-1
Figure 37. DMA/WAIT Control Register
2-28
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
MMU Registers
CBR
Bit
Upon Reset
R/W
Addr 38h
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MMU Common Base
Register
Figure 38. MMU Common Base Register
BBR
Bit
Upon Reset
R/W
Addr 39h
BB7
BB6
BB5
BB4
BB3
BB2
BB1
BB0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MMU Bank Base Register
Figure 39. MMU Bank Base Register
CBAR
Bit
Upon Reset
R/W
Addr 3Ah
CA3
CA2
CA1
CA0
BA3
BA2
BA1
BA0
1
1
1
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MMU Bank Area Register
MMU Common Area Register
Figure 40. MMU Common/Bank Area Register
DS971800500
PS009701-0301
2-29
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
System Control Registers
IL
Bit
Upon Reset
R/W
Addr 33h
IL7
IL6
IL5
-
-
-
-
-
0
0
0
0
0
0
0
0
R/W
R/W
R/W
Interrupt Vector Low
Figure 41. Interrupt Vector Low Register
ITC
Bit
Upon Reset
R/W
Addr 34h
TRAP
UFO
-
-
-
0
0
1
1
1
R/W
R
ITE2
ITE1
ITE0
0
0
1
R/W
R/W
R/W
/INT Enable 2, 1, 0
Undefined Fetch Object
TRAP
Figure 42. INT/TRAP Control Register
RCR
Bit
Upon Reset
R/W
Addr 36h
REFE REFW
1
1
R/W
R/W
-
-
-
-
1
1
1
1
CYC1 CYC0
0
0
R/W
R/W
Cycle Select
Refresh Wait State
Refresh Enable
CYC1, 0
Interval of Refresh Cycle
00
01
10
11
10 states
20 states
40 states
80 states
Figure 43. Refresh Control Register
2-30
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
OMCR
Bit
Upon Reset
R/W
Addr 3Eh
M1E
/M1TE
/IOC
-
-
-
-
-
1
1
1
1
1
1
1
1
R/W
W
R/W
I/O Compatibility
/M1 Temporary Enable
/M1 Enable
Note: This register has to be programmed as 0x0xxxxxb(x:don't care) as a part of Initialization.
Figure 44. Operation Mode Control Register
ICR
Bit
Upon Reset
R/W
IOA7
Addr 3Fh
IOA6 IOSTP
0
0
0
R/W
R/W
R/W
-
-
-
-
-
1
1
1
1
1
I/O Stop
I/O Address
Combination of 11
is reserved
Figure 45. I/O Control Register
DS971800500
PS009701-0301
2-31
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
CTC Control Registers
Channel Control Word
This word sets the operating modes and parameters as
described below. Bit D0 must be a “1” to indicate that this
is a Control Word (Figure 46).
For more detailed information, refer to the CTC Technical
Manual.
Addr: E4h (Ch 0)
E5h (Ch 1)
E6h (Ch 2)
E7h (Ch 3)
D7 D6 D5 D4 D3 D2 D1 D0
Control or Vector
0 Vector
1 Control Word
Reset
0 Continued Operation
1 Software Reset
Time Constant
0 No Time Constant Follows
1 Time Constant Follows
Time Trigger *
0 Automatic Trigger When
Time Constant is Loaded
1 CLK/TRG Pulse Starts Timer
CLK/TRG Edge Selection
0 Selects Falling Edge
1 Selects Rising Edge
Prescaler Value *
1 Value of 256
0 Value of 16
Mode
0 Selects Timer Mode
1 Selects Counter Mode
Interrupt
1 Enables Interrupt
0 Disables Interrupt
* Timer Mode Only
Figure 46. CTC Channel Control Word
This register has the following fields:
Bit D4. Clock/Trigger Edge Selector. This bit selects the
active edge of the CLK/TRG input pulses.
Bit D7. Interrupt Enable. This bit enables the interrupt logic
so that an internal INT is generated at zero count. Interrupts
are programmed in either mode and may be enabled or
disabled at any time.
Bit D3. Timer Trigger. This bit selects the trigger mode for
timer operation. Either automatic or external trigger may be
selected.
Bit D6. Mode Bit. This bit selects either Timer Mode or
Counter Mode.
Bit D2. Time Constant. This bit indicates that the next word
programmed is time constant data for the downcounter.
Bit D5. Prescaler Factor. This bit selects the prescaler
factor for use in the timer mode. Either divide-by-16 or
divide-by-256 is available.
Bit D1. Software Reset. Writing a “1” to this bit indicates a
software reset operation, which stops counting activities
until another time constant word is written.
2-32
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
Time Constant Word
Before a channel can start counting, it must receive a time
constant word. The time constant value may be anywhere
between 1 and 256, with “0” being accepted as a count of
256 (Figure 47).
Interrupt Vector Word
If one or more of the CTC channels have interrupt enabled,
then the Interrupt Vector Word is programmed. Only the
five most significant bits of this word are programmed, and
bit D0 must be “0”. Bits D2-D1 are automatically modified
by the CTC channels after responding with an interrupt
vector (Figure 48).
D7 D6 D5 D4 D3 D2 D1 D0
Addr: E4h
TC0
D7 D6 D5 D4 D3 D2 D1 D0
TC1
TC2
0 Interrupt Vector Word
1 Control Word
TC3
Channel Identifier
(Automatically Inserted
by CTC)
0 0 Channel 0
0 1 Channel 1
1 0 Channel 2
1 1 Channel 3
TC4
TC5
TC6
TC7
Supplied By User
Figure 47. CTC Time Constant Word
Figure 48. CTC Interrupt Vector Word
SCC REGISTERS
For more detailed information, please refer to the Z8030/
Z8530 SCC Technical Manual.
Note:
The Address for the Control/Status Register is E8h. The
Address for the Data Register is E9h.
Read Registers
The SCC contains eight read registers. To read the contents of a register (rather than RR0), the program must first
initialize a pointer to WR0 in exactly the same manner as a
write operation. The next I/O read cycle will place the
contents of the selected read registers onto the data bus
(Figure 49).
Table 2. SCC Read Registers
Bit
Description
Bit
Description
RR0
Transmit and Receive buffer status
and external status.
Special Receive Condition status.
Interrupt vector (modified if VIS Bit in WR9 is set).
Interrupt pending bits.
SDLC FIFO byte counter lower byte
(only when enabled).
RR7
SDLC FIFO byte count and status
(only when enabled).
Receive buffer.
Miscellaneous status bits.
Lower byte of baud rate.
Upper byte of baud rate generator time constant.
External Status interrupt information.
RR1
RR2
RR3
RR6
DS971800500
RR8
RR10
RR12
RR13
RR15
PS009701-0301
2-33
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
SCC REGISTERS (Continued)
Read Register 2
Read Register 0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Rx Character Available
V0
Zero Count
V1
Tx Buffer Empty
V2
DCD
V3
Sync/Hunt
V4
CTS
V5
Tx Underrun/EOM
V6
Break/Abort
V7
*
(a)
Interrupt
Vector *
Modified if VIS bit in Write register 9 is set.
(c)
Read Register 1
Read Register 3
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
All Sent
0
Residue Code 2
0
Residue Code 1
0
Residue Code 0
Ext/Status IP
Parity Error
Tx IP
Rx Overrun Error
Rx IP
CRC/Framing Error
0
End of Frame (SDLC)
0
(d)
(b)
Figure 49. SCC Read Register Bit Functions
2-34
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
Read Register 6 *
Read Register 10
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
*
BC0
0
BC1
On Loop
BC2
0
BC3
0
BC4
Loop Sending
BC5
0
BC6
Two Clocks Missing
BC7
One Clock Missing
Can only be accessed if the SDLC FIFO enhancement
is enabled (WR15 bit D2 set to 1)
(g)
(e) SDLC FIFO Status and Byte Count (LSB)
Read Register 7 *
Read Register 12
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
BC8
TC0
BC9
TC1
BC10
TC2
BC11
TC3
BC12
TC4
BC13
TC5
FDA: FIFO Available Status
1 Status Reads from FIFO
TC6
FOS: FIFO Overflow Status
1 FIFO Overflowed
0 Normal
*
Lower Byte
of Time Constant
TC7
(h)
Can only be accessed if the SDLC FIFO enhancement
is enabled (WR15 bit D2 set to 1)
(f) SDLC FIFO Status and Byte Count (MSB)
Figure 49. SCC Read Register Bit Functions (Continued)
DS971800500
PS009701-0301
2-35
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
SCC REGISTERS (Continued)
Read Register 13
Read Register 15
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
TC8
0
TC9
Zero Count IE
TC10
0
TC11
TC12
DCD IE
Upper Byte
of Time Constant
Sync/Hunt IE
TC13
CTS IE
TC14
Tx Underrun/EOM IE
TC15
Break/Abort IE
(j)
(i)
Figure 49. SCC Read Register Bit Functions (Continued)
Write Registers
The SCC contains fifteen write registers that are programmed to configure the operating modes of the channel. With the exception of WR0, programming the write
registers is a two step operation. The first operation is a
pointer written to WR0 that points to the selected register.
The second operation is the actual control word that is
written into the register to configure the SCC channel
(Figure 50).
Table 3. SCC Write Registers
Bit
Description
Bit
Description
WR0
Register Pointers, various initialization
commands
Transmit and Receive interrupt enables,
WAIT/DMA commands
Interrupt Vector
Receive parameters and control modes
Transmit and Receive modes and parameters
Transmit parameters and control modes
Sync Character or SDLC address
Sync Character or SDLC flag
WR8
WR9
WR10
WR11
WR12
WR13
WR14
WR15
Transmit buffer
Master Interrupt control and reset commands
Miscellaneous transmit and receive control bits
Clock mode controls for receive and transmit
Lower byte of baud rate generator
Upper byte of baud rate generator
Miscellaneous control bits
External status interrupt enable control
WR1
WR2
WR3
WR4
WR5
WR6
WR7
2-36
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
Write Register 1
Write Register 0 (non-multiplexed bus mode)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
Register 13
Register 14
Register 15
Null Code
Point High
Reset Ext/Status Interrupts
Send Abort (SDLC)
Enable Int on Next Rx Character
Reset Tx Int Pending
Error Reset
Reset Highest IUS
Ext Int Enable
Tx Int Enable
Parity is Special
Condition
0
0
0
1
1
0
1
1
Rx Int Disable
Rx Int On First Character or
Special Condition
Int On All Rx Characters or
Special Condition
Rx Int On Special Condition Only
*
WAIT/DMA Request
On Receive//Transmit
/WAIT/DMA Request
Function
WAIT/DMA Request
Enable
(b)
Write Register 2
D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
0
1
0
1
Null Code
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx Underrun/EOM Latch
V0
V1
*
With Point High Command
V2
V3
(a)
V4
Interrupt
Vector
V5
V6
V7
(c)
Figure 50. Write Register Bit Functions
DS971800500
PS009701-0301
2-37
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
SCC REGISTERS (Continued)
Write Register 3
D7 D6 D5 D4 D3 D2 D1 D0
Rx Enable
Sync Character Load Inhibit
Address Search Mode (SDLC)
Rx CRC Enable
Enter Hunt Mode
Auto Enables
0
0
1
1
0
1
0
1
Rx 5 Bits/Character
Rx 7 Bits/Character
Rx 6 Bits/Character
Rx 8 Bits/Character
(d)
Write Register 4
Write Register 5
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Parity Enable
Tx CRC Enable
Parity EVEN//ODD
RTS
/SDLC/CRC-16
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Sync Modes Enable
1 Stop Bit/Character
1 1/2 Stop Bits/Character
2 Stop Bits/Character
8-Bit Sync Character
16-Bit Sync Character
SDLC Mode (01111110 Flag)
External Sync Mode
Tx Enable
Send Break
0
0
1
1
0
1
0
1
Tx 5 Bits(Or Less)/Character
Tx 7 Bits/Character
Tx 6 Bits/Character
Tx 8 Bits/Character
DTR
0
0
1
1
0
1
0
1
X1 Clock Mode
X16 Clock Mode
X32 Clock Mode
X64 Clock Mode
(f)
(e)
Figure 50. Write Register Bit Functions (Continued)
2-38
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
Write Register 6
D7 D6 D5 D4 D3 D2 D1 D0
Sync7
Sync1
Sync7
Sync3
ADR7
ADR7
Sync6
Sync0
Sync6
Sync2
ADR6
ADR6
Sync5
Sync5
Sync5
Sync1
ADR5
ADR5
Sync4
Sync4
Sync4
Sync0
ADR4
ADR4
Sync3
Sync3
Sync3
1
ADR3
x
Sync2
Sync2
Sync2
1
ADR2
x
Sync1
Sync1
Sync1
1
ADR1
x
Sync0
Sync0
Sync0
1
ADR0
x
Monosync, 8 Bits
Monosync, 6 Bits
Bisync, 16 Bits
Bisync, 12 Bits
SDLC
SDLC (Address Range)
(g)
Write Register 7
D7 D6 D5 D4 D3 D2 D1 D0
Sync7
Sync5
Sync15
Sync11
0
Sync6
Sync4
Sync14
Sync10
1
Sync5
Sync3
Sync13
Sync9
1
Sync4
Sync2
Sync12
Sync8
1
Sync3
Sync1
Sync11
Sync7
1
Sync2 Sync1
Sync0
x
Sync10 Sync9
Sync6 Sync5
1
1
Sync0
x
Sync8
Sync4
0
Monosync, 8 Bits
Monosync, 6 Bits
Bisync, 16 Bits
Bisync, 12 Bits
SDLC
(h)
Figure 50. Write Register Bit Functions (Continued)
DS971800500
PS009701-0301
2-39
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
SCC REGISTERS (Continued)
Write Register 11
Write Register 9
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
VIS
0
0
1
1
NV
DLC
0
1
0
1
/TRxC Out - Xtal Output
/TRxC Out - Transmit Clock
/TRxC Out - BR Generator Output
/TRxC Out - DPLL Output
MIE
/TRxC O/I
Status High//Status Low
0
0
1
1
0
0
0
1
1
0
1
0
1
No Reset
Reserved
Channel Reset A
Force Hardware Reset
0
0
1
1
0
1
0
1
0
1
0
1
Transmit Clock - /RTxC Pin
Transmit Clock - /TRxC Pin
Transmit Clock - BR Generator Output
Transmit Clock - DPLL Output
Receive Clock - /RTxC Pin
Receive Clock - /TRxC Pin
Receive Clock - BR Generator Output
Receive Clock - DPLL Output
(i)
/RTxC Xtal//No Xtal
(k)
Write Register 10
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 12
6 Bit//8 Bit Sync
D7 D6 D5 D4 D3 D2 D1 D0
Loop Mode
Abort//Flag On Underrun
TC0
Mark//Flag Idle
TC1
Go Active On Poll
0
0
1
1
0
1
0
1
TC2
TC3
NRZ
NRZI
FM1 (Transition = 1)
FM0 (Transition = 0)
TC4
Lower Byte of
Time Constant
TC5
TC6
CRC Preset I//O
TC7
(j)
(l)
Figure 50. Write Register Bit Functions (Continued)
2-40
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
Write Register 13
Write Register 14
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
TC8
BR Generator Enable
TC9
BR Generator Source
TC10
/DTR/Request Function
TC11
TC12
Auto Echo
Upper Byte of
Time Constant
Local Loopback
TC13
0
0
0
0
1
1
1
1
TC14
TC15
(m)
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Null Command
Enter Search Mode
Reset Missing Clock
Disable DPLL
Set Source = BR Generator
Set Source = /RTxC
Set FM Mode
Set NRZI Mode
(n)
Write Register 15
D7 D6 D5 D4 D3 D2 D1 D0
0
Zero Count IE
SDLC FIFO Enable
DCD IE
Sync/Hunt IE
CTS IE
Tx Underrun/EOM IE
Break/Abort IE
(o)
Figure 50. Write Register Bit Functions (Continued)
DS971800500
PS009701-0301
2-41
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
PIA Control Registers
PIA1 Data Direction Register (P1DDR, I/O Address E0h),
PIA1 Data Port (P1DP, I/O address E1h), PIA2 Data Direction Register (P2DDR, I/O Address E2h) and PIA2 Data
Register (P2DP, I/O Address E3h). These four registers are
E0H
7
E2H
6
5
4
3
2
1
7
0
6
5
4
3
2
1
0
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
Figure 51. PIA 1 Data Direction Register
E1H
7
shown in Figures 51-54. Note that if the CTC/PIA bit in the
System Configuration Register is set to one, the CTC I/O
functions override the PIA1 function, and programming of
P1DDR is ignored.
Figure 53. PIA 2 Data Direction Register
E3H
6
5
4
3
2
1
0
7
6
PIA 1
I/O Data
5
4
3
2
1
0
PIA 2
I/O Data
Figure 52. PIA 1 Data Register
Figure 54. PIA 2 Data Register
The Data Port is the register to/from the 8-bit parallel port.
At power on Reset, they are initialized to 1.
a "1", the bit becomes an input, otherwise it is an output. On
reset, these registers are initialized to 1, resulting in all lines
being inputs.
The Data Direction Register has eight control bits. Individual bits specify each bit's direction. When the bit is set to
2-42
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
REGISTERS FOR SYSTEM CONFIGURATION
There are four registers to determine system configuration
with the Z181. These registers are: RAM upper boundary
address register (RAMUBR, I/O address EAh), RAM lower
boundary address register (RAMLBR, I/O address EBh),
ROM address boundary register (ROMBR, I/O address
ECh) and System Configuration Register (SCR, I/O address EDh).
RAMLBR, /RAMCS is asserted. (Figure 13) The A18 signal
from the CPU is taken before it is multiplexed with “TOUT”.
In the case that these register are programmed to overlap,
/ROMCS takes priority over /RAMCS (/ROMCS is asserted
and /RAMCS is inactive).
ROM Address Boundary Register
(ROMBR, I/O Address ECh)
This register specifies the address range for the /ROMCS
signal. When accessed memory addresses are less than
or equal to the value programmed in this register, the
/ROMCS signal is asserted (Figure 55).
/ROMCS: (ROMBR) ≥ A19-A12 ≥ 0
/RAMCS: (RAMUBR) ≥ A19-A12 > (RAMLBR)
The A18 signal from the CPU is obtained before it is
multiplexed with “TOUT”. This signal can be forced to “1”
(inactive state) by setting Bit D5 of the System Configuration Register, to allow the user to overlay the RAM area over
the ROM area. At power-up reset, this register contains all
1's so that /ROMCS is asserted for all addresses.
RAM Lower Boundary Address Register (RAMLBR,
I/O Address EBh) and RAM Upper Boundary
Address Register (RAMUBR, I/O Address EAh)
These two registers specify the address range for the
/RAMCS signal. When accessed memory addresses are
less than or equal to the value programmed in the RAMUBR
and greater than or equal to the value programmed in the
These registers are set to “FFh” at power-on Reset, and the
boundary addresses of ROM and RAM are the following:
ROM lower boundary address
(fixed) = 00000h
ROM upper boundary address
(ROMBR register) = 0FFFFFh
RAM lower boundary address
(RAMLBR register) = 0FFFFFh
RAM upper boundary address
(RAMUBR register) = 0FFFFFh
Since /ROMCS takes priority over /RAMCS, the latter will
never be asserted until the value in the ROMBR and
RAMLBR registers are re-initialized to lower values.
EBH
EAH
7
Chip Select signals are going active for the address range:
6
5
4
3
2
1
7
0
5
4
3
2
1
0
A12
A12
A13
A13
A14
A14
A15
A15
A16
A16
A17
A17
A18
A18
A19
A19
Figure 55. RAM Upper Boundary Register
DS971800500
6
Figure 56. RAM Lower Boundary Register
PS009701-0301
2-43
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
REGISTERS FOR SYSTEM CONFIGURATION (Continued)
ECH
7
6
5
4
3
2
1
0
A12
A13
A14
A15
A16
A17
A18
A19
Figure 57. ROM Boundary Register
EDH
7
6
5
4
3
2
1
0
PIA1/CTIO
1 PIA1 Functions as CTC's I/O Pins
0 PIA1 Functions as I/O Port
Reserved - Program as 0
ROM Emulator Mode (REME)
1 Data Bus in ROM Emulator Mode
0 Data Bus in Normal Mode
Reserved - Program as 0
Reserved - Program as 0
Disable /ROMCS
1 /ROMCS is Disabled
0 /ROMCS is Enabled
Daisy Chain Configuration
1 IEI Pin-CTC-SCC-IEO Pin
0 IEI Pin-SCC-CTC-IEO Pin
Reserved - Program as 0
Figure 58. System Configuration Register
2-44
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
System Configuration Register (I/O address EDh)
This register is to determine the functionality of PIA1 and
the Interrupt Daisy-Chain Configuration (Figure 13). This
register has the following control bits:
Bit D5. Disable /ROMCS. When this bit is set to “1”.
/ROMCS is forced to a “1” regardless of the status of the
address decode logic. This bit’s default (after Reset) is 0
and /ROMCS function is enabled.
Bit D7. Reserved and should be programmed as “0”.
Bit D4-D3. Reserved and should be programmed as “00”.
Bit D6. Daisy-Chain Configuration. Determines the
arrangement of the interrupt priority daisy chain.
Bit D2. ROM Emulator Mode Enable. When this bit is set to
a 1, the Z181 is in “ROM emulator mode”. In this mode, bus
direction for certain transaction periods are set to the
opposite direction to export internal bus transactions outside the Z80181. This allows the use of ROM emulators/
logic analyzers for applications development. This bit’s
default (after Reset) is 0.
When this bit is set to “1”, priority is as follows:
IEI pin - CTC - SCC - IEO pin
When this bit is “0”, priority is as follows:
Bit D1. Reserved and shall be programmed as “0”.
IEI pin - SCC - CTC - IEO pin
This bit’s default (after Reset) is 0.
DS971800500
Bit D0. CTC/PIA1. When this bit is set to “1”, PIA1 functions
as the CTC’s I/O pins. This bit’s default (after Reset) is 0.
PS009701-0301
2-45
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
Data Bus Direction
Table 4 shows the state of the SAC’s data bus when in SAC
bus master condition.
Table 4. Data Bus Direction (Z181 Is Bus Master)
I/O And Memory Transactions
I/O
Write To
On-Chip
Peripherals
(SCC/CTC/
PIA1/PIA2)
I/O
Read From
On-Chip
Peripherals
(SCC/CTC/
PIA1/PIA2)
I/O
Write To
Off-Chip
Peripheral
I/O
Write
Read From To
Off-Chip
Memory
Peripheral
Read
Refresh
From
Memory
Z80181
Idle
Mode
Z80181 Data Bus
(REME Bit = 0)
Out
Z
Out
In
Out
In
Z
Z
Z80181 Data Bus
(REME Bit = 1)
Out
Out
Out
In
Out
In
Z
Z
Interrupt Acknowledge Transaction
Intack For
On-Chip
Intack For
Off-Chip
Peripheral Peripheral
(SCC/CTC)
Z80181 Data Bus
(REME Bit = 0)
Z
In
Z80181 Data Bus
(REME Bit = 1)
Out
In
2-46
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
Table 5 shows the state of the SAC’s data bus when the
Z80181 is NOT in bus master condition.
Table 5. Data Bus Direction for External Bus Master (Z80181 Is Not Bus Master)
I/O And Memory Transactions
I/O
Write To
On-Chip
Peripherals
(SCC/CTC/
PIA1/PIA2)
I/O
Read From
On-Chip
Peripherals
(SCC/CTC/
PIA1/PIA2)
I/O
Write To
Off-Chip
Peripheral
I/O
Write
Read From To
Off-Chip
Memory
Peripheral
Read
Refresh
From
Memory
Z80181
Idle
Mode
Z80181 Data Bus
(REME Bit = 0)
In
Out
Z
Z
Z
In
Z
Z
Z80181 Data Bus
(REME Bit = 1)
In
Out
Z
Z
Z
In
Z
Z
Interrupt Acknowledge Transaction
Intack For Intack For
On-Chip
Off-Chip
Peripheral Peripheral
(SCC/CTC)
Z80181 Data Bus
(REME Bit = 0)
Out
In
Z80181 Data Bus
(REME Bit = 1)
Out
In
The word “OUT” means that the Z181 data bus direction is
in output mode, “IN” means input mode, and “HI-Z” means
high impedance.
DS971800500
“REME” stands for “ROM Emulator Mode” and is the status
of D2 bit in the System Configuration Register.
PS009701-0301
2-47
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
ABSOLUTE MAXIMUM RATINGS
Voltage on V CC with respect to VSS ........... –0.3V to +7.0V
Voltages on all inputs
with respect to VSS ........................... –0.3V to VCC +0.3V
Storage Temperature ............................ –65°C to +150°C
Operating Ambient
Temperature ........................ See Ordering Information
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
STANDARD TEST CONDITIONS
+5V
The DC Characteristics and capacitance sections below
apply for the following standard test conditions, unless
otherwise noted. All voltages are referenced to GND (0V).
Positive current flows into the referenced pin (Figure 59).
Available operating
temperature range is: E = –40°C to +100°C
2.1 K
From Output
Under Test
Voltage Supply Range: +4.50V ≤ Vcc ≤ + 5.50V
All AC parameters assume a load capacitance of 100 pF.
Add 10 ns delay for each 50 pF increase in load up to a
maximum of 150 pF for the data bus and 100 pF for
address and control lines. AC timing measurements are
referenced to 1.5 volts (except for clock, which is referenced to the 10% and 90% points). Maximum capacitive
load for CLK is 125 pF.
2-48
100 pf
250 µA
Figure 59. Standard Test Circuit
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
DC CHARACTERISTICS
Z80181
Symbol
Parameter
Min
V IH1
Input “H” Voltage
/RESET, EXTAL, /NMI
Input “H” Voltage
Except /RESET, EXTAL, /NMI
V IH2
V IL1
V IL2
V OH
V OL
IIL
ITL
ICC*
Cp
Typ
Max
Unit
VCC –0.6
VCC +0.3
V
2.0
VCC +0.3
V
Input “L” Voltage
/RESET, EXTAL, /NMI
Input “L” Voltage
Except /RESET, EXTAL, /NMI
–0.3
0.6
V
–0.3
0.8
V
Output “H” Voltage
All outputs.
Output “L” Voltage
All outputs.
2.4
VCC –1.2
V
Input Leakage
Current All Inputs
Except XTAL, EXTAL
Tri-State Leakage Current
Power Dissipation*
(Normal Operation)
Power Dissipation*
(SYSTEM STOP mode)
Condition
IOH = -200 µA
IOH = – 20 µA
IOL = 2.2 mA
0.45
V
10
µA
V IN = 0.5 – VCC –0.5
10
µA
V IN = 0.5 – VCC –0.5
25
80
f = 10 MHz
6.3
40
f = 10 MHz
Pin Capacitance
12
pF
V IN = 0V, f = 1 MHz
TA = 25°C
Notes:
* VIH Min = VCC -1.0V, VIL Max = 0.8V (all output terminals are at no load.)
VCC = 5.0V
DS971800500
PS009701-0301
2-49
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
AC CHARACTERISTICS
Z180 MPU Timing
Figures 60-68 show the timing for the Z181 MPU and the referenced parameters appear in Table A.
T1
T2
4
Tw
T3
T1
5
3
Ø
2
1
6
Address
70
70
/ROMCS
/RAMCS
20
19
20
19
/WAIT
7
11
/MREQ
8
12
13
/RD
9
14
/M1
10
18
ST
/IORQ
/WR
17
"H"
15
16
Data In
61
62
61
62
/RESET
67
66
67
66
Figure 60a. Opcode Fetch Cycle
2-50
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
T1
T2
Twa
T3
T1
Ø
6
Address
70
70
/ROMCS
/RAMCS
19
20
/WAIT
7
28
11
12
11
/IORQ
27
9
/RD
22
24
25, 25a
/WR
15
16
Data IN
21
23
26
Data OUT
[1]
"H"
ST
[1] Output buffer is off at this point.
[2] Memory Read/Write cycle timing is the same as this figure, except there is
no automatic wait status (Twa), and /MREQ is active instead of /IORQ.
Figure 60b. I/O Read/Write, Memory Read/Write Timing
DS971800500
PS009701-0301
2-51
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
AC CHARACTERISTICS (Continued)
Z180 MPU Timing
Ø
31
30
/INTI
32
/NMI
C7
/INTSCC [4]
/M1 [1]
29
/IORQ [1]
16
15
/Data IN [1]
38
/MREQ [2]
40
39
42
/RFSH [2]
34
34
33
33
/BUSREQ
35
36
/BUSACK
37
37
Address
Data /MREQ,
/RD, /WR,
/IORQ
42
[3]
43
/HALT
Notes:
[1] During /INT0 acknowledge cycle
[2] During refresh cycle
[3] Output buffer is off at this point
[4] Refer to Table C, parameter 7
Figure 61. CPU Timing
(/INT0 Acknowledge Cycle, Refresh Cycle, BUS RELEASE Mode
HALT Mode, SLEEP Mode, SYSTEM STOP Mode)
2-52
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
I/O Read Cycle
T1
T2
Tw
I/O Write Cycle
T3
T1
T2
Tw
T3
Ø
Address
27
28
9
13
27
28
22
24
/IORQ
/RD
/WR
Figure 62. CPU Timing (/IOC = 0)
(I/O Read Cycle, I/O Write Cycle)
DS971800500
PS009701-0301
2-53
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
AC CHARACTERISTICS (Continued)
Z180 MPU Timing
CPU or DMA Read/Write Cycle (Only DMA Write Cycle for /TENDi)
T1
T2
Tw
T3
T1
Ø
44
45
[1]
/DREQi
(At level
sense)
44
45
[2]
/DREQi
(At edge
sence)
18
[4]
46
47
/TENDi
[3]
17
ST
DMA Control Signals
[1]
[2]
[3]
[4]
tDRQS and tDRQH are specified for the rising edge of clock followed by T3.
tDRQS and tDRQH are specified for the rising edge of clock.
DMA cycle starts.
CPU cycle starts.
Figure 63. DMA Control Signals
2-54
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
T1
T2
Tw
Tw
T3
Ø
48
49
E
(Memory
Read/Write)
48
49
E
(I/O Read)
48
49
E
(I/O Read)
15
16
D7-D0
(a) E Clock Timing
(Memory Read/Write Cycle, I/O Read/Write Cycle)
Ø
48
E
48
BUS RELEASE Mode
SLEEP Mode
SYSTEM STOP Mode
(b) E Clock Timing
(BUS RELEASE Mode, SLEEP Mode, SYSTEM STOP Mode)
Figure 64. E Clock Timing
DS971800500
PS009701-0301
2-55
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
AC CHARACTERISTICS (Continued)
Z180 MPU Timing
T2
Tw
T3
T1
T2
Ø
49
48
51
E
(Example:
I/O Read Op-code
Fetch)
49
48
53
52
50
E
(I/O Write)
52
53
Figure 65. E Clock Timing
(Minimum timing example of PWEL and PWEH)
Ø
Timer Data
Reg = 0000H
A18/TOUT
54
Figure 66. Timer Output Timing
2-56
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
SLP Instruction Fetch
T3
Next Op-code Fetch
T1
T2
TS
TS
T1
T2
Ø
31
30
/INTi
/NMI
32
A18-A0
/MREQ, /M1
/RD
42
43
/HALT
Figure 67. SLP Execution Cycle
DS971800500
PS009701-0301
2-57
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
AC CHARACTERISTICS (Continued)
Z180 MPU Timing
CSI/O Clock
55
55
Transmit Data
(Internal Clock)
56
56
11 tcyc
11 tcyc
Transmit Data
(External Clock)
57
58
57
58
Receive Data
(Internal Clock)
11.5 tcyc
11.5 tcyc
16.5 tcyc
16.5 tcyc
Receive Data
(External Clock)
59
60
59
60
Figure 68. CSI/O Receive/Transmit Timing
Table A. Z180 CPU & 180 Peripherals Timing
2-58
Z8018110
Min
Max
No
Symbol
Parameter
1
2
3
4
tcyc
tCHW
tCLW
tcf
Clock Cycle Time
Clock Pulse Width (High)
Clock Pulse Width (Low)
Clock Fall Time
5
6
7
8
9
tcr
tAD
tAS
tMED1
tRDD1
10
tM1D1
Clock Rise Time
Address Valid from Clock Rise
Address Valid to /MREQ, /IORQ Fall
Clock Fall to /MREQ Fall Delay
Clock Fall to /RD Fall (/IOC=1)
Clock Rise to /RD Fall (/IOC=0)
Clock Rise to /M1 Fall Delay
PS009701-0301
100
40
40
2000
10
10
70
10
50
50
55
60
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
Table A. Z180 CPU & 180 Peripherals Timing (Continued)
Z8018110
Min
Max
No
Symbol
Parameter
11
tAH
10
12
13
14
15
tMED2
tRDD2
tM1D2
tDRS
Address Hold Time
(/MREQ, /IORQ, /RD, /WR)
Clock Fall to /MREQ Rise Delay
Clock Fall to /RD Rise Delay
Clock Rise to /M1 Rise Delay
Data Read Setup Time
16
17
18
19
20
tDRH
tSTD1
tSTD2
tWS
tWH
Data Read Hold Time
Clock Fall to ST Fall
Clock Fall to ST Rise
/WAIT Setup Time to Clock Fall
/WAIT Hold time from Clock Fall
0
21
22
23
24
25
tWDZ
tWRD1
tWDO
tWRD2
tWRP
Clock Rise to Data Float Delay
Clock Rise to /WR Fall Delay
/WR fall to Data Out Delay
Clock Fall to /WR Rise
/WR Pulse Width
(Memory Write Cycles)
25a
26
27
tWDH
tIOD1
25
60
60
30
30
60
50
10
50
110
28
tIOD2
29
30
31
32
33
tIOD3
tINTS
tINTH
tNMIW
tBRS
/M1 Fall to /IORQ Fall Delay
/INT Setup Time to Clock Fall
/INT Hold Time from Clock Fall
/NMI Pulse Width
/BUSREQ Setup Time to Clock Fall
200
30
30
80
30
34
35
36
37
tBRH
tBAD1
tBAD2
tBZD
/BUSREQ Hold Time from Clock Fall
Clock Rise to /BUSACK Fall Delay
Clock Fall to /BUSACK Rise Delay
Clock Rise to Bus Floating Delay Time
30
38
39
40
41
42
tMEWH
tMEWL
tRFD1
tRFD2
tHAD1
/MREQ Pulse Width (High)
/MREQ Pulse Width (Low)
Clock Rise to /RFSH Fall Delay
Clock Rise to /RFSH Rise Delay
Clock Rise to /HALT Fall Delay
70
80
43
44
45
46
tHAD2
tDRQS
tDRQH
tTED1
Clock Rise to /HALT Rise Delay
/DREQi Setup Time to Clock Rise
/DREQi Hold Time from Clock Rise
Clock Fall to /TENDi Fall Delay
DS971800500
PS009701-0301
ns
50
50
60
/WR Pulse Width (I/O Write Cycles)
Write Data Hold Time from /WR Rise
Clock Fall to /IORQ Fall Delay
(/IOC=1)
Clock Rise to /IORQ Fall Delay
(/IOC=0)
Clock Fall /IOQR Rise Delay
210
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
ns
ns
ns
55
ns
50
ns
ns
ns
ns
ns
ns
60
60
80
ns
ns
ns
ns
60
60
50
ns
ns
ns
ns
ns
50
30
30
50
ns
ns
ns
ns
2-59
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
AC CHARACTERISTICS (Continued)
Z180™ MPU Timing
Table A. Z180 CPU &180 Peripherals Timing (Continued)
2-60
Z8018110
Min
Max
No
Symbol
Parameter
47
48
49
50
51
tTED2
tED1
tED2
PWEH
PWEL
Clock Fall to /TENDi Rise Delay
Clock Rise to E Rise Delay
Clock Edge to E Fall Delay
E Pulse Width (High)
E Pulse Width (Low)
52
53
54
55
tEr
tEf
tTOD
tSTDI
56
tSTDE
Enable Rise Time
Enable Fall Time
Clock Fall to Timer Output Delay
CSI/O Tx Data Delay Time
(Internal Clock Operation)
CSI/O Tx Data Delay Time
(External Clock Operation)
57
tSRSI
58
tSRHI
59
tSRSE
60
tSRHE
61
62
63
64
65
tRES
tREH
tOSC
tEXr
tEXf
/RESET Setup Time to Clock Fall
/RESET Hold Time from Clock Fall
Oscillator Stabilization Time
External Clock Rise Time (EXTAL)
External Clock Fall Time (EXTAL)
66
67
68
tRr
tRf
tIr
69
tIf
70
TdCS(A)
/RESET Rise Time
/RESET Fall Time
Input Rise Time
(Except EXTAL, /RESET)
Input Fall Time
(Except EXTAL, /RESET)
Address Valid to /ROMCS, /RAMCS
Valid Delay
CSI/O Rx Data Setup Time
(Internal Clock Operation)
CSI/O Rx Data Hold Time
(Internal Clock Operation)
CSI/O Rx Data Setup Time
(External Clock Operation)
CSI/O Rx Data Hold Time
(External Clock Operation)
PS009701-0301
Unit
50
60
60
ns
ns
ns
ns
ns
20
20
150
150
ns
ns
ns
ns
7.5tcyc+150
ns
55
110
1
tcyc
1
tcyc
1
tcyc
1
tcyc
80
50
20
25
25
ns
ns
ms
ns
ns
50
50
100
ns
ns
ns
100
ns
20
ns
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
AC CHARACTERISTICS (Continued)
CTC Timing
Figure 69 shows the timing for the on-chip CTC. Parameters referenced in this figure appear in Table B.
Clock
5
7
6
CLK/TRG
Counter
2
9
8
CLK/TRG
Timer
10
3
11
ZC/TO
1
4
/INT
Figure 69. CTC Timing
Table B. CTC Timing Parameters
Z8018110
Min
Max
No
Symbol
Parameter
1
2
TdCr(INTf)
TsCTRr(Cr)c
3
TsCTR(Ct)
Clock Rise to /INT Fall Delay
CLK/TRG Rise to Clock Rise
Setup Time for Immediate Count
CLK/TRG Rise to Clock Rise
Setup Time for Enabling of Prescaler
On Following Clock Rise
CLK/TRG Rise to /INT Fall Delay
TsCTR(C) Satisfied
TsCTR(C) Not Satisfied
4
TdCTRr(INTf)
5
6
7
8
TcCTR
TwCTRh
TwCTRl
TrCTR
CLK/TRG Cycle Time
CLK/TRG Width (Low)
CLK/TRG Width (High)
CLK/TRG Rise Time
9
10
11
TfCTR
TdCr(ZCr)
TdCf(ZCf)
CLK/TRG Fall Time
Clock Rise to ZC/TO Rise Delay
Clock Fall to ZC/TO Fall Delay
Unit
Note
ns
[B1]
ns
[B2]
90
ns
[B1]
(1)+(3)
TcC+(1)+(3)
ns
ns
[B2]
[B2]
DC
DC
DC
30
ns
ns
ns
ns
[B3]
30
80
80
ns
ns
ns
(TcC+100)
90
(2TcC)
90
90
Notes for Table B:
[B1] Timer Mode
[B2] Counter Mode
[B3] Counter Mode Only. When using a cycle time less than 3TcC, parameter #2 must be met.
DS971800500
PS009701-0301
2-61
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
AC CHARACTERISTICS (Continued)
SCC Timing
Figure 70 shows the AC characteristics for the on-chip
SCC. Parameters referenced in this figure appear in
Table C.
Ø
/WR
/RD
1
/W//REQ
Wait
2
/W//REQ
Request
3
4
/DTR//REQ
Request
5
/INT
6
Figure 70. SCC AC Parameters
Table C. SCC Timing Parameters (85C30 AC Characteristics)
Z8018110
Min
Max
No
Symbol
Parameter
1
2
3
4
TdWR(W)
TdWR(W)
TdWRf(REQ)
TdRDf(REQ)
/WR Fall to Wait Valid Delay
/RD Fall to Wait Valid Delay
/WR Fall to /W//REQ Not Valid Delay
/RD Fall to /W//REQ Not Valid Delay
5
6
7
TdWRr(REQ)
TdPC(INT)
TdRDA(INT)
/WR Rise to /DTR//REQ Not Valid Delay
Clock to /INT Valid Delay
/M1 Fall to /INT Inactive Delay
Unit
Note
180 + TcC
180
180 + TcC
180
ns
ns
ns
ns
[C1]
[C1]
5TcC
500
TBS
ns
ns
ns
[C1]
[C1]
Note for Table C:
[C1] Open-drain output, measured with open-drain test load.
2-62
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
Figure 71 shows the general timing for the on-chip SCC.
Parameters referenced in this figure appear in Table D.
PCLK
1
/W//REQ
Request
2
/W//REQ
Wait
/RTxC, /TRxC
Receive
3
4
6
5
RxD
7
8
/SYNC
External
/TRxC, /RTxC
Transmit
9
10
TxD
11
/TRxC
Output
13
/RTxC
12
14
15, 21
17
/TRxC
16
18, 21
19
/CTS, /DCD
19
20
/SYNC
Input
20
Figure 71. SCC General Timing
DS971800500
PS009701-0301
2-63
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
AC CHARACTERISTICS (Continued)
SCC General Timing
Table D. SCC General Timing Parameters
Z8018110
Min
Max
No
Symbol
Parameter
Unit
Note
1
2
3
4
TdPC(REQ)
TdPC(W)
TsRXD(RXCr)
ThRXD(RXCr)
Clock Fall to /W//REQ Valid
Clock Fall to Wait Inactive
RxD to /RxC Rise Setup Time
RxD to /RxC Rise Hold Time
0
125
ns
ns
ns
ns
[D1]
[D1]
5
6
7
8
TsRXD(RXCf)
ThRXD(RXCf)
TsSY(RXC)
ThSY(RXC)
RxD to /RxC Fall Setup Time
RxD to /RxC Fall Hold Time
/SYNC to /RxC Setup Time
/SYNC to /RxC Hold Time
0
125
–150
5TcC
ns
ns
ns
ns
[D1,4]
[D1,4]
[D1]
[D1]
9
10
11
12
13
TdTXCf(TXD)
TdTXCr(TXD)
TdTXD(TRX)
TwRTXh
TwRTXl
/TxC Fall to TxD Delay
/TxC Rise to TxD Delay
TxD to /TRxC Delay
/RTxC High Width
/RTxC Low Width
ns
ns
ns
ns
ns
[D2]
[D2,4]
120
120
14
15
16
17
TcRTX
TcRTXX
TwTRXh
TwTRXl
/RTxC Cycle Time (RxD, TxD)
Xtal OSC Period
/TRxC High Width
/TRxC Low Width
400
100
120
120
ns
ns
ns
ns
[D5,6]
[D3]
[D5]
[D5]
18
19
20
21
TcTRX
TwEXT
TwSY
TxRx(DPLL)
/TRxC Cycle Time
/DCD or /CTS Pulse Width
/SYNC Pulse Width
DPLL Cycle Time
400
120
100
50
ns
ns
ns
ns
[D5,7]
200
300
150
150
140
1000
[D5]
[D5]
[D6,7]
Notes to Table D:
[D1] /RXC is /RTxC or /TRxC, whichever is supplying the receiver clock.
[D2] /TXC is /TRxC or /RTxC, whichever is supplying the transmitter clock.
[D3] Both /RTxC and /SYNC pins have 30 pF Capacitors (to Ground).
[D4] Parameter applies only to FM encoding/decoding.
[D5] Parameter applies only to transmitter and receiver; baud rate generator timing requirements are different.
[D6] The maximum receive or transmit data rate is 1/4 TcC.
[D7] Applies to DPLL clock source only; maximum data rate of 1/4 TcC still applies.
2-64
PS009701-0301
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
Figure 72 shows the system timing for the on-chip SCC.
Parameters referenced in this figure appear in Table E.
/RTxC, /TRxC
Receive
/W//REQ
Request
1
/W//REQ
Wait
2
/SYNC
Output
3
/INT
4
/RTxC, /TRxC
Transmit
/W//REQ
Request
5
/W//REQ
Wait
6
/DTR//REQ
Request
7
/INT
8
/CTS, /DCD
/SYNC
Input
9
/INT
10
Figure 72. SCC System Timing
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2-65
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
AC CHARACTERISTICS (Continued)
SCC System Timing
Table E. SCC System Timing Parameters
No
Symbol
Parameter
Z8018110
Min
Max
Unit
Note
1
2
3
4
5
TdRxC(REQ)
TdRxC(W)
TdRxC(SY)
TdRxC(INT)
TdTxC(REQ)
/RxC to /W//REQ Valid
/RxC to Wait inactive
/RxC to /SYNC Valid
/RxC to /INT Valid
/TxC to /W//REQ Valid
8
8
4
10
5
12
14
7
16
8
TcC
TcC
TcC
TcC
TcC
[E2]
[E1,2]
[E2]
[E1,2]
[E3]
6
7
8
9
10
TdTxC(W)
TdRxC(DRQ)
TdTxC(INT)
TdSY(INT)
TdEXT(INT)
/TxC to Wait inactive
/TxC to /DTR//REQ Valid
/TxC to /INT Valid
/SYNC to /INT Valid
/DCD or /CTS to /INT Valid
5
4
6
2
2
11
7
10
6
6
TcC
TcC
TcC
TcC
TcC
[E1,3]
[E3]
[E1,3]
[E1]
[E1]
Notes for Table E:
[E1] Open-drain output, measured with open-drain test load.
[E2] /RXC is /RTxC or /TRxC, whichever is supplying the receiver clock.
[E3] /TXC is /TRxC or /RTxC, whichever is supplying the transmitter clock.
2-66
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DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
AC CHARACTERISTICS (Continued)
PIA General-Purpose I/O Port Timing
Figure 73 shows the timing for the PIA ports. Parameters
referenced in this figure appear in Table F.
T1
T2
Tw
T3
Ø
/IORQ, /RD
1
PIA Input
2
PIA Output
Figure 73. PIA Timing
Table F. PIA General-Purpose I/O Timing Parameters
Z8018110
Min
Max
No
Symbol
Parameter
1
2
TsPIA(C)
TdCr(PIA)
PIA Data Setup time to Clock Rise
Clock Rise to PIA Data Valid Delay
DS971800500
PS009701-0301
10
50
Unit
ns
ns
2-67
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
AC CHARACTERISTICS (Continued)
Interrupt Daisy-Chain Timing
Figure 74 shows the interrupt daisy-chain timing. Parameters referenced in this figure appear in Table G.
CLK
1
3
/M1
/IORQ
2
5
4
Data
6
IEI
7, 8
IEO
9
/INT
(SCC)
11
/WAIT
10
Figure 74. Interrupt Daisy-Chain Timing
Table G. Interrupt Daisy-Chain Timing Parameters
2-68
No
Symbol
Parameter
Z8018110
Min
Max
1
TsM1(Cr)
/M1 Fall to Clock Rise Setup Time
20
ns
2
TsM1(IO)INTA
Th
TdM1r(DOz)
TdCr(DO)
2TcC
0
0
ns
3
4
5
/M1 Fall to /IORQ Fall Setup Time
(During INTACK Cycle)
Hold Time
/M1 Rise to Data Out Float Delay
Clock Rise to Data Out Delay
ns
6
7
8
9
10
11
TsIEI(TW4)
TdIEIf(IEOf)
TdIEIr(IEOr)
TdM1f(IEOf)
TdCWA(f)INTA
TdCWA(r)INTA
IEI to TW4 Rise Setup Time
IEI Fall to IEO Fall Delay
IEO Rise to IEO Rise Delay
/M1 Fall to IEO Fall Delay
Clock Rise to /WAIT Fall Delay
Clock Rise to /WAIT Rise Delay
95
ns
PS009701-0301
Unit
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
Note for Interrupt Acknowledge Cycle and
Daisy Chain
When using the interrupt daisy chained device(s) for other
than the Z181 (without external logic), the following restrictions/notes apply:
The device(s) must be connected to the higher priority
location (Figure 75).
The device(s) IEI-IEO delay must be less than two clock
cycles.
The Z181 on-chip interface logic inserts another three wait
states into the interrupt acknowledge cycle to meet the onchip SCC and the Z80 CTC timing requirements. (For a
total of five wait states, including the two automatically
inserted wait states).
To meet the timing requirements, the Z181’s on-chip circuit
generates interface signals for the SCC and CTC.
Figure 78 has the timing during the interrupt acknowledge
cycle, including the internally generated signals.
The following are three separate cases for the daisy-chain
settle times:
Case 1 - SCC: The SCC /INTACK signal goes active on the
T1 clock fall time. The settle time is from SCC /INTACK
active until the SCC /RD signal goes active on the fourth
rising wait state clock.
Case 2 - CTC: The settle time for the on-chip /IORQ is
between the fall of /M1 until the internal CTC /IORQ goes
active on the rise of the fourth wait state (the same time as
SCC /RD goes active).
Case 3 - OFF-chip Z80 Peripheral: The settle time for the
off-chip Z80 peripheral is from the fall of /M1 until CTC
/IORQ goes active. Since the Z181’s external /IORQ signal
goes active on the clock fall of the first automatically
inserted wait state (TWA ), the external daisy-chain device
must be connected to the upper chain location. Also, it
must settle within two clock cycles.
If any peripheral is connected externally with a lower daisy
chain priority than Z181 peripherals, /IORQ must be delayed by external logic as shown in Figure 79.
Vcc
IEI
Peripheral
Device(s)
IEO
IEI
CTC
IEO
IEI
SCC
IEO
Z80181
Figure 75. Peripheral Device as Part of the Daisy Chain
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2-69
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
AC CHARACTERISTICS (Continued)
Read Write External BUS Master Timing
CLK
1
Address
A7-A0
2
3
4
3
/IORQ
10
/RD
11
5
6
Data
Data OUT
3
7
/WR
12
8
Data
9
Data IN
Figure 76. Read/Write External BUS Master Timing
Table H. External Bus Master Interface Timing (Read/Write Cycles)
2-70
Z8018110
Min
Max
No
Symbol
Parameter
1
2
3
4
5
TsA(Cr)
TsIO(Cr)
Th
TsRD(Cr)
TdRD(DO)
Address to CLK Rise Setup Time
/IORQ Fall to CLK Rise Setup Time
Hold Time
/RD Fall to CLK Rise Setup Time
/RD Fall to Data Out Delay
20
20
0
20
6
7
8
9
TdRIr(DOz)
TsWR(Cr)
TsDi(WRf)
ThWIr(Di)
/RD, /IORQ Rise to Read Data Float
/WR Fall to CLK Rise Setup Time
Data in to /WR Fall Setup Time
/IORQ, /WR Rise to Data In Hold Time
0
20
0
0
10
11
12
TsA(IORQf)
TsA(RDf)
TsA(WRf)
Address to /IORQ Fall Setup Time
Address to /RD Fall Setup Time
Address to /WR Fall Setup Time
50
50
50
PS009701-0301
Unit
ns
ns
120
ns
ns
ns
ns
ns
ns
DS971800500
Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
SCC External BUS Master Timing
Valid SCC
Addr * IORQ
1
/RD or
/WR
2
DTR/REQ
Request
Figure 77. SCC External BUS Master Timing
Table I. External Bus Master Interface Timing (SCC Related Timing)
Z8018110
Min
Max
No
Symbol
Parameter
1
2
TrC
TdRDr(REQ)
Valid Access Recovery Time
/RD Rise to /DTR//REQ Not Valid Delay
4TcC
4TcC
Unit
Notes
ns
ns
[1]
Note for Table I:
[1] Only applies between transactions involving the SCC.
DS971800500
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SMART ACCESS CONTROLLER SAC™
Zilog
AC CHARACTERISTICS (Continued)
T1
T2
T WA
T WA
TW
TW
TW
T3
CLK
Settle Time for
Off-chip Z80
Peripherals
/M1
Settle Time for
On-chip CTC
/IORQ
Settle Time
for SCC
SCC
/INTACK
/WAIT Signal generated
by interface circuit
/WAIT
SCC
/RD
CTC
/IORQ
Figure 78. Interrupt Acknowledge Cycle Timing
Vcc
IEI
CTC
IEO
IEI
SCC
IEO
IEI
Peripheral
Device(s)
IEO
/IORQ
Z80181
External
Logic to
Extend
/IORQ
Signal
Figure 79. Peripheral Device as Part of the Daisy Chain
2-72
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Z80181
S MART A CCESS C ONTROLLER SAC™
Zilog
PACKAGE INFORMATION
100-Pin QFP Package Diagram
DS971800500
PS009701-0301
2-73
Z80181
SMART ACCESS CONTROLLER SAC™
Zilog
ORDERING INFORMATION
Z80181 (10 MHz)
Extended Temperature
100-Pin QFP
Z8018110FEC
Package
Longer Lead Time
F = Plastic Quad Flat Pack
Temperature
Longer Lead Time
E = –40°C to +100°C
Environmental
C = Plastic Standard
Speed
10 = 10 MHz
Example:
Z 80181 10 F E C
is a Z80181, 10 MHz, QFP, –40°C to +100°C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
© 1997 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
2-74
Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
Internet: http://www.zilog.com
PS009701-0301
DS971800500
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