Z80C30/Z85C30
CMOS SCC Serial
Communications
Controller
Product Specification
PS011708-0115
Copyright ©2015 Zilog®, Inc. All rights reserved.
www.zilog.com
CMOS SCC Serial Communications Controller
Product Specification
ii
Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
LIFE SUPPORT POLICY
ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
©2015 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. Zilog, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. Zilog ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
Z8 is a registered trademark of Zilog, Inc. All other product or service names are the property of their
respective owners.
PS011708-0115
CMOS SCC Serial Communications Controller
Product Specification
iii
Revision History
Each instance in Revision History reflects a change to this document from its previous
revision. For more details, refer to the corresponding pages and appropriate links in the
following table.
Revision
Level
Description
Page
Jan
2015
08
Updated the Ordering Information chapter to delete Z80C3008PSG and
Z80C3010PSG, which are EOL status.
75
Oct
2012
07
Corrected state of RTSB pin on Z85C30 DIP package; corrected name of
PCLK pin on Z85C30 PLCC package.
11, 12
May
2011
06
Corrected Ordering Information chapter to reflect lead-free parts; updated
logo and style to conform to current template.
75, all
Jun
2008
05
Updated Zilog logo, Zilog Text, Disclaimer as per latest template.
All
Aug
2001
01
Original issue
All
Date
PS011708-0115
Revision History
CMOS SCC Serial Communications Controller
Product Specification
iv
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .viii
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Z85C30-Only Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
CTSA, CTSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DCDA, DCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DTR/REQA, DTR/REQB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
IEI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
IEO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
INT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
INTACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
RxDA, RxDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
RTxCA, RTxCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
RTSA, RTSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SYNCA, SYNCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TxDA, TxDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TRxCA, TRxCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
W/REQA, W/REQB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Z85C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
A/B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
D7–D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
D/C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Z80C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
AD7–AD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
AS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PS011708-0115
Table of Contents
CMOS SCC Serial Communications Controller
Product Specification
v
R/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Interface Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU/DMA Block Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCC Data Communications Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Echo and Local Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDLC FIFO Frame Status FIFO Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z85C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z80C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z85C30/Z80C30 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z85C30 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z80C30 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
16
18
18
21
22
22
23
26
26
27
28
29
32
32
33
33
40
43
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
47
47
49
49
49
50
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Part Number Suffix Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PS011708-0115
Table of Contents
CMOS SCC Serial Communications Controller
Product Specification
vi
List of Figures
Figure 1. SCC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Z85C30 and Z80C30 DIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3. Z85C30 and Z80C30 PLCC Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4. Z85C30 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Z80C30 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. SCC Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. SCC Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. SCC Interrupt Priority Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. SCC Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Detecting 5- or 7-Bit Synchronous Characters . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. An SDLC Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Data Encoding Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13. SDLC Frame Status FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14. SDLC Byte Counting Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15. Write Register Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 16. Write Register Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 17. Write Register Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 18. Write Register Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 19. Read Register Bit Functions, #1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 20. Read Register Bit Functions, #2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 21. Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 22. Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 23. Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 24. Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 25. Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 26. Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 27. Standard Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 28. Open-Drain Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PS011708-0115
List of Figures
CMOS SCC Serial Communications Controller
Product Specification
vii
Figure 29. Z85C30 Read/Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 30. Z85C30 Interrupt Acknowledge Timing Diagram . . . . . . . . . . . . . . . . . . . . . 52
Figure 31. Z85C30 Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 32. Z85C30 Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 33. Z85C30 General Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 34. Z85C30 System Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 35. Z80C30 Read/Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 36. Z80C30 Interrupt Acknowledge Timing Diagram . . . . . . . . . . . . . . . . . . . . . 65
Figure 37. Z80C30 Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 38. Z80C30 General Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 39. Z80C30 System Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 40. 40-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 41. 44-Pin PLCC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
PS011708-0115
List of Figures
CMOS SCC Serial Communications Controller
Product Specification
viii
List of Tables
Table 1. SCC Read Register Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 2. SCC Write Register Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 4. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 5. Z80C30/Z85C30 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 6. Z85C30 Read/Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 7. Z85C30 General Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 8. Z85C30 System Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 9. Z85C30 Read/Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 10. Z80C30 Read/Write Timing1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 11. Z80C30 General Timing1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 12. Z80C30 System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 13. Z80C30/Z85C30 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
PS011708-0115
List of Tables
CMOS SCC Serial Communications Controller
Product Specification
1
Overview
The features of Zilog’s Z80C30 and Z85C30 devices include:
•
•
•
•
Z85C30: optimized for nonmultiplexed bus microprocessors
•
Multiprotocol operation under program control; programmable for NRZ, NRZI or FM
data encoding
•
Asynchronous Mode with 5 to 8 bits and 1, 1½, or 2 stop bits per character, programmable clock factor, break detection and generation; parity, overrun, and framing error
detection
•
Synchronous Mode with internal or external character synchronization on 1 or 2 synchronous characters and CRC generation and checking with CRC-16 or CRC-CCITT
preset to either 1s or 0s
•
SDLC/HDLC Mode with comprehensive frame-level control, automatic zero insertion
and deletion, I-Field residue handling, abort generation and detection, CRC generation
and checking, and SDLC loop
•
•
•
•
Software interrupt acknowledge feature (not available with NMOS)
•
Speeds
– Z85C3O: 8.5, 10, 16.384 MHz
– Z80C3O: 8, 10 MHz
Z80C30: optimized for multiplexed bus microprocessors
Pin-compatible to NMOS versions
Two independent 0 to 4.1 Mbps, full-duplex channels, each with separate crystal oscillator, Baud Rate Generator (BRG), and Digital Phase-Locked Loop (DPLL) for clock
recovery
Local Loopback and Auto Echo modes
Supports T1 Digital Trunk76
Enhanced DMA support (not available with NMOS), 10 x 19-bit status FIFO, 14-bit
byte counter
Z85C30-Only Features
Some of the features listed below are available by default. Some of them (features with *)
are disabled on default to maintain compatibility with the existing Serial Communications
Controller (SCC) design, and program to enable through WR7:
PS011708-0115
Overview
CMOS SCC Serial Communications Controller
Product Specification
2
PS011708-0115
•
•
New programmable Write Register 7 prime (WR7) to enable new features
•
Improved AC timing:
– 3 to 3.6 PCLK access recovery time
– Programmable DTR/REQ timing
– Write data to falling edge of WR setup time requirement is now eliminated
– Reduced INT timing
•
Other features include:
– Extended read function to read back the written value to the write registers
– Latching RRO during read
– RRO, bit D7 and RR10, bit D6 now has reset default value
Improvements to support the SDLC Mode of synchronous communication:
– Improve functionality to ease sending back-to-back frames
– Automatic SDLC opening Flag transmission
– Automatic Tx Underrun/EOM Latch reset in SDLC Mode
– Automatic RTS deactivation
– TxD pin forced High in SDLC NRZI Mode after closing flag
– Complete CRC reception
– Improved response to Abort sequence in status FIFO
– Automatic Tx CRC generator preset/reset
– Extended read for write registers
– Write data set-up timing improvement
Overview
CMOS SCC Serial Communications Controller
Product Specification
3
General Description
The Z80C30/Z85C30 Serial Communications Controller (SCC), is a pin and software
compatible CMOS member of the SCC family introduced by Zilog in 1981. It is a dualchannel, multiprotocol data communications peripheral that easily interfaces with CPU’s
with either multiplexed or nonmultiplexed address/data buses.
The advanced CMOS process offers lower power consumption, higher performance, and
superior noise immunity. The programming flexibility of the internal registers allow the
SCC to be configured to various serial communications applications.
The many on-chip features such as Baud Rate Generators (BRG), Digital Phase Locked
Loops (DPLL), and crystal oscillators reduce the need for an external logic.
Additional features include a 10 x 19-bit status FIFO and 14-bit byte counter to support
high speed SDLC transfers using DMA controllers.
The SCC handles asynchronous formats, synchronous byte-oriented protocols such as
IBM Bisync, and synchronous bit-oriented protocols such as HDLC and IBM SDLC. This
device supports virtually any serial data transfer application (for example, cassette, diskette, tape drives, etc.).
The device generates and checks CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The SCC also contains facilities for
modem controls in both channels. In applications where these controls are not required,
the modem controls can be used for general-purpose I/O. The daisy-chain interrupt hierarchy is also supported.
Figure 1 shows a block diagram of the SCC.
PS011708-0115
General Description
CMOS SCC Serial Communications Controller
Product Specification
4
Transmit Logic
Transmit MUX
Transmit
Buffer
TxDA
Data Encoding & CRC
Generation
Channel A
Exploded View
Receive and Transmit Clock Multiplexer
TRxCA
RTxCA
Crystal
Oscillator
Amplifier
Digital
Baud Rate
Phase-Locked Generator
Loop
CTSA
DCDA
Modem/Control Logic
SYNCA
RTSA
DTRA/REQA
Receive Logic
Rec. Status Rec. Status
FIFO 3 Byte FIFO 3 Byte
SDLC Frame Status FIFO
10 X 19
Databus
Receive MUX
RxDA
CRC Checker
Data Decode &
Sync Character
Detection
Interrupt
Control
Logic
Channel A
Register
Interrupt
Control
Logic
Channel B
Register
Channel A
CPU & DMA
Bus Interface
Control
Interrupt
Control
INT
INTACK
IEI
IEO
Channel B
Figure 1.SCC Block Diagram
PS011708-0115
General Description
CMOS SCC Serial Communications Controller
Product Specification
5
Pin Descriptions
The following links refer to descriptions of the pin functions common to the Z85C30 and
Z80C30 devices.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CTSA, CTSB
DCDA, DCDB
DTR/REQA, DTR/REQB
IEI
IEO
INT
INTACK
PCLK
RxDA, RxDB
RTxCA, RTxCB
RTSA, RTSB
SYNCA, SYNCB
TxDA, TxDB
TRxCA, TRxCB
W/REQA, W/REQB
CTSA, CTSB
Clear To Send (inputs, active Low) . If these pins are programmed for Auto Enable
functions, a Low on the inputs enables the respective transmitters. If not programmed as
Auto Enable, these pins can be used as general-purpose inputs. Both inputs are Schmitttrigger buffered to accommodate slow rise-time inputs. The SCC detects pulses on these
inputs and can interrupt the CPU on both logic level transitions.
DCDA, DCDB
Data Carrier Detect (inputs, active Low) . These pins function as receiver enables if
programmed for Auto Enable. Otherwise, these pins are used as general-purpose input
pins. Both pins are Schmitt-trigger buffered to accommodate slow rise-time signals. The
SCC detects pulses on these pins and can interrupt the CPU on both logic level transitions.
PS011708-0115
Pin Descriptions
CMOS SCC Serial Communications Controller
Product Specification
6
DTR/REQA, DTR/REQB
Data Terminal Ready/Request (outputs, active Low) . These outputs follow the state
programmed into the DTR bit. They can also be used as general-purpose outputs or as
Request lines for a DMA controller.
IEI
Interrupt Enable In (input, active High) . IEI is used with IEO to form an interrupt
daisy-chain when there is more than one interrupt driven device. A high IEI indicates that
no other higher priority device has an interrupt under service or is requesting an interrupt.
IEO
Interrupt Enable Out (output, active High) . IEO is High only if IEI is High and the
CPU is not servicing the SCC interrupt or the SCC is not requesting an interrupt (interrupt
Acknowledge cycle only). IEO is connected to the next lower priority device’s IEI input
and thus inhibits interrupts from lower priority devices.
INT
Interrupt Request (output, open-drain, active Low) . This signal activates when the
SCC requests an interrupt.
INTACK
Interrupt Acknowledge (input, active Low) . This signal indicates an active Interrupt
Acknowledge cycle. During this cycle, the SCC interrupt daisy chain settles. When RD is
active, the SCC places an interrupt vector on the data bus (if IEI is High). INTACK is
latched by the rising edge of PCLK.
PCLK
Clock (input) . This is the master SCC clock used to synchronize internal signals. PCLK
is a TTL level signal. PCLK is not required to have any phase relationship with the master
system clock. The maximum transmit rate is 1/4 PCLK.
RxDA, RxDB
Receive Data (inputs, active High) . These signals receive serial data at standard TTL
levels.
PS011708-0115
Pin Descriptions
CMOS SCC Serial Communications Controller
Product Specification
7
RTxCA, RTxCB
Receive/Transmit Clocks (inputs, active Low) . These pins can be programmed in sev-
eral different operating modes. In each channel, RTxC can supply the receive clock, the
transmit clock, clock for the Baud Rate Generator, or the clock for the Digital PhaseLocked Loop. These pins can also be programmed for use with the respective SYNC pins
as a crystal oscillator. The receive clock can be 1, 16, 32, or 64 times the data rate in Asynchronous modes.
RTSA, RTSB
Request To Send (outputs, active Low) . When the Request To Send (RTS) bit in Write
Register 5 is set (see Figure 9 on page 22), the RTS signal goes Low. When the RTS bit is
reset in Asynchronous Mode and Auto Enable is ON, the signal goes High after the transmitter is empty. In Synchronous Mode, it strictly follows the state of the RTS bit. When
Auto Enable is OFF, the RTS pins can be used as general-purpose outputs.
SYNCA, SYNCB
Synchronization (inputs or outputs, active Low) . These pins function as inputs, out-
puts, or part of the crystal oscillator circuit. In the Asynchronous Receive Mode (crystal
oscillator option not selected), these pins are inputs similar to CTS and DCD. In this
mode, transitions on these lines affect the state of the Synchronous/Hunt status bits in
Read Register 0 (see Figure 8 on page 19) but have no other function.
In External Synchronization Mode with the crystal oscillator not selected, these lines also
act as inputs. In this mode, SYNC must be driven Low for two receive clock cycles after
the last bit in the synchronous character is received. Character assembly begins on the rising edge of the receive clock immediately preceding the activation of SYNC.
In the Internal Synchronization Mode (Monosync and Bisync) with the crystal oscillator
not selected, these pins act as outputs and are active only during the part of the receive
clock cycle in which synchronous characters are recognized. This synchronous condition
is not latched. These outputs are active each time a synchronization pattern is recognized
(regardless of character boundaries). In SDLC Mode, these pins act as outputs and are
valid on receipt of a flag.
TxDA, TxDB
Transmit Data (outputs, active High) . These output signals transmit serial data at stan-
dard TTL levels.
PS011708-0115
Pin Descriptions
CMOS SCC Serial Communications Controller
Product Specification
8
TRxCA, TRxCB
Transmit/Receive Clocks (inputs or outputs, active Low). These pins can be pro-
grammed in several different operating modes. TRxC may supply the receive clock or the
transmit clock in the input mode or supply the output of the Digital Phase-locked loop, the
crystal oscillator, the Baud Rate Generator, or the transmit clock in the output mode.
W/REQA, W/REQB
Wait/Request (outputs, open-drain when programmed for a Wait function, driven
High or low when programmed for a Request function). These dual-purpose outputs
can be programmed as Request lines for a DMA controller or as Wait lines to synchronize
the CPU to the SCC data rate. The reset state is Wait.
Z85C30
The following links refer to descriptions of the pin functions specific to the Z85C30
device.
•
•
•
•
•
•
A/B
CE
D7–D0
D/C
RD
WR
A/B
Channel A/Channel B (input). This signal selects the channel in which the read or write
operation occurs.
CE
Chip Enable (input, active Low). This signal selects the SCC for a read or write opera-
tion
PS011708-0115
Pin Descriptions
CMOS SCC Serial Communications Controller
Product Specification
9
D7–D0
Data Bus (bidirectional, tri-state) . These lines carry data and command to and from the
SCC.
D/C
Data/Control Select (input) . This signal defines the type of information transferred to or
from the SCC. A High indicates a data transfer; a Low indicates a command.
RD
Read (input, active Low) . This signal indicates a read operation and when the SCC is
selected, enables the SCC’s bus drivers. During the Interrupt Acknowledge cycle, this signal gates the interrupt vector onto the bus if the SCC is the highest priority device requesting an interrupt.
WR
Write (input, active Low) . When the SCC is selected, this signal indicates a write operation. The coincidence of RD and WR is interpreted as a reset.
Z80C30
The following links refer to descriptions of the pin functions specific to the Z80C30
device.
•
•
•
•
•
•
AD7–AD0
AS
CS0
CS1
DS
R/W
AD7–AD0
Address/Data Bus (bidirectional, active High, Tri-state) . These multiplexed lines
carry register addresses to the SCC as well as data or control information.
PS011708-0115
Pin Descriptions
CMOS SCC Serial Communications Controller
Product Specification
10
AS
Address Strobe (input, active Low) . Addresses on AD7–AD0 are latched by the rising
edge of this signal.
CS0
Chip Select 0 (input, active Low) . This signal is latched concurrently with the
addresses on AD7–AD0 and must be active for the intended bus transaction to occur.
CS1
Chip Select 1 (input, active High) . This second select signal must also be active before
the intended bus transaction can occur. CS1 must remain active throughout the transaction.
DS
Data strobe (input, active Low) . This signal provides timing for the transfer of data into
and out of the SCC. If AS and DS coincide, this confluence is interpreted as a reset.
R/W
Read/Write (input) . This signal specifies whether the operation to be performed is a read
or a write.
PS011708-0115
Pin Descriptions
CMOS SCC Serial Communications Controller
Product Specification
11
Pin Diagrams
Figure 2 shows the pin assignments for the Z85C30 and Z80C30 DIP packages.
D1
1
40
D0
AD1
1
40
D3
2
39
AD0
D2
AD3
2
39
D5
3
38
AD2
D4
AD5
3
38
AD4
D7
4
37
D6
AD7
4
37
AD6
INT
5
36
RD
INT
5
36
DS
IEO
6
35
WR
IEO
6
35
AS
IEI
7
34
A/B
IEI
7
34
R/W
INTACK
8
33
CE
INTACK
8
33
CS0
+5V
9
32
D/C
+5V
9
32
CS1
31
GND
31
GND
Z85C30
W/REQA
10
SYNCA
11
30
RTxCA
12
RxDA
Z80C30
W/REQA
10
W/REQB
SYNCA
11
30
W/REQB
29
SYNCB
RTxCA
12
29
SYNCB
13
28
RTxCB
RxDA
13
28
RTxCB
TRxCA
14
27
RxDB
TRxCA
14
27
RxDB
TxDA
15
26
TRxCB
TxDA
15
26
TRxCB
DTR/REQA
16
25
TxDB
DTR/REQA
16
25
TxDB
RTSA
17
24
DTR/REQB
RTSA
17
24
DTR/REQB
CTSA
18
23
RTSB
CTSA
18
23
RTSB
DCDA
19
22
CTSB
DCDA
19
22
CTSB
PCLK
20
21
DCDB
PCLK
20
21
DCDB
Figure 2.Z85C30 and Z80C30 DIP Pin Assignments
PS011708-0115
Pin Descriptions
CMOS SCC Serial Communications Controller
Product Specification
12
6 5 4 3 2 1 44 43 42 41 40
7
39
38
8
9
37
10
36
11
35
34
Z85C30
12
33
13
14
32
15
31
16
30
29
17
18 19 20 21 22 2324 25 26 27 28
NC
DTR/REQA
RTSA
CTSA
DCDA
PCLK
DCDB
CTSB
RTSB
DTR/REQB
NC
IEO
IEI
INTACK
+5V
W/REQA
SYNCA
RTxCA
RxDA
TRxCA
TxDA
NC
A/B
CE
D/C
NC
GND
W/REQB
SYNCB
RTxCB
RxDB
TRxCB
TxDB
IEO
IEI
INTACK
+5V
W/REQA
SYNCA
RTxCA
RxDA
TRxCA
TxDA
NC
6 5 4 3 2 1 44 43 42 41 40
7
39
38
8
9
37
10
36
11
35
34
Z80C30
12
33
13
14
32
15
31
16
30
29
17
18 19 20 21 22 2324 25 26 27 28
R/W
CS0
CS1
NC
GND
W/REQB
SYNCB
RTxCB
RxDB
TRxCB
TxDB
NC
DTR/REQA
RTSA
CTSA
DCDA
PCLK
DCDB
CTSB
RTSB
DTR/REQB
NC
INT
D7
D5
D3
D1
D0
D2
D4
D6
RD
WR
INT
AD7
AD5
AD3
AD1
AD0
AD2
AD4
AD6
DS
AS
Figure 3 shows the pin assignments for the Z85C30 and Z80C30 PLCC packages.
Figure 3.Z85C30 and Z80C30 PLCC Pin Assignments
PS011708-0115
Pin Descriptions
CMOS SCC Serial Communications Controller
Product Specification
13
Figures 4 and show the pin functions for the Z85C30 and Z80C30 devices, respectively.
Descriptions for each of these pins can be found in the Functional Descriptions chapter on
page 15.
Data Bus
Bus Timing
and Reset
Control
Interrupt
D7
TxDA
D6
RxDA
D5
TRxCA
D4
RTxCA
D3
SYNCA
D2
W/REQA
D1
DTR/REQA
D0
RTSA
RD
CTSA
WR
Z85C30
TxDB
CE
RxDB
D/C
TRxCB
INT
RTxCB
IEO
Channel
Controls
for Modem,
DMA and
Other
CH-A
Serial
Data
Channel
Clocks
SYNCB
CH-B
W/REQB
IEI
Channel
Clocks
DCDA
A/B
INTACK
Serial
Data
DTR/REQB
RTSB
CTSB
Channel
Controls
for Modem,
DMA and
Other
DCDB
Figure 4.Z85C30 Pin Functions
PS011708-0115
Pin Descriptions
CMOS SCC Serial Communications Controller
Product Specification
14
Data Bus
Bus Timing
and Reset
Control
Interrupt
AD7
TxDA
AD6
RxDA
AD5
TRxCA
AD4
RTxCA
AD3
SYNCA
AD2
W/REQA
AD1
DTR/REQA
AD0
RTSA
AS
CTSA
DS
Z80C30
TxDB
CS1
RxDB
CS0
TRxCB
INT
RTxCB
INTACK
SYNCB
IEO
Channel
Clocks
Channel
Controls
for Modem,
DMA and
Other
CH-A
DCDA
R/W
IEI
Serial
Data
Serial
Data
Channel
Clocks
CH-B
W/REQB
DTR/REQB
RTSB
CTSB
Channel
Controls
for Modem,
DMA and
Other
DCDB
Figure 5.Z80C30 Pin Functions
PS011708-0115
Pin Descriptions
CMOS SCC Serial Communications Controller
Product Specification
15
Functional Descriptions
The architecture of the SCC device functions as:
•
•
A data communications device which transmits and receives data in various protocols
A microprocessor peripheral in which the SCC offers valuable features such as vectored interrupts and DMA support
The SCC’s peripheral and data communication features are described in the following sections.
Figure 1 on page 4 shows a SCC block diagram; Figures 6 and 7 show the details of the
communication between the receive and transmit logic to the system bus. The features and
data path for each of the SCC’s A and B channels are identical.
Internal Data Bus
To Other Channel
Internal TXD
WR6
WR7
SYNC
Register SYNC
WRB
TX Buffer
1 Byte
Register
Final TX
MUX
20-Bit TX Shift Register
TXD
Sync
Sync
Zero Insert
(5 Bits)
SDLC
Transmit
MUX & 2-Bit
Delay
NRZ
Encode
Transmit Clock
CRC-Gen
From Receiver
Figure 6. SCC Transmit Data Path
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
16
CPU/I/O
I/O Data buffer
Internal Data Bus
Upper Byte (WR13)
Time Constant
BRG
Input
Status FIFO
10 X 19 Frame
Lower Byte (WR12)
Time Constant
16-Bit Down Counter
Rec. Error FIFO
3 Byte Deep
Rec. Error FIFO
3 Byte Deep
BRG
Output
DIV 2
14-Bit Counter
Rec. Error Logic
Hunt Mode (BISYNC)
DPLL
IN
DPLL
OUT
DPLL
SYNC Register
& Zero Delete
3-Bit
Receive Shift
Register
Internal TXD
1-Bit
RXD
MUX
NRZI Decode
CRC Delay
Register (8 bits)
MUX
To Transmit Section
SDLC-CRC
CRC
Checker
SYNC
CRC
CRC Result
Figure 7. SCC Receive Data Path
I/O Interface Capabilities
System communication to and from the SCC device is performed through the SCC’s register set. There are sixteen write registers and eight read registers.
Throughout this document, write and read registers are referenced with the following
notation:
•
•
PS011708-0115
WR for write registers
RR for read registers
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
17
For example:
WR4A
Write Register 4 for channel A
RR3
Read Register 3 for either/both channels
Tables 1 and 2 list the SCC registers and provide a brief description of their functions.
Table 1. SCC Read Register Functions
Register
Function
RR0
Transmit/Receive buffer status and External status
RR1
Special Receive Condition status
RR2
Modified interrupt vector (Channel B only) Unmodified interrupt vector (Channel A only)
RR3
Interrupt Pending bits (Channel A only)
RR8
Receive Buffer
RR10
Miscellaneous status
RR12
Lower byte of Baud Rate Generator time constant
RR13
Upper byte of Baud Rate Generator time constant
RR15
External/Status interrupt information
Table 2. SCC Write Register Functions
Register
Function
WR0
CRC initialize, initialization commands for the various modes, register pointers
WR1
Transmit/Receive interrupt and data transfer mode definition
WR2
Interrupt vector (accessed through either channel)
WR3
Receive parameters and control
WR4
Transmit/Receive miscellaneous parameters and modes
WR5
Transmit parameters and controls
WR6
Sync characters or SDLC address field
WR7
Sync character or SDLC flag
WR7*
Extended Feature and FIFO Control (WR7 Prime) 85C30 Only
WR8
Transmit buffer
WR9
Master interrupt control and reset (accessed through either channel)
WR10
Miscellaneous transmitter/receiver control bits
WR11
Clock mode control
WR12
Lower byte of Baud Rate Generator time constant
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
18
Table 2. SCC Write Register Functions (continued)
Register
Function
WR13
Upper byte of Baud Rate Generator time constant
WR14
Miscellaneous control bits
WR15
External/Status interrupt control
The following three methods move data, status and control information in and out of the
SCC; each is described in this section.
•
•
•
Polling
Interrupts (vectored and nonvectored)
CPU/DMA Block Transfer, in which BLOCK TRANSFER Mode can be implemented
under CPU or DMA control
Polling
When polling, all interrupts are disabled. Three status registers in the SCC are automatically updated when any function is performed. For example, End-Of-Frame in SDLC
Mode sets a bit in one of these status registers. The purpose of polling is for the CPU to
periodically read a status register until the register contents indicate the need for data to be
transferred. Only one register is read, and depending on its contents, the CPU either writes
data, reads data, or continues. Two bits in the register indicate the need for data transfer.
An alternative is a poll of the Interrupt Pending register to determine the source of an
interrupt. The status for both channels resides in one register.
Interrupts
The SCC’s interrupt structure supports vectored and nested interrupts. Nested interrupts
are supported with the interrupt acknowledge feature (INTACK pin) of the SCC.
This allows the CPU to recognize the occurrence of an interrupt, and reenable higher priority interrupts. Because an INTACK cycle releases the INT pin from the active state, a
higher priority SCC interrupt or another higher priority device can interrupt the CPU.
When an SCC responds to an Interrupt Acknowledge signal (INTACK) from the CPU, an
interrupt vector can be placed on the data bus. This vector is written in WR2 and can be
read in RR2A or RR2B. To speed interrupt response time, the SCC can modify three bits
in this vector to indicate status. If the vector is read in Channel A, status is never included.
If the vector is read in Channel B, status is always included.
Each of the six sources of interrupts in the SCC (Transmit, Receive, and External/Status
interrupts in both channels) has three bits associated with the interrupt source.
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
19
Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE). Operation of the IE bit is straight forward. If the IE bit is set for a given interrupt source, then
that source can request interrupts. The exception is when the MIE (Master Interrupt
Enable) bit in WR9 is reset and no interrupts can be requested. The IE bits are write-only.
The other two bits are related to the interrupt priority chain (see Figure 8). As a microprocessor peripheral, the SCC can request an interrupt only when no higher priority device is
requesting one, that is, when IEI is High. If the device in question requests an interrupt, it
pulls down INT. The CPU responds with INTACK, and the interrupting device places the
vector on the data bus.
Peripheral
Peripheral
IEI D7–D0 INT INTACK IEO
IEI D7–D0 INT INTACK IEO
+5 V
Peripheral
IEI D7–D0 INT INTACK
+5 V
D7–D0
INT
INTACK
Figure 8. SCC Interrupt Priority Schedule
The SCC can also execute an interrupt acknowledge cycle through software. In some CPU
environments, it is difficult to create the INTACK signal with the necessary timing to
acknowledge interrupts and allow the nesting of interrupts. In these cases, the INTACK
signal can be created with a software command to the SCC.
In the SCC, the Interrupt Pending (IP) bit signals a need for interrupt servicing. When an
IP bit is 1 and the IEI input is High, the INT output is pulled Low, requesting an interrupt.
In the SCC, if the IE bit is not set by enabling interrupts, then the IP for that source is
never set. The IP bits are readable in RR3A.
The IUS bits signal that an interrupt request is being serviced. If an IUS is set, all interrupt
sources of lower priority in the SCC and external to the SCC are prevented from requesting interrupts.
The internal interrupt sources are inhibited by the state of the internal daisy chain, while
lower priority devices are inhibited by the IEO output of the SCC being pulled Low and
propagated to subsequent peripherals. An IUS bit is set during an Interrupt Acknowledge
cycle, if there are no higher priority devices requesting interrupts.
There are three types of interrupts:
•
PS011708-0115
Transmit
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
20
•
•
Receive
External/Status
Each interrupt type is enabled under program control with Channel A having higher priority than Channel B, and with Receiver, Transmit, and External/Status interrupts prioritized
in that order within each channel.
When enabled, the receiver interrupts the CPU in one of three ways:
•
•
•
Interrupt on First Receive Character or Special Receive Condition
Interrupt on All Receive Characters or Special Receive Conditions
Interrupt on Special Receive Conditions Only
Interrupt on First Character or Special Condition and Interrupt on Special Condition Only
are typically used with the Block Transfer Mode. A special Receive Condition is one of
the following. receiver overrun, framing error in Asynchronous Mode, end-of-frame in
SDLC Mode and, optionally, a parity error. The Special Receive Condition interrupt is different from an ordinary receive character available interrupt only by the status placed in
the vector during the Interrupt Acknowledge cycle. In Interrupt on First Receive Character, an interrupt occurs from Special Receive Conditions anytime after the first receive
character interrupt.
The main function of the External/Status interrupt is to monitor the signal transitions of
the CTS, DCD, and SYNC pins, however, an External/Status interrupt is also caused by a
Transmit Underrun condition; a zero count in the Baud Rate Generator; by the detection of
a Break (Asynchronous Mode), Abort (SDLC Mode) or EOP (SDLC Loop Mode)
sequence in the data stream. The interrupt caused by the Abort or EOP has a special feature allowing the SCC to interrupt when the Abort or EOP sequence is detected or terminated. This feature facilitates the proper termination of the current message, correct
initialization of the next message, and the accurate timing of the Abort condition in external logic in SDLC Mode. In SDLC Loop Mode, this feature allows secondary stations to
recognize the primary station regaining control of the loop during a poll sequence.
Software Interrupt Acknowledge
On the CMOS version of the SCC, the SCC interrupt acknowledge cycle can be initiated
through software. If Write Register 9 (WR9) bit D5 is set, Read Register 2 (RR2) results in
an interrupt acknowledge cycle to be executed internally. Like a hardware INTACK cycle,
a software acknowledge causes the INT pin to return High, the IEO pin to go low and set
the IUS latch for the highest priority interrupt pending.
Similar to using the hardware INTACK signal, a software acknowledge cycle requires that
a Reset Highest IUS command be issued in the interrupt service routine. Whenever an
interrupt acknowledge cycle is used, hardware or software, a reset highest IUS command
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
21
is required. If RR2 is read from channel A, the unmodified vector is returned. If RR2 is
read from channel B, then the vector is modified to indicate the source of the interrupt.
The Vector Includes Status (VIS) and No Vector (NV) bits in WR9 are ignored when bit
05 is set to 1.
When the INTACK and IEI pins are not being used, they should be pulled up to VCC
through a resistor (10 K typical).
CPU/DMA Block Transfer
The SCC provides a Block Transfer Mode to accommodate CPU block transfer functions
and DMA controllers. The Block Transfer Mode uses the WAIT/REOUEST output in conjunction with the Wait/Request bits in WR1. The WAIT/REOUEST output can be defined
under software control as a WAIT line in the CPU Block Transfer Mode or as a
REQUEST line in the DMA Block Transfer Mode.
To a DMA controller, the SCC REQUEST output indicates that the SCC is ready to transfer data to or from memory To the CPU, the WAIT line indicates that the ESCC is not
ready to transfer data, thereby requesting that the CPU extend the I/O cycle. The DTR/
REQUEST line allows full-duplex operation under DMA control.
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
22
SCC Data Communications Capabilities
The SCC provides two independent full-duplex programmable channels for use in any
common asynchronous or synchronous data communication protocols; see Figure 9. Each
data communication channel has identical feature and capabilities.
Parity
Start
Stop
Marking Line
Data
Data
Marking Line
Data
Asynchronous
SYNC
Data
Data
CRC1
CRC2
Data
CRC1
CRC2
Data
CRC1
CRC2
CRC1
CRC2
Monosync
SYNC
SYNC
Data
Signal
Bisync
Data
External Sync
Flag
Address
Information
Information
Flag
SDLC/HDLC/X.25
Figure 9. SCC Protocols
Asynchronous Modes
Send and Receive is accomplished independently on each channel with five to eight bits
per character, plus optional even or odd parity. The transmitters can supply one, one-anda-half, or two stop bits per character and can provide a break output at any time. The
receiver break-detection logic interrupts the CPU both at the start and at the end of a
received break.
Reception is protected from spikes by a transient spike-rejection mechanism that checks
the signal one-half a bit time after a Low level is detected on the receive data input (RxDA
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
23
or RxDB pins). If the Low does not persist (a transient), the character assembly process
does not start.
Framing errors and overrun errors are detected and buffered together with the partial character on which they occur. Vectored interrupts allow fast servicing or error conditions
using dedicated routines. A built-in checking process avoids the interpretation of a framing error as a new start bit. A framing error results in the addition of one-half a bit time to
the point at which the search for the next start bit begins.
The SCC does not require symmetric transmit and receive clock signals – a feature that
allows the use of a wide variety of clock sources. The transmitter and receiver handle data
at a rate supplied to the receive and transmit clock inputs. In Asynchronous modes, the
SYNC pin can be programmed as an input used for functions such as monitoring a ring
indicator.
Synchronous Modes
The SCC supports both byte and bit-oriented synchronous communication. Synchronous
byte-oriented protocols are handled in several modes. They allow character synchronization with a 6-bit or 8-bit sync character (Monosync), and a 12-bit or 16-bit synchronization pattern (Bisync), or with an external sync signal. Leading sync characters are
removed without interrupting the CPU.
5- or 7-bit synchronous characters are detected with 8- or 16-bit patterns in the SCC by
overlapping the larger pattern across multiple incoming synchronous characters, as shown
in Figure 10.
7 Bits
SYNC
SYNC
SYNC
Data
Data
Data
Data
8
16
Figure 10. Detecting 5- or 7-Bit Synchronous Characters
CRC checking for Synchronous byte-oriented modes is delayed by one character time so
that the CPU can disable CRC checking on specific characters. This feature permits the
implementation of protocols such as IBM Bisync.
Both CRC-16 (X16 + X15 + X12 +1) and CCITT (X16 + X12 + X5 + 1) error-checking
polynomials are supported. Either polynomial can be selected in all Synchronous modes.
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
24
You can preset the CRC generator and checker to all 1s or all 0s. The SCC also provides a
feature that automatically transmits CRC data when no other data is available for transmission. This feature allows for high speed transmissions under DMA control, with no need
for CPU intervention at the end of a message.
When there is no data or CRC to send in Synchronous modes, the transmitter inserts 6-,8-,
or 16-bit sync characters, regardless of the programmed character length.
SDLC Mode
The SCC supports Synchronous bit-oriented protocols, such as SDLC and HDLC, by performing automatic flag sending, zero insertion, and CRC generation. A special command
is used to abort a frame in transmission. At the end of a message, the SCC automatically
transmits the CRC and trailing flag when the transmitter underruns. The transmitter can
also be programmed to send an idle line consisting of continuous flag characters or a
steady marking condition.
If a transmit underrun occurs in the middle of a message, an external/status interrupt warns
the CPU of this status change, issuing an abort. The SCC can also be programmed to send
an abort itself in case of an underrun, relieving the CPU of this task. One to eight bits per
character can be sent, allowing reception of a message with no prior information about the
character structure in the information field of a frame.
The receiver automatically acquires synchronization on the leading flag of a frame in
SDLC or HDLC and provides a synchronization signal on the SYNC pin (an interrupt can
also be programmed). The receiver can be programmed to search for frames addressed by
a single byte (or four bits within a byte) of a user-selected address or to a global broadcast
address. In this mode, frames not matching either the user-selected or broadcast address
are ignored.
The number of address bytes are extended under software control. For receiving data, an
interrupt on the first received character, or an interrupt on every character, or on special
condition only (end-of-frame) can be selected. The receiver automatically deletes all 0s
inserted by the transmitter during character assembly CRC is also calculated and is automatically checked to validate frame transmission. At the end of transmission, the status of
a received frame is available in the status registers. In SDLC Mode, the SCC must be programmed to use the SDLC CRC polynomial, but the generator and checker can be preset
to all 1s or all 0s. The CRC inverts before transmission and the receiver checks against the
bit pattern 0001110100001111.
NRZ, NRZI or FM coding can be used in any 1x mode. The parity options available in
Asynchronous modes are available in Synchronous modes.
SDLC Loop Mode
The SCC supports SDLC Loop Mode in addition to normal SDLC. In an SDLC Loop, a
primary controller station manages the message traffic flow on the loop and any number of
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
25
secondary stations. In SDLC Loop Mode, the SCC performs the functions of a secondary
station while an SCC operating in regular SDLC Mode acts as a controller; see Figure 11.
The SDLC Loop Mode can be selected by setting WR10 bit D1.
Controller
Secondary #1
Secondary #4
Secondary #2
Secondary #3
Figure 11. An SDLC Loop
A secondary station in an SDLC Loop is always listening to the messages sent around the
loop and passes these messages to the rest of the loop by retransmitting them with a onebit-time delay. The secondary station places its own message on the loop only at specific
times.
The controller signals that secondary stations can transmit messages by sending a special
character, called an End Of Poll (EOP), around the loop. The EOP character is the bit pattern 11111110. Because of zero insertion during messages, this bit pattern is unique and
easily recognized.
When a secondary station contains a message to transmit and recognizes an EOP on the
line, it changes the last binary 1 of the EOP to a 0 before transmission. This change has the
effect of turning the EOP into a flag sequence. The secondary station now places its message on the loop and terminates the message with an EOP. Any secondary stations further
down the loop with messages to transmit append their messages to the message of the first
secondary station by the same process. Any secondary stations without messages to send
echo the incoming message and are prohibited from placing messages on the loop (except
when recognizing an EOP). In SDLC Loop Mode, NRZ, NRZI, and FM coding can be
used.
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
26
The SCC’s ability to receive high speed back-to-back SDLC frames is maximized by a 10deep by 19-bit wide status FIFO. When enabled (through WR15, bit D2), it provides the
DMA the ability to continue to transfer data into memory so that the CPU can examine the
message later. For each SDLC frame, a 14-bit byte count and 5 status/error bits are stored.
The byte count and status bits are accessed through read registers 6 and 7, which are only
accessible when the SDLC FIFO is enabled. The 10 x 19 status FIFO is separate from the
3-byte receive data FIFO.
Baud Rate Generator
Each channel in the SCC contains a programmable Baud Rate Generator (BRG). Each
generator consists of two 8-bit time constant registers that form a 16-bit time constant, a
16-bit down counter, and a flip-flop on the output producing a square wave. On startup,
the output flip-flop is set in a High state, the value in the time constant register is loaded
into the counter, and the counter starts counting down. The output of the BRG toggles
when reaching 0, the value in the time constant register is loaded into the counter, and the
process is repeated. The time constant can be changed at any time, but the new value does
not take effect until the next load of the counter.
The output of the BRG can be used as either the transmit clock, the receive clock, or both.
It can also drive the Digital Phase-locked loop (see section on page 26).
If the receive clock or transmit clock is not programmed to come from the TRxC pin, the
output of the BRG can be echoed out through the TRxC pin. The following formula relates
the time constant to the baud rate where PCLK or RTxC is the BRG input frequency in
Hertz. The clock mode is 1, 16, 32, or 64, as selected in Write Register 4, bits D6 and D7.
Synchronous operation modes select 1 and Asynchronous modes select 16, 32 or 64.
Time Constant =
PCLK or RTxC Frequency
-2
2(Baud Rate)(Clock Mode)
Digital Phase-Locked Loop
The SCC contains a Digital Phase-Locked Loop (DPLL) to recover clock information
from a data stream with NRZI or FM encoding. The DPLL is driven by a clock that is
nominally 32 (NRZI) or 16 (FM) times the data rate. The DPLL uses this clock, along with
the data stream, to construct a clock for the data. This clock is used as the SCC receive
clock, the transmit clock, or both. When the DPLL is selected as the transmit clock source,
it provides a jitter-free clock output that is the DPLL input frequency divided by the
appropriate divisor for the selected encoding technique.
For NRZI encoding, the DPLL counts the 32x clock to create nominal bit times. As the
32x clock is counted, the DPLL is searching the incoming data stream for edges (either 1
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
27
to 0, or 0 to 1). Whenever an edge is detected, the DPLL makes a count adjustment (during
the next counting cycle), producing a terminal count closer to the center of the bit cell.
For FM encoding, the DPLL again counts from 0 to 31, but with a cycle corresponding to
two bit times. When the DPLL is locked, the clock edges in the data stream occur between
counts 15 and 16 and between counts 31 and 0. The DPLL looks for edges only during a
time centered on the 15 to 16 counting transition.
The 32x clock for the DPLL can be programmed to come from either the RTxC input or
the output of the BRG. The DPLL output can be programmed to be echoed out of the SCC
through the TRxC pin (if this pin is not being used as an input).
Data Encoding
The SCC can be programmed to encode and decode the serial data in four different methods; see Figure 12. In NRZ encoding, a 1 is represented by a High level and a 0 is represented by a Low level. In NRZI encoding, a 1 is represented by no change in level and a 0
is represented by a change in level.
In FM1 (more properly, bi-phase mark), a transition occurs at the beginning of every bit
cell. A 1 is represented by an additional transition at the center of the bit cell and a 0 is represented by no additional transition at the center of the bit cell.
In FM0 (bi-phase space), a transition occurs at the beginning of every bit cell. A 0 is represented by an additional transition at the center of the bit cell, and a 1 is represented by no
additional transition at the center of the bit cell.
In addition to these four methods, the SCC can be used to decode Manchester (bi-phase
level) data by using the DPLL in FM Mode and programming the receiver for NRZ data.
Manchester encoding always produces a transition at the center of the bit cell. If the transition is 0 to 1, the bit is a 0. If the transition is 1 to 0, the bit is a 1.
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
28
Data
1
1
0
0
1
0
NRZ
NRZI
FM1
FM0
Manchester
Figure 12. Data Encoding Methods
Auto Echo and Local Loopback
The SCC is capable of automatically echoing everything it receives. This feature is useful
mainly in Asynchronous modes, but works in Synchronous and SDLC modes as well.
Auto Echo Mode (Tx0 is Rx0) is used with NRZI or FM encoding with no additional
delay because the data stream is not decoded before retransmission. In Auto Echo Mode,
the CTS input is ignored as a transmitter enable (although transitions on this input can still
cause interrupts if programmed to do so). In this mode, the transmitter is actually bypassed
and the programmer is responsible for disabling transmitter interrupts and WAIT/
REQUEST on transmit.
The SCC is also capable of local loopback. In this mode, TxD or RxD is similar to Auto
Echo Mode. However, in Local Loopback Mode the internal transmit data is tied to the
internal receive data and RxD is ignored (except to be echoed out through TxD). The CTS
and DCD inputs are also ignored as transmit and receive enables. However, transitions on
these inputs can still cause interrupts. Local Loopback works in Asynchronous, Synchronous and SDLC modes with NRZ, NRZI or FM coding of the data stream.
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
29
SDLC FIFO Frame Status FIFO Enhancement
The SCC’s ability to receive high speed back-to-back SDLC frames is maximized by a 10deep by 19-bit wide status FIFO. When enabled (through WR15, bit D2), it provides the
DMA the ability to continue to transfer data into memory so that the CPU can examine the
message later. For each SDLC frame, a 14-bit byte count and 5 status/error bits are stored.
The byte count and status bits are accessed through read registers 6 and 7, which are only
accessible when the SDLC FIFO is enabled. The 10x19 status FIFO is separate from the 3byte receive data FIFO.
When the enhancement is enabled, the status in Read Register 1 (RR1) and byte count for
the SDLC frame are stored in the 10 x 19 bit status FIFO. This arrangement allows the
DMA controller to transfer the next frame into memory while the CPU verifies that the
message was properly received.
Summarizing the operation; data is received, assembled, and loaded into the eight byte
FIFO before being transferred to memory by the DMA controller. When a flag is received
at the end of an SDLC frame, the frame byte count from the 14-bit counter and five status
bits are loaded into the status FIFO for verification by the CPU. The CRC checker automatically resets in preparation for the next frame which can begin immediately. Because
the byte count and status are saved for each frame, the message integrity is verified at a
later time. The status information for up to 10 frames is stored before a status FIFO overrun occurs.
If a frame is terminated with an ABORT, the byte count is loaded to the status FIFO and
the counter resets for the next frame.
FIFO Detail
For more details about FIFO operation, see Figure 13 on page 31.
Enable/Disable
This FIFO is implemented is enabled when WR15, bit D2, is set and the SCC is in the
SDLC/HDLC Mode. Otherwise, the status register contents bypass the FIFO and go
directly to the bus interface (the FIFO pointer logic is reset either when disabled or
through a channel or Power-On Reset). When FIFO Mode is disabled, the SCC is downward-compatible with the NMOS Z8530. The FIFO Mode is disabled on power-up (WR15
D2 is set to 0 on reset). The effects of backward compatibility on the register set are that
RR4 is an image of RR0, RR5 is an image of RR1, RR6 is an image of RR2 and RR7 is an
image of RR3. For more details about the added registers, see Figure 16 on page 35. The
status of the FIFO Enable signal is obtained by reading RR15, bit D2. If the FIFO is
enabled, the bit is set to 1; otherwise, it resets.
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
30
Read Operation
When WR15 bit D2 sets and the FIFO is not empty, the next read to status register RR1 or
registers RR7 and RR6, is from the FIFO. Reading status register RR1 causes one location
of the FIFO to become empty. Status is read after reading the byte count, otherwise the
count is incorrect. Before the FIFO underflows, it is disabled. In this case, the multiplexer
is switched allowing status to read directly from the status register. Reads from RR7 and
RR6 contain bits that are undefined. Bit D6 of RR7 (FIFO Data Available) determines if
status data is coming from the FIFO or directly from the status register, which sets to 1
when the FIFO is not empty. Not all status bits are stored in the FIFO. The All Sent, Parity,
and EOF bits bypass the FIFO. Status bits sent through the FIFO are Residue Bits (3),
Overrun, and CRC Error.
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
31
Frame Status FIFO Circuitry
RR1
Reset on Flag Detect
SCC Status Reg
Residue Bits (3)
Overrun, CRC Error
Byte Counter
Increment on Byte Detection
Enable Count in SDLC
End of Frame Signal
5 Bits
14 Bits
Status Read Comp
FIFO Array
10 Deep by 19 Bits Wide
Tail Pointer
4-Bit Counter
Head Pointer
4-Bit Counter
4-Bit Comparator
Over
EOF = 1
5 Bits
6 Bits
8 Bits
EN
6-Bit MUX
2 Bits
6 Bits
RR1
Equal
Bit 7 Bit 6
Bits 5-0
RR6
RR7 D5-D0 + RR6 D7-D0
Byte Counter Contains 14 bits
for a 16 KByte maximum count
Interface
to SCC
FIFO Enable
WR(15) Bit 2
Set Enables
Status FIFO
RR7 D6
FIFO Data available status bit Status Bit set to 1
When reading from FIFO
RR7 D7
FIFO Overflow Status Bit
MSB pf RR(7) is set on Status FIFO overflow
In SDLC Mode the following definitions apply
Figure 13. SDLC Frame Status FIFO
The sequence for operation of the byte count and FIFO logic is to read the registers in the
following order. RR7, RR6, and RR1 (reading RR6 is optional). Additional logic prevents
the FIFO from being emptied by multiple reads from RR1. The read from RR7 latches the
FIFO empty/full status bit (D6) and steers the status multiplexer to read from the SCC
megacell instead of the status FIFO (since the status FIFO is empty). The read from RR1
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
32
allows an entry to be read from the FIFO (if the FIFO was empty, logic was added to prevent a FIFO underflow condition).
Write Operation
When the end of an SDLC frame (EOF) is received and the FIFO is enabled, the contents
of the status and byte-count registers are loaded into the FIFO. The EOF signal is used to
increment the FIFO. If the FIFO overflows, RR7, bit D7 (FIFO Overflow) sets to indicate
the overflow. This bit and the FIFO control logic is reset by disabling and reenabling the
FIFO control bit (WR15, bit 02). For details of FIFO control timing during an SDLC
frame, see Figure 14.
0
F
A
D
D
D
D
C
7
0
0
C
F
F
Internal Byte Strobe
Increments Counter
Don’t Load
Counter On
1st Flag
Reset Byte
Counter Here
A
D
D
D
D
C
7
0
C
F
Internal Byte Strobe
Increments Counter
Reset
Byte Counter
Load Counter
Into FIFO and
Increment PTR
Reset
Byte Counter
Reset
Byte Counter
Load Counter
Into FIFO and
Increment PTR
Figure 14. SDLC Byte Counting Detail
Programming
The SCC contains write registers in each channel that are programmed by the system separately to configure the functional personality of the channels.
Z85C30
In the SCC, the data registers are directly addressed by selecting a High on the D/C pin.
With all other registers (except WR0 and RR0), programming the write registers requires
two write operations and reading the read registers requires both a write and a read operation. The first write is to WR0 and contains three bits that point to the selected register.
The second write is the actual control word for the selected register, and if the second
operation is read, the selected read register is accessed. All the SCC registers, including
the data registers, can be accessed in this fashion. The pointer bits are automatically
cleared after the read or write operation so that WR0 (or RR0) is addressed again.
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
33
Z80C30
All SCC registers are directly addressable. A command issued in WR0B controls how the
SCC decodes the address placed on the address/data bus at the beginning of a read or write
cycle. In the Shift Right Mode, the channel select A/B is taken from AD0 and the state of
AD5 is ignored. In the Shift Left Mode, the channel select A/B is taken from AD5 and the
state of AD0 is ignored. AD7 and AD6 are always ignored as address bits and the register
address occupies AD4-AD1.
Z85C30/Z80C30 Setup
The system program first issues a series of commands to initialize the basic mode of operation. This is followed by other commands to qualify conditions within the selected mode.
For example, in Asynchronous Mode, character length, clock rate, number of stop bits,
and even or odd parity must be set first. The interrupt mode is set, and finally, the receiver
and transmitter are enabled.
Write Registers
The SCC contains 15 write registers for the 80C30, while there are 16 for the 85C30 (one
more additional write register if counting the transmit buffer) in each channel. These write
registers are programmed separately to configure the functional ‘personality’ of the channels. There are two registers (WR2 and WR9) shared by the two channels that are
accessed through either of them. WR2 contains the interrupt vector for both channels,
while WR9 contains the interrupt control bits and reset commands. Figures 15 through 18
show the format of each write register.
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
34
Write Register 0 (non-multiplexed bus mode)
Write Register 1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Ext Int Enable
0 0 0 Register 0
0 0 1 Register 1
0 1 0 Register 2
0 1 1 Register 3
1 0 0 Register 4
1 0 1 Register 5
1 1 0 Register 6
1 1 1 Register 7
0 0 0 Register 8
0 0 1 Register 9
0 1 0 Register 10
0 1 1 Register 11
*
1 0 0 Register 12
1 0 1 Register 13
1 1 0 Register 14
1
1 Register 15
Null Code
Point High
Reset Ext/Status Interrupts
Send Abort (SDLC)
Enable Int on Next Rx Character
Reset Tx Int Pending
Error Reset
Reset Highest IUS
0
0
1
1
0
1
0
1
Tx Int Enable
Parity is Special Condition
0
0
1
1
0
1
0
1
Rx Int Disable
Rx Int on First Character or Special Condition
Int on all Rx Characters or Special Condition
Rx Int on Special Condition Only
WAIT/DMA Request on
Receive /Transmit
WAIT/DMA Request Function
WAIT/DMA Request
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Null Code
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx Underrun/EOM Latch
Write Register 2
D7 D6 D5 D4 D3 D2 D1 D0
V0
V1
V2
V3
V4
* With Point High Command
Interrupt
Vector
V5
V6
Write Register 0 (multiplexed bus mode)
V7
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 3
0
0
1
1
0
1
0
1
Null Code
Null Code
Select Shift Left Mode
Select Shift Right Mode
D7 D6 D5 D4 D3 D2 D1 D0
*
Rx Enable
Sync Character Load Inhibit
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Null Code
Null Code
Reset Ext/Status Interrupts
Send Abort
Enable Int on Next Rx Character
Reset Tx Int Pending
Error Reset
Reset Highest IUS
Null Code
Reset Rx CRC Checker
Reset Tx CRC Checker
Reset Tx Underrun/EOM Latch
Address Search Mode (SDLC)
Rx CRC Enable
Enter Hunt Mode
Auto Enables
0
0
1
1
0
1
0
1
Rx 5 Bits/Character
Rx 7 Bits/Character
Rx 6 Bits/Character
Rx 8 Bits/Character
* B Channel Only
Figure 15. Write Register Bit Functions
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
35
Write Register 4
Write Register 5
D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
Parity Enable
Tx CRC Enable
Parity EVEN/ODD
RTS
SDLC/CRC-16
Sync Modes Enable
1 Stop Bit/Character
1 1/2 Stop Bits/Character
2 Stop Bits/Character
8-Bit Sync Character
16-Bit Sync Character
SDLC Mode (01111110 Flag)
External Sync Mode
Tx Enable
Send Break
0
0
1
1
0
1
0
1
Tx 5 Bits (or Less)/Character
Tx 7 Bits/Character
Tx 6 Bits/Character
Tx 8 Bits/Character
DTR
0
0
1
1
0 X1 Clock Mode
1 X16 Clock Mode
0 X32 Clock Mode
1 X64 Clock Mode
Figure 16. Write Register Bit Functions
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
36
Write Register 6
D7 D6 D5 D4 D3 D2 D1 D0
Sync7
Sync1
Sync7
Sync3
ADR7
ADR7
Sync6
Sync0
Sync6
Sync2
ADR6
ADR6
Sync5
Sync5
Sync5
Sync1
ADR5
ADR5
Sync4
Sync4
Sync4
Sync0
ADR4
ADR4
Sync3
Sync3
Sync3
1
ADR3
x
Sync2
Sync2
Sync2
1
ADR2
x
Sync1
Sync1
Sync1
1
ADR1
x
Sync0
Sync0
Sync0
1
ADR0
x
Monosync, 8 Bits
Monosync, 6 Bits
Bisync, 16 Bits
Bisync, 12 Bits
SDLC
SDLC (Address Range)
Write Register 7
D7 D6 D5 D4 D3 D2 D1 D0
Sync7 Sync6
Sync5 Sync4
Sync15 Sync14
Sync11 Sync10
1
0
Sync5
Sync3
Sync13
Sync9
1
Sync4
Sync2
Sync12
Sync8
1
Sync3
Sync1
Sync11
Sync7
1
Sync2 Sync1 Sync0
x
Sync0
x
Sync10 Sync9 Sync8
Sync6 Sync5 Sync4
1
1
0
Monosync, 8 Bits
Monosync, 6 Bits
Bisync, 16 Bits
Bisync, 12 Bits
SDLC
WR 7’ Prime (85C30 only)
D7 D6 D5 D4 D3 D2 D1 D0
Auto Tx Flag
Auto EOM Reset
Auto RTS Deactivation
Force TxD High
DTR/REQ Fast Mode
Complete CRC Reception
Extended Read Enable
Reserved (Program as 0)
Figure 17. Write Register Bit Functions
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
37
Write Register 12
Write Register 9
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
VIS
TC0
NV
TC1
DLC
TC2
MIE
TC3
Status High/Status Low
TC4
Software INTACK Enable
0
0
1
1
0
1
0
1
Lower Byte of
Time Constant
TC5
TC6
No Reset
Channel Reset B
Channel Reset A
Force Hardware Reset
TC7
Write Register 13
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 10
D7 D6 D5 D4 D3 D2 D1 D0
TC8
TC9
0
0
1
1
6-Bit/8-Bit Sync
TC10
Loop Mode
TC11
Abort/Flag on Underrun
TC12
Mark/Flag Idle
TC13
Go Active on Poll
TC14
Upper Byte of
Time Constant
TC15
0 NRZ
1 NRZI
0 FM1 (Transition = 1)
1 FM1 (Transition = 0)
Write Register 14
D7 D6 D5 D4 D3 D2 D1 D0
CRC Preset I/O
BR Generator Enable
Write Register 11
BR Generator Source
D7 D6 D5 D4 D3 D2 D1 D0
DTR/Request Function
Auto Echo
0
0
1
1
0
1
0
1
TRxC Out = Xtal Output
TRxC Out = Transmit Clock
TRxC Out = BR Generator Output
TRxC Out = DPLL Output
TRxC O/I
0
0
1
1
0
1
0
1
Transmit Clock = RTxC Pin
Transmit Clock = TRxC Pin
Transmit Clock = BR Generator Output
Transmit Clock = DPLL Output
Local Loopback
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 Null Command
1 Enter Search Mode
0 Reset Missing Clock
1 Disable DPLL
0 Set Source = BR Generator
1 Set Source = RTxC
0 Set FM Mode
1 Set NRZI Mode
Write Register 15
0
0
1
1
0
1
0
1
Receive Clock = RTxC Pin
Receive Clock = TRxC Pin
Receive Clock = BR Generator Output
Receive Clock = DPLL Output
D7 D6 D5 D4 D3 D2 D1 D0
RTxC Xtal/No Xtal
0
Zero Count IE
SDLC FIFO Enable
DCD IE
Sync/Hunt IE
CTS IE
Tx Underrun/EOM IE
Break/Abort IE
Figure 18. Write Register Bit Functions
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
38
Read Registers
The SCC contains ten read registers (eleven, counting the receive buffer (RR8) in each
channel). Four of these can be read to obtain status information (RR0, RR1, RR10, and
RR15). Two registers (RR12 and RR13) are read to learn the Baud Rate Generator time
constant. RR2 contains either the unmodified interrupt vector (Channel A) or the vector
modified by status information (Channel B). RR3 contains the Interrupt Pending (IP) bits
(Channel A only; see Figure 19). RR6 and RR7 contain the information in the SDLC
Frame Status FIFO, but is only read when WR15 D2 is set (see Figures 19 and 20 ).
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
39
Read Register 3
Read Register 0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Rx Character Available
Channel B Ext/Status IP
Zero Count
Channel B Tx IP
Tx Buffer Empty
Channel B Rx IP
DCD
Channel A Ext/Status IP
Sync/Hunt
Channel A Tx IP
CTS
Channel A Rx IP
Tx Underrun/EOM
0
Break/Abort
0
*
* Always 0 in B Channel
Read Register 1
D7 D6 D5 D4 D3 D2 D1 D0
Read Register 10
D7 D6 D5 D4 D3 D2 D1 D0
All Sent
Residue Code 2
0
Residue Code 1
On Loop
Residue Code 0
0
Parity Error
0
Rx Overrun Error
Loop Sending
CRC/Framing Error
0
End of Frame (SDLC)
Two Clocks Missing
One Clocks Missing
Read Register 2
Read Register 12
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
V0
V1
TC0
V2
TC1
V3
V4
Interrupt
Vector *
TC2
TC3
V5
TC4
V6
TC5
V7
Lower Byte
of Time Constant
TC6
TC7
* Modified in B Channel
Figure 19. Read Register Bit Functions, #1 of 2
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
40
Read Register 13
Read Register 15
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
TC8
0
TC9
Zero Count IE
TC10
TC11
TC12
0
Upper Byte
of Time Constant
TC13
DCD IE
Sync/Hunt IE
CTS IE
TC14
Tx Underrun/EOM IE
TC15
Break/Abort IE
Figure 20. Read Register Bit Functions, #2 of 2
Z85C30 Timing
The SCC generates internal control signals from the WR and RD that are related to PCLK.
PCLK has no phase relationship with WR and RD, the circuitry generating the internal
control signals provides time for meta-stable conditions to disappear. This gives rise to a
recovery time related to PCLK. The recovery time applies only between bus transactions
involving the SCC.
The recovery time required for proper operation is specified from the falling edge of WR
or RD in the first transaction involving the SCC to the falling edge of WR or RD in the
second transaction involving the SCC. This time must be at least 3 PCLKs regardless of
which register or channel is being accessed. The remainder of this section describes the
read cycle, write cycle and interrupt acknowledge cycle timing for the Z85C30 device.
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
41
Read Cycle Timing
Figure 21 shows read cycle timing. Addresses on A/ B and D/C and the status on INTACK
must remain stable throughout the cycle. If CE falls after RD falls, or if CE rises before
RD rises, the effective RD is shortened.
A/B,
D/C
Address Valid
INTACK
CE
RD
Data Valid
D7–D0
Figure 21. Read Cycle Timing
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
42
Write Cycle Timing
Figure 22 shows write cycle timing. Addresses on A/B and D/C and the status on
INTACK must remain stable throughout the cycle. If CE falls after WR falls, or if CE rises
before WR rises, the effective WR is shortened. Data must be valid before the rising edge
of WR.
A/B, D/C
A Ad
Add Address Valid
INTACK
CE
WR
D7-D0
Data Valid
Figure 22. Write Cycle Timing
Interrupt Acknowledge Cycle Timing
Figure 23 shows an Interrupt Acknowledge cycle timing. Between the time INTACK goes
Low and the falling edge of RD, the internal and external IEI/IEO daisy chains settle. If
there is an interrupt pending in the SCC and IEI is High when RD falls, the Acknowledge
cycle is intended for the SCC. In this case, the SCC can be programmed to respond to RD
Low by placing its interrupt vector on D7-D0. It then sets the appropriate Interrupt-UnderService latch internally.
If the external daisy chain is not used, AC parameter #38 is required to settle the interrupt
priority daisy chain internal to the SCC. If the external daisy chain is used, you must follow the equation in Table 6 on page 53 for calculating the required daisy-chain settle time.
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
43
INTACK
RD
D7–D0
Vector
Figure 23. Interrupt Acknowledge Cycle Timing
Z80C30 Timing
The SCC generates internal control signals from AS and DS that are related to PCLK.
Because PCLK has no phase relationship with AS and DS, the circuitry generating these
internal control signals must provide time for metastable conditions to disappear. This
gives rise to a recovery time related to PCLK. The recovery time applies only between bus
transactions involving the SCC. The recovery time required for proper operation is specified from the falling edge of DS in the first transaction involving the SCC to the falling
edge of DS in the second transaction involving the SCC. The remainder of this section
describes read cycle, write cycle and interrupt acknowledge cycle timing for the Z80C30
device.
Read Cycle Timing
Figure 24 shows the read cycle timing. The address on AD7–AD0 and the state of CS0
and INTACK are latched by the rising edge of AS. R/W must be High to indicate a read
cycle. CS1 must also be High for the read cycle to occur. The data bus drivers in the SCC
are then enabled while DS is Low.
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
44
AS
CS0
INTACK
AD7–AD0
Address
Data Valid
R/W
CS1
DS
Figure 24. Read Cycle Timing
Write Cycle Timing
Figure 25 shows the write cycle timing. The address on AD7–AD0 and the state of CS0
and INTACK are latched by the rising edge of AS. R/W must be Low to indicate a write
cycle. CS1 must be High for the write cycle to occur DS Low strobes the data into the
SCC.
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
45
AS
CS0
INTACK
AD7–AD0
Address
Data
R/W
CS1
DS
Figure 25. Write Cycle Timing
Interrupt Acknowledge Cycle Timing
Figure 26 shows the Interrupt Acknowledge cycle timing. The address on AD7–AD0 and
the state of CS0 and INTACK are latched by the rising edge of AS. If INTACK is Low, the
address and CS0 are ignored. The state of the R/W and CS1 are also ignored for the duration of the Interrupt Acknowledge cycle. Between the rising edge of AS and the falling
edge of DS, the internal and external IEI/IEO daisy chains settle. If there is an interrupt
pending in the SCC, and IEI is High when DS falls, the Acknowledge cycle was intended
for the SCC. In this case, the SCC is programmed to respond to RD Low by placing its
interrupt vector on D7-D0 and internally setting the appropriate Interrupt-Under-Service
latch.
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
46
AS
CS0
(Ignored)
INTACK
AD7–AD0
(Ignored)
Vector
DS
Figure 26. Interrupt Acknowledge Cycle Timing
PS011708-0115
Functional Descriptions
CMOS SCC Serial Communications Controller
Product Specification
47
Electrical Characteristics
The electrical characteristics of the Z80C30 and the Z85C30 devices are described in the
following sections.
Absolute Maximum Ratings
Stresses greater than those listed in Absolute Maximum Ratings may cause permanent
damage to the device This is a stress rating only. Operation of the device at any condition
above those indicated in the operational sections of these specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Table 3. Absolute Maximum Ratings
Vcc Supply Voltage range
–0.3 V to +7.0 V
Voltages on all pins with respect to GND
–3 V to VCC +0.3 V
TA Operating Ambient Temperature
See the Ordering Information chapter on page 75
Storage Temperature
–65° C to +150° C
Standard Test Conditions
The DC Characteristics and capacitance sections below apply for the following standard
test conditions, unless otherwise noted. All voltages are referenced to GND. Positive current flows into the referenced pin. See Figures 27 and 28 .
•
•
•
PS011708-0115
+4.50 V Vcc + 5.50 V
GND = 0 V
TA (see the Ordering Information section on page 75)
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
48
+5 V
2.1 K
From Output
Under Test
250 A
100 pF
Figure 27. Standard Test Load
39
+5 V
2.2 K
From Output
50 pF
Figure 28. Open-Drain Test Load
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
49
Capacitance
Capacitance lists the input, output and bidirectional capacitance.
Table 4. Capacitance
Symbol
Parameter
Min
Max
Unit
1
CIN
Input Capacitance
10
pF
COUT
Output Capacitance
15
pF
CI/O
Bidirectional Capacitance
20
pF
Test Condition
Unmeasured Pins Returned to Ground2
Notes:
1. pF = 1 MHz, over specified temperature range.
2. Unmeasured pins returned to Ground.
Miscellaneous
The Gate Count is 6800.
DC Characteristics
Z80C30/Z85C30 DC Characteristics lists the DC characteristics for the Z80C30 and
Z85C30 devices.
Table 5. Z80C30/Z85C30 DC Characteristics
Symbol
Parameter
Min
Typ
Max
Unit Condition
1
VIH
Input High Voltage
2.2
VCC +0.3
V
VIL
Input Low Voltage
–0.3
0.8
V
VOH1
Output High Voltage
2.4
V
IOH = –1.6 mA
VOH2
Output High Voltage
VCC – 0.8
V
IOH = –250 A
VOL
Output Low Voltage
0.4
V
IOL = +2.0 mA
IIL
Input Leakage
A
0.4 VIN + 2.4 V
IOL
Output Leakage
10.0
10.0
A
0.4 VOUT + 2.4 V
ICC1
VCC Supply
Current2
7
12 (10 MHz)
mA VCC = 5 V; VIH = 4.8 VIL = 0
Notes:
1. VCC = SV t10% unless otherwise specified, over specified temperature range.
2. Typical ICC was measured with oscillator off.
3. No ICC (OSC) max is specified due to dependency on external circuit and frequency of oscillation.
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
50
Table 5. Z80C30/Z85C30 DC Characteristics (continued)
Symbol
Parameter
Min
Typ
9
ICCOSC
Crystal OSC
Current3
4
Max
Unit Condition
15 (16.384 MHz) mA Crystal Oscillator off
mA Current for each OSC in
addition to ICC1
Notes:
1. VCC = SV t10% unless otherwise specified, over specified temperature range.
2. Typical ICC was measured with oscillator off.
3. No ICC (OSC) max is specified due to dependency on external circuit and frequency of oscillation.
AC Characteristics
Figures 29 through 32 show read and write timing for the Z85C30 device.
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
51
1
PCLK
2
4
3
5
6
A/B, D/C
10
7
9
12
INTACK
11
10
15
14
13
CE
18
16
RD
19
21
20
22
D7–D0
Read
Active
Valid
23
17
24
26
25
27
WR
28
D7–D0
Write
31
30
29
W/REQ
Wait
32
35
W/REQ
Request
DTR/REQ
Request
33
34
36
INT
37
Figure 29. Z85C30 Read/Write Timing Diagram
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
52
PCLK
15
10
INTACK
38
10
14
RD
24
38
23
D7–D0
Active
Valid
26
40
41
42
IEI
44
43
IEO
45
INT
Figure 30. Z85C30 Interrupt Acknowledge Timing Diagram
49b
49b
PCLK
CE
49a
or
WR
Figure 31. Z85C30 Cycle Timing Diagram
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
53
WR
48
48
47
RD
Figure 32. Z85C30 Reset Timing Diagram
Z85C30 Read/Write Timing lists the read/write timing parameters for the Z85C30 device.
Table 6. Z85C30 Read/Write Timing
8.5 MHz
No
Symbol
Parameter
1
TwPCI
2
10 MHz
16 MHz
Min
Max
Min
Max
Min
Max
PCLK Low Width
45
2000
40
2000
26
2000
TwPCh
PCLK High Width
45
2000
40
2000
26
2000
3
TfPC
PCLK Fall Time
10
10
5
4
TrPC
PCLK Rise Time
10
10
5
5
TcPC
PCLK Cycle Time
118
6
TsA(WR)
Address to WR Fall
Setup Time
66
50
35
7
ThA(WR)
Address to WR Rise
Hold Time
0
0
0
8
TsA(RD)
Address to RD Fall
Setup Time
66
50
35
9
ThA(RD)
Address to RD Rise
Hold Time
0
0
0
4000
100
4000
61
4000
Notes:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Open-drain output, measured with open-drain test load.
3. Parameter applies to enhanced request mode oniy (WR7’ D4 = 1).
4. Parameter is system-dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of
TdPC(IEO) for the highest priority device in the daisy chain. TsiEI(RDA) for the SCC and TdIEI(IEO) for each
device separating them in the daisy chain.
5. Parameter applies only between transactions involving the Z85C30 SL1480, if WR/RD falling edge is synchronized to PCLK falling edge, then TrC = 3TcPc.
6. This specification is only applicable when Valid Access Recovery Time is less than 35 PCLK.
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
54
Table 6. Z85C30 Read/Write Timing (continued)
8.5 MHz
Min
Max
10 MHz
Min
Max
16 MHz
No
Symbol
Parameter
Min
10
TsiA(PC)
INTACK to PCLK Rise
Setup Time
20
20
15
11
TsiAi(WR)1
INTACK to WR Fall
Setup Time
140
120
70
12
ThIA(WR)
INTACK to WR Rise
Hold Time
0
0
0
13
TsiAi(RD)1
INTACK to RD Fall
Setup Time
140
120
70
14
ThIA(RD)
INTACK to RD Rise
Hold Time
0
0
0
15
ThIA(PC)
INTACK to PCLK Rise
Hold Time
38
30
15
16
TsCEI(WR)
CE Low to WR Fall
Setup Time
0
0
0
17
ThCE(WR)
CE to WR Rise Hold
Time
0
0
0
18
TsCEh(WR)
CE High to WR Fall
Setup Time
58
50
30
19
TsCEI(RD)1
CE Low to RD Fall
Setup Time
0
0
0
20
ThCE(RD)1
CE to RD Rise Hold
Time
0
0
0
21
TsCEh(RD)1
CE High to RD Fall
Setup Time
58
50
22
TwRDI1
RD Low Width
145
125
Max
30
70
Notes:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Open-drain output, measured with open-drain test load.
3. Parameter applies to enhanced request mode oniy (WR7’ D4 = 1).
4. Parameter is system-dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of
TdPC(IEO) for the highest priority device in the daisy chain. TsiEI(RDA) for the SCC and TdIEI(IEO) for each
device separating them in the daisy chain.
5. Parameter applies only between transactions involving the Z85C30 SL1480, if WR/RD falling edge is synchronized to PCLK falling edge, then TrC = 3TcPc.
6. This specification is only applicable when Valid Access Recovery Time is less than 35 PCLK.
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
55
Table 6. Z85C30 Read/Write Timing (continued)
8.5 MHz
Max
Symbol
Parameter
23
TdRD(DRA)
RD Fall to Read Data
Active Delay
0
0
0
24
TdRDr(DR)
RD Rise to Data Not
Valid Delay
0
0
0
25
TdRDI(DR)
RD Fall to Read Data
Valid Delay
135
120
70
26
TdRD(DRz)
RD Rise to Read Data
Float Delay
38
35
30
27
TdA(DR)
Addr to Read Data
Valid Delay
210
160
100
28
TwWRI
WR Low Width
29
TdWR(DW)
WR Fall to Write Data
Valid Delay
30
ThDW(WR)
Write Data to WR Rise
Hold Time
31
TdWR(W)2
WR Fall to Wait Valid
Delay
168
100
50
32
TdRD(W)2
RD Fall to Wait Valid
Delay
168
100
50
33
TdWRf(REQ)
WR Fall to W/REQ Not
Valid Delay
168
120
70
34
TdRDf(REQ)3
RD Fall to W/REQ Not
Valid Delay
168
120
70
WR Fall to DTR/REQ
Not Valid
4TcPc
4TcPc
4TcPc
145
Min
16 MHz
No
35a TdWRr(REQ)
Min
10 MHz
Max
Min
125
35
0
Max
75
35
20
0
0
Notes:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Open-drain output, measured with open-drain test load.
3. Parameter applies to enhanced request mode oniy (WR7’ D4 = 1).
4. Parameter is system-dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of
TdPC(IEO) for the highest priority device in the daisy chain. TsiEI(RDA) for the SCC and TdIEI(IEO) for each
device separating them in the daisy chain.
5. Parameter applies only between transactions involving the Z85C30 SL1480, if WR/RD falling edge is synchronized to PCLK falling edge, then TrC = 3TcPc.
6. This specification is only applicable when Valid Access Recovery Time is less than 35 PCLK.
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
56
Table 6. Z85C30 Read/Write Timing (continued)
8.5 MHz
No
Symbol
Parameter
Min
Max
10 MHz
Min
Max
16 MHz
Min
Max
35b TdWRr(REQ)3 WR Fall to DTR/REQ
Not Valid
168
100
70
36
TdRDrrREQ)
RD Rise to DTR/REQ
Not Valid Delay
NA
NA
NA
37
TdPC(INT)
PCLK Fall to INT Valid
Delay
500
320
175
38
TdIAi(RD)4
INTACK to RD Fall
(Ack) Delay
145
90
50
39
TwRDA
RD (Acknowledge)
Width
145
125
75
40
TdRDA(DR)
RD Fall (Ack) to Read
Data Valid Delay
135
120
70
41
TsiEI(RDA)
IEI to RD Fall (Ack)
Setup Time
95
80
50
42
ThIEI(RDA)
IEI to RD Rise (Ack)
Hold Time
0
0
0
43
TdIElrIEO)
IEI to IEO Delay Time
95
80
45
44
TdPC(IEO)
PCLK Rise to IEO
Delay
195
175
80
45
TdRDA(INT)2
RD Fall to INT Inactive
Delay
480
320
200
46
TdRDrWRQ)
RD Rise to WR Fall
Delay for No Reset
15
15
10
47
TdWRQ(RD)
WR Rise to RD Fall
Delay for No Reset
15
15
10
Notes:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Open-drain output, measured with open-drain test load.
3. Parameter applies to enhanced request mode oniy (WR7’ D4 = 1).
4. Parameter is system-dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of
TdPC(IEO) for the highest priority device in the daisy chain. TsiEI(RDA) for the SCC and TdIEI(IEO) for each
device separating them in the daisy chain.
5. Parameter applies only between transactions involving the Z85C30 SL1480, if WR/RD falling edge is synchronized to PCLK falling edge, then TrC = 3TcPc.
6. This specification is only applicable when Valid Access Recovery Time is less than 35 PCLK.
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
57
Table 6. Z85C30 Read/Write Timing (continued)
8.5 MHz
No
Symbol
Parameter
Min
48
TwRES
WR and RD Low for
Reset
145
Max
10 MHz
Min
100
49a Trce
Valid Access Recovery 3.5TcPc 3.5TcPc 3.5TcPc
Time
49b Trcif
RD or WR Fall to PC
Fall Setup Time
0
0
Max
16 MHz
Min
Max
75
0
Notes:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Open-drain output, measured with open-drain test load.
3. Parameter applies to enhanced request mode oniy (WR7’ D4 = 1).
4. Parameter is system-dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of
TdPC(IEO) for the highest priority device in the daisy chain. TsiEI(RDA) for the SCC and TdIEI(IEO) for each
device separating them in the daisy chain.
5. Parameter applies only between transactions involving the Z85C30 SL1480, if WR/RD falling edge is synchronized to PCLK falling edge, then TrC = 3TcPc.
6. This specification is only applicable when Valid Access Recovery Time is less than 35 PCLK.
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
58
Figure 33 shows a general timing diagram for the Z85C30 device.
PCLK
1
W/REQ
Request
2
W/REQ
Wait
3
CTS/TRxC,
RTxC
Receive
4
6
5
7
RxD
9
SYNC
External
8
CTS/TRxC,
RTxC
Transmit
10
11
12
TxD
13
CTS/TRxC
Output
14
15
RTxC
16
17
CTS/TRxC
19
18
20
CTS/TRxC
DCD
22
22
22
22
SYNC
Input
Figure 33. Z85C30 General Timing Diagram
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
59
Z85C30 General Timing Table lists the general timing characteristics for the Z85C30
device.
Table 7. Z85C30 General Timing Table
8.5 MHz
No
Symbol
Parameter
1
TdPC(REQ)
PCLK to W/REQ Valid
2
TdPC(W)
PCLK to Wait Inactive
3
4
5
6
7
8
9
10
11
TsRXC(PC)
TsRXD(RXCr)
ThRXD(RxCr)
TsRXD(RXCf)
ThRXD(RXCf)
TsSY(RXC)
ThSY(RXC)
TsTXC(PC)
TdTXCf(TXD)
Min
RxC to PCLK Setup Time
RxD to RxC Setup Time
RxD to /RXC Hold
RxD to /RXC Setup Time
TxC to TxD
TxD to TRxC Delay
15a
15b
16a
16b
17
TwRTXI
TwRTXI(E)
TcRTX
TcRTX(E)
TcRTXX
RTxC High
Width6
80
350
250
180
N/A
N/A
0
0
50
0
0
0
150 1
25
50
–200
–150
–100
5TcPc
5TcPc
5TcPc
N/A
N/A
N/A
200
150
80
200
150
80
200
140
80
150
120
80
7
50
40
15.6
TRxC Low Width
6
150
120
80
RTxC Low Width
7
50
40
15.6
488
400
244
125
100
31.25
RTxC High Width
RTxC Cycle
Time6,8
RTxC Cycle Time
7
Crystal Osc. Period
9
125
Max
150
125
3,4
TdTXD(TRX)
Min
150
Delay4
13
TwRTXh(E)
1
TxC to PCLK Setup Time
TxC to TxD Delay
14b
Time1
4,5
TdTxCr(TXD)
TwRTXh
1,3
RxD to /RXC Hold Time
SYNC to RxC Hold Time
Max
0
1,3
SYNC to RxC Setup
Min
16 MHz
250
N/A
1
Time1
12
14a
1,2
Max
10 MHz
1000
100
1000
62
1000
Notes:
1. RxC is RTxC or TRxC, whichever is supplying the receive clock.
2. Synchronization of RxC to PCLK is eliminated in divide by four operation.
3. Parameter applies only to FM encoding/decoding.
4. TxC is TRxC or /RTxC, whichever is supplying the transmit clock.
5. External PCLK to RTxC or TxC synchronization requirement eliminated for PCLK divide-by-four operation.TRxC
and RTxC rise and fall times are identical to PCLK. Reference timing specs TfPC and TrPC.Tx and Rx input
clock slew rates should be kept to a maximum of 30 nsec. All parameters related to input CLK edges must be
referenced at the point at which the transition begins or ends, whichever is worst case.
6. Parameter applies only for transmitter and receiver; DPLL and Baud Rate Generator timing requirements are
identical to case PCLK requirements.
7. Enhanced Feature — RTxC used as input to internal DPLL only.
8. The maximum receive or transmit data rate is 1/4 PCLK.
9. Both RTxC and SYNC have 30 pF capacitors to ground connections.
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
60
Table 7. Z85C30 General Timing Table (continued)
8.5 MHz
No
18
19
Symbol
Parameter
Min
Max
10 MHz
Min
Max
16 MHz
Min
TwTRXh
TRxC High Width
6
150
120
180
TwTRXI
Width6
150
120
80
488
400
244
TRxC Low
6,8
20
TcTRX
TRxC Cycle Time
21
TwEXT
DCD or CTS Pulse Width
200
120
70
22
TwSY
SYNC Pulse Width
200
120
70
Max
Notes:
1. RxC is RTxC or TRxC, whichever is supplying the receive clock.
2. Synchronization of RxC to PCLK is eliminated in divide by four operation.
3. Parameter applies only to FM encoding/decoding.
4. TxC is TRxC or /RTxC, whichever is supplying the transmit clock.
5. External PCLK to RTxC or TxC synchronization requirement eliminated for PCLK divide-by-four operation.TRxC
and RTxC rise and fall times are identical to PCLK. Reference timing specs TfPC and TrPC.Tx and Rx input
clock slew rates should be kept to a maximum of 30 nsec. All parameters related to input CLK edges must be
referenced at the point at which the transition begins or ends, whichever is worst case.
6. Parameter applies only for transmitter and receiver; DPLL and Baud Rate Generator timing requirements are
identical to case PCLK requirements.
7. Enhanced Feature — RTxC used as input to internal DPLL only.
8. The maximum receive or transmit data rate is 1/4 PCLK.
9. Both RTxC and SYNC have 30 pF capacitors to ground connections.
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
61
Figure 34 shows the system timing for the Z85C30 device.
RTxC, TRxC
Receive
W/REQ
Request
1
W/REQ
Wait
2
SYNC
Output
3
INT
4
TRxC, RTxC
Transmit
W/REQ
Request
6
W/REQ
Wait
6
DTR/REQ
Request
7
INT
8
CTS, DCD
SYNC
Input
9
INT
10
Figure 34. Z85C30 System Timing Diagram
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
62
Z85C30 System Timing Table lists the system timing characteristics for the Z85C30
device.
Table 8. Z85C30 System Timing Table
8.5 MHz
No
1
2
3
4
5
6
7
8
9a
9b
10
Symbol
Parameter
TdRXC(REQ)
TdRXC(W)
TdRdXC(SY)
TsRXC(INT)
TdTXC(REQ)
TdTXC(W)
TdTXC(DRQ)
TdTXC(INT)
TdSY(INT)
TdSY(INT)
TdEXT(INT)
RxC High to W/REQ Valid
RxC High to Wait
1,2
Inactive1,2,3
RxC High to SYNC Valid
Min
Max
Min
Max
Min
Max
8
12
8
12
8
12
8
14
8
14
8
14
4
7
4
7
4
70
10
16
10
16
10
16
Valid2,4
5
8
5
8
5
8
5
11
5
11
5
11
TxC Low to Wait Inactive
2,3,4
TxC Low to DTR/REQ Valid
TxC Low to INT
16 MHz
1,2,3
RxC High to INT Valid
TxC Low to W/REQ
1,2
10 MHz
3,4
4
7
4
7
4
7
Valid2,3,4
6
10
6
10
6
10
2,3
2
6
2
6
2
6
2,3,5
2
3
2
3
2
3
2
6
2
6
2
6
SYNC to INT Valid
SYNC to INT Valid
DCD or CTS to INT
Valid2,3
Notes:
1. RxC is RTxC or TRxC, whichever is supplying the receive clock.
2. Units equal to TcPc.
3. Open-drain output, measured with open-drain test load.
4. TxC is TRxC or RTxC whichever is supplying the transmit clock.
5. Units equal to AS.
Z85C30 Read/Write Timing provides the read/write timing characteristics for the Z85C30
device.
Table 9. Z85C30 Read/Write Timing
8.5 MHz
No
Symbol
Parameter
1
TwPCI
2
10 MHz
16 MHz
Min
Max
Min
Max
Min
Max
PCLK Low Width
45
2000
40
2000
26
2000
TwPCh
PCLK High Width
45
2000
40
2000
26
2000
3
TfPC
PCLK Fail Time
10
10
5
4
TrPC
PCLK Rise Time
10
10
5
5
TcPC
PCLK Cycle Time
118
6
TsA(WR)
Address to WR Fail Setup Time
66
50
35
7
ThA(WR)
Address to WR Rise Hold Time
0
0
0
PS011708-0115
4000
100
4000
61
4000
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
63
Table 9. Z85C30 Read/Write Timing (continued)
8.5 MHz
Max
Min
Max
16 MHz
No
Symbol
Parameter
8
TsA(RD)
Address to RD Fall Setup Time
66
50
35
9
ThA(RD)
Address to RD Rise Hold Time
0
0
0
10
TsiA(PC)
INTACK to PCLK Rise Setup Time
20
20
15
PS011708-0115
Min
10 MHz
Min
Max
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
64
Figures 35 through 37 show the read/write timing, interrupt acknowledge timing and reset
timing, respectively, for the Z80C30 device.
AS
2
4
CS0
7
CS1
4
6
14
INTACK
7
8
R/W
Read
9
10
R/W
Write
12
10
DS
12
AD7–AD0
Write
13
18
16
15
17
AD7–AD0
Read
20
16
19
15
23
21
22
24
W/REQ
Wait
25
W/REQ
Request
26
DTR/REQ
Request
27
INT
44
PCLK
41
40
43
42
44
Figure 35. Z80C30 Read/Write Timing Diagram
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
65
AS
7
INTACK
8
DS
30
29
20
19
AD7–AD0
31
22
32
33
IEI
35
34
IEO
36
INT
Figure 36. Z80C30 Interrupt Acknowledge Timing Diagram
AS
37
38
35
DS
Figure 37. Z80C30 Reset Timing Diagram
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
66
Z80C30 Read/Write Timing1 provides the read/write timing characteristics for the
Z80C30 device.
Table 10. Z80C30 Read/Write Timing1
8 MHz
No
Symbol
Parameter
1
TwAS
AS Low Width
2
3
4
5
TdDS(AS)
DS Rise to AS Fall
Min
Delay2
2
10 MHz
Max
Min
35
30
15
10
TsCSO(AS)
CS0 to AS Rise Setup Time
0
0
ThCSO(AS)
2
30
20
Time2
65
50
2
TsCS1(DS)
CS0 to AS Rise Hold Time
CS1 to DS Fall Setup
6
ThCS1(DS)
CS1 to DS Rise Hold Time
30
20
7
TsiA(AS)
INTACK to AS Rise Setup Time
10
10
8
ThIA(AS)
INTACK to AS Rise Hold Time
150
125
9
TsRWR(DS)
R/W (Read) to DS Fall Setup Time
65
50
10
ThRW(DS)
R/W to DS Rise Hold Time
0
0
11
TsRWW(DS)
R/W (Write) to DS Fall Setup Time
0
0
12
TdAS(DS)
AS Rise to DS Fall Delay
30
20
13
TwDSI
DS Low Width
150
125
4TcPC
4TcPC
10
10
25
20
14
15
TrC
Valid Access Recovery
Time3
2
TsA(AS)
Address to AS Rise Setup Time
16
ThA(AS)
Address to AS Rise Hold Time
2
17
TsDW(DS)
Write Data to DS Fall Setup Time
15
10
18
ThDW(DS)
Write Data to DS Rise Hold Time
0
0
19
TdDS(DA)
DS Fall to Data Active Delay
0
0
20
TdDSr(DR)
DS Rise to Read Data Not Valid Delay
0
0
21
TdDSf(DR)
DS Fall to Read Data Valid Delay
140
Max
120
Notes:
1. Units in nanoseconds (ns) unless otherwise noted.
2. Parameter does not apply to Interrupt Acknowledge transactions.
3. Parameter applies only between transactions involving the SCC.
4. Float delay is defined as the time required for a 0.5 V change in the output with a maximum DC load and a minimum AC load.
5. Open-drain output, measured with open-drain test load.
6. Parameter is system dependent. For any Z-SCC in the daisy chain. TdAS(DSA) must be greater than the sum of
TdAS(IEO) for the highest priority device in the daisy chain TsiEI(DSA) for the Z-SCC, and TdIElf(IEO) for each
device separating them in the daisy chain.
7. Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction.
8. Internal circuitry allows for the reset provided by the ZB to be recognized as a reset by the Z-SCC. All timing references assume 20 V for a logic “1” and 08 V for a logic “0”.
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
67
Table 10. Z80C30 Read/Write Timing1 (continued)
8 MHz
No
Symbol
Parameter
Min
22
TdAS(DR)
AS Rise to Read Data Valid Delay
Delay4
10 MHz
Max
Min
Max
250
190
40
35
23
TdDS(DRz)
DS Rise to Read Data Float
24
TdA(DR)
Address Required Valid to Read Data
Valid Delay
260
210
25
TdDS(W)
DS Fall to Wait Valid Delay5
170
160
26
TdDSf(REQ)
DS Fall to W/REQ Not Valid Delay
170
160
27
TdDSr(REQ)
DS Fall to DTR/REQ Not Valid Delay
4TcPC
4TcPC
500
500
5
28
TdAS(INT)
AS Rise to INT Valid Delay
29
TdAS(DSA)
AS Rise to DS Fall (Acknowledge)
Delay6
250
225
30
TwDSA
DS (Acknowledge) Low Width
150
125
31
TdDSA(DR)
DS Fall (Acknowledge) to Read Data
Valid Delay
32
TsiEI(DSA)
IEI to DS Fall (Acknowledge) Setup
Time
80
80
33
ThIEI(DSA)
IEI to DS Rise (Acknowledge) Hold
Time
0
0
34
TdIEI(IEO)
IEI to IEO Delay
90
90
35
TdAS(IEO)
AS Rise to IEO Delayg
200
175
36
TdDSA(INT)
DS Fall (Acknowledge) to INT Inactive
Delay5
450
450
37
TdDS(ASQ)
DS Rise to AS Fall Delay for No Reset
15
15
38
TdASQ(DS)
AS Rise to DS Fall Delay for No Reset
20
15
TwRES
AS and DS Coincident Low for Reseth
150
100
39
140
120
Notes:
1. Units in nanoseconds (ns) unless otherwise noted.
2. Parameter does not apply to Interrupt Acknowledge transactions.
3. Parameter applies only between transactions involving the SCC.
4. Float delay is defined as the time required for a 0.5 V change in the output with a maximum DC load and a minimum AC load.
5. Open-drain output, measured with open-drain test load.
6. Parameter is system dependent. For any Z-SCC in the daisy chain. TdAS(DSA) must be greater than the sum of
TdAS(IEO) for the highest priority device in the daisy chain TsiEI(DSA) for the Z-SCC, and TdIElf(IEO) for each
device separating them in the daisy chain.
7. Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction.
8. Internal circuitry allows for the reset provided by the ZB to be recognized as a reset by the Z-SCC. All timing references assume 20 V for a logic “1” and 08 V for a logic “0”.
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
68
Table 10. Z80C30 Read/Write Timing1 (continued)
8 MHz
No
Symbol
Parameter
40
TwPCI
41
10 MHz
Min
Max
Min
Max
PCLK Low Width
50
1000
40
1000
TwPCh
PCLK High Width
50
1000
40
1000
42
TcPC
PCLK Cycle Time
125
2000
100
2000
43
TrPC
PCLK Rise Time
10
10
44
TfPC
PCLK Fall Time
10
10
Notes:
1. Units in nanoseconds (ns) unless otherwise noted.
2. Parameter does not apply to Interrupt Acknowledge transactions.
3. Parameter applies only between transactions involving the SCC.
4. Float delay is defined as the time required for a 0.5 V change in the output with a maximum DC load and a minimum AC load.
5. Open-drain output, measured with open-drain test load.
6. Parameter is system dependent. For any Z-SCC in the daisy chain. TdAS(DSA) must be greater than the sum of
TdAS(IEO) for the highest priority device in the daisy chain TsiEI(DSA) for the Z-SCC, and TdIElf(IEO) for each
device separating them in the daisy chain.
7. Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction.
8. Internal circuitry allows for the reset provided by the ZB to be recognized as a reset by the Z-SCC. All timing references assume 20 V for a logic “1” and 08 V for a logic “0”.
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
69
Figure 38 shows a general timing diagram for the Z80C30 device, and Z80C30 General
Timing1 lists its associated general timing characteristics.
PCLK
1
W/REQ
Request
2
W/REQ
Wait
3
RTxC, TRxC
Receive
5
4
6
7
RxD
8
9
SYNC
External
10
TRxC, RTxC
Transmit
12
11
TxD
13
TRxC
Output
14
15
RTxC
16
17
TRxC
18
19
20
CTS, DCD
22
22
22
22
SYNC
Input
Figure 38. Z80C30 General Timing Diagram
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
70
Table 11. Z80C30 General Timing1
8 MHz
No
Symbol
Parameter
Min
1
TdPC(REQ)
PCLK Low to W/REQ Valid
2
TsPC(W)
PCLK Low to Wait Inactive
2,3
3
TsRXC(PC)
RxC High to PCLK High Setup Time
4
TsRXD(RXCr)
RxD to RxC High Setup Time
ThRXD(RxCr)
2
5
6
7
8
9
10
11
TsRXD(RXCf)
ThRXD(RXCf)
RxD to RxC High Hold Time
2,4
RxD to RxC Low Setup Time
RxD to RxC Low Hold
Time2,4
2
TsSY(RXC)
SYNC to RxC High Setup Time
ThSY(RXC)
SYNC to RxC High Hold Time
2
TxC Low to PCLK High Setup
Time3,5
TsTXC(PC)
TdTXCf(TXD)
TxC Low to TxD Delay
16a TcRTX
16b TxRx (DPLL)
17
18
19
TcRTXX
RTxC Cycle
350
300
NA
NA
0
0
150
125
0
0
150
125
-200
-150
5TcPc
5TcPc
NA
NA
200
140
6
130
120
6
130
120
472
400
59
50
Time6,7
DPLL Cycle Time Min
Crystal Osc. Period
7,8
9
118
1000
100
TwTRXh
TRxC High Width
6
130
120
TwTRXI
Width6
130
120
472
400
TRxC Low
NA
150
TxD to TRxC Delay
TRxC Low Width
200
190
TdTXD(TRX)
TwRTXI
250
150
13
RTxC High Width
Max
190
TxC High to TxD Delay
15
Min
4,5
TdTxCr(TXD)
TwRTXh
Max
5
12
14
NA
10 MHz
6,7
20
TcTRX
TRxC Cycle Time
21
TwEXT
DCD or CTS Pulse Width
200
120
22
TwSY
SYNC Pulse Width
200
120
1000
Notes:
1. Units in nanoseconds (ns) otherwise noted.
2. RxC is RTxC or (TRxC, whichever is supplying the receive clock.
3. Synchronization of RxC to PCLK is eliminated in divide by four operation.
4. Parameter applies only to FM encoding/decoding.
5. TxC is TRxC or RTxC, whichever is supplying the transmit clock.
6. Parameter applies only for transmitter and receiver; DPLL and Baud Rate Generator timing requirements are
identical to case PCLK requirements.
7. The maximum receive or transmit data rate is 1/4 PCLK.
8. Applies to DPLL clock source oniy Maximum data rate of 1/4 PCLK still applies DPLL clock should have a 50%
duty cycle.
9. Both RTxC and SYNC have 30 pf capacitors to ground connected to them.
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
71
Figure 39 shows a system timing diagram for the Z80C30 device, and Z80C30 System
Timing lists its associated parameters.
PCLK
1
W/REQ
Request
2
W/REQ
Wait
3
RTxC, TRxC
Receive
4
6
5
7
RxD
9
8
SYNC
External
10
TRxC, RTxC
Transmit
11
12
TxD
10
TRxC
Output
15
14
RTxC
18
17
TRxC
19
18
20
CTS, DCD
21
21
22
22
SYNC
Input
Figure 39. Z80C30 System Timing Diagram
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
72
Table 12. Z80C30 System Timing
8 MHz
No
1
2
3
4
5
6
7
8
9a
9b
10
Symbol
TdRXC(REQ)
TdRXC(W)
TdRdXC(SY)
TdRXC(INT)
TdTXC(REQ)
TdTXC(W)
TdTXC(DRQ)
TdTXC(INT)
TdSY(INT)
Parameter
RxC High to W/REQ
Valid1,2
RxC High to Wait Inactive
RxC High to SYNC Valid
RxC High to INT
1,2,3
1,2
Valid1,2,3
TxC Low to W/REQ Valide,2
TxC Low to Wait Inactive
1,2,3
TxC Low to DTR/REQ Valid
TxC Low to INT Valid
2,3
1,2
SYNC to INT Valid2,3
TdSY(INT)
SYNC to INT Valid
TdEXT(INT)
Note2,3,4
2,3,4
10 MHz
Min
Max
Min
Max
8
12
8
12
8
14
8
14
4
7
4
7
8
12
8
12
4
2
4
3
4
2
34
5
8
5
8
5
11
5
11
4
7
4
7
4
6
4
6
24
34
24
34
2
6
2
6
2
3
2
3
2
3
2
3
Notes:
1. RxC is RTxC or TRxC whichever is supplying the receive clock.
2. Units equal to TcPc.
3. Open-drain output, measured with open-drain test load.
4. Units equal to AS.
5. TxC is TRxC or RTxC, whichever is supplying the transmit clock.
PS011708-0115
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
73
Packaging
Figure 40 shows the 40-pin DIP package available for the Z80C30 and Z85C30 devices.
Figure 40. 40-Pin DIP Package Diagram
PS011708-0115
Packaging
CMOS SCC Serial Communications Controller
Product Specification
74
Figure 41 shows the 44-pin Plastic Leaded Chip Carriers (PLCC) package diagram available for Z80C30 and Z85C30 devices.
Figure 41. 44-Pin PLCC Package Diagram
PS011708-0115
Packaging
CMOS SCC Serial Communications Controller
Product Specification
75
Ordering Information
Z80C30/Z85C30 Ordering Information provides ordering information for the Z80C30 and
the Z85C30 devices.
Table 13. Z80C30/Z85C30 Ordering Information
8 MHz
10 MHz
16 MHz
Z80C3008VSG
Z80C3010VSG
Z85C3016PSG
Z85C3008PSG/PEG
Z85C3010PSG/PEG
Z85C3016VSG
Z85C3008VSG/VEG
Z85C3010VSG/VEG
For complete details about Zilog’s Z80C30 and Z85C30 devices, development tools and
downloadable software, visit www.zilog.com.
Part Number Suffix Designations
Zilog part numbers consist of a number of components, as indicated in the following
example:
Part number Z80C3016PSG is a Z80C30, 16 MHz, PLCC, 0º C to +70º C, Lead Free
Z
80C30
16
P
S
G
Environmental Flow
G = Lead Free
Ambient Temperature Range (TA)
S = 0º C to +70º C
E = Extended, –40° C to +100° C
Package
P = Plastic DIP
V = Plastic Leaded Chip Carrier
D = Ceramic DIP
Speed
8 = 8 MHz
10 = 10 MHz
16 = 16 MHz
Product Number
Zilog Prefix
PS011708-0115
Ordering Information
CMOS SCC Serial Communications Controller
Product Specification
76
Customer Support
To share comments, get your technical questions answered, or report issues you may be
experiencing with our products, please visit Zilog’s Technical Support page at
http://support.zilog.com.
To learn more about this product, find additional documentation, or to discover other facets about Zilog product offerings, please visit the Zilog Knowledge Base at http://
zilog.com/kb or consider participating in the Zilog Forum at http://zilog.com/forum.
This publication is subject to replacement by a later edition. To determine whether a later
edition exists, please visit the Zilog website at http://www.zilog.com.
PS011708-0115
Customer Support
工商网监
湘ICP备2023018690号
