Z86C6116PSCR1546

PRELIMINARY PRODUCT SPECIFICATION 1 Z86C61/62/96 1 CMOS Z8 MICROCONTROLLER FEATURES Device Z86C61 Z86C62 Z86C96 ROM (KB) RAM* (Bytes) I/O Lines 16 16 16 236 236 236 32 52 52 ■ All Digital Inputs are TTL Levels ■ Auto Latches ■ RAM and ROM Protect ■ Two Programmable 8-Bit Counter/Timers, ■ Each with 6-Bit Programmable Prescaler ■ Six Vectored, Priority Interrupts from Eight Different Sources Note: *General-Purpose ■ 3.0V to 5.5V Operating Range ■ Low Power Consumption: 200 mW (max) ■ Fast Instruction Pointer: 0.75 µs @ 16 MHz ■ Clock Speeds: 16 and 20 MHz ■ Two Standby Modes: STOP and HALT ■ On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, or External Clock Drive ■ Full-Duplex UART GENERAL DESCRIPTION The Z86C61/62/96 microcontroller is a member of the Z8 single-chip microcontroller family with 16 KB of ROM and 236 bytes of RAM. The Z86C96 is ROMless. The Z86C61 is offered in 40-pin DIP and 44-pin PLCC style packages, however, the ROMless pin option is available on the 44-pin version only. The Z86C62/96 is offered in 64pin DIP and 68-pin PLCC style packages. A ROMless pin option enables these MCUs to address both external memory and preprogrammed ROM, making them well-suited for high-volume applications or where code flexibility is required. With 16 KB of ROM and 236 bytes of general-purpose RAM, these low-cost, low power consumption CMOS Z86C61/62/96 MCUs offer fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion. DS97Z8X1600 The Z86C61/62/96 architecture is characterized by Zilog’s 8-bit microcontroller core. The device offers a flexible I/O scheme, an efficient register and address space structure, multiplexed capabilities between address/data, I/O, and a number of ancillary features that are useful in many industrial and advanced scientific applications. For applications which demand powerful I/O capabilities, the Z86C61 fulfills this with 32 pins dedicated to input and output. These lines are grouped into four ports with eight lines each. The Z86C62/96 has 52 pins for input and output, and these lines are grouped into six, 8-bit ports and one 4-bit port. Each port is configurable under software control to provide timing, status signals, serial or parallel I/O with or without handshake, and an address/data bus for interfacing external memory. There are three basic address spaces available to support this configuration: Program Memory, Data Memory, and 236 General-Purpose Registers. PRELIMINARY PS003501-0301 1 Z86C61/62/96 CMOS Z8 Microcontroller Zilog GENERAL DESCRIPTION (Continued) To unburden the program from coping with the real-time tasks, such as counting/timing and serial data communication, the Z86C61/62/96 offers two on-chip counter/timers with a large number of user selectable modes, and an onboard UART (Figures 1, 2, and 3). Power connections follow conventional descriptions below: Notes: All Signals with a preceding front slash, "/", are active Low. For example B//W (WORD is active Low); /B/W (BYTE is active Low, only). Output Input Vcc Connection Circuit Device Power VCC VDD Ground GND VSS GND XTAL /AS /DS R//W /RESET Machine Timing and Instruction Control Port 3 UART ALU Counter/ Timers (2) FLAGS Prg. Memory 16,384 x 8-Bit Register Pointer Interrupt Control Register File 256 x 8-Bit Program Counter Port 0 Port 1 Port 2 4 I/O (Bit Programmable) 4 Address or I/O (Nibble Programmable) 8 Address/Data or I/O (Byte Programmable) Figure 1. Z86C61 Functional Block Diagram 2 PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog Output Input Vcc GND XTAL /AS /DS R//W /RESET 1 Port 3 Machine Timing and Instruction Control ALU UART Program Memory 16,384 x 8-Bit Flags Counter/ Timers (2) Register Pointer Interrupt Control Port 6 Port 5 Port 4 Register File 256 x 8-Bit Port 2 Port 0 4 I/O (Bit Programmable) I/O (Bit Programmable) Program Counter Port 1 4 Address or I/O (Nibble Programmable) 8 Address/Data or I/O (Byte Programmable) Figure 2. Z86C62 Functional Block Diagram DS97Z8X1600 PRELIMINARY PS003501-0301 3 Z86C61/62/96 CMOS Z8 Microcontroller Zilog GENERAL DESCRIPTION (Continued) Output Input Vcc GND Port 3 XTAL /AS /DS R//W /RESET Machine Timing and Instruction Control ALU UART Flags Counter/ Timers (2) Register Pointer Interrupt Control Port 6 Port 5 Port 4 Register File 256 x 8-Bit Port 2 Port 0 4 I/O (Bit Programmable) Program Counter Port 1 4 Address or I/O (Nibble Programmable) 8 Address/Data or I/O (Byte Programmable) Z-BUS When Used As Address/Data Bus Figure 3. Z86C96 Functional Block Diagram 4 PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog PIN DESCRIPTION Table 1. Z86C61 40-Pin DIP Pin Identification VCC XTAL2 XTAL1 P37 P30 /RESET R//W /DS /AS P35 GND P32 P00 P01 P02 P03 P04 P05 P06 P07 1 21 DIP 40 - Pin 20 40 Pin # P36 P31 P27 P26 P25 P24 P23 P22 P21 P20 P33 P34 P17 P16 P15 P14 P13 P12 P11 P10 Function VCC Power Supply Input 2 XTAL2 Output 3 XTAL1 Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pin 7 Port 3, Pin 0 Reset Read/Write Data Strobe Address Strobe Port 3, Pin 5 Ground Port 3, Pin 2 Port 0, Pins 0,1,2,3,4,5,6,7 Port 1, Pins 0,1,2,3,4,5,6,7 Port 3, Pin 4 Port 3, Pin 3 Port 2, Pins 0,1,2,3,4,5,6,7 Port 3, Pin 1 Port 3, Pin 6 P37 P30 /RESET R//W /DS /AS P35 GND P32 P07-P00 21-28 P17-P10 29 P34 30 P33 31-38 P27-P20 39 40 P31 P36 PRELIMINARY PS003501-0301 1 Direction 1 4 5 6 7 8 9 10 11 12 13-20 Figure 4. Z86C61 40-Pin DIP Pin Assignments DS97Z8X1600 Symbol Input Output Input Input Output Output Output Output Input Input In/Output In/Output Output Input In/Output Input Output 5 Z86C61/62/96 CMOS Z8 Microcontroller Zilog PIN DESCRIPTION (Continued) 6 /RESET R//W /DS /AS P35 GND P32 P00 P01 P02 R//RL 1 40 39 7 PLCC 44 - Pin 17 29 28 18 NC P24 P23 P22 P21 P20 P33 P34 P17 P16 P15 Figure 5. Z86C61 44-Pin PLCC Pin Assignments Table 2. Z86C61 44-Pin PLCC Pin Assignments Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14-16 17 18-22 6 Symbol Function Direction VCC Power Supply Input XTAL2 XTAL1 P37 P30 N/C /RESET R//W /DS /AS P35 GND P32 P02-P00 R//RL P07-P03 Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pin 7 Port 3, Pin 0 Not Connected Reset Read/Write Data Strobe Address Strobe Port 3, Pin 5 Ground Port 3, Pin 2 Port 0, Pins 0,1,2 ROM/ROMless control Port 0, Pins 3,4,5,6,7 Output Input Output Input Input Input Output Output Output Output Input Input In/Output Input In/Output Table 2. Z86C61 44-Pin PLCC Pin Assignments Pin # 23-27 28 29-31 32 33 34-38 39 40-42 43 44 Symbol P14-P10 N/C P17-P15 P34 P33 P24-P20 N/C P25-P27 P31 P36 PRELIMINARY PS003501-0301 Function Port 1, Pins 0,1,2,3,4 Not Connected Port 1, Pins 5,6,7 Port 3, Pin 4 Port 3, Pin 3 Port 2, Pins 0,1,2,3,4 Not Connected Port 2, Pins 5,6,7 Port 3, Pin 1 Port 3, Pin 6 Direction In/Output Input In/Output Output Input In/Output Input In/Output Input Output DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog Table 3. Z86C62/C96 64-Pin DIP Pin Identification P44 VCC P45 XTAL2 XTAL1 P37 P30 NC /RESET R//W /DS P46 P47 /AS P35 R//RL GND P32 P50 P51 P00 P01 P02 P03 P04 P05 P06 P07 VCC P52 P53 P54 1 32 33 64 P43 P42 P36 P31 P41 P40 P27 P26 P25 P24 P23 P22 P60 P61 P21 P20 GND P33 P34 P62 P63 P17 P16 P15 P14 P13 P12 P57 P56 P11 P10 P55 Figure 6. Z86C62/C96 64-Pin DIP Pin Assignments DS97Z8X1600 Pin # Symbol Function Direction 1 2 P44 VCC Port 4, Pin 4 Power Supply In/Output Input 3 4 P45 XTAL2 In/Output Output 5 XTAL1 6 7 8 9 10 11 12-13 14 15 16 P37 P30 N/C /RESET R//W /DS P47-P46 /AS P35 R//RL 17 18 19-20 21-28 GND P32 P51-P50 P07-P00 29 VCC Port 4, Pin 5 Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pin 7 Port 3, Pin 0 Not Connected Reset Read/Write Data Strobe Port 4, Pin 6,7 Address Strobe Port 3, Pin 5 ROM/ROMless control Ground Port 3, Pin 2 Port 5, Pin 0,1 Port 0, Pins 0,1,2,3,4,5,6,7 Power Supply 30-33 34-35 36-37 38-43 P52-P55 P11-P10 P57-P56 P17-P12 44-45 46 47 48 49-50 51-52 53-58 P63-P62 P34 P33 GND P21-P20 P61-P60 P27-P22 59-60 61 62 63 64 P41-P40 P31 P36 P42 P43 PRELIMINARY PS003501-0301 Port 5, Pins 2,3,4,5 Port 1, Pins 0,1 Port 5, Pins 6,7 Port 1, Pins 2,3,4,5,6,7 Port 6, Pins 3,2 Port 3, Pin 4 Port 3, Pin 3 Ground Port 2, Pins 0,1 Port 6, Pins 1,0 Port 2, Pins 2,3,4,5,6,7 Port 4, Pins 0,1 Port 3, Pin 1 Port 3, Pin 6 Port 4, Pin 2 Port 4, Pin 3 1 Input Output Input Input Input Output Output In/Output Output Output Input Input Input In/Output In/Output Input In/Output In/Output In/Output In/Output In/Output Output Input Input In/Output In/Output In/Output In/Output Input Output In/Output In/Output 7 Z86C61/62/96 CMOS Z8 Microcontroller Zilog PIN DESCRIPTION (Continued) R//W /PODS /DS P46 P47 /P1DS /AS /DTimers P35 R//RL GND P32 P50 P51 P00 P01 P02 9 10 1 61 60 PLCC 68 - Pin 26 27 44 43 P24 P23 P22 P60 P61 P21 P20 SCLK /SYNC GND P33 P34 P62 P63 P17 P16 P15 Figure 7. Z86C62/C96 68-Pin PLCC Pin Assignments 8 PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog Table 4. Z86C62/C96 68-Pin PLCC Pin Identification Pin # Symbol Function Direction 1-2 3 P44-P43 VCC Port 4, Pins 3,4 Power Supply In/Output Input 4 5 6 7 8 9 10 11 12 13-14 15 16 17 18 19 20 21 22-23 24-31 32 P45 XTAL2 XTAL1 P37 P30 /RESET R//W /P0DS /DS P47-P46 /P1DS /AS /DTIMER P35 R//RL GND P32 P51-P50 P07-P00 VCC Port 4, Pin 5 Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pin 7 Port 3, Pin 0 Reset Read/Write Port 0 Data Strobe Data Strobe Port 4, Pins 6,7 Port 1, Data Strobe Address Strobe DTIMER Port 3, Pin 5 ROM/ROMless control Ground Port 3, Pin 2 Port 5, Pins 0,1 Port 0, Pins 0,1,2,3,4,5,6,7 Power Supply In/Output Output Input Output Input Input Output Output Output In/Output Output Output Input Output Input Input Input In/Output In/Output Input 33-36 37-38 39-40 41-46 47-48 49 50 51 52 53 54-55 56-57 58-63 64-65 66 67 68 P55-P52 P11-P10 P56-P57 P17-P12 P63-P62 P34 P33 GND /SYNC SCLK P21-P20 P60-P61 P27-P22 P41-P40 P31 P36 P42 Port 5, Pins 2,3,4,5 Port 1, Pins 0,1 Port 5, Pins 6,7 Port 1, Pins2,3,4,5,6,7 Port 6, Pins 3,2 Port 3, Pin 4 Port 3, Pin 3 Ground Synchronization System Clock Port 2, Pins 0,1 Port 6, Pins 1,0 Port 2, Pins 2,3,4,5,6,7 Port 4, Pins 0,1 Port 3, Pin 1 Port 3, Pin 6 Port 4, Pin 2 In/Output In/Output In/Output In/Output In/Output Output Input Input Output Output In/Output In/Output In/Output In/Output Input Output In/Output DS97Z8X1600 PRELIMINARY PS003501-0301 1 9 Z86C61/62/96 CMOS Z8 Microcontroller Zilog ABSOLUTE MAXIMUM RATINGS Sym Description Min Max Units VCC Supply Voltage* –0.3 +7.0 V TSTG Storage Temp –65 +150 C TA Oper Ambient Temp † † Notes: *Voltages on all pins with respect to GND. †See ordering information Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Figure 4). I Figure 8. Test Load Diagram 10 PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog DC ELECTRICAL CHARACTERISTICS Z86C61/62/96 TA = 0°C to +70°C Sym Parameter Min Max Input Voltage VCH Max 1 TA = -40°C to +105°C Typical Min Max 7 @ 25°C Units 7 V IIN < 250 µA Driven by External Clock Generator Driven by External Clock Generator 0.85 VCC VCC + 0.3 0.85 VCC VCC + 0.3 V VSS – 0.3 0.8 VSS – 0.3 0.8 V VIH Clock Input High Voltage Clock Input Low Voltage Input High Voltage 2 VCC + 0.3 2 VCC + 0.3 V VIL Input Low Voltage VSS – 0.3 0.2 VCC VSS – 0.3 0.2 VCC V VOH Output High Voltage VOH Output High Voltage VOL VCL 2.4 Conditions 2.4 V IOH = –2.0 mA VCC – 100 mV 0.4 V IOH = –100 µA Output Low Voltage VCC – 100 mV 0.4 V IOL = +5.0 mA [3] VOL Output Low Voltage 0.6 0.6 V IOL = +4.0 mA [2] VRH 0.85 VCC VCC + 0.3 0.85 VCC VCC + 0.3 V –0.3 0.2 VCC –0.3 0.2 VCC V IIL Reset Input High Voltage Reset Input Low Voltage Input Leakage –2 2 –2 2 µA VIN = 0V, VCC IOL Output Leakage –2 2 –2 2 µA VIN = 0V, VCC µA VRL = 0 V VRl IIR Reset Input Current –80 –80 ICC Supply Current 35 35 24 mA [1] @ 16 MHz ICC Supply Current 40 40 30 mA [1] @ 20 MHz ICC1 Standby Current 15 15 4.5 ICC2 Standby Current 10 20 5 mA [1] HALT Mode VIN = 0 V, VCC @ 16 MHz µA [1] STOP Mode VIN = 0 V, VCC Notes: 1. All inputs driven to either 0V or VCC, outputs floating. 2. VCC = 3.0V to 3.6V 3. VCC = 4.5V to 5.5V DS97Z8X1600 PRELIMINARY PS003501-0301 11 Z86C61/62/96 CMOS Z8 Microcontroller Zilog DC ELECTRICAL CHARACTERISTICS (Continued) R//W Port 0, /DM Port 1 A7 - A0 D7 - D0 IN /AS /DS (Read) Port 1 A7 - A0 D7 - D0 OUT /DS (Write) Figure 9. External I/O or Memory Read/Write 12 PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog AC CHARACTERISTICS External I/O or Memory Read and Write Timing Z86C61/62/96 (16 MHz) No Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TdA(AS) TdAS(A) TdAS(DR) TwAS TdAZ(DS) TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) 15 TdDS(DW) 16 TdA(DR) 17 18 TdAS(DS) TdDM(AS) 1 TA = 0°C to +70°C TA = -40°C to +105°C 16 MHz 16 MHz Parameter Min Address Valid to /AS rise Delay /AS rise to Address Float Delay /AS rise to Read Data Req’d Valid /AS Low Width Address Float to /DS fall /DS (Read) Low Width /DS (Write) Low Width /DS fall to Read Data Req’d Valid Read Data to /DS rise Hold Time /DS rise to Address Active Delay /DS rise to /AS fall Delay R//W Valid to /AS rise Delay /DS rise to R//W Not Valid Write Data Valid to /DS fall (Write) Delay /DS rise to Write Data Not Valid Delay Address Valid to Read Data Req’d Valid /AS rise to /DS fall Delay /DM Valid to /AS rise Delay 25 35 Max Min Max 25 35 Units Notes 2,3 2,3 1,2,3 2,3 80 75 0 50 35 25 35 25 80 75 0 50 35 25 35 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 35 35 ns 2,3 ns 1,2,3 ns ns 2,3 2,3 150 40 0 150 40 0 135 135 210 45 25 210 45 25 1,2,3 1,2,3 1,2,3 2,3 2,3 2,3 2,3 2,3 2,3 Notes: 1. When using extended memory timing add 2 TpC. 2. Timing numbers given are for minimum TpC. 3. See clock cycle dependent characteristics table. Standard Test Load All timing references use 2.0 V for a logic 1 and 0.8 V for a logic 0. Table 5. Clock Dependent Formulas Number 1 2 3 4 6 7 DS97Z8X1600 Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS TwDSR TwDSW Table 5. Clock Dependent Formulas Equation 0.40 TpC + 0.32 0.59 TpC – 3.25 2.83 TpC + 6.14 0.66 TpC – 1.65 2.33 TpC – 10.56 1.27 TpC + 1.67 Number 8 10 11 12 13 14 15 16 17 18 PRELIMINARY PS003501-0301 Symbol TdDSR(DR) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS) Equation 1.97 TpC – 42.5 0.8 TpC 0.59 TpC – 3.14 0.4 TpC 0.8 TpC – 15 0.4 TpC 0.88 TpC – 19 4 TpC – 20 0.91 TpC – 10.7 0.9 TpC – 26.3 13 Z86C61/62/96 CMOS Z8 Microcontroller Zilog AC CHARACTERISTICS External I/O or Memory Read and Write Timing Z86C61/62/96 (20 MHz) TA = 0°C to +70°C TA = -40°C to +105°C 20 MHz No Sym 1 TdA(AS) 2 TdAS(A) 3 TdAS(DR) 4 5 6 7 8 TwAS TdAZ(DS) TwDSR TwDSW TdDSR(DR) 9 ThDR(DS) 10 TdDS(A) 11 12 TdDS(AS) TdR/W(AS) 13 14 TdDS(R/W) TdDW(DSW) 15 TdDS(DW) 16 TdA(DR) 17 18 TdAS(DS) TdDM(AS) Parameter Min Address Valid to /AS rise Delay /AS rise to Address Float Delay /AS rise to Read Data Req’d Valid /AS Low Width Address Float to /DS fall /DS (Read) Low Width /DS (Write) Low Width /DS fall to Read Data Req’d Valid Read Data to /DS rise Hold Time /DS rise to Address Active Delay /DS rise to /AS fall Delay R//W Valid to /AS rise Delay /DS rise to R//W Not Valid Write Data Valid to /DS fall (Write) Delay /DS rise to Write Data Not Valid Delay Address Valid to Read Data Req’d Valid /AS rise to /DS fall Delay /DM Valid to /AS rise Delay 15 25 Max 20 MHz Min Units Notes 25 ns 2,3 35 ns 2,3 120 ns 1,2,3 2,3 105 1,2,3 1,2,3 1,2,3 120 30 0 Max 30 0 65 55 65 55 ns ns ns ns ns 0 0 ns 2,3 40 40 ns 2,3 25 20 25 20 ns ns 2,3 2,3 25 20 25 20 ns ns 2,3 2,3 25 25 ns 2,3 ns 1,2,3 ns ns 2,3 2,3 105 150 35 15 150 35 15 Notes: 1. When using extended memory timing add 2 TpC. 2. Timing numbers given are for minimum TpC. 3. See clock cycle dependent characteristics table. 14 PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog AC CHARACTERISTICS Additional Timing Diagram 1 3 1 Clock 2 2 3 7 7 TIN 4 5 6 IRQN 8 9 Figure 10. Additional Timing DS97Z8X1600 PRELIMINARY PS003501-0301 15 Z86C61/62/96 CMOS Z8 Microcontroller Zilog AC CHARACTERISTICS Additional Timing Table Z86C61/62/96 No 1 2 3 4 5 6 7 8a 8b 9 Symbol TpC TrC,TfC Parameter Input Clock Period Clock Input Rise & Fall Times TwC Input Clock Width TwTinL Timer Input Low Width TwTinH Timer Input High Width TpTin Timer Input Period TrTin,TfTin Timer Input Rise and Fall Times TwIL Interrupt Request Input Low Times TwIL Interrupt Request Input Low Times TwIH Interrupt Request Input High Times TA = 0°C to +70°C TA = -40°C to +105°C 20/16 MHz 20/16 MHz Min Max Min Max Units Notes 50/62.5 1000 10 50/62.5 10 1000 ns ns 1 1 25 75 5 TpC 8 TpC 100 25 75 5 TpC 8 TpC 100 ns ns ns ns ns 1 2 2 2 2 70 50 ns 2,4 5 TpC 5 TpC ns 2,5 5 TpC 5 TpC ns 2,3 Notes: 1. Clock timing references use 0.8VCC for a logic 1 and 0.8V for a logic 0. 2. Timing references use 2.0V for a logic 1 and 0.8V for a logic 0. 3. Interrupt references request through Port 3. 4. Interrupt request through Port 3 (P33-P31). 5. Interrupt request through Port 30. 16 PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog AC CHARACTERISTICS Handshake Timing Diagrams 1 Data In Data In Valid 1 Next Data In Valid 2 3 /DAV (Input) Delayed DAV 4 5 RDY (Output) 6 Delayed RDY Figure 11. Input Handshake Timing Data Out Data Out Valid Next Data Out Valid 7 /DAV (Output) Delayed DAV 8 9 11 10 RDY (Input) Delayed RDY Figure 12. Output Handshake Timing DS97Z8X1600 PRELIMINARY PS003501-0301 17 Z86C61/62/96 CMOS Z8 Microcontroller Zilog AC CHARACTERISTICS Handshake Timing Table Z86C61/62/96 No 1 2 3 4 5 6 7 8 9 10 11 18 Symbol TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY) TdDAVId(RDY) TdRDY0(DAV) TdDO(DAV) TdDAV0(RDY) TdRDY0(DAV) TwRDY TdRDY0d(DAV) Parameter Data In Setup Time Data In Hold Time Data Available Width DAV fall to RDY fall Delay DAV rise to RDY rise Delay RDY rise to DAV fall Delay Data Out to DAV fall Delay DAV fall to RDY fall Delay RDY fall to DAV rise Delay RDY Width RDY rise to DAV fall Delay TA = 0°C to +70°C TA = –40°C to +105°C 20/16 MHz 20/16 MHZ Min 0 145 110 115 115 0 TpC 0 115 110 115 PRELIMINARY PS003501-0301 Max Min 0 145 110 115 115 0 TpC 0 115 110 115 Max Data Direction IN IN IN IN IN IN OUT OUT OUT OUT OUT DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog PIN FUNCTIONS R//RL (input, active Low). This pin when connected to GND disables the internal ROM and forces the device to function as a Z86C96 ROMless Z8. (Note: When left unconnected or pulled High to VCC the part functions as a normal Z86C61/62 ROM version.) This pin is only available on the 44-pin version of the Z86C61, and both versions of the Z86C62. /DS (output, active Low). Data Strobe is activated once for each external memory transfer. For a READ operation, data must be available prior to the trailing edge of /DS. For WRITE operations, the falling edge of /DS indicates that output data is valid. /AS (output, active Low). Address Strobe is pulsed once at the beginning of each machine cycle. Address out-put is through Port 1 for all external programs. Memory address transfers are valid at the trailing edge of /AS. Under program control, /AS can be placed in the high-impedance state along with Ports 0 and 1, Data Strobe, and Read/Write. XTAL1, XTAL2 Crystal 1, Crystal 2 (time-based input and output, respectively). These pins connect a parallel-resonant crystal, ceramic resonator, LC, or any external singlephase clock to the on-chip oscillator and buffer. R//W (output, write Low). The Read/Write signal is Low when the MCU is writing to the external program or data memory. /RESET (input, active Low). To avoid asynchronous and noisy reset problems, the Z86C61/62/96 is equipped with a reset filter of four external clocks (4TpC). If the external /RESET signal is less than 4TpC in duration, no reset occurs. On the fifth clock after the /RESET is detected, an internal RST signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external /RESET, whichever is longer. During the reset cycle, /DS is held active Low while /AS cycles at a rate of TpC/2. When /RESET is deactivated, program execution begins at location 000C (HEX). Reset time must be held Low for 50 ms, or until VCC is stable, whichever is longer. DS97Z8X1600 /P0DS Port 0 Data Strobe (output, active Low). Signal used to emulate Port 0 when in ROMless mode. /P1DS Port 1 Data Strobe (output, active Low). Signal used to emulate Port 1 when in ROMless mode. /DTIMERS Disable Timers (input, active Low). All timers are stopped by the Low level at this pin. This pin has an internal pull up resistor. SCLK (output). System clock pin. /SYNC Instruction SYNC Signal (output, active Low). This signal indicates the last clock of the current executing instruction. Port 0 (P07-P00). Port 0 is an 8-bit, nibble programmable, bidirectional, TTL compatible port. These eight I/O lines can be configured under software control as a nibble I/O port, or as an address port for interfacing external memory. When used as an I/O port, Port 0 may be placed under handshake control. In this configuration, Port 3, lines P32 and P35 are used as the handshake control /DAV0 and RDY0 (Data Available and Ready). Handshake signal assignment is dictated by the I/O direction of the upper nibble P07-P04. The lower nibble must have the same direction as the upper nibble to be under handshake control. For external memory references, Port 0 can provide address bits A11-A8 (lower nibble) or A15-A8 (lower and upper nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 Mode register. In ROMless mode, after a hardware reset, Port 0 lines are defined as address lines A15-A8, and extended timing is set to accommodate slow memory access. The initialization routine includes reconfiguration to eliminate this extended timing mode (Figure 14). PRELIMINARY PS003501-0301 19 1 Z86C61/62/96 CMOS Z8 Microcontroller Zilog PIN FUNCTIONS (Continued) 4 Port 0 (I/O) 4 MCU Handshake Controls /DAV0 and RDY0 (P32 and P35) OEN PAD Out TTL Level Shifter In Auto Latch R ≈ 500 KΩ Figure 13. Port 0 Configuration 20 PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog Port 1 (P17-P10). Port 1 is an 8-bit, byte programmable, bidirectional, TTL compatible port. It has multiplexed Address (A7-A0) and Data (D7-D0) ports. For Z86C61/62/96, these eight I/O lines can be programmed as Input or Output lines or can be configured under software control as an address/data port for interfacing external memory. When used as an I/O port, Port 1 may be placed under handshake control. In this configuration, Port 3 line P33 and P34 are used as the handshake controls RDY1 and /DAV1. 8 Memory locations greater than 16,384 are referenced through Port 1. To interface external memory, Port 1 must be programmed for the multiplexed Address/Data mode. If more than 256 external locations are required, Port 0 must output the additional lines. Port 1 can be placed in high-impedance state along with Port 0, /AS, /DS, and R//W, allowing the microcontroller to share common resources in multiprocessor and DMA applications. Data transfers can be controlled by assigning P33 as a Bus Acknowledge input, and P34 as a Bus request output (Figure 14). Port 1 (AD7-AD0) MCU Handshake Controls /DAV1 and RDY1 (P33 and P34) OEN PAD Out TTL Level Shifter In Auto Latch R ≈ 500 KΩ Figure 14. Port 1 Configuration DS97Z8X1600 PRELIMINARY PS003501-0301 21 1 Z86C61/62/96 CMOS Z8 Microcontroller Zilog PIN FUNCTIONS (Continued) Port 2 (P27-P20). Port 2 is an 8-bit, bit programmable, bidirectional, CMOS-compatible port. Each of these eight I/O lines can be independently programmed as an input or output or globally as an open-drain output. Port 2 is always available for I/O operation. When used as an I/O port, Port 2 may be placed under handshake control. In this configuration, Port 3 lines P31 and P36 are used as the handshake control lines /DAV2 and RDY2. The handshake signal assignment for Port 3 lines P31 and P36 is dictated by the direction (input or output) assigned to P27 (Figure 15). Port 2 (I/O) MCU Handshake Controls /DAV2 and RDY2 (P31 and P36) Open-Drain OEN PAD Out TTL Level Shifter In Auto Latch R ≈ 500 KΩ Figure 15. Port 2 Configuration 22 PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog Port 3 (P37-P30). Port 3 is an 8-bit, CMOS-compatible four-fixed input and four-fixed output port. These eight I/O lines have four-fixed (P33-P30) input and four-fixed (P37- P34) output ports. Port 3, when used as serial I/O, are programmed as serial in and serial out, respectively (Figure 16). MCU Port 3 (I/O or Control) PAD Out Port 3 Output Configuration PAD In Auto Latch R ≈ 500 KΩ Port 3 Input Configuration Figure 16. Port 3 Configuration DS97Z8X1600 PRELIMINARY PS003501-0301 23 1 Z86C61/62/96 CMOS Z8 Microcontroller Zilog PIN FUNCTIONS (Continued) Port 3 can be configured under software control to provide the following control functions: handshake for Ports 0 and 2 (/DAV and RDY); four external interrupt request signals (IRQ3-IRQ0); timer input and output signals (TIN and TOUT), and Data Memory Select (/DM). Table 6. Port 3 Pin Assignments Pin I/O CTC1 Int. P30 P31 IN IN TIN IRQ3 IRQ2 P32 P33 P34 P35 P36 IN IN OUT OUT OUT P37 T0 T1 OUT IRQ0 IRQ1 P0 HS P1 HS P2 HS UART Ext Serial In D/R D/R D/R R/D DM R/D TOUT R/D Serial Out IRQ4 IRQ5 Notes: HS = Handshake Signals D = Data Available R = Ready Uart Operation Port 3 lines P30 and P37, can be programmed as serial I/O lines for full-duplex serial asynchronous receiver/transmitter operation. The bit rate is controlled by the Counter/Timer0. The Z86C61/62/96 automatically adds a start bit and two stop bits to transmitted data (Figure 17). Odd parity is also available as an option. Eight data bits are always transmitted, regardless of parity selection. If parity is enabled, the eighth bit is the odd parity bit. An interrupt request (IRQ4) is generated on all transmitted characters. 24 Received data must have a start bit, eight data bits and at least one stop bit. If parity is on, bit 7 of the received data is replaced by a parity error flag. Received characters generate the IRQ3 interrupt request. Note: UART function is only available in standard timing mode (i.e., P01M D5 = 0). PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog Transmitted Data (No Parity) SP SP D7 D6 D5 D4 D3 D2 Received Data (No Parity) D1 D0 ST SP D7 D6 D5 D4 D3 Start Bit Start Bit Eight Data Bits Eight Data Bits Two Stop Bits One Stop Bit Transmitted Data (With Parity) SP SP P D6 D5 D4 D3 D2 1 D2 D1 D0 ST Received Data (With Parity) D1 D0 ST SP P D6 D5 D4 D3 D2 D1 D0 ST Start Bit Start Bit Seven Data Bits Seven Data Bits Odd Parity Parity Error Flag Two Stop Bits One Stop Bit Figure 17. Serial Data Formats DS97Z8X1600 PRELIMINARY PS003501-0301 25 Z86C61/62/96 CMOS Z8 Microcontroller Zilog PIN FUNCTIONS (Continued) Port 4 (P47-P40). Port 4 is an 8-bit, bit programmable, bidirectional, CMOS-compatible port. Each of these eight I/O lines can be independently programmed as an input or output or globally as an open-drain output. Port 4 is always available for I/O operation (Figure 18). Port address (F)02. Port 5 (P57-P50). Same as Port 4. Port address (F)04. Port 6 (P63-P60). Same as Port 4. (Note: this is a 4-bit port, bits D3-D0.) Port address (F)07. Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs that are not externally driven. This reduces excessive supply current flow in the input buffer when it is not being driven by any source. Port 4 (I/O) MCU Open-Drain OEN PAD Out TTL Level Shifter In Auto Latch R ≈ 500 KΩ Figure 18. Port 4 Configuration 26 PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog FUNCTIONAL DESCRIPTION Address Space Program Memory. The Z86C61/62 can address up to 48 KB of external program memory (Figure 19). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. For ROM mode, byte 13 to byte 16383 consists of on-chip ROM. At addresses 16384 and greater, the Z86C61/62 executes external program memory fetches. The Z86C96, and the Z86C61/62 in ROMless mode, can address up to 64 KB of external program memory. Program execution begins at external location 000CH after a reset. Data Memory (/DM). The ROM version can address up to 48 KB of external data memory space beginning at location 16384. The ROMless version can address up to 64 KB of external data memory. External data memory may be included with, or separated from, the external program memory space. /DM, an optional I/O function that can be programmed to appear on pin P34, is used to distinguish between data and program memory space (Figure 20). The state of the /DM signal is controlled by the type instruction being executed. An LDC opcode references PROGRAM (/DM inactive) memory, and an LDE instruction references DATA (/DM active Low) memory. 65535 External ROM and RAM 65535 16384 16383 On-Chip ROM Location of 12 First Byte of Instruction 11 Executed After RESET 10 IRQ5 9 IRQ4 8 IRQ4 7 IRQ3 6 IRQ3 5 IRQ2 4 IRQ2 3 IRQ1 2 IRQ1 1 IRQ0 0 IRQ0 Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte) External Data Memory IRQ5 16384 16383 Not Addressable 0 Figure 20. Data Memory Configuration Figure 19. Program Memory Configuration DS97Z8X1600 PRELIMINARY PS003501-0301 27 1 Z86C61/62/96 CMOS Z8 Microcontroller Zilog FUNCTIONAL DESCRIPTION (Continued) Register File. The Register File consists of four I/O port registers, 236 general-purpose registers and 16 control and status registers (Figure 18). There are eight further registers for I/O ports 4, 5 and 6 in the Expanded Register File (Bank F, R9-R2) (Figure 20). Location Identifiers R255 Stack Pointer (Bits 7-0) SPL The instructions can access registers directly or indirectly through an 8-bit address field. The Z86C61/62/96 also allows short 4-bit register addressing using the Register Pointer (Figure 21). In the 4-bit mode, the Register File is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working-register group. R254 Stack Pointer (Bits 15-8) SPH R253 Register Pointer R252 Program Control Flags FLAGS R251 Interrupt Mask Register IMR R250 Interrupt Request Register IRQ Note: Register Bank E0-EF can only be accessed through working registers and indirect addressing modes. R249 Interrupt Priority Register IPR R248 Ports 0-1 Mode P01M R247 Port 3 Mode P3M R246 Port 2 Mode P2M R245 T0 Prescaler PRE0 R244 Timer/Counter0 R243 T1 Prescaler R242 Timer/Counter1 R241 Timer Mode TMR R240 Serial I/O SIO R253 RP D7 D6 D5 D4 D3 D2 D1 D0 Expanded Register Group Working Register Group Default Setting After Reset = 00000000 Figure 21. Register Pointer Register RP T0 PRE1 T1 R239 General-Purpose Registers R4 R3 Port 3 P3 R2 Port 2 P2 R1 Port 1 P1 R0 Port 0 P0 Figure 22. Register File 28 PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog 1 Figure 23. Expanded Register File Architecture DS97Z8X1600 PRELIMINARY PS003501-0301 29 Z86C61/62/96 CMOS Z8 Microcontroller Zilog FUNCTIONAL DESCRIPTION (Continued) Expanded Register File. The register file has been expanded to allow for additional system control registers, and for mapping of additional peripheral devices along with I/O ports into the register address area. The Z8 register address space R0 through R15 has now been implemented as 16 groups of 16 registers per group. These register groups are known as the ERF (Expanded Register File). Bits 7-4 of Register RP select the working register group. Bits 3-0 of Register RP select the expanded register group (Figure 21). Eight I/O port registers reside in the Expanded Register File at Bank F. The rest of the Expanded Register is not physically implemented and is open for future expansion. The upper nibble of the register pointer (Figure 20) selects which group of 16 bytes in the register file, out of the full 236, will be accessed. The lower nibble selects the expanded register file bank and in the case of the Z86C61/62/96, only Bank F is implemented. A 0H in the lower nibble will allow the normal register file to be addressed, but any other value from 1H to FH will exchange the lower 16 registers in favor of an expanded register group of 16 registers. For example: Z86C61: (See Figures 21 and 22) R253 RP = 00H R0 = Port 0 R2 = Port 2 R1 = Port 1 R3 = Port 3 But If: R253 RP = 0FH R0 = Reserved R1 = Reserved R2 = Port 4 R3 = Port 4, Direction Register R9 = Port 6, Mode Register Further examples: SRP #0FH Set working group 0 and Bank F LD R2, #10010110 Load value into Port 4 using working register addressing. LD 2, #10010110 Load value into Port 4 using absolute addressing. LD 9, #11110000 Load value into Port 6 mode. SRP #1FH Set working group 1 and Bank F LD R2, #11010110 Load value into general purpose register 12H LD 12H, #11010110 Load value into general purpose register 12H LD 2, #10010110 Load value into Port 4 RAM Protect. The upper portion of the RAM’s address spaces 80FH to EFH (excluding the control registers) can be protected from reading and writing. The RAM Protect bit option is mask-programmable and is selected by the customer when the ROM code is submitted. After the mask option is selected, the user can activate from the internal ROM code to turn off/on the RAM Protect by loading a bit D6 in the IMR register to either a 0 or a 1, respectively. A 1 in D6 indicates RAM Protect enabled. ROM Protect. The first 16 Kbytes of program memory is mask programmable. A ROM protect feature prevents “dumping” of the ROM contents by inhibiting execution of LDC, LDCI, LDE, and LDEI instructions by external program memory when pointing to internal memory locations. Therefore these instructions can be used only when they are executed from internal memory, or if they are executed from external memory and pointing to external memory locations. The ROM Protect option is mask-programmable, to be selected by the customer at the time when the ROM code is submitted. 30 PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog r7 r6 r3 r2 r5 r4 r1 r0 R253 (Register Pointer) The upper nibble of the register file address provided by the register pointer specifies the active working-register group. FF Register Group F R15 to R0 F0 • • • • • • • • • • • • • • Specified Working Register Group 2F The lower nibble of the register file address provided by the instruction points to the specified register. 20 1F 10 0F Register Group 1 R15 to R0 Register Group 0 R15 to R4 R3 to R0 I/O Ports 00 Figure 24. Register Pointer Stack. The Z86C61/62/96 has a 16-bit Stack Pointer (R255-R254) used for external stack that resides anywhere in the data memory for the ROMless mode, but only from 16384 to 65535 in the ROM mode. An 8-bit Stack Pointer (R255) is used for the internal stack that resides within the 236 general-purpose registers (R239-R4). The high byte of the Stack Pointer (SPH-Bit 8-15) can be used as a general purpose register when using internal stack only. DS97Z8X1600 Counter/Timers. There are two 8-bit programmable counter/timers (T0-T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler can be driven by internal or external clock sources; however, the T0 prescaler is driven by the internal clock only (Figure 22). The 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When both the counters and prescaler reach the end of the count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated. The counter can be programmed to start, stop, restart to continue, or restart from the initial value. The counters can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). The counter, but not the prescalers, can be read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and can be either the internal microprocessor clock divided-by-four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. Port 3, line P36, also serves as a timer output (TOUT) through which T0, T1 or the internal clock can be output. The counter/timers can be cascaded by connecting the T0 output to the input of T1. PRELIMINARY PS003501-0301 31 1 Z86C61/62/96 CMOS Z8 Microcontroller Zilog FUNCTIONAL DESCRIPTION (Continued) Internal Data Bus Write OSC Write Read PRE0 Initial Value Register T0 Initial Value Register 6-Bit Down Counter 8-bit Down Counter T0 Current Value Register ÷2 ÷4 Internal Clock IRQ4 Serial I/O Clock ÷2 External Clock Tout P36 Clock Logic ÷4 Internal Clock Gated Clock Triggered Clock TIN P31 Write 6-Bit Down Counter 8-Bit Down Counter PRE1 Initial Value Register T1 Initial Value Register Write IRQ5 T1 Current Value Register Read Internal Data Bus Figure 25. Counter/Timer Block Diagram 32 PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog Interrupts. The Z86C61/62/96 has six different interrupts from eight different sources. The interrupts are maskable and prioritized. The eight sources are divided as follows: four sources are claimed by Port 3 lines P33-P30, one in Serial Out, one is Serial In, and two in the counter/timers (Figure 26). The Interrupt Mask Register globally or individually enables or disables the six interrupt requests. When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. All Z86C61/62/96 interrupts are vectored through locations in the program memory. When an interrupt machine cycle is activated, an interrupt request is granted. Thus, this disables all of the subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the Interrupt Request register is polled to determine which of the interrupt requests need service. Software initialed interrupts are supported by setting the appropriate bit in the Interrupt Request Register (IRQ). Internal interrupt requests are sampled on the falling edge of the last cycle of every instruction. The interrupt request must be valid 5TpC before the falling edge of the last clock cycle of the currently executing instruction. For the ROMless mode, when the device samples a valid interrupt request, the next 48 (external) clock cycles are used to prioritize the interrupt, and push the two PC bytes and the FLAG register onto the stack. The following nine cycles are used to fetch the interrupt vector from external memory. The first byte of the interrupt service routine is fetched beginning on the 58th TpC cycle following the internal sample point, which corresponds to the 63rd TpC cycle following the external interrupt sample point. IRQ0 - IRQ5 IRQ IMR 6 Global Interrupt Enable Interrupt Request IPR PRIORITY LOGIC Vector Select Figure 26. Interrupt Block Diagram DS97Z8X1600 PRELIMINARY PS003501-0301 33 1 Z86C61/62/96 CMOS Z8 Microcontroller Zilog FUNCTIONAL DESCRIPTION (Continued) Clock. The Z86C61/62/96 on-chip oscillator has a highgain, parallel-resonant amplifier for connection to a crystal, LC, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal should be AT cut, 1 MHz to 20 MHz max, and series resistance (RS) is less than or equal to 100 Ohms. The crystal should be connected across XTAL1 and XTAL2 using the recommended capacitors (10 pF < CL < 100 pF) from each pin to device ground (Figure 27). Note: Actual capacitor values specified by the crystal manufacturer. XTAL1 C1 XTAL1 XTAL1 XTAL2 XTAL2 C1 L XTAL2 C2 Ceramic Resonator or Crystal C2 External Clock LC Clock Figure 27. Oscillator Configuration HALT. Turns off the internal CPU clock but not the XTAL oscillation. The counter/timers and the external interrupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT. 34 STOP. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 5 µA (typical) or less. The STOP mode is terminated by a reset, which causes the processor to restart the application program at address 000CH. In order to enter STOP (or HALT) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute a NOP (opcode=0FFH) immediately before the appropriate sleep instruction, i.e., FF 6F NOP STOP FF 7F NOP HALT PRELIMINARY PS003501-0301 ; clear the pipeline ; enter STOP mode or ; clear the pipeline ; enter HALT mode DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog Z8 CONTROL REGISTER DIAGRAMS 1 R243 PRE1 R240 SIO D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Count Mode 0 T1 Single Pass 1 T1 Modulo N Serial Data (D0 = LSB) Clock Source 1 T1 Internal 0 T1 External Timing Input (TIN) Mode Figure 28. Serial I/O Register (F0H: Read/Write) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) R241 TMR Figure 31. Prescaler 1 Register (F3H: Write Only) D7 D6 D5 D4 D3 D2 D1 D0 0 1 No Function Load T0 0 1 Disable T0 Count Enable T0 Count 0 1 No Function Load T1 0 1 Disable T1 Count Enable T1 Count R244 T0 D7 D6 D5 D4 D3 D2 D1 D0 T0 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T0 Current Value (When Read) TIN Modes 00 External Clock Input 01 Gate Input 10 Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) Figure 32. Counter/Timer 0 Register (F4H: Read/Write) TOUT Modes 00 Not Used 01 T0 Out 10 T1 Out 11 Internal Clock Out R245 PRE0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 29. Timer Mode Register (F1H: Read/Write) Count Mode 0 T0 Single Pass 1 T0 Modulo N Reserved (Must be 0) R242 T1 Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) D7 D6 D5 D4 D3 D2 D1 D0 T1 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T1 Current Value (When Read) Figure 33. Prescaler 0 Register (F5H: Write Only) Figure 30. Counter/Timer1 Register (F2H: Read/Write) DS97Z8X1600 PRELIMINARY PS003501-0301 35 Z86C61/62/96 CMOS Z8 Microcontroller Zilog Z8 CONTROL REGISTER DIAGRAMS (Continued) R248 P01M R246 P2M D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 P00 - P00 Mode 00 Output 01 Input 1X A11 - A8 P20 - P27 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input Stack Selection 0 External 1 Internal Figure 34. Port 2 Mode Register (F6H: Write Only) P17 - P10 Mode 00 Byte Output 01 Byte Input 10 AD7 - AD0 11 High-Impedance AD7 - DA0, /AS, /DS, /R//W, A11 - A8, A15 - A12, If Selected R247 P3M D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) P0 7 - P04 Mode 00 Output 01 Input 1X A 15 - A12 0 Port 2 Open Drain 1 Port 2 Push-pull Reserved (Must be 0) 0 P32 = Input P35 = Output 1 P32 = /DAV0/RDY0 P35 = RDY0//DAV0 00 01 10 11 P33 = Input P34 = Output P33 = Input P34 = /DM P33 = /DAV1/RDY1 P34 = RDY1//DAV1 0 P31 = Input (TIN) P36 = Output (TOUT) 1 P31 = /DAV2/RDY2 P36 = RDY2//DAV2 0 1 Figure 36. Port 0 and 1 Mode Register (F8H: Write Only) R249 IPR D7 D6 D5 D4 D3 D2 D1 D0 Interrupt Group Priority Reserved = 000 C > A > B = 001 A > B > C = 010 A > C > B = 011 B > C > A = 100 C > B > A = 101 B > A > C = 110 Reserved = 111 P30 = Input P37 = Output P30 = Serial In P37 = Serial Out 0 Parity Off 1 Parity On IRQ1, IRQ4 Priority (Group C) 0 IRQ1 > IRQ4 1 IRQ4 > IRQ1 Figure 35. Port 3 Mode Register (F7H: Write Only) IRQ0, IRQ2 Priority (Group B) 0 IRQ2 > IRQ0 1 IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 IRQ5 > IRQ3 1 IRQ3 > IRQ5 Reserved (Must be 0) Figure 37. Interrupt Priority Register (F9H: Write Only) 36 PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog R253 RP R250 IRQ 1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 IRQ0 = P32 IRQ1 = P33 IRQ2 = P31 IRQ3 = P30 IRQ4 = T0 IRQ5 = T1 Expanded Register Pointer Input (D0 = IRQ0) Input Input Input, Serial Input Serial Output Working Register Pointer Reserved (Must be 0) Figure 41. Register Pointer Register (FDH: Read/Write) Figure 38. Interrupt Request Register (FAH: Read/Write) R254 SPH D7 D6 D5 D4 D3 D2 D1 D0 R251 IMR Stack Pointer Upper Byte (SP15 - SP8) D7 D6 D5 D4 D3 D2 D1 D0 1 Enables IRQ5-IRQ0 (D0 = IRQ0) 1 Enables RAM Protect 1 Enables Interrupts Figure 39. Interrupt Mask Register (FBH: Read/Write) Figure 42. Stack Pointer Register (FEH: Read/Write) R255 SPL D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer Lower Byte (SP7 - SP0) R252 FLAGS D7 D6 D5 D4 D3 D2 D1 D0 User Flag F1 Figure 43. Stack Pointer Register (FFH: Read/Write) User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag Figure 40. Flag Register (FCH: Read/Write) DS97Z8X1600 PRELIMINARY PS003501-0301 37 Z86C61/62/96 CMOS Z8 Microcontroller Zilog Z8 EXPANDED REGISTER FILE CONTROL REGISTERS P4 (FH) 02H D7 D6 P45M (FH) 06H D5 D4 D3 D2 D1 D0 D4 D0 0 Port 4 Open-drain* 1 Port 4 Push-pull Data 0 Defines Level 0 1 Defines Level 1 Reserved (Must be 0) 0 Port 5 Open-drain* 1 Port 5 Push-pull Figure 44. Port 4 Data Register (F) 02: Read/Write) Reserved (Must be 0) *Default Value After RESET P4M (FH) 03H Figure 48. Port 4/5 Configuration Register (F) 06: (Write Only) D7 D6 D5 D4 D3 D2 D1 D0 P40 - P47 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input P6 (FH) 07H D7 D6 D5 D4 D3 D2 D1 D0 Figure 45. Port 4 Mode Register (F( 03: (Write Only) Data 0 Defines Level 0 1 Defines Level 1 Reserved (Must be 0) P5 (FH) 04H D7 D6 D5 D4 D3 D2 D1 D0 Figure 49. Port 6 Data Register (F) 07: (Read/Write) Data 0 Defines Level 0 1 Defines Level 1 P6D (FH) 08H Figure 46. Port 5 Data Register (f) 04: (Read/Write) D3 D2 D1 D0 P60 - P63 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input* P5D (FH) 05H Reserved (Must be 0) D7 D6 D5 D4 D3 D2 D1 D0 *Default Value After RESET *Default Value After RESET P50 - P57 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input* Figure 47. Port 5 Mode Register (F) 05: (Write Only) Figure 50. Port 6 Mode Register (F) 08: (Write Only) P6M (FH) 09H D7 D6 D5 D4 D3 D2 D1 D0 0 1 Port 6 Open-drain* Port 6 Push-pull *Default Value After RESET Figure 51. Port 6 Mode Register (F) 09: (Write Only) 38 PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog PACKAGE INFORMATION 1 Figure 52. 40-Pin DIP Package Diagram Figure 53. 44-Pin PLCC Package Diagram DS97Z8X1600 PRELIMINARY PS003501-0301 39 Z86C61/62/96 CMOS Z8 Microcontroller Zilog PACKAGE INFORMATION (Continued) Figure 54. 64-Pin DIP Package Diagram 40 PRELIMINARY PS003501-0301 DS97Z8X1600 Z86C61/62/96 CMOS Z8 Microcontroller Zilog 1 Figure 55. 68-Pin PLCC Package Diagram DS97Z8X1600 PRELIMINARY PS003501-0301 41 Z86C61/62/96 CMOS Z8 Microcontroller Zilog ORDERING INFORMATION Z86C61/62/96 Codes 16 MHz Package P = Plastic DIP V = Plastic Chip Carrier 40-pin DIP Z86C6116PSC 44-pin PLCC Z86C6116VSC Preferred Temperature S = 0°C to +70°C 16 MHz 64-pin DIP Z86C6216PSC Longer Lead Time E = -40°C to 105°C 68-pin PLCC Z86C6216VSC Speeds 16 = 16 MHz 20 = 20 MHz 20 MHz 64-pin DIP Z86C9620PSC 68-pin PLCC Z86C9620VSC For fast results, contact your Zilog sales office for assistance in ordering the part desired. Example: Z 86C61 16 P S C Environmental C = Plastic Standard is a Z86C61, 16 MHz, DIP, 0° to +70°C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY, IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com 42 PRELIMINARY PS003501-0301 DS97Z8X1600