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Z8F0431SJ020SG

Z8F0431SJ020SG

  • 厂商:

    ZILOG(齐洛格)

  • 封装:

    SOIC28

  • 描述:

    IC MCU 8BIT 4KB FLASH 28SOIC

  • 数据手册
  • 价格&库存
Z8F0431SJ020SG 数据手册
High-Performance 8-Bit Microcontrollers Z8 Encore!® F0830 Series Product Specification PS025114-1314 Copyright ©2014 Zilog®, Inc. All rights reserved. www.zilog.com Z8 Encore!® F0830 Series Product Specification ii Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2014 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES or TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES or TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore! and Z8 Encore! XP are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS025114-1314 Disclaimer Z8 Encore!® F0830 Series Product Specification iii Revision History Each instance in this document’s revision history reflects a change from its previous edition. For more details, refer to the corresponding page(s) or appropriate links furnished in the table below. Date Revision Level Chapter/Section Page No. Description May 2014 14 Electrical Characteristics Corrected minimum ambient temperature under bias value from 0°C to –40°C, Table 115. 184 Dec 2012 13 GPIO Modified GPIO Port D0 language in Shared Reset Pin section and Port Alternate Function Mapping table. 35, 36 Sep 2011 12 LED Drive Enable Register Clarified statement surrounding the Alternate 51, Function Register as it relates to the LED 115, function; revised Sector Based Flash Protec- 199 tion description; revised Packaging chapter. Dec 2007 11 n/a Updated all instances of Z8 Encore! XP F0830 to Z8 Encore! F0830. All Nov 2007 10 DC Characteristics, On-Chip Peripheral AC and DC Electrical Characteristics Updated Tables 116 and and 122. 185, 193 Sep 2007 09 Timers, PWM SINGLE OUTPUT Mode, PWM DUAL OUTPUT Mode, Analog-to-Digital Converter, Reference Buffer. Updated Figures 2 and 4, Table 4. 8, 9, 11, 68, 74, 75, 98, 101 Apr 2007 08 Optimizing NVDS Memory Usage for Execution Speed, On-Chip Peripheral AC and DC Electrical Characteristics Added a note under Table 93 in Nonvolatile Data Storage chapter. Updated Table 121 and Table 122 in Electrical Characteristics chapter. Other style updates. 137, 193, 193 PS025114-1314 Revision History Z8 Encore!® F0830 Series Product Specification iv Date Dec 2006 Revision Level Chapter/Section Description Page No. 07 General Purpose Input/Output Added PD0 in Table 16. 38 Overview, Interrupt Controller Changed the number of interrupts to 17. 1,5, 53 Nonvolatile Data Storage Updated chapter. 136 PS025114-1314 Oscillator Control Register Defi- Updated Tables 117 and 122. Added nitions, AC Characteristics, On- Figure 24. Chip Peripheral AC and DC Electrical Characteristics 156, 189, 193 Ordering Information Updated Part Number Suffix Designations. 205 n/a Removed Preliminary stamp from footer. All Revision History Z8 Encore!® F0830 Series Product Specification iv Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nonvolatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acronyms and Expansions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 2 3 4 4 4 5 5 5 5 5 5 5 6 6 6 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 15 16 16 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reset and Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS025114-1314 21 21 23 23 Table of Contents Z8 Encore!® F0830 Series Product Specification v Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode Recovery using WDT Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode Recovery using GPIO Port Pin Transition . . . . . . . . . . . . . . . . . . . . . . . Stop Mode Recovery Using the External RESET Pin . . . . . . . . . . . . . . . . . . . . . . . Debug Pin Driven Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 25 25 26 26 26 27 27 28 28 28 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Level Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 31 31 31 General Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Port Availability by Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct LED Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shared Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Clock Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A–D Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A–D Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A–D Data Direction Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A–D Alternate Function Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A–C Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A–D Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Drive Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Drive Level High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Drive Level Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 33 34 34 35 35 35 35 36 39 39 40 41 41 42 49 50 51 51 52 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 53 55 55 PS025114-1314 Table of Contents Z8 Encore!® F0830 Series Product Specification vi Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Edge Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shared Interrupt Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 56 56 57 57 58 59 60 60 62 63 65 66 67 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Pin Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 0–1 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 0–1 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 0–1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 68 69 69 82 82 83 83 85 86 87 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer Reload Upper, High and Low Byte Registers . . . . . . . . . . . . . . . 92 92 93 93 94 95 95 96 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ADC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Reference Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Internal Voltage Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 PS025114-1314 Table of Contents Z8 Encore!® F0830 Series Product Specification vii Calibration and Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample Settling Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 101 102 103 103 104 105 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Comparator Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Memory Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Operation Timing Using the Flash Frequency Registers . . . . . . . . . . . . . . . Flash Code Protection Against External Access . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Code Protection Against Accidental Program and Erasure . . . . . . . . . . . . . Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Controller Behavior in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVDS Operational Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 111 111 112 114 114 114 116 117 117 117 117 118 118 119 120 121 122 123 Flash Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Option Bit Configuration by Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Option Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Option Bit Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trim Bit Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trim Bit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trim Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 124 124 125 126 126 126 127 129 Nonvolatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 PS025114-1314 Table of Contents Z8 Encore!® F0830 Series Product Specification viii Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVDS Code Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Failure Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optimizing NVDS Memory Usage for Execution Speed . . . . . . . . . . . . . . . . . . . . 134 134 135 136 137 137 On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DEBUG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Autobaud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Runtime Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 139 140 140 141 142 142 143 143 144 144 148 148 150 Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Failure Detection and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 151 151 153 154 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Operation with an External RC Network . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 157 157 159 Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 eZ8 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ8 CPU Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 162 163 164 166 171 Op Code Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 PS025114-1314 Table of Contents Z8 Encore!® F0830 Series Product Specification ix Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . General Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . . . . . . . . General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 184 185 189 190 195 196 197 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Part Number Suffix Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Appendix A. Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparator 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trim Bit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 208 208 213 216 216 217 218 218 222 226 228 228 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 PS025114-1314 Table of Contents Z8 Encore!® F0830 Series Product Specification x List of Figures Figure 1. Z8 Encore! F0830 Series Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Z8F0830 Series in 20-Pin SOIC, SSOP, PDIP Package . . . . . . . . . . . . . . . . 8 Figure 3. Z8F0830 Series in 28-Pin SOIC, SSOP, PDIP Package . . . . . . . . . . . . . . . . 8 Figure 4. Z8F0830 Series in 20-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. Z8F0830 Series in 28-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6. Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 7. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 8. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 9. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 10. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 11. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 12. ADC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 13. ADC Convert Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 14. 1K Flash with NVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 15. 2K Flash with NVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 16. 4K Flash with NVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 17. 8K Flash with NVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 18. 12K Flash without NVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 19. Flash Controller Operation Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 20. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Figure 21. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface,  #1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Figure 22. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface,  #2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 23. OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Figure 24. Oscillator Control Clock Switching Flow Chart . . . . . . . . . . . . . . . . . . . . 156 Figure 25. Recommended 20 MHz Crystal Oscillator Configuration . . . . . . . . . . . . . 158 Figure 26. Connecting the On-Chip Oscillator to an External RC Network . . . . . . . . 159 PS025114-1314 List of Figures Z8 Encore!® F0830 Series Product Specification xi Figure 27. Typical RC Oscillator Frequency as a Function of External Capacitance with a 45 kΩ Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Figure 28. Op Code Map Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Figure 29. First Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Figure 30. Second Op Code Map After 1Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Figure 31. ICC Versus System Clock Frequency (HALT Mode) . . . . . . . . . . . . . . . . 187 Figure 32. ICC Versus System Clock Frequency (Normal Mode) . . . . . . . . . . . . . . . 188 Figure 33. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Figure 34. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Figure 35. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Figure 36. Flash Current Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 PS025114-1314 List of Figures Z8 Encore!® F0830 Series Product Specification xii List of Tables Table 1. Z8 Encore! F0830 Series Family Part Selection Guide . . . . . . . . . . . . . . . . . 2 Table 2. Acronyms and Expansions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Z8 Encore! F0830 Series Package Options . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Pin Characteristics (20- and 28-pin Devices) . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6. Z8 Encore! F0830 Series Program Memory Maps . . . . . . . . . . . . . . . . . . . 15 Table 7. Z8 Encore! F0830 Series Flash Memory Information Area Map . . . . . . . . 16 Table 8. Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9. Reset and Stop Mode Recovery Characteristics and Latency . . . . . . . . . . . 22 Table 10. Reset Sources and Resulting Reset Type . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 11. Stop Mode Recovery Sources and Resulting Action . . . . . . . . . . . . . . . . . . 27 Table 12. POR Indicator Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 13. Reset Status Register (RSTSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 14. Power Control Register 0 (PWRCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 15. Port Availability by Device and Package Type . . . . . . . . . . . . . . . . . . . . . . 33 Table 16. Port Alternate Function Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 17. GPIO Port Registers and Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 18. Port A–D GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . . 40 Table 19. Port Control Subregister Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 20. Port A–D Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 21. Port A–D Data Direction Subregisters (PxDD) . . . . . . . . . . . . . . . . . . . . . . 41 Table 22. Port A–D Alternate Function Subregisters (PxAF) . . . . . . . . . . . . . . . . . . . 42 Table 23. Port A–D Output Control Subregisters (PxOC) . . . . . . . . . . . . . . . . . . . . . 43 Table 24. Port A–D High Drive Enable Subregisters (PxHDE) . . . . . . . . . . . . . . . . . 44 Table 25. Port A–D Stop Mode Recovery Source Enable Subregisters (PxSMRE) . . 45 Table 26. Port A–D Pull-Up Enable Subregisters (PxPUE) . . . . . . . . . . . . . . . . . . . . 46 Table 27. Port A–D Alternate Function Set 1 Subregisters (PxAFS1) . . . . . . . . . . . . 47 Table 28. Port A–D Alternate Function Set 2 Subregisters (PxAFS2) . . . . . . . . . . . . 48 PS025114-1314 List of Tables Z8 Encore!® F0830 Series Product Specification xiii Table 29. Port A–C Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 30. Port A–D Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 31. LED Drive Enable (LEDEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 32. LED Drive Level High Register (LEDLVLH) . . . . . . . . . . . . . . . . . . . . . . 51 Table 33. LED Drive Level Low Register (LEDLVLL) . . . . . . . . . . . . . . . . . . . . . . . 52 Table 34. Trap and Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . . . . . . . 54 Table 35. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 36. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 37. Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 38. IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 39. IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 40. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . . 61 Table 41. IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 42. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . . 62 Table 43. IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 44. IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 45. IRQ2 Enable Low Bit Register (IRQ2ENL) . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 46. IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . . . . 64 Table 47. Interrupt Edge Select Register (IRQES) . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 48. Shared Interrupt Select Register (IRQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 49. Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 50. Timer 0–1 High Byte Register (TxH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 51. Timer 0–1 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 52. Timer 0–1 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . . . . . 85 Table 53. Timer 0–1 Reload Low Byte Register (TxRL) . . . . . . . . . . . . . . . . . . . . . . 85 Table 54. Timer 0–1 PWM High Byte Register (TxPWMH) . . . . . . . . . . . . . . . . . . . 86 Table 55. Timer 0–1 PWM Low Byte Register (TxPWML) . . . . . . . . . . . . . . . . . . . . 86 Table 56. Timer 0–1 Control Register 0 (TxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 57. Timer 0–1 Control Register 1 (TxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 58. Watchdog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . . . . . . 92 PS025114-1314 List of Tables Z8 Encore!® F0830 Series Product Specification xiv Table 59. Watchdog Timer Control Register (WDTCTL) . . . . . . . . . . . . . . . . . . . . . 95 Table 60. Watchdog Timer Reload Upper Byte Register (WDTU) . . . . . . . . . . . . . . 96 Table 61. Watchdog Timer Reload High Byte Register (WDTH) . . . . . . . . . . . . . . . 96 Table 62. Watchdog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . . . . . 97 Table 63. ADC Control Register 0 (ADCCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 64. ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 65. ADC Data Low Bits Register (ADCD_L) . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 66. Sample Settling Time (ADCSST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 67. Sample Time (ADCST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 68. Comparator Control Register (CMP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 69. Z8 Encore! F0830 Series Flash Memory Configuration . . . . . . . . . . . . . . 108 Table 70. Z8F083 Flash Memory Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 71. Flash Code Protection using the Flash Option Bits . . . . . . . . . . . . . . . . . . 115 Table 72. Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 73. Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 74. Flash Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 75. Flash Sector Protect Register (FPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 76. Flash Frequency High Byte Register (FFREQH) . . . . . . . . . . . . . . . . . . . 123 Table 77. Flash Frequency Low Byte Register (FFREQL) . . . . . . . . . . . . . . . . . . . . 123 Table 78. Trim Bit Address Register (TRMADR) . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 79. Trim Bit Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 80. Trim Bit Data Register (TRMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 81. Flash Option Bits at Program Memory Address 0000h . . . . . . . . . . . . . . 127 Table 82. Flash Options Bits at Program Memory Address 0001h . . . . . . . . . . . . . 128 Table 83. Trim Option Bits at 0000h (ADCREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 84. Trim Option Bits at 0001h (TADC_COMP) . . . . . . . . . . . . . . . . . . . . . . 130 Table 85. Trim Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 86. Trim Option Bits at 0002h (TIPO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 87. Trim Option Bits at 0003h (TVBO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 88. VBO Trim Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 PS025114-1314 List of Tables Z8 Encore!® F0830 Series Product Specification xv Table 89. Trim Option Bits at 0006h (TCLKFLT) . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table 90. ClkFlt Delay Control Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 91. Write Status Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 92. Read Status Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 93. NVDS Read Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Table 94. OCD Baud-Rate Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Table 95. On-Chip Debugger Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . 144 Table 96. OCD Control Register (OCDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Table 97. OCD Status Register (OCDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Table 98. Oscillator Configuration and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 99. Oscillator Control Register (OSCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 100. Recommended Crystal Oscillator Specifications . . . . . . . . . . . . . . . . . . . 158 Table 101. Assembly Language Syntax Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Table 102. Assembly Language Syntax Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Table 103. Notational Shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Table 104. Additional Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Table 105. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 106. Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Table 107. Block Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Table 108. CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table 109. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table 110. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Table 111. Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Table 112. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Table 113. eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 114. Op Code Map Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Table 115. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Table 116. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table 117. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Table 118. Power-On Reset and Voltage Brown-Out Electrical Characteristics  and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 PS025114-1314 List of Tables Z8 Encore!® F0830 Series Product Specification xvi Table 119. Flash Memory Electrical Characteristics and Timing . . . . . . . . . . . . . . . . 192 Table 120. Watchdog Timer Electrical Characteristics and Timing . . . . . . . . . . . . . . 192 Table 121. Nonvolatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Table 122. Analog-to-Digital Converter Electrical Characteristics and Timing . . . . . 193 Table 123. Comparator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Table 124. GPIO Port Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Table 125. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 126. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Table 127. Power Consumption Reference Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Table 128. Z8 Encore! XP F0830 Series Ordering Matrix . . . . . . . . . . . . . . . . . . . . . 200 Table 129. Package and Pin Count Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Table 130. Timer 0 High Byte Register (T0H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Table 131. Timer 0 Low Byte Register (T0L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Table 132. Timer 0 Reload High Byte Register (T0RH) . . . . . . . . . . . . . . . . . . . . . . . 209 Table 133. Timer 0 Reload Low Byte Register (T0RL) . . . . . . . . . . . . . . . . . . . . . . . 209 Table 134. Timer 0 PWM High Byte Register (T0PWMH) . . . . . . . . . . . . . . . . . . . . 209 Table 135. Timer 0 PWM Low Byte Register (T0PWML) . . . . . . . . . . . . . . . . . . . . . 210 Table 136. Timer 0 Control Register 0 (T0CTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Table 137. Timer 0 Control Register 1 (T0CTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Table 138. Timer 1 High Byte Register (T1H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Table 139. Timer 1 Low Byte Register (T1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Table 140. Timer 1 Reload High Byte Register (T1RH) . . . . . . . . . . . . . . . . . . . . . . . 211 Table 141. Timer 1 Reload Low Byte Register (T1RL) . . . . . . . . . . . . . . . . . . . . . . . 211 Table 142. Timer 1 PWM High Byte Register (T1PWMH) . . . . . . . . . . . . . . . . . . . . 211 Table 143. Timer 1 PWM Low Byte Register (T1PWML) . . . . . . . . . . . . . . . . . . . . . 212 Table 144. Timer 1 Control Register 0 (T1CTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 145. Timer 1 Control Register 1 (T1CTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 146. ADC Control Register 0 (ADCCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Table 147. ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . . . . . 214 Table 148. ADC Data Low Bits Register (ADCD_L) . . . . . . . . . . . . . . . . . . . . . . . . . 214 PS025114-1314 List of Tables Z8 Encore!® F0830 Series Product Specification xvii Table 149. ADC Sample Settling Time (ADCSST) . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 150. ADC Sample Time (ADCST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 151. Power Control Register 0 (PWRCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Table 152. LED Drive Enable (LEDEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Table 153. LED Drive Level High Register (LEDLVLH) . . . . . . . . . . . . . . . . . . . . . 217 Table 154. LED Drive Level Low Register (LEDLVLL) . . . . . . . . . . . . . . . . . . . . . . 217 Table 155. Oscillator Control Register (OSCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Table 156. Comparator Control Register (CMP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Table 157. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Table 158. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . 219 Table 159. IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . . 219 Table 160. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Table 161. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . 219 Table 162. IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . . 220 Table 163. Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Table 164. IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . . . 220 Table 165. IRQ2 Enable Low Bit Register (IRQ2ENL) . . . . . . . . . . . . . . . . . . . . . . . 220 Table 166. Interrupt Edge Select Register (IRQES) . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Table 167. Shared Interrupt Select Register (IRQSS) . . . . . . . . . . . . . . . . . . . . . . . . . 221 Table 168. Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Table 169. Port A GPIO Address Register (PAADDR) . . . . . . . . . . . . . . . . . . . . . . . 222 Table 170. Port A Control Registers (PACTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Table 171. Port A Input Data Registers (PAIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Table 172. Port A Output Data Register (PAOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Table 173. Port B GPIO Address Register (PBADDR) . . . . . . . . . . . . . . . . . . . . . . . 223 Table 174. Port B Control Registers (PBCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Table 175. Port B Input Data Registers (PBIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Table 176. Port B Output Data Register (PBOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Table 177. Port C GPIO Address Register (PCADDR) . . . . . . . . . . . . . . . . . . . . . . . 224 Table 178. Port C Control Registers (PCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 PS025114-1314 List of Tables Z8 Encore!® F0830 Series Product Specification xviii Table 179. Port C Input Data Registers (PCIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Table 180. Port C Output Data Register (PCOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Table 181. Port D GPIO Address Register (PDADDR) . . . . . . . . . . . . . . . . . . . . . . . 225 Table 182. Port D Control Registers (PDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Table 183. Port D Output Data Register (PDOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Table 184. Watchdog Timer Control Register (WDTCTL) . . . . . . . . . . . . . . . . . . . . 226 Table 185. Reset Status Register (RSTSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Table 186. Watchdog Timer Reload Upper Byte Register (WDTU) . . . . . . . . . . . . . 227 Table 187. Watchdog Timer Reload High Byte Register (WDTH) . . . . . . . . . . . . . . 227 Table 188. Watchdog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . . . . 227 Table 189. Trim Bit Address Register (TRMADR) . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Table 190. Trim Bit Data Register (TRMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Table 191. Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Table 192. Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Table 193. Flash Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Table 194. Flash Sector Protect Register (FPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Table 195. Flash Frequency High Byte Register (FFREQH) . . . . . . . . . . . . . . . . . . . 229 Table 196. Flash Frequency Low Byte Register (FFREQL) . . . . . . . . . . . . . . . . . . . . 230 PS025114-1314 List of Tables Z8 Encore!® F0830 Series Product Specification 1 Overview Zilog’s Z8 Encore! MCU family of products are the first in a line of Zilog microcontroller products based on the 8-bit eZ8 CPU. The Z8 Encore! F0830 Series products expand on Zilog’s extensive line of 8-bit microcontrollers. The Flash in-circuit programming capability allows for faster development time and program changes in the field. The new eZ8 CPU is upward-compatible with existing Z8 CPU instructions. The rich peripheral set of Z8 Encore! F0830 Series makes it suitable for a variety of applications including motor control, security systems, home appliances, personal electronic devices and sensors. Features The key features of Z8 Encore! F0830 Series MCU include: • • • • • • • • • • • • • • • • • • • PS025114-1314 20 MHz eZ8 CPU Up to 12 KB Flash memory with in-circuit programming capability Up to 256 B register RAM 64 B Nonvolatile Data Storage (NVDS) Up to 25 I/O pins depending upon package Internal Precision Oscillator (IPO) External crystal oscillator Two enhanced 16-bit timers with capture, compare and PWM capability Watchdog Timer (WDT) with dedicated internal RC oscillator Single-pin, On-Chip Debugger (OCD) Optional 8-channel, 10-bit Analog-to-Digital Converter (ADC) On-chip analog comparator Up to 17 interrupt sources Voltage Brown-Out (VBO) protection Power-On Reset (POR) 2.7 V to 3.6 V operating voltage Up to thirteen 5 V-tolerant input pins 20- and 28-pin packages 0°C to +70°C standard temperature range and –40°C to +105°C extended temperature operating ranges Overview Z8 Encore!® F0830 Series Product Specification 2 Part Selection Guide Table 1 lists the basic features available for each device within the Z8 Encore! F0830 Series product line. See the Ordering Information chapter on page 200 for details. Table 1. Z8 Encore! F0830 Series Family Part Selection Guide PS025114-1314 Part Number Flash (KB) RAM (B) NVDS (64B) ADC Z8F1232 12 256 No Yes Z8F1233 12 256 No No Z8F0830 8 256 Yes Yes Z8F0831 8 256 Yes No Z8F0430 4 256 Yes Yes Z8F0431 4 256 Yes No Z8F0230 2 256 Yes Yes Z8F0231 2 256 Yes No Z8F0130 1 256 Yes Yes Z8F0131 1 256 Yes No Part Selection Guide Z8 Encore!® F0830 Series Product Specification 3 Block Diagram Figure 1 displays a block diagram of the Z8 Encore! F0830 Series architecture. System Clock Oscillator Control XTAL/RC Oscillator Internal Precision Oscillator Low Power RC Oscillator On-Chip Debugger eZ8 CPU Interrupt Controller POR/VBO & Reset Controller WDT Memory Bus Register Bus Timers Comparator ADC NVDS Controller Flash Controller Flash Memory RAM Controller RAM GPIO Figure 1. Z8 Encore! F0830 Series Block Diagram PS025114-1314 Block Diagram Z8 Encore!® F0830 Series Product Specification 4 CPU and Peripheral Overview The eZ8 CPU, Zilog’s latest 8-bit CPU, meets the continuing demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8 instruction set. The eZ8 CPU features include: • Direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required program memory • Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks • • • Compatible with existing Z8 CPU code • • Pipelined instruction fetch and execution • • • • New instructions support 12-bit linear addressing of the register file Expanded internal register file allows access up to 4 KB New instructions improve execution efficiency for code developed using high-level programming languages, including C New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC, LDCI, LEA, MULT and SRL Up to 10 MIPS operation C Compiler-friendly 2 to 9 clock cycles per instruction For more information about the eZ8 CPU, refer to the eZ8 CPU Core User Manual (UM0128), which is available for download on www.zilog.com. General Purpose Input/Output The Z8 Encore! F0830 Series features up to 25 port pins (Ports A–D) for general-purpose input/output (GPIO). The number of GPIO pins available is a function of package. Each pin is individually programmable. Flash Controller The Flash Controller programs and erases the Flash memory. It also supports protection against accidental programming and erasure. PS025114-1314 CPU and Peripheral Overview Z8 Encore!® F0830 Series Product Specification 5 Nonvolatile Data Storage The Nonvolatile Data Storage (NVDS) function uses a hybrid hardware/software scheme to implement a byte-programmable data memory and is capable of storing about 100,000 write cycles. Internal Precision Oscillator The Internal Precision Oscillator (IPO) function, with an accuracy of ± 4% full voltage/ temperature range, is a trimmable clock source that requires no external components. External Crystal Oscillator The crystal oscillator circuit provides highly accurate clock frequencies using an external crystal, ceramic resonator or RC network. 10-Bit Analog-to-Digital Converter The optional Analog-to-Digital Converter (ADC) converts an analog input signal to a 10bit binary number. The ADC accepts inputs from eight different analog input pins. Analog Comparator The analog comparator compares the signal at an input pin with either an internal programmable reference voltage or with a signal at the second input pin. The comparator output is used either to drive a logic output pin or to generate an interrupt. Timers Two enhanced 16-bit reloadable timers can be used for timing/counting events or for motor control operations. These timers provide a 16-bit programmable reload counter and operate in ONE-SHOT, CONTINUOUS, GATED, CAPTURE, CAPTURE RESTART, COMPARE, CAPTURE and COMPARE, PWM SINGLE OUTPUT and PWM DUAL OUTPUT Modes. Interrupt Controller The Z8 Encore! F0830 Series products support seventeen interrupt sources with sixteen interrupt vectors: up to five internal peripheral interrupts and up to twelve GPIO interrupts. These interrupts have three levels of programmable interrupt priority. PS025114-1314 CPU and Peripheral Overview Z8 Encore!® F0830 Series Product Specification 6 Reset Controller The Z8 Encore! F0830 Series products are reset using any one of the following: the RESET pin, Power-On Reset, Watchdog Timer (WDT) time-out, Stop Mode exit or Voltage Brown-Out (VBO) warning signal. The RESET pin is bidirectional; i.e., it functions as a reset source as well as a reset indicator. On-Chip Debugger The Z8 Encore! F0830 Series products feature an integrated On-Chip Debugger (OCD). The OCD provides a rich set of debugging capabilities, such as reading and writing registers, programming Flash memory, setting breakpoints and executing code. The OCD uses one single-pin interface for communication with an external host. Acronyms and Expansions This document references a number of acronyms; each is expanded in Table 2 for the reader’s understanding. Table 2. Acronyms and Expansions PS025114-1314 Acronyms Expansions ADC Analog-to-Digital Converter NVDS Nonvolatile Data Storage WDT Watchdog Timer GPIO General-Purpose Input/Output OCD On-Chip Debugger POR Power-On Reset VBO Voltage Brown-Out IPO Internal Precision Oscillator PDIP Plastic Dual Inline Package SOIC Small Outline Integrated Circuit SSOP Small Shrink Outline Package QFN Quad Flat No Lead IRQ Interrupt request ISR Interrupt service routine MSB Most significant byte LSB Least significant byte PWM Pulse Width Modulation SAR Successive Approximation Regis- Acronyms and Expansions Z8 Encore!® F0830 Series Product Specification 7 Pin Description The Z8 Encore! F0830 Series products are available in a variety of package styles and pin configurations. This chapter describes the signals and the pin configurations for each of the package styles. For information about the physical package specifications, see the Packaging chapter on page 199. Available Packages Table 3 lists the package styles that are available for each device in the Z8 Encore! F0830 Series product line. Table 3. Z8 Encore! F0830 Series Package Options Part Number ADC 20-pin QFN 20-pin SOIC 20-pin SSOP 20-pin PDIP 28-pin QFN 28-pin SOIC 28-pin SSOP 28-pin PDIP Z8F1232 Yes X X X X X X X X Z8F1233 No X X X X X X X X Z8F0830 Yes X X X X X X X X Z8F0831 No X X X X X X X X Z8F0430 Yes X X X X X X X X Z8F0431 No X X X X X X X X Z8F0230 Yes X X X X X X X X Z8F0231 No X X X X X X X X Z8F0130 Yes X X X X X X X X Z8F0131 No X X X X X X X X Pin Configurations Figures 2 and 3 display the pin configurations of all of the packages available in the Z8 Encore! F0830 Series. See Table 4 on page 11 for a description of the signals. Analog input alternate functions (ANAx) are not available on the following devices: • • • • • PS025114-1314 Z8F0831 Z8F0431 Z8F0131 Z8F0231 Z8F1233 Pin Description Z8 Encore!® F0830 Series Product Specification 8 The analog supply pins (AVDD and AVSS) are also not available on these parts and are replaced by PB6 and PB7. At reset, by default, all pins of Port A, B and C are in Input state. The alternate functionality is also disabled, so the pins function as general purpose input ports until programmed otherwise. At power-up, the Port D0 pin defaults to the RESET Alternate function. The pin configurations listed are preliminary and subject to change based on manufacturing limitations. PB1/ANA1 PB2/ANA2 PB3/CLKIN/ANA3 VDD PA0/T0IN/T0OUT/XIN PA1/T0OUT/XOUT VSS PA2 PA3 PA4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PB0/ANA0 PC3/COUT/LED PC2/ANA6/LED PC1/ANA5/CINN/LED PC0/ANA4/CINP/LED DBG RESET/PD0 PA7/T1OUT PA6/T1IN/T1OUT PA5 Figure 2. Z8F0830 Series in 20-Pin SOIC, SSOP, PDIP Package PB2/ANA2 PB4/ANA7 PB5/VREF PB3/CLKIN/ANA3 (PB6) AVDD VDD PA0/T0IN/T0OUT/XIN PA1/T0OUT/XOUT VSS (PB7) AVSS PA2 PA3 PA4 PA5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PB1/ANA1 PB0/ANA0 PC3/COUT/LED PC2/ANA6/LED PC1/ANA5/CINN/LED PC0/ANA4/CINP/LED DBG RESET/PD0 PC7/LED PC6/LED PA7/T1OUT PC5/LED PC4/LED PA6/T1IN/T1OUT Figure 3. Z8F0830 Series in 28-Pin SOIC, SSOP, PDIP Package PS025114-1314 Pin Configurations Z8 Encore!® F0830 Series Product Specification 11 18 DGB  RESET/PD0 PB1/ANA1 12 17 13 PB0/ANA0 14 16 PC2/ANA6/LED  PC1/ANA5/CINN/LED  PC0/ANA4/CINP/LED PC3/COUT/LED 15 9 10 9 8 20-Pin QFN 3 4 5 VSS PA2 6 PA1/T0OUT/XOUT 20 2 PB3/CLKIN/ANA3 PA0/T0IN/T0OUT/XIN 7 1 19 VDD PB2/ANA2 PA7/T1OUT  PA6/T1IN/T1OUT  PA5  PA4  PA3 Figure 4. Z8F0830 Series in 20-Pin QFN Package PS025114-1314 Pin Configurations Z8 Encore!® F0830 Series Product Specification 21 20 19 PC6/LED PC7/LED RESET/PD0 DBG PC0/ANA4/CINP/LED PC1/ANA5/CINN/LED PC2/ANA6/LED 10 18 17 16 15 PC3/COUT/LED 22 14 PA7/T1OUT PB0/ANA0 23 13 PC5/LED 24 12 PB1/ANA1 PB2/ANA2 PA3 1 2 3 4 5 6 7 PA2 9 (PB7) AVSS 27 VSS PA4 PA1/T0OUT/XOUT 10 PA0/T0IN/T0OUT/XIN PB3/CLKIN/ANA3 PA5 26 VDD PB5/VREF 11 (PB6) AVDD PB4/ANA7 PA6/T1IN/T1OUT 28-Pin QFN 25 PC4/LED Figure 5. Z8F0830 Series in 28-Pin QFN Package PS025114-1314 Pin Configurations Z8 Encore!® F0830 Series Product Specification 11 Signal Descriptions Table 4 describes the Z8 Encore! F0830 Series signals. See the Pin Configurations section on page 7 to determine the signals available for each specific package style. Table 4. Signal Descriptions Signal Mnemonic I/O Description General-Purpose I/O Ports A–D PA[7:0] I/O Port A. These pins are used for general purpose I/O. PB[7:0] I/O Port B. These pins are used for general purpose I/O. PB6 and PB7 are available only in those devices without an ADC. PC[7:0] I/O Port C. These pins are used for general purpose I/O. PD[0] I/O Port D. This pin is used for general purpose output only. Note: PB6 and PB7 are only available in 28-pin packages without ADC. In 28-pin packages with ADC, they are replaced by AVDD and AVSS. Timers T0OUT/T1OUT O Timer output 0–1. These signals are the output from the timers. T0OUT/T1OUT O Timer complement output 0–1. These signals are output from the timers in PWM DUAL OUTPUT Mode. T0IN/T1IN I Timer Input 0–1. These signals are used as the capture, gating and counter inputs. The T0IN signal is multiplexed T0OUT signals. CINP/CINN I Comparator inputs. These signals are the positive and negative inputs to the comparator. COUT O Comparator output. This is the output of the comparator. I Analog port. These signals are used as inputs to the analog-to-digital converter (ADC). Comparator Analog ANA[7:0] VREF I/O Analog-to-digital converter reference voltage input. Note: When configuring ADC using external VREF, PB5 is used as VREF in 28-pin package. Note: The AVDD and AVSS signals are available only in the 28-pin packages with ADC. They are replaced by PB6 and PB7 on 28-pin packages without ADC. PS025114-1314 Signal Descriptions Z8 Encore!® F0830 Series Product Specification 12 Table 4. Signal Descriptions (Continued) Signal Mnemonic I/O Description Oscillators XIN I External crystal input. This is the input pin to the crystal oscillator. A crystal can be connected between it and the XOUT pin to form the oscillator. In addition, this pin is used with external RC networks or external clock drivers to provide the system clock. XOUT O External crystal output. This pin is the output of the crystal oscillator. A crystal can be connected between it and the XIN pin to form the oscillator. I Clock input signal. This pin may be used to input a TTL-level signal to be used as the system clock. O Direct LED drive capability. All Port C pins have the capability to drive an LED without any other external components. These pins have programmable drive strengths set by the GPIO block. I/O Debug. This signal is the control and data input and output to and from the On-Chip Debugger. Clock Input CLKIN LED Drivers LED On-Chip Debugger DBG Caution: The DBG pin is open-drain and requires an external pull-up resistor to ensure proper operation. Reset RESET I/O RESET. Generates a reset when asserted (driven Low). Also serves as a reset indicator; the Z8 Encore! forces this pin low when in reset. This pin is open-drain and features an enabled internal pull-up resistor. Power Supply VDD I Digital power supply. AVDD I Analog power supply. VSS I Digital ground. AVSS I Analog ground. Note: The AVDD and AVSS signals are available only in the 28-pin packages with ADC. They are replaced by PB6 and PB7 on 28-pin packages without ADC. PS025114-1314 Signal Descriptions Z8 Encore!® F0830 Series Product Specification 13 Pin Characteristics Table 5 provides detailed characteristics of each pin available on the Z8 Encore! F0830 Series 20- and 28-pin devices. Data in Table 5 are sorted alphabetically by the pin symbol mnemonic. Table 5. Pin Characteristics (20- and 28-pin Devices) Symbol Mnemonic Reset Direction Direction Active Low or Active High Internal Tristate Pull-Up or Output Pull-Down Schmitt5V Trigger Open Drain Output Tolerance Input AVDD N/A N/A N/A N/A N/A N/A N/A N/A AVSS N/A N/A N/A N/A N/A N/A N/A NA DBG I/O I N/A Yes No Yes Yes Yes PA[7:0] I/O I N/A Yes Programmable pull-up Yes Yes, Programmable PA[7:2] only PB[7:0] I/O I N/A Yes Programmable pull-up Yes Yes, Programmable PB[7:6] only PC[7:0] I/O I N/A Yes Programmable pull-up Yes Yes, Programmable PC[7:3] only RESET/PD0 I/O I/O (defaults to RESET) Low (in RESET mode) Yes (PD0 only) Programmable for PD0; always on for RESET Yes Programmable for PD0; always on for RESET Yes VDD N/A N/A N/A N/A N/A N/A VSS N/A N/A N/A N/A N/A N/A Note: PB6 and PB7 are available only in devices without an ADC function. PS025114-1314 Pin Characteristics Z8 Encore!® F0830 Series Product Specification 14 Address Space The eZ8 CPU can access the following three distinct address spaces: • The register file addresses access for the general purpose registers and the eZ8 CPU, peripheral and general purpose I/O port control registers • The program memory addresses access for all of the memory locations having executable code and/or data • The data memory addresses access for all of the memory locations containing only the data The following sections describe these three address spaces. For more information about the eZ8 CPU and its address space, refer to the eZ8 CPU Core User Manual (UM0128), which is available for download at www.zilog.com. Register File The register file address space in the Z8 Encore! MCU is 4 KB (4096 bytes). The register file consists of two sections: control registers and general-purpose registers. When instructions are executed, registers defined as source are read and registers defined as destinations are written. The architecture of the eZ8 CPU allows all general purpose registers to function as accumulators, address pointers, index registers, stack areas or scratch pad memory. The upper 256 bytes of the 4 KB register file address space are reserved for controlling the eZ8 CPU, on-chip peripherals and the I/O ports. These registers are located at addresses from F00h to FFFh. Some of the addresses within the 256 B Control Register section are reserved (unavailable). Reading from a reserved register file address returns an undefined value. Writing to reserved register file addresses is not recommended and can produce unpredictable results. The on-chip RAM always begins at address 000h in the register file address space. The Z8 Encore! F0830 Series devices contain up to 256 B of on-chip RAM. Reading from register file addresses outside the available RAM addresses (and not within the Control Register address space), returns an undefined value. Writing to these register file addresses has no effect. PS025114-1314 Address Space Z8 Encore!® F0830 Series Product Specification 15 Program Memory The eZ8 CPU supports 64 KB of program memory address space. The Z8 Encore! F0830 Series devices contain 1 KB to 12 KB of on-chip Flash memory in the program memory address space, depending on the device. Reading from program memory addresses outside the available Flash memory address range returns FFh. Writing to these unimplemented program memory addresses produces no effect. Table 6 shows a program memory map for the Z8 Encore! F0830 Series products. Table 6. Z8 Encore! F0830 Series Program Memory Maps Program Memory Address (Hex) Function Z8F0830 and Z8F0831 Products 0000–0001 Flash Option Bits 0002–0003 Reset Vector 0004–003D Interrupt Vectors* 003E–1FFF Program Memory Z8F0430 and Z8F0431 Products 0000–0001 Flash Option Bits 0002–0003 Reset Vector 0004–003D Interrupt Vectors* 003E–0FFF Program Memory Z8F0130 and Z8F0131 Products 0000–0001 Flash Option Bits 0002–0003 Reset Vector 0004–003D Interrupt Vectors* 003E–03FF Program Memory Z8F0230 and Z8F0231 Products 0000–0001 Flash Option Bits 0002–0003 Reset Vector 0004–003D Interrupt Vectors* 003E–07FF Program Memory Note: *See Table 34 on page 54 for a list of interrupt vectors. PS025114-1314 Program Memory Z8 Encore!® F0830 Series Product Specification 16 Data Memory The Z8 Encore! F0830 Series does not use the eZ8 CPU’s 64 KB data memory address space. Flash Information Area Table 7 maps the Z8 Encore! F0830 Series Flash information area. The 128-byte information area is accessed, by setting bit 7 of the Flash Page Select Register to 1. When access is enabled, the Flash information area is mapped into program memory and overlays these 128 bytes at addresses FE00h to FE7Fh. When information area access is enabled, all reads from these program memory addresses return information area data rather than program memory data. Access to the Flash information area is read-only. Table 7. Z8 Encore! F0830 Series Flash Memory Information Area Map PS025114-1314 Program Memory Address (Hex) Function FE00–FE3F Zilog option bits FE40–FE53 Part Number 20-character ASCII alphanumeric code Left-justified and filled with Fh FE54–FE5F Reserved FE60–FE7F Reserved FE80–FFFF Reserved Data Memory Z8 Encore!® F0830 Series Product Specification 17 Register Map Table 8 provides an address map of the Z8 Encore! F0830 Series register file. Not all devices and package styles in the Z8 Encore! F0830 Series support the ADC or all of the GPIO ports. Consider registers for unimplemented peripherals as reserved. Table 8. Register File Address Map Address (Hex) Register Description Mnemonic Reset (Hex) Page No. General Purpose RAM 000–0FF General purpose register file RAM — XX 100–EFF Reserved — XX Timer 0 F00 Timer 0 high byte T0H 00 83 F01 Timer 0 low byte T0L 01 83 F02 Timer 0 reload high byte T0RH FF 85 F03 Timer 0 reload low byte T0RL FF 85 F04 Timer 0 PWM high byte T0PWMH 00 86 F05 Timer 0 PWM low byte T0PWML 00 86 F06 Timer 0 control 0 T0CTL0 00 87 F07 Timer 0 control 1 T0CTL1 00 88 F08 Timer 1 high byte T1H 00 83 F09 Timer 1 low byte T1L 01 83 F0A Timer 1 reload high byte T1RH FF 85 F0B Timer 1 reload low byte T1RL FF 85 F0C Timer 1 PWM high byte T1PWMH 00 86 F0D Timer 1 PWM low byte T1PWML 00 86 F0E Timer 1 control 0 T1CTL0 00 87 F0F Timer 1 control 1 T1CTL1 00 83 F10–F6F Reserved — XX ADCCTL0 00 — XX ADCD_H XX Timer 1 Analog-to-Digital Converter (ADC) F70 ADC control 0 F71 Reserved F72 ADC data high byte 102 103 Note: XX = Undefined. PS025114-1314 Register Map Z8 Encore!® F0830 Series Product Specification 18 Table 8. Register File Address Map (Continued) Address (Hex) Register Description Mnemonic Reset (Hex) Page No. Analog-to-Digital Converter (ADC, cont’d) F73 ADC data low bits ADCD_L XX 103 F74 ADC sample settling time ADCSST 0F 104 F75 ADC sample time ADCST 3F 105 F76 Reserved — XX F77–F7F Reserved — XX PWRCTL0 88 — XX LEDEN 00 51 Low Power Control F80 Power control 0 F81 Reserved 32 LED Controller F82 LED drive enable F83 LED drive level high LEDLVLH 00 51 F84 LED drive level low LEDLVLL 00 52 F85 Reserved — XX OSCCTL A0 — XX CMP0 14 — XX IRQ0 00 58 Oscillator Control F86 Oscillator control F87–F8F Reserved 154 Comparator 0 F90 Comparator 0 control F91–FBF Reserved 107 Interrupt Controller FC0 Interrupt request 0 FC1 IRQ0 enable high bit IRQ0ENH 00 61 FC2 IRQ0 enable low Bit IRQ0ENL 00 61 FC3 Interrupt request 1 IRQ1 00 59 FC4 IRQ1 enable high bit IRQ1ENH 00 62 FC5 IRQ1 enable low bit IRQ1ENL 00 63 FC6 Interrupt request 2 IRQ2 00 60 FC7 IRQ2 enable high bit IRQ2ENH 00 64 FC8 IRQ2 enable low bit IRQ2ENL 00 64 FC9–FCC Reserved — XX FCD Interrupt edge select IRQES 00 66 Note: XX = Undefined. PS025114-1314 Register Map Z8 Encore!® F0830 Series Product Specification 19 Table 8. Register File Address Map (Continued) Address (Hex) Register Description Mnemonic Reset (Hex) Page No. Interrupt Controller (cont’d) FCE Shared interrupt select IRQSS 00 66 FCF Interrupt control IRQCTL 00 67 FD0 Port A address PAADDR 00 39 FD1 Port A control PACTL 00 41 FD2 Port A input data PAIN XX 41 FD3 Port A output data PAOUT 00 41 GPIO Port A GPIO Port B FD4 Port B address PBADDR 00 39 FD5 Port B control PBCTL 00 41 FD6 Port B input data PBIN XX 41 FD7 Port B output data PBOUT 00 41 GPIO Port C FD8 Port C address PCADDR 00 39 FD9 Port C control PCCTL 00 41 FDA Port C input data PCIN XX 41 FDB Port C output data PCOUT 00 41 GPIO Port D FDC Port D address PDADDR 00 39 FDD Port D control PDCTL 00 41 FDE Reserved — XX FDF Port D output data PDOUT 00 FE0–FEF Reserved — XX Reset status RSTSTAT XX 95 Watchdog Timer control WDTCTL XX 95 41 Watchdog Timer (WDT) FF0 FF1 Watchdog Timer reload upper byte WDTU FF 96 FF2 Watchdog Timer reload high byte WDTH FF 96 FF3 Watchdog Timer reload low byte WDTL FF 97 FF4–FF5 Reserved — XX Note: XX = Undefined. PS025114-1314 Register Map Z8 Encore!® F0830 Series Product Specification 20 Table 8. Register File Address Map (Continued) Address (Hex) Register Description Mnemonic Reset (Hex) Page No. TRMADR 00 126 TRMDR XX 127 Trim Bit Control FF6 Trim bit address FF7 Trim data Flash Memory Controller FF8 Flash control FCTL 00 119 FF8 Flash status FSTAT 00 120 FF9 Flash page select FPS 00 121 FPROT 00 122 Flash sector protect FFA Flash programming frequency high byte FFREQH 00 123 FFB Flash programming frequency low byte FFREQL 00 123 Refer to the eZ8 CPU Core User Manual (UM0128) eZ8 CPU FFC Flags — XX FFD Register pointer RP XX FFE Stack pointer high byte SPH XX FFF Stack pointer low byte SPL XX Note: XX = Undefined. PS025114-1314 Register Map Z8 Encore!® F0830 Series Product Specification 21 Reset and Stop Mode Recovery The reset controller in the Z8 Encore! F0830 Series controls RESET and Stop Mode Recovery operations. In a typical operation, the following events can cause a reset: • • • Power-On Reset (POR) • External RESET pin assertion (when the alternate RESET function is enabled by the GPIO register) • On-Chip Debugger initiated reset (OCDCTL[0] set to 1) Voltage Brown-Out (VBO) Watchdog Timer time-out (when configured by the WDT_RES Flash option bit to initiate a reset) When the device is in Stop Mode, a Stop Mode Recovery event is initiated by either of the following occurrences: • • A Watchdog Timer time-out A GPIO port input pin transition on an enabled Stop Mode Recovery source The VBO circuitry on the device generates a VBO reset when the supply voltage drops below a minimum safe level. Reset Types The Z8 Encore! F0830 Series provides different types of Reset operations. Stop Mode Recovery is considered a form of reset. Table 9 lists the types of resets and their operating characteristics. The duration of a system reset is longer if the external crystal oscillator is enabled by the Flash option bits; the result is additional time for oscillator startup. PS025114-1314 Reset and Stop Mode Recovery Z8 Encore!® F0830 Series Product Specification 22 Table 9. Reset and Stop Mode Recovery Characteristics and Latency Reset Characteristics and Latency Reset Type Control Registers eZ8 CPU Reset Latency (Delay) System Reset Reset (as applicable) Reset About 66 Internal Precision Oscillator Cycles System Reset with Crystal Reset (as applicable) Oscillator Enabled Reset About 5000 Internal Precision Oscillator Cycles Stop Mode Recovery Unaffected, except WDT_CTL and OSC_CTL registers Reset About 66 Internal Precision Oscillator cycles Stop Mode Recovery with Unaffected, except crystal oscillator enabled WDT_CTL and OSC_CTL registers Reset About 5000 Internal Precision Oscillator cycles During a system RESET or Stop Mode Recovery, the Z8 Encore! F0830 Series device is held in reset for about 66 cycles of the Internal Precision Oscillator. If the crystal oscillator is enabled in the Flash option bits, the reset period is increased to about 5000 IPO cycles. When a reset occurs because of a low voltage condition or Power-On Reset, the reset delay is measured from the time that the supply voltage first exceeds the POR level (discussed later in this chapter). If the external pin reset remains asserted at the end of the reset period, the device remains in reset until the pin is deasserted. At the beginning of reset, all GPIO pins are configured as inputs with pull-up resistor disabled, except PD0 which is shared with the reset pin. On reset, the Port D0 pin is configured as a bidirectional open-drain reset. This pin is internally driven low during port reset, after which the user code may reconfigure this pin as a general purpose output. During reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal oscillator and Watchdog Timer Oscillator continues to run. On reset, control registers within the register file that have a defined reset value are loaded with their reset values. Other control registers (including the Stack Pointer, Register Pointer and Flags) and general purpose RAM are undefined following the reset. The eZ8 CPU fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program counter. Program execution begins at the reset vector address. Because the control registers are reinitialized by a system reset, the system clock after reset is always the IPO. User software must reconfigure the oscillator control block, to enable and select the correct system clock source. PS025114-1314 Reset Types Z8 Encore!® F0830 Series Product Specification 23 Reset Sources Table 10 lists the possible sources of a system reset. Table 10. Reset Sources and Resulting Reset Type Operating Mode Reset Source Special Conditions Normal or Halt modes Power-On Reset/Voltage Brown-Out Reset delay begins after supply voltage exceeds POR level. Watchdog Timer time-out when con- None. figured for reset Stop Mode RESET pin assertion All reset pulses less than four system clocks in width are ignored. On-Chip Debugger initiated reset (OCDCTL[0] set to 1) System, except the On-Chip Debugger is unaffected by the reset. Power-On Reset/Voltage Brown-Out Reset delay begins after supply voltage exceeds POR level. RESET pin assertion All reset pulses less than 12 ns are ignored. DBG pin driven Low None. Power-On Reset Each device in the Z8 Encore! F0830 Series contains an internal Power-On Reset circuit. The POR circuit monitors the digital supply voltage and holds the device in the Reset state until the digital supply voltage reaches a safe operating level. After the supply voltage exceeds the POR voltage threshold (VPOR), the device is held in the Reset state until the POR counter has timed out. If the crystal oscillator is enabled by the option bits, the timeout is longer. After the Z8 Encore! F0830 Series device exits the Power-On Reset state, the eZ8 CPU fetches the reset vector. Following the Power-On Reset, the POR status bit in the Reset Status (RSTSTAT) Register is set to 1. Figure 6 displays the Power-On Reset operation. See the Electrical Characteristics chapter on page 184 for the POR threshold voltage (VPOR). PS025114-1314 Reset Sources Z8 Encore!® F0830 Series Product Specification 24 VDD = 3.3V VPOR VVBO Program Execution VDD = 0.0V Internal Precision Oscillator Crystal Oscillator Oscillator Start-up Internal RESET signal Note: Not to Scale POR counter delay optional XTAL counter delay Figure 6. Power-On Reset Operation Voltage Brown-Out Reset The devices in the Z8 Encore! F0830 Series provide low Voltage Brown-Out (VBO) protection. The VBO circuit forces the device to the Reset state, when the supply voltage drops below the VBO threshold voltage (unsafe level). While the supply voltage remains below the Power-On Reset threshold voltage (VPOR), the VBO circuit holds the device in reset. After the supply voltage exceeds the Power-On Reset threshold voltage, the device progresses through a full system reset sequence, as described in the POR section. Following Power-On Reset, the POR status bit in the Reset Status (RSTSTAT) Register is set to 1. Figure 7 displays the Voltage Brown-Out operation. See the Electrical Characteristics chapter on page 184 for the VBO and POR threshold voltages (VVBO and VPOR). The POR level is greater than the VBO level by the specified hysteresis value. This ensures that the device undergoes a POR after recovering from a VBO condition. PS025114-1314 Reset Sources Z8 Encore!® F0830 Series Product Specification 25 The Voltage Brown-Out circuit can be either enabled or disabled during Stop Mode. Operations during Stop Mode is set by the VBO_AO Flash option bit. See the Flash Option Bits chapter on page 124 for information about configuring VBO_AO. VDD = 3.3V VDD = 3.3V VPOR VVBO Program Execution Voltage Brown-Out Program Execution WDT Clock System Clock Internal RESET signal POR counter delay Note: Not to Scale Figure 7. Voltage Brown-Out Reset Operation Watchdog Timer Reset If the device is operating in Normal or Stop modes, the Watchdog Timer can initiate a system reset at time-out if the WDT_RES Flash option bit is programmed to 1; this state is the unprogrammed state of the WDT_RES Flash option bit. If the bit is programmed to 0, it configures the Watchdog Timer to cause an interrupt – not a system reset – at time-out. The WDT status bit in the Reset Status (RSTSTAT) Register is set to 1 to signify that the reset was initiated by the Watchdog Timer. External Reset Input The RESET pin has a Schmitt-triggered input and an internal pull-up resistor. After the RESET pin is asserted for a minimum of four system clock cycles, the device progresses through the system reset sequence. Because of the possible asynchronicity of the system PS025114-1314 Reset Sources Z8 Encore!® F0830 Series Product Specification 26 clock and reset signals, the required reset duration may be three or four clock periods. A reset pulse of three clock cycles in duration might trigger a reset and a reset pulse of four cycles in duration always triggers a reset. While the RESET input pin is asserted low, the Z8 Encore! F0830 Series devices remain in the Reset state. If the RESET pin is held low beyond the system reset time-out, the device exits the Reset state on the system clock rising edge following RESET pin deassertion. Following a system reset initiated by the external RESET pin, the EXT status bit in the Reset Status (RSTSTAT) Register is set to 1. External Reset Indicator During system reset or when enabled by the GPIO logic, the RESET pin functions as an open-drain (active low) RESET mode indicator in addition to the input functionality. This reset output feature allows an Z8 Encore! F0830 Series device to reset other components to which it is connected, even if that reset is caused by internal sources such as POR, VBO or WDT events. See the Port A–D Control Registers section on page 41. After an internal Reset event occurs, the internal circuitry begins driving the RESET pin low. The RESET pin is held low by the internal circuitry until the appropriate delay listed in Table 9 (see page 22) has elapsed. On-Chip Debugger Initiated Reset A Power-On Reset can be initiated using the On-Chip Debugger by setting the RST bit in the OCD Control Register. The OCD block is not reset, but the remainder of the chip goes through a normal system reset. The RST bit automatically clears during the system reset. Following the system reset, the POR bit in the Reset Status (RSTSTAT) Register is set. Stop Mode Recovery The device enters the Stop Mode when the STOP instruction is executed by the eZ8 CPU. See the Low-Power Modes chapter on page 30 for detailed Stop Mode information. During Stop Mode Recovery, the CPU is held in reset for about 66 IPO cycles if the crystal oscillator is disabled or about 5000 cycles if it is enabled. Stop Mode Recovery does not affect the on-chip registers other than the Reset Status (RSTSTAT) Register and the Oscillator Control Register (OSCCTL). After any Stop Mode Recovery, the IPO is enabled and selected as the system clock. If another system clock source is required or IPO disabling is required, the Stop Mode Recovery code must reconfigure the oscillator control block such that the correct system clock source is enabled and selected. PS025114-1314 Stop Mode Recovery Z8 Encore!® F0830 Series Product Specification 27 The eZ8 CPU fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program counter. Program execution begins at the reset vector address. Following Stop Mode Recovery, the STOP bit in the Reset Status (RSTSTAT) Register is set to 1. Table 11 lists the Stop Mode Recovery sources and resulting actions. The following sections provide more details about each of the Stop Mode Recovery sources. Table 11. Stop Mode Recovery Sources and Resulting Action Operating Mode Stop Mode Stop Mode Recovery Source Action Watchdog Timer time-out when configured for Reset Stop Mode Recovery Watchdog Timer time-out when configured for interrupt Stop Mode Recovery followed by interrupt (if interrupts are enabled) Data transition on any GPIO port pin enabled Stop Mode Recovery as a Stop Mode Recovery source Assertion of external RESET Pin System reset Debug pin driven Low System reset Stop Mode Recovery using WDT Time-Out If the Watchdog Timer times out during Stop Mode, the device undergoes a Stop Mode Recovery sequence. In the Reset Status (RSTSTAT) Register, the WDT and STOP bits are set to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and the Z8 Encore! F0830 Series device is configured to respond to interrupts, the eZ8 CPU services the WDT interrupt request following the normal Stop Mode Recovery sequence. Stop Mode Recovery using GPIO Port Pin Transition Each of the GPIO port pins may be configured as a Stop Mode Recovery input source. If any GPIO pin is enabled as a Stop Mode Recovery source, a change in the input pin value (from High to Low or from Low to High) initiates Stop Mode Recovery. In the Reset Status (RSTSTAT) Register, the STOP bit is set to 1. Caution: In Stop Mode, the GPIO Port Input Data registers (PxIN) are disabled. These Port Input Data registers record the port transition only if the signal stays on the port pin through the end of the Stop Mode Recovery delay. As a result, short pulses on the port pin can initiate Stop Mode Recovery without being written to the Port Input Data Register or without initiating an interrupt (if enabled for that pin). PS025114-1314 Stop Mode Recovery Z8 Encore!® F0830 Series Product Specification 28 Stop Mode Recovery Using the External RESET Pin When the Z8 Encore! F0830 Series device is in Stop Mode and the external RESET pin is driven low, a system reset occurs. Because of a glitch filter operating on the RESET pin, the low pulse must be greater than the minimum width specified about 12 ns or it is ignored. The EXT bit in the Reset Status (RSTSTAT) Register is set. Debug Pin Driven Low Debug reset is initiated when the On-Chip Debugger detects any of the following error conditions on the DBG pin: • • • Serial break (a minimum of nine continuous bits Low) Framing error (received STOP bit is Low) Transmit collision (simultaneous OCD and host transmission detected by the OCD) When the Z8F0830 Series device is operating in Stop Mode, the debug reset will cause a system reset. The On-Chip Debugger block is not reset, but the remainder of the chip’s operations go through a normal system reset. The POR bit in the Reset Status (RSTSTAT) Register is set to 1. Reset Register Definitions The following sections define the Reset registers. Reset Status Register The Reset Status (RSTSTAT) Register, shown in Table 12, is a read-only register that indicates the source of the most recent Reset event, Stop Mode Recovery event or Watchdog Timer time-out event. Reading this register resets the upper four bits to 0. This register shares its address with the Watchdog Timer Control Register, which is writeonly. PS025114-1314 Debug Pin Driven Low Z8 Encore!® F0830 Series Product Specification 29 Table 12. Reset Status Register (RSTSTAT) Bit Field 7 6 5 4 POR STOP WDT EXT RESET R/W See Table 13 R R R Address 3 2 1 0 Reserved 0 0 0 0 0 R R R R R FF0h Bit Description [7] POR Power-On Reset Indicator This bit is set to 1 if a Power-On Reset event occurs and is reset to 0, if a WDT time-out or Stop Mode Recovery occurs. Reading this register also reset this bit to 0. [6] STOP Stop Mode Recovery Indicator This bit is set to 1 if a Stop Mode Recovery occurs. If the STOP and WDT bits are both set to 1, the Stop Mode Recovery occurs because of a WDT time-out. If the STOP bit is 1 and the WDT bit is 0, the Stop Mode Recovery is not caused by a WDT time-out. This bit is reset by a PowerOn Reset or a WDT time-out that occurred while not in Stop Mode. Reading this register also resets this bit. [5] WDT Watchdog Timer Time-Out Indicator This bit is set to 1 if a WDT time-out occurs. A Power-On Reset resets this pin. A Stop Mode Recovery from a change in an input pin also resets this bit. Reading this register resets this bit. This read must occur before clearing the WDT interrupt. [4] EXT External Reset Indicator If this bit is set to 1, a reset initiated by the external RESET pin occurred. A Power-On Reset or a Stop Mode Recovery from a change in an input pin resets this bit. Reading this register resets this bit. [3:0] Reserved These registers are reserved and must be programmed to 0000. Table 13. POR Indicator Values Reset or Stop Mode Recovery Event POR STOP WDT EXT Power-On Reset 1 0 0 0 Reset using RESET pin assertion 0 0 0 1 Reset using Watchdog Timer time-out 0 0 1 0 Reset using the On-Chip Debugger (OCTCTL[1] set to 1) 1 0 0 0 Reset from Stop Mode using DBG pin driven Low 1 0 0 0 Stop Mode Recovery using GPIO pin transition 0 1 0 0 Stop Mode Recovery using WDT time-out 0 1 1 0 PS025114-1314 Reset Register Definitions Z8 Encore!® F0830 Series Product Specification 30 Low-Power Modes The Z8 Encore! F0830 Series products contain power saving features. The highest level of power reduction is provided by the Stop Mode. The next level of power reduction is provided by the HALT Mode. Further power savings can be implemented by disabling the individual peripheral blocks while in Normal Mode. The user must not enable the pull-up register bits for unused GPIO pins, since these ports are default output to VSS. Unused GPIOs include those missing on 20-pin packages, as well as those missing on the ADC-enabled 28-pin packages. Stop Mode Executing the eZ8 CPU’s STOP instruction places the device into Stop Mode. In Stop Mode, the operating characteristics are: • Primary crystal oscillator and Internal Precision Oscillator are stopped; XIN and XOUT (if previously enabled) are disabled and PA0/PA1 revert to the states programmed by the GPIO registers • • • • System clock is stopped • • If enabled, the Watchdog Timer logic continues to operate • All other on-chip peripherals are idle eZ8 CPU is stopped Program counter (PC) stops incrementing Watchdog Timer’s internal RC oscillator continues to operate if enabled by the Oscillator Control Register If enabled for operation in Stop Mode by the associated Flash option bit, the Voltage Brown-Out protection circuit continues to operate To minimize the current in Stop Mode, all GPIO pins that are configured as digital inputs must be driven to VDD when the pull-up register bit is enabled or to one of power rail (VDD or GND) when the pull-up register bit is disabled. The device can be brought out of Stop Mode using Stop Mode Recovery. For more information about Stop Mode Recovery, see the Reset and Stop Mode Recovery chapter on page 21. PS025114-1314 Low-Power Modes Z8 Encore!® F0830 Series Product Specification 31 HALT Mode Executing the eZ8 CPU HALT instruction places the device into HALT Mode. In HALT Mode, the operating characteristics are: • • • • • • • Primary oscillator is enabled and continues to operate System clock is enabled and continues to operate eZ8 CPU is stopped Program counter (PC) stops incrementing Watchdog Timer’s internal RC oscillator continues to operate If enabled, the Watchdog Timer continues to operate All other on-chip peripherals continue to operate The eZ8 CPU can be brought out of HALT Mode by any one of the following operations: • • • • • Interrupt Watchdog Timer time-out (interrupt or reset) Power-On Reset Voltage Brown-Out reset External RESET pin assertion To minimize current in HALT Mode, all GPIO pins that are configured as digital inputs must be driven to VDD when pull-up register bit is enabled or to one of power rail (VDD or GND) when pull-up register bit is disabled. Peripheral Level Power Control In addition to the Stop and Halt modes, it is possible to disable each peripheral on each of the Z8 Encore! F0830 Series devices. Disabling a given peripheral minimizes its power consumption. Power Control Register Definitions Power Control Register 0 Each bit of the following registers disables a peripheral block, either by gating its system clock input or by removing power from the block. PS025114-1314 HALT Mode Z8 Encore!® F0830 Series Product Specification 32 Note: This register is only reset during a Power-On Reset sequence. Other system reset events do not affect it. Table 14. Power Control Register 0 (PWRCTL0) Bit 7 Field RESET R/W 6 5 Reserved 4 VBO 3 2 Reserved Reserved 1 0 COMP Reserved 1 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address F80h Bit Description [7:5] Reserved These registers are reserved and must be programmed to 000. [4] VBO Voltage Brown-Out detector disable This bit takes only effect when the VBO_AO Flash option bit is disabled. In Stop Mode, VBO is always disabled when the VBO_AO Flash option bit is disabled. To learn more about the VBO_AO Flash option bit function, see the Flash Option Bits chapter on page 124. 0 = VBO enabled. 1 = VBO disabled. [3] Reserved This bit is reserved and must be programmed to 1. [2] Reserved This bit is reserved and must be programmed to 0. [1] COMP Comparator Disable 0 = Comparator is enabled. 1 = Comparator is disabled. [0] Reserved This bit is reserved and must be programmed to 0. PS025114-1314 Power Control Register Definitions Z8 Encore!® F0830 Series Product Specification 33 General Purpose Input/Output The Z8 Encore! F0830 Series products support a maximum of 25 port pins (Ports A–D) for General Purpose Input/Output (GPIO) operations. Each port contains control and data registers. The GPIO control registers determine data direction, open-drain, output drive current, programmable pull-ups, Stop Mode Recovery functionality and alternate pin functions. Each port pin is individually programmable. In addition, the Port C pins are capable of direct LED drive at programmable drive strengths. GPIO Port Availability by Device Table 15 lists the port pins available with each device and package type. Table 15. Port Availability by Device and Package Type Package 10-Bit ADC Port A Port B Port C Port D Total I/O Z8F1232, Z8F0830, Z8F0430, Z8F0230, Z8F0130 20-pin Yes [7:0] [3:0] [3:0] [0] 17 Z8F1233, Z8F0831 Z8F0431, Z8F0231 Z8F0131 20-pin No [7:0] [3:0] [3:0] [0] 17 Z8F1232, Z8F0830, Z8F0430, Z8F0230, Z8F0130 28-pin Yes [7:0] [5:0] [7:0] [0] 23 Z8F1233, Z8F0831 Z8F0431, Z8F0231 Z8F0131 28-pin No [7:0] [7:0] [7:0] [0] 25 Devices Note: 20-pin and 28-pin and 10-bit ADC Enabled or Disabled can be selected via the option bits. PS025114-1314 General Purpose Input/Output Z8 Encore!® F0830 Series Product Specification 34 Architecture Figure 8 displays a simplified block diagram of a GPIO port pin. In this figure, the ability to accommodate alternate functions and variable port current drive strength is not displayed. Port Input Data Register Q D Schmitt Trigger Q D System Clock VDD Port Output Control Port Output Data Register DATA Bus D Q Port Pin System Clock Port Data Direction GND Figure 8. GPIO Port Pin Block Diagram GPIO Alternate Functions Many of the GPIO port pins can be used for general purpose input/output and access to onchip peripheral functions such as the timers and serial communication devices. The Port A–D Alternate Function subregisters configure these pins for either GPIO or Alternate function operation. When a pin is configured for Alternate function, control of the port pin direction (input/output) is passed from the Port A–D data direction registers to the Alternate function assigned to this pin. Table 16 on page 36 lists the alternate functions possible with each port pin. The alternate function associated at a pin is defined through Alternate Function subregisters AFS1 and AFS2. The crystal oscillator functionality is not controlled by the GPIO block. When the crystal oscillator is enabled in the oscillator control block, the GPIO functionality of PA0 and PA1 is overridden. In that case, pins PA0 and PA1 functions as input and output for the crystal oscillator. PS025114-1314 Architecture Z8 Encore!® F0830 Series Product Specification 35 PA0 and PA6 contain two different Timer functions, a timer input and a complementary timer output. Both of these functions require the same GPIO configuration, the selection between the two is based on the TIMER mode. For more details, see the Timers chapter on page 68. Direct LED Drive The Port C pins provide a sinked current output, capable of driving an LED without requiring an external resistor. The output sinks current at programmable levels, 3 mA, 7 mA, 13 mA and 20 mA. This mode is enabled through the LED Control registers. For proper function, the LED anode must be connected to VDD and the cathode to the GPIO pin. Using all Port C pins in LED drive mode with maximum current may result in excessive total current. See the Electrical Characteristics chapter on page 184 for the maximum total current for the applicable package. Shared Reset Pin On the 20- and 28-pin devices, the Port D0 pin shares function with a bidirectional reset pin. Unlike all other I/O pins, this pin does not default to GPIO function on power-up. This pin acts as a bidirectional input/output open-drain reset with an internal pull-up until the user software reconfigures it as a GPIO PD0. When in GPIO mode, the Port D0 pin functions as output only, and must be configured as an output. PD0 supports the high drive feature, but not the stop-mode recovery feature. Crystal Oscillator Override For systems using a crystal oscillator, the pins PA0 and PA1 are connected to the crystal. When the crystal oscillator is enabled, the GPIO settings are overridden and PA0 and PA1 are disabled. See the Oscillator Control Register Definitions section on page 154. 5 V Tolerance In the 20- and 28-pin versions of this device, any pin, which shares functionality with an ADC, crystal or comparator port is not 5 V-tolerant, including PA[1:0], PB[5:0] and PC[2:0]. All other signal pins are 5 V-tolerant and can safely handle inputs higher than VDD even with the pull-ups enabled, but with excess power consumption on pull-up resistor. PS025114-1314 Direct LED Drive Z8 Encore!® F0830 Series Product Specification 36 External Clock Setup For systems using an external TTL drive, PB3 is the clock source for 20- and 28-pin devices. In this case, configure PB3 for Alternate function CLKIN. Write to the Oscillator Control Register (see the Oscillator Control Register Definitions section on page 154) to select the PB3 as the system clock. Table 16. Port Alternate Function Mapping Port Pin Mnemonic Alternate Function Description Alternate Function Set Register AFS1 Port A1 PA0 T0IN/T0OUT Timer 0 input/Timer 0 output complement N/A Reserved PA1 T0OUT Timer 0 output Reserved PA2 Reserved Reserved Reserved PA3 Reserved Reserved Reserved PA4 Reserved Reserved Reserved PA5 Reserved Reserved Reserved PA6 T1IN/T1OUT Timer 1 input/Timer 1 output complement Reserved PA7 T1OUT Timer 1 output Reserved Notes: 1. Because there is only a single alternate function for each Port A and Port D (PD0) pin, the Alternate Function Set registers are not implemented for Port A and Port D (PD0). Enabling alternate function selections (as described in the Port A–D Alternate Function Subregisters section on page 42) automatically enables the associated alternate function. 2. Because there are at most two choices of alternate functions for any Port B pin, the AFS2 Alternate Function Set Register is implemented but is not used to select the function. Additionally, alternate function selection (as described in the Port A–D Alternate Function Subregisters section on page 42) must also be enabled. 3. Because there are at most two choices of alternate functions for any Port C pin, the AFS2 Alternate Function Set Register is implemented but is not used to select the function. Additionally, alternate function selection (as described in the Port A–D Alternate Function Subregisters section on page 42) must also be enabled. PS025114-1314 External Clock Setup Z8 Encore!® F0830 Series Product Specification 37 Table 16. Port Alternate Function Mapping (Continued) Port Pin Mnemonic Port B2 PB0 Reserved ANA0 PB1 PB3 PB4 PB7 AFS1[0]: 1 AFS1[1]: 0 ADC analog input AFS1[1]: 1 AFS1[2]: 0 ANA2 ADC analog input AFS1[2]: 1 CLKIN External input clock AFS1[3]: 0 ANA3 ADC analog input AFS1[3]: 1 Reserved AFS1[4]: 0 ADC analog input Reserved VREF PB6 ADC analog input Reserved ANA7 PB5 Alternate Function Set Register AFS1 AFS1[0]: 0 Reserved ANA1 PB2 Alternate Function Description AFS1[4]: 1 AFS1[5]: 0 ADC reference voltage AFS1[5]: 1 Reserved AFS1[6]: 0 Reserved AFS1[6]: 1 Reserved AFS1[7]: 0 Reserved AFS1[7]: 1 Notes: 1. Because there is only a single alternate function for each Port A and Port D (PD0) pin, the Alternate Function Set registers are not implemented for Port A and Port D (PD0). Enabling alternate function selections (as described in the Port A–D Alternate Function Subregisters section on page 42) automatically enables the associated alternate function. 2. Because there are at most two choices of alternate functions for any Port B pin, the AFS2 Alternate Function Set Register is implemented but is not used to select the function. Additionally, alternate function selection (as described in the Port A–D Alternate Function Subregisters section on page 42) must also be enabled. 3. Because there are at most two choices of alternate functions for any Port C pin, the AFS2 Alternate Function Set Register is implemented but is not used to select the function. Additionally, alternate function selection (as described in the Port A–D Alternate Function Subregisters section on page 42) must also be enabled. PS025114-1314 External Clock Setup Z8 Encore!® F0830 Series Product Specification 38 Table 16. Port Alternate Function Mapping (Continued) Port Pin Mnemonic Port C3 PC0 Reserved ANA4/CINP PC1 PC3 PC4 Alternate Function Set Register AFS1 AFS1[0]: 0 ADC or comparator input Reserved ANA5/CINN PC2 Alternate Function Description AFS1[0]: 1 AFS1[1]: 0 ADC or comparator input Reserved AFS1[1]: 1 AFS1[2]: 0 ANA6 ADC analog input AFS1[2]: 1 COUT Comparator output AFS1[3]: 0 Reserved AFS1[3]: 1 Reserved AFS1[4]: 0 AFS1[4]: 1 PC5 Reserved AFS1[5]: 0 AFS1[5]: 1 PC6 Reserved AFS1[6]: 0 AFS1[6]: 1 PC7 Reserved AFS1[7]: 0 AFS1[7]: 1 Port D1 PD0 RESET Default to be Reset function N/A Notes: 1. Because there is only a single alternate function for each Port A and Port D (PD0) pin, the Alternate Function Set registers are not implemented for Port A and Port D (PD0). Enabling alternate function selections (as described in the Port A–D Alternate Function Subregisters section on page 42) automatically enables the associated alternate function. 2. Because there are at most two choices of alternate functions for any Port B pin, the AFS2 Alternate Function Set Register is implemented but is not used to select the function. Additionally, alternate function selection (as described in the Port A–D Alternate Function Subregisters section on page 42) must also be enabled. 3. Because there are at most two choices of alternate functions for any Port C pin, the AFS2 Alternate Function Set Register is implemented but is not used to select the function. Additionally, alternate function selection (as described in the Port A–D Alternate Function Subregisters section on page 42) must also be enabled. PS025114-1314 External Clock Setup Z8 Encore!® F0830 Series Product Specification 39 GPIO Interrupts Many of the GPIO port pins can be used as interrupt sources. Some port pins can be configured to generate an interrupt request on either the rising edge or falling edge of the input pin signal. Other port pin interrupt sources, generate an interrupt when any edge occurs (both rising and falling). See the Interrupt Controller chapter on page 53 for more information about interrupts using the GPIO pins. GPIO Control Register Definitions Four registers for each port provide access to GPIO control, input data and output data; Table 17 lists these port registers. Use the Port A–D Address and Control registers together to provide access to subregisters for port configuration and control. Table 17. GPIO Port Registers and Subregisters Port Register Mnemonic Port Register Name PxADDR Port A–D Address Register (selects subregisters) PxCTL Port A–D Control Register (provides access to subregisters) PxIN Port A–D Input Data Register PxOUT Port A–D Output Data Register Port Subregister Mnemonic Port Register Name PxDD Data Direction PxAF Alternate Function PxOC Output Control (open-drain) PxHDE High Drive Enable PxSMRE Stop Mode Recovery Source Enable PxPUE Pull-Up Enable PxAFS1 Alternate Function Set 1 PxAFS2 Alternate Function Set 2 PS025114-1314 GPIO Interrupts Z8 Encore!® F0830 Series Product Specification 40 Port A–D Address Registers The Port A–D Address registers select the GPIO port functionality accessible through the Port A–D Control registers. The Port A–D Address and Control registers combine to provide access to all GPIO port controls; see Tables 18 and 19. Table 18. Port A–D GPIO Address Registers (PxADDR) Bit 7 6 5 4 Field 3 2 1 0 R/W R/W R/W PADDR[7:0] RESET 00h R/W R/W R/W R/W Address R/W R/W FD0h, FD4h, FD8h, FDCh Bit Description [7:0] PADDR Port Address The port address selects one of the subregisters accessible through the Port Control Register. Table 19. Port Control Subregister Access PADDR[7:0] Port Control Subregister accessible using the Port A–D Control registers 00h No function. Provides some protection against accidental port reconfiguration. 01h Data Direction 02h Alternate Function 03h Output Control (open-drain) 04h High Drive Enable 05h Stop Mode Recovery Source Enable 06h Pull-Up Enable 07h Alternate Function Set 1 08h Alternate Function Set 2 09h–FFh PS025114-1314 No function GPIO Control Register Definitions Z8 Encore!® F0830 Series Product Specification 41 Port A–D Control Registers The Port A–D Control registers, shown in Table 20, set the GPIO port operation. The value in the corresponding Port A–D Address Register determines which subregister is read from or written to by a Port A–D Control Register transaction. Table 20. Port A–D Control Registers (PxCTL) Bit 7 6 5 4 Field 2 1 0 R/W R/W R/W R/W PCTL RESET R/W 3 00h R/W R/W R/W Address R/W FD1h, FD5h, FD9h, FDDh Bit Description [7:0] PCTL Port Control The Port Control Register provides access to all subregisters that configure the GPIO port operation. Port A–D Data Direction Subregisters The Port A–D Data Direction Subregister, shown in Table 21, is accessed through the Port A–D Control Register by writing 01h to the Port A–D Address Register. Table 21. Port A–D Data Direction Subregisters (PxDD) Bit 7 6 5 4 3 2 1 0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address If 01h in Port A–D Address Register, accessible through the Port A–D Control Register Field RESET Bit Description [7:0] DDx Data Direction These bits control the direction of the associated port pin. Port Alternate Function operation overrides the Data Direction Register setting. 0 = Output. Data in the Port A–D Output Data Register is driven onto the port pin. 1 = Input. The port pin is sampled and the value written into the Port A–D Input Data Register. The output driver is tristated. Note: x indicates the specific GPIO port pin number (7–0). PS025114-1314 GPIO Control Register Definitions Z8 Encore!® F0830 Series Product Specification 42 Port A–D Alternate Function Subregisters The Port A–D Alternate Function Subregister is accessed through the Port A–D Control Register by writing 02h to the Port A–D Address Register. See Table 22 on page 42. The Port A–D Alternate Function subregisters enable the alternate function selection on pins. If disabled, the pins function as GPIOs. If enabled, select one of four alternate functions using Alternate Function Set subregisters 1 and 2, as described in the the Port A–D Alternate Function Set 1 Subregisters section on page 47 and the Port A–D Alternate Function Set 2 Subregisters section on page 48. See the GPIO Alternate Functions section on page 34 to determine the alternate functions associated with each port pin. Caution: Do not enable alternate functions for GPIO port pins for which there is no associated Alternate function. Failure to follow this guideline can result in unpredictable operation. Table 22. Port A–D Alternate Function Subregisters (PxAF) Bit Field 7 6 5 4 3 2 1 0 AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0 RESET 00h (Ports A–C); 01h (Port D) R/W Address R/W If 02h in Port A–D Address Register, then accessible through the Port A–D Control Register Bit Description [7:0] AFx Port Alternate Function Enable 0 = The port pin is in Normal Mode and the DDx bit in the Port A–D Data Direction Subregister determines the direction of the pin. 1 = The alternate function selected through Alternate function set subregisters is enabled. Port pin operation is controlled by the Alternate function. Note: x indicates the specific GPIO port pin number (7–0). PS025114-1314 GPIO Control Register Definitions Z8 Encore!® F0830 Series Product Specification 43 Port A–D Output Control Subregisters The Port A–D Output Control Subregister, shown in Table 23, is accessed through the Port A–D Control Register by writing 03h to the Port A–D Address Register. Setting the bits in the Port A–D Output Control subregisters to 1 configures the specified port pins for opendrain operation. These subregisters affect the pins directly and, as a result, alternate functions are also affected. Table 23. Port A–D Output Control Subregisters (PxOC) Bit 7 6 5 4 3 2 1 0 POC7 POC6 POC5 POC4 POC3 POC2 POC1 POC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address If 03h in Port A–D Address Register, accessible through the Port A–D Control Register Field RESET Bit Description [7:0] POCx Port Output Control These bits function independently of the Alternate function bit and always disable the drains, if set to 1. 0 = The drains are enabled for any OUTPUT Mode (unless overridden by the Alternate function). 1 = The drain of the associated pin is disabled (OPEN-DRAIN mode). Note: x indicates the specific GPIO port pin number (7–0). PS025114-1314 GPIO Control Register Definitions Z8 Encore!® F0830 Series Product Specification 44 Port A–D High Drive Enable Subregisters The Port A–D High Drive Enable Subregister, shown in Table 24, is accessed through the Port A–D Control Register by writing 04h to the Port A–D Address Register. Setting the bits in the Port A–D High Drive Enable subregisters to 1 configures the specified port pins for high-output current drive operation. The Port A–D High Drive Enable Subregister affects the pins directly and, as a result, alternate functions are also affected. Table 24. Port A–D High Drive Enable Subregisters (PxHDE) Bit 7 6 5 4 3 2 1 0 PHDE7 PHDE6 PHDE5 PHDE4 PHDE3 PHDE2 PHDE1 PHDE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address If 04h in Port A–D Address Register, accessible through the Port A–D Control Register Field RESET Bit Description [7:0] PHDEx Port High Drive Enable 0 = The port pin is configured for standard output current drive. 1 = The port pin is configured for high output current drive. Note: x indicates the specific GPIO port pin number (7–0). PS025114-1314 GPIO Control Register Definitions Z8 Encore!® F0830 Series Product Specification 45 Port A–D Stop Mode Recovery Source Enable Subregisters The Port A–D Stop Mode Recovery Source Enable Subregister, shown in Table 25, is accessed through the Port A–D Control Register by writing 05h to the Port A–D Address Register. Setting the bits in the Port A–D Stop Mode Recovery Source Enable subregisters to 1 configures the specified port pins as a Stop Mode Recovery source. During Stop Mode, any logic transition on a port pin enabled as a Stop Mode Recovery source initiates a Stop Mode Recovery event. Table 25. Port A–D Stop Mode Recovery Source Enable Subregisters (PxSMRE) Bit 7 6 5 4 3 2 1 0 PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMRE1 PSMRE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address If 05h in Port A–D Address Register, accessible through the Port A–D Control Register Field RESET Bit Description [7:0] Port Stop Mode Recovery Source Enable PSMREx 0 = The port pin is not configured as a Stop Mode Recovery source. Transitions on this pin during Stop Mode do not initiate Stop Mode Recovery. 1 = The port pin is configured as a Stop Mode Recovery source. Any logic transition on this pin during Stop Mode initiates Stop Mode Recovery. Note: x indicates the specific GPIO port pin number (7–0). PS025114-1314 GPIO Control Register Definitions Z8 Encore!® F0830 Series Product Specification 46 Port A–D Pull-up Enable Subregisters The Port A–D Pull-Up Enable Subregister is accessed through the Port A–D Control Register by writing 06h to the Port A–D Address Register. See Table 26. Setting the bits in the Port A–D Pull-Up Enable subregisters enables a weak internal resistive pull-up on the specified port pins. Table 26. Port A–D Pull-Up Enable Subregisters (PxPUE) Bit 7 6 5 4 3 2 1 0 PPUE7 PPUE6 PPUE5 PPUE4 PPUE3 PPUE2 PPUE1 PPUE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address If 06h in Port A–D Address Register, accessible through the Port A–D Control Register Field RESET Bit Description [7:0] PxPUE Port Pull-Up Enable 0 = The weak pull-up on the port pin is disabled. 1 = The weak pull-up on the port pin is enabled. Note: x indicates the specific GPIO port pin number (7–0). PS025114-1314 GPIO Control Register Definitions Z8 Encore!® F0830 Series Product Specification 47 Port A–D Alternate Function Set 1 Subregisters The Port A–D Alternate Function Set 1 Subregister, shown in Table 27, is accessed through the Port A–D Control Register by writing 07h to the Port A–D Address Register. The Alternate Function Set 1 subregisters select the alternate function available at a port pin. Alternate functions selected by setting or clearing bits in this register are defined in the GPIO Alternate Functions section on page 34. Note: Alternate function selection on the port pins must also be enabled, as described in the Port A–D Alternate Function Subregisters section on page 42. Table 27. Port A–D Alternate Function Set 1 Subregisters (PxAFS1) Bit 7 6 5 4 3 2 1 0 PAFS17 PAFS16 PAFS15 PAFS14 PAFS13 PAFS12 PAFS11 PAFS10 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address If 07h in Port A–D Address Register, accessible through the Port A–D Control Register Field RESET Bit Description [7:0] PAFS1x Port Alternate Function Set 1 0 = Port Alternate function selected as defined in Table 16 in GPIO Alternate Functions section. 1 = Port Alternate function selected as defined in Table 16 in GPIO Alternate Functions section. Note: x indicates the specific GPIO port pin number (7–0). PS025114-1314 GPIO Control Register Definitions Z8 Encore!® F0830 Series Product Specification 48 Port A–D Alternate Function Set 2 Subregisters The Port A–D Alternate Function Set 2 Subregister, shown in Table 28, is accessed through the Port A–D Control Register by writing 08h to the Port A–D Address Register. The Alternate Function Set 2 subregisters select the alternate function available at a port pin. Alternate functions selected by setting or clearing bits in this register are defined in Table 16 in the GPIO Alternate Functions section on page 34. Note: Alternate function selection on the port pins must also be enabled, as described in the Port A–D Alternate Function Subregisters section on page 42. Table 28. Port A–D Alternate Function Set 2 Subregisters (PxAFS2) Bit 7 6 5 4 3 2 1 0 PAFS27 PAFS26 PAFS25 PAFS24 PAFS23 PAFS22 PAFS21 PAFS20 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address If 08h in Port A–D Address Register, accessible through the Port A–D Control Register Field RESET Bit Description [7:0] PAFS2x Port Alternate Function Set 2 0 = The Port Alternate function is selected, as defined in Table 16 in the GPIO Alternate Functions section on page 34. 1 = The Port Alternate function is selected, as defined in Table 16 in the GPIO Alternate Functions section on page 34. Note: x indicates the specific GPIO port pin number (7–0). PS025114-1314 GPIO Control Register Definitions Z8 Encore!® F0830 Series Product Specification 49 Port A–C Input Data Registers Reading from the Port A–C Input Data registers, shown in Table 29, return the sampled values from the corresponding port pins. The Port A–C Input Data registers are read-only. The value returned for any unused ports is 0. Unused ports include those not included in the 8- and 28-pin packages, as well as those not included in the ADC-enabled 28-pin packages. Table 29. Port A–C Input Data Registers (PxIN) Bit 7 6 5 4 3 2 1 0 PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 RESET X X X X X X X X R/W R R R R R R R R Field Address FD2h, FD6h, FDAh Bit Description [7:0] PxIN Port Input Data Sampled data from the corresponding port pin input. 0 = Input data is logical 0 (Low). 1 = Input data is logical 1 (High). Note: x indicates the specific GPIO port pin number (7–0). PS025114-1314 GPIO Control Register Definitions Z8 Encore!® F0830 Series Product Specification 50 Port A–D Output Data Register The Port A–D Output Data Register, shown in Table 30, controls the output data to the pins. Table 30. Port A–D Output Data Register (PxOUT) Bit Field RESET R/W 7 6 5 4 3 2 1 0 POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FD3h, FD7h, FDBh, FDFh Bit Description [7:0] PxOUT Port Output Data These bits contain the data to be driven to the port pins. The values are only driven if the corresponding pin is configured as an output and the pin is not configured for Alternate function operation. 0 = Drive a logical 0 (Low). 1= Drive a logical 1 (High). High value is not driven if the drain has been disabled by setting the corresponding port output Control Register bit to 1. Note: x indicates the specific GPIO port pin number (7–0). PS025114-1314 GPIO Control Register Definitions Z8 Encore!® F0830 Series Product Specification 51 LED Drive Enable Register The LED Drive Enable Register, shown in Table 31, activates the controlled current drive. The Alternate Function Register has no control over the LED function; therefore, setting the Alternate Function Register to select the LED function is not required. LEDEN bits [7:0] correspond to Port C bits [7:0], respectively. Table 31. LED Drive Enable (LEDEN) Bit 7 6 5 Field RESET R/W 4 3 2 1 0 LEDEN[7:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address F82h Bit Description [7:0] LEDEN LED Drive Enable These bits determine which Port C pins are connected to an internal current sink. 0 = Tristate the Port C pin. 1= Connect controlled current sink to the Port C pin. LED Drive Level High Register The LED Drive Level High Register, shown in Table 32, contains two control bits for each Port C pin. These two bits select one of four programmable current drive levels for each Port C pin. Each pin is individually programmable. Table 32. LED Drive Level High Register (LEDLVLH) Bit 7 6 5 Field RESET R/W 3 2 1 0 LEDLVLH[7:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address Bit 4 F83h Description [7:0] LED Level High Bits LEDLVLH {LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each Port C pin. 00 = 3 mA. 01= 7 mA. 10= 13 mA. 11= 20 mA. PS025114-1314 GPIO Control Register Definitions Z8 Encore!® F0830 Series Product Specification 52 LED Drive Level Low Register The LED Drive Level Low Register, shown in Table 33, contains two control bits for each Port C pin. These two bits select one of four programmable current drive levels for each Port C pin. Each pin is individually programmable. Table 33. LED Drive Level Low Register (LEDLVLL) Bit 7 6 5 Field RESET R/W 3 2 1 0 LEDLVLL[7:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address Bit 4 F84h Description [7:0] LED Level Low Bits LEDLVLL {LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each Port C pin. 00 = 3 mA. 01 = 7 mA. 10 = 13 mA. 11 = 20 mA. PS025114-1314 GPIO Control Register Definitions Z8 Encore!® F0830 Series Product Specification 53 Interrupt Controller The Interrupt Controller on the Z8 Encore!® F0830 Series products prioritize the interrupt requests from the on-chip peripherals and the GPIO port pins. The features of the Interrupt Controller include: • Seventeen interrupt sources using sixteen unique interrupt vectors: – Twelve GPIO port pin interrupt sources – Five on-chip peripheral interrupt sources (Comparator Output interrupt shares one interrupt vector with PA6) • Flexible GPIO interrupts – Eight selectable rising and falling edge GPIO interrupts – Four dual-edge interrupts • • Three levels of individually programmable interrupt priority Watchdog Timer can be configured to generate an interrupt m Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt service routine is involved with the exchange of data, status information or control information between the CPU and the interrupting peripheral. When the service routine is completed, the CPU returns to the operation from which it was interrupted. The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the Interrupt Controller has no effect on operation. For more information about interrupt servicing by the eZ8 CPU, refer to the eZ8 CPU User Manual (UM0128), which is available for download at www.zilog.com. Interrupt Vector Listing Table 34 lists the interrupts available in order of priority. The interrupt vector is stored with the most significant byte (MSB) at the even program memory address and the least significant byte (LSB) at the odd program memory address. Note: Some port interrupts are not available on the 20-pin and 28-pin packages. The ADC interrupt is unavailable on devices not containing an ADC. PS025114-1314 Interrupt Controller Z8 Encore!® F0830 Series Product Specification 54 Table 34. Trap and Interrupt Vectors in Order of Priority Priority Program Memory Vector Address Interrupt or Trap Source Highest 0002h Reset (not an interrupt) 0004h Watchdog Timer (see Watchdog Timer chapter) 003Ah Primary oscillator fail trap (not an interrupt) 003Ch Watchdog Oscillator fail trap (not an interrupt) 0006h Illegal instruction trap (not an interrupt) 0008h Reserved 000Ah Timer 1 000Ch Timer 0 000Eh Reserved 0010h Reserved 0012h Reserved 0014h Reserved 0016h ADC 0018h Port A7, selectable rising or falling input edge 001Ah Port A6, selectable rising or falling input edge or Comparator Output 001Ch Port A5, selectable rising or falling input edge 001Eh Port A4, selectable rising or falling input edge 0020h Port A3, selectable rising or falling input edge 0022h Port A2, selectable rising or falling input edge 0024h Port A1, selectable rising or falling input edge 0026h Port A0, selectable rising or falling input edge 0028h Reserved 002Ah Reserved 002Ch Reserved 002Eh Reserved 0030h Port C3, both input edges 0032h Port C2, both input edges 0034h Port C1, both input edges 0036h Port C0, both input edges 0038h Reserved Lowest PS025114-1314 Interrupt Vector Listing Z8 Encore!® F0830 Series Product Specification 55 Architecture Figure 9 displays the Interrupt Controller block diagram. High Priority Internal Interrupts Interrupt Request Latches and Control Port Interrupts Vector Medium Priority Priority Mux IRQ Request Low Priority Figure 9. Interrupt Controller Block Diagram Operation This section describes the operational aspects of the following functions. Master Interrupt Enable: see page 55 Interrupt Vectors and Priority: see page 56 Interrupt Assertion: see page 56 Software Interrupt Assertion: see page 57 Master Interrupt Enable The master interrupt enable bit (IRQE) in the Interrupt Control Register globally enables and disables the interrupts. Interrupts are globally enabled by any of the following actions: • • PS025114-1314 Execution of an EI (enable interrupt) instruction Execution of an IRET (return from interrupt) instruction Architecture Z8 Encore!® F0830 Series Product Specification 56 • Writing 1 to the IRQE bit in the Interrupt Control Register Interrupts are globally disabled by any of the following actions: • • • • • • • • Execution of a Disable Interrupt (DI) instruction eZ8 CPU acknowledgement of an interrupt service request from the Interrupt Controller Writing a 0 to the IRQE bit in the Interrupt Control Register Reset Execution of a trap instruction Illegal instruction Trap Primary oscillator fail trap Watchdog Oscillator fail trap Interrupt Vectors and Priority The Interrupt Controller supports three levels of interrupt priority. Level 3 is the highest priority, level 2 is the second highest priority and level 1 is the lowest priority. If all of the interrupts are enabled with identical interrupt priority (all as level 2 interrupts, for example), the interrupt priority is assigned from highest to lowest as specified in Table 34 on page 54. Level 3 interrupts are always assigned higher priority than level 2 interrupts and level 2 interrupts are assigned higher priority than level 1 interrupts. Within each interrupt priority level (level 1, level 2 or level 3), priority is assigned as specified in Table 34, above. Reset, Watchdog Timer interrupt (if enabled), primary oscillator fail trap, Watchdog Oscillator fail trap and illegal instruction trap always have highest (level 3) priority. Interrupt Assertion Interrupt sources assert their interrupt requests for only a single system clock period (single pulse). When the interrupt request is acknowledged by the eZ8 CPU, the corresponding bit in the interrupt request register is cleared. Writing 0 to the corresponding bit in the interrupt request register clears the interrupt request. Caution: Zilog recommends not using a coding style that clears bits in the Interrupt Request registers. All incoming interrupts received between execution of the first LDX command and the final LDX command are lost. See Example 1, which follows. Example 1. A poor coding style that can result in lost interrupt requests: PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 57 LDX r0, IRQ0 AND r0, MASK LDX IRQ0, r0 To avoid missing interrupts, use the coding style in Example 2 to clear bits in the Interrupt Request 0 Register: Example 2. A good coding style that avoids lost interrupt requests: ANDX IRQ0, MASK Software Interrupt Assertion Program code can generate interrupts directly. Writing 1 to the correct bit in the interrupt request register triggers an interrupt (assuming that interrupt is enabled). When the interrupt request is acknowledged by the eZ8 CPU, the bit in the interrupt request register is automatically cleared to 0. Caution: Zilog recommends not using a coding style to generate software interrupts by setting bits in the Interrupt Request registers. All incoming interrupts received between execution of the first LDX command and the final LDX command are lost. See Example 3, which follows. Example 3. A poor coding style that can result in lost interrupt requests: LDX r0, IRQ0 OR r0, MASK LDX IRQ0, r0 To avoid missing interrupts, use the coding style in Example 4 to set bits in the Interrupt Request registers: Example 4. A good coding style that avoids lost interrupt requests: ORX IRQ0, MASK Interrupt Control Register Definitions The Interrupt Control registers enable individual interrupts, set interrupt priorities and indicate interrupt requests for all of the interrupts other than the Watchdog Timer interrupt, the primary oscillator fail trap and the Watchdog Oscillator fail trap interrupts. PS025114-1314 Interrupt Control Register Definitions Z8 Encore!® F0830 Series Product Specification 58 Interrupt Request 0 Register The Interrupt Request 0 (IRQ0) Register, shown in Table 35 stores the interrupt requests for both vectored and polled interrupts. When a request is sent to the Interrupt Controller, the corresponding bit in the IRQ0 Register becomes 1. If interrupts are globally enabled (vectored interrupts), the Interrupt Controller passes an interrupt request to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 0 Register to determine if any interrupt requests are pending. Table 35. Interrupt Request 0 Register (IRQ0) Bit Field RESET R/W 7 6 5 Reserved T1I T0I 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address 4 3 2 1 Reserved 0 ADCI FC0h Bit Description [7] Reserved This bit is reserved and must be programmed to 0. [6] T1I Timer 1 Interrupt Request 0 = No interrupt request is pending for timer 1. 1 = An interrupt request from timer 1 is awaiting service. [5] T0I Timer 0 Interrupt Request 0 = No interrupt request is pending for timer 0. 1 = An interrupt request from timer 0 is awaiting service. [4:1] Reserved These registers are reserved and must be programmed to 0000. [0] ADCI ADC Interrupt Request 0 = No interrupt request is pending for the analog-to-digital converter. 1 = An interrupt request from the analog-to-digital converter is awaiting service. PS025114-1314 Interrupt Control Register Definitions Z8 Encore!® F0830 Series Product Specification 59 Interrupt Request 1 Register The Interrupt Request 1 (IRQ1) Register, shown in Table 36, stores interrupt requests for both vectored and polled interrupts. When a request is sent to the Interrupt Controller, the corresponding bit in the IRQ1 Register becomes 1. If interrupts are globally enabled (vectored interrupts), the Interrupt Controller passes an interrupt request to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1 Register to determine if any interrupt requests are pending. Table 36. Interrupt Request 1 Register (IRQ1) Bit Field RESET R/W 7 6 5 4 3 2 1 0 PA7I PA6CI PA5I PA4I PA3I PA2I PA1I PA0I 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FC3h Bit Description [7] PA7I Port A7 0 = No interrupt request is pending for GPIO Port A. 1 = An interrupt request from GPIO Port A. [6] PA6CI Port A6 or Comparator Interrupt Request 0 = No interrupt request is pending for GPIO Port A or comparator. 1 = An interrupt request from GPIO Port A or comparator. [5] PAxI Port A Pin x Interrupt Request 0 = No interrupt request is pending for GPIO Port A pin x. 1 = An interrupt request from GPIO Port A pin x is awaiting service. Note: x indicates the specific GPIO port pin number (5–0). PS025114-1314 Interrupt Control Register Definitions Z8 Encore!® F0830 Series Product Specification 60 Interrupt Request 2 Register The Interrupt Request 2 (IRQ2) Register, shown in Table 37, stores interrupt requests for both vectored and polled interrupts. When a request is sent to the Interrupt Controller, the corresponding bit in the IRQ2 Register becomes 1. If interrupts are globally enabled (vectored interrupts), the Interrupt Controller passes an interrupt request to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 2 Register to determine if any interrupt requests are pending. Table 37. Interrupt Request 2 Register (IRQ2) Bit 7 6 Field RESET R/W 5 4 Reserved 3 2 1 0 PC3I PC2I PC1I PC0I 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FC6h Bit Description [7:4] Reserved These registers are reserved and must be programmed to 0000. [3] PCxI Port C Pin x Interrupt Request 0 = No interrupt request is pending for GPIO Port C pin x. 1 = An interrupt request from GPIO Port C pin x is awaiting service. Note: x indicates the specific GPIO port pin number (3–0). IRQ0 Enable High and Low Bit Registers Table 38 lists the priority control values for IRQ0. The IRQ0 Enable High and Low Bit registers, shown in Tables 39 and 40, form a priority-encoded enabling service for interrupts in the Interrupt Request 0 Register. Priority is generated by setting the bits in each register. Table 38. IRQ0 Enable and Priority Encoding IRQ0ENH[x] IRQ0ENL[x] Priority Description 0 0 Disabled Disabled 0 1 Level 1 Low 1 0 Level 2 Nominal 1 1 Level 3 High Note: x indicates the register bits in the range 7–0. PS025114-1314 Interrupt Control Register Definitions Z8 Encore!® F0830 Series Product Specification 61 Table 39. IRQ0 Enable High Bit Register (IRQ0ENH) Bit Field RESET R/W 7 6 5 4 3 2 1 Reserved T1ENH T0ENH 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 1 0 Reserved Address 0 ADCENH FC1h Bit Description [7] Reserved This bit is reserved and must be programmed to 0. [6] T1ENH Timer 1 Interrupt Request Enable High Bit [5] T0ENH Timer 0 Interrupt Request Enable High Bit [4:1] Reserved These registers are reserved and must be programmed to 0000. [0] ADC Interrupt Request Enable High Bit ADCENH Table 40. IRQ0 Enable Low Bit Register (IRQ0ENL) Bit 7 6 5 Reserved T1ENL T0ENL RESET 0 0 0 0 0 0 0 0 R/W R R/W R/W R/W R/W R R R/W Field 4 3 2 Reserved Address ADCENL FC2h Bit Description [7] Reserved This bit is reserved and must be programmed to 0. [6] T1ENL Timer 1 Interrupt Request Enable Low Bit [5] T0ENL Timer 0 Interrupt Request Enable Low Bit [4:1] Reserved These registers are reserved and must be programmed to 0000. [0] ADC Interrupt Request Enable Low Bit ADCENL PS025114-1314 Interrupt Control Register Definitions Z8 Encore!® F0830 Series Product Specification 62 IRQ1 Enable High and Low Bit Registers Table 41 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit registers, shown in Tables 42 and 43, form a priority-encoded enabling service for interrupts in the Interrupt Request 1 Register. Priority is generated by setting the bits in each register. Table 41. IRQ1 Enable and Priority Encoding IRQ1ENH[x] IRQ1ENL[x] Priority Description 0 0 Disabled Disabled 0 1 Level 1 Low 1 0 Level 2 Nominal 1 1 Level 3 High Note: x indicates register bits in the address range 7–0. Table 42. IRQ1 Enable High Bit Register (IRQ1ENH) Bit Field RESET R/W 7 6 5 PA7ENH PA6CENH PA5ENH 4 3 2 1 0 PA4ENH PA3ENH PA2ENH PA1ENH PA0ENH 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FC4h Bit Description [7] PA7ENH Port A Bit[7] Interrupt Request Enable High Bit [6] PA6CENH Port A Bit[7] or Comparator Interrupt Request Enable High Bit [5:0] PAxENH Port A Bit[x] Interrupt Request Enable High Bit See the interrupt port select register for selection of either Port A or Port D as the interrupt source. Note: x indicates register bits in the address range 5–0. PS025114-1314 Interrupt Control Register Definitions Z8 Encore!® F0830 Series Product Specification 63 Table 43. IRQ1 Enable Low Bit Register (IRQ1ENL) Bit Field RESET R/W 7 6 5 4 3 2 1 0 PA7ENL PA6CENL PA5ENL PA4ENL PA3ENL PA2ENL PA1ENL PA0ENL 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FC5h Bit Description [7] PA7ENL Port A Bit[7] Interrupt Request Enable Low Bit [6] PA6CENL Port A Bit[7] or Comparator Interrupt Request Enable Low Bit [5:0] PAxENL Port A Bit[x] Interrupt Request Enable Low Bit See the interrupt port select register for selection of either Port A or Port D as the interrupt source. Note: x indicates register bits in the address range 5–0. IRQ2 Enable High and Low Bit Registers Table 44 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit registers, shown in Tables 45 and 46, form a priority-encoded enabling service for interrupts in the Interrupt Request 2 Register. Priority is generated by setting the bits in each register. Table 44. IRQ2 Enable and Priority Encoding IRQ2ENH[x] IRQ2ENL[x] Priority Description 0 0 Disabled Disabled 0 1 Level 1 Low 1 0 Level 2 Nominal 1 1 Level 3 High Note: x indicates register bits in the address range 7–0. PS025114-1314 Interrupt Control Register Definitions Z8 Encore!® F0830 Series Product Specification 64 Table 45. IRQ2 Enable High Bit Register (IRQ2ENH) Bit 7 6 Field RESET R/W 5 4 Reserved 3 2 1 0 C3ENH C2ENH C1ENH C0ENH 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FC7h Bit Description [7:4] Reserved These registers are reserved and must be programmed to 0000. [3] C3ENH Port C3 Interrupt Request Enable High Bit [2] C2ENH Port C2 Interrupt Request Enable High Bit [1] C1ENH Port C1 Interrupt Request Enable High Bit [0] C0ENH Port C0 Interrupt Request Enable High Bit Table 46. IRQ2 Enable Low Bit Register (IRQ2ENL) Bit 7 6 Field RESET R/W 5 4 Reserved 3 2 1 0 C3ENL C2ENL C1ENL C0ENL 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FC8h Bit Description [7:4] Reserved These registers are reserved and must be programmed to 0000. [3] C3ENL Port C3 Interrupt Request Enable Low Bit [2] C2ENL Port C2 Interrupt Request Enable Low Bit [1] C1ENL Port C1 Interrupt Request Enable Low Bit [0] C0ENL Port C0 Interrupt Request Enable Low Bit PS025114-1314 Interrupt Control Register Definitions Z8 Encore!® F0830 Series Product Specification 65 Interrupt Edge Select Register The interrupt edge select (IRQES) register determines whether an interrupt is generated for the rising edge or falling edge on the selected GPIO Port A or Port D input pin. See Table 47. Table 47. Interrupt Edge Select Register (IRQES) Bit Field RESET R/W 7 6 5 4 3 2 1 0 IES7 IES6 IES5 IES4 IES3 IES2 IES1 IES0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FCDh Bit Description [7] IESx Interrupt Edge Select x 0 = An interrupt request is generated on the falling edge of the PAx input or PDx. 1 = An interrupt request is generated on the rising edge of the PAx input or PDx. Note: x indicates register bits in the address range 7–0. PS025114-1314 Interrupt Control Register Definitions Z8 Encore!® F0830 Series Product Specification 66 Shared Interrupt Select Register The shared interrupt select (IRQSS) register determines the source of the PADxS interrupts. See Table 48. The shared interrupt select register selects between Port A and alternate sources for the individual interrupts. Because these shared interrupts are edge-triggered, it is possible to generate an interrupt just by switching from one shared source to another. For this reason, an interrupt must be disabled before switching between sources. Table 48. Shared Interrupt Select Register (IRQSS) Bit Field RESET R/W 7 6 Reserved PA6CS 0 0 0 0 R/W R/W R/W R/W Address 5 4 3 2 1 0 0 0 0 0 R/W R/W R/W R/W Reserved FCEh Bit Description [7] Reserved This bit is reserved and must be programmed to 0. [6] PA6CS PA6/Comparator Selection 0 = PA6 is used for the interrupt caused by PA6CS interrupt request. 1 = The comparator is used for the interrupt caused by PA6CS interrupt request. [5:0] Reserved These registers are reserved and must be programmed to 000000. PS025114-1314 Interrupt Control Register Definitions Z8 Encore!® F0830 Series Product Specification 67 Interrupt Control Register The Interrupt Control (IRQCTL) Register, shown in Table 49, contains the master enable bit for all interrupts. Table 49. Interrupt Control Register (IRQCTL) Bit Field RESET R/W 7 6 5 4 IRQE 3 2 1 0 Reserved 0 0 0 0 0 0 0 0 R/W R R R R R R R Address FCFh Bit Description [7] IRQE Interrupt Request Enable This bit is set to 1 by executing an Enable Interrupts (EI) or Interrupt Return (IRET) instruction or by a direct register write of 1 to this bit. It is reset to 0 by executing a DI instruction, eZ8 CPU acknowledgement of an interrupt request, reset, or by a direct register write of a 0 to this bit. 0 = Interrupts are disabled. 1 = Interrupts are enabled. [6:0] Reserved These registers are reserved and must be programmed to 0000000. PS025114-1314 Interrupt Control Register Definitions Z8 Encore!® F0830 Series Product Specification 68 Timers The Z8 Encore! F0830 Series products contain up to two 16-bit reloadable timers that can be used for timing, event counting or generation of pulse width modulated (PWM) signals. The timers feature include: • • • • • 16-bit reload counter • • Timer output pin Programmable prescaler with prescale values ranging from 1 to 128 PWM output generation Capture and compare capability External input pin for timer input, clock gating or capture signal. External input pin signal frequency is limited to a maximum of one-fourth the system clock frequency Timer interrupt Architecture Figure 10 displays the architecture of the timers. PS025114-1314 Timers Z8 Encore!® F0830 Series Product Specification 69 Timer Block Block Control 16-Bit Reload Register System Clock Compare Timer Control Data Bus Interrupt, PWM, and Timer Output Control Timer Input Gate Input 16-Bit PWM/Compare Compare 16-Bit Counter with Prescaler Timer Interrupt Timer Output Timer Output Complement Capture Input Figure 10. Timer Block Diagram Operation The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value 0001h into the Timer Reload High and Low Byte registers and setting the prescale value to 1. Maximum time-out delay is set by loading the value 0000h into the Timer Reload High and Low Byte registers and setting the prescale value to 128. If the Timer reaches FFFFh, the timer resets back to 0000h and continues counting. Timer Operating Modes The timers can be configured to operate in the following modes: ONE-SHOT Mode In ONE-SHOT Mode, the timer counts up to the 16-bit reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the reload value, the timer generates an interrupt and the count value in the Timer High and Low Byte registers is reset to 0001h. The timer is automatically disabled and stops counting. Additionally, if the timer output alternate function is enabled, the timer output pin changes state for one system clock cycle (from Low to High or from High to Low) upon timer PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 70 reload. For the timer output to make a state change at a ONE-SHOT time-out (rather than a single cycle pulse), first set the TPOL bit in the Timer Control Register to the start value before enabling ONE-SHOT Mode. After starting the timer, set TPOL to the opposite bit value. Observe the following steps for configuring a timer for ONE-SHOT Mode and for initiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for ONE-SHOT Mode – Set the prescale value – Set the initial output level (High or Low) if using the timer output Alternate function 2. Write to the Timer High and Low Byte registers to set the starting count value. 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the timer output function, configure the associated GPIO port pin for the timer output alternate function. 6. Write to the Timer Control Register to enable the timer and initiate counting. In ONE-SHOT Mode, the system clock always provides the timer input. The timer period is calculated with the following equation:  Reload Value – Start Value   Prescale One-Shot Mode Time-Out Period (s) = ------------------------------------------------------------------------------------------------System Clock Frequency (Hz) CONTINUOUS Mode In CONTINUOUS Mode, the timer counts up to the 16-bit reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h and the counting resumes. Additionally, if the timer output alternate function is enabled, the timer output pin changes state (from Low to High or from High to Low) at timer reload. Observe the following steps for configuring a timer for CONTINUOUS Mode and for initiating the count: 1. Write to the Timer Control Register to: PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 71 – – – – Disable the timer Configure the timer for CONTINUOUS Mode Set the prescale value If using the timer output Alternate function, set the initial output level (High or Low) 2. Write to the Timer High and Low Byte registers to set the starting count value (usually 0001h). This action only affects the first pass in CONTINUOUS Mode. After the first timer reload in CONTINUOUS Mode, counting always begins at the reset value of 0001h. 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. Enable the timer interrupt (if appropriate) and set the timer interrupt priority by writing to the relevant interrupt registers. 5. Configure the associated GPIO port pin (if using the timer output function) for the timer output alternate function. 6. Write to the Timer Control Register to enable the timer and initiate counting. In CONTINUOUS Mode, the system clock always provides the timer input. The timer period is calculated with the following equation: Reload Value  Prescale Continuous Mode Time-Out Period (s) = -----------------------------------------------------------------------System Clock Frequency (Hz) If an initial starting value other than 0001h is loaded into the Timer High and Low Byte registers, use the ONE-SHOT Mode equation to determine the first time-out period. COUNTER Mode In COUNTER Mode, the timer counts input transitions from a GPIO port pin. The timer input is taken from the GPIO port pin: timer input alternate function. The TPOL bit in the Timer Control Register determines whether the count occurs on the rising edge or the falling edge of the timer input signal. In COUNTER Mode, the prescaler is disabled. Caution: The input frequency of the timer input signal must not exceed one-fourth the system clock frequency. Upon reaching the reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h and counting resumes. Additionally, if the timer output alternate function PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 72 is enabled, the timer output pin changes state (from Low to High or from High to Low) at timer reload. Observe the following steps for configuring a timer for COUNTER Mode and for initiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for COUNTER Mode – Select either the rising edge or falling edge of the timer input signal for the count. This selection also sets the initial logic level (High or Low) for the timer output alternate function. However, the timer output function is not required to be enabled. 2. Write to the Timer High and Low Byte registers to set the starting count value. This only affects the first pass in COUNTER Mode. After the first timer reload in COUNTER Mode, counting always begins at the reset value 0001h. In COUNTER Mode, the Timer High and Low Byte registers must be written with the value 0001h. 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. Configure the associated GPIO port pin for the timer input alternate function. 6. If using the timer output function, configure the associated GPIO port pin for the timer output alternate function. 7. Write to the Timer Control Register to enable the timer. In COUNTER Mode, the number of timer input transitions is calculated with the following equation: Counter Mode Timer Input Transitions = Current Count Value – Start Value COMPARATOR COUNTER Mode In COMPARATOR COUNTER Mode, the timer counts the input transitions from the analog comparator output. The TPOL bit in the Timer Control Register determines whether the count occurs on the rising edge or the falling edge of the comparator output signal. In COMPARATOR COUNTER Mode, the prescaler is disabled. PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 73 Caution: The frequency of the comparator output signal must not exceed one-fourth the system clock frequency. After reaching the reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h and counting resumes. Additionally, if the timer output alternate function is enabled, the timer output pin changes state (from Low to High or from High to Low) at timer reload. Observe the following steps for configuring a timer for COMPARATOR COUNTER Mode and for initiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for COMPARATOR COUNTER Mode. – Select either the rising edge or falling edge of the comparator output signal for the count. This also sets the initial logic level (High or Low) for the timer output alternate function. However, the timer output function is not required to be enabled. 2. Write to the Timer High and Low Byte registers to set the starting count value. This action only affects the first pass in COMPARATOR COUNTER Mode. After the first timer reload in COMPARATOR COUNTER Mode, counting always begins at the reset value 0001h. Generally, in COMPARATOR COUNTER Mode, the Timer High and Low Byte registers must be written with the value 0001h. 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the timer output function, configure the associated GPIO port pin for the timer output alternate function. 6. Write to the Timer Control Register to enable the timer. In COMPARATOR COUNTER Mode, the number of comparator output transitions is calculated with the following equation: Comparator Output Transitions = Current Count Value – Start Value PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 74 PWM SINGLE OUTPUT Mode In PWM SINGLE OUTPUT Mode, the timer outputs a pulse width modulated (PWM) output signal through a GPIO port pin. The timer input is the system clock. The timer first counts up to 16-bit PWM match value stored in the timer PWM High and Low Byte registers. When the timer count value matches the PWM value, the timer output toggles. The timer continues counting until it reaches the reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h and counting resumes. If the TPOL bit in the Timer Control Register is set to 1, the timer output signal begins as a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The timer output signal returns to a High (1) after the timer reaches the reload value and is reset to 0001h. If the TPOL bit in the Timer Control Register is set to 0, the timer output signal begins as a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The timer output signal returns to a Low (0) after the timer reaches the reload value and is reset to 0001h. Observe the following steps for configuring a timer for PWM SINGLE OUTPUT Mode and for initiating PWM operation: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for PWM Mode – Set the prescale value – Set the initial logic level (High or Low) and PWM High/Low transition for the timer output alternate function 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001h). This value only affects the first pass in PWM Mode. After the first timer reset in PWM Mode, counting always begins at the reset value of 0001h. 3. Write to the PWM High and Low Byte registers to set the PWM value. 4. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM period). The reload value must be greater than the PWM value. 5. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 6. Configure the associated GPIO port pin for the timer output alternate function. 7. Write to the Timer Control Register to enable the timer and initiate counting. The PWM period is represented by the following equation: PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 75 Reload Value  Prescale PWM Period (s) = -----------------------------------------------------------------------System Clock Frequency (Hz) If an initial starting value other than 0001h is loaded into the Timer High and Low Byte registers, use the ONE-SHOT Mode equation to determine the first PWM time-out period. If TPOL bit is set to 0, the ratio of the PWM output high time to the total period is represented by: Reload Value – PWM Value PWM Output High Time Ratio (%) = ---------------------------------------------------------------------  100 Reload Value If TPOL bit is set to 1, the ratio of the PWM output high time to the total period is represented by: PWM Value PWM Output High Time Ratio (%) = --------------------------------  100 Reload Value PWM DUAL OUTPUT Mode In PWM DUAL OUTPUT Mode, the timer outputs a PWM output signal pair (basic PWM signal and its complement) through two GPIO port pins. The timer input is the system clock. The timer first counts up to 16-bit PWM match value stored in the timer PWM High and Low Byte registers. When the timer count value matches the PWM value, the timer output toggles. The timer continues counting until it reaches the reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h and counting resumes. If the TPOL bit in the Timer Control Register is set to 1, the timer output signal begins as a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The timer output signal returns to a High (1) after the timer reaches the reload value and is reset to 0001h. If the TPOL bit in the Timer Control Register is set to 0, the timer output signal begins as a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The timer output signal returns to a Low (0) after the timer reaches the reload value and is reset to 0001h. The timer also generates a second PWM output signal: the timer output complement. The timer output complement is the complement of the timer output PWM signal. A programmable deadband delay can be configured to time delay (0 to 128 system clock cycles) PWM output transitions on these two pins from a Low to a High (inactive to active) to ensure a time gap between the deassertion of one PWM output to the assertion of its complement. PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 76 Observe the following steps for configuring a timer for PWM DUAL OUTPUT Mode and for initiating the PWM operation: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for PWM DUAL OUTPUT Mode; setting the mode also involves writing to TMODEHI bit in the TxCTL1 Register – Set the prescale value – Set the initial logic level (High or Low) and PWM High/Low transition for the timer output alternate function 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001h). This write only affects the first pass in PWM Mode. After the first timer reset in PWM Mode, counting always begins at the reset value of 0001h. 3. Write to the PWM High and Low Byte registers to set the PWM value. 4. Write to the PWM Control Register to set the PWM deadband delay value. The deadband delay must be less than the duration of the positive phase of the PWM signal (as defined by the PWM High and Low Byte registers). It must also be less than the duration of the negative phase of the PWM signal (as defined by the difference between the PWM registers and the Timer Reload registers). 5. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM period). The reload value must be greater than the PWM value. 6. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 7. Configure the associated GPIO port pin for the timer output and timer output complement alternate functions. The timer output complement function is shared with the timer input function for both timers. Setting the timer mode to DUAL PWM will automatically switch the function from timer-in to timer-out complement. 8. Write to the Timer Control Register to enable the timer and initiate counting. The PWM period is represented by the following equation: Reload Value  Prescale PWM Period (s) = -----------------------------------------------------------------------System Clock Frequency (Hz) If an initial starting value other than 0001h is loaded into the Timer High and Low Byte registers, the ONE-SHOT Mode equation determines the first PWM time-out period. If TPOL is set to 0, the ratio of the PWM output high time to the total period is represented by: PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 77 Reload Value – PWM Value PWM Output High Time Ratio (%) = ---------------------------------------------------------------------  100 Reload Value If TPOL is set to 1, the ratio of the PWM output high time to the total period is represented by: PWM Value PWM Output High Time Ratio (%) = --------------------------------  100 Reload Value CAPTURE Mode In CAPTURE Mode, the current timer count value is recorded when the appropriate external timer input transition occurs. The capture count value is written to the timer PWM High and Low Byte registers. The timer input is the system clock. The TPOL bit in the Timer Control Register determines if the capture occurs on a rising edge or a falling edge of the timer input signal. When the capture event occurs, an interrupt is generated and the timer continues counting. The INPCAP bit in the TxCTL1 Register is set to indicate the timer interrupt because of an input capture event. The timer continues counting up to the 16-bit reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an interrupt and continues counting. The INPCAP bit in the TxCTL1 Register clears, indicating that the timer interrupt has not occurred because of an input capture event. Observe the following steps for configuring a timer for CAPTURE Mode and initiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for CAPTURE Mode – Set the prescale value – Set the capture edge (rising or falling) for the timer input 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001h). 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. Clear the timer PWM High and Low Byte registers to 0000h. Clearing these registers allows user software to determine if interrupts were generated either by a capture event or by a reload. If the PWM High and Low Byte registers still contain 0000h after the interrupt, the interrupt were generated by a reload. PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 78 5. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input capture and Reload events. If appropriate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting the TICONFIG field of the TxCTL1 Register. 6. Configure the associated GPIO port pin for the timer input alternate function. 7. Write to the Timer Control Register to enable the timer and initiate counting. In CAPTURE Mode, the elapsed time between the timer start and the capture event can be calculated using the following equation: Capture Value – Start Value   PrescaleCapture Elapsed Time (s) = -------------------------------------------------------------------------------------------------System Clock Frequency (Hz) CAPTURE RESTART Mode In CAPTURE RESTART Mode, the current timer count value is recorded when the acceptable external timer input transition occurs. The capture count value is written to the timer PWM High and Low Byte registers. The timer input is the system clock. The TPOL bit in the Timer Control Register determines whether the capture occurs on a rising edge or a falling edge of the timer input signal. When the capture event occurs, an interrupt is generated and the count value in the Timer High and Low Byte registers is reset to 0001h and counting resumes. The INPCAP bit in the TxCTL1 Register is set to indicate that the timer interrupt has been caused by an input capture event. If no capture event occurs, the timer counts up to 16-bit compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h and counting resumes. The INPCAP bit in the TxCTL1 Register is cleared to indicate that the timer interrupt has not been caused by an input capture event. Observe the following steps for configuring a timer for CAPTURE RESTART Mode and for initiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for CAPTURE RESTART Mode; setting the mode also involves writing to TMODEHI bit in the TxCTL1 Register – Set the prescale value – Set the capture edge (rising or falling) for the timer input 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001h). PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 79 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. Clear the timer PWM High and Low Byte registers to 0000h. This allows user software to determine if interrupts are generated by either a capture event or a reload. If the PWM High and Low Byte registers still contain 0000h after the interrupt, the interrupt were generated by a reload. 5. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input capture and Reload events. The user can configure the timer interrupt to be generated only at the input capture event or the reload event by setting the TICONFIG field of the TxCTL1 Register. 6. Configure the associated GPIO port pin for the timer input alternate function. 7. Write to the Timer Control Register to enable the timer and initiate counting. In CAPTURE Mode, the elapsed time between the timer start and the capture event can be calculated using the following equation:  Capture Value – Start Value   Prescale Capture Elapsed Time (s) = --------------------------------------------------------------------------------------------------System Clock Frequency (Hz) COMPARE Mode In COMPARE Mode, the timer counts up to 16-bit maximum compare value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the compare value, the timer generates an interrupt and counting continues (the timer value is not reset to 0001h). Additionally, if the timer output alternate function is enabled, the timer output pin changes state (from Low to High or from High to Low) upon compare. If the timer reaches FFFFh, the timer resets to 0000h and continues counting. Observe the following steps for configuring a timer for COMPARE Mode and for initiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for COMPARE Mode – Set the prescale value – Set the initial logic level (High or Low) for the timer output alternate function 2. Write to the Timer High and Low Byte registers to set the starting count value. 3. Write to the Timer Reload High and Low Byte registers to set the compare value. PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 80 4. Enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the timer output function, configure the associated GPIO port pin for the timer output alternate function. 6. Write to the Timer Control Register to enable the timer and initiate counting. In COMPARE Mode, the system clock always provides the timer input. The compare time can be calculated by the following equation:  Compare Value – Start Value   Prescale Compare Mode Time (s) = -----------------------------------------------------------------------------------------------------System Clock Frequency (Hz) GATED Mode In GATED Mode, the timer counts only when the timer input signal is in its active state (asserted), as determined by the TPOL bit in the Timer Control Register. When the timer input signal is asserted, counting begins. A timer interrupt is generated when the timer input signal is deasserted or a timer reload occurs. To determine whether the timer input signal deassertion generated the interrupt, read the associated GPIO input value and compare to the value stored in the TPOL bit. The timer counts up to the 16-bit reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h and counting resumes (assuming the timer input signal remains asserted). Additionally, if the timer output alternate function is enabled, the timer output pin changes state (from Low to High or from High to Low) at timer reset. Observe the following steps for configuring a timer for GATED Mode and for initiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for GATED Mode – Set the prescale value 2. Write to the Timer High and Low Byte registers to set the starting count value. Writing these registers only affects the first pass in GATED Mode. After the first timer reset in GATED Mode, counting always begins at the reset value of 0001h. 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. Enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input deasser- PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 81 tion and reload events. The user can configure the timer interrupt to be generated only at the input deassertion event or the reload event by setting the TICONFIG field of the TxCTL1 Register. 5. Configure the associated GPIO port pin for the timer input alternate function. 6. Write to the Timer Control Register to enable the timer. 7. Assert the timer input signal to initiate the counting. CAPTURE/COMPARE Mode In CAPTURE/COMPARE Mode, the timer begins counting on the first external timer input transition. The acceptable transition (rising edge or falling edge) is set by the TPOL bit in the Timer Control Register. The timer input is the system clock. Every subsequent acceptable transition (after the first) of the timer input signal, captures the current count value. The capture value is written to the timer PWM High and Low Byte registers. When the capture event occurs, an interrupt is generated, the count value in the Timer High and Low Byte registers is reset to 0001h and the counting resumes. The INPCAP bit in the TxCTL1 Register is set to indicate that the timer interrupt is caused by an input capture event. If no capture event occurs, the timer counts up to the 16-bit compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the compare value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h and counting resumes. The INPCAP bit in the TxCTL1 Register is cleared to indicate that the timer interrupt has not been caused by an input capture event. Observe the following steps for configuring a timer for CAPTURE/COMPARE Mode and for initiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for CAPTURE/COMPARE Mode. – Set the prescale value. – Set the capture edge (rising or falling) for the timer input. 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001h). 3. Write to the Timer Reload High and Low Byte registers to set the compare value. 4. Enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers.By default, the timer interrupt are generated for both input capture and Reload events. The user can configure the timer interrupt to be generated only at the input capture event or the reload event by setting TICONFIG field of the TxCTL1 Register. 5. Configure the associated GPIO port pin for the timer input alternate function. PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 82 6. Write to the Timer Control Register to enable the timer. 7. Counting begins on the first appropriate transition of the timer input signal. No interrupt is generated by the first edge. In CAPTURE/COMPARE Mode, the elapsed time from timer start to capture event can be calculated using the following equation:  Capture Value – Start Value   Prescale Capture Elapsed Time (s) = --------------------------------------------------------------------------------------------------System Clock Frequency (Hz) Reading the Timer Count Values The current count value in the timers can be read while counting (enabled). This capability has no effect on Timer operation. When the timer is enabled and the Timer High Byte Register is read, the contents of the timer low byte register are placed in a holding register. A subsequent read from the timer low byte register returns the value in the holding register. This operation allows accurate reads of the full 16-bit timer count value when enabled. When the timers are not enabled, a read from the timer low byte register returns the actual value in the counter. Timer Pin Signal Operation Timer output is a GPIO port pin alternate function. The timer output is toggled every time the counter is reloaded. The timer input can be used as a selectable counting source. It shares the same pin as the complementary timer output. When selected by the GPIO alternate function registers, this pin functions as a timer input in all modes except for the DUAL PWM OUTPUT Mode. For this mode, no timer input is available. PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 83 Timer Control Register Definitions This section defines the features of the following Timer Control registers. Timer 0–1 High and Low Byte Registers: see page 83 Timer Reload High and Low Byte Registers: see page 85 Timer 0–1 PWM High and Low Byte Registers: see page 86 Timer 0–1 Control Registers: see page 87 Timer 0–1 High and Low Byte Registers The Timer 0–1 High and Low Byte (TxH and TxL) registers, shown in Tables 50 and 51, contain the current 16-bit timer count value. When the timer is enabled, a read from TxH causes the value in TxL to be stored in a temporary holding register. A read from TxL always returns this temporary register content when the timer is enabled; however, when the timer is disabled, a read from the TxL reads the TxL Register content directly. Writing to the Timer High and Low Byte registers while the timer is enabled is not recommended. There are no temporary holding registers available for write operations; therefore, simultaneous 16-bit writes are not possible. If either the timer High or Low Byte registers are written during counting, the 8-bit written value is placed in the counter (High or Low byte) at the next clock edge. The counter continues counting from the new value. Table 50. Timer 0–1 High Byte Register (TxH) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 TH 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address F00h, F08h Table 51. Timer 0–1 Low Byte Register (TxL) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 TL 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W Address PS025114-1314 F01h, F09h Timer Control Register Definitions Z8 Encore!® F0830 Series Product Specification 84 Bit Description [7:0] TH, TL Timer High and Low Bytes These 2 bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value. PS025114-1314 Timer Control Register Definitions Z8 Encore!® F0830 Series Product Specification 85 Timer Reload High and Low Byte Registers The Timer 0–1 Reload High and Low Byte (TxRH and TxRL) registers, shown in Tables 52 and 53, store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer Reload High Byte Register are stored in a temporary holding register. When a write to the Timer Reload Low Byte Register occurs, the temporary holding register value is written to the Timer High Byte Register. This operation allows simultaneous updates of the 16-bit timer reload value. In COMPARE Mode, the Timer Reload High and Low Byte registers store the 16-bit compare value. Table 52. Timer 0–1 Reload High Byte Register (TxRH) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 TRH 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Address F02h, F0Ah Table 53. Timer 0–1 Reload Low Byte Register (TxRL) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 TRL 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Address F03h, F0Bh Bit Description [7:0] TRH, TRL Timer Reload Register High and Low These two bytes form the 16-bit reload value, {TRH[7:0], TRL[7:0]}. This value sets the maximum count value, which initiates a timer reload to 0001h. In COMPARE Mode, these two bytes form the 16-bit compare value. PS025114-1314 Timer Control Register Definitions Z8 Encore!® F0830 Series Product Specification 86 Timer 0–1 PWM High and Low Byte Registers The Timer 0–1 PWM High and Low Byte (TxPWMH and TxPWML) registers, shown in Tables 54 and 55, control PWM operations. These registers also store the capture values for the CAPTURE and CAPTURE/COMPARE modes. Table 54. Timer 0–1 PWM High Byte Register (TxPWMH) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 PWMH 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address F04h, F0Ch Table 55. Timer 0–1 PWM Low Byte Register (TxPWML) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 PWML 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address F05h, F0Dh Bit Description [7:0] PWMH, PWML Pulse Width Modulator High and Low Bytes These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the current 16-bit timer count. When a match occurs, the PWM output changes state. The PWM output value is set by the TPOL bit in the Timer Control Register (TxCTL1). The TxPWMH and TxPWML registers also store the 16-bit captured timer value when operating in capture or CAPTURE/COMPARE modes. PS025114-1314 Timer Control Register Definitions Z8 Encore!® F0830 Series Product Specification 87 Timer 0–1 Control Registers The Timer Control registers are 8-bit read/write registers that control the operation of their associated counter/timers. Time 0–1 Control Register 0 The Timer Control 0 (TxCTL0) and Timer Control 1 (TxCTL1) registers determine the timer operating mode. These registers also include a programmable PWM deadband delay, two bits to configure the timer interrupt definition, and a status bit to identify if the most recent timer interrupt is caused by an input capture event. Table 56. Timer 0–1 Control Register 0 (TxCTL0) Bit Field RESET R/W 7 TMODEHI 6 5 TICONFIG 4 3 Reserved 2 1 PWMD 0 INPCAP 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address F06h, F0Eh Bit Description [7] TMODEHI Timer Mode High Bit This bit along with the TMODE field in the TxCTL1 Register determines the operating mode of the timer. This is the most significant bit of the timer mode selection value. See the TxCTL1 Register description on the next page for additional details. [6:5] TICONFIG Timer Interrupt Configuration This field configures timer interrupt definition. 0x = Timer interrupt occurs on all of the defined reload, compare and input events. 10 = Timer interrupt occurs only on defined input capture/deassertion events. 11 = Timer interrupt occurs only on defined reload/compare events. [4] Reserved This bit is reserved and must be programmed to 0. [3:1] PWMD PWM Delay Value This field is a programmable delay to control the number of system clock cycles delay before the timer output and the timer output complement are forced to their Active state. 000 = No delay. 001 = 2 cycles delay. 010 = 4 cycles delay. 011 = 8 cycles delay. 100 = 16 cycles delay. 101 = 32 cycles delay. 110 = 64 cycles delay. 111 = 128 cycles delay. PS025114-1314 Timer Control Register Definitions Z8 Encore!® F0830 Series Product Specification 88 Bit Description (Continued) [0] INPCAP Input Capture Event This bit indicates whether the most recent timer interrupt is caused by a timer input capture event. 0 = Previous timer interrupt is not caused by timer input capture event. 1 = Previous timer interrupt is caused by timer input capture event. Timer 0–1 Control Register 1 The Timer 0–1 Control (TxCTL1) registers enable/disable the timers, set the prescaler value, and determine the timer operating mode. Table 57. Timer 0–1 Control Register 1 (TxCTL1) Bit Field RESET R/W 7 6 5 4 3 2 TEN TPOL 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PRES Address 1 0 TMODE F07h, F0Fh Bit Description [7] TEN Timer Enable 0 = Timer is disabled. 1 = Timer enabled to count. PS025114-1314 Timer Control Register Definitions Z8 Encore!® F0830 Series Product Specification 89 Bit Description (Continued) [6] TPOL Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer. ONE-SHOT Mode When the timer is disabled, the timer output signal is set to the value of this bit. When the timer is enabled, the timer output signal is complemented on timer reload. CONTINUOUS Mode When the timer is disabled, the timer output signal is set to the value of this bit. When the timer is enabled and reloaded, the timer output signal is complemented. COUNTER Mode If the timer is disabled, the timer output signal is set to the value of this bit. If the timer is enabled the timer output signal is complemented after timer reload. 0 = Count occurs on the rising edge of the timer input signal. 1 = Count occurs on the falling edge of the timer input signal. PWM SINGLE OUTPUT Mode 0 = Timer output is forced Low (0), when the timer is disabled. The timer output is forced High (1) when the timer is enabled and the PWM count matches and the timer output is forced Low (0) when the timer is enabled and reloaded. 1 = Timer output is forced High (1), when the timer is disabled. The timer output is forced low(0), when the timer is enabled and the PWM count matches and forced High (1) when the timer is enabled and reloaded. CAPTURE Mode 0 = Count is captured on the rising edge of the timer input signal. 1 = Count is captured on the falling edge of the timer input signal. COMPARE Mode When the timer is disabled, the timer output signal is set to the value of this bit. When the timer is enabled and reloaded, the timer output signal is complemented. GATED Mode 0 = Timer counts when the timer input signal is High (1) and interrupts are generated on the falling edge of the timer input. 1 = Timer counts when the timer input signal is Low (0) and interrupts are generated on the rising edge of the timer input. CAPTURE/COMPARE Mode 0 = Counting is started on the first rising edge of the timer input signal. The current count is captured on subsequent rising edges of the timer input signal. 1 = Counting is started on the first falling edge of the timer input signal. The current count is captured on subsequent falling edges of the timer input signal. PS025114-1314 Timer Control Register Definitions Z8 Encore!® F0830 Series Product Specification 90 Bit Description (Continued) [6] TPOL (cont’d) PWM DUAL OUTPUT Mode 0 = Timer output is forced Low (0) and timer output complement is forced High (1), when the timer is disabled. When enabled and the PWM count matches, the timer output is forced High (1) and forced Low (0) when enabled and reloaded. When enabled and the PWM count matches, the timer output complement is forced Low (0) and forced High (1) when enabled and reloaded. 1 = Timer output is forced High (1) and timer output complement is forced Low (0) when the timer is disabled. When enabled and the PWM count matches, the timer output is forced Low (0) and forced High (1) when enabled and reloaded.When enabled and the PWM count matches, the timer output complement is forced High (1) and forced Low (0) when enabled and reloaded. The PWMD field in the TxCTL0 register determines an optional added delay on the assertion (Low to High) transition of both timer output and timer output complement for deadband generation. CAPTURE RESTART Mode 0 = Count is captured on the rising edge of the timer input signal. 1 = Count is captured on the falling edge of the timer input signal. COMPARATOR COUNTER Mode When the timer is disabled, the timer output signal is set to the value of this bit. When the timer is enabled, the timer output signal is complemented on timer reload. Caution: When the timer output alternate function TxOUT on a GPIO port pin is enabled, TxOUT will change to whatever state the TPOL bit is in. The timer does not need to be enabled for that to happen. Additionally, the port data direction sub register is not needed to be set to output on TxOUT. Changing the TPOL bit when the timer is enabled and running does not immediately change the polarity TxOUT. [5:3] PRES Prescale Value The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7. The prescaler is reset each time the timer is disabled. This reset ensures proper clock division each time the timer is restarted. 000 = Divide by 1. 001 = Divide by 2. 010 = Divide by 4. 011 = Divide by 8. 100 = Divide by 16. 101 = Divide by 32. 110 = Divide by 64. 111 = Divide by 128. PS025114-1314 Timer Control Register Definitions Z8 Encore!® F0830 Series Product Specification 91 Bit Description (Continued) [2:0] TMODE Timer Mode This field along with the TMODEHI bit in TxCTL0 register determines the operating mode of the timer. TMODEHI is the most significant bit of the timer mode selection value. 0000 = ONE-SHOT Mode. 0001 = CONTINUOUS Mode. 0010 = COUNTER Mode. 0011 = PWM SINGLE OUTPUT Mode. 0100 = CAPTURE Mode. 0101 = COMPARE Mode. 0110 = GATED Mode. 0111 = CAPTURE/COMPARE Mode. 1000 = PWM DUAL OUTPUT Mode. 1001 = CAPTURE RESTART Mode. 1010 = COMPARATOR COUNTER Mode. PS025114-1314 Timer Control Register Definitions Z8 Encore!® F0830 Series Product Specification 92 Watchdog Timer The Watchdog Timer (WDT) protects from corrupted or unreliable software, power faults and other system-level problems which can place the Z8 Encore! F0830 Series devices into unsuitable operating states. The features of the Watchdog Timer include: • • • On-chip RC oscillator A selectable time-out response: reset or interrupt 24-bit programmable time-out value Operation The Watchdog Timer is a retriggerable one-shot timer that resets or interrupts the Z8 Encore! F0830 Series devices when the WDT reaches its terminal count. The WDT uses a dedicated on-chip RC oscillator as its clock source. The WDT operates only in two modes: ON and OFF. Once enabled, it always counts and must be refreshed to prevent a time-out. Perform an enable by executing the WDT instruction or by setting the WDT_AO Flash option bit. The WDT_AO bit forces the WDT to operate immediately on reset, even if a WDT instruction has not been executed. The Watchdog Timer is a 24-bit reloadable downcounter that uses three 8-bit registers in the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is calculated using the following equation: WDT Reload Value WDT Time-out Period (ms) = -----------------------------------------------10 where the WDT reload value is the 24-bit decimal value provided by {WDTU[7:0], WDTH[7:0], WDTL[7:0]} and the typical Watchdog Timer RC oscillator frequency is 10 KHz. The Watchdog Timer cannot be refreshed after it reaches 000002h. The WDT reload value must not be set to values below 000004h. Table 58 provides information about approximate time-out delays for the minimum and maximum WDT reload values. Table 58. Watchdog Timer Approximate Time-Out Delays Approximate Time-Out Delay (with 10 KHz Typical WDT Oscillator Frequency) WDT Reload Value (Hex) WDT Reload Value (Decimal) 000004 4 400 µs Minimum time-out delay 000400 1024 102 ms Default time-out delay FFFFFF 16,777,215 28 minutes PS025114-1314 Typical Description Maximum time-out delay Watchdog Timer Z8 Encore!® F0830 Series Product Specification 93 Watchdog Timer Refresh Upon first enable, the Watchdog Timer is loaded with the value in the Watchdog Timer Reload registers. The Watchdog Timer counts down to 000000h unless a WDT instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes the downcounter to be reloaded with the WDT reload value stored in the Watchdog Timer Reload registers. Counting resumes following the Reload operation. When the Z8 Encore! F0830 Series devices are operating in DEBUG Mode (using the OnChip Debugger), the Watchdog Timer must be continuously refreshed to prevent any WDT time-outs. Watchdog Timer Time-Out Response The Watchdog Timer times out when the counter reaches 000000h. A time-out of the Watchdog Timer generates either an interrupt or a system reset. The WDT_RES Flash option bit determines the time-out response of the Watchdog Timer. See the Flash Option Bits chapter on page 124 for information about programming the WDT_RES Flash option bit. WDT Interrupt in Normal Operation If configured to generate an interrupt when a time-out occurs, the Watchdog Timer issues an interrupt request to the Interrupt Controller and sets the WDT status bit in the Reset Status Register. If interrupts are enabled, the eZ8 CPU responds to the interrupt request by fetching the Watchdog Timer interrupt vector and executing code from the vector address. After time-out and interrupt generation, the Watchdog Timer counter resets to its maximum value of FFFFFh and continues counting. The Watchdog Timer counter will not automatically return to its reload value. The Reset Status Register (see Table 12 on page 29) must be read before clearing the WDT interrupt. This read clears the WDT time-out flag and prevents further WDT interrupts occurring immediately. WDT Interrupt in Stop Mode If configured to generate an interrupt when a time-out occurs and the Z8 Encore! F0830 Series devices are in Stop Mode, the Watchdog Timer automatically initiates a Stop Mode Recovery and generates an interrupt request. Both the WDT status bit and the STOP bit in the Watchdog Timer Control Register are set to 1 following a WDT time-out in Stop Mode. See the Reset and Stop Mode Recovery chapter on page 21 for more information about Stop Mode Recovery operations. If interrupts are enabled, following completion of the Stop Mode Recovery, the eZ8 CPU responds to the interrupt request by fetching the Watchdog Timer interrupt vector and executes the code from the vector address. PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 94 WDT Reset in Normal Operation If configured to generate a reset when a time-out occurs, the Watchdog Timer forces the device into the System Reset state. The WDT status bit in the Watchdog Timer Control Register is set to 1. See the Reset and Stop Mode Recovery chapter on page 21 for more information about system reset operations. WDT Reset in Stop Mode If configured to generate a reset when a time-out occurs and the device is in Stop Mode, the Watchdog Timer initiates a Stop Mode Recovery. Both the WDT status bit and the STOP bit in the Watchdog Timer Control Register are set to 1 following WDT time-out in Stop Mode. See the Reset and Stop Mode Recovery chapter on page 21 for more information about Stop Mode Recovery operations. Watchdog Timer Reload Unlock Sequence Writing the unlock sequence to the Watchdog Timer (WDTCTL) Control Register address, unlocks the three Watchdog Timer Reload Byte registers (WDTU, WDTH and WDTL) to allow changes to the time-out period. These write operations to the WDTCTL Register address produce no effect on the bits in the WDTCTL Register. The locking mechanism prevents spurious writes to the reload registers. The following sequence is required to unlock the Watchdog Timer Reload Byte registers (WDTU, WDTH and WDTL) for write access: 1. Write 55h to the Watchdog Timer Control Register (WDTCTL). 2. Write AAh to the Watchdog Timer Control Register (WDTCTL). 3. Write the Watchdog Timer Reload Upper Byte Register (WDTU). 4. Write the Watchdog Timer Reload High Byte Register (WDTH). 5. Write the Watchdog Timer Reload Low Byte Register (WDTL). All three Watchdog Timer Reload registers must be written in the order listed above. There must be no other register writes between each of these operations. If a register write occurs, the lock state machine resets and no further writes can occur unless the sequence is restarted. The value in the Watchdog Timer Reload registers is loaded into the counter when the Watchdog Timer is first enabled and every time a WDT instruction is executed. PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 95 Watchdog Timer Control Register Definitions This section defines the features of the following Watchdog Timer Control registers. Watchdog Timer Control Register (WDTCTL): see page 95 Watchdog Timer Reload Low Byte Register (WDTL): see page 97 Watchdog Timer Reload Upper Byte Register (WDTU): see page 96 Watchdog Timer Reload High Byte Register (WDTH): see page 96 Watchdog Timer Control Register The Watchdog Timer Control (WDTCTL) Register is a write-only control register. Writing the unlock sequence: 55h, AAh to the WDTCTL Register address unlocks the three Watchdog Timer Reload Byte registers (WDTU, WDTH and WDTL) to allow changes to the time-out period. These write operations to the WDTCTL Register address have no effect on the bits in the WDTCTL Register. The locking mechanism prevents spurious writes to the reload registers. This register address is shared with the read-only Reset Status Register. Table 59. Watchdog Timer Control Register (WDTCTL) Bit 7 6 5 Field 4 3 2 1 0 WDTUNLK RESET X X X X X X X X R/W W W W W W W W W Address FF0h Bit Description [7:0] WDTUNLK Watchdog Timer Unlock The user software must write the correct unlocking sequence to this register before it is allowed to modify the contents of the Watchdog Timer Reload registers. PS025114-1314 Watchdog Timer Control Register Definitions Z8 Encore!® F0830 Series Product Specification 96 Watchdog Timer Reload Upper, High and Low Byte Registers The Watchdog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) registers, shown in Tables 60 through 62, form the 24-bit reload value that is loaded into the Watchdog Timer when a WDT instruction executes. This 24-bit value ranges across bits [23:0] to encompass the three bytes {WDTU[7:0], WDTH[7:0], WDTL[7:0]}. Writing to these registers sets the appropriate reload value; reading from these registers returns the current Watchdog Timer count value. Caution: The 24-bit WDT reload value must not be set to a value less than 000004h. Table 60. Watchdog Timer Reload Upper Byte Register (WDTU) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 WDTU 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Address FF1h Note: *A read returns the current WDT count value; a write sets the appropriate reload value. Bit Description [7:0] WDTU WDT Reload Upper Byte Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value. Table 61. Watchdog Timer Reload High Byte Register (WDTH) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 WDTH 0 0 0 0 0 1 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Address FF2h Note: *A read returns the current WDT count value; a write sets the appropriate reload value. Bit Description [7:0] WDTH WDT Reload High Byte Middle byte, bits[15:8] of the 24-bit WDT reload value. PS025114-1314 Watchdog Timer Control Register Definitions Z8 Encore!® F0830 Series Product Specification 97 Table 62. Watchdog Timer Reload Low Byte Register (WDTL) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 WDTL 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Address FF3h Note: *A read returns the current WDT count value; a write sets the appropriate reload value. Bit Description [7:0] WDTL WDT Reload Low Least significant byte (LSB), bits[7:0] of the 24-bit WDT reload value. PS025114-1314 Watchdog Timer Control Register Definitions Z8 Encore!® F0830 Series Product Specification 98 Analog-to-Digital Converter The Z8 Encore! MCU includes an eight-channel Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The ADC converts an analog input signal to a 10-bit binary number. The features of the SAR ADC include: • • • • • • • Eight analog input sources multiplexed with general purpose I/O ports Fast conversion time, less than 11.9 µs Programmable timing controls Interrupt on conversion complete Internal voltage reference generator Ability to select external reference voltage When configuring an ADC using external VREF, PB5 is used as VREF in the 28-pin package Architecture The ADC architecture, displayed in Figure 11, consists of an 8-input multiplexer, sampleand-hold amplifier and 10-bit SAR ADC. The ADC digitizes the signal on a selected channel and stores the digitized data in the ADC data registers. In an environment with high electrical noise, an external RC filter must be added at the input pins to reduce highfrequency noise. TCONV = TS/H + TCON TCONV = TS + TH + 13 * SCLK * 16 where: SCLK = System Clock TCONV = Total conversion time TS = Sample time (SCLK * ADCST) TCON = Conversion time (13 * SCLK * 16) TH = Hold time (SCLK * ADCSST) DIV = 16 (fixed to divide by 16 for F0830 Series products) Example: For an F0830 Series MCU running @ 20 MHz: TCONV = 1µs + 0.5µs + 13 * SCLK * DIV TCONV = 1 µs + 0.5 µs + 13 * (1/20 MHz) * 16 = 11.9 µs PS025114-1314 Analog-to-Digital Converter Z8 Encore!® F0830 Series Product Specification 99 REFEN Sel 28 Package Internal Voltage Reference Generator VR2 RBUF Analog Input Multiplexer Analog-to-Digital Converter ANA0 ANA1 Reference Input Data Output VREF 10 ANA2 ANA3 Analog Input BUSY Sample-and-Hold Amplifier ANA4 ANA5 ANA6 ANA7 ADCLK ANAIN[2:0] ADCEN SAMPLE/HOLD START Figure 11. Analog-to-Digital Converter Block Diagram Operation The ADC converts the analog input, ANAX, to a 10-bit digital representation. The equation for calculating the digital value is represented by: ADCOutput = 1024   ANA x  V REF  Assuming zero gain and offset errors, any voltage outside the ADC input limits of AVSS and VREF returns all 0s or 1s, respectively. A new conversion can be initiated by a software to the ADC Control Register’s start bit. Initiating a new conversion, stops any conversion currently in progress and begins a new conversion. To avoid disrupting a conversion already in progress, the START bit can be read to determine ADC operation status (busy or available). PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 100 ADC Timing Each ADC measurement consists of three phases: 1. Input sampling (programmable, minimum of 1.0 µs) 2. Sample-and-hold amplifier settling (programmable, minimum of 0.5 µs) 3. Conversion is 13 ADCLK cycles Figures 12 and 13 display the timing of an ADC conversion. conversion period START 1.0µs min sample period Programable settling period SAMPLE/HOLD 13 clocks convert period BUSY convertbit7 convertbit6 convertbit5 convertbit4 convertbit3 4 5 6 7 8 9 store in register convertbit8 3 convertbit0 convertbitmsb 2 convertbit1 sync 1 convertbit2 sync Figure 12. ADC Timing Diagram 10 11 12 13 14 15 16 17 ADC Clock BUSY 13 clocks convert period Figure 13. ADC Convert Timing PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 101 ADC Interrupt The ADC can generate an interrupt request when a conversion has been completed. An interrupt request that is pending when the ADC is disabled is not cleared automatically. Reference Buffer The reference buffer, RBUF, supplies the reference voltage for the ADC. When enabled, the internal voltage reference generator supplies the ADC. When RBUF is disabled, the ADC must have the reference voltage supplied externally through the VREF pin in 28-pin package. RBUF is controlled by the REFEN bit in the ADC Control Register. Internal Voltage Reference Generator The internal voltage reference generator provides the voltage VR2, for the RBUF. VR2 is 2 V. Calibration and Compensation A user can perform calibration and store the values into Flash or the user code can perform a manual offset calibration. There is no provision for manual gain calibration. ADC Control Register Definitions The ADC Control registers are defined in this section. PS025114-1314 ADC Control Register Definitions Z8 Encore!® F0830 Series Product Specification 102 ADC Control Register 0 The ADC Control 0 Register, shown in Table 63, initiates an A/D conversion and provides ADC status information. Table 63. ADC Control Register 0 (ADCCTL0) Bit Field RESET R/W 7 6 5 4 3 START Reserved REFEN ADCEN Reserved 0 0 0 0 0 0 0 0 R/W1 R/W R/W R/W R/W R/W R/W R/W Address 2 1 0 ANAIN[2:0] F70h Bit Description [7] START ADC Start/Busy 0 = Writing to 0 has no effect; reading a 0 indicates that the ADC is available to begin a conversion. 1 = Writing to 1 starts a conversion; reading a 1 indicates that a conversion is currently in progress. [6] Reserved This bit is reserved and must be programmed to 0. [5] REFEN Reference Enable 0 = Internal reference voltage is disabled allowing an external reference voltage to be used by the ADC. 1 = Internal reference voltage for the ADC is enabled. The internal reference voltage can be measured on the VREF pin. [4] ADCEN ADC Enable 0 = ADC is disabled for low power operation. 1 = ADC is enabled for normal use. [3] Reserved This bit is reserved and must be programmed to 0. [2:0] ANAIN Analog Input Select 000 = ANA0 input is selected for analog to digital conversion. 001 = ANA1 input is selected for analog to digital conversion. 010 = ANA2 input is selected for analog to digital conversion. 011 = ANA3 input is selected for analog to digital conversion. 100 = ANA4 input is selected for analog to digital conversion. 101 = ANA5 input is selected for analog to digital conversion. 110 = ANA6 input is selected for analog to digital conversion. 111 = ANA7 input is selected for analog to digital conversion. PS025114-1314 ADC Control Register Definitions Z8 Encore!® F0830 Series Product Specification 103 ADC Data High Byte Register The ADC Data High Byte Register, listed in Table 64, contains the upper eight bits of the ADC output. Access to the ADC Data High Byte Register is read-only. Reading the ADC Data High Byte Register latches data in the ADC Low Bits Register. Table 64. ADC Data High Byte Register (ADCD_H) Bit 7 6 5 4 Field 3 2 1 0 ADCDh RESET X R/W R Address F72h Bit Description [7:0] ADCDh ADC High Byte 00h–FFh = The last conversion output is held in the data registers until the next ADC conversion is completed. ADC Data Low Bits Register The ADC Data Low Bits Register, shown in Table 65, contains the lower bits of the ADC output. Access to the ADC Data Low Bits Register is read-only. Reading the ADC Data High Byte Register latches lower bits of the ADC in the ADC Data Low Bits Register. Table 65. ADC Data Low Bits Register (ADCD_L) Bit 7 Field 6 5 4 3 2 ADCDL Reserved RESET X X R/W R R Address 1 0 F73h Bit Description [7:6] ADCDL ADC Low Bits 00–11b = These bits are the two least-significant bits of the 10-bit ADC output. These bits are undefined after a reset. The low bits are latched into this register whenever the ADC Data High Byte Register is read. [5:0] Reserved These bits are reserved and must be programmed to 000000. PS025114-1314 ADC Control Register Definitions Z8 Encore!® F0830 Series Product Specification 104 Sample Settling Time Register The Sample Settling Time Register, shown in Table 66, is used to program a delay after the SAMPLE/HOLD signal is asserted and before the START signal is asserted; an ADC conversion then begins. The number of clock cycles required for settling will vary from system to system depending on the system clock period used. The system designer should program this register to contain the number of clocks required to meet a 0.5 µs minimum settling time. Table 66. Sample Settling Time (ADCSST) Bit 7 Field 6 5 4 3 2 Reserved RESET 0 R/W R Address 1 0 1 1 SST 1 1 R/W F74h Bit Description [7:4] Reserved These bits are reserved and must be programmed to 0000. [3:0] SST 0h–Fh = Sample settling time in number of system clock periods to meet 0.5 µs minimum. PS025114-1314 ADC Control Register Definitions Z8 Encore!® F0830 Series Product Specification 105 Sample Time Register The Sample Time Register, shown in Table 67, is used to program the length of active time for a sample after a conversion has begun by setting the START bit in the ADC Control Register. The number of system clock cycles required for the sample time varies from system to system, depending on the clock period used. The system designer should program this register to contain the number of system clocks required to meet a 1 µs minimum sample time. Table 67. Sample Time (ADCST) Bit 7 Field 6 5 4 3 Reserved RESET 0 R/W 1 0 1 1 1 ST 1 1 1 R/W Address 2 R/W F75h Bit Description [7:6] Reserved These bits are reserved and must be programmed to 00. [5:0] ST 0h–Fh = Sample-hold time in number of system clock periods to meet 1 µs minimum. PS025114-1314 ADC Control Register Definitions Z8 Encore!® F0830 Series Product Specification 106 Comparator The Z8 Encore! F0830 Series devices feature a general purpose comparator that compares two analog input signals. A GPIO (CINP) pin provides the positive comparator input. The negative input (CINN) can be taken from either an external GPIO pin or from an internal reference. The output is available as an interrupt source or can be routed to an external pin using the GPIO multiplex. The comparator includes the following features: • • Positive input is connected to a GPIO pin • Output can be either an interrupt source or an output to an external pin Negative input can be connected to either a GPIO pin or a programmable internal reference Operation One of the comparator inputs can be connected to an internal reference that is a userselectable reference and is user-programmable with 200 mV resolution. The comparator can be powered down to save supply current. For details, see the Power Control Register 0 section on page 31. Caution: As a result of the propagation delay of the comparator, Zilog does not recommend enabling the comparator without first disabling interrupts and waiting for the comparator output to settle. This delay prevents spurious interrupts after comparator enabling. The following example shows how to safely enable the comparator: di ld cmp0,r0; load some new configuration nop nop ; wait for output to settle clr irq0 ; clear any spurious interrupts pending ei PS025114-1314 Comparator Z8 Encore!® F0830 Series Product Specification 107 Comparator Control Register Definitions The Comparator Control Register (CMP0) configures the comparator inputs and sets the value of the internal voltage reference. The GPIO pin is always used as positive comparator input. Table 68. Comparator Control Register (CMP0) Bit Field RESET R/W 7 6 Reserved INNSEL 0 0 0 1 0 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address 5 4 3 2 1 REFLVL 0 Reserved F90h Bit Description [7] Reserved This bit is reserved and must be programmed to 0. [6] INNSEL Signal Select for Negative Input 0 = internal reference disabled, GPIO pin used as negative comparator input. 1 = internal reference enabled as negative comparator input. [5:2] REFLVL Internal Reference Voltage Level This reference is independent of the ADC voltage reference. 0000 = 0.0 V. 0001 = 0.2 V. 0010 = 0.4 V. 0011 = 0.6 V. 0100 = 0.8 V. 0101 = 1.0 V (Default). 0110 = 1.2 V. 0111 = 1.4 V. 1000 = 1.6 V. 1001 = 1.8 V. 1010–1111 = Reserved. [1:0] Reserved These bits are reserved and must be programmed to 00. PS025114-1314 Comparator Control Register Definitions Z8 Encore!® F0830 Series Product Specification 108 Flash Memory The products in the Z8 Encore! F0830 Series features either 1 KB (1024 bytes with NVDS), 2 KB (2048 bytes with NVDS), 4 KB (4096 bytes with NVDS), 8 KB (8192 bytes with NVDS) or 12 KB (12288 bytes with no NVDS) of nonvolatile Flash memory with read/write/erase capability. Flash memory can be programmed and erased in-circuit by either user code or through the On-Chip Debugger. The Flash memory array is arranged in pages with 512 bytes per page. The 512-byte page is the minimum Flash block size that can be erased. Each page is divided into eight rows of 64 bytes. For program/data protection, Flash memory is also divided into sectors. In the Z8 Encore! F0830 Series, each sector maps to one page (for 1 KB, 2 KB and 4 KB devices), two pages (8 KB device) or three pages (12 KB device). The first two bytes of Flash program memory is used as Flash option bits. For more information, see the Flash Option Bits chapter on page 124. Table 69 lists the Flash memory configuration for each device in the Z8 Encore! F0830 Series. Figures 14 through 18 display the memory arrangements for each Flash memory size. Table 69. Z8 Encore! F0830 Series Flash Memory Configuration Flash Pages Program Memory Addresses Flash Sector Size (bytes) 12 (12,288) 24 0000h–2FFFh 1536 Z8F083x 8 (8196) 16 0000h–1FFFh 1024 Z8F043x 4 (4096) 8 0000h–0FFFh 512 Z8F023x 2 (2048) 4 0000h–07FFh 512 Z8F013x 1 (1024) 2 0000h–03FFh 512 Part Number Flash Size KB (Bytes) Z8F123x 03FFh 03FFh 0200h 01FFh Sector 1 Page 1 Sector 0 Page 0 0200h 01FFh 0000h 0000h Figure 14. 1K Flash with NVDS PS025114-1314 Flash Memory Z8 Encore!® F0830 Series Product Specification 109 07FFh 0600h 05FFh 0400h 03FFh 0200h 01FFh 07FFh Sector 3 Page 3 Sector 2 Page 2 Sector 1 Page 1 Sector 0 Page 0 0000h 0600h 05FFh 0400h 03FFh 0200h 01FFh 0000h Figure 15. 2K Flash with NVDS 0FFFh 0FFFh Page 7 Sector 7 0E00h 0DFFh 0E00h 0DFFh Page 6 Sector 6 0C00h 0BFFh 0C00h 0BFFh Page 5 Sector 5 0A00h 09FFh 0A00h 09FFh Page 4 Sector 4 0800h 07FFh Page 3 Sector 3 0800h 07FFh 0600h 05FFh 0600h 05FFh Page 2 Sector 2 0400h 03FFh 0400h 03FFh Page 1 Sector 1 0200h 01FFh 0200h 01FFh Page 0 Sector 0 0000h 0000h Figure 16. 4K Flash with NVDS PS025114-1314 Flash Memory Z8 Encore!® F0830 Series Product Specification 110 Page 15 1FFFh Page 14 Sector 7 1C00h 18FFh Page 13 Page 12 Sector 6 1800h 17FFh Page 11 Sector 5 Page 10 1400h 13FFh Page 9 Sector 4 1C00h 0FFFh Page 8 Page 7 Sector 3 Page 6 0C00h 0BFFh Page 5 Sector 2 Page 4 0800h 07FFh Page 3 Sector 1 Page 2 0400h 03FFh Page 1 Sector 0 Page 0 0000h 1FFFh 1E00h 1DFFh 1C00h 1BFFh 1A00h 19FFh 1800h 17FFh 1600h 15FFh 1400h 13FFh 1200h 11FFh 1C00h 0FFFh 0E00h 0DFFh 0C00h 0BFFh 0A00h 09FFh 0800h 07FFh 0600h 05FFh 0400h 03FFh 0200h 0100h 0000h Figure 17. 8K Flash with NVDS PS025114-1314 Flash Memory Z8 Encore!® F0830 Series Product Specification 111 2FFFh Sector 7 2A00h 29FFh Page 23 2FFFh 2E00h Page 22 2DFFh 2C00h Page 21 2BFFh 2A00h Sector 6 1600h 23FFh Page 20 Sector 5 1E00h 1DFFh Sector 4 1800h 17FFh Sector 3 1200h 11FFh Sector 2 0C00h 0BFFh Page 2 05FFh 0400h Page 1 03FFh 0200h Page 0 01FFh 0000h Sector 1 0600h 05FFh Sector 0 0000h Figure 18. 12K Flash without NVDS Data Memory Address Space The Flash information area, including Zilog Flash option bits, are located in the data memory address space. The Z8 Encore! MCU is configured by these proprietary Flash option bits to prevent the user from writing to the eZ8 CPU data memory address space. Flash Information Area The Flash information area is physically separate from program memory and is mapped to the address range FE00h to FE7Fh. Not all of these addresses are user-accessible. Factory trim values for the VBO, Internal Precision Oscillator and factory calibration data for the ADC are stored here. Table 70 describes the Flash information area. This 128-byte information area is accessed by setting the bit 7 of the Flash Page Select Register to 1. When access is enabled, the PS025114-1314 Data Memory Address Space Z8 Encore!® F0830 Series Product Specification 112 Flash information area is mapped into program memory and overlays the 128 bytes in the address range FE00h to FE7Fh. When the information area access is enabled, all reads from these program memory addresses return the information area data rather than the program memory data. Access to the Flash information area is read-only. The trim bits are handled differently than the other Zilog Flash option bits. The trim bits are the hybrid of the user option bits and the standard Zilog option bits. These trim bits must be user-accessible for reading at all times using external registers regardless of the state of bit 7 in the Flash Page Select Register. Writes to the trim space change the value of the Option Bit Holding Register but do not affect the Flash bits, which remain as readonly. Table 70. Z8F083 Flash Memory Area Map Program Memory Address (Hex) Function FE00–FE3F Zilog option bits FE40–FE53 Part number 20-character ASCII alphanumeric code Left justified and filled with Fh FE54–FE5F Reserved FE60–FE7F Reserved Operation The Flash Controller programs and erases Flash memory. The Flash Controller provides the proper Flash controls and timing for byte programming, page erase and mass erase of Flash memory. The Flash Controller contains several protection mechanisms to prevent accidental programming or erasure. These mechanism operate on the page, sector and full-memory levels. The flowchart in Figure 19 display basic Flash Controller operation. The following subsections provide details about the various operations (Lock, Unlock, Byte Programming, Page Protect, Page Unprotect, Page Select Page Erase and Mass Erase) displayed in Figure 19. PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 113 Reset Lock State 0 Write Page Select Register Write FCTL No 73H Yes Lock State 1 Write FCTL Writes to Page Select Register in Lock State 1 result in a return to Lock State 0 No 8Ch Yes Write Page Select Register No Page Select values match? Yes Yes Page in Protected Sector? Byte Program Write FCTL No Page Unlocked Program/Erase Enabled Yes 95h Page Erase No Figure 19. Flash Controller Operation Flow Chart PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 114 Flash Operation Timing Using the Flash Frequency Registers Before performing either a Program or Erase operation on Flash memory, the user must first configure the Flash Frequency High and Low Byte registers. The Flash frequency registers allow programming and erasing of the Flash with system clock frequencies ranging from 10 kHz to 20 MHz. The Flash Frequency High and Low Byte registers combine to form a 16-bit value, FFREQ, to control the timing for Flash Program and Erase operations. The 16-bit binary Flash frequency value must contain the system clock frequency (in kHz). This value is calculated using the following equation: System Clock Frequency (Hz) FFREQ[15:0] = -----------------------------------------------------------------------1000 Caution: Flash programming and erasure are not supported for system clock frequencies below 10 kHz or above 20 MHz. The Flash Frequency High and Low Byte registers must be loaded with the correct value to ensure operation of the Z8 Encore! F0830 Series devices. Flash Code Protection Against External Access The user code contained within Flash memory can be protected against external access by using the On-Chip Debugger. Programming the FRP Flash option bit prevents reading of the user code using the On-Chip Debugger. For more information, see the Flash Option Bits chapter on page 124 and the On-Chip Debugger chapter on page 139. Flash Code Protection Against Accidental Program and Erasure The Z8 Encore! F0830 Series provides several levels of protection against accidental program and erasure of the Flash memory contents. This protection is provided by a combination of the Flash option bits, the register locking mechanism, the page select redundancy and the sector level protection control of the Flash Controller. Flash Code Protection Using the Flash Option Bits The FHSWP and FWP Flash option bits combine to provide three levels of Flash program memory protection, as listed in Table 71. See the Flash Option Bits chapter on page 124 for more information. PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 115 Table 71. Flash Code Protection using the Flash Option Bits FHSWP FWP Flash Code Protection Description 0 0 Programming and erasing disabled for all Flash program memory. In user code programming, page erase and mass erase are all disabled. Mass erase is available through the On-Chip Debugger. 0 or 1 1 Programming, page erase and mass erase are enabled for all of the Flash program memory. At reset, the Flash Controller is locked to prevent accidental program or erasure of Flash memory. To program or erase Flash memory, first write the target page to the page select register. Unlock the Flash Controller by making two consecutive writes to the Flash Control Register with the values 73h and 8Ch, sequentially. The page select register must be rewritten with the same page previously stored there. If the two page select writes do not match, the controller reverts to a Locked state. If the two writes match, the selected page becomes active. See Figure 19 for details. After unlocking a specific page, you can enable either page program or erase. Writing the value 95h causes a page erase only if the active page resides in a sector that is not protected. Any other value written to the Flash Control Register locks the Flash Controller. Mass erase is not allowed in the user code, but is allowed through the debug port. After unlocking a specific page, the user can also write to any byte on that page. After a byte is written, the page remains unlocked, allowing for subsequent writes to other bytes on the same page. Further writes to the Flash Control Register causes the active page to revert to a Locked state. Sector Based Flash Protection The final protection mechanism is implemented on a per-sector basis. The Flash memories of Z8 Encore! devices are divided into maximum number of eight sectors. A sector is oneeighth of the total size of Flash memory, unless this value is smaller than the page size, in which case the sector and page sizes are equal. On Z8 Encore! F0830 Series devices, the sector size is varied according to the Z8 Encore! F0830 Series Flash Memory Configuration shown in Table 69 on page 108 and in Figures 14 through 18, which follow the table The Flash Sector Protect Register can be configured to prevent sectors from being programmed or erased. After a sector is protected, it cannot be unprotected by user code. The Flash Sector Protect Register is cleared after reset and any previously written protection values is lost. User code must write this register in their initialization routine if they want to enable sector protection. The Flash Sector Protect Register shares its Register File address with the Page Select Register. The Flash Sector Protect Register is accessed by writing the Flash Control Register with 5Eh. After the Flash Sector Protect Register is selected, it can be accessed at the Page Select Register address. When user code writes the Flash Sector Protect Register, PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 116 bits can only be set to 1. Thus, sectors can be protected, but not unprotected, via register write operations. Writing a value other than 5Eh to the Flash Control Register deselects the Flash Sector Protect Register and reenables access to the Page Select Register. Observe the following procedure to setup the Flash Sector Protect Register from user code: 1. Write 00h to the Flash Control Register to reset the Flash Controller. 2. Write 5Eh to the Flash Control Register to select the Flash Sector Protect Register. 3. Read and/or write the Flash Sector Protect Register which is now at Register File address FF9h. 4. Write 00h to the Flash Control Register to return the Flash Controller to its reset state. The Sector Protect Register is initialized to 0 on reset, putting each sector into an unprotected state. When a bit in the Sector Protect Register is written to 1, the corresponding sector can no longer be written or erased. After setting a bit in the Sector Protect Register, the bit cannot be cleared by the user. Byte Programming Flash memory is enabled for byte programming after unlocking the Flash Controller and successfully enabling either mass erase or page erase. When the Flash Controller is unlocked and mass erase is successfully enabled, all of the program memory locations are available for byte programming. In contrast, when the Flash Controller is unlocked and page erase is successfully enabled, only the locations of the selected page are available for byte programming. An erased Flash byte contains all 1’s (FFh). The programming operation can only be used to change bits from 1 to 0. To change a Flash bit (or multiple bits) from 0 to 1 requires execution of either the page erase or mass erase commands. Byte programming can be accomplished using the On-Chip Debugger’s write memory command or eZ8 CPU execution of the LDC or LDCI instructions. Refer to the eZ8 CPU Core User Manual (UM0128), which is available for download on www.zilog.com, for the description of the LDC and LDCI instructions. While the Flash Controller programs the Flash memory, the eZ8 CPU idles, but the system clock and on-chip peripherals continue to operate. To exit programming mode and lock the Flash, write any value to the Flash Control Register, except the mass erase or page erase commands. Caution: The byte at each address within Flash memory cannot be programmed (any bits written to 0) more than twice before an erase cycle occurs. PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 117 Page Erase Flash memory can be erased one page (512 bytes) at a time. Page erasing Flash memory sets all bytes in that page to the value FFh. The Flash Page Select Register identifies the page to be erased. Only a page residing in an unprotected sector can be erased. With the Flash Controller unlocked and the active page set, writing the value 95h to the Flash Control Register initiates the Page Erase operation. While the Flash Controller executes the Page Erase operation, the eZ8 CPU idles, but the system clock and on-chip peripherals continue to operate. The eZ8 CPU resumes operation after the page erase operation completes. If the Page Erase operation is performed using the On-Chip Debugger, poll the Flash Status Register to determine when the Page Erase operation is complete. When the page erase is complete, the Flash Controller returns to its Locked state. Mass Erase Flash memory can also be mass erased using the Flash Controller, but only by using the On-Chip Debugger. Mass erasing Flash memory sets all bytes to the value FFh. With the Flash Controller unlocked and the mass erase successfully enabled, writing the value 63h to the Flash Control Register initiates the Mass Erase operation. While the Flash Controller executes the Mass Erase operation, the eZ8 CPU idles, but the system clock and onchip peripherals continue to operate. Using the On-Chip Debugger, poll the Flash Status Register to determine when the Mass Erase operation is complete. When the mass erase is complete, the Flash Controller returns to its Locked state. Flash Controller Bypass The Flash Controller can be bypassed; instead, the control signals for Flash memory can be brought out to the GPIO pins. Bypassing the Flash Controller allows faster row programming algorithms by controlling the Flash programming signals directly. Row programing is recommended for gang programming applications and large volume customers who do not require in-circuit initial programming of Flash memory. Mass Erase and Page Erase operations are also supported, when the Flash Controller is bypassed. For more information about bypassing the Flash Controller, refer to Third-Party Flash Programming Support for Z8 Encore!. This document is available for download at www.zilog.com. Flash Controller Behavior in Debug Mode The following behavioral changes can be observed in the Flash Controller when the Flash Controller is accessed using the On-Chip Debugger: • PS025114-1314 The Flash write protect option bit is ignored. Operation Z8 Encore!® F0830 Series Product Specification 118 • • • • The Flash Sector Protect Register is ignored for programming and Erase operations. • • The page select register can be written when the Flash Controller is unlocked. Programming operations are not limited to the page selected in the page select register. Bits in the Flash Sector Protect Register can be written to one or zero. The second write of the page select register to unlock the Flash Controller is not necessary. The mass erase command is enabled through the Flash Control Register Caution: For security reasons, Flash Controller allows only a single page to be opened for write/ erase. When writing multiple Flash pages, the Flash Controller must go through the unlock sequence again to select another page. NVDS Operational Requirements The device uses a 12 KB Flash memory space, despite the maximum specified Flash size of 8 KB (with the exception of 12 KB mode with non-NVDS). User code accesses the lower 8 KB of Flash, leaving the upper 4 KB for proprietary (for Zilog-only) memory. The NVDS is implemented by using this proprietary memory space for special-purpose routines and for the data required by these routines, which are factory-programmed and cannot be altered by the user. The NVDS operation is described in detail in the Nonvolatile Data Storage chapter on page 134. The NVDS routines are triggered by a user code: CALL into proprietary memory. Code executing from this proprietary memory must be able to read and write other locations within proprietary memory. User code must not be able to read or write proprietary memory. Flash Control Register Definitions This section defines the features of the following Flash Control registers. Flash Control Register: see page 119 Flash Status Register: see page 120 Flash Page Select Register: see page 121 Flash Sector Protect Register: see page 122 Flash Frequency High and Low Byte Registers: see page 123 PS025114-1314 NVDS Operational Requirements Z8 Encore!® F0830 Series Product Specification 119 Flash Control Register The Flash Controller must be unlocked using the Flash Control Register before programming or erasing Flash memory. Writing the sequence 73h 8Ch, sequentially, to the Flash Control Register unlocks the Flash Controller. When the Flash Controller is unlocked, Flash memory can be enabled for mass erase or page erase by writing the appropriate enable command to the FCTL. Page erase applies only to the active page selected in Flash Page Select Register. Mass erase is enabled only through the On-Chip Debugger. Writing an invalid value or an invalid sequence returns the Flash Controller to its Locked state. The write-only Flash Control Register shares its register file address with the read-only Flash Status Register. Table 72. Flash Control Register (FCTL) Bit 7 6 5 4 Field 3 2 1 0 FCMD RESET 0 0 0 0 0 0 0 0 R/W W W W W W W W W Address FF8h Bit Description [7:0] FCMD Flash Command 73h = First unlock command. 8Ch = Second unlock command. 95h = Page erase command (must be third command in sequence to initiate page erase). 63h = Mass erase command (must be third command in sequence to initiate mass erase). 5Eh = Enable Flash Sector Protect Register access. PS025114-1314 Flash Control Register Definitions Z8 Encore!® F0830 Series Product Specification 120 Flash Status Register The Flash Status Register indicates the current state of the Flash Controller. This register can be read at any time. The read-only Flash Status Register shares its register file address with the write-only Flash Control Register. Table 73. Flash Status Register (FSTAT) Bit 7 Field 6 5 4 3 Reserved 2 1 0 FSTAT RESET 0 0 0 0 0 0 0 0 R/W R R R R R R R R Address FF8h Bit Description [7:6] Reserved These bits are reserved and must be programmed to 00. [5:0] FSTAT Flash Controller Status 000000 = Flash Controller locked. 000001 = First unlock command received (73h written). 000010 = Second unlock command received (8Ch written). 000011 = Flash Controller unlocked. 000100 = Sector protect register selected. 001xxx = Program operation in progress. 010xxx = Page Erase operation in progress. 100xxx = Mass Erase operation in progress. PS025114-1314 Flash Control Register Definitions Z8 Encore!® F0830 Series Product Specification 121 Flash Page Select Register The Flash Page Select Register shares address space with the Flash Sector Protect Register. Unless the Flash Controller is locked and written with 5Eh, any writes to this address will target the Flash Page Select Register. The register selects one of the eight available Flash memory pages to be programmed or erased. Each Flash page contains 512-bytes of Flash memory. During a page erase operation, all Flash memory containing addresses with the most significant 7 bits within FPS[6:0] are chosen for program/erase operations. Table 74. Flash Page Select Register (FPS) Bit Field RESET R/W 7 5 4 3 INFO_EN 2 1 0 PAGE 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address Bit 6 FF9h Description [7] Information Area Enable INFO_EN 0 = Information area is not selected. 1 = Information area is selected. The information area is mapped into the program memory address space at addresses FE00h through FFFFh. [6:0] PAGE Page Select This 7-bit field identifies the Flash memory page for page erase and page unlocking. Program memory address[15:9] = PAGE[6:0]. For Z8F04xx and Z8F02xx devices, the upper four bits must always be 0. For Z8F01xx devices, the upper five bits must always be 0. PS025114-1314 Flash Control Register Definitions Z8 Encore!® F0830 Series Product Specification 122 Flash Sector Protect Register The Flash Sector Protect Register is shared with the Flash Page Select Register. When the Flash Control Register is locked and written with 5Eh, the next write to this address targets the Flash Sector Protect Register. In all other cases, it targets the Flash Page Select Register. This register selects one of the eight available Flash memory sectors to be protected. The Reset state of each sector protect bit is the zero (unprotected) state. After a sector is protected by setting its corresponding register bit, the register bit cannot be cleared by the user. To determine the appropriate Flash memory sector address range and sector number for your F0830 Series product, please refer to Table 70 on page 112. Table 75. Flash Sector Protect Register (FPROT) Bit Field RESET R/W 7 6 5 4 3 2 1 0 SPROT7 SPROT6 SPROT5 SPROT4 SPROT3 SPROT2 SPROT1 SPROT0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address Bit FF9h Description [7:0] Sector Protection SPROTx For Z8F12xx, Z8F08xx and Z8F04xx devices, all bits are used. For Z8F02xx devices, the upper four bits remain unused. For Z8F01xx devices, the upper six bits remain unused. To determine the appropriate Flash memory sector address range and sector number for your F0830 Series product, please refer to Table 69 and to Figures 14 through 18. Note: x indicates bits in the range 7–0. PS025114-1314 Flash Control Register Definitions Z8 Encore!® F0830 Series Product Specification 123 Flash Frequency High and Low Byte Registers The Flash Frequency High and Low Byte registers, shown in Tables 76 and 77, combine to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit binary Flash frequency value must contain the system clock frequency (in kHz) and is calculated using the following equation: System Clock Frequency FFREQ[15:0] =  FFREQH[7:0],FFREQL[7:0]  = -----------------------------------------------------------1000 Caution: Flash programming and erasure is not supported for system clock frequencies below 10 kHz or above 20 MHz. The Flash Frequency High and Low Byte registers must be loaded with the correct value to ensure proper operation of the device. Table 76. Flash Frequency High Byte Register (FFREQH) Bit 7 6 5 4 Field RESET R/W 2 1 0 FFREQH 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 1 0 Address Bit 3 FFAh Description [7:0] Flash Frequency High Byte FFREQH High byte of the 16-bit Flash frequency value. Table 77. Flash Frequency Low Byte Register (FFREQL) Bit 7 Field 6 5 4 3 FFREQL RESET 0 R/W R/W Address FFBh Bit 2 Description [7:0] Flash Frequency High Byte FFREQL Low byte of the 16-bit Flash frequency value. PS025114-1314 Flash Control Register Definitions Z8 Encore!® F0830 Series Product Specification 124 Flash Option Bits Programmable Flash option bits allow user configuration of certain aspects of Z8 Encore! F0830 Series operation. The feature configuration data is stored in the Flash program memory and read during reset. The features available for control through the Flash option bits are: • • • • Watchdog Timer time-out response selection–interrupt or system reset • Voltage Brown-Out configuration always enabled or disabled during Stop Mode to reduce Stop Mode power consumption • OSCILLATOR Mode selection for high, medium and low power crystal oscillators or external RC oscillator • Factory trimming information for the Internal Precision Oscillator and VBO voltage Watchdog Timer enabled at reset The ability to prevent unwanted read access to user code in program memory The ability to prevent accidental programming and erasure of all or a portion of the user code in program memory Operation This section describes the type and configuration of the programmable Flash option bits. Option Bit Configuration by Reset Each time the Flash option bits are programmed or erased, the device must be reset for the change to be effective. During any Reset operation (system reset or Stop Mode Recovery), the Flash option bits are automatically read from Flash program memory and written to the Option Configuration registers, which control Z8 Encore! F0830 Series device operation. Option bit control is established before the device exits reset and the eZ8 CPU begins code execution. The Option Configuration registers are not part of the register file and are not accessible for read or write access. PS025114-1314 Flash Option Bits Z8 Encore!® F0830 Series Product Specification 125 Option Bit Types This section describes the two types of Flash option bits offered in the F0830 Series. User Option Bits The user option bits are contained in the first two bytes of program memory. User access to these bits is provided because these locations contain application specific device configurations. The information contained here is lost when page 0 of program memory is erased. Trim Option Bits The trim option bits are contained in the information page of the Flash memory. These bits are factory programmed values required to optimize the operation of onboard analog circuitry and cannot be permanently altered by the user. Program memory can be erased without endangering these values. It is possible to alter working values of these bits by accessing the trim bit address and data registers, but these working values are lost after a power loss. There are 32 bytes of trim data. To modify one of these values, the user code must first write a value between 00h and 1Fh into the Trim Bit Address Register. The next write to the Trim Bit Data Register changes the working value of the target trim data byte. Reading the trim data requires the user code to write a value between 00h and 1Fh into the Trim Bit Address Register. The next read from the Trim Bit Data Register returns the working value of the target trim data byte. Note: The trim address range is from information address 20–3F only. The remaining information page is not accessible via the Trim Bit Address and Data registers. During reset, the first 43 system clock cycles perform 43 Flash accesses. The six bits of the counter provide the lower six bits of the Flash memory address. All other address bits are set to 0. The option bit registers use the 6-bit address from the counter as an address and latch the data from the Flash on the positive edge of the IPO clock, allowing for a maximum of 344 bits (43 bytes) of option information to be read from Flash. Because option information is stored in both the first two bytes of program memory and in the information area of Flash memory, the data must be placed in specific locations to be read correctly. In this case, the first two bytes at addresses 0 and 1 in program memory are read out and the remainder of the bytes are read out of the Flash information area. PS025114-1314 Operation Z8 Encore!® F0830 Series Product Specification 126 Flash Option Bit Control Register Definitions This section briefly describes the features of the Trim Bit Address and Data registers. Trim Bit Address Register The Trim Bit Address Register, shown in Table 78, contains the target address to access the trim option bits. Trim bit addresses in the range 00h–1Fh map to the information area at addresses 20h–3Fh, as shown in Table 79. Table 78. Trim Bit Address Register (TRMADR) Bit 7 6 Field RESET R/W 5 4 3 2 1 0 TRMADR: Trim Bit Address (00h to 1Fh) 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FF6h Table 79. Trim Bit Address Map Trim Bit Address Information Area Address 00h 20h 01h 21h 02h 22h 03h 23h : : 1Fh 3Fh Trim Bit Data Register The Trim Bit Data Register, shown in Table 80, contains the read or write data to access the trim option bits. PS025114-1314 Flash Option Bit Control Register Definitions Z8 Encore!® F0830 Series Product Specification 127 Table 80. Trim Bit Data Register (TRMDR) Bit 7 6 5 Field RESET R/W 4 3 2 1 0 TRMDR: Trim Bit Data 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FF7h Flash Option Bit Address Space The first two bytes of Flash program memory at addresses 0000h and 0001h are reserved for the user-programmable Flash option bits. See Tables 81 and 82. Table 81. Flash Option Bits at Program Memory Address 0000h Bit Field 7 WDT_RES WDT_AO RESET R/W 6 5 4 OSC_SEL[1:0] 3 2 1 0 VBO_AO FRP Reserved FWP U U U U U U U U R/W R/W R/W R/W R/W R/W R/W R/W Address Program Memory 0000h Note: U = Unchanged by Reset. R/W = Read/Write. Bit Description [7] WDT_RES Watchdog Timer Reset 0 = Watchdog Timer time-out generates an interrupt request. Interrupts must be globally enabled for the eZ8 CPU to acknowledge the interrupt request. 1 = Watchdog Timer time-out causes a system reset. This is the default setting for unprogrammed (erased) Flash. [6] WDT_AO Watchdog Timer Always On 0 = On application of system power, Watchdog Timer is automatically enabled. Watchdog Timer cannot be disabled. 1 = Watchdog Timer is enabled on execution of the WDT instruction. Once enabled, the Watchdog Timer can only be disabled by a reset. This is the default setting for unprogrammed (erased) Flash. [5:4] OSC_SEL OSCILLATOR Mode Selection 00 = On-chip oscillator configured for use with external RC networks ( VPOR; TPOR Digital Reset delay follows TANA Note: 1Data in the typical column is from characterization at 3.3 V and 0°C. These values are provided for design guidance only and are not tested in production. PS025114-1314 On-Chip Peripheral AC and DC Electrical Z8 Encore!® F0830 Series Product Specification 191 Table 118. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing TA = 0°C to +70°C TA = –40°C to +105°C Min Typ1 Power-On Reset Digital Delay TBD TPOR Power-On Reset Digital Delay TSMR Max Units Conditions 13 TBD µs 66 Internal Precision Oscillator cycles TBD 8 TBD ms 5000 Internal Precision Oscillator cycles Stop Mode Recovery with crystal oscillator disabled TBD 13 TBD µs 66 Internal Precision Oscillator cycles TSMR Stop Mode Recovery with crystal oscillator enabled TBD 8 TBD ms 5000 Internal Precision Oscillator cycles TVBO Voltage Brown-Out Pulse Rejection Period – 10 – µs VDD < VVBO to generate a Reset. TRAMP Time for VDD to transition from VSS to VPOR to ensure valid Reset 0.10 – 100 ms Symbol Parameter TPOR Min Typ Max Note: 1Data in the typical column is from characterization at 3.3 V and 0°C. These values are provided for design guidance only and are not tested in production. PS025114-1314 On-Chip Peripheral AC and DC Electrical Z8 Encore!® F0830 Series Product Specification 192 Table 119. Flash Memory Electrical Characteristics and Timing VDD = 2.7 to 3.6 V TA = 0°C to +70°C Min Min Typ Max Flash Byte Read Time 50 – – ns Flash Byte Program Time 20 – – µs Flash Page Erase Time 50 – – ms Flash Mass Erase Time 50 – – ms Writes to Single Address Before Next Erase – – 2 Flash Row Program Time – – 8 Data Retention 10 – – years 25°C 10,000 – – cycles Program/erase cycles Parameter Typ Max VDD = 2.7 to 3.6 V TA = –40°C to +105°C Endurance Units Notes ms Cumulative program time for single row cannot exceed limit before next erase. This parameter is only an issue when bypassing the Flash Controller. Table 120. Watchdog Timer Electrical Characteristics and Timing VDD = 2.7 to 3.6 V TA = 0°C to +70°C Symbol Parameter Min Typ Max VDD = 2.7 - 3.6 V TA = –40°C to +105°C Min Active power consumption FWDT WDT oscillator frequency PS025114-1314 2.5 Typ Max Units Conditions 2 3 µA 5 7.5 kHz On-Chip Peripheral AC and DC Electrical Z8 Encore!® F0830 Series Product Specification 193 Table 121. Nonvolatile Data Storage VDD = 2.7 to 3.6 V TA = 0°C to +70°C Min Min Typ Max NVDS Byte Read Time 71 – 258 µs With system clock at 20 MHz NVDS Byte Program Time 126 – 136 µs With system clock at 20 MHz Data Retention 10 – – years 25°C 100,000 – – cycles Cumulative write cycles for entire memory Parameter Typ Max VDD = 2.7 to 3.6 V TA = –40°C to +105°C Endurance Note: Units Notes For every 200 writes, a maintenance operation is necessary. In this rare occurrence, the write can take up to 58 ms to complete. Table 122. Analog-to-Digital Converter Electrical Characteristics and Timing VDD = 2.7 to 3.6 V TA = 0°C to +70°C Symbol Parameter Min Typ Max VDD = 2.7 to 3.6 V TA = –40°C to +105°C Min Typ Max Resolution – 10 – bits Differential Nonlinearity (DNL) 1 –1 – +4 LSB Integral Nonlinearity (INL) 1 –5 – +5 LSB Gain Error Offset Error VREF On chip reference Active Power Consumption Power Down Current 15 Units Conditions LSB –15 – 15 LSB PDIP package –9 – 9 LSB Other packages 1.9 2.0 2.1 V 4 mA 1 µA Note: 1When the input voltage is lower than 20 mV, the conversion error is out of spec. PS025114-1314 On-Chip Peripheral AC and DC Electrical Z8 Encore!® F0830 Series Product Specification 194 Table 122. Analog-to-Digital Converter Electrical Characteristics and Timing (Continued) VDD = 2.7 to 3.6 V TA = 0°C to +70°C Min Typ Max VDD = 2.7 to 3.6 V TA = –40°C to +105°C Min Typ Max Symbol Parameter ZIN Input Impedance 10 VIN Input Voltage Range 0 2.0 0 0.9*VD D Conversion Time Units Conditions MΩ 11.9 V External reference µs Input Bandwidth 500 KHz Wake Up Time 0.02 ms 10 Input Clock Duty 45 50 Maximum Input Clock Frequency Internal reference 20 MHz (ADC Clock) Internal reference External reference 55 20 MHz Note: 1When the input voltage is lower than 20 mV, the conversion error is out of spec. Table 123. Comparator Electrical Characteristics VDD = 2.7 to 3.6V TA = 0°C to +70°C VDD = 2.7 to 3.6V TA = –40°C to +105°C Symbol Parameter VOS Input DC Offset VCREF Programmable Internal Reference Voltage Range 0 VCREF Programmable internal reference voltage 0.92 TPROP Propagation delay VHYS Input hysteresis PS025114-1314 Min Typ Max Min Typ Max 5 1.0 Units Conditions mV 1.8 V User-programmable in 200 mV step 1.08 V Default (CMP0[REFLVL] =5h) 100 ns 8 mV On-Chip Peripheral AC and DC Electrical Z8 Encore!® F0830 Series Product Specification 195 General Purpose I/O Port Input Data Sample Timing Figure 33 displays timing of the GPIO port input sampling. The input value on a GPIO port pin is sampled on the rising edge of the system clock. The port value is available to the eZ8 CPU on the second rising clock edge following the change of the port value. TCLK System Clock Port Value Changes to 0 Port Pin Input Value Port Input Data Register Latch 0 Latched Into Port Input Data Register Port Input Data Register Value 0 Read by eZ8 Port Input Data Read on Data Bus Figure 33. Port Input Sample Timing Table 124. GPIO Port Input Timing Delay (ns) Parameter Abbreviation Minimum Maximum TS_PORT Port Input Transition to XIN Rise Setup Time (not pictured) 5 – TH_PORT XIN Rise to Port Input Transition Hold Time (not pictured) 0 – TSMR GPIO port pin pulse width to ensure Stop Mode Recovery (for GPIO port pins enabled as SMR sources) PS025114-1314 1 µs On-Chip Peripheral AC and DC Electrical Z8 Encore!® F0830 Series Product Specification 196 General Purpose I/O Port Output Timing Figure 34 and Table 125 provide timing information for the GPIO port pins. TCLK XIN T1 T2 Port Output Figure 34. GPIO Port Output Timing Table 125. GPIO Port Output Timing Delay (ns) Parameter Abbreviation Minimum Maximum GPIO Port Pins T1 XIN Rise to Port Output Valid Delay – 15 T2 XIN Rise to Port Output Hold Time 2 – PS025114-1314 On-Chip Peripheral AC and DC Electrical Z8 Encore!® F0830 Series Product Specification 197 On-Chip Debugger Timing Figure 35 and Table 126 provide timing information for the DBG pin. The DBG pin timing specifications assume a 4 ns maximum rise and fall time. TCLK XIN T1 T2 DBG (Output) Output Data T3 DBG (Input) T4 Input Data Figure 35. On-Chip Debugger Timing Table 126. On-Chip Debugger Timing Delay (ns) Parameter Abbreviation Minimum Maximum DBG T1 XIN Rise to DBG Valid Delay – 15 T2 XIN Rise to DBG Output Hold Time 2 – T3 DBG to XIN Rise Input Setup Time 5 – T4 DBG to XIN Rise Input Hold Time 5 – PS025114-1314 On-Chip Peripheral AC and DC Electrical Z8 Encore!® F0830 Series Product Specification 198 Table 127. Power Consumption Reference Table Power Consumption Category Block Logic CPU/Peripherals @ 20 MHz Flash Flash @ 20 MHz ADC @ 20 MHz Analog Typical Maximum 5 mA 12 mA 4 mA 4.5 mA IPO 350 µA 400 µA Comparator @ 10 MHz 330 µA 450 µA POR & VBO 120 µA 150 µA WDT Oscillator 2 µA 3 µA OSC @ 20 MHz 600 µA 900 µA Clock Filter 120µA 150 µA Note: The values in this table are subject to change after characterization. Figure 36. Flash Current Diagram PS025114-1314 On-Chip Peripheral AC and DC Electrical Z8 Encore!® F0830 Series Product Specification 199 Packaging Zilog’s F0830 Series of MCUs includes the Z8F0130, Z8F0131, Z8F0230, Z8F0231, Z8F1232 and Z8F1233 devices, which are available in the following packages: • • • • • • • • 20-Pin Quad Flat No-Lead Package (QFN) 20-pin Small Outline Integrated Circuit Package (SOIC) 20-pin Plastic Dual-Inline Package (PDIP) 20-pin Small Shrink Outline Package (SSOP) 28-Pin Quad Flat No-Lead Package (QFN) 28-pin Small Outline Integrated Circuit Package (SOIC) 28-pin Plastic Dual-Inline Package (PDIP) 28-pin Small Shrink Outline Package (SSOP) Current diagrams for each of these packages are published in Zilog’s Packaging Product Specification (PS0072), which is available free for download from the Zilog website. PS025114-1314 Packaging Z8 Encore!® F0830 Series Product Specification 200 Ordering Information Order your F0830 Series products from Zilog using the part numbers shown in Table 128. For more information about ordering, please consult your local Zilog sales office. The Sales Location page on the Zilog website lists all regional offices. Table 128. Z8 Encore! XP F0830 Series Ordering Matrix Part Number Flash RAM NVDS ADC Channels Description Z8 Encore! F0830 Series MCUs with 12 KB Flash Standard Temperature: 0°C to 70°C Z8F1232SH020SG 12 KB 256 No 7 SOIC 20-pin Z8F1232HH020SG 12 KB 256 No 7 SSOP 20-pin Z8F1232PH020SG 12 KB 256 No 7 PDIP 20-pin Z8F1232QH020SG 12 KB 256 No 7 QFN 20-pin Z8F1233SH020SG 12 KB 256 No 0 SOIC 20-pin Z8F1233HH020SG 12 KB 256 No 0 SSOP 20-pin Z8F1233PH020SG 12 KB 256 No 0 PDIP 20-pin Z8F1233QH020SG 12 KB 256 No 0 QFN 20-pin Z8F1232SJ020SG 12 KB 256 No 8 SOIC 28-pin Z8F1232HJ020SG 12 KB 256 No 8 SSOP 28-pin Z8F1232PJ020SG 12 KB 256 No 8 PDIP 28-pin Z8F1232QJ020SG 12 KB 256 No 8 QFN 28-pin Z8F1233SJ020SG 12 KB 256 No 0 SOIC 28-pin Z8F1233HJ020SG 12 KB 256 No 0 SSOP 28-pin Z8F1233PJ020SG 12 KB 256 No 0 PDIP 28-pin Z8F1233QJ020SG 12 KB 256 No 0 QFN 28-pin Extended Temperature: –40°C to 105°C Z8F1232SH020EG 12 KB 256 No 7 SOIC 20-pin Z8F1232HH020EG 12 KB 256 No 7 SSOP 20-pin Z8F1232PH020EG 12 KB 256 No 7 PDIP 20-pin Z8F1232QH020EG 12 KB 256 No 7 QFN 20-pin Z8F1233SH020EG 12 KB 256 No 0 SOIC 20-pin Z8F1233HH020EG 12 KB 256 No 0 SSOP 20-pin Z8F1233PH020EG 12 KB 256 No 0 PDIP 20-pin PS025114-1314 Ordering Information Z8 Encore!® F0830 Series Product Specification 201 Table 128. Z8 Encore! XP F0830 Series Ordering Matrix ADC Channels Description Part Number Flash RAM NVDS Z8F1233QH020EG 12 KB 256 No 0 QFN 20-pin Z8F1232SJ020EG 12 KB 256 No 8 SOIC 28-pin Z8F1232HJ020EG 12 KB 256 No 8 SSOP 28-pin Z8F1232PJ020EG 12 KB 256 No 8 PDIP 28-pin Z8F1232QJ020EG 12 KB 256 No 8 QFN 28-pin Z8F1233SJ020EG 12 KB 256 No 0 SOIC 28-pin Z8F1233HJ020EG 12 KB 256 No 0 SSOP 28-pin Z8F1233PJ020EG 12 KB 256 No 0 PDIP 28-pin Z8F1233QJ020EG 12 KB 256 No 0 QFN 28-pin Z8 Encore! F0830 with 8 KB Flash Standard Temperature: 0°C to 70°C Z8F0830SH020SG 8 KB 256 Yes 7 SOIC 20-pin Z8F0830HH020SG 8 KB 256 Yes 7 SSOP 20-pin Z8F0830PH020SG 8 KB 256 Yes 7 PDIP 20-pin Z8F0830QH020SG 8 KB 256 Yes 7 QFN 20-pin Z8F0831SH020SG 8 KB 256 Yes 0 SOIC 20-pin Z8F0831HH020SG 8 KB 256 Yes 0 SSOP 20-pin Z8F0831PH020SG 8 KB 256 Yes 0 PDIP 20-pin Z8F0831QH020SG 8 KB 256 Yes 0 QFN 20-pin Z8F0830SJ020SG 8 KB 256 Yes 8 SOIC 28-pin Z8F0830HJ020SG 8 KB 256 Yes 8 SSOP 28-pin Z8F0830PJ020SG 8 KB 256 Yes 8 PDIP 28-pin Z8F0830QJ020SG 8 KB 256 Yes 8 QFN 28-pin Z8F0831SJ020SG 8 KB 256 Yes 0 SOIC 28-pin Z8F0831HJ020SG 8 KB 256 Yes 0 SSOP 28-pin Z8F0831PJ020SG 8 KB 256 Yes 0 PDIP 28-pin Z8F0831QJ020SG 8 KB 256 Yes 0 QFN 28-pin Extended Temperature: –40°C to 105°C Z8F0830SH020EG 8 KB 256 Yes 7 SOIC 20-pin Z8F0830HH020EG 8 KB 256 Yes 7 SSOP 20-pin Z8F0830PH020EG 8 KB 256 Yes 7 PDIP 20-pin Z8F0830QH020EG 8 KB 256 Yes 7 QFN 20-pin Z8F0831SH020EG 8 KB 256 Yes 0 SOIC 20-pin PS025114-1314 Ordering Information Z8 Encore!® F0830 Series Product Specification 202 Table 128. Z8 Encore! XP F0830 Series Ordering Matrix Part Number ADC Channels Description Flash RAM NVDS Z8F0831HH020EG 8 KB 256 Yes 0 SSOP 20-pin Z8F0831PH020EG 8 KB 256 Yes 0 PDIP 20-pin Z8F0831QH020EG 8 KB 256 Yes 0 QFN 20-pin Z8F0830SJ020EG 8 KB 256 Yes 8 SOIC 28-pin Z8F0830HJ020EG 8 KB 256 Yes 8 SSOP 28-pin Z8F0830PJ020EG 8 KB 256 Yes 8 PDIP 28-pin Z8F0830QJ020EG 8 KB 256 Yes 8 QFN 28-pin Z8F0831SJ020EG 8 KB 256 Yes 0 SOIC 28-pin Z8F0831HJ020EG 8 KB 256 Yes 0 SSOP 28-pin Z8F0831PJ020EG 8 KB 256 Yes 0 PDIP 28-pin Z8F0831QJ020EG 8 KB 256 Yes 0 QFN 28-pin Z8 Encore! F0830 with 4 KB Flash Standard Temperature: 0°C to 70°C Z8F0430SH020SG 4 KB 256 Yes 7 SOIC 20-pin Z8F0430HH020SG 4 KB 256 Yes 7 SSOP 20-pin Z8F0430PH020SG 4 KB 256 Yes 7 PDIP 20-pin Z8F0430QH020SG 4 KB 256 Yes 7 QFN 20-pin Z8F0431SH020SG 4 KB 256 Yes 0 SOIC 20-pin Z8F0431HH020SG 4 KB 256 Yes 0 SSOP 20-pin Z8F0431PH020SG 4 KB 256 Yes 0 PDIP 20-pin Z8F0431QH020SG 4 KB 256 Yes 0 QFN 20-pin Z8F0430SJ020SG 4 KB 256 Yes 8 SOIC 28-pin Z8F0430HJ020SG 4 KB 256 Yes 8 SSOP 28-pin Z8F0430PJ020SG 4 KB 256 Yes 8 PDIP 28-pin Z8F0430QJ020SG 4 KB 256 Yes 8 QFN 28-pin Z8F0431SJ020SG 4 KB 256 Yes 0 SOIC 28-pin Z8F0431HJ020SG 4 KB 256 Yes 0 SSOP 28-pin Z8F0431PJ020SG 4 KB 256 Yes 0 PDIP 28-pin Z8F0431QJ020SG 4 KB 256 Yes 0 QFN 28-pin Extended Temperature: –40°C to 105°C Z8F0430SH020EG 4 KB 256 Yes 7 SOIC 20-pin Z8F0430HH020EG 4 KB 256 Yes 7 SSOP 20-pin Z8F0430PH020EG 4 KB 256 Yes 7 PDIP 20-pin PS025114-1314 Ordering Information Z8 Encore!® F0830 Series Product Specification 203 Table 128. Z8 Encore! XP F0830 Series Ordering Matrix Part Number ADC Channels Description Flash RAM NVDS Z8F0430QH020EG 4 KB 256 Yes 7 QFN 20-pin Z8F0431SH020EG 4 KB 256 Yes 0 SOIC 20-pin Z8F0431HH020EG 4 KB 256 Yes 0 SSOP 20-pin Z8F0431PH020EG 4 KB 256 Yes 0 PDIP 20-pin Z8F0431QH020EG 4 KB 256 Yes 0 QFN 20-pin Z8F0430SJ020EG 4 KB 256 Yes 8 SOIC 28-pin Z8F0430HJ020EG 4 KB 256 Yes 8 SSOP 28-pin Z8F0430PJ020EG 4 KB 256 Yes 8 PDIP 28-pin Z8F0430QJ020EG 4 KB 256 Yes 8 QFN 28-pin Z8F0431SJ020EG 4 KB 256 Yes 0 SOIC 28-pin Z8F0431HJ020EG 4 KB 256 Yes 0 SSOP 28-pin Z8F0431PJ020EG 4 KB 256 Yes 0 PDIP 28-pin Z8F0431QJ020EG 4 KB 256 Yes 0 QFN 28-pin Z8 Encore! F0830 with 2 KB Flash Standard Temperature: 0°C to 70°C Z8F0230SH020SG 2 KB 256 Yes 7 SOIC 20-pin Z8F0230HH020SG 2 KB 256 Yes 7 SSOP 20-pin Z8F0230PH020SG 2 KB 256 Yes 7 PDIP 20-pin Z8F0230QH020SG 2 KB 256 Yes 7 QFN 20-pin Z8F0231SH020SG 2 KB 256 Yes 0 SOIC 20-pin Z8F0231HH020SG 2 KB 256 Yes 0 SSOP 20-pin Z8F0231PH020SG 2 KB 256 Yes 0 PDIP 20-pin Z8F0231QH020SG 2 KB 256 Yes 0 QFN 20-pin Z8F0230SJ020SG 2 KB 256 Yes 8 SOIC 28-pin Z8F0230HJ020SG 2 KB 256 Yes 8 SSOP 28-pin Z8F0230PJ020SG 2 KB 256 Yes 8 PDIP 28-pin Z8F0230QJ020SG 2 KB 256 Yes 8 QFN 28-pin Z8F0231SJ020SG 2 KB 256 Yes 0 SOIC 28-pin Z8F0231HJ020SG 2 KB 256 Yes 0 SSOP 28-pin Z8F0231PJ020SG 2 KB 256 Yes 0 PDIP 28-pin Z8F0231QJ020SG 2 KB 256 Yes 0 QFN 28-pin PS025114-1314 Ordering Information Z8 Encore!® F0830 Series Product Specification 204 Table 128. Z8 Encore! XP F0830 Series Ordering Matrix Part Number Flash RAM NVDS ADC Channels Description Extended Temperature: –40°C to 105°C Z8F0230SH020EG 2 KB 256 Yes 7 SOIC 20-pin Z8F0230HH020EG 2 KB 256 Yes 7 SSOP 20-pin Z8F0230PH020EG 2 KB 256 Yes 7 PDIP 20-pin Z8F0230QH020EG 2 KB 256 Yes 7 QFN 20-pin Z8F0231SH020EG 2 KB 256 Yes 0 SOIC 20-pin Z8F0231HH020EG 2 KB 256 Yes 0 SSOP 20-pin Z8F0231PH020EG 2 KB 256 Yes 0 PDIP 20-pin Z8F0231QH020EG 2 KB 256 Yes 0 QFN 20-pin Z8F0230SJ020EG 2 KB 256 Yes 8 SOIC 28-pin Z8F0230HJ020EG 2 KB 256 Yes 8 SSOP 28-pin Z8F0230PJ020EG 2 KB 256 Yes 8 PDIP 28-pin Z8F0230QJ020EG 2 KB 256 Yes 8 QFN 28-pin Z8F0231SJ020EG 2 KB 256 Yes 0 SOIC 28-pin Z8F0231HJ020EG 2 KB 256 Yes 0 SSOP 28-pin Z8F0231PJ020EG 2 KB 256 Yes 0 PDIP 28-pin Z8F0231QJ020EG 2 KB 256 Yes 0 QFN 28-pin Z8 Encore! F0830 with 1KB Flash Standard Temperature: 0°C to 70°C Z8F0130SH020SG 1 KB 256 Yes 7 SOIC 20-pin Z8F0130HH020SG 1 KB 256 Yes 7 SSOP 20-pin Z8F0130PH020SG 1 KB 256 Yes 7 PDIP 20-pin Z8F0130QH020SG 1 KB 256 Yes 7 QFN 20-pin Z8F0131SH020SG 1 KB 256 Yes 0 SOIC 20-pin Z8F0131HH020SG 1 KB 256 Yes 0 SSOP 20-pin Z8F0131PH020SG 1 KB 256 Yes 0 PDIP 20-pin Z8F0131QH020SG 1 KB 256 Yes 0 QFN 20-pin Z8F0130SJ020SG 1 KB 256 Yes 8 SOIC 28-pin Z8F0130HJ020SG 1 KB 256 Yes 8 SSOP 28-pin Z8F0130PJ020SG 1 KB 256 Yes 8 PDIP 28-pin Z8F0130QJ020SG 1 KB 256 Yes 8 QFN 28-pin Z8F0131SJ020SG 1 KB 256 Yes 0 SOIC 28-pin Z8F0131HJ020SG 1 KB 256 Yes 0 SSOP 28-pin PS025114-1314 Ordering Information Z8 Encore!® F0830 Series Product Specification 205 Table 128. Z8 Encore! XP F0830 Series Ordering Matrix Part Number ADC Channels Description Flash RAM NVDS Z8F0131PJ020SG 1 KB 256 Yes 0 PDIP 28-pin Z8F0131QJ020SG 1 KB 256 Yes 0 QFN 28-pin Extended Temperature: –40°C to 105°C Z8F0130SH020EG 1 KB 256 Yes 7 SOIC 20-pin Z8F0130HH020EG 1 KB 256 Yes 7 SSOP 20-pin Z8F0130PH020EG 1 KB 256 Yes 7 PDIP 20-pin Z8F0130QH020EG 1 KB 256 Yes 7 QFN 20-pin Z8F0131SH020EG 1 KB 256 Yes 0 SOIC 20-pin Z8F0131HH020EG 1 KB 256 Yes 0 SSOP 20-pin Z8F0131PH020EG 1 KB 256 Yes 0 PDIP 20-pin Z8F0131QH020EG 1 KB 256 Yes 0 QFN 20-pin Z8F0130SJ020EG 1 KB 256 Yes 8 SOIC 28-pin Z8F0130HJ020EG 1 KB 256 Yes 8 SSOP 28-pin Z8F0130PJ020EG 1 KB 256 Yes 8 PDIP 28-pin Z8F0130QJ020EG 1 KB 256 Yes 8 QFN 28-pin Z8F0131SJ020EG 1 KB 256 Yes 0 SOIC 28-pin Z8F0131HJ020EG 1 KB 256 Yes 0 SSOP 28-pin Z8F0131PJ020EG 1 KB 256 Yes 0 PDIP 28-pin Z8F0131QJ020EG 1 KB 256 Yes 0 QFN 28-pin ZUSBSC00100ZACG USB Smart Cable Accessory Kit ZUSBOPTSC01ZACG Opto-Isolated USB Smart Cable Accessory Kit Part Number Suffix Designations Zilog part numbers consist of a number of components, as indicated in the following example. Example. Part number Z8F0830SH020SG is an 8-bit 20 MHz Flash MCU with 8 KB Pro- gram Memory and equipped with ADC and NVDS in a 20-pin SOIC package, operating within a 0ºC to +70ºC temperature range and built using lead-free solder. PS025114-1314 Part Number Suffix Designations Z8 Encore!® F0830 Series Product Specification 206 Z8 F 08 30 S H 020 S G Environmental Flow G = Green Plastic Packaging Compound Temperature Range S = Standard, 0°C to 70°C E = Extended, –40°C to +105°C Speed 020 = 20 MHz Pin Count* H = 20 J = 28 Package* P = PDIP Q = QFN S = SOIC H = SSOP Device Type 30 = Equipped with ADC and with NVDS. 31 = Equipped without ADC and with NVDS. 32 = Equipped with ADC and without NVDS (12 K version only). 33 = Equipped without ADC and without NVDS (12 K version only). Memory Size 12 = 12 KB Flash 08 = 8 KB Flash 04 = 4 KB Flash 02 = 2 KB Flash 01 = 1 KB Flash Memory Type F = Flash Device Family Z8 = Zilog’s 8-bit microcontroller PS025114-1314 Part Number Suffix Designations Z8 Encore!® F0830 Series Product Specification 207 Table 129 lists the pin count by package. Table 129. Package and Pin Count Description Pin Count PS025114-1314 Package 20 28 PDIP √ √ QFN √ √ SOIC √ √ SSOP √ √ Part Number Suffix Designations Z8 Encore!® F0830 Series Product Specification 208 Appendix A. Register Tables For the reader’s convenience, this appendix lists all F0830 Series registers numerically by hexadecimal address. General Purpose RAM In the F0830 Series, the 000–EFF hexadecimal address range is partitioned for generalpurpose random access memory, as follows. Hex Addresses: 000–0FF This address range is reserved for general-purpose register file RAM. For more details, see the Register File section on page 14. Hex Addresses: 100–EFF This address range is reserved. Timer 0 For more information about these Timer Control registers, see the Timer Control Register Definitions section on page 83. Hex Address: F00 Table 130. Timer 0 High Byte Register (T0H) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 TH 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address PS025114-1314 F00h General Purpose RAM Z8 Encore!® F0830 Series Product Specification 209 Hex Address: F01 Table 131. Timer 0 Low Byte Register (T0L) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 TL 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W Address F01h Hex Address: F02 Table 132. Timer 0 Reload High Byte Register (T0RH) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 TRH 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Address F02h Hex Address: F03 Table 133. Timer 0 Reload Low Byte Register (T0RL) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 TRL 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Address F03h Hex Address: F04 Table 134. Timer 0 PWM High Byte Register (T0PWMH) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 PWMH 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address PS025114-1314 F04h Timer 0 Z8 Encore!® F0830 Series Product Specification 210 Hex Address: F05 Table 135. Timer 0 PWM Low Byte Register (T0PWML) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 PWML 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 1 0 Address F05h Hex Address: F06 Table 136. Timer 0 Control Register 0 (T0CTL0) Bit Field RESET R/W 7 TMODEHI 6 5 TICONFIG 4 3 Reserved 2 PWMD INPCAP 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 1 0 Address F06h Hex Address: F07 Table 137. Timer 0 Control Register 1 (T0CTL1) Bit Field RESET R/W 7 6 5 4 3 2 TEN TPOL 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PRES Address TMODE F07h Hex Address: F08 Table 138. Timer 1 High Byte Register (T1H) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 TH 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address PS025114-1314 F08h Timer 0 Z8 Encore!® F0830 Series Product Specification 211 Hex Address: F09 Table 139. Timer 1 Low Byte Register (T1L) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 TL 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W Address F09h Hex Address: F0A Table 140. Timer 1 Reload High Byte Register (T1RH) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 TRH 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Address F0Ah Hex Address: F0B Table 141. Timer 1 Reload Low Byte Register (T1RL) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 TRL 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Address F0Bh Hex Address: F0C Table 142. Timer 1 PWM High Byte Register (T1PWMH) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 PWMH 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address PS025114-1314 F0Ch Timer 0 Z8 Encore!® F0830 Series Product Specification 212 Hex Address: F0D Table 143. Timer 1 PWM Low Byte Register (T1PWML) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 PWML 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 1 0 Address F0Dh Hex Address: F0E Table 144. Timer 1 Control Register 0 (T1CTL0) Bit Field RESET R/W 7 TMODEHI 6 5 TICONFIG 4 3 Reserved 2 PWMD INPCAP 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 1 0 Address F0Eh Hex Address: F0F Table 145. Timer 1 Control Register 1 (T1CTL1) Bit Field RESET R/W 7 6 5 4 3 2 TEN TPOL 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PRES Address TMODE F0Fh Hex Addresses: F10–F6F This address range is reserved. PS025114-1314 Timer 0 Z8 Encore!® F0830 Series Product Specification 213 Analog-to-Digital Converter For more information about these ADC registers, see the ADC Control Register Definitions section on page 101. Hex Address: F70 Table 146. ADC Control Register 0 (ADCCTL0) Bit Field RESET R/W 7 6 5 4 3 START Reserved REFEN ADCEN Reserved 0 0 0 0 0 0 0 0 R/W1 R/W R/W R/W R/W R/W R/W R/W Address 2 1 0 ANAIN[2:0] F70h Bit Description [7] START ADC Start/Busy 0 = Writing to 0 has no effect; reading a 0 indicates that the ADC is available to begin a conversion. 1 = Writing to 1 starts a conversion; reading a 1 indicates that a conversion is currently in progress. [6] This bit is reserved and must be programmed to 0. [5] REFEN Reference Enable 0 = Internal reference voltage is disabled allowing an external reference voltage to be used by the ADC. 1 = Internal reference voltage for the ADC is enabled. The internal reference voltage can be measured on the VREF pin. [4] ADCEN ADC Enable 0 = ADC is disabled for low power operation. 1 = ADC is enabled for normal use. [3] This bit is reserved and must be programmed to 0. [2:0] ANAIN Analog Input Select 000 = ANA0 input is selected for analog to digital conversion. 001 = ANA1 input is selected for analog to digital conversion. 010 = ANA2 input is selected for analog to digital conversion. 011 = ANA3 input is selected for analog to digital conversion. 100 = ANA4 input is selected for analog to digital conversion. 101 = ANA5 input is selected for analog to digital conversion. 110 = ANA6 input is selected for analog to digital conversion. 111 = ANA7 input is selected for analog to digital conversion. PS025114-1314 Analog-to-Digital Converter Z8 Encore!® F0830 Series Product Specification 214 Hex Address: F71 This address range is reserved. Hex Address: F72 Table 147. ADC Data High Byte Register (ADCD_H) Bit 7 6 5 4 Field 3 2 1 0 ADCDh RESET X R/W R Address F72h Bit Description [7:0] ADC High Byte 00h–FFh = The last conversion output is held in the data registers until the next ADC conversion is completed. Hex Address: F73 Table 148. ADC Data Low Bits Register (ADCD_L) Bit 7 Field 6 5 4 3 2 ADCDL Reserved RESET X X R/W R R Address 1 0 F73h Bit Position Description [7:6] ADC Low Bits 00–11b = These bits are the two least significant bits of the 10-bit ADC output. These bits are undefined after a reset. The low bits are latched into this register whenever the ADC Data High Byte Register is read. [5:0] Reserved These bits are reserved and must be programmed to 000000. PS025114-1314 Analog-to-Digital Converter Z8 Encore!® F0830 Series Product Specification 215 Hex Address: F74 Table 149. ADC Sample Settling Time (ADCSST) Bit 7 6 Field 5 4 3 2 1 0 1 1 2 1 0 1 1 1 Reserved RESET 0 R/W R SST 1 1 R/W Address F74h Bit Description [7:4] Reserved These bits are reserved and must be programmed to 0000. [3:0] SST Sample Settling Time 0h–Fh = Number of system clock periods to meet 0.5 µs minimum. Hex Address: F75 Table 150. ADC Sample Time (ADCST) Bit 7 Field 6 5 4 3 Reserved RESET 0 R/W ST 1 1 1 R/W Address R/W F75h Bit Description [7:6] Reserved This register is reserved and must be programmed to 0. [5:0] ST Sample/Hold Time 0h–Fh = Number of system clock periods to meet 1 µs minimum. Hex Addresses: F77–F7F This address range is reserved. PS025114-1314 Analog-to-Digital Converter Z8 Encore!® F0830 Series Product Specification 216 Low Power Control For more information about the Power Control Register, see the Power Control Register Definitions section on page 31. Hex Address: F80 Table 151. Power Control Register 0 (PWRCTL0) Bit 7 Field RESET R/W 6 5 Reserved 4 VBO 3 2 Reserved Reserved 1 0 COMP Reserved 1 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address F80h Hex Address: F81 This address range is reserved. LED Controller For more information about the LED Drive registers, see the GPIO Control Register Definitions section on page 39. Hex Address: F82 Table 152. LED Drive Enable (LEDEN) Bit 7 6 5 Field RESET R/W 4 3 2 1 0 LEDEN[7:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address PS025114-1314 F82h Low Power Control Z8 Encore!® F0830 Series Product Specification 217 Hex Address: F83 Table 153. LED Drive Level High Register (LEDLVLH) Bit 7 6 5 Field RESET R/W 4 3 2 1 0 LEDLVLH[7:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 2 1 0 Address F83h Hex Address: F84 Table 154. LED Drive Level Low Register (LEDLVLL) Bit 7 6 5 Field RESET R/W 4 3 LEDLVLL[7:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address F84h Hex Address: F85 This address range is reserved. Oscillator Control For more information about the Oscillator Control registers, see the Oscillator Control Register Definitions section on page 154. Hex Address: F86 Table 155. Oscillator Control Register (OSCCTL) Bit Field RESET R/W 7 6 5 4 3 INTEN XTLEN WDTEN POFEN WDFEN 1 0 1 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address PS025114-1314 2 1 0 SCKSEL F86h Oscillator Control Z8 Encore!® F0830 Series Product Specification 218 Hex Addresses: F87–F8F This address range is reserved. Comparator 0 For more information about the Comparator Register, see the Comparator Control Register Definitions section on page 107. Hex Address: F90 Table 156. Comparator Control Register (CMP0) Bit Field RESET R/W 7 6 5 4 3 2 1 Reserved INNSEL 0 0 0 1 0 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W REFLVL Address 0 Reserved F90h Hex Addresses: F91–FBF This address range is reserved. Interrupt Controller For more information about the Interrupt Control registers, see the Interrupt Control Register Definitions section on page 57. Hex Address: FC0 Table 157. Interrupt Request 0 Register (IRQ0) Bit Field RESET R/W 7 6 5 Reserved T1I T0I 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address PS025114-1314 4 3 2 1 0 Reserved Reserved Reserved Reserved ADCI FC0h Comparator 0 Z8 Encore!® F0830 Series Product Specification 219 Hex Address: FC1 Table 158. IRQ0 Enable High Bit Register (IRQ0ENH) Bit Field RESET R/W 7 6 5 4 3 2 1 Reserved T1ENH T0ENH 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 1 0 Reserved Reserved Reserved Reserved Address 0 ADCENH FC1h Hex Address: FC2 Table 159. IRQ0 Enable Low Bit Register (IRQ0ENL) Bit 7 6 5 Reserved T1ENL T0ENL RESET 0 0 0 0 0 0 0 0 R/W R R/W R/W R/W R/W R R R/W Field 4 3 2 Reserved Reserved Reserved Reserved Address ADCENL FC2h Hex Address: FC3 Table 160. Interrupt Request 1 Register (IRQ1) Bit Field RESET R/W 7 6 5 4 3 2 1 0 PA7I PA6CI PA5I PA4I PA3I PA2I PA1I PA0I 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FC3h Hex Address: FC4 Table 161. IRQ1 Enable High Bit Register (IRQ1ENH) Bit Field RESET R/W 7 6 5 PA7ENH PA6CENH PA5ENH 4 3 2 1 0 PA4ENH PA3ENH PA2ENH PA1ENH PA0ENH 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address PS025114-1314 FC4h Interrupt Controller Z8 Encore!® F0830 Series Product Specification 220 Hex Address: FC5 Table 162. IRQ1 Enable Low Bit Register (IRQ1ENL) Bit Field RESET R/W 7 6 5 4 3 2 1 0 PA7ENL PA6CENL PA5ENL PA4ENL PA3ENL PA2ENL PA1ENL PA0ENL 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FC5h Hex Address: FC6 Table 163. Interrupt Request 2 Register (IRQ2) Bit 7 6 Field RESET R/W 5 4 Reserved 3 2 1 0 PC3I PC2I PC1I PC0I 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FC6h Hex Address: FC7 Table 164. IRQ2 Enable High Bit Register (IRQ2ENH) Bit 7 6 Field RESET R/W 5 4 Reserved 3 2 1 0 C3ENH C2ENH C1ENH C0ENH 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FC7h Hex Address: FC8 Table 165. IRQ2 Enable Low Bit Register (IRQ2ENL) Bit 7 6 Field RESET R/W 5 4 Reserved 3 2 1 0 C3ENL C2ENL C1ENL C0ENL 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address PS025114-1314 FC8h Interrupt Controller Z8 Encore!® F0830 Series Product Specification 221 Hex Addresses: FC9–FCC This address range is reserved. Hex Address: FCD Table 166. Interrupt Edge Select Register (IRQES) Bit Field RESET R/W 7 6 5 4 3 2 1 0 IES7 IES6 IES5 IES4 IES3 IES2 IES1 IES0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 2 1 0 Address FCDh Hex Address: FCE Table 167. Shared Interrupt Select Register (IRQSS) Bit Field RESET R/W 7 6 5 4 3 Reserved PA6CS 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 2 1 0 Reserved Address FCEh Hex Address: FCF Table 168. Interrupt Control Register (IRQCTL) Bit Field RESET R/W 7 6 5 4 IRQE 3 Reserved 0 0 0 0 0 0 0 0 R/W R R R R R R R Address PS025114-1314 FCFh Interrupt Controller Z8 Encore!® F0830 Series Product Specification 222 GPIO Port A For more information about the GPIO registers, see the GPIO Control Register Definitions section on page 39. Hex Address: FD0 Table 169. Port A GPIO Address Register (PAADDR) Bit 7 6 5 Field 4 2 1 0 R/W R/W R/W PADDR[7:0] RESET R/W 3 00h R/W R/W R/W R/W Address R/W FD0h Hex Address: FD1 Table 170. Port A Control Registers (PACTL) Bit 7 6 5 4 Field 2 1 0 R/W R/W R/W R/W PCTL RESET R/W 3 00h R/W R/W R/W R/W Address FD1h Hex Address: FD2 Table 171. Port A Input Data Registers (PAIN) Bit 7 6 5 4 3 2 1 0 PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 RESET X X X X X X X X R/W R R R R R R R R Field Address PS025114-1314 FD2h GPIO Port A Z8 Encore!® F0830 Series Product Specification 223 Hex Address: FD3 Table 172. Port A Output Data Register (PAOUT) Bit Field RESET R/W 7 6 5 4 3 2 1 0 POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 2 1 0 R/W R/W R/W Address FD3h Hex Address: FD4 Table 173. Port B GPIO Address Register (PBADDR) Bit 7 6 5 Field 4 PADDR[7:0] RESET R/W 3 00h R/W R/W R/W R/W Address R/W FD4h Hex Address: FD5 Table 174. Port B Control Registers (PBCTL) Bit 7 6 5 4 Field 2 1 0 R/W R/W R/W R/W PCTL RESET R/W 3 00h R/W R/W R/W R/W Address FD5h Hex Address: FD6 Table 175. Port B Input Data Registers (PBIN) Bit 7 6 5 4 3 2 1 0 PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 RESET X X X X X X X X R/W R R R R R R R R Field Address PS025114-1314 FD6h GPIO Port A Z8 Encore!® F0830 Series Product Specification 224 Hex Address: FD7 Table 176. Port B Output Data Register (PBOUT) Bit Field RESET R/W 7 6 5 4 3 2 1 0 POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 2 1 0 R/W R/W R/W Address FD7h Hex Address: FD8 Table 177. Port C GPIO Address Register (PCADDR) Bit 7 6 5 Field 4 PADDR[7:0] RESET R/W 3 00h R/W R/W R/W R/W Address R/W FD8h Hex Address: FD9 Table 178. Port C Control Registers (PCCTL) Bit 7 6 5 4 Field 2 1 0 R/W R/W R/W R/W PCTL RESET R/W 3 00h R/W R/W R/W R/W Address FD9h Hex Address: FDA Table 179. Port C Input Data Registers (PCIN) Bit 7 6 5 4 3 2 1 0 PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 RESET X X X X X X X X R/W R R R R R R R R Field Address PS025114-1314 FDAh GPIO Port A Z8 Encore!® F0830 Series Product Specification 225 Hex Address: FDB Table 180. Port C Output Data Register (PCOUT) Bit Field RESET R/W 7 6 5 4 3 2 1 0 POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 2 1 0 R/W R/W R/W Address FDBh Hex Address: FDC Table 181. Port D GPIO Address Register (PDADDR) Bit 7 6 5 Field 4 PADDR[7:0] RESET R/W 3 00h R/W R/W R/W R/W Address R/W FDCh Hex Address: FDD Table 182. Port D Control Registers (PDCTL) Bit 7 6 5 4 Field 2 1 0 R/W R/W R/W R/W PCTL RESET R/W 3 00h R/W R/W R/W Address R/W FDDh Hex Address: FDE This address range is reserved. PS025114-1314 GPIO Port A Z8 Encore!® F0830 Series Product Specification 226 Hex Address: FDF Table 183. Port D Output Data Register (PDOUT) Bit Field RESET R/W 7 6 5 4 3 2 1 0 POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FDFh Hex Addresses: FE0–FEF This address range is reserved. Watchdog Timer For more information about the Watchdog Timer registers, see the Watchdog Timer Control Register Definitions section on page 95. Hex Address: FF0 The Watchdog Timer Control Register address is shared with the read-only Reset Status Register. Table 184. Watchdog Timer Control Register (WDTCTL) Bit 7 6 5 Field 4 3 2 1 0 WDTUNLK RESET X X X X X X X X R/W W W W W W W W W 1 0 Address FF0h Table 185. Reset Status Register (RSTSTAT) Bit Field 7 6 5 4 POR STOP WDT EXT 3 2 Reserved RESET See Table 12 on page 29 0 0 0 0 0 R/W R R R R R R Address PS025114-1314 R R FF0h Watchdog Timer Z8 Encore!® F0830 Series Product Specification 227 Hex Address: FF1 Table 186. Watchdog Timer Reload Upper Byte Register (WDTU) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 WDTU 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Address FF1h Note: *Read returns the current WDT count value; write sets the appropriate reload value. Hex Address: FF2 Table 187. Watchdog Timer Reload High Byte Register (WDTH) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 WDTH 0 0 0 0 0 1 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Address FF2h Note: *Read returns the current WDT count value; write sets the appropriate reload value. Hex Address: FF3 Table 188. Watchdog Timer Reload Low Byte Register (WDTL) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 WDTL 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Address FF3h Note: *Read returns the current WDT count value; write sets the appropriate reload value. Hex Addresses: FF4–FF5 This address range is reserved. PS025114-1314 Watchdog Timer Z8 Encore!® F0830 Series Product Specification 228 Trim Bit Control For more information about the Trim Bit Control registers, see the Flash Option Bit Control Register Definitions section on page 126. Hex Address: FF6 Table 189. Trim Bit Address Register (TRMADR) Bit 7 6 5 Field RESET R/W 4 3 2 1 0 TRMADR - Trim Bit Address (00h to 1Fh) 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 2 1 0 Address FF6h Hex Address: FF7 Table 190. Trim Bit Data Register (TRMDR) Bit 7 6 5 Field RESET R/W 4 3 TRMDR - Trim Bit Data 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FF7h Flash Memory Controller For more information about the Flash Control registers, see the Flash Control Register Definitions section on page 118. Hex Address: FF8 Table 191. Flash Control Register (FCTL) Bit 7 6 5 4 Field 3 2 1 0 FCMD RESET 0 0 0 0 0 0 0 0 R/W W W W W W W W W Address PS025114-1314 FF8h Trim Bit Control Z8 Encore!® F0830 Series Product Specification 229 Hex Address: FF8 Table 192. Flash Status Register (FSTAT) Bit 7 Field 6 5 4 3 Reserved 2 1 0 FSTAT RESET 0 0 0 0 0 0 0 0 R/W R R R R R R R R Address FF8h Hex Address: FF9 The Flash Page Select Register is shared with the Flash Sector Protect Register. Table 193. Flash Page Select Register (FPS) Bit Field RESET R/W 7 6 5 4 3 INFO_EN 2 1 0 PAGE 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FF9h Table 194. Flash Sector Protect Register (FPROT) Bit Field RESET R/W 7 6 5 4 3 2 1 0 SPROT7 SPROT6 SPROT5 SPROT4 SPROT3 SPROT2 SPROT1 SPROT0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address FF9h Hex Address: FFA Table 195. Flash Frequency High Byte Register (FFREQH) Bit 7 6 5 4 Field RESET R/W 3 2 1 0 FFREQH 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address PS025114-1314 FFAh Flash Memory Controller Z8 Encore!® F0830 Series Product Specification 230 Hex Address: FFB Table 196. Flash Frequency Low Byte Register (FFREQL) Bit 7 Field RESET 6 5 4 3 1 0 FFREQL 0 R/W R/W Address FFBh PS025114-1314 2 Flash Memory Controller Z8 Encore!® F0830 Series Product Specification 231 Index Numerics 10-bit ADC 4 A absolute maximum ratings 184 AC characteristics 189 ADC 166 block diagram 99 overview 98 ADC Channel Register 1 (ADCCTL) 102 ADC Data High Byte Register (ADCDH) 103 ADC Data Low Bit Register (ADCDL) 103, 104, 105 ADCX 166 ADD 166 add - extended addressing 166 add with carry 166 add with carry - extended addressing 166 additional symbols 165 address space 14 ADDX 166 analog block/PWM signal synchronization 100 analog block/PWM signal zynchronization 100 analog signals 11 analog-to-digital converter overview 98 AND 169 ANDX 169 architecture voltage measurements 98 arithmetic instructions 166 assembly language programming 162 assembly language syntax 163 B B 165 b 164 BCLR 167 PS025114-1314 binary number suffix 165 BIT 167 bit 164 clear 167 manipulation instructions 167 set 167 set or clear 167 swap 167 test and jump 169 test and jump if non-zero 169 test and jump if zero 169 bit jump and test if non-zero 166 bit swap 169 block diagram 3 block transfer instructions 167 BRK 169 BSET 167 BSWAP 167, 169 BTJ 169 BTJNZ 166, 169 BTJZ 169 C calibration and compensation, motor control measurements 101 CALL procedure 169 capture mode 89, 90 capture/compare mode 89 cc 164 CCF 168 characteristics, electrical 184 clear 168 CLR 168 COM 169 compare 89 compare - extended addressing 166 compare mode 89 compare with carry 166 compare with carry - extended addressing 166 PRELIMINARY Index Z8 Encore!® F0830 Series Product Specification 232 complement 169 complement carry flag 167, 168 condition code 164 continuous mode 89 Control Registers 14, 17 counter modes 89 CP 166 CPC 166 CPCX 166 CPU and peripheral overview 4 CPU control instructions 168 CPX 166 current measurement architecture 98 operation 99 Customer Feedback Form 239 Customer Information 239 D DA 164, 166 data memory 16 DC characteristics 185 debugger, on-chip 139 DEC 166 decimal adjust 166 decrement 166 decrement and jump non-zero 169 decrement word 166 DECW 166 destination operand 165 device, port availability 33 DI 168 direct address 164 disable interrupts 168 DJNZ 169 dst 165 E EI 168 electrical characteristics 184 GPIO input data sample timing 195 watch-dog timer 194 PS025114-1314 electrical noise 98 enable interrupt 168 ER 164 extended addressing register 164 external pin reset 25 eZ8 CPU features 4 eZ8 CPU instruction classes 166 eZ8 CPU instruction notation 164 eZ8 CPU instruction set 162 eZ8 CPU instruction summary 171 F FCTL register 119, 126, 127, 228 features, Z8 Encore! 1 first opcode map 182 FLAGS 165 flags register 165 flash controller 4 option bit address space 127 option bit configuration - reset 124 program memory address 0000h 127 program memory address 0001h 128 flash memory 108 byte programming 116 code protection 114 configurations 108 control register definitions 118, 126 controller bypass 117 flash control register 119, 126, 127, 228 flash option bits 115 flash status register 120 flow chart 113 frequency high and low byte registers 123 mass erase 117 operation 112 operation timing 114 page erase 117 page select register 121, 122 FPS register 121, 122 FSTAT register 120 PRELIMINARY Index Z8 Encore!® F0830 Series Product Specification 233 G gated mode 89 general-purpose I/O 33 GPIO 4, 33 alternate functions 34 architecture 34 control register definitions 39 input data sample timing 195 interrupts 39 port A-C pull-up enable sub-registers 46, 47, 48 port A-H address registers 40 port A-H alternate function sub-registers 42 port A-H control registers 41 port A-H data direction sub-registers 41 port A-H high drive enable sub-registers 44 port A-H input data registers 49 port A-H output control sub-registers 43 port A-H output data registers 50, 51 port A-H stop mode recovery sub-registers 45 port availability by device 33 port input timing 195 port output timing 196 H H 165 HALT 168 halt mode 31, 168 hexadecimal number prefix/suffix 165 I IM 164 immediate data 164 immediate operand prefix 165 INC 166 increment 166 increment word 167 INCW 167 indexed 165 indirect address prefix 165 indirect register 164 indirect register pair 164 PS025114-1314 indirect working register 164 indirect working register pair 164 instruction set, ez8 CPU 162 instructions ADC 166 ADCX 166 ADD 166 ADDX 166 AND 169 ANDX 169 arithmetic 166 BCLR 167 BIT 167 bit manipulation 167 block transfer 167 BRK 169 BSET 167 BSWAP 167, 169 BTJ 169 BTJNZ 166, 169 BTJZ 169 CALL 169 CCF 167, 168 CLR 168 COM 169 CP 166 CPC 166 CPCX 166 CPU control 168 CPX 166 DA 166 DEC 166 DECW 166 DI 168 DJNZ 169 EI 168 HALT 168 INC 166 INCW 167 IRET 169 JP 169 LD 168 LDC 168 LDCI 167, 168 PRELIMINARY Index Z8 Encore!® F0830 Series Product Specification 234 LDE 168 LDEI 167 LDX 168 LEA 168 load 168 logical 169 MULT 167 NOP 168 OR 169 ORX 169 POP 168 POPX 168 program control 169 PUSH 168 PUSHX 168 RCF 167, 168 RET 169 RL 169 RLC 169 rotate and shift 169 RR 170 RRC 170 SBC 167 SCF 167, 168 SRA 170 SRL 170 SRP 168 STOP 168 SUB 167 SUBX 167 SWAP 170 TCM 167 TCMX 167 TM 167 TMX 167 TRAP 169 watch-dog timer refresh 168 XOR 169 XORX 169 instructions, eZ8 classes of 166 interrupt control register 67 interrupt controller 53 architecture 53 interrupt assertion types 56 PS025114-1314 interrupt vectors and priority 56 operation 55 register definitions 57 software interrupt assertion 57 interrupt edge select register 65 interrupt request 0 register 58 interrupt request 1 register 59 interrupt request 2 register 60 interrupt return 169 interrupt vector listing 53 IR 164 Ir 164 IRET 169 IRQ0 enable high and low bit registers 60 IRQ1 enable high and low bit registers 62 IRQ2 enable high and low bit registers 63 IRR 164 Irr 164 J JP 169 jump, conditional, relative, and relative conditional 169 L LD 168 LDC 168 LDCI 167, 168 LDE 168 LDEI 167, 168 LDX 168 LEA 168 load 168 load constant 167 load constant to/from program memory 168 load constant with auto-increment addresses 168 load effective address 168 load external data 168 load external data to/from data memory and autoincrement addresses 167 load external to/from data memory and auto-increment addresses 168 PRELIMINARY Index Z8 Encore!® F0830 Series Product Specification 235 load instructions 168 load using extended addressing 168 logical AND 169 logical AND/extended addressing 169 logical exclusive OR 169 logical exclusive OR/extended addressing 169 logical instructions 169 logical OR 169 logical OR/extended addressing 169 low power modes 30 M master interrupt enable 55 memory data 16 program 15 mode capture 89, 90 capture/compare 89 continuous 89 counter 89 gated 89 one-shot 89 PWM 89, 90 modes 89 motor control measurements ADC Control register definitions 101 calibration and compensation 101 interrupts 101 overview 98 MULT 167 multiply 167 N noise, electrical 98 NOP (no operation) 168 notation b 164 cc 164 DA 164 ER 164 IM 164 PS025114-1314 IR 164 Ir 164 IRR 164 Irr 164 p 164 R 165 r 164 RA 165 RR 165 rr 165 vector 165 X 165 notational shorthand 164 O OCD architecture 139 auto-baud detector/generator 142 baud rate limits 142 block diagram 139 breakpoints 143 commands 144 control register 148 data format 142 DBG pin to RS-232 Interface 140 debug mode 141 debugger break 169 interface 140 serial errors 143 status register 150 timing 197 OCD commands execute instruction (12h) 148 read data memory (0Dh) 147 read OCD control register (05h) 146 read OCD revision (00H) 145 read OCD status register (02h) 145 read program counter (07h) 146 read program memory (0Bh) 147 read program memory CRC (0Eh) 147 read register (09h) 146 read runtime counter (03h) 145 step instruction (10H) 148 PRELIMINARY Index Z8 Encore!® F0830 Series Product Specification 236 stuff instruction (11h) 148 write data memory (0Ch) 147 write OCD control register (04h) 145 write program counter (06h) 146 write program memory (0Ah) 146 write register (08h) 146 on-chip debugger (OCD) 139 on-chip debugger signals 12 on-chip oscillator 157 one-shot mode 89 opcode map abbreviations 181 cell description 180 first 182 second after 1Fh 183 operation 100 current measurement 99 voltage measurement timing diagram 100 Operational Description 21, 30, 33, 53, 68, 92, 98, 106, 108, 124, 134, 139, 151, 157, 161 OR 169 ordering information 200 ORX 169 oscillator signals 12 P p 164 Packaging 199 part selection guide 2 PC 165 peripheral AC and DC electrical characteristics 190 pin characteristics 13 Pin Descriptions 7 polarity 164 POP 168 pop using extended addressing 168 POPX 168 port availability, device 33 port input timing (GPIO) 195 port output timing, GPIO 196 power supply signals 12 power-on reset (POR) 23 program control instructions 169 PS025114-1314 program counter 165 program memory 15 PUSH 168 push using extended addressing 168 PUSHX 168 PWM mode 89, 90 PxADDR register 40, 222, 223, 224, 225 PxCTL register 41, 222, 223, 224, 225 R R 165 r 164 RA register address 165 RCF 167, 168 register 165 flash control (FCTL) 119, 126, 127, 228 flash high and low byte (FFREQH and FREEQL) 123 flash page select (FPS) 121, 122 flash status (FSTAT) 120 GPIO port A-H address (PxADDR) 40, 222, 223, 224, 225 GPIO port A-H alternate function sub-registers 42 GPIO port A-H control address (PxCTL) 41, 222, 223, 224, 225 GPIO port A-H data direction sub-registers 41 OCD control 148 OCD status 150 watch-dog timer control (WDTCTL) 95, 107, 154, 217, 218, 226 watchdog timer control (WDTCTL) 29 watch-dog timer reload high byte (WDTH) 227 watchdog timer reload high byte (WDTH) 96 watch-dog timer reload low byte (WDTL) 227 watchdog timer reload low byte (WDTL) 97 watch-dog timer reload upper byte (WDTU) 227 watchdog timer reload upper byte (WDTU) 96 register file 14 register pair 165 register pointer 165 PRELIMINARY Index Z8 Encore!® F0830 Series Product Specification 237 registers ADC channel 1 102 ADC data high byte 103 ADC data low bit 103, 104, 105 reset and stop mode characteristics 22 and stop mode recovery 21 carry flag 167 sources 23 RET 169 return 169 RL 169 RLC 169 rotate and shift instuctions 169 rotate left 169 rotate left through carry 169 rotate right 170 rotate right through carry 170 RP 165 RR 165, 170 rr 165 RRC 170 S SBC 167 SCF 167, 168 second opcode map after 1Fh 183 set carry flag 167, 168 set register pointer 168 shift right arithmatic 170 shift right logical 170 signal descriptions 11 software trap 169 source operand 165 SP 165 SRA 170 src 165 SRL 170 SRP 168 stack pointer 165 STOP 168 stop mode 30, 168 stop mode recovery PS025114-1314 sources 26 using a GPIO port pin transition 27, 28 using watch-dog timer time-out 27 SUB 167 subtract 167 subtract - extended addressing 167 subtract with carry 167 subtract with carry - extended addressing 167 SUBX 167 SWAP 170 swap nibbles 170 symbols, additional 165 T Table 134. Power Consumption Reference Table 197 TCM 167 TCMX 167 test complement under mask 167 test complement under mask - extended addressing 167 test under mask 167 test under mask - extended addressing 167 tiing diagram, voltage measurement 100 timer signals 11 timers 68 architecture 68 block diagram 69 capture mode 77, 78, 89, 90 capture/compare mode 81, 89 compare mode 79, 89 continuous mode 70, 89 counter mode 71, 72 counter modes 89 gated mode 80, 89 one-shot mode 69, 89 operating mode 69 PWM mode 74, 75, 89, 90 reading the timer count values 82 reload high and low byte registers 85 timer control register definitions 83 timer output signal operation 82 timers 0-3 PRELIMINARY Index Z8 Encore!® F0830 Series Product Specification 238 control registers 87, 88 high and low byte registers 83, 86 TM 167 TMX 167 TRAP 169 XORX 169 Z Z8 Encore! block diagram 3 features 1 part selection guide 2 V vector 165 voltage brown-out reset (VBR) 24 voltage measurement timing diagram 100 W watch-dog timer approximate time-out delay 92 approximate time-out delays 92, 106, 134, 151, 161 CNTL 24 control register 95, 154 electrical characteristics and timing 194 interrupt in noromal operation 93 interrupt in stop mode 93 operation 92, 106, 134, 151, 161 refresh 93 reload unlock sequence 94 reload upper, high and low registers 96 reset 25 reset in normal operation 94 reset in Stop mode 94 time-out response 93 watchdog timer refresh 168 WDTCTL register 29, 95, 107, 154, 217, 218, 226 WDTH register 96, 227 WDTL register 97, 227 working register 164 working register pair 165 WTDU register 96, 227 X X 165 XOR 169 PS025114-1314 PRELIMINARY Index Z8 Encore!® F0830 Series Product Specification 239 Customer Support To share comments, get your technical questions answered or report issues you may be experiencing with our products, please visit Zilog’s Technical Support page at  http://support.zilog.com. To learn more about this product, find additional documentation or to discover other facets about Zilog product offerings, please visit the Zilog Knowledge Base at http://zilog.com/ kb or consider participating in the Zilog Forum at http://zilog.com/forum. This publication is subject to replacement by a later edition. To determine whether a later edition exists, please visit the Zilog website at http://www.zilog.com. PS025114-1314 Customer Support
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