High Performance 8-Bit Microcontrollers
Z8 Encore! XP® F0822
Series
Product Specification
PS022517-0508
®
Copyright ©2008 by Zilog , Inc. All rights reserved.
www.zilog.com
Z8 Encore! XP® F0822 Series
Product Specification
Warning: DO NOT USE IN LIFE SUPPORT
LIFE SUPPORT POLICY
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A
critical component is any component in a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system or to affect its safety or
effectiveness.
Document Disclaimer
©2008 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.
Z I L O G A L S O D O E S N O T A S S U M E L I A B I L I T Y F O R I N T E L L E C T U A L P R O P E RT Y
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this
document has been verified according to the general principles of electrical and mechanical engineering.
Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered
trademarks of Zilog, Inc. All other product or service names are the property of their respective owners.
PS022517-0508
Z8 Encore! XP® F0822 Series
Product Specification
iii
Revision History
Each instance in Revision History reflects a change to this document from its previous
revision. For more details, refer to the corresponding pages and appropriate links in the
table below.
PS022517-0508
Date
Revision
Level
May 2008
17
Removed Flash Microcontrollers from the title
throughout the document.
February
2008
16
Updated the flag status for BCLR, BIT, and BSET in 219
Table 126.
December
2007
15
Updated Zilog logo, Zilog text, Disclaimer section,
and implemented style guide. Updated Z8 Encore!
8K Series to Z8 Encore! XP F0822 Series Flash
Microcontrollers throughout the document.
All
June 2007 13
and
and
August 2007 14
No Changes.
All
December
2006
Updated Ordering Information and minor edits done. All
12
Page
Number
Description
All
Revision History
Z8 Encore! XP® F0822 Series
Product Specification
iv
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .x
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .x
Manual Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .x
Safeguards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Abbreviations/Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
eZ8 CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Signal and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Information Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Control Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset and Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Brownout Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode Recovery Using WDT Time-Out . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode Recovery Using a GPIO Port Pin Transition . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Port Availability by Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–C Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–C Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–C Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–C Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Edge Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents
Z8 Encore! XP® F0822 Series
Product Specification
vi
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Timer Output Signal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Timer 0–1 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . 79
Timer 0–1 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . 79
Timer 0–3 Control 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Timer 0–1 Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Watchdog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Watchdog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Watchdog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 85
Watchdog Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Watchdog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Watchdog Timer Reload Upper, High and Low Byte Registers . . . . . . . . . . 87
Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . 89
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Transmitting Data using Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Transmitting Data Using Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . 92
Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Receiving Data Using Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . 94
Clear To Send Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Multiprocessor (9-bit) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
UART Control Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
UART Receive Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
UART Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
UART Status 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
UART Control 0 and Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 103
UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
UART Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . 106
Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Infrared Endec Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Clock Phase and Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Control Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . .
I2C Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDA and SCL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Control of I2C Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Write and Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Only Transaction with a 7-bit Address . . . . . . . . . . . . . . . . . . . . .
Write Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Only Transaction with a 10-bit Address . . . . . . . . . . . . . . . . . . . .
Write Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . .
I2C Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Z8 Encore! XP® F0822 Series
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I2C Diagnostic Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Shot Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Information Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Using the Flash Frequency Registers . . . . . . . . . . . . . . . . . . . . . .
Flash Read Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Write/Erase Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Controller Behavior in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . .
Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Option Bit Configuration By Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Operation with an External RC Network. . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Product Specification
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OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Auto-Baud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCDCNTR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . .
OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . . .
General Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . .
General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI MASTER Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI SLAVE Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ8 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . . . . .
Assembly Language Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ8 CPU Instruction Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Condition Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ8 CPU Instruction Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Opcode Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Part Number Suffix Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Z8 Encore! XP® F0822 Series
Product Specification
x
Introduction
This Product Specification provides detailed operating information for Z8 Encore! XP®
F0822 Series devices within the Z8 Encore! XP Microcontroller (MCU) family of products. Within this document, Z8 Encore! XP® F0822 Series is referred as Z8 Encore! XP or
the F0822 Series unless specifically stated otherwise.
About This Manual
Zilog recommends that you read and understand everything in this manual before setting
up and using the product. We have designed this Product Specification to be used either as
a how to procedural manual or a reference guide to important data.
Intended Audience
This document is written for Zilog customers who are experienced at working with microcontrollers, integrated circuits, or printed circuit assemblies.
Manual Conventions
The following assumptions and conventions are adopted to provide clarity and ease of use:
Courier Typeface
Commands, code lines and fragments, bits, equations, hexadecimal addresses, and various
executable items are distinguished from general text by the use of the Courier typeface.
Where the use of the font is not indicated, as in the Index, the name of the entity is presented in upper case.
•
Example: FLAGS[1] is smrf.
Hexadecimal Values
Hexadecimal values are designated by uppercase H suffix and appear in the Courier
typeface.
•
Example: R1 is set to F8H.
Brackets
The square brackets [ ], indicate a register or bus.
•
PS022517-0508
Example: For the register R1[7:0], R1 is an 8-bit register, R1[7] is the most
significant bit, and R1[0] is the least significant bit.
Introduction
Z8 Encore! XP® F0822 Series
Product Specification
xi
Braces
The curly braces { }, indicate a single register or bus created by concatenating some combination of smaller registers, buses, or individual bits.
•
Example: The 12-bit register address {0H, RP[7:4], R1[3:0]} is composed of a 4-bit
hexadecimal value (0H) and two 4-bit register values taken from the Register Pointer
(RP) and Working Register R1. 0H is the most significant nibble (4-bit value) of the
12-bit register, and R1[3:0] is the least significant nibble of the 12-bit register.
Parentheses
The parentheses ( ), indicate an indirect register address lookup.
•
Example: (R1) is the memory location referenced by the address contained in the
Working Register R1.
Parentheses/Bracket Combinations
The parentheses ( ), indicate an indirect register address lookup and the square brackets,
[ ], indicate a register or bus.
•
Example: Assume PC[15:0] contains the value 1234h. (PC [15:0]) then refers to the
contents of the memory location at address 1234h.
Use of the Words Set, Reset and Clear
The word set implies that a register bit or a condition contains a logical 1. The words reset
or clear imply that a register bit or a condition contains a logical 0. When either of these
terms is followed by a number, the word logical cannot be included; however, it is
implied.
Notation for Bits and Similar Registers
A field of bits within a register is designated as: Register[n:n].
•
Example: ADDR[15:0] refers to bits 15 through bit 0 of the Address.
Use of the Terms LSB, MSB, lsb, and msb
In this document, the terms LSB and MSB, when appearing in upper case, mean least
significant byte and most significant byte, respectively. The lowercase forms, lsb and msb,
mean least significant bit and most significant bit, respectively.
Use of Initial Uppercase Letters
Initial uppercase letters designate settings and conditions in general text.
•
•
PS022517-0508
Example 1: The receiver forces the SCL line to Low.
Example 2: The Master generates a STOP condition to abort the transfer.
Introduction
Z8 Encore! XP® F0822 Series
Product Specification
xii
Use of All Uppercase Letters
The use of all uppercase letters designates the names of states, modes, and commands.
•
•
Example 1: The bus is considered BUSY after the Start condition.
Example 2: A START command triggers the processing of the initialization
sequence.
•
Example 3: STOP mode.
Bit Numbering
Bits are numbered from 0 to n–1 where n indicates the total number of bits. For example,
the 8 bits of a register are numbered from 0 to 7.
Safeguards
It is important that you understand the following safety terms, which are defined here.
Caution: Indicates a procedure or file can become corrupted if you does not follow
directions.
Abbreviations/Acronyms
This document uses the following abbreviations or acronyms.
Abbreviations/
Acronyms
Expansion
ADC
Analog-to-Digital Converter
LPO
Low-Power Operational Amplifier
SPI
Serial Peripheral Interface
WDT
Watchdog Timer
GPIO
General-Purpose Input/Output
OCD
On-Chip Debugger
POR
Power-On Reset
LVD
Low-Voltage Detection
VBO
Voltage Brownout
ISR
Interrupt Service Routine
UART
Universal Asynchronous Receiver/Transmitter
IrDA
Infrared Data Association
2
I C
PS022517-0508
Inter-Integrated Circuit
Introduction
Z8 Encore! XP® F0822 Series
Product Specification
xiii
PS022517-0508
Abbreviations/
Acronyms
Expansion
PDIP
Plastic Dual Inline Package
SOIC
Small Outline Integrated Circuit
SSOP
Small Shrink Outline Package
PC
Program Counter
IRQ
Interrupt Request
Introduction
Z8 Encore! XP® F0822 Series
Product Specification
1
Introduction
Zilog’s Z8 Encore! XP® MCU product family is a line of Zilog microcontrollers based on
the 8-bit eZ8 CPU. Z8 Encore! XP® F0822 Series, hereafter referred as Z8 Encore! XP or
the 8K Series adds Flash memory to Zilog’s extensive line of 8-bit microcontrollers. The
Flash in-circuit programming allows faster development time and program changes in the
field. The new eZ8 CPU is upward-compatible with the existing Z8® instructions. The
rich peripheral set of Z8 Encore! XP makes it suitable for a variety of applications including motor control, security systems, home appliances, personal electronic devices, and
sensors.
Features
The features of Z8 Encore! XP MCU product family include:
PS022517-0508
•
•
•
•
•
20 MHz eZ8 CPU core
•
•
•
•
•
•
•
•
•
•
•
Inter-Integrated Circuit (I2C)
Up to 8 KB Flash with in-circuit programming capability
1 KB Register RAM
Optional 2- to 5-channel, 10-bit Analog-to-Digital Converter (ADC)
Full-duplex 9-bit Universal Asynchronous Receiver/Transmitter (UART) with bus
transceiver Driver Enable Control
Serial Peripheral Interface (SPI)
Infrared Data Association (IrDA)-compliant infrared encoder/decoders
Two 16-bit timers with Capture, Compare, and PWM capability
Watchdog Timer (WDT) with internal RC oscillator
11 to 19 Input/Output pins depending upon package
Up to 19 interrupts with configurable priority
On-Chip Debugger (OCD)
Voltage Brownout (VBO) protection
Power-On Reset (POR)
Crystal oscillator with three power settings and RC oscillator option
Introduction
Z8 Encore! XP® F0822 Series
Product Specification
2
•
•
•
2.7 V to 3.6 V operating voltage with 5 V-tolerant inputs
20-pin and 28-pin packages
0 °C to +70 °C standard temperature and -40 °C to +105 °C extended temperature
operating ranges
Part Selection Guide
Table 1 identifies the basic features and package styles available for each device within the
Z8 Encore! XP® F0822 Series product line.
Table 1. Z8 Encore! XP® F0822 Series Part Selection Guide
16-bit
Timers
ADC
UARTs
with PWM Inputs with IrDA I2C SPI
Part
Number
Flash
(KB)
RAM
(KB)
I/O
Z8F0822
8
1
19
2
5
1
1
Z8F0821
8
1
11
2
2
1
1
Z8F0812
8
1
19
2
0
1
1
Z8F0811
8
1
11
2
0
1
1
Z8F0422
4
1
19
2
5
1
1
Z8F0421
4
1
11
2
2
1
1
Z8F0412
4
1
19
2
0
1
1
Z8F0411
4
1
11
2
0
1
1
PS022517-0508
Package Pin
Counts
20
1
28
X
X
1
X
X
1
X
X
1
X
X
Introduction
Z8 Encore! XP® F0822 Series
Product Specification
3
Block Diagram
Figure 1 displays the block diagram of the architecture of Z8 Encore! XP® F0822 Series
devices.
Crystal
Oscillator
On-Chip
Debugger
eZ8
CPU
POR/VBO
& Reset
Controller
Interrupt
Controller
System
Clock
WDT with
RC Oscillator
Memory Buses
Register Bus
Timers
UART
I2C
IrDA
SPI
ADC
Flash
Controller
RAM
Controller
Flash
Memory
RAM
GPIO
Figure 1. Z8 Encore! XP® F0822 Series Block Diagram
CPU and Peripheral Overview
eZ8 CPU Features
Zilog’s latest eZ8 8-bit CPU, meets the continuing demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8® instruction
set.
PS022517-0508
Introduction
Z8 Encore! XP® F0822 Series
Product Specification
4
The eZ8 CPU features include:
•
Direct register-to-register architecture allows each register to function as an
accumulator, improving execution time and decreasing the required Program Memory.
•
Software stack allows much greater depth in subroutine calls and interrupts than
hardware stacks.
•
•
•
Compatible with existing Z8® code.
•
•
Pipelined instruction fetch and execution.
•
•
•
•
New instructions support 12-bit linear addressing of the Register File.
Expanded internal Register File allows access of up to 4 KB.
New instructions improve execution efficiency for code developed using higher-level
programming languages, including C.
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
LDCI, LEA, MULT, and SRL.
Up to 10 MIPS operation.
C-Compiler friendly.
2 to 9 clock cycles per instruction.
For more information regarding the eZ8 CPU, refer to eZ8 CPU Core User Manual
(UM0128) available for download at www.zilog.com.
General Purpose Input/Output
Z8 Encore! XP® F0822 Series features 11 to 19 port pins (Ports A–C) for General Purpose
Input/Output (GPIO). The number of GPIO pins available is a function of package. Each
pin is individually programmable. Ports A and C supports 5 V-tolerant inputs.
Flash Controller
The Flash Controller programs and erases the Flash memory.
10-Bit Analog-to-Digital Converter
The optional Analog-to-Digital Converter (ADC) converts an analog input signal to a
10-bit binary number. The ADC accepts inputs from 2 to 5 different analog input sources.
UART
The Universal Asynchronous Receiver/Transmitter (UART) is full-duplex and capable of
handling asynchronous data transfers. The UART supports 8-bit and 9-bit data modes and
selectable parity.
PS022517-0508
Introduction
Z8 Encore! XP® F0822 Series
Product Specification
5
I2C
The Inter-Integrated Circuit (I2C) controller makes the Z8 Encore! XP compatible with the
I2C protocol. The I2C Controller consists of two bidirectional bus lines, a serial data
(SDA) line, and a serial clock (SCL) line.
Serial Peripheral Interface
The Serial Peripheral Interface (SPI) allows the Z8 Encore! XP to exchange data between
other peripheral devices such as EEPROMs, A/D converters, and ISDN devices. The SPI
is a full-duplex, synchronous, and character-oriented channel that supports a four-wire
interface.
Timers
Two 16-bit reloadable timers are used for timing/counting events or for motor control
operations. These timers provide a 16-bit programmable reload counter and operate in
One-Shot, Continuous, Gated, Capture, Compare, Capture and Compare, and PWM
modes.
Interrupt Controller
Z8 Encore! XP® F0822 Series products support up to 18 interrupts. These interrupts consist of 7 internal peripheral interrupts and 11 GPIO pin interrupt sources. The interrupts
have 3 levels of programmable interrupt priority.
Reset Controller
Z8 Encore! XP F0822 Series products are reset using the RESET pin, POR, WDT, STOP
mode exit, or VBO warning signal.
On-Chip Debugger
Z8 Encore! XP F0822 Series products feature an integrated On-Chip Debugger (OCD).
The OCD provides a rich-set of debugging capabilities, such as, reading and writing registers, programming the Flash, setting breakpoints, and executing code. A single-pin interface provides communication to the OCD.
PS022517-0508
Introduction
Z8 Encore! XP® F0822 Series
Product Specification
6
PS022517-0508
Introduction
Z8 Encore! XP® F0822 Series
Product Specification
7
Signal and Pin Descriptions
Z8 Encore! XP® F0822 Series products are available in a variety of packages, styles, and
pin configurations. This chapter describes the signals and available pin configurations for
each of the package styles. For information regarding the physical package specifications,
see Packaging on page 233.
Available Packages
Table 2 identifies the package styles available for each device within Z8 Encore! XP
F0822 Series product line.
Table 2. Z8 Encore! XP F0822 Series Package Options
Part Number 10-Bit ADC 20-Pin SSOP and PDIP 28-Pin SOIC and PDIP
Z8F0822
Yes
Z8F0821
Yes
Z8F0812
No
Z8F0811
No
Z8F0422
Yes
Z8F0421
Yes
Z8F0412
No
Z8F0411
No
X
X
X
X
X
X
X
X
Pin Configurations
Figure 2 through Figure 5 display the pin configurations for all of the packages available
in Z8 Encore! XP F0822 Series. See Table 4 for a description of the signals.
Note: The analog input alternate functions (ANAx) are not available on Z8 Encore! XP® F0822
Series devices.
PS022517-0508
Signal and Pin Descriptions
Z8 Encore! XP® F0822 Series
Product Specification
8
PA6 / SCL
PA7 / SDA
RESET
VSS
XIN
XOUT
VDD
PA0 / T0IN
PA1 / T0OUT
PA2 / DE0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PC0 / T1IN
PB0 / ANA0
PB1 / ANA1
VREF
AVSS
AVDD
DBG
PA5 / TXD0
PA4 / RXD0
PA3 / CTS0
Figure 2. Z8F0821 and Z8F0421 in 20-Pin SSOP and PDIP Packages
PC0 / T1IN
PA6 / SCL
PA7 / SDA
RESET
VSS
XIN
XOUT
VDD
PC5 / MISO
PC4 / MOSI
PC3 / SCK
PC2 / SS
PA0 / T0IN
PA1 / T0OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PB0 / ANA0
PB1 / ANA1
PB2 / ANA2
PB3 / ANA3
PB4 / ANA4
VREF
AVSS
AVDD
DBG
PC1 / T1OUT
PA5 / TXD0
PA4 / RXD0
PA3 / CTS0
PA2 / DE0
Figure 3. Z8F0822 and Z8F0422 in 28-Pin SOIC and PDIP Packages
PA6 / SCL
PA7 / SDA
RESET
VSS
XIN
XOUT
VDD
PA0 / T0IN
PA1 / T0OUT
PA2 / DE0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PC0 / T1IN
PB0
PB1
No Connect
AVSS
AVDD
DBG
PA5 / TXD0
PA4 / RXD0
PA3 / CTS0
Figure 4. Z8F0811 and Z8F0411 in 20-Pin SSOP and PDIP Packages
PS022517-0508
Signal and Pin Descriptions
Z8 Encore! XP® F0822 Series
Product Specification
9
PC0 / T1IN
PA6 / SCL
PA7 / SDA
RESET
VSS
XIN
XOUT
VDD
PC5 / MISO
PC4 / MOSI
PC3 / SCK
PC2 / SS
PA0 / T0IN
PA1 / T0OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PB0
PB1
PB2
PB3
PB4
No Connect
AVSS
AVDD
DBG
PC1 / T1OUT
PA5 / TXD0
PA4 / RXD0
PA3 / CTS0
PA2 / DE0
Figure 5. Z8F0812 and Z8F0412 in 28-Pin SOIC and PDIP Packages
Signal Descriptions
Table 3 describes Z8 Encore! XP® F0822 Series signals. See Pin Configurations on page 7
to determine the signals available for the specific package styles
.
Table 3. Signal Descriptions
Signal
Mnemonic
I/O
Description
General-Purpose I/O Ports A-H
PA[7:0]
I/O
Port C—These pins are used for general-purpose I/O and
supports 5 V-tolerant inputs.
PB[4:0]
I/O
Port B—These pins are used for general-purpose I/O.
PC[5:0]
I/O
Port C—These pins are used for general-purpose I/O and
support 5 V-tolerant inputs.
SCL
I/O
Serial Clock—This open-drain pin clocks data transfers in accordance with the
I2C standard protocol. This pin is multiplexed with a GPIO pin. When the GPIO
pin is configured for alternate function to enable the SCL function, this pin is
open-drain.
SDA
I/O
Serial Data—This open-drain pin transfers data between the I2C and a slave.
This pin is multiplexed with a GPIO pin. When the GPIO pin is configured for
alternate function to enable the SDA function, this pin is
open-drain.
I2C Controller
PS022517-0508
Signal and Pin Descriptions
Z8 Encore! XP® F0822 Series
Product Specification
10
Table 3. Signal Descriptions (Continued)
Signal
Mnemonic
I/O
Description
SPI Controller
SS
I/O
Slave Select—This signal can be an output or an input. If the Z8 Encore! XP®
is the SPI Master, this pin can be configured as the Slave Select output. If the
Z8 Encore! XP is the SPI Slave, this pin is the input slave select. It is
multiplexed with a GPIO pin.
SCK
I/O
SPI Serial Clock—The SPI Master supplies this pin. If the Z8 Encore! XP is
the SPI Master, this pin is the output. If the Z8 Encore! XP is the SPI Slave,
this pin is the input. It is multiplexed with a GPIO pin.
MOSI
I/O
Master-Out/Slave-In—This signal is the data output from the SPI Master
device and the data input to the SPI Slave device. It is multiplexed with a GPIO
pin.
MISO
I/O
Master-In/Slave-Out—This pin is the data input to the SPI Master device and
the data output from the SPI Slave device. It is multiplexed with a GPIO pin.
UART Controllers
TXD0
O
Transmit Data—This signal is the transmit output from the UART and IrDA.
The TXD signals are multiplexed with GPIO pins.
RXD0
I
Receive Data—This signal is the receiver input for the UART and IrDA. The
RXD signals are multiplexed with GPIO pins.
CTS0
I
Clear To Send—This signal is control inputs for the UART. The CTS signals
are multiplexed with GPIO pins.
DE0
O
Driver Enable—This signal allows automatic control of external RS-485
drivers. This signal is approximately the inverse of the TXE (Transmit Empty)
bit in the UART Status 0 Register. The DE signal can be used to ensure the
external RS-485 driver is enabled when data is transmitted by the UART.
T0OUT /
T1OUT
O
Timer Output 0–1—These signals are output pins from the timers. The Timer
Output signals are multiplexed with GPIO pins.
T0IN / T1IN
I
Timer Input 0–1—These signals are used as the Capture, Gating and Counter
inputs. The Timer Input signals are multiplexed with GPIO pins.
ANA[4:0]
I
Analog Input—These signals are inputs to the Analog-to-Digital Converter
(ADC). The ADC analog inputs are multiplexed with GPIO pins.
VREF
I
Analog-to-Digital Converter reference voltage input—As an output, the
VREF signal is not recommended for use as a reference voltage for external
devices. If the ADC is configured to use the internal reference voltage
generator, this pin should be left unconnected or capacitively coupled to
analog ground (AVSS).
Timers
Analog
PS022517-0508
Signal and Pin Descriptions
Z8 Encore! XP® F0822 Series
Product Specification
11
Table 3. Signal Descriptions (Continued)
Signal
Mnemonic
I/O
Description
Oscillators
XIN
I
External Crystal Input—This is the input pin to the crystal oscillator. A crystal
is connected between the external crystal input and the XOUT pin to form the
oscillator. In addition, this pin is used with external RC networks or external
clock drivers to provide the system clock to the system.
XOUT
O
External Crystal Output—This pin is the output of the crystal oscillator. A
crystal is connected between external crystal output and the XIN pin to form
the oscillator. When the system clock is referred in this manual, it refers to the
frequency of the signal at this pin. This pin must be left unconnected when not
using a crystal.
On-Chip Debugger
DBG
I/O
Debug—This pin is the control and data input and output to and from the OCD.
This pin is open-drain.
Caution: For operation of the OCD, all power pins (VDD and AVDD) must be supplied
with power and all ground pins (VSS and AVSS) must be properly grounded.
The DBG pin is open-drain and must have an external pull-up resistor to ensure
proper operation.
Reset
RESET
I
RESET—Generates a Reset when asserted (driven Low).
Power Supply
VDD
I
Digital Power Supply.
AVDD
I
Analog Power Supply—Must be powered up and grounded to VDD, even if
not using analog features.
VSS
I
Digital Ground.
AVSS
I
Analog Ground—Must be grounded and connected to VSS, even if not using
analog features.
PS022517-0508
Signal and Pin Descriptions
Z8 Encore! XP® F0822 Series
Product Specification
12
Pin Characteristics
Table 4 provides detailed information on the characteristics for each pin available on
Z8 Encore! XP® F0822 Series products. Table 4 data is sorted alphabetically by the pin
symbol mnemonic.
Table 4. Pin Characteristics
Active Low
Internal
Symbol
Reset
or
Tri-State Pull-up or
Mnemonic Direction Direction Active High Output Pull-down
Schmitt-Trigger Open Drain
Input
Output
AVDD
N/A
N/A
N/A
N/A
No
No
N/A
AVSS
N/A
N/A
N/A
N/A
No
No
N/A
DBG
I/O
I
N/A
Yes
No
Yes
Yes
PA[7:0]
I/O
I
N/A
Yes
Programmable Yes
Pull-up
Yes,
Programmable
PB[4:0]
I/O
I
N/A
Yes
Programmable Yes
Pull-up
Yes,
Programmable
PC[5:0]
I/O
I
N/A
Yes
Programmable Yes
Pull-up
Yes,
Programmable
RESET
I
I
Low
N/A
Pull-up
Yes
N/A
VDD
N/A
N/A
N/A
N/A
No
No
N/A
VREF
Analog
N/A
N/A
N/A
No
No
N/A
VSS
N/A
N/A
N/A
N/A
No
No
N/A
XIN
I
I
N/A
N/A
No
No
N/A
XOUT
O
O
N/A
No
No
No
No
PS022517-0508
Signal and Pin Descriptions
Z8 Encore! XP® F0822 Series
Product Specification
13
Address Space
The eZ8 CPU accesses three distinct address spaces:
•
The Register File contains addresses for the general-purpose registers and
the eZ8 CPU, Peripheral, and GPIO Port Control Registers.
•
The Program Memory contains addresses for all memory locations having executable
code and/or data.
•
The Data Memory contains addresses for all memory locations that hold data only.
These three address spaces are covered briefly in the following sections. For more information on the eZ8 CPU and its address space, refer to eZ8 CPU Core User Manual
(UM0128) available for download at www.zilog.com.
Register File
The Register File address space in the Z8 Encore! XP® is 4 KB (4096 bytes). It is composed of two sections—Control Registers and General-Purpose Registers. When instructions are executed, registers are read from when defined as sources and written to when
defined as destinations. The architecture of the eZ8 CPU allows all general-purpose registers to function as accumulators, address pointers, index registers, stack areas, or scratch
pad memory.
The upper 256 bytes of the 1 KB Register File address space is reserved for control
of the eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at
addresses from F00H to FFFH. Some of the addresses within the 256-byte Control Register
section is reserved (unavailable). Reading from the reserved Register File addresses
returns an undefined value. Writing to reserved Register File addresses is not recommended and can produce unpredictable results.
The on-chip RAM always begins at address 000H in the Register File address space.
Z8 Encore! XP F0822 Series contains 1 KB of on-chip RAM. Reading from Register File
addresses outside the available RAM addresses (and not within the control register address
space) returns an undefined value. Writing to these Register File addresses produces no
effect.
Program Memory
The eZ8 CPU supports 64 KB of Program Memory address space. Z8 Encore! XP® F0822
Series contain 4 KB to 8 KB on-chip Flash in the Program Memory address space,
depending on the device. Reading from Program Memory addresses outside the available
Flash addresses returns FFH. Writing to unimplemented Program Memory addresses produces no effect. Table 5 describes the Program Memory Maps for Z8 Encore! XP F0822
Series devices.
PS022517-0508
Address Space
Z8 Encore! XP® F0822 Series
Product Specification
14
Table 5. Z8 Encore! XP® F0822 Series Program Memory Maps
Program Memory Address (Hex)
Function
Z8F082x and Z8F081x Products
0000-0001
Option Bits
0002-0003
Reset Vector
0004-0005
WDT Interrupt Vector
0006-0007
Illegal Instruction Trap
0008-0037
Interrupt Vectors*
0038-1FFF
Program Memory
Z8F042x and Z8F041x Products
0000-0001
Option Bits
0002-0003
Reset Vector
0004-0005
WDT Interrupt Vector
0006-0007
Illegal Instruction Trap
0008-0037
Interrupt Vectors*
0038-0FFF
Program Memory
Note: *See Table 24 on page 57 for a list of the interrupt vectors.
Data Memory
Z8 Encore! XP® F0822 Series does not use the eZ8 CPU’s 64 KB Data Memory address
space.
Information Area
Table 6 describes the Z8 Encore! XP F0822 Series Information Area. This 512 byte Information Area is accessed by setting bit 7 of the Page Select Register to 1. When access is
enabled, the Information Area is mapped into the Program Memory and overlays the 512
bytes at addresses FE00H to FFFFH. When the Information Area access is enabled, all
reads from these Program Memory addresses return the Information Area data rather than
the Program Memory data. Access to the Information Area is read-only.
Table 6. Information Area Map
Program Memory Address (Hex) Function
PS022517-0508
FE00H-FE3FH
Reserved
FE40H-FE53H
Part Number
20-character ASCII alphanumeric code
Left justified and filled with zeros
FE54H-FFFFH
Reserved
Address Space
Z8 Encore! XP® F0822 Series
Product Specification
15
Register File Address Map
Table 7 provides the address map for the Register File of the Z8 Encore! XP® F0822
Series products. Not all devices and package styles in the F0822 Series support the ADC,
the SPI, or all of the GPIO Ports. Consider registers for unimplemented peripherals as
Reserved.
Table 7. Register File Address Map
Address
(Hex)
Register Description
General Purpose RAM
Mnemonic
Reset (Hex) Page No
000-3FF
400-EFF
General-Purpose Register File RAM
Reserved
—
—
XX
XX
Timer 0 High Byte
Timer 0 Low Byte
Timer 0 Reload High Byte
Timer 0 Reload Low Byte
Timer 0 PWM High Byte
Timer 0 PWM Low Byte
Timer 0 Control 0
Timer 0 Control 1
T0H
T0L
T0RH
T0RL
T0PWMH
T0PWML
T0CTL0
T0CTL1
00
01
FF
FF
00
00
00
00
78
78
79
79
79
79
81
81
Timer 1 High Byte
Timer 1 Low Byte
Timer 1 Reload High Byte
Timer 1 Reload Low Byte
Timer 1 PWM High Byte
Timer 1 PWM Low Byte
Timer 1 Control 0
Timer 1 Control 1
Reserved
T1H
T1L
T1RH
T1RL
T1PWMH
T1PWML
T1CTL0
T1CTL1
—
00
01
FF
FF
00
00
00
00
XX
78
78
79
79
79
79
81
81
UART0 Transmit Data
UART0 Receive Data
UART0 Status 0
UART0 Control 0
UART0 Control 1
UART0 Status 1
UART0 Address Compare Register
UART0 Baud Rate High Byte
U0TXD
U0RXD
U0STAT0
U0CTL0
U0CTL1
U0STAT1
U0ADDR
U0BRH
XX
XX
0000011Xb
00
00
00
00
FF
100
101
101
103
103
101
105
106
Timer 0
F00
F01
F02
F03
F04
F05
F06
F07
Timer 1
F08
F09
F0A
F0B
F0C
F0D
F0E
F0F
F10-F3F
UART 0
F40
F41
F42
F43
F44
F45
F46
XX=Undefined
PS022517-0508
Register File Address Map
Z8 Encore! XP® F0822 Series
Product Specification
16
Table 7. Register File Address Map (Continued)
Address
(Hex)
Register Description
Mnemonic
Reset (Hex) Page No
F47
F48-F4F
UART0 Baud Rate Low Byte
Reserved
U0BRL
—
FF
XX
106
I2C Data
I2C Status
I2C Control
I2C Baud Rate High Byte
I2C Baud Rate Low Byte
I2C Diagnostic State
I2C Diagnostic Control
Reserved
I2CDATA
I2CSTAT
I2CCTL
I2CBRH
I2CBRL
I2CDST
I2CDIAG
—
00
80
00
FF
FF
XX000000b
00
XX
139
140
141
143
143
143
145
I 2C
F50
F51
F52
F53
F54
F55
F56
F57-F5F
Serial Peripheral Interface (SPI) Unavailable in 20-Pin Package Devices
F60
F61
F62
F63
F64
F65
F66
F67
F68-F6F
SPI Data
SPI Control
SPI Status
SPI Mode
SPI Diagnostic State
Reserved
SPI Baud Rate High Byte
SPI Baud Rate Low Byte
Reserved
SPIDATA
SPICTL
SPISTAT
SPIMODE
SPIDST
—
SPIBRH
SPIBRL
—
01
00
00
00
00
XX
FF
FF
XX
121
122
123
124
125
ADCCTL
—
ADCD_H
ADCD_L
—
20
XX
XX
XX
XX
150
IRQ0
IRQ0ENH
IRQ0ENL
IRQ1
IRQ1ENH
IRQ1ENL
IRQ2
IRQ2ENH
IRQ2ENL
—
IRQES
00
00
00
00
00
00
00
00
00
XX
00
61
63
63
62
64
64
63
65
65
125
125
Analog-to-Digital Converter (ADC)
F70
F71
F72
F73
F74-FBF
ADC Control
Reserved
ADC Data High Byte
ADC Data Low Bits
Reserved
151
151
Interrupt Controller
FC0
FC1
FC2
FC3
FC4
FC5
FC6
FC7
FC8
FC9-FCC
FCD
XX=Undefined
PS022517-0508
Interrupt Request 0
IRQ0 Enable High Bit
IRQ0 Enable Low Bit
Interrupt Request 1
IRQ1 Enable High Bit
IRQ1 Enable Low Bit
Interrupt Request 2
IRQ2 Enable High Bit
IRQ2 Enable Low Bit
Reserved
Interrupt Edge Select
67
Register File Address Map
Z8 Encore! XP® F0822 Series
Product Specification
17
Table 7. Register File Address Map (Continued)
Address
(Hex)
Register Description
Mnemonic
Reset (Hex) Page No
FCE
FCF
Reserved
Interrupt Control
—
IRQCTL
00
00
67
Port A Address
Port A Control
Port A Input Data
Port A Output Data
PAADDR
PACTL
PAIN
PAOUT
00
00
XX
00
50
51
54
55
Port B Address
Port B Control
Port B Input Data
Port B Output Data
PBADDR
PBCTL
PBIN
PBOUT
00
00
XX
00
50
51
54
55
Port C Address
Port C Control
Port C Input Data
Port C Output Data
Reserved
PCADDR
PCCTL
PCIN
PCOUT
—
00
00
XX
00
XX
50
51
54
55
WDTCTL
WDTU
WDTH
WDTL
—
XXX00000b
FF
FF
FF
XX
86
87
87
87
FCTL
FSTAT
FPS
FPROT
FFREQH
FFREQL
00
00
00
00
00
00
159
160
160
161
161
161
—
RPS
—
XX
00
XX
160
GPIO Port A
FD0
FD1
FD2
FD3
GPIO Port B
FD4
FD5
FD6
FD7
GPIO Port C
FD8
FD9
FDA
FDB
FDC-FEF
Watchdog Timer (WDT)
FF0
FF1
FF2
FF3
FF4-FF7
Watchdog Timer Control
Watchdog Timer Reload Upper Byte
Watchdog Timer Reload High Byte
Watchdog Timer Reload Low Byte
Reserved
Flash Memory Controller
FF8
FF8
FF9
FF9 (if enabled)
FFA
FFB
Flash Control
Flash Status
Page Select
Flash Sector Protect
Flash Programming Frequency High Byte
Flash Programming Frequency Low Byte
Read-Only Memory
FF8
FF9
FFA-FFB
Reserved
Page Select
Reserved
eZ8 CPU
XX=Undefined
PS022517-0508
Register File Address Map
Z8 Encore! XP® F0822 Series
Product Specification
18
Table 7. Register File Address Map (Continued)
Address
(Hex)
FFC
FFD
FFE
FFF
XX=Undefined
PS022517-0508
Register Description
Mnemonic
Reset (Hex) Page No
Flags
Register Pointer
Stack Pointer High Byte
Stack Pointer Low Byte
—
RP
SPH
SPL
XX
XX
XX
XX
Refer to eZ8
CPU User
Manual
Register File Address Map
Z8 Encore! XP® F0822 Series
Product Specification
19
Control Register Summary
Timer 0 Control 1
T0CTL1 (F07H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer Mode
000 = One-Shot mode
001 = Continuous mode
010 = Counter mode
011 = PWM mode
100 = Capture mode
101 = Compare mode
110 = Gated mode
111 = Capture/Compare
mode
Timer 0 High Byte
T0H (F00H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 current count value
Timer 0 Low Byte
T0L (F01H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 current count value
Prescale Value
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
Timer 0 Reload High Byte
T0RH (F02H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 reload value [15:8]
Timer Input/Output Polarity
Operation of this bit is a
function of
the current operating mode
of the timer
Timer 0 Reload Low Byte
T0RL (F03H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 reload value [7:0]
Timer Enable
0 = Timer is disabled
1 = Timer is enabled
Timer 0 PWM High Byte
T0PWMH (F04H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 PWM value [15:8]
Timer 1 High Byte
T1H (F08H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 Control 0
T0CTL0 (F06H - Read/Write)
Timer 1 current count value
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Cascade Timer
0 = Timer 0 Input signal is
GPIO pin
1 = Timer 0 Input signal is
Timer 1 out
Reserved
Timer 1 Low Byte
T1L (F09H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 current count value
Timer 1 Reload High Byte
T1RH (F0AH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 reload value [15:8]
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
20
Timer 1 Reload Low Byte
T1RL (F0BH - Read/Write)
Timer 1 Control 1
T1CTL1 (F0FH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 reload value [7:0]
Timer Mode
000 = One-Shot mode
001 = Continuous mode
010 = Counter mode
011 = PWM mode
100 = Capture mode
101 = Compare mode
110 = Gated mode
111 = Capture/Compare
mode
Timer 1 PWM High Byte
T1PWMH (F0CH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 PWM value [15:8]
Prescale Value
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
Timer 1 PWM Low Byte
T1PWML (F0DH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 PWM value [7:0]
Timer 1 Control 0
T1CTL0 (F0EH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer Input/Output Polarity
Operation of this bit is a
function of
the current operating mode
of the timer
Reserved
Cascade Timer
0 = Timer 1 Input signal is
GPIO pin
1 = Timer 1 Input signal is
Timer 0 out
Reserved
Timer Enable
0 = Timer is disabled
1 = Timer is enabled
UART0 Transmit Data
U0TXD (F40H - Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 transmitter data byte
UART0 Receive Data
U0RXD (F40H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 receiver data byte
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
21
UART0 Status 0
U0STAT0 (F41H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
CTS signal
Returns the level of the CTS
signal
Transmitter Empty
0 = Data is currently
transmitting
1 = Transmission is
complete
Transmitter Data Register
0 = Transmit Data Register is
full
1 = Transmit Data register is
empty
Break Detect
0 = No break occurred
1 = A break occurred
Framing Error
0 = No framing error
occurred
1 = A framing occurred
Overrun Error
0 = No overrrun error
occurred
1 = An overrun error
occurred
Parity Error
0 = No parity error occurred
1 = A parity error occurred
Receive Data Available
0 = Receive Data Register is
empty
1 = A byte is available in the
Receive
Data Register
PS022517-0508
UART0 Control 0
U0CTL0 (F42H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Loop Back Enable
0 = Normal operation
1 = Transmit data is looped
back to
the receiver
STOP Bit Select
0 = Transmitter sends 1
STOP bit
1 = Transmitter sends 2
STOP bits
Send Break
0 = No break is sent
1 = Output of the transmitter
is zero
Parity Select
0 = Even parity
1 = Odd parity
Parity Enable
0 = Parity is disabled
1 = Parity is enabled
CTS Enable
0 = CTS signal has no effect
on the
transmitter
1 = UART recognizes CTS
signal as a
transmit enable control
signal
Receive Enable
0 = Receiver disabled
1 = Receiver enabled
Transmit Enable
0 = Transmitter disabled
1 = Transmitter enabled
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
22
UART0 Control 1
U0CTL1 (F43H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Infrared Encoder/Decoder
0 = Infrared endec is
disabled
1 = Infrared endec is
enabled
Received Data Interrupt
0 = Received data and errors
generate
interrupt requests
1 = Only errors generate
interrupt
requests. Received data
does not.
Baud Rate Registers Control
See UART chapter for
operation
Driver Enable Polarity
0 = DE signal is active High
1 = DE signal is active Low
Multiprocessor Bit Transmit
0 = Send a 0 as the
multiprocessor bit
1 = Send a 1 as the
multiprocessor bit
Multiprocessor Mode [0]
See Multiprocessor Mode [1]
below
Multiprocessor (9-bit) Enable
0 = Multiprocessor mode is
disabled
1 = Multiprocessor mode is
enabled
Multiprocessor Mode [1]
with Multiprocess Mode bit 0:
00 = Interrupt on all received
bytes
01 = Interrupt only on
address bytes
10 = Interrupt on address
match and
following data
11 = Interrupt on data
following an
address match
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
23
UART0 Status 1
U0STAT1 (F44H- Read Only)
I2C Status
I2CSTAT (F51H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Mulitprocessor Receive
Returns value of last
multiprocessor bit
New Frame
0 = Current byte is not start
of frame
1 = Current byte is start of
new frame
NACK Interrupt
0 = No action required to
service NAK
1 = START/STOP not set
after NAK
Data Shift State
0 = Data is not being
transferred
1 = Data is being transferred
Reserved
UART0 Address Compare
U0ADDR (F45H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 Address Compare
UART0 Baud Rate Generator High Byte
U0BRH (F46H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 Baud Rate divisor
UART0 Baud Rate Generator Low Byte
U0BRL (F47H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 Baud Rate divisor
I2C Data
I2CDATA (F50H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Transmit Address State
0 = Address is not being
transferred
1 = Address is being
transferred
Read
0 = Write operation
1 = Read operation
10-Bit Address
0 = 7-bit address being
transmitted
1 = 10-bit address being
transmitted
Acknowledge
0 = Acknowledge not
transmitted/received
1 = For last byte,
Acknowledge was
transmitted/received
Receive Data Register Full
0 = I2C has not received
data
1 = Data register contains
received data
I2C data [7:0]
Transmit Data Register Empty
0 = Data register is full
1 = Data register is empty
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
24
I2C Control
I2CCTL (F52H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
I2C Signal Filter Enable
0 = Digital filtering disabled
1 = Low-pass digital filters
enabled
on SDA and SCL input
signals
Flush Data
0 = No effect
1 = Clears I2C Data register
Send NAK
0 = Do not send NAK
1 = Send NAK after next byte
received
from slave
Enable TDRE Interrupts
0 = Do not generate an
interrupt when
the I2C Data register is
empty
1 = Generate an interrupt
when the I2C
Transmit Data register is
empty
Baud Rate Generator
0 = Interrupts behave as set
by I2C
control
1 = BRG generates an
interrupt when
it counts down to zero
Send STOP Condition
0 = Do not issue STOP
condition after
data transmission is
complete
1 = Issue STOP condition
after data
transmission is complete
Send Start Condition
0 = Do not send Start
Condition
1 = Send Start Condition
I2C Enable
0 = I2C is disabled
1 = I2C is enabled
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
25
I2C Baud Rate Generator High Byte
I2CBRH (F53H - Read/Write)
SPI Control
SPICTL (F61H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
I2C Baud Rate divisor [15:8]
I2C Baud Rate Generator Low Byte
I2CBRL (F54H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
I2C Baud Rate divisor [7:0]
SPI Data
SPIDATA (F60H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
SPI Data [7:0]
SPI Enable
0 = SPI disabled
1 = SPI enabled
Master Mode Enabled
0 = SPI configured in Slave
mode
1 = SPI configured in Master
mode
Wire-OR (open-drain) Mode
0 = SPI signals not
configured for
open-drain
1 = SPI signals (SCK, SS,
MISO, and
MOSI) configured for
open-drain
Clock Polarity
0 = SCK idles Low
1 = SPI idles High
Phase Select
Sets the phase relationship
of the data
to the clock.
BRG Timer Interrupt Request
0 = BRG timer function is
disabled
1 = BRG time-out interrupt is
enabled
Start an SPI Interrupt Request
0 = No effect
1 = Generate an SPI
interrupt request
Interrupt Request Enable
0 = SPI interrupt requests
are disabled
1 = SPI interrupt requests
are enabled
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
26
SPI Status
SPISTAT (F62H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Slave Select
0 = If Slave, SS pin is
asserted
1 = If Slave, SS pin is not
asserted
Transmit Status
0 = No data transmission in
progress
1 = Data transmission now in
progress
Reserved
Slave Mode Transaction
0 = No slave mode
transaction abort
detected
1 = Slave mode transaction
abort was
detected
Collision
0 = No multi-master collision
detected
1 = Multi-master collision
was detected
Overrun
0 = No overrun error
detected
1 = Overrun error was
detected
SPI Mode
SPIMODE (F63H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Slave Select Value
If Master and SPIMODE[1] =
1:
0 = SS pin driven Low
1 = SS pin driven High
Slave Select I/O
0 = SS pin configured as an
input
1 = SS pin configured as an
output
(Master mode only)
Number of Data Bits Per
000 = 8 bits
001 = 1 bit
010 = 2 bits
011 = 3 bits
100 = 4 bits
101 = 5 bit
110 = 6 bits
111 = 7 bits
Diagnostic Mode Control
0 = Reading from SPIBRH,
SPIBRL
returns reload values
1 = Reading from SPIBRH,
SPIBRL
returns current BRG
count value
Reserved
Interrupt Request
0 = No SPI interrupt request
pending
1 = SPI interrupt request is
pending
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
27
SPI Diagnostic State
SPIDST (F64H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
SPI State
Transmit Clock Enable
0 = Internal transmit clock
enable
signal is deasserted
1 = Internal transmit clock
enable
signal is asserted
Shift Clock Enable
0 = Internal shift clock enable
signal
is deasserted
1 = Internal shift clock enable
signal
is asserted
SPI Baud Rate Generator High Byte
SPIBRH (F66H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
SPI Baud Rate divisor [15:8]
SPI Baud Rate Generator Low Byte
SPIBRL (F67H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
SPI Baud Rate divisor [7:0]
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
28
ADC Control
ADCCTL (F70H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Analog Input Select
0000 = ANA0
0001 =
ANA1
0010 = ANA2
0011 =
ANA3
0100 = ANA4
0101 through 21111 =
Reserved
Continuous Mode Select
0 = Single-shot conversion
1 = Continuous conversion
External VREF select
0 = Internal voltage
reference selected
1 = External voltage
reference selected
Reserved
Conversion Enable
0 = Conversion is complete
1 = Begin conversion
ADC Data High Byte
ADCD_H (F72H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
ADC Data [9:2]
ADC Data Low Bits
ADCD_L (F73H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
ADC Data [1:0]
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
29
Interrupt Request 0
IRQ0 (FC0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
ADC Interrupt Request
SPI Interrupt Request
I2C Interrupt Request
UART 0 Transmitter Interrupt
UART 0 Receiver Interrupt
Timer 0 Interrupt Request
Timer 1 Interrupt Request
Reserved
For all of the above
peripherals:
0 = Peripheral IRQ is not
pending
1 = Peripheral IRQ is
awaiting service
IRQ0 Enable High Bit
IRQ0ENH (FC1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
ADC IRQ Enable Hit Bit
SPI IRQ Enable High Bit
I2C IRQ Enable High Bit
UART 0 Transmitter IRQ
UART 0 Receiver IRQ Enable
Timer 0 IRQ Enable High Bit
Timer 1 IRQ Enable High Bit
Reserved
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
30
IRQ0 Enable Low Bit
IRQ0ENL (FC2H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
ADC IRQ Enable Hit Bit
SPI IRQ Enable Low Bit
I2C IRQ Enable Low Bit
UART 0 Transmitter IRQ
UART 0 Receiver IRQ Enable
Timer 0 IRQ Enable Low Bit
Timer 1 IRQ Enable Low Bit
Reserved
Interrupt Request 1
IRQ1 (FC3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Pin Interrupt Request
0 = IRQ from corresponding
pin [7:0]
is not pending
1 = IRQ from corresponding
pin [7:0]
is awaiting service
IRQ1 Enable High Bit
IRQ1ENH (FC4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Pin IRQ Enable High
IRQ1 Enable Low Bit
IRQ1ENL (FC5H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Pin IRQ Enable Low
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
31
Interrupt Request 2
IRQ2 (FC6H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Pin Interrupt Request
0 = IRQ from corresponding
pin [3:0]
is not pending
1 = IRQ from corresponding
pin [3:0]
is awaiting service
Reserved
IRQ2 Enable High Bit
IRQ2ENH (FC7H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Pin IRQ Enable High
Reserved
IRQ2 Enable Low Bit
IRQ2ENL (FC8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Pin IRQ Enable Low
Reserved
Interrupt Control
IRQCTL (FCFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Interrupt Request Enable
0 = Interrupts are disabled
1 = Interrupts are enabled
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
32
Port A Address
PAADDR (FD0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (opendrain)
04H = High drive enable
05H = STOP mode recovery
enable
06H = Pull-up enable
07H-FFH = No function
Port A Control
PACTL (FD1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Control[7:0]
Provides Access to Port
Sub-Registers
Port A Input Data
PAIN (FD2H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Input Data [7:0]
Port A Output Data
PAOUT (FD3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Output Data [7:0]
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
33
Port B Address
PBADDR (FD4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port B Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (opendrain)
04H = High drive enable
05H = STOP mode recovery
enable
06H = Pull-up enable
07H-FFH = No function
Port B Control
PBCTL (FD5H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port B Control [4:0]
Provides Access to Port
Sub-Registers
Reserved
Port B Input Data
PBIN (FD6H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port B Input Data [4:0]
Reserved
Port B Output Data
PBOUT (FD7H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port B Output Data [4:0]
Reserved
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
34
Port C Address
PCADDR (FD8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (opendrain)
04H = High drive enable
05H = STOP mode recovery
enable
06H = Pull-up enable
07H-FFH = No function
Port C Control
PCCTL (FD9H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Control [5:0]
Provides Access to Port
Sub-Registers
Reserved
Port C Input Data
PCIN (FDAH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Input Data [5:0]
Reserved
Port C Output Data
PCOUT (FDBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Output Data [5:0]
Reserved
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
35
Watchdog Timer Control
WDTCTL (FF0H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
SM configuration indicator
Reserved
EXT
0 = Reset not generated by
RESET pin
1 = Reset generated by
RESET pin
WDT
0 = WDT timeout has not
occurred
1 = WDT timeout occurred
STOP
0 = SMR has not occurred
1 = SMR has occurred
POR
0 = POR has not occurred
1 = POR has occurred
Watchdog Timer Reload Upper Byte
WDTU (FF1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
WDT reload value [23:16]
Watchdog Timer Reload Middle Byte
WDTH (FF2H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
WDT reload value [15:8]
Watchdog Timer Reload Low Byte
WDTL (FF3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
WDT reload value [7:0]
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
36
Flash Control
FCTL (FF8H - Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Command
73H = First unlock command
8CH = Second unlock
command
95H = Page erase command
63H = Mass erase command
5EH = Flash Sector Protect
reg select
Flash Status
FSTAT (FF8H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Controller Status
00_0000 = Flash controller
locked
00_0001 = First unlock
received
00_0010 = Second unlock
received
00_0011 = Flash controller
unlocked
00_0100 = Flash Sector
Protect register
selected
00_1xxx = Programming in
progress
01_0xxx = Page erase in
progress
10_0xxx = Mass erase in
progress
Reserved
Page Select
FPS (FF9H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Page Select [6:0]
Identifies the Flash memory
page for
Page Erase operation.
Information Area Enable
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
37
Flash Sector Protect
FPROT (FF9H - Read/Write to 1’s)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Sector Protect [7:0]
0 = Sector can be
programmed or
erased from user code
1 = Sector is protected and
cannot be
programmed or erased
from user
code
Flash Frequency High Byte
FFREQH (FFAH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Frequency value [15:8]
Flash Frequency Low Byte
FFREQL (FFBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Frequency value [7:0]
Flags
FLAGS (FFCH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
F1 - User Flag 1
F2 - User Flag 2
H - Half Carry
D - Decimal Adjust
V - Overflow Flag
S - Sign Flag
Z - Zero Flag
C - Carry Flag
Register Pointer
RP (FFDH- Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Working Register Page
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
38
Register Pointer
RP (FFDH- Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Working Register Group
Stack Pointer High Byte
SPH (FFEH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer [15:8]
Stack Pointer Low Byte
SPL (FFFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer [7:0]
PS022517-0508
Control Register Summary
Z8 Encore! XP® F0822 Series
Product Specification
39
Reset and Stop Mode Recovery
The Reset Controller within the Z8 Encore! XP® F0822 Series controls Reset and Stop
Mode Recovery operation. In typical operation, the following events cause a Reset to
occur:
•
•
•
Power-On Reset (POR)
•
•
External RESET pin assertion
Voltage Brownout
WDT time-out (when configured through the WDT_RES Option Bit to initiate a
Reset)
On-Chip Debugger initiated Reset (OCDCTL[0] set to 1)
When the Z8 Encore! XP F0822 Series device is in STOP mode, a Stop Mode Recovery is
initiated by any of the following events:
•
•
•
WDT time-out
GPIO Port input pin transition on an enabled Stop Mode Recovery source
DBG pin driven Low
Reset Types
Z8 Encore! XP F0822 Series provides two types of reset operation (System Reset and Stop
Mode Recovery). The type of reset is a function of both the current operating mode of the
Z8 Encore! XP F0822 Series device and the source of the Reset. Table 8 lists the types of
Resets and their operating characteristics.
Table 8. Reset and Stop Mode Recovery Characteristics and Latency
Reset Characteristics and Latency
Reset Type
eZ8
Control Registers CPU
Reset Latency (Delay)
System Reset Reset (as applicable) Reset
66 WDT Oscillator cycles + 16 System Clock cycles
Stop Mode
Recovery
66 WDT Oscillator cycles + 16 System Clock cycles
PS022517-0508
Unaffected, except
WDT_CTL register
Reset
Reset and Stop Mode Recovery
Z8 Encore! XP® F0822 Series
Product Specification
40
System Reset
During a System Reset, a Z8 Encore! XP® F0822 Series device is held in Reset for 66
cycles of the WDT oscillator followed by 16 cycles of the system clock. At the beginning
of Reset, all GPIO pins are configured as inputs. All GPIO programmable pull-ups are disabled.
During Reset, the eZ8 CPU and the on-chip peripherals are idle; however, the on-chip
crystal oscillator and WDT oscillator continue to run. The system clock begins operating
following the WDT oscillator cycle count. The eZ8 CPU and on-chip peripherals remain
idle through all the 16 cycles of the system clock.
Upon Reset, control registers within the Register File which have a defined Reset value
are loaded with their reset values. Other control registers (including the Stack Pointer,
Register Pointer, and Flags) and general-purpose RAM are undefined following the Reset.
The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H
and loads that value into the Program Counter. Program execution begins at the Reset vector address.
Reset Sources
Table 9 lists the reset sources as a function of the operating mode. The text following
provides more detailed information on the individual reset sources.
Note: A POR/VBO event always has priority over all other possible reset sources to insure a full
system reset occurs.
Table 9. Reset Sources and Resulting Reset Type
Operating Mode
Reset Source
Reset Type
NORMAL or HALT
modes
POR/VBO
System Reset
WDT time-out
when configured for Reset
System Reset
RESET pin assertion
System Reset
OCD initiated Reset
(OCDCTL[0] set to 1)
System Reset except the OCD is unaffected by the
reset
POR/ VBO
System Reset
RESET pin assertion
System Reset
DBG pin driven Low
System Reset
STOP mode
PS022517-0508
Reset and Stop Mode Recovery
Z8 Encore! XP® F0822 Series
Product Specification
41
Power-On Reset
Each device in the Z8 Encore! XP® F0822 Series contains an internal POR circuit. The
POR circuit monitors the supply voltage and holds the device in the Reset state until the
supply voltage reaches a safe operating level. After the supply voltage exceeds the POR
voltage threshold (VPOR), the POR Counter is enabled and counts 66 cycles of the WDT
oscillator. After the POR counter times out, the XTAL Counter is enabled to count a total
of 16 system clock pulses. The device is held in the Reset state until both the POR Counter
and XTAL counter have timed out. After the Z8 Encore! XP F0822 Series device exits the
POR state, the eZ8 CPU fetches the Reset vector. Following POR, the POR status bit in the
Watchdog Timer Control Register (WDTCTL) is set to 1.
Figure 6 displays POR operation. See Electrical Characteristics for POR threshold voltage
(VPOR).
VCC = 3.3 V
VPOR
VVBO
Program
Execution
VCC = 0.0 V
WDT Clock
Primary
Oscillator
Internal RESET
signal
Oscillator
Start-up
POR
Counter Delay
Not to Scale
XTAL
Counter Delay
Figure 6. Power-On Reset Operation
Voltage Brownout Reset
The devices in Z8 Encore! XP F0822 Series provide low Voltage Brownout protection.
The VBO circuit senses when the supply voltage drops to an unsafe level (below the VBO
threshold voltage) and forces the device into the Reset state. While the supply voltage
PS022517-0508
Reset and Stop Mode Recovery
Z8 Encore! XP® F0822 Series
Product Specification
42
remains below the POR voltage threshold (VPOR), the VBO block holds the device in the
Reset state.
After the supply voltage again exceeds the POR voltage threshold, the device progresses
through a full System Reset sequence as described in the POR section. Following POR,
the POR status bit in the Watchdog Timer Control Register (WDTCTL) is set to 1.
Figure 7 displays the VBO operation. See Electrical Characteristics on page 185 for the
VBO and POR threshold voltages (VVBO and VPOR).
The VBO circuit can be either enabled or disabled during STOP mode. Operation during
STOP mode is set by the VBO_AO Option Bit. For information on configuring VBO_AO,
see Option Bits on page 163.
VCC = 3.3 V
VCC = 3.3 V
VPOR
VVBO
Program
Execution
Voltage
Brownout
Program
Execution
WDT Clock
Primary
Oscillator
Internal RESET
signal
POR
Counter Delay
XTAL
Counter Delay
Figure 7. Voltage Brownout Reset Operation
Watchdog Timer Reset
If the device is in NORMAL or HALT mode, WDT initiates a System Reset at time-out, if
the WDT_RES Option Bit is set to 1. This is the default (unprogrammed) setting of the
WDT_RES Option Bit. The WDT status bit in the WDT Control Register is set to signify
that the reset was initiated by the WDT.
PS022517-0508
Reset and Stop Mode Recovery
Z8 Encore! XP® F0822 Series
Product Specification
43
External Pin Reset
The RESET pin contains a Schmitt-triggered input, an internal pull-up, an analog filter,
and a digital filter to reject noise. After the RESET pin is asserted for at least 4 system
clock cycles, the device progresses through the System Reset sequence. While the RESET
input pin is asserted Low, Z8 Encore! XP F0822 Series device continues to be held in the
Reset state. If the RESET pin is held Low beyond the System Reset time-out, the device
exits the Reset state immediately following RESET pin deassertion. Following a System
Reset initiated by the external RESET pin, the EXT status bit in the Watchdog Timer Control Register (WDTCTL) is set to 1.
On-Chip Debugger Initiated Reset
A POR is initiated using the OCD by setting the RST bit in the OCD Control Register. The
OCD block is not reset but the rest of the chip goes through a normal system reset. The
RST bit automatically clears during the system reset. Following the system reset, the POR
bit in the WDT Control Register is set.
Stop Mode Recovery
STOP mode is entered by execution of a STOP instruction by the eZ8 CPU. For detailed
information on STOP mode, see Low-Power Modes on page 45. During Stop Mode
Recovery, the device is held in reset for 66 cycles of the WDT oscillator followed by 16
cycles of the system clock. Stop Mode Recovery only affects the contents of the WDT
Control Register and does not affect any other values in the Register File,
including the Stack Pointer, Register Pointer, Flags, Peripheral Control Registers, and
General-Purpose RAM.
The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H
and loads that value into the Program Counter. Program execution begins at the Reset
vector address. Following Stop Mode Recovery, the STOP bit in the WDT Control
Register is set to 1. Table 10 lists the Stop Mode Recovery sources and resulting actions.
The text following provides more detailed information on each of the Stop Mode Recovery sources.
Table 10. Stop Mode Recovery Sources and Resulting Action
Operating Mode Stop Mode Recovery Source
STOP mode
Action
WDT time-out when configured for Reset Stop Mode Recovery
WDT time-out when configured for
interrupt
Stop Mode Recovery followed by interrupt
(if interrupts are enabled)
Data transition on any GPIO Port pin
Stop Mode Recovery
enabled as a Stop Mode Recovery source
PS022517-0508
Reset and Stop Mode Recovery
Z8 Encore! XP® F0822 Series
Product Specification
44
Stop Mode Recovery Using WDT Time-Out
If the WDT times out during STOP mode, the device undergoes a Stop Mode Recovery
sequence. In the WDT Control Register, the WDT and STOP bits are set to 1. If the WDT is
configured to generate an interrupt upon time-out and the Z8 Encore! XP® F0822 Series
device is configured to respond to interrupts, the eZ8 CPU services the WDT interrupt
request following the normal Stop Mode Recovery sequence.
Stop Mode Recovery Using a GPIO Port Pin Transition
Each of the GPIO Port pins can be configured as a Stop Mode Recovery input source. On
any GPIO pin enabled as a STOP Mode Recover source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery. The GPIO Stop
Mode Recovery signals are filtered to reject pulses less than 10 ns (typical) in duration. In
the WDT Control Register, the STOP bit is set to 1.
Caution:
PS022517-0508
In STOP mode, the GPIO Port Input Data Registers (PxIN) are disabled. The Port
Input Data Registers record the Port transition only if the signal stays on the Port
pin through the end of the Stop Mode Recovery delay. Therefore, short pulses on
the Port pin initiates Stop Mode Recovery without being written to the Port Input
Data Register or without initiating an interrupt (if enabled for that pin).
Reset and Stop Mode Recovery
Z8 Encore! XP® F0822 Series
Product Specification
45
Low-Power Modes
Z8 Encore! XP® F0822 Series products contain power-saving features. The highest level
of power reduction is provided by STOP mode. The next level of power reduction is provided by the HALT mode.
STOP Mode
Execution of the eZ8 CPU’s STOP instruction places the device into STOP mode. In
STOP mode, the operating characteristics are:
•
Primary crystal oscillator is stopped; the XIN pin is driven High and the XOUT pin is
driven Low.
•
•
•
•
System clock is stopped.
eZ8 CPU is stopped.
Program counter (PC) stops incrementing.
If enabled for operation in STOP Mode, the WDT and its internal RC oscillator
continue to operate.
•
If enabled for operation in STOP mode through the associated Option Bit,
the VBO protection circuit continues to operate.
•
All other on-chip peripherals are idle.
To minimize current in STOP mode, WDT must be disabled and all GPIO pins configured
as digital inputs must be driven to one of the supply rails (VCC or GND). The device can be
brought out of STOP mode using Stop Mode Recovery. For more information on Stop
Mode Recovery, see Reset and Stop Mode Recovery on page 39.
Caution:
STOP Mode must not be used when driving the Z8F082x family devices with an external clock driver source.
HALT Mode
Execution of the eZ8 CPU’s HALT instruction places the device into HALT mode. In
HALT mode, the operating characteristics are:
•
•
•
•
PS022517-0508
Primary crystal oscillator is enabled and continues to operate.
System clock is enabled and continues to operate.
eZ8 CPU is stopped.
Program counter stops incrementing.
Low-Power Modes
Z8 Encore! XP® F0822 Series
Product Specification
46
•
•
•
WDT’s internal RC oscillator continues to operate.
If enabled, the WDT continues to operate.
All other on-chip peripherals continue to operate.
The eZ8 CPU can be brought out of HALT mode by any of the following operations:
•
•
•
•
•
Interrupt
WDT time-out (interrupt or reset)
Power-On Reset
Voltage Brownout reset
External RESET pin assertion
To minimize current in HALT mode, all GPIO pins which are configured as inputs must be
driven to one of the supply rails (VCC or GND).
PS022517-0508
Low-Power Modes
Z8 Encore! XP® F0822 Series
Product Specification
47
General-Purpose Input/Output
Z8 Encore! XP® F0822 Series products support a maximum of 19 port pins (Ports A–C)
for General-Purpose Input/Output (GPIO) operations. Each port consists Control and Data
Registers. The GPIO Control Registers are used to determine data direction, open-drain,
output drive current, programmable pull-ups, Stop Mode Recovery functionality, and
alternate pin functions. Each port pin is individually programmable. Ports A and C support
5 V-tolerant inputs.
GPIO Port Availability by Device
Table 11 lists the port pins available with each device and package type.
Table 11. Port Availability by Device and Package Type
Devices
Package
Port A
Port B
Port C
Z8X0821, Z8X0811, Z8X0421, Z8X0411 20-pin
[7:0]
[1:0]
[0]
Z8X0822, Z8X0812, Z8X0422, Z8X0412 28-pin
[7:0]
[4:0]
[5:0]
Architecture
Figure 8 displays a simplified block diagram of a GPIO port pin. It does not display the
ability to accommodate alternate functions, variable port current drive strength, and programmable pull-up.
GPIO Alternate Functions
Many of the GPIO port pins are used as both general-purpose I/O and to provide access to
on-chip peripheral functions such as timers and serial communication devices. The
Port A–C Alternate Function sub-registers configure these pins for either general-purpose
I/O or alternate function operation. When a pin is configured for alternate function, control
of the port-pin direction (input/output) is passed from the Port A–C Data Direction
registers to the alternate function assigned to this pin. Table 12 lists the alternate functions
associated with each port pin.
PS022517-0508
General-Purpose Input/Output
Z8 Encore! XP® F0822 Series
Product Specification
48
Schmitt-Trigger
Port Input
Data Register
Q
D
Q
D
System
Clock
VDD
Port Output Control
Port Output
Data Register
DATA
Bus
D
Q
Port
Pin
System
Clock
Port Data Direction
GND
Figure 8. GPIO Port Pin Block Diagram
Table 12. Port Alternate Function Mapping
Port
Pin
Mnemonic
Alternate Function Description
Port A
PA0
T0IN
Timer 0 Input
PA1
T0OUT
Timer 0 Output
PA2
DE
UART 0 Driver Enable
PA3
CTS0
UART 0 Clear to Send
PA4
RXD0 / IRRX0 UART 0 / IrDA 0 Receive Data
PA5
TXD0 / IRTX0
UART 0 / IrDA 0 Transmit Data
PA6
SCL
I2C Clock (automatically open-drain)
PA7
SDA
I2C Data (automatically open-drain)
PB0
ANA0
ADC Analog Input 0
PB1
ANA1
ADC Analog Input 1
PB2
ANA2
ADC Analog Input 2
PB3
ANA3
ADC Analog Input 3
PB4
ANA4
ADC Analog Input 4
Port B
PS022517-0508
General-Purpose Input/Output
Z8 Encore! XP® F0822 Series
Product Specification
49
Table 12. Port Alternate Function Mapping (Continued)
Port
Pin
Mnemonic
Alternate Function Description
Port C
PC0
T1IN
Timer 1 Input
PC1
T1OUT
Timer 1 Output
PC2
SS
SPI Slave Select
PC3
SCK
SPI Serial Clock
PC4
MOSI
SPI Master Out Slave In
PC5
MISO
SPI Master In Slave Out
GPIO Interrupts
Many of GPIO port pins are used as interrupt sources. Some port pins are configured to
generate an interrupt request on either the rising edge or falling edge of the pin input
signal. Other port pin interrupts generate an interrupt when any edge occurs (both rising
and falling). For more details on interrupts using the GPIO pins, see GPIO Port Pin Block
Diagram on page 48.
GPIO Control Register Definitions
Four registers for each port provide access to GPIO control, input data, and output data.
Table 13 lists the GPIO Port Registers and Sub-Registers. Use the Port A–C Address and
Control Registers together to provide access to sub-registers for Port configuration and
control.
Table 13. GPIO Port Registers and Sub-Registers
Port Register Mnemonic
Port Register Name
PxADDR
Port A–C Address Register
(selects sub-registers)
PxCTL
Port A–C Control Register
(provides access to sub-registers)
PxIN
Port A–C Input Data Register
PxOUT
Port A–C Output Data Register
Port Sub-Register Mnemonic Port Register Name
PS022517-0508
PxDD
Data Direction
PxAF
Alternate Function
General-Purpose Input/Output
Z8 Encore! XP® F0822 Series
Product Specification
50
Table 13. GPIO Port Registers and Sub-Registers (Continued)
Port Register Mnemonic
Port Register Name
PxOC
Output Control (Open-Drain)
PxHDE
High Drive Enable
PxSMRE
Stop Mode Recovery Source Enable
PxPUE
Pull-up Enable
Port A–C Address Registers
The Port A–C Address Registers select the GPIO Port functionality accessible through
the Port A–C Control Registers. The Port A–C Address and Control Registers combine to
provide access to all GPIO Port control (Table 14).
Table 14. Port A–C GPIO Address Registers (PxADDR)
BITS
7
6
5
4
3
FIELD
PADDR[7:0]
RESET
00H
R/W
R/W
2
1
0
FD0H, FD4H, FD8H
ADDR
PADDR[7:0]—Port Address
The Port Address selects one of the sub-registers accessible through the Port Control
register.
PADDR[7:0]
PS022517-0508
Port Control Sub-Register Accessible Using the Port A–C
Control Registers
00H
No function. Provides some protection against accidental
Port reconfiguration.
01H
Data Direction
02H
Alternate Function
03H
Output Control (Open-Drain)
04H
High Drive Enable
05H
Stop Mode Recovery Source Enable
06H
Pull-up Enable
07H–FFH
No Function
General-Purpose Input/Output
Z8 Encore! XP® F0822 Series
Product Specification
51
Port A–C Control Registers
The Port A–C Control Registers set the GPIO port operation. The value in the corresponding Port A–C Address Register determines the control sub-registers accessible using the
Port A–C Control Register (Table 15).
Table 15. Port A–C Control Registers (PxCTL)
BITS
7
6
5
4
3
FIELD
PCTL
RESET
00H
R/W
R/W
2
1
0
FD1H, FD5H, FD9H
ADDR
PCTL[7:0]—Port Control
The Port Control Register provides access to all sub-registers that configure the GPIO Port
operation.
Port A–C Data Direction Sub-Registers
The Port A–C Data Direction sub-register is accessed through the Port A–C Control
register by writing 01H to the Port A–C Address Register (Table 16).
Table 16. Port A–C Data Direction Sub-Registers
BITS
FIELD
7
6
DD7
5
DD6
4
DD5
2
DD3
1
DD2
0
DD1
DD0
1
RESET
R/W
R/W
ADDR
3
DD4
If 01H in Port A–C Address Register, accessible through the Port A–C Control Register
DD[7:0]—Data Direction
These bits control the direction of the associated port pin. Port Alternate Function
operation overrides the Data Direction register setting.
0 = Output. Data in the Port A–C Output Data Register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A–C Input
Data Register. The output driver is tri-stated.
Port A–C Alternate Function Sub-Registers
The Port A–C Alternate Function sub-register (Table 17) is accessed through the
Port A–C Control Register by writing 02H to the Port A–C Address Register. The
Port A–C Alternate Function sub-registers select the alternate functions for the selected
PS022517-0508
General-Purpose Input/Output
Z8 Encore! XP® F0822 Series
Product Specification
52
pins.To determine the alternate function associated with each port pin, see GPIO Port Pin
Block Diagram on page 48.
Caution: Do not enable alternate function for GPIO port pins which do not have an associated
alternate function. Failure to follow this guideline can result in unpredictable operation.
Table 17. Port A–CA–C Alternate Function Sub-Registers
BITS
7
6
AF7
FIELD
5
AF6
4
AF5
3
AF4
2
AF3
1
AF2
0
AF1
AF0
0
RESET
R/W
R/W
If 02H in Port A–C Address Register, accessible through the Port A–C Control Register
ADDR
AF[7:0]—Port Alternate Function enabled
0 = The port pin is in NORMAL mode and the DDx bit in the Port A–C Data
Direction sub-register determines the direction of the pin.
1 = The alternate function is selected. Port pin operation is controlled by the
alternate function.
Port A–C Output Control Sub-Registers
The Port A–C Output Control sub-register (Table 18) is accessed through the Port A–C
Control Register by writing 03H to the Port A–C Address Register. Setting the bits in the
Port A–C Output Control sub-registers to 1 configures the specified port pins for
open-drain operation. These sub-registers affect the pins directly and, as a result,
alternate functions are also affected.
Table 18. Port A–C Output Control Sub-Registers
BITS
FIELD
7
6
POC7
5
POC6
4
POC5
3
POC4
POC3
1
POC2
0
POC1
POC0
0
RESET
R/W
R/W
ADDR
2
If 03H in Port A–C Address Register, accessible through the Port A–C Control Register
POC[7:0]—Port Output Control
These bits function independently of the alternate function bit and always disable the
drains if set to 1.
0 = The drains are enabled for any output mode (unless overridden by the
PS022517-0508
General-Purpose Input/Output
Z8 Encore! XP® F0822 Series
Product Specification
53
alternate function).
1 = The drain of the associated pin is disabled (open-drain mode).
Port A–C High Drive Enable Sub-Registers
The Port A–C High Drive Enable sub-register (Table 19) is accessed through the
Port A–C Control Register by writing 04H to the Port A–C Address Register. Setting the
bits in the Port A–C High Drive Enable sub-registers to 1 configures the specified port
pins for high current output drive operation. The Port A–C High Drive Enable sub-register
affects the pins directly and, as a result, alternate functions are also affected.
Table 19. Port A–C High Drive Enable Sub-Registers
BITS
7
6
PHDE7
FIELD
5
PHDE6
4
PHDE5
3
PHDE4
2
PHDE3
1
PHDE2
0
PHDE1
PHDE0
0
RESET
R/W
R/W
If 04H in Port A–C Address Register, accessible through the Port A–C Control Register
ADDR
PHDE[7:0]—Port High Drive Enabled
0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Port A–C Stop Mode Recovery Source Enable Sub-Registers
The Port A–C Stop Mode Recovery Source Enable sub-register (Table 20) is accessed
through the Port A–C Control Register by writing 05H to the Port A–C Address Register.
Setting the bits in the Port A–C Stop Mode Recovery Source Enable sub-registers to 1
configures the specified Port pins as a Stop Mode Recovery source. During STOP Mode,
any logic transition on a Port pin enabled as a Stop Mode Recovery source initiates Stop
Mode Recovery.
Table 20. Port A–C Stop Mode Recovery Source Enable Sub-Registers
BITS
FIELD
7
6
PSMRE7
RESET
R/W
ADDR
PSMRE6
5
PSMRE5
4
3
2
1
0
PSMRE4
PSMRE3
PSMRE2
PSMRE1
PSMRE0
0
R/W
If 05H in Port A–C Address Register, accessible through the Port A–C Control Register
PSMRE[7:0]—Port Stop Mode Recovery Source Enabled
0 = The port pin is not configured as a Stop Mode Recovery source. Transitions on
this pin during STOP mode does not initiate Stop Mode Recovery.
PS022517-0508
General-Purpose Input/Output
Z8 Encore! XP® F0822 Series
Product Specification
54
1 = The port pin is configured as a Stop Mode Recovery source. Any logic transition
on this pin during STOP mode initiates Stop Mode Recovery.
Port A–C Pull-up Enable Sub-Registers
The Port A–C Pull-Up Enable sub-register (Table 21) is accessed through the Port A–C
Control Register by writing 06H to the Port A–C Address Register. Setting the bits in the
Port A–C Pull-Up Enable sub-registers enables a weak internal resistive pull-up on the
specified Port pins.
Table 21. Port A–C Pull-Up Enable Sub-Registers
BITS
FIELD
7
6
PPUE7
5
PPUE6
4
PPUE5
3
PPUE4
RESET
2
PPUE3
1
PPUE2
0
PPUE1
PPUE0
0
R/W
R/W
ADDR
If 06H in Port A–C Address Register, accessible through the Port A–C Control Register
PPUE[7:0]—Port Pull-up Enabled
0 = The weak pull-up on the Port pin is disabled.
1 = The weak pull-up on the Port pin is enabled.
Port A–C Input Data Registers
Reading from the Port A–C Input Data Registers (Table 22) returns the sampled values
from the corresponding port pins. The Port A–C Input Data Registers are Read-only.
Table 22. Port A–C Input Data Registers (PxIN)
7
6
5
4
3
2
1
0
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
BITS
FIELD
RESET
X
R/W
R
FD2H, FD6H, FDAH
ADDR
PIN[7:0]—Port Input Data
Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low).
1 = Input data is logical 1 (High).
PS022517-0508
General-Purpose Input/Output
Z8 Encore! XP® F0822 Series
Product Specification
55
Port A–C Output Data Register
The Port A–C Output Data Register (Table 23) controls the output data to the pins.
Table 23. Port A–C Output Data Register (PxOUT)
BITS
FIELD
7
6
POUT7
5
POUT6
4
POUT5
3
POUT4
1
POUT2
0
POUT1
POUT0
0
RESET
R/W
R/W
ADDR
2
POUT3
FD3H, FD7H, FDBH
POUT[7:0]—Port Output Data
These bits contain the data to be driven to the port pins. The values are only driven if the
corresponding pin is configured as an output and the pin is not configured for alternate
function operation.
0 = Drive a logical 0 (Low).
1 = Drive a logical 1 (High). High value is not driven if the drain has been disabled
by setting the corresponding Port Output Control Register bit to 1.
PS022517-0508
General-Purpose Input/Output
Z8 Encore! XP® F0822 Series
Product Specification
56
PS022517-0508
General-Purpose Input/Output
Z8 Encore! XP® F0822 Series
Product Specification
57
Interrupt Controller
The interrupt controller on Z8 Encore! XP® F0822 Series products prioritizes the interrupt
requests from the on-chip peripherals and the GPIO port pins. The features of the interrupt
controller include the following:
• 19 unique interrupt vectors:
– 12 GPIO port pin interrupt sources.
– 7 On-chip peripheral interrupt sources.
• Flexible GPIO interrupts:
– 8 selectable rising and falling edge GPIO interrupts.
– 4 dual-edge interrupts.
• Three levels of individually programmable interrupt priority.
• WDT is configured to generate an interrupt.
Interrupt Requests (IRQs) allow peripheral devices to suspend CPU operation in an
orderly manner and force the CPU to start an Interrupt Service Routine (ISR). Usually this
ISR is involved with the exchange of data, status information, or control information
between the CPU and the interrupting peripheral. When the service routine is
completed, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt control has no effect on operation. For more information on interrupt servicing, refer to eZ8 CPU Core User Manual (UM0128) available for download at
www.zilog.com.
Interrupt Vector Listing
Table 24 lists all the interrupts available in order of priority. The interrupt vector is stored
with the most significant byte (MSB) at the even Program Memory address and the least
significant byte (LSB) at the following odd Program Memory address.
Table 24. Interrupt Vectors in Order of Priority
PS022517-0508
Priority
Program Memory
Vector Address
Interrupt Source
Highest
0002H
Reset (not an interrupt)
0004H
WDT (see Watchdog Timer on page 83)
0006H
Illegal Instruction Trap (not an interrupt)
Interrupt Controller
Z8 Encore! XP® F0822 Series
Product Specification
58
Table 24. Interrupt Vectors in Order of Priority (Continued)
Priority
Lowest
PS022517-0508
Program Memory
Vector Address
Interrupt Source
0008H
Reserved
000AH
Timer 1
000CH
Timer 0
000EH
UART 0 receiver
0010H
UART 0 transmitter
0012H
I 2C
0014H
SPI
0016H
ADC
0018H
Port A7, rising or falling input edge
001AH
Port A6, rising or falling input edge
001CH
Port A5, rising or falling input edge
001EH
Port A4, rising or falling input edge
0020H
Port A3, rising or falling input edge
0022H
Port A2, rising or falling input edge
0024H
Port A1, rising or falling input edge
0026H
Port A0, rising or falling input edge
0028H
Reserved
002AH
Reserved
002CH
Reserved
002EH
Reserved
0030H
Port C3, both input edges
0032H
Port C2, both input edges
0034H
Port C1, both input edges
0036H
Port C0, both input edges
Interrupt Controller
Z8 Encore! XP® F0822 Series
Product Specification
59
Architecture
Figure 9 displays a block diagram of the interrupt controller.
Interrupt Request Latches and Control
Port Interrupts
Internal Interrupts
High
Priority
Vector
Medium
Priority
Priority
Mux
IRQ Request
Low
Priority
Figure 9. Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control Register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
• Execution of an EI (Enable Interrupt) instruction.
• Execution of an IRET (Return from Interrupt) instruction.
• Writing a 1 to the IRQE bit in the Interrupt Control Register.
Interrupts are globally disabled by any of the following actions:
•
•
•
•
•
•
PS022517-0508
Execution of a DI (Disable Interrupt) instruction.
eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller.
Writing a 0 to the IRQE bit in the Interrupt Control Register.
Reset.
Execution of a Trap instruction.
Illegal Instruction trap.
Interrupt Controller
Z8 Encore! XP® F0822 Series
Product Specification
60
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all the
interrupts were enabled with identical interrupt priority (all as Level 2 interrupts), then
interrupt priority would be assigned from highest to lowest as specified in Table 24.
Level 3 interrupts always have higher priority than Level 2 interrupts which in turn always
have higher priority than Level 1 interrupts. Within each interrupt priority level (Level 1,
Level 2, or Level 3), priority is assigned as specified in Table 24. Reset, WDT interrupt (if
enabled), and Illegal Instruction Trap always have highest priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period
(single pulse). When the interrupt request is acknowledged by the eZ8 CPU, the corresponding bit in the Interrupt Request Register is cleared until the next interrupt occurs.
Writing a 0 to the corresponding bit in the Interrupt Request Register likewise clears
the interrupt request.
Caution: The following style of coding to clear bits in the Interrupt Request Registers
is not recommended. All incoming interrupts received between execution of
the first LDX command and the last LDX command is lost.
Poor coding style resulting in lost interrupt requests:
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
Note: To avoid missing interrupts, the following style of coding to clear bits in the
Interrupt Request 0 register is recommended:
Good coding style that avoids lost interrupt requests:
ANDX IRQ0, MASK
Software Interrupt Assertion
Program code generates interrupts directly. Writing 1 to the desired bit in the Interrupt
Request Register triggers an interrupt (assuming that interrupt is enabled). When the
interrupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request Register is automatically cleared to 0.
Caution:
PS022517-0508
The following style of coding to generate software interrupts by setting bits
in the Interrupt Request Registers is not recommended. All incoming
interrupts received between execution of the first LDX command and the last
LDX command is lost.
Interrupt Controller
Z8 Encore! XP® F0822 Series
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Poor coding style that resulting in lost interrupt requests:
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
Note:
To avoid missing interrupts, the following style of coding to set bits in the
Interrupt Request Registers is recommended
Good coding style that avoids lost interrupt requests:
ORX IRQ0, MASK
Interrupt Control Register Definitions
For all interrupts other than the WDT interrupt, the Interrupt Control Registers enable
individual interrupts, set interrupt priorities, and indicate interrupt requests.
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) Register (Table 25) stores the interrupt requests for both
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ0 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU.
If interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the IRQ0
Register to determine if any interrupt requests are pending.
Table 25. Interrupt Request 0 Register (IRQ0)
BITS
7
6
FIELD
Reserved
5
T1I
4
T0I
3
U0RXI
2
U0TXI
1
I2CI
0
SPII
ADCI
0
RESET
R/W
R/W
FC0H
ADDR
Reserved—Must be 0
T1I—Timer 1 Interrupt Request
0 = No interrupt request is pending for Timer 1.
1 = An interrupt request from Timer 1 is awaiting service.
T0I—Timer 0 Interrupt Request
0 = No interrupt request is pending for Timer 0.
1 = An interrupt request from Timer 0 is awaiting service.
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U0RXI—UART 0 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 0 receiver.
1 = An interrupt request from the UART 0 receiver is awaiting service.
U0TXI—UART 0 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 0 transmitter.
1 = An interrupt request from the UART 0 transmitter is awaiting service.
I2CI— I2C Interrupt Request
0 = No interrupt request is pending for the I2C.
1 = An interrupt request from the I2C is awaiting service.
SPII—SPI Interrupt Request
0 = No interrupt request is pending for the SPI.
1 = An interrupt request from the SPI is awaiting service.
ADCI—ADC Interrupt Request
0 = No interrupt request is pending for the ADC.
1 = An interrupt request from the ADC is awaiting service.
Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) Register (Table 26) stores interrupt requests for both
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ1 register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU.
If interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the IRQ1
Register to determine if any interrupt requests are pending.
Table 26. Interrupt Request 1 Register (IRQ1)
BITS
FIELD
7
6
PA7I
RESET
R/W
ADDR
5
PA6I
4
PA5I
3
PA4I
2
PA3I
PA2I
1
0
PA1I
PA0I
0
R/W
FC3H
PAxI—Port A Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port A pin x.
1 = An interrupt request from GPIO Port A pin x is awaiting service.
Where x indicates the specific GPIO Port pin number (0 through 7).
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Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) Register (Table 27) stores interrupt requests for both
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ2 register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU.
If interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the IRQ2
Register to determine if any interrupt requests are pending.
Table 27. Interrupt Request 2 Register (IRQ2)
BITS
7
6
5
4
3
Reserved
FIELD
2
PC3I
1
PC2I
0
PC1I
PC0I
0
RESET
R/W
R/W
FC6H
ADDR
Reserved—Must be 0
PCxI—Port C Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
Where x indicates the specific GPIO Port C pin number (0 through 3).
IRQ0 Enable High and Low Bit Registers
The IRQ0 Enable High and Low Bit Registers (Table 29 and Table 30) form a priority
encoded enabling for interrupts in the Interrupt Request 0 Register. Priority is generated
by setting bits in each register. Table 28 describes the priority control for IRQ0.
Table 28. IRQ0 Enable and Priority Encoding
IRQ0ENH[x]
IRQ0ENL[x]
Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
where x indicates the register bits from 0 through 7.
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Table 29. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS
FIELD
7
6
5
4
3
2
1
0
Reserved
T1ENH
T0ENH
U0RENH
U0TENH
I2CENH
SPIENH
ADCENH
0
RESET
R/W
R/W
FC1H
ADDR
Reserved—Must be 0
T1ENH—Timer 1 Interrupt Request Enable High Bit
T0ENH—Timer 0 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
I2CENH—I2C Interrupt Request Enable High Bit
SPIENH—SPI Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
Table 30. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS
7
6
FIELD
Reserved
5
T1ENL
4
T0ENL
3
U0RENL
U0TENL
2
1
I2CENL
0
SPIENL
ADCENL
0
RESET
R/W
R/W
FC2H
ADDR
Reserved—Must be 0
T1ENL—Timer 1 Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
I2CENL—I2C Interrupt Request Enable Low Bit
SPIENL—SPI Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
IRQ1 Enable High and Low Bit Registers
Table 31 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit
Registers (Table 32 and Table 33) form a priority encoded enabling for interrupts in the
Interrupt Request 1 Register. Priority is generated by setting bits in each register.
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Table 31. IRQ1 Enable and Priority Encoding
IRQ1ENH[x]
IRQ1ENL[x]
Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
where x indicates the register bits from 0 through 7.
Table 32. IRQ1 Enable High Bit Register (IRQ1ENH)
BITS
FIELD
7
6
PA7ENH
PA6ENH
5
PA5ENH
4
3
PA4ENH
PA3ENH
2
PA2ENH
1
0
PA1ENH
PA0ENH
0
RESET
R/W
R/W
FC4H
ADDR
PAxENH—Port A Bit[x] Interrupt Request Enable High Bit
Table 33. IRQ1 Enable Low Bit Register (IRQ1ENL)
BITS
FIELD
7
6
PA7ENL
PA6ENL
5
PA5ENL
4
3
PA4ENL
PA3ENL
2
PA2ENL
1
0
PA1ENL
PA0ENL
0
RESET
R/W
R/W
FC5H
ADDR
PAxENL—Port A Bit[x] Interrupt Request Enable Low Bit
IRQ2 Enable High and Low Bit Registers
Table 34 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit
Registers (Table 35 and Table 36) form a priority encoded enabling for interrupts in the
Interrupt Request 2 register. Priority is generated by setting bits in each register.
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Table 34. IRQ2 Enable and Priority Encoding
IRQ2ENH[x]
IRQ2ENL[x]
Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
where x indicates the register bits from 0 through 7.
Table 35. IRQ2 Enable High Bit Register (IRQ2ENH)
BITS
7
6
5
4
3
Reserved
FIELD
2
C3ENH
1
C2ENH
0
C1ENH
C0ENH
0
RESET
R/W
R/W
FC7H
ADDR
Reserved—Must be 0.
C3ENH—Port C3 Interrupt Request Enable High Bit
C2ENH—Port C2 Interrupt Request Enable High Bit
C1ENH—Port C1 Interrupt Request Enable High Bit
C0ENH—Port C0 Interrupt Request Enable High Bit
Table 36. IRQ2 Enable Low Bit Register (IRQ2ENL)
BITS
7
FIELD
RESET
R/W
ADDR
6
5
4
3
Reserved
2
C3ENL
1
C2ENL
0
C1ENL
C0ENL
0
R/W
FC8H
Reserved—Must be 0.
C3ENL—Port C3 Interrupt Request Enable Low Bit
C2ENL—Port C2 Interrupt Request Enable Low Bit
C1ENL—Port C1 Interrupt Request Enable Low Bit
C0ENL—Port C0 Interrupt Request Enable Low Bit
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Interrupt Edge Select Register
The Interrupt Edge Select (IRQES) register (Table 37) determines whether an interrupt is
generated for the rising edge or falling edge on the selected GPIO Port input pin. The
minimum pulse width must be greater than 1 system clock to guarantee capture of the edge
triggered interrupt. Edge detection for pulses less than 1 system clock are not guaranteed.
Table 37. Interrupt Edge Select Register (IRQES)
BITS
7
6
IES7
FIELD
5
IES6
4
IES5
3
IES4
2
IES3
1
IES2
0
IES1
IES0
0
RESET
R/W
R/W
FCDH
ADDR
IESx—Interrupt Edge Select x
0 = An interrupt request is generated on the falling edge of the PAx input.
1 = An interrupt request is generated on the rising edge of the PAx input.
Where x indicates the specific GPIO Port pin number (0 through 7).
Interrupt Control Register
The Interrupt Control (IRQCTL) register (Table 38) contains the master enable bit for all
interrupts.
Table 38. Interrupt Control Register (IRQCTL)
BITS
FIELD
7
6
5
3
IRQE
2
1
0
Reserved
0
RESET
R/W
4
R/W
R
FCFH
ADDR
IRQE—Interrupt Request Enable
This bit is set to 1 by execution of an EI (Enable Interrupts) or IRET (Interrupt Return)
instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a
DI instruction, eZ8 CPU acknowledgement of an interrupt request, Reset or by a direct
register write of a 0 to this bit.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
Reserved—Must be 0
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PS022517-0508
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Timers
Z8 Encore! XP® F0822 Series products contain up to two 16-bit reloadable timers that can
be used for timing, event counting, or generation of pulse-width modulated signals. The
timer features include:
•
•
•
•
•
16-bit reload counter.
•
•
Timer output pin.
Programmable prescaler with prescale values from 1 to 128.
PWM output generation.
Capture and compare capability.
External input pin for timer input, clock gating, or capture signal. External input pin
signal frequency is limited to a maximum of one-fourth the system clock frequency.
Timer interrupt.
In addition to the timers described in this chapter, the Baud Rate Generators for any
unused UART, SPI, or I2C peripherals can also be used to provide basic timing
functionality. See the respective serial communication peripheral chapters for
information on using the Baud Rate Generators as timers.
Architecture
Figure 10 displays the architecture of the timers.
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value
0001H into the Timer Reload High and Low Byte registers and setting the prescale value
to 1. Maximum time-out delay is set by loading the value 0000H into the Timer Reload
High and Low Byte registers and setting the prescale value to 128. If the Timer reaches
FFFFH, the timer rolls over to 0000H and continues counting.
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Timer Block
Block
Control
16-Bit
Reload Register
System
Clock
Compare
Timer
Control
Data
Bus
Interrupt,
PWM,
and
Timer Output
Control
Gate
Input
16-Bit
PWM / Compare
Timer
Output
Compare
16-Bit Counter
with Prescaler
Timer
Input
Timer
Interrupt
Capture
Input
Figure 10. Timer Block Diagram
Timer Operating Modes
The timers are configured to operate in the following modes:
ONE-SHOT Mode
In ONE-SHOT mode, the timer counts up to the 16-bit Reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. On reaching the
Reload value, the timer generates an interrupt and the count value in the Timer High and
Low Byte registers is reset to 0001H. Then, the timer is automatically disabled and stops
counting.
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes
state for one system clock cycle (from Low to High or vice-versa) on timer Reload.
If it is required for the Timer Output to make a permanent state change on One-Shot
time-out, first set the TPOL bit in the Timer Control Register to the start value before
beginning ONE-SHOT mode. Then, after starting the timer, set TPOL to the opposite bit
value.
Follow the steps below for configuring a timer for ONE-SHOT mode and initiating the
count:
1. Write to the Timer Control Register to:
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Disable the timer
–
Configure the timer for ONE-SHOT mode
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–
–
Set the prescale value
If using the Timer Output alternate function, set the initial output level
(High or Low).
2. Write to the Timer High and Low Byte Registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte Registers to set the Reload value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control Register to enable the timer and initiate counting.
In ONE-SHOT mode, the system clock always provides the timer input. The timer period
is given by the following equation:
( Reload Value – Start Value )xPrescale
ONE-SHOT Mode Time-Out Period (s) = ------------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
CONTINUOUS Mode
In CONTINUOUS mode, the timer counts up to the 16-bit Reload value stored in the
Timer Reload High and Low Byte Registers. The timer input is the system clock. Upon
reaching the Reload value, the timer generates an interrupt, the count value in the Timer
High and Low Byte Registers is reset to 0001H and counting resumes. Also, if the Timer
Output alternate function is enabled, the Timer Output pin changes state (from Low to
High or from High to Low) upon timer Reload.
Follow the steps below for configuring a timer for CONTINUOUS mode and initiating the
count:
1. Write to the Timer Control Register to:
– Disable the timer
– Configure the timer for CONTINUOUS mode
– Set the prescale value.
– If using the Timer Output alternate function, set the initial output level
(High or Low).
2. Write to the Timer High and Low Byte registers to set the starting count value (usually
0001H). This only affects the first pass in CONTINUOUS mode. After the first timer
Reload in CONTINUOUS mode, counting always begins at the reset value of 0001H.
3. Write to the Timer Reload High and Low Byte Registers to set the Reload value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
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6. Write to the Timer Control Register to enable the timer and initiate counting.
In CONTINUOUS mode, the system clock always provides the timer input. The timer
period is given by the following equation:
Reload Value x Prescale
CONTINUOUS Mode Time-Out Period (s) = ------------------------------------------------------------------------------System Clock Frequency (Hz)
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
Registers, the ONE-SHOT mode equation must be used to determine the first time-out
period.
COUNTER Mode
In COUNTER mode, the timer counts input transitions from a GPIO port pin. The timer
input is taken from the GPIO Port pin Timer Input alternate function. The TPOL bit in the
Timer Control Register selects whether the count occurs on the rising edge or the falling
edge of the Timer Input signal. In COUNTER mode, the prescaler is disabled.
Caution: The input frequency of the Timer Input signal must not exceed one-fourth system clock
frequency.
Upon reaching the Reload value stored in the Timer Reload High and Low Byte Registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte Registers
is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is
enabled, the Timer Output pin changes state (from Low to High or from High to Low) at
timer Reload.
Follow the steps below for configuring a timer for COUNTER mode and initiating the
count:
1. Write to the Timer Control Register to:
– Disable the timer
– Configure the timer for COUNTER mode.
– Select either the rising edge or falling edge of the Timer Input signal for the count.
This also sets the initial logic level (High or Low) for the Timer Output alternate
function. However, the Timer Output function does not have to be enabled.
2. Write to the Timer High and Low Byte Registers to set the starting count value. This
only affects the first pass in COUNTER mode. After the first timer Reload in
COUNTER mode, counting always begins at the reset value of 0001H. Generally, in
COUNTER mode the Timer High and Low Byte Registers must be written with the
value 0001H.
3. Write to the Timer Reload High and Low Byte Registers to set the Reload value.
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4. If required, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
7. Write to the Timer Control Register to enable the timer.
In COUNTER mode, the number of Timer Input transitions since the timer start is given
by the following equation:
COUNTER Mode Timer Input Transitions = Current Count Value – Start Value
PWM Mode
In PWM mode, the timer outputs a Pulse-Width Modulator output signal through a GPIO
port pin. The timer input is the system clock. The timer first counts up to the 16-bit PWM
match value stored in the Timer PWM High and Low Byte Registers. When the timer
count value matches the PWM value, the Timer Output toggles. The timer continues
counting until it reaches the Reload value stored in the Timer Reload High and Low Byte
registers. Upon reaching the Reload value, the timer generates an interrupt, the count
value in the Timer High and Low Byte Registers is reset to 0001H and counting resumes.
If the TPOL bit in the Timer Control Register is set to 1, the Timer Output signal begins as
a High (1) and then transitions to a Low (0) when the timer value matches the PWM value.
The Timer Output signal returns to a High (1) after the timer reaches the Reload value and
is reset to 0001H.
If the TPOL bit in the Timer Control Register is set to 0, the Timer Output signal begins as
a Low (0) and then transitions to a High (1) when the timer value matches the PWM value.
The Timer Output signal returns to a Low (0) after the timer reaches the Reload value and
is reset to 0001H.
Follow the steps below for configuring a timer for PWM mode and initiating the PWM
operation:
1. Write to the Timer Control Register to:
– Disable the timer
– Configure the timer for PWM mode.
– Set the prescale value.
– Set the initial logic level (High or Low) and PWM High/Low transition for the
Timer Output alternate function.
2. Write to the Timer High and Low Byte Registers to set the starting count value
(typically 0001H). This only affects the first pass in PWM mode. After the first timer
reset in PWM mode, counting always begins at the reset value of 0001H.
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3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the Timer Reload High and Low Byte Registers to set the Reload value
(PWM period). The Reload value must be greater than the PWM value.
5. If required, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
6. Configure the associated GPIO port pin for the Timer Output alternate function.
7. Write to the Timer Control Register to enable the timer and initiate counting.
The PWM period is given by the following equation.
Reload Value x Prescale
PWM Period (s) = ------------------------------------------------------------------------------System Clock Frequency (Hz)
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
Registers, the ONE-SHOT mode equation is used to determine the first PWM time-out
period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is given by
Reload Value – PWM Value
PWM Output High Time Ratio (%) = -------------------------------------------------------------------------x100
Reload Value
If TPOL is set to 1, the ratio of the PWM output High time to the total period is given by
PWM Value
PWM Output High Time Ratio (%) = ------------------------------------ x100
Reload Value
CAPTURE Mode
In CAPTURE mode, the current timer count value is recorded when the desired external
Timer Input transition occurs. The Capture count value is written to the Timer PWM High
and Low Byte Registers. The timer input is the system clock. The TPOL bit in the Timer
Control Register determines if the Capture occurs on a rising edge or a falling edge of the
Timer Input signal. When the Capture event occurs, an interrupt is generated and the timer
continues counting.
The timer continues counting up to the 16-bit Reload value stored in the Timer Reload
High and Low Byte registers. Upon reaching the Reload value, the timer generates an
interrupt and continues counting.
Follow the steps below for configuring a timer for CAPTURE mode and initiating the
count:
1. Write to the Timer Control Register to:
– Disable the timer
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–
–
–
Configure the timer for CAPTURE mode
Set the prescale value
Set the Capture edge (rising or falling) for the Timer Input
2. Write to the Timer High and Low Byte Registers to set the starting count value
(typically 0001H).
3. Write to the Timer Reload High and Low Byte Registers to set the Reload value.
4. Clear the Timer PWM High and Low Byte Registers to 0000H. This allows user
software to determine if interrupts were generated by either a capture event or a
reload. If the PWM High and Low Byte Registers still contains 0000H after the
interrupt, then the interrupt was generated by a Reload.
5. If required, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
6. Configure the associated GPIO port pin for the Timer Input alternate function.
7. Write to the Timer Control Register to enable the timer and initiate counting.
In CAPTURE mode, the elapsed time from timer start to Capture event is calculated using
the following equation:
( Capture Value – Start Value )xPrescale
Capture Elapsed Time (s) = ---------------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
COMPARE Mode
In COMPARE mode, the timer counts up to the 16-bit maximum Compare value stored
in the Timer Reload High and Low Byte Registers. The timer input is the system clock.
Upon reaching the Compare value, the timer generates an interrupt and counting continues
(the timer value is not reset to 0001H). Also, if the Timer Output alternate function is
enabled, the Timer Output pin changes state (from Low to High or from High to Low)
upon Compare.
If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting.
Follow the steps below for configuring a timer for COMPARE mode and initiating the
count:
1. Write to the Timer Control Register to:
– Disable the timer
– Configure the timer for COMPARE mode
– Set the prescale value
– Set the initial logic level (High or Low) for the Timer Output alternate function, if
required
2. Write to the Timer High and Low Byte registers to set the starting count value
3. Write to the Timer Reload High and Low Byte registers to set the Compare value
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4. If required, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function
6. Write to the Timer Control Register to enable the timer and initiate counting
In COMPARE mode, the system clock always provides the timer input. The
Compare time is calculated by the following equation:
( Compare Value – Start Value ) x Prescale
Compare Mode Time (s) = ------------------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
GATED Mode
In GATED mode, the timer counts only when the Timer Input signal is in its active state
(asserted), as determined by the TPOL bit in the Timer Control Register. When the Timer
Input signal is asserted, counting begins. A timer interrupt is generated when the Timer
Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal
deassertion generated the interrupt, read the associated GPIO input value and compare to
the value stored in the TPOL bit.
The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low
Byte Registers. The timer input is the system clock. When reaching the Reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte Registers is
reset to 0001H and counting resumes (assuming the Timer Input signal is still asserted).
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reset.
Follow the steps below for configuring a timer for GATED mode and initiating the count:
1. Write to the Timer Control Register to:
– Disable the timer
– Configure the timer for GATED mode
– Set the prescale value
2. Write to the Timer High and Low Byte Registers to set the starting count value. This
only affects the first pass in GATED mode. After the first timer reset in GATED mode,
counting always begins at the reset value of 0001H
3. Write to the Timer Reload High and Low Byte Registers to set the Reload value
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers
5. Configure the associated GPIO port pin for the Timer Input alternate function
6. Write to the Timer Control Register to enable the timer
7. Assert the Timer Input signal to initiate the counting
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CAPTURE/COMPARE Mode
In CAPTURE/COMPARE mode, the timer begins counting on the first external Timer
Input transition. The required transition (rising edge or falling edge) is set by the TPOL bit
in the Timer Control Register. The timer input is the system clock.
Every subsequent desired transition (after the first) of the Timer Input signal captures the
current count value. The Capture value is written to the Timer PWM High and Low Byte
Registers. When the Capture event occurs, an interrupt is generated, the count value in the
Timer High and Low Byte Registers is reset to 0001H and counting resumes.
If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer
generates an interrupt, the count value in the Timer High and Low Byte Registers is reset
to 0001H and counting resumes.
Follow the steps below for configuring a timer for CAPTURE/COMPARE mode and initiating the count:
1. Write to the Timer Control Register to:
– Disable the timer
– Configure the timer for CAPTURE/COMPARE mode
– Set the prescale value
– Set the Capture edge (rising or falling) for the Timer Input
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H)
3. Write to the Timer Reload High and Low Byte registers to set the Compare value
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers
5. Configure the associated GPIO port pin for the Timer Input alternate function
6. Write to the Timer Control Register to enable the timer
7. Counting begins on the first appropriate transition of the Timer Input signal.
No interrupt is generated by this first edge
In CAPTURE/COMPARE mode, the elapsed time from timer start to Capture event is
calculated using the following equation:
( Capture Value – Start Value )xPrescale
Capture Elapsed Time (s) = ---------------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
Reading the Timer Count Values
The current count value in the timers can be read while counting (enabled). This capability
has no effect on timer operation. When the timer is enabled and the Timer High Byte
PS022517-0508
Timers
Z8 Encore! XP® F0822 Series
Product Specification
78
Register is read, the contents of the Timer Low Byte Register are placed in a holding
register. A subsequent read from the Timer Low Byte Register returns the value in the
holding register. This operation allows accurate reads of the full 16-bit timer count value
while enabled. When the timers are not enabled, a read from the Timer Low Byte Register
returns the actual value in the counter.
Timer Output Signal Operation
Timer Output is a GPIO port pin alternate function. Generally, the Timer Output is toggled
every time the counter is reloaded.
Timer Control Register Definitions
Timer 0–1 High and Low Byte Registers
The Timer 0–1 High and Low Byte (TxH and TxL) Registers (Table 39) contain the
current 16-bit timer count value. When the timer is enabled, a read from TxH causes the
value in TxL to be stored in a temporary holding register. A read from TMRL always
returns this temporary register when the timers are enabled. When the timer is disabled,
reads from the TMRL reads the register directly.
Writing to the Timer High and Low Byte Registers while the timer is enabled is not
recommended. There are no temporary holding registers available for write operations,
so simultaneous 16-bit writes are not possible. If either the Timer High or Low Byte
Registers are written during counting, the 8-bit written value is placed in the counter (High
or Low Byte) at the next clock edge. The counter continues counting from the new value.
Table 39. Timer 0–1 High Byte Register (TxH)
BITS
7
6
5
4
3
FIELD
TH
RESET
0
2
1
0
2
1
0
R/W
R/W
F00H, F08H
ADDR
Table 40. Timer 0–1 Low Byte Register (TxL)
BITS
7
6
5
4
3
TL
FIELD
RESET
R/W
ADDR
PS022517-0508
0
1
R/W
F01H, F09H
Timers
Z8 Encore! XP® F0822 Series
Product Specification
79
TH and TL—Timer High and Low Bytes
These 2 bytes, {TMRH[7:0], TMRL[7:0]}, contain the current 16-bit timer count value.
Timer Reload High and Low Byte Registers
The Timer 0–1 Reload High and Low Byte (TxRH and TxRL) Registers (Table 41) store a
16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer Reload High Byte
register are stored in a temporary holding register. When a write to the Timer Reload Low
Byte Register occurs, the temporary holding register value is written to the Timer High
Byte Register. This operation allows simultaneous updates of the 16-bit Timer Reload
value.
In COMPARE mode, the Timer Reload High and Low Byte Registers store the 16-bit
Compare value.
Table 41. Timer 0–1 Reload High Byte Register (TxRH)
BITS
7
6
5
4
3
FIELD
TRH
RESET
1
2
1
0
2
1
0
R/W
R/W
F02H, F0AH
ADDR
Table 42. Timer 0–1 Reload Low Byte Register (TxRL)
BITS
7
6
5
4
3
FIELD
TRL
RESET
1
R/W
R/W
F03H, F0BH
ADDR
TRH and TRL—Timer Reload Register High and Low
These two bytes form the 16-bit Reload value, {TRH[7:0], TRL[7:0]}. This value sets the
maximum count value which initiates a timer reload to 0001H. In COMPARE mode, these
two bytes form the 16-bit Compare value.
Timer 0–1 PWM High and Low Byte Registers
The Timer 0–1 PWM High and Low Byte (TxPWMH and TxPWML) registers (Table 43
and Table 44) are used for Pulse-Width Modulator (PWM) operations. These registers also
store the Capture values for the CAPTURE and CAPTURE/COMPARE modes.
PS022517-0508
Timers
Z8 Encore! XP® F0822 Series
Product Specification
80
Table 43. Timer 0–1 PWM High Byte Register (TxPWMH)
BITS
7
6
5
4
3
FIELD
PWMH
RESET
0
2
1
0
R/W
R/W
F04H, F0CH
ADDR
Table 44. Timer 0–1 PWM Low Byte Register (TxPWML)
BITS
7
6
5
4
3
FIELD
PWML
RESET
0
2
1
0
R/W
R/W
F05H, F0DH
ADDR
PWMH and PWML—Pulse-Width Modulator High and Low Bytes
These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the
current 16-bit timer count. When a match occurs, the PWM output changes state. The
PWM output value is set by the TPOL bit in the Timer Control Register (TxCTL) register.
The TxPWMH and TxPWML registers also store the 16-bit captured timer value when
operating in CAPTURE or CAPTURE/COMPARE modes.
Timer 0–3 Control 0 Registers
The Timer 0–3 Control 0 (TxCTL0) registers (Table 45) allow cascading of the Timers.
Table 45. Timer 0–3 Control 0 Register (TxCTL0)
BITS
FIELD
RESET
R/W
ADDR
7
6
Reserved
5
4
3
CSC
2
1
0
Reserved
0
R/W
F06H, F0EH, F16H, F1EH
CSC—Cascade Timers
0 = Timer Input signal comes from the pin.
1 = For Timer 0, input signal is connected to Timer 1 output.
For Timer 1, input signal is connected to Timer 0 output.
PS022517-0508
Timers
Z8 Encore! XP® F0822 Series
Product Specification
81
Timer 0–1 Control 1 Registers
The Timer 0–1 Control (TxCTL) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
Table 46. Timer 0–1 Control Register (TxCTL)
BITS
FIELD
7
6
TEN
TPOL
5
4
3
2
PRES
1
0
TMODE
0
RESET
R/W
R/W
F07H, F0FH
ADDR
TEN—Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
TPOL—Timer Input/Output Polarity
Operation of this bit is a function of the current operating mode of the timer.
ONE-SHOT Mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer Reload.
CONTINUOUS Mode
When the timer is disabled, the Timer Output signal is set to the value of this bit. When the
timer is enabled, the Timer Output signal is complemented upon timer Reload.
COUNTER Mode
If the timer is enabled the Timer Output signal is complemented after timer reload.
0 = Count occurs on the rising edge of the Timer Input signal.
1 = Count occurs on the falling edge of the Timer Input signal.
PWM Mode
0 = Timer Output is forced Low (0) when the timer is disabled. When enabled,
the Timer Output is forced High (1) upon PWM count match and forced
Low (0) upon Reload.
1 = Timer Output is forced High (1) when the timer is disabled. When enabled,
the Timer Output is forced Low (0) upon PWM count match and forced
High (1) upon Reload.
CAPTURE Mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
PS022517-0508
Timers
Z8 Encore! XP® F0822 Series
Product Specification
82
COMPARE Mode
When the timer is disabled, the Timer Output signal is set to the value of this bit. When the
timer is enabled, the Timer Output signal is complemented upon timer Reload.
GATED Mode
0 = Timer counts when the Timer Input signal is High (1) and interrupts are
generated on the falling edge of the Timer Input.
1 = Timer counts when the Timer Input signal is Low (0) and interrupts are
generated on the rising edge of the Timer Input.
CAPTURE/COMPARE Mode
0 = Counting is started on the first rising edge of the Timer Input signal. The
current count is captured on subsequent rising edges of the Timer Input signal.
1 = Counting is started on the first falling edge of the Timer Input signal. The
current count is captured on subsequent falling edges of the Timer Input signal.
PRES—Prescale value
The timer input clock is divided by 2PRES, where PRES is set from 0 to 7. The prescaler is
reset each time the Timer is disabled. This insures proper clock division each time the
Timer is restarted.
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
TMODE—Timer Mode
000 = ONE-SHOT mode
001 = CONTINUOUS mode
010 = COUNTER mode
011 = PWM mode
100 = CAPTURE mode
101 = COMPARE mode
110 = GATED mode
111 = CAPTURE/COMPARE mode
PS022517-0508
Timers
Z8 Encore! XP® F0822 Series
Product Specification
83
Watchdog Timer
Watchdog Timer (WDT) protects against corrupt or unreliable software, power faults, and
other system-level problems which can place the Z8 Encore! XP® F0822 Series device
into unsuitable operating states. It includes the following features:
• On-chip RC oscillator.
• A selectable time-out response—Reset or Interrupt.
• 24-bit programmable time-out value.
Operation
WDT is a retriggerable one-shot timer that resets or interrupts the Z8 Encore! XP F0822
Series device when the WDT reaches its terminal count. It uses its own dedicated on-chip
RC oscillator as its clock source. The WDT has only two modes of operation—ON and
OFF. When enabled, it always counts and must be refreshed to prevent a time-out. An
enable is performed by executing the WDT instruction or by setting the WDT_AO Option
Bit. The WDT_AO bit enables the WDT to operate all the time, even if a WDT instruction
has not been executed.
The WDT is a 24-bit reloadable downcounter that uses three 8-bit registers in the
eZ8 CPU register space to set the reload value. The nominal WDT time-out period is
given by the following equation:
WDT Reload Value
WDT Time-out Period (ms) = --------------------------------------------------10
where the WDT reload value is the decimal value of the 24-bit value given by
{WDTU[7:0], WDTH[7:0], WDTL[7:0]} and the typical Watchdog Timer RC oscillator
frequency is 10 kHz. WDT cannot be refreshed once it reaches 000002H. The WDT
Reload Value must not be set to values below 000004H. Table 47 provides information on
approximate time-out delays for minimum and maximum WDT reload values.
Table 47. Watchdog Timer Approximate Time-Out Delays
WDT Reload
Value
(Hex)
PS022517-0508
WDT Reload
Value
Approximate Time-Out Delay
(with 10 kHz typical WDT Oscillator Frequency)
(Decimal)
Typical
Description
000004
4
400 μs
Minimum time-out delay
FFFFFF
16,777,215
1677.5 s
Maximum time-out delay
Watchdog Timer
Z8 Encore! XP® F0822 Series
Product Specification
84
Watchdog Timer Refresh
When first enabled, the WDT is loaded with the value in the WDT Reload registers. The
WDT then counts down to 000000H unless a WDT instruction is executed by the eZ8
CPU. Execution of the WDT instruction causes the downcounter to be reloaded with the
WDT Reload value stored in the WDT Reload registers. Counting resumes following the
reload operation.
When Z8 Encore! XP® F0822 Series device is operating in DEBUG Mode (using the
OCD), the WDT is continuously refreshed to prevent spurious WDT time-outs.
Watchdog Timer Time-Out Response
The WDT times out when the counter reaches 000000H. A WDT time-out generates
either an Interrupt or a Reset. The WDT_RES Option Bit determines the time-out response
of the WDT. For information regarding programming of the WDT_RES Option Bit, see
Option Bits on page 163.
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the WDT issues an interrupt
request to the interrupt controller and sets the WDT Status Bit in the WDT Control Register.
If interrupts are enabled, the eZ8 CPU responds to the interrupt request by fetching the
WDT interrupt vector and executing the code from the vector address. After time-out and
interrupt generation, the WDT counter rolls over to its maximum value of FFFFFH and
continues counting. The WDT counter is not automatically returned to its Reload Value.
WDT Reset in STOP Mode
If enabled in STOP mode and configured to generate a Reset when a time-out occurs and
the device is in STOP mode, the WDT initiates a Stop Mode Recovery. Both the WDT
status bit and the STOP bit in the WDT Control Register is set to 1 following the
WDT time-out in STOP mode. For more information, see Reset and Stop Mode Recovery
on page 39. Default operation is for the WDT and its RC oscillator to be enabled during
STOP mode.
To minimize power consumption in STOP mode, the WDT and its RC oscillator is
disabled in STOP mode. The following sequence configures the WDT to be disabled when
the Z8F082x family device enters STOP mode following execution of a STOP instruction:
1. Write 55H to the Watchdog Timer Control Register (WDTCTL).
2. Write AAH to the Watchdog Timer Control Register (WDTCTL).
3. Write 81H to the Watchdog Timer Control Register (WDTCTL) to configure the WDT
and its oscillator to be disabled during STOP mode. Alternatively, write 00H to the
WDTCTL as the third step in this sequence to reconfigure the WDT and its oscillator
to be enabled during STOP mode. This sequence only affects WDT operation in STOP
mode.
PS022517-0508
Watchdog Timer
Z8 Encore! XP® F0822 Series
Product Specification
85
WDT Reset in Normal Operation
If configured to generate a Reset when a time-out occurs, the WDT forces the device into
the Reset state. The WDT status bit in the WDT Control Register is set to 1. For more information on Reset, see Reset and Stop Mode Recovery on page 39.
WDT Reset in STOP Mode
If enabled in STOP mode and configured to generate a Reset when a time-out occurs
and the device is in STOP mode, the WDT initiates a Stop Mode Recovery. Both the
WDT status bit and the STOP bit in the WDT Control Register is set to 1 following
WDT time-out in STOP mode. For more information on Reset, see Reset and Stop Mode
Recovery on page 39. Default operation is for the WDT and its RC oscillator to be enabled
during STOP mode.
WDT RC Disable in STOP Mode
To minimize power consumption in STOP mode, the WDT and its RC oscillator can be
disabled in STOP mode. The following sequence configures the WDT to be disabled when
the Z8F082x family device enters STOP mode following execution of a STOP instruction:
1. Write 55H to the Watchdog Timer Control Register (WDTCTL).
2. Write AAH to the Watchdog Timer Control Register (WDTCTL).
3. Write 81H to the Watchdog Timer Control Register (WDTCTL) to configure the WDT
and its oscillator to be disabled during STOP mode. Alternatively, write 00H to the
Watchdog Timer Control Register (WDTCTL) as the third step in this sequence to
reconfigure the WDT and its oscillator to be enabled during STOP mode. This
sequence only affects WDT operation in STOP mode.
Watchdog Timer Reload Unlock Sequence
Writing the unlock sequence to the WDTCTL address unlocks the three Watchdog Timer
Reload Byte Registers (WDTU, WDTH, and WDTL) to allow changes to the time-out
period. These write operations to the WDTCTL address produce no effect on the bits in
the WDTCTL. The locking mechanism prevents spurious writes to the Reload Registers.
The following sequence is required to unlock the Watchdog Timer Reload Byte Registers
(WDTU, WDTH, and WDTL) for write access.
1. Write 55H to the Watchdog Timer Control Register (WDTCTL).
2. Write AAH to the Watchdog Timer Control Register (WDTCTL).
3. Write the Watchdog Timer Reload Upper Byte Register (WDTU).
4. Write the Watchdog Timer Reload High Byte Register (WDTH).
5. Write the Watchdog Timer Reload Low Byte Register (WDTL).
PS022517-0508
Watchdog Timer
Z8 Encore! XP® F0822 Series
Product Specification
86
All three Watchdog Timer Reload Registers must be written in this order. There must be
no other register writes between each of these operations. If a register write occurs, the
lock state machine resets and no further writes occur unless the sequence is restarted. The
value in the Watchdog Timer Reload Registers is loaded into the counter when the WDT is
first enabled and every time a WDT instruction is executed.
Watchdog Timer Control Register Definitions
Watchdog Timer Control Register
The Watchdog Timer Control Register (WDTCTL), detailed in Table 48, is a Read-Only
Register that indicates the source of the most recent Reset event, a Stop Mode Recovery
event, and a WDT time-out. Reading this register resets the upper four bits to 0.
Writing the 55H, AAH unlock sequence to the Watchdog Timer Control Register
(WDTCTL) address unlocks the three Watchdog Timer Reload Byte registers (WDTU,
WDTH, and WDTL) to allow changes to the time-out period. These write operations to
the WDTCTL address produce no effect on the bits in the WDTCTL. The locking
mechanism prevents spurious writes to the Reload registers.
Table 48. Watchdog Timer Control Register (WDTCTL)
BITS
FIELD
7
6
5
4
POR
STOP
WDT
EXT
RESET
3
2
1
0
Reserved
See descriptions below
0
R
R/W
FF0H
ADDR
Reset or Stop Mode Recovery Event
POR STOP WDT
EXT
Power-On Reset
1
0
0
0
Reset through RESET pin assertion
0
0
0
1
Reset through WDT time-out
0
0
1
0
Reset through the OCD (OCTCTL[1] set to 1)
1
0
0
0
Reset from STOP Mode through the DBG Pin driven Low
1
0
0
0
Stop Mode Recovery through GPIO pin transition
0
1
0
0
Stop Mode Recovery through WDT time-out
0
1
1
0
POR—Power-On Reset Indicator
If this bit is set to 1, a POR event occurred. This bit is reset to 0, if a WDT time-out or
Stop Mode Recovery occurs. This bit is also reset to 0, when the register is read.
PS022517-0508
Watchdog Timer
Z8 Encore! XP® F0822 Series
Product Specification
87
STOP—Stop Mode Recovery Indicator
If this bit is set to 1, a Stop Mode Recovery occurred. If the STOP and WDT bits are both
set to 1, the Stop Mode Recovery occurred due to a WDT time-out. If the STOP bit is 1
and the WDT bit is 0, the Stop Mode Recovery was not caused by a WDT time-out. This bit
is reset by a POR or a WDT time-out that occurred while not in STOP mode. Reading this
register also resets this bit.
WDT—Watchdog Timer Time-Out Indicator
If this bit is set to 1, a WDT time-out occurred. A POR resets this pin. A Stop Mode
Recovery due a change in an input pin also resets this bit. Reading this register resets
this bit.
EXT—External Reset Indicator
If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A POR or a
Stop Mode Recovery from a change in an input pin resets this bit. Reading this register
resets this bit.
Reserved
These bits are reserved and must be 0.
Watchdog Timer Reload Upper, High and Low Byte Registers
The Watchdog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL)
Registers (Table 49 through Table 51) form the 24-bit reload value that is loaded into the
WDT, when a WDT instruction executes. The 24-bit reload value is {WDTU[7:0],
WDTH[7:0], WDTL[7:0]}. Writing to these registers sets the required Reload Value.
Reading from these registers returns the current WDT count value.
Caution:
The 24-bit WDT Reload Value must not be set to a value less than
000004H.
Table 49. Watchdog Timer Reload Upper Byte Register (WDTU)
BITS
7
6
5
4
3
FIELD
WDTU
RESET
1
R/W
R/W*
ADDR
FF1H
2
1
0
R/W*—Read returns the current WDT count value. Write sets the desired Reload Value.
WDTU—WDT Reload Upper Byte
Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value.
PS022517-0508
Watchdog Timer
Z8 Encore! XP® F0822 Series
Product Specification
88
Table 50. Watchdog Timer Reload High Byte Register (WDTH)
BITS
7
6
5
4
3
FIELD
WDTH
RESET
1
R/W
R/W*
ADDR
FF2H
2
1
0
R/W*–Read returns the current WDT count value. Write sets the desired Reload Value.
WDTH—WDT Reload High Byte
Middle byte, Bits[15:8], of the 24-bit WDT reload value.
Table 51. Watchdog Timer Reload Low Byte Register (WDTL)
BITS
7
6
5
4
3
FIELD
WDTL
RESET
1
R/W
R/W*
ADDR
FF3H
2
1
0
R/W*–Read returns the current WDT count value. Write sets the desired Reload Value.
WDTL—WDT Reload Low
Least significant byte (LSB), Bits[7:0], of the 24-bit WDT reload value.
PS022517-0508
Watchdog Timer
Z8 Encore! XP® F0822 Series
Product Specification
89
Universal Asynchronous
Receiver/Transmitter
The Universal Asynchronous Receiver/Transmitter (UART) is a full-duplex
communication channel capable of handling asynchronous data transfers. The UART uses
a single 8-bit data mode with selectable parity. Features of the UART include:
•
•
•
•
•
•
•
•
•
•
8-bit asynchronous data transfer
Selectable even- and odd-parity generation and checking
Option of one or two STOP bits
Separate transmit and receive interrupts
Framing, parity, overrun, and break detection
Separate transmit and receive enables
16-bit Baud Rate Generator
Selectable Multiprocessor (9-bit) mode with three configurable interrupt schemes
BRG timer mode
Driver Enable output for external bus transceivers
Architecture
The UART consists of three primary functional blocks: Transmitter, Receiver, and Baud
Rate Generator. The UART’s transmitter and receiver functions independently, but use
the same baud rate and data format. Figure11 on page 90 displays the UART architecture.
PS022517-0508
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
90
Parity Checker
Receiver Control
with address compare
RXD
Receive Shifter
Receive Data
Register
Control Registers
System Bus
Transmit Data
Register
Status Register
Baud Rate
Generator
Transmit Shift
Register
TXD
Transmitter Control
Parity Generator
CTS
DE
Figure 11. UART Block Diagram
Operation
Data Format
The UART always transmits and receives data in an 8-bit data format, least-significant bit
first. An even or odd parity bit is optionally added to the data stream. Each character
begins with an active Low START bit and ends with either 1 or 2 active High STOP bits.
Figure12 on page 91 and Figure13 on page 91 display the asynchronous data format used
by the UART without parity and with parity, respectively.
PS022517-0508
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
91
Data Field
Idle State
of Line
STOP Bit(s)
lsb
msb
1
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
0
1
2
Figure 12. UART Asynchronous Data Format without Parity
STOP Bit(s)
Data Field
Idle State
of Line
lsb
msb
1
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Parity
0
1
2
Figure 13. UART Asynchronous Data Format with Parity
Transmitting Data using Polled Method
Follow the steps below to transmit data using polled method of operation:
1. Write to the UART Baud Rate High Byte and Low Byte registers to set the required
baud rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. If MULTIPROCESSOR mode is required, write to the UART Control 1 Register to
enable multiprocessor (9-bit) mode functions.
– Set the Multiprocessor Mode Select (MPEN) to enable MULTIPROCESSOR
mode.
4. Write to the UART Control 0 Register to:
– Set the transmit enable bit (TEN) to enable the UART for data transmission
– If parity is required, and MULTIPROCESSOR mode is not enabled, set the parity
enable bit (PEN) and select either even or odd parity (PSEL).
– Set or clear the CTSE bit to enable or disable control from the remote receiver
using the CTS pin.
PS022517-0508
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
92
5. Check the TDRE bit in the UART Status 0 Register to determine if the Transmit Data
Register is empty (indicated by a 1). If empty, continue to step 6. If the Transmit Data
Register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit
Data Register becomes available to receive new data.
6. Write the UART Control 1 Register to select the outgoing address bit:
– Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte,
clear it if sending a data byte.
7. Write data byte to the UART Transmit Data Register. The transmitter automatically
transfers data to the Transmit Shift Register and then transmits the data.
8. If required, and multiprocessor mode is enabled, make any changes to the
Multiprocessor Bit Transmitter (MPBT) value.
9. To transmit additional bytes, return to step 5.
Transmitting Data Using Interrupt-Driven Method
The UART Transmitter interrupt indicates the availability of the Transmit Data Register to
accept new data for transmission. Follow the below steps to configure the UART for
interrupt-driven data transmission:
1. Write to the UART Baud Rate High and Low Byte Registers to set the required
baud rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt Control Registers to enable the UART Transmitter interrupt and
set the required priority.
5. If MULTIPROCESSOR mode is required, write to the UART Control 1 Register to
enable Multiprocessor (9-bit) mode functions:
– Set the Multiprocessor Mode Select (MPEN) to enable MULTIPROCESSOR
mode.
6. Write to the UART Control 0 Register to:
– Set the transmit enable (TEN) bit to enable the UART for data transmission
– Enable parity, if required, and if MULTIPROCESSOR mode is not enabled, and
select either even or odd parity.
– Set or clear the CTSE bit to enable or disable control from the remote receiver
through the CTS pin.
7. Execute an EI instruction to enable interrupts.
PS022517-0508
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
93
The UART is now configured for interrupt-driven data transmission. Because the UART
Transmit Data Register is empty, an interrupt is generated immediately. When the UART
Transmit Interrupt is detected, the associated ISR performs the following:
1. Write the UART Control 1 Register to select the outgoing address bit:
– Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it
if sending a data byte.
2. Write the data byte to the UART Transmit Data Register. The transmitter
automatically transfers data to the Transmit Shift Register and then transmits the data.
3. Clear the UART Transmit Interrupt bit in the applicable Interrupt Request Register.
4. Execute the IRET instruction to return from the ISR and waits for the Transmit Data
Register to again become empty.
Receiving Data using the Polled Method
Follow the steps below to configure the UART for polled data reception:
1. Write to the UART Baud Rate High and Low Byte Registers to set the required
baud rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. Write to the UART Control 1 Register to enable Multiprocessor mode functions, if
desired.
4. Write to the UART Control 0 Register to:
– Set the receive enable bit (REN) to enable the UART for data reception
– Enable parity, if required, and if MULTIPROCESSOR mode is not enabled, and
select either even or odd parity.
5. Check the RDA bit in the UART Status 0 Register to determine if the Receive Data
Register contains a valid data byte (indicated by 1). If RDA is set to 1 to indicate
available data, continue to step 6. If the Receive Data Register is empty (indicated by
a 0), continue to monitor the RDA bit awaiting reception of the valid data.
6. Read data from the UART Receive Data Register. If operating in Multiprocessor
(9-bit) mode, further actions may be required depending on the Multiprocessor Mode
bits MPMD[1:0].
7. Return to step 5 to receive additional data.
PS022517-0508
Universal Asynchronous Receiver/Transmitter
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Product Specification
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Receiving Data Using Interrupt-Driven Method
The UART Receiver interrupt indicates the availability of new data (as well as error conditions). Follow the steps below to configure the UART receiver for interrupt-driven operation:
1. Write to the UART Baud Rate High and Low Byte Registers to set the required
baud rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt Control Registers to enable the UART Receiver interrupt and set
the required priority.
5. Clear the UART Receiver interrupt in the applicable Interrupt Request Register.
6. Write to the UART Control 1 Register to enable MULTIPROCESSOR (9-bit) mode
functions, if desired.
– Set the Multiprocessor Mode Select (MPEN) to enable MULTIPROCESSOR
mode.
– Set the Multiprocessor Mode Bits, MPMD[1:0], to select the required address
matching scheme.
– Configure the UART to interrupt on received data and errors or errors only
(interrupt on errors only is unlikely to be useful for Z8 Encore! XP devices
without a DMA block)
7. Write the device address to the Address Compare Register (automatic multiprocessor
modes only).
8. Write to the UART Control 0 Register to:
– Set the receive enable bit (REN) to enable the UART for data reception
– Enable parity, if required, and if MULTIPROCESSOR mode is not enabled, and
select either even or odd parity.
9. Execute an EI instruction to enable interrupts.
The UART is now configured for interrupt-driven data reception. When the UART
Receiver Interrupt is detected, the associated ISR performs the following:
1. Check the UART Status 0 Register to determine the source of the interrupt-error,
break, or received data.
2. If the interrupt was due to data available, read the data from the UART Receive Data
Register. If operating in MULTIPROCESSOR (9-bit) mode, further actions may be
required depending on the Multiprocessor Mode bits MPMD[1:0].
3. Clear the UART Receiver Interrupt in the applicable Interrupt Request Register.
4. Execute the IRET instruction to return from the ISR and await more data.
PS022517-0508
Universal Asynchronous Receiver/Transmitter
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Clear To Send Operation
The CTS pin, if enabled by the CTSE bit of the UART Control 0 register, performs
flow control on the outgoing transmit datastream. The Clear To Send (CTS) input pin is
sampled one system clock before beginning any new character transmission. To delay
transmission of the next data character, an external receiver must deassert CTS
at least one system clock cycle before a new data transmission begins. For multiple
character transmissions, this would be done during STOP bit transmission. If CTS
deasserts in the middle of a character transmission, the current character is sent
completely.
Multiprocessor (9-bit) Mode
The UART has a MULTIPROCESSOR (9-bit) mode that uses an extra (9th) bit for
selective communication when a number of processors share a common UART bus.
In MULTIPROCESSOR mode (also referred to as 9-bit mode), the multiprocessor bit is
transmitted following the 8-bits of data and immediately preceding the STOP bit(s) as displayed in Figure 14. The character format is as displayed in Figure 14.
STOP Bit(s)
Data Field
Idle State
of Line
lsb
msb
1
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
MP
0
1
2
Figure 14. UART Asynchronous MULTIPROCESSOR Mode Data Format
In MULTIPROCESSOR (9-bit) mode, the Parity bit location (9th bit) becomes the
Multiprocessor control bit. The UART Control 1 and Status 1 Registers provide
Multiprocessor (9-bit) mode control and status information. If an automatic address
matching scheme is enabled, the UART Address Compare Register holds the network
address of the device.
MULTIPROCESSOR (9-bit) Mode Receive Interrupts
When multiprocessor mode is enabled, the UART only processes frames addressed to it.
The determination of whether a frame of data is addressed to the UART can be made in
hardware, software, or combination of the two depending on the multiprocessor configuration bits. In general, the address compare feature reduces the load on the CPU, because it
does not need to access the UART when it receives data directed to other devices on the
PS022517-0508
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
96
multi-node network. The following MULTIPROCESSOR modes are available in hardware:
•
•
•
Interrupt on all address bytes.
Interrupt on matched address bytes and correctly framed data bytes.
Interrupt only on correctly framed data bytes.
These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all
MULTIPROCESSOR modes, bit MPEN of the UART Control 1 Register must be set to 1.
The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming
address bytes cause an interrupt, while data bytes never cause an interrupt. The ISR
must manually check the address byte that caused triggered the interrupt. If it
matches the UART address, the software should clear MPMD[0]. At this point, each new
incoming byte interrupts the CPU. The software is then responsible for determining the
end-of-frame. It checks for the end-of-frame by reading the MPRX bit of the UART
Status 1 Register for each incoming byte. If MPRX=1, then a new frame begins. If the
address of this new frame is different from the UART’s address, then MPMD[0] must be set
to 1 causing the UART interrupts to go inactive until the next address byte. If the new
frame’s address matches the UART’s address, then the data in the new frame should be
processed as well.
The second scheme is enabled by setting MPMD[1:0] to 10b and writing the UART’s
address into the UART Address Compare Register. This mode introduces more hardware
control, interrupting only on frames that match the UART’s address. When an incoming
address byte does not match the UART’s address, it is ignored. All successive data bytes in
this frame are also ignored. When a matching address byte occurs, an interrupt is issued
and further interrupts occur on each successive data byte. The first data byte in the frame
contains the NEWFRM=1 in the UART Status 1 Register. When the next address byte
occurs, the hardware compares it to the UART’s address. If there is a match, the interrupts
continue and the NEWFRM bit is set for the first byte of the new frame. If there is no match,
then the UART ignores all incoming bytes until the next address match.
The third scheme is enabled by setting MPMD[1:0] to 11b and by writing the UART’s
address into the UART Address Compare Register. This mode is identical to the second
scheme, except that there are no interrupts on address bytes. The first data byte of each
frame is still accompanied by a NEWFRM assertion.
External Driver Enable
The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This
feature reduces the software overhead associated with using a GPIO pin to control the
transceiver when communicating on a multi-transceiver bus, such as RS-485.
Driver Enable is an active High signal that envelopes the entire transmitted data frame
including parity and STOP bits as displayed in Figure15 on page 97. The Driver Enable
signal asserts when a byte is written to the UART Transmit Data Register. The Driver
PS022517-0508
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
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Enable signal asserts at least one UART bit period and no greater than two UART bit periods before the Start bit is transmitted. This format allows a setup time to enable the transceiver. The Driver Enable signal deasserts one system clock period after the last STOP bit
is transmitted. This one system clock delay allows both time for data to clear the transceiver before disabling it, as well as the ability to determine if another character follows
the current character. In the event of back to back characters (new data must be written to
the Transmit Data Register before the previous character is completely transmitted) the
DE signal is not deasserted between characters. The DEPOL bit in the UART Control
Register 1 sets the polarity of the Driver Enable signal.
1
DE
0
Data Field
Idle State
of Line
STOP Bit
lsb
msb
1
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Parity
0
1
Figure 15. UART Driver Enable Signal Timing (with 1 STOP Bit and Parity)
The Driver Enable to Start bit setup time is calculated as follows:
1
⎛ ----------------------------------------⎞
⎝ Baud Rate (Hz) ⎠
2
-⎞
≤ DE to Start Bit Setup Time (s) ≤ ⎛⎝ ---------------------------------------⎠
Baud Rate (Hz)
UART Interrupts
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the BRG also functions as a basic timer
with interrupt capability.
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for
transmission. The TDRE interrupt occurs after the Transmit shift register has shifted the
first bit of data out. At this point, the Transmit Data Register can be written with the next
character to send. This provides 7 bit periods of latency to load the Transmit Data Register
before the Transmit shift register completes shifting the current character. Writing to the
UART Transmit Data Register clears the TDRE bit to 0.
PS022517-0508
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
98
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
•
A data byte is received and is available in the UART Receive Data Register. This
interrupt can be disabled independent of the other receiver interrupt sources. The
received data interrupt occurs once the receive character is received and placed in the
Receive Data Register. Software must respond to this received data available
condition before the next character is completely received to avoid an overrun error. In
MULTIPROCESSOR mode (MPEN = 1), the receive data interrupts are dependent on
the multiprocessor configuration and the most recent address byte
•
•
•
A break is received
An overrun is detected
A data framing error is detected
UART Overrun Errors
When an overrun error condition occurs the UART prevents overwriting of the valid data
currently in the Receive Data Register. The break detect and overrun status bits are not
displayed until the valid data is read.
After the valid data has been read, the UART Status 0 Register is updated to indicate the
overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that
the Receive Data Register contains a data byte. However, because the overrun error
occurred, this byte cannot contain valid data and should be ignored. The BRKD bit indicates if the overrun was caused by a break condition on the line. After reading the status
byte indicating an overrun error, the Receive Data Register must be read again to clear the
error bits is the UART Status 0 Register. Updates to the Receive Data Register occur only
when the next data word is received.
UART Data and Error Handling Procedure
Figure16 on page 99 displays the recommended procedure for UART receiver ISRs.
Baud Rate Generator Interrupts
If the BRG interrupt enable is set, the UART Receiver interrupt asserts when the UART
Baud Rate Generator reloads. This action allows the BRG to function as an additional
counter if the UART functionality is not employed.
PS022517-0508
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
99
Receiver
Ready
Receiver
Interrupt
Read Status
No
Errors?
Yes
Read Data which
clears RDA bit and
resets error bits
Read Data
Discard Data
Figure 16. UART Receiver Interrupt Service Routine Flow
UART Baud Rate Generator
The UART Baud Rate Generator creates a lower frequency baud rate clock for data
transmission. The input to the BRG is the system clock. The UART Baud Rate High and
Low Byte Registers combine to create a 16-bit baud rate divisor value (BRG[15:0]) that
sets the data transmission rate (baud rate) of the UART. The UART data rate is calculated
using the following equation:
System Clock Frequency (Hz)
UART Data Rate (bits/s) = --------------------------------------------------------------------------------------------16xUART Baud Rate Divisor Value
PS022517-0508
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
100
When the UART is disabled, the BRG functions as a basic 16-bit timer with interrupt on
time-out. Follow the steps below to configure the BRG as a timer with interrupt on timeout:
1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 Register
to 0.
2. Load the desired 16-bit count value into the UART Baud Rate High and Low Byte
Registers.
3. Enable the BRG timer function and associated interrupt by setting the BKGCTL bit in
the UART Control 1 Register to 1.
When configured as a general-purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval (s) = System Clock Period (s) ×BRG[15:0] ]
UART Control Register Definitions
The UART Control Registers support the UART and the associated Infrared Encoder/
Decoders. See Infrared Encoder/Decoder on page 109 for more information on the infrared operation.
UART Transmit Data Register
Data bytes written to the UART Transmit Data Register (Table 52) are shifted out on the
TXDx pin. The Write-only UART Transmit Data Register shares a Register File address
with the Read-only UART Receive Data Register.
Table 52. UART Transmit Data Register (U0TXD)
BITS
7
6
5
4
3
2
1
0
TXD
FIELD
RESET
X
X
X
X
X
X
X
X
R/W
W
W
W
W
W
W
W
W
ADDR
F40H
TXD—Transmit Data
UART transmitter data byte to be shifted out through the TXDx pin.
PS022517-0508
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
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UART Receive Data Register
Data bytes received through the RXDx pin are stored in the UART Receive Data Register
(Table 53). The Read-only UART Receive Data Register shares a Register File address
with the Write-only UART Transmit Data Register.
Table 53. UART Receive Data Register (U0RXD)
BITS
7
6
5
4
3
FIELD
RXD
RESET
X
R/W
R
2
1
0
F40H
ADDR
RXD—Receive Data
UART receiver data byte from the RXDx pin
UART Status 0 Register
The UART Status 0 and Status 1 registers (Table 54 and Table 55 on page 102) identify
the current UART operating configuration and status.
Table 54. UART Status 0 Register (U0STAT0)
7
6
5
4
3
2
1
0
RDA
PE
OE
FE
BRKD
TDRE
TXE
CTS
BITS
FIELD
RESET
R/W
ADDR
0
1
X
R
F41H
RDA—Receive Data Available
This bit indicates that the UART Receive Data Register has received data. Reading the
UART Receive Data Register clears this bit.
0 = The UART Receive Data Register is empty.
1 = There is a byte in the UART Receive Data Register.
PE—Parity Error
This bit indicates that a parity error has occurred. Reading the UART Receive Data Register clears this bit.
0 = No parity error has occurred.
1 = A parity error has occurred.
OE—Overrun Error
This bit indicates that an overrun error has occurred. An overrun occurs when new data is
received and the UART Receive Data Register has not been read. If the RDA bit is reset to
PS022517-0508
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
102
0, then reading the UART Receive Data Register clears this bit.
0 = No overrun error occurred.
1 = An overrun error occurred.
FE—Framing Error
This bit indicates that a framing error (no STOP bit following data reception) was
detected. Reading the UART Receive Data Register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
BRKD—Break Detect
This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and
STOP bit(s) are all zeros then this bit is set to 1. Reading the UART Receive Data Register
clears this bit.
0 = No break occurred.
1 = A break occurred.
TDRE—Transmitter Data Register Empty
This bit indicates that the UART Transmit Data Register is empty and ready for additional
data. Writing to the UART Transmit Data Register resets this bit.
0 = Do not write to the UART Transmit Data Register.
1 = The UART Transmit Data Register is ready to receive an additional byte to be
transmitted.
TXE—Transmitter Empty
This bit indicates that the transmit shift register is empty and character transmission
is finished.
0 = Data is currently transmitting.
1 = Transmission is complete.
CTS—CTS Signal
When this bit is read it returns the level of the CTS signal.
UART Status 1 Register
This register contains multiprocessor control and status bits.
Table 55. UART Status 1 Register (U0STAT1)
BITS
7
6
5
PS022517-0508
2
1
0
NEWFRM
MPRX
0
RESET
ADDR
3
Reserved
FIELD
R/W
4
R
R/W
R
F44H
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
103
Reserved—Must be 0
NEWFRM—Status bit denoting the start of a new frame. Reading the UART Receive
Data Register resets this bit to 0.
0 = The current byte is not the first data byte of a new frame.
1 = The current byte is the first data byte of a new frame.
MPRX—Multiprocessor Receive
Returns the value of the last multiprocessor bit received. Reading from the UART Receive
Data Register resets this bit to 0.
UART Control 0 and Control 1 Registers
The UART Control 0 and Control 1 registers (Table 56 and Table 57 on page 104) configure the properties of the UART’s transmit and receive operations. The UART Control
Registers must not been written while the UART is enabled.
Table 56. UART Control 0 Register (U0CTL0)
BITS
FIELD
7
6
5
4
3
2
1
0
TEN
REN
CTSE
PEN
PSEL
SBRK
STOP
LBEN
0
RESET
R/W
R/W
ADDR
F42H
TEN—Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is
enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
REN—Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
CTSE—CTS Enable
0 = The CTS signal has no effect on the transmitter.
1 = The UART recognizes the CTS signal as an enable control from the transmitter.
PEN—Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit. This bit is
overridden by the MPEN bit.
0 = Parity is disabled.
1 = The transmitter sends data with an additional parity bit and the receiver
receives an additional parity bit.
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Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
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PSEL—Parity Select
0 = Even parity is transmitted and expected on all received data.
1 = Odd parity is transmitted and expected on all received data.
SBRK—Send Break
This bit pauses or breaks data transmission by forcing the Transmit data output to 0.
Sending a break interrupts any transmission in progress, so ensure that the transmitter has
finished sending data before setting this bit. The UART does not automatically generate a
STOP Bit when SBRK is deasserted. Software must time the duration of the Break and the
duration of any STOP Bit time desired following the Break.
0 = No break is sent.
1 = The output of the transmitter is zero.
STOP—STOP Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
LBEN—Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver.
Table 57. UART Control 1 Register (U0CTL1)
BITS
FIELD
7
6
5
4
3
2
1
0
MPMD[1]
MPEN
MPMD[0]
MPBT
DEPOL
BRGCTL
RDAIRQ
IREN
RESET
0
R/W
R/W
ADDR
F43H
MPMD[1:0]—Multiprocessor Mode
If Multiprocessor (9-bit) mode is enabled,
00 = The UART generates an interrupt request on all received bytes (data and address).
01 = The UART generates an interrupt request only on received address bytes.
10 = The UART generates an interrupt request when a received address byte matches
the value stored in the Address Compare Register and on all successive data
bytes until an address mismatch occurs.
11 = The UART generates an interrupt request on all received data bytes for which
the most recent address byte matched the value in the Address Compare Register.
MPEN—Multiprocessor (9-bit) Enable
This bit is used to enable Multiprocessor (9-bit) mode.
0 = Disable Multiprocessor (9-bit) mode.
1 = Enable Multiprocessor (9-bit) mode.
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Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
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MPBT—Multiprocessor Bit Transmit
This bit is applicable only when Multiprocessor (9-bit) mode is enabled.
0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit).
1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit).
DEPOL—Driver Enable Polarity
0 = DE signal is Active High.
1 = DE signal is Active Low.
BRGCTL—Baud Rate Control
This bit causes different UART behavior depending on whether the UART receiver is
enabled (REN = 1 in the UART Control 0 Register).
When the UART receiver is not enabled, this bit determines whether the BRG will issue
interrupts.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value
1 = The BRG generates a receive interrupt when it counts down to
zero. Reads from the Baud Rate High and Low Byte registers return the current
BRG count value.
When the UART receiver is enabled, this bit allows reads from the Baud Rate Registers to
return the BRG count value instead of the Reload Value.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value.
1 = Reads from the Baud Rate High and Low Byte registers return the current BRG
count value. Unlike the Timers, there is no mechanism to latch the High Byte
when the Low Byte is read.
RDAIRQ—Receive Data Interrupt Enable
0 = Received data and receiver errors generates an interrupt request to the
Interrupt Controller.
1 = Received data does not generate an interrupt request to the Interrupt Controller.
Only receiver errors generate an interrupt request.
IREN—Infrared Encoder/Decoder Enable
0 = Infrared Encoder/Decoder is disabled. UART operates normally operation.
1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data
through the Infrared Encoder/Decoder.
UART Address Compare Register
The UART Address Compare register stores the multi-node network address of the UART.
When the MPMD[1] bit of UART Control Register 0 is set, all incoming address bytes
will be compared to the value stored in the Address Compare register. Receive
interrupts and RDA assertions will only occur in the event of a match.
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Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
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Table 58. UART Address Compare Register (U0ADDR)
BITS
7
6
5
4
3
FIELD
COMP_ADDR
RESET
0
R/W
R/W
ADDR
F45H
2
1
0
COMP_ADDR—Compare Address
This 8-bit value is compared to the incoming address bytes.
UART Baud Rate High and Low Byte Registers
The UART Baud Rate High and Low Byte registers (Table 59 and Table 60) combine to
create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate
(baud rate) of the UART.
Table 59. UART Baud Rate High Byte Register (U0BRH)
BITS
7
6
5
4
3
FIELD
BRH
RESET
1
R/W
R/W
ADDR
F46H
2
1
0
2
1
0
Table 60. UART Baud Rate Low Byte Register (U0BRL)
BITS
7
6
5
4
3
FIELD
BRL
RESET
1
R/W
R/W
ADDR
F47H
The UART data rate is calculated using the following equation:
System Clock Frequency (Hz)
UART Baud Rate (bits/s) = ----------------------------------------------------------------------------------------------16 xUART Baud Rate Divisor Value
PS022517-0508
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
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For a given UART data rate, the integer baud rate divisor value is calculated using the
following equation:
System Clock Frequency (Hz)
UART Baud Rate Divisor Value (BRG) = Round ⎛ -------------------------------------------------------------------------------⎞
⎝ 16xUART Data Rate (bits/s) ⎠
The baud rate error relative to the desired baud rate is calculated using the following
equation:
UART Baud Rate Error (%)
Actual Data Rate – Desired Data Rate⎞
= 100x ⎛⎝ --------------------------------------------------------------------------------------------------⎠
Desired Data Rate
For reliable communication, the UART baud rate error must never exceed 5 percent.
Table 61 provides information on data rate errors for popular baud rates and commonly
used crystal oscillator frequencies.
Table 61. UART Baud Rates
10.0 MHz System Clock
5.5296 MHz System Clock
Desired
Rate
BRG
Divisor
Actual Rate Error
Desired
Rate
BRG
Divisor
Actual Rate Error
(kHz)
(Decimal)
(kHz)
(kHz)
(Decimal)
(kHz)
(%)
(%)
1250.0
N/A
N/A
N/A
1250.0
N/A
N/A
N/A
625.0
1
625.0
0.00
625.0
N/A
N/A
N/A
250.0
3
208.33
-16.67
250.0
1
345.6
38.24
115.2
5
125.0
8.51
115.2
3
115.2
0.00
57.6
11
56.8
-1.36
57.6
6
57.6
0.00
38.4
16
39.1
1.73
38.4
9
38.4
0.00
19.2
33
18.9
0.16
19.2
18
19.2
0.00
9.60
65
9.62
0.16
9.60
36
9.60
0.00
4.80
130
4.81
0.16
4.80
72
4.80
0.00
2.40
260
2.40
-0.03
2.40
144
2.40
0.00
1.20
521
1.20
-0.03
1.20
288
1.20
0.00
0.60
1042
0.60
-0.03
0.60
576
0.60
0.00
0.30
2083
0.30
0.2
0.30
1152
0.30
0.00
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Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
108
Table 61. UART Baud Rates (Continued)
3.579545 MHz System Clock
1.8432 MHz System Clock
Desired
Rate
BRG
Divisor
Actual Rate Error
Desired
Rate
BRG
Divisor
Actual Rate Error
(kHz)
(Decimal)
(kHz)
(kHz)
(Decimal)
(kHz)
(%)
(%)
1250.0
N/A
N/A
N/A
1250.0
N/A
N/A
N/A
625.0
N/A
N/A
N/A
625.0
N/A
N/A
N/A
250.0
1
223.72
-10.51
250.0
N/A
N/A
N/A
115.2
2
111.9
-2.90
115.2
1
115.2
0.00
57.6
4
55.9
-2.90
57.6
2
57.6
0.00
38.4
6
37.3
-2.90
38.4
3
38.4
0.00
19.2
12
18.6
-2.90
19.2
6
19.2
0.00
9.60
23
9.73
1.32
9.60
12
9.60
0.00
4.80
47
4.76
-0.83
4.80
24
4.80
0.00
2.40
93
2.41
0.23
2.40
48
2.40
0.00
1.20
186
1.20
0.23
1.20
96
1.20
0.00
0.60
373
0.60
-0.04
0.60
192
0.60
0.00
0.30
746
0.30
-0.04
0.30
384
0.30
0.00
PS022517-0508
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0822 Series
Product Specification
109
Infrared Encoder/Decoder
Z8 Encore! XP® F0822 Series products contain a fully-functional, high-performance
UART to Infrared Encoder/Decoder (Endec). The Infrared Endec is integrated with an onchip UART to allow easy communication between the Z8 Encore! XP and IrDA Physical
Layer Specification, v1.3-compliant infrared transceivers. Infrared communication provides secure, reliable, low-cost, point-to-point communication between PCs, PDAs, cell
phones, printers, and other infrared enabled devices.
Architecture
Figure 17 displays the architecture of the Infrared Endec.
System
Clock
Zilog
ZHX1810
RxD
RXD
RXD
TxD
UART
Baud Rate
Clock
Interrupt
I/O
Signal Address
Infrared
Encoder/Decoder
(Endec)
TXD
TXD
Infrared
Transceiver
Data
Figure 17. Infrared Data Communication System Block Diagram
Operation
When the Infrared Endec is enabled, the transmit data from the associated on-chip UART
is encoded as digital signals in accordance with the IrDA standard and output to the
infrared transceiver through the TXD pin. Similarly, data received from the infrared
transceiver is passed to the Infrared Endec through the RXD pin, decoded by the Infrared
Endec, and then passed to the UART. Communication is half-duplex, which means
simultaneous data transmission and reception is not allowed.
PS022517-0508
Infrared Encoder/Decoder
Z8 Encore! XP® F0822 Series
Product Specification
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The baud rate is set by the UART’s Baud Rate Generator and supports IrDA standard baud
rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet
IrDA specifications. The UART must be enabled to use the Infrared Endec. The Infrared
Endec data rate is calculated using the following equation.
System Clock Frequency (Hz)
Infrared Data Rate (bits/s) = --------------------------------------------------------------------------------------------16xUART Baud Rate Divisor Value
Transmitting IrDA Data
The data to be transmitted using the infrared transceiver is first sent to the UART. The
UART’s transmit signal (TXD) and baud rate clock are used by the IrDA to generate the
modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared
data bit is 16-clocks wide. If the data to be transmitted is 1, the IR_TXD signal remains
low for the full 16-clock period. If the data to be transmitted is 0, a 3-clock high pulse is
output following a 7-clock low period. After the 3-clock high pulse, a 6-clock low pulse is
output to complete the full 16-clock data period. Figure 18 displays IrDA data transmission. When the Infrared Endec is enabled, the UART’s TXD signal is internal to the Z8
Encore! XP® F0822 Series products while the IR_TXD signal is output through the TXD
pin.
16-clock
period
Baud Rate
Clock
UART’s
TXD
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
3-clock
pulse
IR_TXD
7-clock
delay
Figure 18. Infrared Data Transmission
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Infrared Encoder/Decoder
Z8 Encore! XP® F0822 Series
Product Specification
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Receiving IrDA Data
Data received from the infrared transceiver through the IR_RXD signal through the RXD
pin is decoded by the Infrared Endec and passed to the UART. The UART’s baud rate
clock is used by the Infrared Endec to generate the demodulated signal (RXD) that drives
the UART. Each UART/Infrared data bit is 16-clocks wide. Figure 19 displays data reception. When the Infrared Endec is enabled, the UART’s RXD signal is internal to the Z8
Encore! XP® F0822 Series products while the IR_RXD signal is received through the
RXD pin.
16-clock
period
Baud Rate
Clock
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_RXD
min. 1.6μs
pulse
UART’s
RXD
Start Bit = 0
8-clock
delay
16-clock
period
Data Bit 0 = 1
16-clock
period
Data Bit 1 = 0
16-clock
period
Data Bit 2 = 1
Data Bit 3 = 1
16-clock
period
Figure 19. Infrared Data Reception
Caution:
The system clock frequency must be at least 1.0 MHz to ensure proper reception of the
1.6 μs minimum width pulses allowed by the IrDA standard.
Endec Receiver Synchronization
The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate
an input stream for the UART and to create a sampling window for detection of incoming
pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods
with respect to the incoming IrDA data stream. When a falling edge in the input data
stream is detected, the Endec counter is reset. When the count reaches a value of 8, the
UART RXD value is updated to reflect the value of the decoded data. When the count
reaches 12 baud clock periods, the sampling window for the next incoming pulse opens.
The window remains open until the count again reaches 8 (or in other words 24 baud clock
periods since the previous pulse was detected). This gives the Endec a sampling window
PS022517-0508
Infrared Encoder/Decoder
Z8 Encore! XP® F0822 Series
Product Specification
112
of minus four baud rate clocks to plus eight baud rate clocks around the expected time of
an incoming pulse. If an incoming pulse is detected inside this window this process is
repeated. If the incoming data is a logical 1 (no pulse), the Endec returns to the initial state
and waits for the next falling edge. As each falling edge is detected, the Endec clock
counter is reset, resynchronizing the Endec to the incoming signal. This procedure allows
the Endec to tolerate jitter and baud rate errors in the incoming data stream. Resynchronizing the Endec does not alter the operation of the UART, which ultimately receives the
data. The UART is only synchronized to the incoming data stream when a Start bit is
received.
Infrared Endec Control Register Definitions
All Infrared Endec configuration and status information is set by the UART control
registers as defined in UART Control Register Definitions on page 100.
Caution: To prevent spurious signals during IrDA data transmission, set the IREN bit in the
UART Control 1 register to 1 to enable the Infrared Endec before enabling the GPIO
Port alternate function for the corresponding pin.
PS022517-0508
Infrared Encoder/Decoder
Z8 Encore! XP® F0822 Series
Product Specification
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Serial Peripheral Interface
The Serial Peripheral Interface (SPI) is a synchronous interface allowing several SPI-type
devices to be interconnected. SPI-compatible devices include EEPROMs, Analog-toDigital Converters, and ISDN devices. Features of the SPI include:
•
•
•
•
•
Full-duplex, synchronous, and character-oriented communication
Four-wire interface
Data transfers rates up to a maximum of one-half the system clock frequency
Error detection
Dedicated Baud Rate Generator
The SPI is not available in 20-pin package devices.
Architecture
The SPI is be configured as either a Master (in single or multi-master systems) or a Slave
as displayed in Figure 20 through Figure 22.
SPI Master
To Slave’s SS Pin
From Slave
To Slave
To Slave
SS
MISO
8-bit Shift Register
Bit 0
Bit 7
MOSI
SCK
Baud Rate
Generator
Figure 20. SPI Configured as a Master in a Single Master, Single Slave System
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Serial Peripheral Interface
Z8 Encore! XP® F0822 Series
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VCC
SPI Master
SS
To Slave #2’s SS Pin
GPIO
To Slave #1’s SS Pin
GPIO
8-bit Shift Register
From Slave
Bit 0
MISO
Bit 7
MOSI
To Slave
Baud Rate
Generator
SCK
To Slave
Figure 21. SPI Configured as a Master in a Single Master, Multiple Slave System
SPI Slave
From Master
To Master
From Master
From Master
SS
MISO
8-bit Shift Register
Bit 7
Bit 0
MOSI
SCK
Figure 22. SPI Configured as a Slave
Operation
The SPI is a full-duplex, synchronous, and character-oriented channel that supports a fourwire interface (serial clock, transmit, receive and Slave select). The SPI block consists of a
transmit/receive shift register, a Baud Rate (clock) Generator and a control unit.
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Serial Peripheral Interface
Z8 Encore! XP® F0822 Series
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During an SPI transfer, data is sent and received simultaneously by both the Master and
the Slave SPI devices. Separate signals are required for data and the serial clock. When an
SPI transfer occurs, a multi-bit (typically 8-bit) character is shifted out one data pin and an
multi-bit character is simultaneously shifted in on a second data pin. An 8-bit shift register
in the Master and another 8-bit shift register in the Slave are connected as a circular buffer.
The SPI shift register is single-buffered in the transmit and receive directions. New data to
be transmitted cannot be written into the shift register until the previous transmission is
complete and receive data (if valid) has been read.
SPI Signals
The four basic SPI signals are:
•
•
•
•
MISO (Master-In, Slave-Out)
MOSI (Master-Out, Slave-In)
SCK (Serial Clock)
SS (Slave Select)
The following sections discuss these SPI signals. Each signal is described in both
Master and Slave modes.
Master-In/Slave-Out
The Master-In/Slave-Out (MISO) pin is configured as an input in a Master device and as
an output in a Slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. The MISO pin of a Slave device is placed in a high-impedance
state if the Slave is not selected. When the SPI is not enabled, this signal is in a highimpedance state.
Master-Out/Slave-In
The Master-Out/Slave-In (MOSI) pin is configured as an output in a Master device and as
an input in a Slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance
state.
Serial Clock
The Serial Clock (SCK) synchronizes data movement both in and out of the device
through its MOSI and MISO pins. In MASTER mode, the SPI’s Baud Rate Generator
creates the serial clock. The Master drives the serial clock out its own SCK pin to the
Slave’s SCK pin. When the SPI is configured as a Slave, the SCK pin is an input and the
clock signal from the Master synchronizes the data transfer between the Master and Slave
devices. Slave devices ignore the SCK signal, unless the SS pin is asserted. When configured as a slave, the SPI block requires a minimum SCK period of greater than or equal to 8
times the system (XIN) clock period.
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Serial Peripheral Interface
Z8 Encore! XP® F0822 Series
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The Master and Slave are each capable of exchanging a character of data during a
sequence of NUMBITS clock cycles (see NUMBITS field in the SPIMODE Register). In
both Master and Slave SPI devices, data is shifted on one edge of the SCK and is sampled
on the opposite edge where data is stable. Edge polarity is determined by the SPI phase
and polarity control.
Slave Select
The active Low Slave Select (SS) input signal selects a Slave SPI device. SS must be Low
prior to all data communication to and from the Slave device. SS must stay Low for the
full duration of each character transferred. The SS signal can stay Low during the transfer
of multiple characters or can deassert between each character.
When the SPI is configured as the only Master in an SPI system, the SS pin is set as either
an input or an output. For communication between the Z8 Encore! XP F0822 Series
device’s SPI Master and external Slave devices, the SS signal, as an output, asserts the SS
input pin on one of the Slave devices. Other GPIO output pins can also be employed to
select external SPI Slave devices.
When the SPI is configured as one Master in a multi-master SPI system, the SS pin should
be set as an input. The SS input signal on the Master must be High. If the SS signal goes
Low (indicating another Master is driving the SPI bus), a Collision error flag is set in the
SPI Status Register.
SPI Clock Phase and Polarity Control
The SPI supports four combinations of serial clock phase and polarity using two bits in the
SPI Control Register. The clock polarity bit, CLKPOL, selects an active high or active low
clock and has no effect on the transfer format. Table 62 lists the SPI Clock Phase and
Polarity Operation parameters. The clock phase bit, PHASE, selects one of two fundamentally different transfer formats. For proper data transmission, the clock phase and polarity
must be identical for the SPI Master and the SPI Slave. The Master always places data on
the MOSI line a half-cycle before the receive clock edge (SCK signal), in order for the
Slave to latch the data.
Table 62. SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation
PHASE
PS022517-0508
CLKPOL
SCK Transmit
Edge
SCK Receive
Edge
SCK Idle
State
0
0
Falling
Rising
Low
0
1
Rising
Falling
High
1
0
Rising
Falling
Low
1
1
Falling
Rising
High
Serial Peripheral Interface
Z8 Encore! XP® F0822 Series
Product Specification
117
Transfer Format PHASE is 0
Figure 23 displays the timing diagram for an SPI transfer in which PHASE is cleared
to 0. The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL
set to one. The diagram can be interpreted as either a Master or Slave timing diagram since
the SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly
connected between the Master and the Slave.
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MISO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Input Sample Time
SS
Figure 23. SPI Timing When PHASE is 0
Transfer Format PHASE is 1
Figure 24 displays the timing diagram for an SPI transfer in which PHASE is one. Two
waveforms are depicted for SCK, one for CLKPOL reset to 0 and another for CLKPOL
set to 1.
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Serial Peripheral Interface
Z8 Encore! XP® F0822 Series
Product Specification
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SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MISO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Input Sample Time
SS
Figure 24. SPI Timing When PHASE is 1
Multi-Master Operation
In a multi-master SPI system, all SCK pins are tied together, all MOSI pins are tied
together and all MISO pins are tied together. All SPI pins must then be configured in
OPEN-DRAIN mode to prevent bus contention. At any one time, only one SPI device is
configured as the Master and all other SPI devices on the bus are configured as Slaves.
The Master enables a single Slave by asserting the SS pin on that Slave only. Then, the
single Master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the
Slaves (including those which are not enabled). The enabled Slave drives data out its
MISO pin to the MISO Master pin.
For a Master device operating in a multi-master system, if the SS pin is configured as
an input and is driven Low by another Master, the COL bit is set to 1 in the SPI Status
Register. The COL bit indicates the occurrence of a multi-master collision (mode fault
error condition).
Slave Operation
The SPI block is configured for SLAVE mode operation by setting the SPIEN bit to 1 and
the MMEN bit to 0 in the SPICTL Register and setting the SSIO bit to 0 in the SPIMODE
Register. The IRQE, PHASE, CLKPOL, and WOR bits in the SPICTL Register and the
PS022517-0508
Serial Peripheral Interface
Z8 Encore! XP® F0822 Series
Product Specification
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NUMBITS field in the SPIMODE Register must be set to be consistent with the other
SPI devices. The STR bit in the SPICTL Register can be used if desired to force a
“startup” interrupt. The BIRQ bit in the SPICTL Register and the SSV bit in the
SPIMODE Register is not used in SLAVE mode. The SPI Baud Rate Generator is not used
in SLAVE mode so the SPIBRH and SPIBRL Registers need not be initialized.
If the slave has data to send to the master, the data must be written to the SPIDAT
Register before the transaction starts (first edge of SCK when SS is asserted). If the
SPIDAT Register is not written prior to the slave transaction, the MISO pin outputs
whatever value is currently in the SPIDAT Register.
Due to the delay resulting from synchronization of the SPI input signals to the internal
system clock, the maximum SPICLK baud rate that can be supported in SLAVE mode is
the system clock frequency (XIN) divided by 8. This rate is controlled by the SPI Master.
Error Detection
The SPI contains error detection logic to support SPI communication protocols and recognize when communication errors have occurred. The SPI Status Register indicates when a
data transmission error has been detected.
Overrun (Write Collision)
An overrun error (write collision) indicates a write to the SPI Data Register was attempted
while a data transfer is in progress (in either Master or Slave modes). An overrun sets the
OVR bit in the SPI Status Register to 1. Writing a 1 to OVR clears this error flag. The data
register is not altered when a write occurs while data transfer is in progress.
Mode Fault (Multi-Master Collision)
A mode fault indicates when more than one Master is trying to communicate at the same
time (a multi-master collision). The mode fault is detected when the enabled Master’s SS
pin is asserted. A mode fault sets the COL bit in the SPI Status Register to 1. Writing a 1 to
COL clears this error Flag.
SLAVE Mode Abort
In SLAVE mode, if the SS pin deasserts before all bits in a character have been
transferred, the transaction aborts. When this condition occurs the ABT bit is set in the
SPISTAT Register as well as the IRQ bit (indicating the transaction is complete). The next
time SS asserts, the MISO pin outputs SPIDAT[7], regardless of where the previous
transaction left off. Writing a 1 to ABT clears this error flag.
SPI Interrupts
When SPI interrupts are enabled, the SPI generates an interrupt after character transmission/reception completes in both Master and Slave modes. A character is defined to be 1
through 8 bits by the NUMBITS field in the SPI Mode Register. In SLAVE mode it is not
PS022517-0508
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Z8 Encore! XP® F0822 Series
Product Specification
120
necessary for SS to deassert between characters to generate the interrupt. The SPI in
SLAVE mode also generates an interrupt if the SS signal deasserts prior to transfer of all
the bits in a character (see description of Slave Abort Error). Writing a 1 to the IRQ bit in
the SPI Status Register clears the pending SPI interrupt request. The IRQ bit must be
cleared to 0 by the ISR to generate future interrupts. To start the transfer process, an SPI
interrupt can be forced by software writing a 1 to the STR bit in the SPICTL Register.
If the SPI is disabled, an SPI interrupt can be generated by a BRG time-out. This timer
function must be enabled by setting the BIRQ bit in the SPICTL Register. This BRG
time-out does not set the IRQ bit in the SPISTAT Register, just the SPI interrupt bit in the
interrupt controller.
SPI Baud Rate Generator
In SPI MASTER mode, the BRG creates a lower frequency serial clock (SCK) for data
transmission synchronization between the Master and the external Slave. The input to the
BRG is the system clock. The SPI Baud Rate High and Low Byte Registers combine to
form a 16-bit reload value, BRG[15:0], for the SPI Baud Rate Generator. The SPI baud
rate is calculated using the following equation:
System Clock Frequency (Hz)
SPI Baud Rate (bits/s) = ------------------------------------------------------------------------------2xBRG[15:0]
Minimum baud rate is obtained by setting BRG[15:0] to 0000H for a clock divisor value
of (2 X 65536 = 131072).
When the SPI is disabled, BRG functions as a basic 16-bit timer with interrupt on
time-out. Follow the steps below to configure BRG as a timer with interrupt on time-out:
1. Disable the SPI by clearing the SPIEN bit in the SPI Control Register to 0.
2. Load the desired 16-bit count value into the SPI Baud Rate High and Low Byte
registers.
3. Enable BRG timer function and associated interrupt by setting the BIRQ bit in the SPI
Control Register to 1.
When configured as a general-purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval (s) = System Clock Period (s) ×BRG[15:0] ]
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SPI Control Register Definitions
SPI Data Register
The SPI Data Register stores both the outgoing (transmit) data and the incoming (receive)
data. Reads from the SPI Data Register always return the current contents of the 8-bit
Shift Register. Data is shifted out starting with bit 7. The last bit received resides in bit
position 0.
With the SPI configured as a Master, writing a data byte to this register initiates the data
transmission. With the SPI configured as a Slave, writing a data byte to this register loads
the shift register in preparation for the next data transfer with the external Master. In either
the Master or Slave modes, if a transmission is already in progress, writes to this register
are ignored and the Overrun error Flag, OVR, is set in the SPI Status Register.
When the character length is less than 8 bits (as set by the NUMBITS field in the SPI Mode
Register), the transmit character must be left justified in the SPI Data Register. A received
character of less than 8 bits is right justified (last bit received is in bit position 0). For
example, if the SPI is configured for 4-bit characters, the transmit characters must be
written to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0].
Table 63. SPI Data Register (SPIDATA)
BITS
7
6
5
4
3
FIELD
DATA
RESET
X
R/W
R/W
ADDR
F60H
2
1
0
DATA—Data
Transmit and/or receive data.
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SPI Control Register
The SPI Control Register configures the SPI for transmit and receive operations.
Table 64. SPI Control Register (SPICTL)
BITS
FIELD
7
6
5
4
3
2
1
0
IRQE
STR
BIRQ
PHASE
CLKPOL
WOR
MMEN
SPIEN
0
RESET
R/W
R/W
ADDR
F61H
IRQE—Interrupt Request Enable
0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller.
1 = SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller.
STR—Start an SPI Interrupt Request
0 = No effect.
1 = Setting this bit to 1 also sets the IRQ bit in the SPI Status Register to 1. Setting this
bit forces the SPI to send an interrupt request to the Interrupt Control. This bit can
be used by software for a function similar to transmit buffer empty in a UART.
Writing a 1 to the IRQ bit in the SPI Status Register clears this bit to 0.
BIRQ—BRG Timer Interrupt Request
If the SPI is enabled, this bit has no effect. If the SPI is disabled:
0 = BRG timer function is disabled.
1 = BRG timer function and time-out interrupt are enabled.
PHASE—Phase Select
Sets the phase relationship of the data to the clock. For more information on operation of
the PHASE bit, see SPI Clock Phase and Polarity Control on page 116.
CLKPOL—Clock Polarity
0 = SCK idles Low (0).
1 = SCK idle High (1).
WOR—Wire-OR (Open-Drain) Mode Enabled
0 = SPI signal pins not configured for open-drain.
1 = All four SPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain function.
This setting is typically used for multi-master and/or multi-slave configurations.
MMEN—SPI MASTER Mode Enable
0 = SPI configured in SLAVE mode.
1 = SPI configured in MASTER mode.
SPIEN—SPI Enable
0 = SPI disabled.
1 = SPI enabled.
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SPI Status Register
The SPI Status Register indicates the current state of the SPI. All bits revert to their reset
state if the SPIEN bit in the SPICTL Register equals 0.
Table 65. SPI Status Register (SPISTAT)
7
6
5
4
IRQ
OVR
COL
ABT
BITS
FIELD
2
Reserved
0
RESET
R/W
3
1
0
TXST
SLAS
1
R/W*
R
F62H
ADDR
R/W* = Read access. Write a 1 to clear the bit to 0.
IRQ—Interrupt Request
If SPIEN = 1, this bit is set if the STR bit in the SPICTL Register is set, or upon completion of an SPI Master or Slave transaction. This bit does not set if SPIEN = 0 and the SPI
Baud Rate Generator is used as a timer to generate the SPI interrupt.
0 = No SPI interrupt request pending.
1 = SPI interrupt request is pending.
OVR—Overrun
0 = An overrun error has not occurred.
1 = An overrun error has been detected.
COL—Collision
0 = A multi-master collision (mode fault) has not occurred.
1 = A multi-master collision (mode fault) has been detected.
ABT—SLAVE mode transaction abort
This bit is set if the SPI is configured in SLAVE mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the SPIMODE Register. The IRQ bit also sets, indicating the transaction has
completed.
0 = A SLAVE mode transaction abort has not occurred.
1 = A SLAVE mode transaction abort has been detected.
Reserved—Must be 0
TXST—Transmit Status
0 = No data transmission currently in progress.
1 = Data transmission currently in progress.
SLAS—Slave Select
If SPI enabled as a Slave
0 = SS input pin is asserted (Low)
1 = SS input is not asserted (High).
If SPI enabled as a Master, this bit is not applicable.
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SPI Mode Register
The SPI Mode Register configures the character bit width and the direction and value of
the SS pin.
Table 66. SPI Mode Register (SPIMODE)
BITS
7
6
Reserved
FIELD
5
DIAG
4
3
2
NUMBITS[2:0]
1
0
SSIO
SSV
0
RESET
R
R/W
R/W
F63H
ADDR
Reserved—Must be 0
DIAG–Diagnostic Mode Control bit
This bit is for SPI diagnostics. Setting this bit allows the BRG value to be read using the
SPIBRH and SPIBRL Register locations.
0 = Reading SPIBRH, SPIBRL returns the value in the SPIBRH and SPIBRL Registers
1 = Reading SPIBRH returns bits [15:8] of the SPI Baud Rate Generator; and reading
SPIBRL returns bits [7:0] of the SPI Baud Rate Counter. The Baud Rate Counter High and
Low byte values are not buffered.
Caution:
Take precautions if you are reading the values while BRG is counting.
NUMBITS[2:0]—Number of Data Bits Per Character to Transfer
This field contains the number of bits to shift for each character transfer. See the SPI Data
Register description for information on valid bit positions when the character length is less
than 8-bits.
000 = 8 bits
001 = 1 bit
010 = 2 bits
011 = 3 bits
100 = 4 bits
101 = 5 bits
110 = 6 bits
111 = 7 bits
SSIO—Slave Select I/O
0 = SS pin configured as an input.
1 = SS pin configured as an output (MASTER mode only).
SSV—Slave Select Value
If SSIO = 1 and SPI configured as a Master:
0 = SS pin driven Low (0).
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1 = SS pin driven High (1).
This bit has no effect if SSIO = 0 or SPI configured as a Slave
SPI Diagnostic State Register
The SPI Diagnostic State Register provides observability of internal state. This is a read
only register used for SPI diagnostics.
Table 67. SPI Diagnostic State Register (SPIDST)
7
6
SCKEN
TCKEN
BITS
FIELD
5
4
3
2
1
0
SPISTATE
RESET
0
R/W
R
F64H
ADDR
SCKEN–Shift Clock Enable
0 = The internal Shift Clock Enable signal is deasserted
1 = The internal Shift Clock Enable signal is asserted (shift register is updates on
next system clock)
TCKEN–Transmit Clock Enable
0 = The internal Transmit Clock Enable signal is deasserted.
1 = The internal Transmit Clock Enable signal is asserted. When this is asserted the serial
data out is updated on the next system clock (MOSI or MISO).
SPISTATE–SPI State Machine
Defines the current state of the internal SPI State Machine.
SPI Baud Rate High and Low Byte Registers
The SPI Baud Rate High and Low Byte Registers combine to form a 16-bit reload value,
BRG[15:0], for the SPI Baud Rate Generator. When configured as a general purpose
timer, the interrupt interval is calculated using the following equation:
Interrupt Interval (s) = System Clock Period (s) × BRG[15:0]
Table 68. SPI Baud Rate High Byte Register (SPIBRH)
BITS
7
6
5
4
3
FIELD
BRH
RESET
1
R/W
R/W
ADDR
F66H
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BRH = SPI Baud Rate High Byte
Most significant byte, BRG[15:8], of the SPI Baud Rate Generator’s reload value.
Table 69. SPI Baud Rate Low Byte Register (SPIBRL)
BITS
7
6
5
4
3
FIELD
BRL
RESET
1
R/W
R/W
ADDR
F67H
2
1
0
BRL = SPI Baud Rate Low Byte
Least significant byte, BRG[7:0], of the SPI Baud Rate Generator’s reload value.
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I2C Controller
The I2C Controller makes the F0822 Series products bus-compatible with the I2C protocol. The I2C Controller consists of two bidirectional bus lines—a serial data signal (SDA)
and a serial clock signal (SCL). Features of the I2C Controller include:
•
•
•
•
Transmit and Receive Operation in MASTER mode.
Maximum data rate of 400 kbit/s.
7-bit and 10-bit addressing modes for Slaves.
Unrestricted number of data bytes transmitted per transfer.
The I2C Controller in the F0822 Series products does not operate in Slave mode.
Architecture
Figure 25 displays the architecture of the I2C Controller.
SDA
SCL
Shift
ISHIFT
Load
I2CDATA
Baud Rate Generator
I2CBRH
Receive
I2CBRL
Tx/Rx State Machine
I2CCTL
I2C Interrupt
I2CSTAT
Register Bus
Figure 25. I2C Controller Block Diagram
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Operation
The I2C Controller operates in MASTER mode to transmit and receive data. Only a single
master is supported. Arbitration between two masters must be accomplished in software.
I2C supports the following operations:
•
•
•
•
Master transmits to a 7-bit Slave
Master transmits to a 10-bit Slave
Master receives from a 7-bit Slave
Master receives from a 10-bit Slave
SDA and SCL Signals
I2C sends all addresses, data and acknowledge signals over the SDA line, most-significant
bit first. SCL is the common clock for the I2C Controller. When the SDA and SCL pin
alternate functions are selected for their respective GPIO ports, the pins are automatically
configured for open-drain operation.
The master (I2C) is responsible for driving the SCL clock signal, although the clock signal
becomes skewed by a slow slave device. During the low period of the clock, the slave
pulls the SCL signal Low to suspend the transaction. The master releases the clock at the
end of the low period and notices that the clock remains low instead of returning to a high
level. When the slave releases the clock, the I2C Controller continues the transaction. All
data is transferred in bytes and there is no limit to the amount of data transferred in one
operation. When transmitting data or acknowledging read data from the slave, the SDA
signal changes in the middle of the low period of SCL and is sampled in the middle of the
high period of SCL.
I2C Interrupts
The I2C Controller contains four sources of interrupts—Transmit, Receive, Not Acknowledge, and Baud Rate Generator. These four interrupt sources are combined into a single
interrupt request signal to the interrupt controller. The Transmit Interrupt is enabled by the
IEN and TXI bits of the control register. The Receive and Not Acknowledge interrupts are
enabled by the IEN bit of the control register. BRG interrupt is enabled by the BIRQ and
IEN bits of the control register.
Not Acknowledge interrupts occur when a Not Acknowledge condition is received from
the slave or sent by the I2C Controller and neither the START or STOP bit is set. The Not
Acknowledge event sets the NCKI bit of the I2C Status Register and can only be cleared
by setting the START or STOP bit in the I2C Control Register. When this interrupt occurs,
the I2C Controller waits until either the STOP or START bit is set before performing any
action. In an ISR, the NCKI bit should always be checked prior to servicing transmit or
receive interrupt conditions because it indicates the transaction is being terminated.
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Receive interrupts occur when a byte of data has been received by the I2C Controller
(Master reading data from Slave). This procedure sets the RDRF bit of the I2C Status
Register. The RDRF bit is cleared by reading the I2C Data Register. The RDRF bit is set
during the acknowledge phase. The I2C Controller pauses after the acknowledge phase
until the receive interrupt is cleared before performing any other action.
Transmit interrupts occur when the TDRE bit of the I2C Status register sets and the TXI
bit in the I2C Control Register is set. Transmit interrupts occur under the following
conditions when the Transmit Data Register is empty:
• The I2C Controller is enabled
•
The first bit of the byte of an address is shifting out and the RD bit of the I2C Status
register is deasserted.
•
•
The first bit of a 10-bit address shifts out.
The first bit of write data shifts out.
Note: Writing to the I2C Data Register always clears the TRDE bit to 0. When TDRE is asserted,
the I2C Controller pauses at the beginning of the Acknowledge cycle of the byte currently
shifting out until the data register is written with the next value to send or the STOP or
START bits are set indicating the current byte is the last one to send.
The fourth interrupt source is the BRG. If the I2C Controller is disabled (IEN bit in the
I2CCTL Register = 0) and the BIRQ bit in the I2CCTL Register = 1,
an interrupt is generated when the BRG counts down to 1. This allows the I2C Baud Rate
Generator to be used by software as a general purpose timer when IEN = 0.
Software Control of I2C Transactions
Software controls I2C transactions by using the I2C Controller interrupt, by polling the I2C
Status register or by DMA. Note that not all products include a DMA Controller.
To use interrupts, the I2C interrupt must be enabled in the Interrupt Controller. The TXI bit
in the I2C Control Register must be set to enable transmit interrupts.
To control transactions by polling, the interrupt bits (TDRE, RDRF and NCKI) in the
I2C Status Register should be polled. The TDRE bit asserts regardless of the state of the
TXI bit.
Either or both transmit and receive data movement can be controlled by the DMA
Controller. The DMA Controller channel(s) must be initialized to select the I2C transmit
and receive requests. Transmit DMA requests require that the TXI bit in the I2C Control
Register be set.
Caution: A transmit (write) DMA operation hangs if the slave responds with a Not Acknowledge
before the last byte has been sent. After receiving the Not Acknowledge, the I2C Controller sets the NCKI bit in the Status Register and pauses until either the STOP or
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START bits in the Control Register are set.
In order for a receive (read) DMA transaction to send a Not Acknowledge on the last
byte, the receive DMA must be set up to receive n-1 bytes, then software must set the
NAK bit and receive the last (nth) byte directly.
Start and Stop Conditions
The Master (I2C) drives all Start and Stop signals and initiates all transactions. To start a
transaction, the I2C Controller generates a START condition by pulling the SDA signal
Low while SCL is High. To complete a transaction, the I2C Controller generates a Stop
condition by creating a low-to-high transition of the SDA signal while the SCL signal is
high. The START and STOP bits in the I2C Control Register control the sending of the
Start and Stop conditions. A Master is also allowed to end one transaction and begin a new
one by issuing a Restart. This is accomplished by setting the START bit at the end of a
transaction, rather than the STOP bit.
Note: The Start condition not sent until the START bit is set and data has been written to the I2C
Data Register.
Master Write and Read Transactions
The following sections provide a recommended procedure for performing I2C write and
read transactions from the I2C Controller (Master) to slave I2C devices. In general software should rely on the TDRE, RDRF and NCKI bits of the status register (these bits
generate interrupts) to initiate software actions. When using interrupts or DMA, the TXI
bit is set to start each transaction and cleared at the end of each transaction to eliminate a
‘trailing’ Transmit Interrupt.
Caution should be used in using the ACK status bit within a transaction because it is difficult for software to tell when it is updated by hardware.
When writing data to a slave, the I2C pauses at the beginning of the Acknowledge cycle if
the data register has not been written with the next value to be sent (TDRE bit in the I2C
Status register equal to 1). In this scenario where software is not keeping up with the I2C
bus (TDRE asserted longer than one byte time), the Acknowledge clock cycle for byte n is
delayed until the data register is written with byte n + 1, and appears to be grouped with
the data clock cycles for byte n + 1. If either the START or STOP bit is set, the I2C does
not pause prior to the Acknowledge cycle because no additional data is sent.
When a Not Acknowledge condition is received during a write (either during the address
or data phases), the I2C Controller generates the Not Acknowledge interrupt (NCKI = 1)
and pause until either the STOP or START bit is set. Unless the Not Acknowledge was
received on the last byte, the data register will already have been written with the next
address or data byte to send. In this case the FLUSH bit of the control register should be
set at the same time the STOP or START bit is set to remove the stale transmit data and
enable subsequent Transmit Interrupts.
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When reading data from the slave, the I2C pauses after the data Acknowledge cycle until
the receive interrupt is serviced and the RDRF bit of the status register is cleared by reading
the I2C Data Register. Once the I2C Data Register has been read, the I2C reads the next
data byte.
Address Only Transaction with a 7-bit Address
In the situation where software determines if a slave with a 7-bit address is responding
without sending or receiving data, a transaction can be done which only consists of an
address phase. Figure 26 on page 131 displays this “address only” transaction to determine
if a slave with a 7-bit address will acknowledge. As an example, this transaction can be
used after a “write” has been done to a EEPROM to determine when the EEPROM completes its internal write operation and is once again responding to I2C transactions. If the
slave does not Acknowledge, the transaction is repeated until the slave does Acknowledge.
S
Slave Address
W = 0 A/A
P
Figure 26. 7-Bit Address Only Transaction Format
Follow the steps below for an address only transaction to a 7-bit addressed slave:
1. Software asserts the IEN bit in the I2C Control Register.
2. Software asserts the TXI bit of the I2C Control Register to enable Transmit interrupts.
3. The I2C interrupt asserts, because the I2C Data Register is empty (TDRE = 1)
4. Software responds to the TDRE bit by writing a 7-bit Slave address plus write bit (=0)
to the I2C Data Register. As an alternative this could be a read operation instead of a
write operation.
5. Software sets the START and STOP bits of the I2C Control Register and clears the
TXI bit.
6. The I2C Controller sends the START condition to the I2C Slave.
7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
Register.
8. Software polls the STOP bit of the I2C Control Register. Hardware deasserts the
STOP bit when the address only transaction is completed.
9.
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Software checks the ACK bit of the I2C Status Register. If the slave acknowledged,
the ACK bit is equal to 1. If the slave does not acknowledge, the ACK bit is equal to 0.
The NCKI interrupt does not occur in the not acknowledge case because the STOP bit
was set.
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Write Transaction with a 7-Bit Address
Figure 27 displays the data transfer format for a 7-bit addressed slave. Shaded regions
indicate data transferred from the I2C Controller to slaves and unshaded regions indicate
data transferred from the slaves to the I2C Controller.
S
Slave Address
W=0
A
Data
A
Data
A
Data
A/A P/S
Figure 27. 7-Bit Addressed Slave Data Transfer Format
Follow the steps below for a transmit operation to a 7-bit addressed slave:
1. Software asserts the IEN bit in the I2C Control Register.
2. Software asserts the TXI bit of the I2C Control Register to enable Transmit Interrupts.
3. The I2C interrupt asserts, because the I2C Data Register is empty.
4. Software responds to the TDRE bit by writing a 7-bit Slave address plus write bit (=0)
to the I2C Data Register.
5. Software asserts the START bit of the I2C Control Register.
6. The I2C Controller sends the START condition to the I2C Slave.
7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
Register.
8. After one bit of address has been shifted out by the SDA signal, the Transmit Interrupt
is asserted (TDRE = 1).
9. Software responds by writing the transmit data into the I2C Data Register.
10. The I2C Controller shifts the rest of the address and write bit out by the SDA signal.
11. If the I2C Slave sends an acknowledge (by pulling the SDA signal low) during the
next high period of SCL the I2C Controller sets the ACK bit in the I2C Status register.
Continue with step 12.
If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is
set in the Status register, ACK bit is cleared). Software responds to the Not
Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit.
The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore following steps).
12. The I2C Controller loads the contents of the I2C Shift register with the contents of the
I2C Data Register.
13. The I2C Controller shifts the data out of using the SDA signal. After the first bit is
sent, the Transmit Interrupt is asserted.
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14. If more bytes remain to be sent, return to step 9.
15. Software responds by setting the STOP bit of the I2C Control Register (or START bit
to initiate a new transaction). In the STOP case, software clears the TXI bit of the I2C
Control Register at the same time.
16. The I2C Controller completes transmission of the data on the SDA signal.
17. The slave can either Acknowledge or Not Acknowledge the last byte. Because either
the STOP or START bit is already set, the NCKI interrupt does not occur.
18. The I2C Controller sends the STOP (or RESTART) condition to the I2C bus. The
STOP or START bit is cleared.
Address Only Transaction with a 10-bit Address
In the situation where software wants to determine if a slave with a 10-bit address is
responding without sending or receiving data, a transaction is done which only consists of
an address phase. Figure 28 displays this “address only” transaction to determine if a slave
with 10-bit address will acknowledge. As an example, this transaction is used after a
“write” has been done to a EEPROM to determine when the EEPROM completes its internal write operation and is once again responding to I2C transactions. If the slave does not
Acknowledge the transaction is repeated until the slave is able to Acknowledge.
S
Slave Address
1st 7 bits
W = 0 A/A
Slave Address
2nd Byte
A/A P
Figure 28. 10-Bit Address Only Transaction Format
Follow the steps below for an address only transaction to a 10-bit addressed slave:
1. Software asserts the IEN bit in the I2C Control Register.
2. Software asserts the TXI bit of the I2C Control Register to enable Transmit interrupts.
3. The I2C interrupt asserts, because the I2C Data Register is empty (TDRE = 1)
4. Software responds to the TDRE interrupt by writing the first slave address byte. The
least-significant bit must be 0 for the write operation.
5. Software asserts the START bit of the I2C Control Register.
6. The I2C Controller sends the START condition to the I2C Slave.
7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
Register.
8. After one bit of address is shifted out by the SDA signal, the Transmit Interrupt is
asserted.
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9. Software responds by writing the second byte of address into the contents of the I2C
Data Register.
10. The I2C Controller shifts the rest of the first byte of address and write bit out the SDA
signal.
11. If the I2C Slave sends an acknowledge by pulling the SDA signal low during the next
high period of SCL the I2C Controller sets the ACK bit in the I2C Status register.
Continue with step 12.
If the slave does not acknowledge the first address byte, the I2C Controller sets the
NCKI bit and clears the ACK bit in the I2C Status register. Software response to the
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore following steps).
12. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
Register (2nd byte of address).
13. The I2C Controller shifts the second address byte out the SDA signal. After the first
bit has been sent, the Transmit Interrupt is asserted.
14. Software responds by setting the STOP bit in the I2C Control Register. The TXI bit
can be cleared at the same time.
15. Software polls the STOP bit of the I2C Control Register. Hardware deasserts the
STOP bit when the transaction is completed (STOP condition has been sent).
16. Software checks the ACK bit of the I2C Status register. If the slave acknowledged, the
ACK bit is equal to 1. If the slave does not acknowledge, the ACK bit is equal
to 0. The NCKI interrupt do not occur because the STOP bit was set.
Write Transaction with a 10-Bit Address
Figure 29 displays the data transfer format for a 10-bit addressed slave. Shaded regions
indicate data transferred from the I2C Controller to slaves and unshaded regions indicate
data transferred from the slaves to the I2C Controller.
S
Slave Address
W=0 A
1st 7 bits
Slave Address
2nd Byte
A Data A Data A/A P/S
Figure 29. 10-Bit Addressed Slave Data Transfer Format
The first seven bits transmitted in the first byte are 11110XX. The two bits XX are the two
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
read/write control bit (=0). The transmit operation is carried out in the same manner as 7bit addressing.
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Follow the steps below for a transmit operation on a 10-bit addressed slave:
1. Software asserts the IEN bit in the I2C Control Register.
2. Software asserts the TXI bit of the I2C Control Register to enable Transmit interrupts.
3. The I2C interrupt asserts because the I2C Data Register is empty.
4. Software responds to the TDRE interrupt by writing the first slave address byte to the
I2C Data Register. The least-significant bit must be 0 for the write operation.
5. Software asserts the START bit of the I2C Control Register.
6. The I2C Controller sends the START condition to the I2C Slave.
7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
Register.
8. After one bit of address is shifted out by the SDA signal, the Transmit Interrupt is
asserted.
9. Software responds by writing the second byte of address into the contents of the I2C
Data Register.
10. The I2C Controller shifts the rest of the first byte of address and write bit out the SDA
signal.
11. If the I2C Slave acknowledges the first address byte by pulling the SDA signal low
during the next high period of SCL, the I2C Controller sets the ACK bit in the I2C
Status register. Continue with step 12.
If the slave does not acknowledge the first address byte, the I2C Controller sets the
NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore the following steps).
12. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
Register.
13. The I2C Controller shifts the second address byte out the SDA signal. After the first
bit has been sent, the Transmit Interrupt is asserted.
14. Software responds by writing a data byte to the I2C Data Register.
15. The I2C Controller completes shifting the contents of the shift register on the SDA
signal.
16. If the I2C Slave sends an acknowledge by pulling the SDA signal low during the next
high period of SCL, the I2C Controller sets the ACK bit in the I2C Status register.
Continue with step 17.
If the slave does not acknowledge the second address byte or one of the data bytes, the
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I2C Controller sets the NCKI bit and clears the ACK bit in the I2C Status register.
Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH
bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus
and clears the STOP and NCKI bits. The transaction is complete (ignore the following
steps).
17. The I2C Controller shifts the data out by the SDA signal. After the first bit is sent, the
Transmit Interrupt is asserted.
18. If more bytes remain to be sent, return to step 14.
19. If the last byte is currently being sent, software sets the STOP bit of the I2C Control
Register (or START bit to initiate a new transaction). In the STOP case, software also
clears the TXI bit of the I2C Control Register at the same time.
20. The I2C Controller completes transmission of the last data byte on the SDA signal.
21. The slave can either Acknowledge or Not Acknowledge the last byte. Because either
the STOP or START bit is already set, the NCKI interrupt does not occur.
22. The I2C Controller sends the STOP (or RESTART) condition to the I2C bus and clears
the STOP (or START) bit.
Read Transaction with a 7-Bit Address
Figure 30 displays the data transfer format for a read operation to a 7-bit addressed slave.
The shaded regions indicate data transferred from the I2C Controller to slaves and
unshaded regions indicate data transferred from the slaves to the I2C Controller.
S
Slave Address
R=1
A
Data
A
Data
A
P/S
Figure 30. Receive Data Transfer Format for a 7-Bit Addressed Slave
Follow the steps below for a read operation to a 7-bit addressed slave:
1. Software writes the I2C Data Register with a 7-bit Slave address plus the read bit (=1).
2. Software asserts the START bit of the I2C Control Register.
3. If this is a single byte transfer, Software asserts the NAK bit of the I2C Control Register
so that after the first byte of data has been read by the I2C Controller, a Not
Acknowledge is sent to the I2C Slave.
4. The I2C Controller sends the START condition.
5. The I2C Controller shifts the address and read bit out the SDA signal.
6. If the I2C Slave acknowledges the address by pulling the SDA signal Low during the
next high period of SCL, the I2C Controller sets the ACK bit in the I2C Status register.
Continue with step 7.
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If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is
set in the Status register, ACK bit is cleared). Software responds to the Not
Acknowledge interrupt by setting the STOP bit and clearing the TXI bit. The I2C
Controller sends the STOP condition on the bus and clears the STOP and NCKI bits.
The transaction is complete (ignore the following steps).
7. The I2C Controller shifts in the byte of data from the I2C Slave on the SDA signal.
The I2C Controller sends a Not Acknowledge to the I2C Slave if the NAK bit is set
(last byte), else it sends an Acknowledge.
8. The I2C Controller asserts the Receive interrupt (RDRF bit set in the Status register).
9. Software responds by reading the I2C Data Register which clears the RDRF bit. If
there is only one more byte to receive, set the NAK bit of the I2C Control Register.
10. If there are more bytes to transfer, return to Step 7.
11. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I2C
Controller.
12. Software responds by setting the STOP bit of the I2C Control Register.
13. A STOP condition is sent to the I2C Slave, the STOP and NCKI bits are cleared.
Read Transaction with a 10-Bit Address
Figure 31 displays the read transaction format for a 10-bit addressed slave. The shaded
regions indicate data transferred from the I2C Controller to slaves and unshaded regions
indicate data transferred from the slaves to the I2C Controller.
S
Slave Address
W=0 A
1st 7 bits
Slave Address
2nd Byte
A S
Slave Address
1st 7 bits
R=1 A Data A Data A P
Figure 31. Receive Data Format for a 10-Bit Addressed Slave
The first seven bits transmitted in the first byte are 11110XX. The two bits XX are the two
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
Follow the steps below for the data transfer procedure for a read operation to a 10-bit
addressed slave:
1. Software writes 11110B followed by the two address bits and a 0 (write) to the I2C
Data Register.
2. Software asserts the START and TXI bits of the I2C Control Register.
3. The I2C Controller sends the Start condition.
4. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
Register.
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5. After the first bit has been shifted out, a Transmit Interrupt is asserted.
6. Software responds by writing the lower eight bits of address to the I2C Data Register.
7. The I2C Controller completes shifting of the two address bits and a 0 (write).
8. If the I2C Slave acknowledges the first address byte by pulling the SDA signal low
during the next high period of SCL, the I2C Controller sets the ACK bit in the I2C
Status register. Continue with step 9.
If the slave does not acknowledge the first address byte, the I2C Controller sets the
NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore following steps).
9. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
Register (second address byte).
10. The I2C Controller shifts out the second address byte. After the first bit is shifted, the
I2C Controller generates a Transmit Interrupt.
11. Software responds by setting the START bit of the I2C Control Register to generate a
repeated START and by clearing the TXI bit.
12. Software responds by writing 11110B followed by the 2-bit Slave address and a 1
(read) to the I2C Data Register.
13. If only one byte is to be read, software sets the NAK bit of the I2C Control Register.
14. After the I2C Controller shifts out the 2nd address byte, the I2C Slave sends an
acknowledge by pulling the SDA signal low during the next high period of SCL, the
I2C Controller sets the ACK bit in the I2C Status register. Continue with step 15.
If the slave does not acknowledge the second address byte, the I2C Controller sets the
NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore the following steps).
15. The I2C Controller sends the repeated START condition.
16. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
Register (third address transfer).
17. The I2C Controller sends 11110B followed by the two most significant bits of the
slave read address and a 1 (read).
18. The I2C Slave sends an acknowledge by pulling the SDA signal Low during the next
high period of SCL.
If the slave were to Not Acknowledge at this point (this should not happen because the
slave did acknowledge the first two address bytes), software would respond by setting
the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the
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STOP condition on the bus and clears the STOP and NCKI bits. The transaction is
complete (ignore the following steps).
19. The I2C Controller shifts in a byte of data from the I2C Slave on the SDA signal. The
I2C Controller sends a Not Acknowledge to the I2C Slave if the NAK bit is set (last
byte), else it sends an Acknowledge.
20. The I2C Controller asserts the Receive interrupt (RDRF bit set in the Status register).
21. Software responds by reading the I2C Data Register which clears the RDRF bit. If
there is only one more byte to receive, set the NAK bit of the I2C Control Register.
22. If there are one or more bytes to transfer, return to step 19.
23. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I2C
Controller.
24. Software responds by setting the STOP bit of the I2C Control Register.
25. A STOP condition is sent to the I2C Slave and the STOP and NCKI bits are cleared.
I2C Control Register Definitions
I2C Data Register
The I2C Data Register (Table 70) holds the data that is to be loaded into the I2C Shift register during a write to a slave. This register also holds data that is loaded from the I2C Shift
register during a read from a slave. The I2C Shift Register is not accessible in the Register
File address space, but is used only to buffer incoming and outgoing data.
Table 70. I2C Data Register (I2CDATA)
BITS
7
6
5
4
3
FIELD
DATA
RESET
0
R/W
R/W
ADDR
F50H
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I2C Status Register
The Read-only I2C Status register (Table 71) indicates the status of the I2C Controller.
Table 71. I2C Status Register (I2CSTAT)
BITS
7
6
5
4
3
2
1
0
FIELD
TDRE
RDRF
ACK
10B
RD
TAS
DSS
NCKI
RESET
1
0
R
R/W
F51H
ADDR
TDRE—Transmit Data Register Empty
When the I2C Controller is enabled, this bit is 1 when the I2C Data Register is empty.
When this bit is set, an interrupt is generated if the TXI bit is set, except when the I2C
Controller is shifting in data during the reception of a byte or when shifting an address and
the RD bit is set. This bit is cleared by writing to the I2CDATA register.
RDRF—Receive Data Register Full
This bit is set = 1 when the I2C Controller is enabled and the I2C Controller has received a
byte of data. When asserted, this bit causes the I2C Controller to generate an interrupt.
This bit is cleared by reading the I2C Data Register (unless the read is performed using
execution of the OCD’s Read Register command).
ACK—Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received.
When set, this bit indicates that an Acknowledge occurred for the last byte transmitted or
received. This bit is cleared when IEN = 0 or when a Not Acknowledge occurred for the
last byte transmitted or received. It is not reset at the beginning of each transaction and is
not reset when this register is read.
Caution: Software must be cautious in making decisions based on this bit within a transaction
because software cannot tell when the bit is updated by hardware. In the case of write
transactions, the I2C pauses at the beginning of the Acknowledge cycle if the next
transmit data or address byte has not been written (TDRE = 1) and STOP and START
= 0. In this case the ACK bit is not updated until the transmit interrupt is serviced and
the Acknowledge cycle for the previous byte completes. For examples on usage of the
ACK bit, see Address Only Transaction with a 7-bit Address on page 131 and Address
Only Transaction with a 10-bit Address on page 133.
10B—10-Bit Address
This bit indicates whether a 10-bit or 7-bit address is being transmitted. After the START
bit is set, if the five most-significant bits of the address are 11110B, this bit is set. When
set, it is reset once the first byte of the address has been sent.
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RD—Read
This bit indicates the direction of transfer of the data. It is active High during a read. The
status of this bit is determined by the least-significant bit of the I2C Shift register after the
START bit is set.
TAS—Transmit Address State
This bit is active High while the address is being shifted out of the I2C Shift Register.
DSS—Data Shift State
This bit is active High while data is being shifted to or from the I2C Shift Register.
NCKI—NACK Interrupt
This bit is set high when a Not Acknowledge condition is received or sent and neither the
START nor the STOP bit is active. When set, this bit generates an interrupt that can only be
cleared by setting the START or STOP bit, allowing you to specify whether you want to
perform a STOP or a repeated START.
I2C Control Register
The I2C Control Register (Table 72) enables the I2C operation.
Table 72. I2C Control Register (I2CCTL)
BITS
FIELD
7
6
5
4
3
2
1
0
IEN
START
STOP
BIRQ
TXI
NAK
FLUSH
FILTEN
R/W
R/W1
W1
R/W
0
RESET
R/W
R/W
ADDR
R/W1
R/W1
R/W
F52H
IEN—I2C Enable
1 = The I2C transmitter and receiver are enabled.
0 = The I2C transmitter and receiver are disabled.
START—Send Start Condition
This bit sends the Start condition. Once asserted, it is cleared by the I2C Controller after it
sends the START condition or if the IEN bit is deasserted. If this bit is 1, it cannot be
cleared to 0 by writing to the register. After this bit is set, the Start condition is sent if
there is data in the I2C Data or I2C Shift register. If there is no data in one of these registers, the I2C Controller waits until the data register is written. If this bit is set while
the I2C Controller is shifting out data, it generates a START condition after the byte shifts
and the acknowledge phase completes. If the STOP bit is also set, it also waits until the
STOP condition is sent before sending the START condition.
STOP—Send Stop Condition
This bit causes the I2C Controller to issue a STOP condition after the byte in the I2C Shift
register has completed transmission or after a byte is received in a receive operation. Once
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set, this bit is reset by the I2C Controller after a STOP condition is sent or by deasserting
the IEN bit. If this bit is 1, it cannot be cleared to 0 by writing to the register.
BIRQ—Baud Rate Generator Interrupt Request
This bit allows the I2C Controller to be used as an additional timer when the I2C
Controller is disabled. This bit is ignored when the I2C Controller is enabled.
1 = An interrupt occurs every time the BRG counts down to one.
0 = No BRG interrupt occurs.
TXI—Enable TDRE interrupts
This bit enables the transmit interrupt when the I2C Data Register is empty (TDRE = 1).
1 = Transmit Interrupt (and DMA transmit request) is enabled.
0 = Transmit Interrupt (and DMA transmit request) is disabled.
NAK—Send NAK
This bit sends a Not Acknowledge condition after the next byte of data is read from the
I2C Slave. Once asserted, it is deasserted after a Not Acknowledge is sent or the IEN bit is
deasserted. If this bit is 1, it cannot be cleared to 0 by writing to the register.
FLUSH—Flush Data
Setting this bit to 1 clears the I2C Data Register and sets the TDRE bit to 1. This bit allows
flushing of the I2C Data Register when a Not Acknowledge interrupt is received after the
data has been sent to the I2C Data Register. Reading this bit always returns 0.
FILTEN—I2C Signal Filter Enable
This bit enables low-pass digital filters on the SDA and SCL input signals. These filters
reject any input pulse with periods less than a full system clock cycle. The filters introduce
a 3-system clock cycle latency on the inputs.
1 = low-pass filters are enabled.
0 = low-pass filters are disabled.
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143
I2C Baud Rate High and Low Byte Registers
The I2C Baud Rate High and Low Byte registers (Tables 73 and 73) combine to form a 16bit reload value, BRG[15:0], for the I2C Baud Rate Generator. When configured as a general purpose timer, the interrupt interval is calculated using the following equation:
Interrupt Interval (s) = System Clock Period (s) ×BRG[15:0]
Table 73. I2C Baud Rate High Byte Register (I2CBRH)
BITS
7
6
5
4
3
FIELD
BRH
RESET
FFH
R/W
R/W
ADDR
F53H
2
1
0
BRH = I2C Baud Rate High Byte
Most significant byte, BRG[15:8], of the I2C Baud Rate Generator’s reload value.
Note: If the DIAG bit in the I2C Diagnostic Control Register is set to 1, a read of the I2CBRH
register returns the current value of the I2C Baud Rate Counter[15:8].
Table 74. I2C Baud Rate Low Byte Register (I2CBRL)
BITS
7
6
5
4
3
FIELD
BRL
RESET
FFH
R/W
R/W
ADDR
F54H
2
1
0
BRL = I2C Baud Rate Low Byte
Least significant byte, BRG[7:0], of the I2C Baud Rate Generator’s reload value.
Note: If the DIAG bit in the I2C Diagnostic Control Register is set to 1, a read of the I2CBRL
register returns the current value of the I2C Baud Rate Counter [7:0].
I2C Diagnostic State Register
The I2C Diagnostic State register (Table 75) provides observability of internal state.
This is a read only register used for I2C diagnostics and manufacturing test.
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Table 75. I2C Diagnostic State Register (I2CDST)
BITS
FIELD
7
6
5
SCLIN
SDAIN
STPCNT
RESET
4
3
2
1
0
TXRXSTATE
X
0
R
R/W
F55H
ADDR
SCLIN—Value of Serial Clock input signal
SDAIN—Value of the Serial Data input signal
STPCNT—Value of the internal Stop Count control signal
TXRXSTATE—Value of the internal I2C state machine
TXRXSTATE
0_0000
0_0001
0_0010
0_0011
0_0100
0_0101
0_0110
0_0111
0_1000
0_1001
0_1010
0_1011
0_1100
0_1101
0_1110
0_1111
1_0000
1_0001
1_0010
1_0011
1_0100
1_0101
1_0110
PS022517-0508
State Description
Idle State
START State
Send/Receive data bit 7
Send/Receive data bit 6
Send/Receive data bit 5
Send/Receive data bit 4
Send/Receive data bit 3
Send/Receive data bit 2
Send/Receive data bit 1
Send/Receive data bit 0
Data Acknowledge State
Second half of data Acknowledge State used only for not acknowledge
First part of STOP state
Second part of STOP state
10-bit addressing: Acknowledge State for 2nd address byte
7-bit addressing: Address Acknowledge State
10-bit address: Bit 0 (Least significant bit) of 2nd address byte
7-bit address: Bit 0 (Least significant bit) (R/W) of address byte
10-bit addressing: Bit 7 (Most significant bit) of 1st address byte
10-bit addressing: Bit 6 of 1st address byte
10-bit addressing: Bit 5 of 1st address byte
10-bit addressing: Bit 4 of 1st address byte
10-bit addressing: Bit 3 of 1st address byte
10-bit addressing: Bit 2 of 1st address byte
10-bit addressing: Bit 1 of 1st address byte
I2C Controller
Z8 Encore! XP® F0822 Series
Product Specification
145
TXRXSTATE
1_0111
1_1000
1_1001
1_1010
1_1011
1_1100
1_1101
1_1110
1_1111
State Description
10-bit addressing: Bit 0 (R/W) of 1st address byte
10-bit addressing: Acknowledge state for 1st address byte
10-bit addressing: Bit 7 of 2nd address byte
7-bit addressing: Bit 7 of address byte
10-bit addressing: Bit 6 of 2nd address byte
7-bit addressing: Bit 6 of address byte
10-bit addressing: Bit 5 of 2nd address byte
7-bit addressing: Bit 5 of address byte
10-bit addressing: Bit 4 of 2nd address byte
7-bit addressing: Bit 4 of address byte
10-bit addressing: Bit 3 of 2nd address byte
7-bit addressing: Bit 3 of address byte
10-bit addressing: Bit 2 of 2nd address byte
7-bit addressing: Bit 2 of address byte
10-bit addressing: Bit 1 of 2nd address byte
7-bit addressing: Bit 1 of address byte
I2C Diagnostic Control Register
The I2C Diagnostic register (Table 76) provides control over diagnostic modes. This
register is a read/write register used for I2C diagnostics.
Table 76. I2C Diagnostic Control Register (I2CDIAG)
BITS
FIELD
7
6
5
4
ADDR
2
1
0
Reserved
DIAG
0
RESET
R/W
3
R
R/W
F56H
DIAG = Diagnostic Control Bit—Selects read back value of the Baud Rate
Reload registers.
0 = Normal mode. Reading the Baud Rate High and Low Byte registers returns
the baud rate reload value.
1 = Diagnostic mode. Reading the Baud Rate High and Low Byte registers
returns the baud rate counter value.
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Product Specification
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PS022517-0508
I2C Controller
Z8 Encore! XP® F0822 Series
Product Specification
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Analog-to-Digital Converter
The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary
number. The features of the sigma-delta ADC include:
•
•
•
Five analog input sources are multiplexed with GPIO ports.
Interrupt upon conversion complete.
Internal voltage reference generator.
The ADC is available only in the Z8F0822, Z8F0821, Z8F0422, Z8F0421, Z8R0822,
Z8R0821, Z8R0422 and Z8R0421 devices.
Architecture
Figure 32 displays the three major functional blocks (converter, analog multiplexer, and
voltage reference generator) of the ADC. The ADC converts an analog input signal to its
digital representation. The 5-input analog multiplexer selects one of the 5 analog input
sources. The ADC requires an input reference voltage for the conversion. The voltage reference for the conversion can be input through the external VREF pin or generated internally by the voltage reference generator.
VREF
Internal Voltage
Reference Generator
Analog-to-Digital
Converter
Analog Input
Multiplexer
IRQ
Reference Input
ANA0
ANA1
Analog Input
ANA2
ANA3
ANA4
ANAIN[3:0]
Figure 32. Analog-to-Digital Converter Block Diagram
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Operation
Automatic Power-Down
If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles,
portions of the ADC are automatically powered-down. From this power-down state, the
ADC requires 40 system clock cycles to power-up. The ADC powers up when a
conversion is requested using the ADC Control Register.
Single-Shot Conversion
When configured for single-shot conversion, the ADC performs a single analog-to-digital
conversion on the selected analog input channel. After completion of the conversion, the
ADC shuts down. Follow the steps below for setting up the ADC and initiating a singleshot conversion:
1. Enable the desired analog inputs by configuring the GPIO pins for alternate function.
This configuration disables the digital input and output drivers.
2. Write to the ADC Control Register to configure the ADC and begin the conversion.
The bit fields in the ADC Control Register is written simultaneously:
– Write to the ANAIN[3:0] field to select one of the 5 analog input sources.
– Clear CONT to 0 to select a single-shot conversion.
– Write to the VREF bit to enable or disable the internal voltage reference generator.
– Set CEN to 1 to start the conversion.
3. CEN remains 1 while the conversion is in progress. A single-shot conversion requires
5129 system clock cycles to complete. If a single-shot conversion is requested from an
ADC powered-down state, the ADC uses 40 additional clock cycles to power-up
before beginning the 5129 cycle conversion.
4. When the conversion is complete, the ADC control logic performs the following
operations:
– 10-bit data result written to {ADCD_H[7:0], ADCD_L[7:6]}.
– CEN resets to 0 to indicate the conversion is complete.
– An interrupt request is sent to the Interrupt Controller.
5. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
powered-down.
Continuous Conversion
When configured for continuous conversion, the ADC continuously performs an
analog-to-digital conversion on the selected analog input. Each new data value over-writes
the previous value stored in the ADC Data Registers. An interrupt is generated after each
conversion.
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Caution:
In CONTINUOUS mode, ensure that ADC updates are limited by the input
signal bandwidth of the ADC and the latency of the ADC and its digital filter. Step changes at the input are not seen at the next output from the ADC.
The response of the ADC (in all modes) is limited by the input signal bandwidth and the latency.
Follow the steps below for setting up the ADC and initiating continuous conversion:
1. Enable the desired analog input by configuring the GPIO pins for alternate function.
This disables the digital input and output driver.
2. Write to the ADC Control Register to configure the ADC for continuous conversion.
The bit fields in the ADC Control Register can be written simultaneously:
–
Write to the ANAIN[3:0] field to select one of the 5 analog input sources.
–
Set CONT to 1 to select continuous conversion.
–
–
Write to the VREF bit to enable or disable the internal voltage reference generator.
Set CEN to 1 to start the conversions.
3. When the first conversion in continuous operation is complete (after 5129 system
clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic
performs the following operations:
– CEN resets to 0 to indicate the first conversion is complete. CEN remains 0 for all
subsequent conversions in continuous operation.
– An interrupt request is sent to the Interrupt Controller to indicate the conversion is
complete.
4. Thereafter, the ADC writes a new 10-bit data result to {ADCD_H[7:0],
ADCD_L[7:6]} every 256 system clock cycles. An interrupt request is sent to the
Interrupt Controller when each conversion is complete.
5. To disable continuous conversion, clear the CONT bit in the ADC Control Register
to 0.
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ADC Control Register Definitions
ADC Control Register
The ADC Control Register selects the analog input channel and initiates the
analog-to-digital conversion.
Table 77. ADC Control Register (ADCCTL)
BITS
FIELD
7
6
5
4
CEN
Reserved
VREF
CONT
RESET
0
3
2
1
0
ANAIN[3:0]
1
0
R/W
R/W
ADDR
F70H
CEN—Conversion Enable
0 = Conversion is complete. Writing a 0 produces no effect. The ADC automatically
clears this bit to 0 when a conversion has been completed.
1 = Begin conversion. Writing a 1 to this bit starts a conversion. If a conversion is
already in progress, the conversion restarts. This bit remains 1 until the conversion
is complete.
Reserved—Must be 0
VREF
0 = Internal reference generator enabled. The VREF pin must be left unconnected or
capacitively coupled to analog ground (AVSS).
1 = Internal voltage reference generator disabled. An external voltage reference must
be provided through the VREF pin.
CONT
0 = SINGLE-SHOT conversion. ADC data is output once at completion of the
5129 system clock cycles.
1 = Continuous conversion. ADC data updated every 256 system clock cycles.
ANAIN—Analog Input Select
These bits select the analog input for conversion. Not all Port pins in this list are available
in all packages for Z8 Encore! XP® F0822 Series. See Signal and Pin Descriptions for
information regarding the Port pins available with each package style.
Do not enable unavailable analog inputs.
0000 = ANA0
0001 = ANA1
0010 = ANA2
0011 = ANA3
0100 = ANA4
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0101 = Reserved
011X = Reserved
1XXX = Reserved
ADC Data High Byte Register
The ADC Data High Byte register contains the upper eight bits of the 10-bit ADC output.
During a SINGLE-SHOT conversion, this value is invalid. Access to the ADC Data High
Byte register is read-only. The full 10-bit ADC result is given by {ADCD_H[7:0],
ADCD_L[7:6]}. Reading the ADC Data High Byte register latches data in the ADC Low
Bits register.
Table 78. ADC Data High Byte Register (ADCD_H)
BITS
7
6
5
4
3
FIELD
ADCD_H
RESET
X
R/W
R
2
1
0
F72H
ADDR
ADCD_H—ADC Data High Byte
This byte contains the upper eight bits of the 10-bit ADC output. These bits are not valid
during a single-shot conversion. During a continuous conversion, the last conversion
output is held in this register. These bits are undefined after a Reset.
ADC Data Low Bits Register
The ADC Data Low Bits register contains the lower two bits of the conversion value. The
data in the ADC Data Low Bits register is latched each time the ADC Data High Byte
register is read. Reading this register always returns the lower two bits of the conversion
last read into the ADC High Byte register. Access to the ADC Data Low Bits register is
read-only. The full 10-bit ADC result is given by {ADCD_H[7:0], ADCD_L[7:6]}.
Table 79. ADC Data Low Bits Register (ADCD_L)
BITS
FIELD
7
6
5
4
3
ADCD_L
X
R/W
R
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0
Reserved
RESET
ADDR
2
F73H
Analog-to-Digital Converter
Z8 Encore! XP® F0822 Series
Product Specification
152
ADCD_L—ADC Data Low Bits
These are the least significant two bits of the 10-bit ADC output. These bits are undefined
after a Reset.
Reserved
These bits are reserved and are always undefined.
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Flash Memory
The products in Z8 Encore! XP® F0822 Series feature either 8 KB (8192) or 4 KB (4096)
bytes of Flash memory with Read/Write/Erase capability. The Flash memory is programmed and erased in-circuit by either user code or through the OCD.
The Flash memory array is arranged in 512-byte per page. The 512-byte page is the
minimum Flash block size that can be erased. The Flash memory is divided into eight
sectors which is protected from programming and erase operations on a per sector basis.
Table 80 describes the Flash memory configuration for each device in the Z8F082x
family. Table 81 lists the sector address ranges. Figure 33 on page 154 displays the Flash
memory arrangement.
Table 80. Flash Memory Configurations
Part Number
Flash Size
Number
of Pages
Flash Memory
Addresses
Sector Size
Number of
Sectors
Pages
per
Sector
Z8F08xx
8 KB (8192)
16
0000H - 1FFFH
1 KB (1024)
8
2
Z8F04xx
4 KB (4096)
8
0000H - 0FFFH
0.5 KB (512)
8
1
Table 81. Flash Memory Sector Addresses
Flash Sector Address Ranges
Sector Number
PS022517-0508
Z8F04xx
Z8F08xx
0
0000H-01FFH
0000H-03FFH
1
0200H-03FFH
0400H-07FFH
2
0400H-05FFH
0800H-0BFFH
3
0600H-07FFH
0C00H-0FFFH
4
0800H-09FFH
1000H-13FFH
5
0A00H-0BFFH
1400H-17FFH
6
0C00H-0DFFH
1800H-1BFFH
7
0E00H-0FFFH
1C00H-1FFFH
Flash Memory
Z8 Encore! XP® F0822 Series
Product Specification
154
8 KB Flash
Program Memory
Addresses
1FFFH
1E00H
1DFFH
1C00H
1BFFH
1A00H
16 Pages
512 Bytes per Page
05FFH
0400H
03FFH
0200H
01FFH
0000H
Figure 33. Flash Memory Arrangement
Information Area
Table 82 on page 155 describes the Z8 Encore! XP® F0822 Series Information Area. This
512-byte Information Area is accessed by setting bit 7 of the Page Select Register to 1.
When access is enabled, the Information Area is mapped into Flash Memory and overlays
the 512 bytes at addresses FE00H to FFFFH. When the Information Area access is enabled,
LDC instructions return data from the Information Area. CPU instruction fetches always
comes from Flash Memory regardless of the Information Area access bit. Access to the
Information Area is read-only.
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Table 82. Z8 Encore! XP® F0822 Series Information Area Map
Flash Memory Address (Hex)
Function
FE00H-FE3FH
Reserved
FE40H-FE53H
Part Number
20-character ASCII alphanumeric code
Left justified and filled with zeros
FE54H-FFFFH
Reserved
Operation
The Flash Controller provides the proper signals and timing for Byte Programming, Page
Erase, and Mass Erase of the Flash memory. The Flash Controller contains a protection
mechanism, using the Flash Control Register (FCTL), to prevent accidental programming
or erasure. The following subsections provide details on the various operations (Lock,
Unlock, Sector Protect, Byte Programming, Page Erase, and Mass Erase).
Timing Using the Flash Frequency Registers
Before performing a program or erase operation on the Flash memory, you must first
configure the Flash Frequency High and Low Byte registers. The Flash Frequency
registers allow programming and erasure of the Flash with system clock frequencies
ranging from 20 kHz through 20 MHz (the valid range is limited to the device operating
frequencies).
The Flash Frequency High and Low Byte registers combine to form a 16-bit value,
FFREQ, to control timing for Flash program and erase operations. The 16-bit Flash
Frequency value must contain the system clock frequency in kHz. This value is calculated
using the following equation:
System Clock Frequency (Hz)
FFREQ[15:0] = ------------------------------------------------------------------------------1000
Caution:
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Flash programming and erasure are not supported for system clock frequencies below 20 kHz, above 20 MHz, or outside of the device operating
frequency range. The Flash Frequency High and Low Byte registers must
be loaded with the correct value to insure proper Flash programming and
erase operations.
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Flash Read Protection
The user code contained within the Flash memory can be protected from external access.
Programming the Flash Read Protect Option Bit prevents reading of user code by the
OCD or by using the Flash Controller Bypass mode. For more information, see Option
Bits on page 163 and On-Chip Debugger on page 171.
Flash Write/Erase Protection
Z8 Encore! XP® F0822 Series provides several levels of protection against accidental program and erasure of the Flash memory contents. This protection is provided by the Flash
Controller unlock mechanism, the Flash Sector Protect Register, and the Flash Write Protect option bit.
Flash Controller Unlock Mechanism
At Reset, the Flash Controller locks to prevent accidental program or erasure of the Flash
memory. To program or erase the Flash memory, the Flash controller must be unlocked.
After unlocking the Flash Controller, the Flash can be programmed or erased. Any value
written by user code to the Flash Control Register or Page Select Register out of sequence
locks the Flash Controller.
Follow the steps below to unlock the Flash Controller from user code:
1. Write 00H to the Flash Control Register to reset the Flash Controller.
2. Write the page to be programmed or erased to the Page Select Register.
3. Write the first unlock command 73H to the Flash Control Register.
4. Write the second unlock command 8CH to the Flash Control Register.
5. Re-write the page written in step 2 to the Page Select Register.
Flash Sector Protection
The Flash Sector Protect Register is configured to prevent sectors from being programmed
or erased. Once a sector is protected, it cannot be unprotected by user code. The Flash
Sector Protect Register is cleared after reset and any previously written protection values
is lost. User code must write this register in the initialization routine if enable sector
protection is desired.
The Flash Sector Protect Register shares its Register File address with the Page Select
Register. The Flash Sector Protect Register is accessed by writing the Flash Control
Register with 5EH. After the Flash Sector Protect Register is selected, it can be accessed
at the Page Select Register address. When the user code writes the Flash Sector Protect
Register, bits can only be set to 1. Sectors can be protected, but not unprotected, using register write operations. Writing a value other than 5EH to the Flash Control Register deselects the Flash Sector Protect Register and re-enables access to the Page Select Register.
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Follow the steps below to setup the Flash Sector Protect Register from user code:
1. Write 00H to the Flash Control Register to reset the Flash Controller.
2. Write 5EH to the Flash Control Register to select the Flash Sector Protect Register.
3. Read and/or write the Flash Sector Protect Register which is now at Register File
address FF9H.
4. Write 00H to the Flash Control Register to return the Flash Controller to its reset state.
Flash Write Protection Option Bit
The Flash Write Protect option bit can block all program and erase operations from user
code. For more information, see Option Bits on page 163.
Byte Programming
When the Flash Controller is unlocked, writes to Flash Memory from user code programs
a byte into the Flash if the address is located in the unlocked page. An erased Flash byte
contains all 1s (FFH). The programming operation is used to change bits from 1 to 0. To
change a Flash bit (or multiple bits) from zero to one requires a Page Erase or Mass Erase
operation.
Byte Programming is accomplished using the eZ8 CPU’s LDC or LDCI instructions.
Refer to eZ8 CPU Core User Manual (UM0128) for a description of the LDC and LDCI
instructions.
While the Flash Controller programs the Flash memory, the eZ8 CPU idles but the system
clock and on-chip peripherals continue to operate. Interrupts that occur when a Programming operation is in progress are serviced once the Programming operation is complete.
To exit Programming mode and lock the Flash Controller, write 00H to the Flash Control
Register.
User code cannot program Flash Memory on a page that is located in a protected sector.
When user code writes memory locations, only addresses located in the unlocked page are
programmed. Memory writes outside of the unlocked page are ignored.
Caution:
Each memory location must not be programmed more than twice before an
erase occurs.
Follow the steps below to program the Flash from user code:
1. Write 00H to the Flash Control Register to reset the Flash Controller.
2. Write the page of memory to be programmed to the Page Select Register.
3. Write the first unlock command 73H to the Flash Control Register.
4. Write the second unlock command 8CH to the Flash Control Register.
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5. Re-write the page written in step 2 to the Page Select Register.
6. Write Flash Memory using LDC or LDCI instructions to program the Flash.
7. Repeat step 6 to program additional memory locations on the same page.
8. Write 00H to the Flash Control Register to lock the Flash Controller.
Page Erase
Flash memory can be erased one page (512 bytes) at a time. Page Erasing the Flash
memory sets all bytes in that page to the value FFH. The Page Select Register identifies
the page to be erased. While the Flash Controller executes the Page Erase operation, the
eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. The eZ8
CPU resumes operation after the Page Erase operation completes. Interrupts that occur
when the Page Erase operation is in progress are serviced once the Page Erase operation is
complete. When the Page Erase operation is complete, the Flash Controller returns to its
locked state. Only pages located in unprotected sectors can be erased.
Follow the steps below to perform a Page Erase operation:
1. Write 00H to the Flash Control Register to reset the Flash Controller.
2. Write the page to be erased to the Page Select Register.
3. Write the first unlock command 73H to the Flash Control Register.
4. Write the second unlock command 8CH to the Flash Control Register.
5. Re-write the page written in step 2 to the Page Select Register.
6. Write the Page Erase command 95H to the Flash Control Register.
Mass Erase
The Flash memory cannot be Mass Erased by user code.
Flash Controller Bypass
The Flash Controller can be bypassed and the control signals for the Flash memory
brought out to the GPIO pins. Bypassing the Flash Controller allows faster Programming
algorithms by controlling the Flash programming signals directly.
Flash Controller Bypass is recommended for gang programming applications and large
volume customers who do not require in-circuit programming of the Flash memory.
For more information on bypassing the Flash Controller, refer to Third-Party Flash Programming Support for Z8 Encore! XP, available for download at www.zilog.com.
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Flash Controller Behavior in Debug Mode
The following changes in behavior of the Flash Controller occur when the Flash Controller is accessed using the OCD:
•
•
•
The Flash Write Protect option bit is ignored
•
•
Bits in the Flash Sector Protect Register can be written to 1 or 0
•
•
The Page Select Register is written when the Flash Controller is unlocked
The Flash Sector Protect Register is ignored for programming and erase operations
Programming operations are not limited to the page selected in the Page Select
Register
The second write of the Page Select Register to unlock the Flash Controller is not
necessary
The Mass Erase command is enabled
Flash Control Register Definitions
Flash Control Register
The Flash Control Register (Table 83) is used to unlock the Flash Controller for programming and erase operations, or to select the Flash Sector Protect Register. The Write-only
Flash Control Register shares its Register File address with the Read-only Flash Status
Register.
Table 83. Flash Control Register (FCTL)
BITS
7
6
5
4
3
FIELD
FCMD
RESET
0
R/W
W
ADDR
2
1
0
FF8H
FCMD—Flash Command
73H = First unlock command.
8CH = Second unlock command.
95H = Page erase command.
63H = Mass erase command
5EH = Flash Sector Protect Register select.
* All other commands, or any command out of sequence, lock the Flash Controller.
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Flash Status Register
The Flash Status Register (Table 84) indicates the current state of the Flash Controller.
This register can be read at any time. The Read-only Flash Status Register shares its Register File address with the Write-only Flash Control Register.
Table 84. Flash Status Register (FSTAT)
BITS
7
6
5
4
3
2
Reserved
FIELD
1
0
FSTAT
RESET
0
R/W
R
FF8H
ADDR
Reserved
These bits are reserved and must be 0.
FSTAT—Flash Controller Status
00_0000 = Flash Controller locked.
00_0001 = First unlock command received.
00_0010 = Second unlock command received.
00_0011 = Flash Controller unlocked.
00_0100 = Flash Sector Protect Register selected.
00_1xxx = Program operation in progress.
01_0xxx = Page erase operation in progress.
10_0xxx = Mass erase operation in progress.
Page Select Register
The Page Select (FPS) Register (Table 85) selects the Flash memory page to be erased or
programmed. Each Flash Page contains 512 bytes of Flash memory. During a Page Erase
operation, all Flash memory locations with the 7 most significant bits of the address given
by the PAGE field are erased to FFH.
The Page Select Register shares its Register File address with the Flash Sector Protect
Register. The Page Select Register cannot be accessed when the Flash Sector Protect
Register is enabled.
Table 85. Page Select Register (FPS)
BITS
FIELD
7
INFO_EN
RESET
6
5
4
3
PAGE
1
0
0
R/W
R/W
ADDR
FF9H
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INFO_EN—Information Area Enable
0 = Information Area is not selected.
1 = Information Area is selected. The Information area is mapped into the
Flash Memory address space at addresses FE00H through FFFFH.
PAGE—Page Select
This 7-bit field selects the Flash memory page for Programming and Page Erase
operations. Flash Memory Address[15:9] = PAGE[6:0].
Flash Sector Protect Register
The Flash Sector Protect Register (Table 86) protects Flash memory sectors from being
programmed or erased from user code. The Flash Sector Protect Register shares its
Register File address with the Page Select Register. The Flash Sector Protect Register can
be accessed only after writing the Flash Control Register with 5EH. User code can only
write bits in this register to 1 (bits cannot be cleared to 0 by user code).
Table 86. Flash Sector Protect Register (FPROT)
BITS
FIELD
7
6
5
4
3
2
1
0
SECT7
SECT6
SECT5
SECT4
SECT3
SECT2
SECT1
SECT0
0
RESET
R/W
R/W1
ADDR
FF9H
R/W1 = Register is accessible for Read operations. Register can be written to 1 only (using user code).
SECTn—Sector Protect
0 = Sector n can be programmed or erased from user code.
1 = Sector n is protected and cannot be programmed or erased from user code.
User code can only write bits from 0 to 1.
Flash Frequency High and Low Byte Registers
The Flash Frequency High and Low Byte Registers (Table 87 and Table 88) combine to
form a 16-bit value, FFREQ, to control timing for Flash program and erase operations.
The 16-bit Flash Frequency registers must be written with the system clock frequency in
kHz for Program and Erase operations. The Flash Frequency value is calculated using the
following equation:
System Clock Frequency
FFREQ[15:0] = { FFREQH[7:0],FFREQL[7:0] } = -----------------------------------------------------------------1000
Caution:
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Flash programming and erasure is not supported for system clock frequencies below 20 kHz, above 20 MHz, or outside of the valid operating
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frequency range for the device. The Flash Frequency High and Low Byte
Registers must be loaded with the correct value to insure proper program
and erase times.
Table 87. Flash Frequency High Byte Register (FFREQH)
BITS
7
6
5
4
3
FIELD
FFREQH
RESET
0
2
1
0
2
1
0
R/W
R/W
FFAH
ADDR
Table 88. Flash Frequency Low Byte Register (FFREQL)
BITS
7
6
5
4
3
FIELD
FFREQL
RESET
0
R/W
ADDR
R/W
FFBH
FFREQH and FFREQL—Flash Frequency High and Low Bytes
These 2 bytes, {FFREQH[7:0], FFREQL[7:0]}, contain the 16-bit Flash Frequency value.
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Option Bits
Option Bits allow user configuration of certain aspects of Z8 Encore! XP® F0822 Series
operation. The feature configuration data is stored in Flash Memory and read during
Reset. Features available for control through the Option Bits are:
•
•
•
•
Watchdog Timer time-out response selection–interrupt or Reset.
•
Voltage Brownout configuration-always enabled or disabled during STOP mode to
reduce STOP mode power consumption.
•
Oscillator mode selection-for high, medium, and low power crystal oscillators, or
external RC oscillator.
Watchdog Timer enabled at Reset.
The ability to prevent unwanted read access to user code in Flash Memory.
The ability to prevent accidental programming and erasure of all or a portion of the
user code in Flash Memory.
Operation
Option Bit Configuration By Reset
During any reset operation (System Reset, Reset, or Stop Mode Recovery), the Option
Bits are automatically read from the Flash Memory and written to Option Configuration
registers. The Option Configuration registers control operation of the devices within the
Z8 Encore! XP F0822 Series. Option Bit control is established before the device exits
Reset and the eZ8 CPU begins code execution. The Option Configuration registers are not
part of the Register File and are not accessible for read or write access. Each time the
Option Bits are programmed or erased, the device must be Reset for the change to take
place (Flash version only).
Option Bit Address Space
The first two bytes of Flash Memory at addresses 0000H (Table 89 on page 164) and
0001H (Table 90 on page 165) are reserved for the user programmable Option Bits. The
byte at Program Memory address 0000H configures user options. The byte at Flash Memory address 0001H is reserved for future use and must be left in its unprogrammed state.
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Flash Memory Address 0000H
Table 89. Option Bits at Flash Memory Address 0000H for 8K Series Flash Devices
BITS
FIELD
7
6
WDT_RES
WDT_AO
5
4
OSC_SEL[1:0]
2
1
0
VBO_AO
RP
Reserved
FWP
U
RESET
R/W
R/W
ADDR
3
Program Memory 0000H
Note: U = Unchanged by Reset. R/W = Read/Write.
WDT_RES—Watchdog Timer Reset
0 = Watchdog Timer time-out generates an interrupt request. Interrupts must be
globally enabled for the eZ8 CPU to acknowledge the interrupt request.
1 = Watchdog Timer time-out causes a Reset. This setting is the default for
unprogrammed (erased) Flash.
WDT_AO—Watchdog Timer Always On
0 = Watchdog Timer is automatically enabled upon application of system power.
Watchdog Timer can not be disabled.
1 = Watchdog Timer is enabled upon execution of the WDT instruction. Once enabled,
the Watchdog Timer can only be disabled by a Reset or Stop Mode Recovery.
This setting is the default for unprogrammed (erased) Flash.
OSC_SEL[1:0]—OSCILLATOR Mode Selection
00 = On-chip oscillator configured for use with external RC networks (
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