High Performance 8-Bit Microcontrollers
Z8 Encore! XP® F64xx
Series
Product Specification
PS019926-1114
Copyright ©2014 Zilog®, Inc. All rights reserved.
www.zilog.com
Z8 Encore! XP® F64xx Series
Product Specification
ii
Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
LIFE SUPPORT POLICY
ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
©2014 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
Z8, Z8 Encore!, Z8 Encore! XP and Z8 Encore! MC are trademarks or registered trademarks of Zilog, Inc.
All other product or service names are the property of their respective owners.
PS019926-1114
PRELIMINARY
Foreword
Z8 Encore! XP® F64xx Series
Product Specification
iii
Revision History
Each instance in the Revision History table reflects a change to this document from its previous revision. For more details, refer to the corresponding pages or appropriate links
listed in the table below.
Date
Revision
Level
Description
Page
Nov
2014
26
Corrected IPU Units value in DC Characteristics table to µA from incorrect mA. 203
Feb
2014
25
Added footnote to Z8 Encore! XP F64xx Series Ordering Matrix table specific to 64-pin LQFP packages.
Jan
2013
24
Restored 40-pin PDIP package to Signal and Pin Descriptions and Packag- 7, 286
ing chapters.
Feb
2012
23
Corrected formatting of IDDS section, Table 107; corrected language in the 202, 248
General Purpose RAM section of Appendix A;
Sep
2011
22
Revised Flash Sector Protect Register description; revised Packaging
chapter.
178, 286
Mar
2008
21
Changed title to Z8 Encore! XP F64xx Series.
All
Feb
2008
20
Changed Z8 Encore! XP 64K Series Flash Microcontrollers to Z8 Encore! 287, 234
XP F64xx Series Flash Microcontrollers. Deleted three sentences that mentioned Z8R642. Removed the 40 PDIP package. Added
ZENETSC0100ZACG to the end of the Ordering Information table.
Changed the flag status to unaffected for BIT, BSET, and BCLR in the eZ8
CPU Instruction Summary table.
Dec
2007
19
Updated Zilog logo, Disclaimer section, and implemented style guide.
All
Updated Table 113. Changed Z8 Encore! 64K Series to Z8 Encore! XP 64K
Series Flash Microcontrollers throughout the document.
Dec
2006
18
Updated Flash Memory Electrical Characteristics and Timing table and
Ordering Information chapter.
213, 287
Nov
2006
17
Updated Part Number Suffix Designations section.
292
PS019926-1114
PRELIMINARY
287
Revision History
Z8 Encore! XP® F64xx Series
Product Specification
iv
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiii
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
2
3
3
4
4
4
4
5
5
5
5
5
5
6
Signal and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
19
20
20
Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset and Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS019926-1114
PRELIMINARY
28
28
29
30
31
Table of Contents
Z8 Encore! XP® F64xx Series
Product Specification
v
Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode Recovery Using Watchdog Timer Time-Out . . . . . . . . . . . . . . . . .
Stop Mode Recovery Using a GPIO Port Pin Transition HALT . . . . . . . . . . . .
32
32
32
32
33
33
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Port Availability By Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
36
37
37
39
39
40
41
46
46
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Edge Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Port Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
47
49
49
49
50
50
51
51
51
53
54
55
56
58
60
60
61
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PS019926-1114
PRELIMINARY
Table of Contents
Z8 Encore! XP® F64xx Series
Product Specification
vi
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Output Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 Control 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
63
71
72
72
72
74
75
76
77
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer Reload Upper, High and Low Byte Registers . . . . . . . . . . . .
80
80
81
81
82
83
83
85
Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Transmitting Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Transmitting Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . 90
Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Receiving Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . 92
Clear To Send (CTS) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Multiprocessor (9-Bit) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
UART Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
UART Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
UART Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
UART Status 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
UART Control 0 and Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
UART Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . 105
Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
PS019926-1114
PRELIMINARY
Table of Contents
Z8 Encore! XP® F64xx Series
Product Specification
vii
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Infrared Encoder/Decoder Control Register Definitions . . . . . . . . . . . . . . . . . . . .
109
110
111
112
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Clock Phase and Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multimaster Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . .
113
113
115
115
116
118
119
119
120
120
121
121
122
123
125
126
126
I2C Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDA and SCL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Control of I2C Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Write and Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Only Transaction with a 7-bit Address . . . . . . . . . . . . . . . . . . . . . . .
Write Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Only Transaction with a 10-bit Address . . . . . . . . . . . . . . . . . . . . . .
Write Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . .
128
128
129
130
130
131
132
132
133
133
135
136
138
139
141
141
142
144
145
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PRELIMINARY
Table of Contents
Z8 Encore! XP® F64xx Series
Product Specification
viii
I2C Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
I2C Diagnostic Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuring DMA0 and DMA1 for Data Transfer . . . . . . . . . . . . . . . . . . . . .
DMA_ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuring DMA_ADC for Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAx Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAx I/O Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAx Address High Nibble Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAx Start/Current Address Low Byte Register . . . . . . . . . . . . . . . . . . . . . .
DMAx End Address Low Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA_ADC Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA_ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA_ADC Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
150
150
150
151
152
152
153
154
155
156
156
157
158
159
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Shot Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Control of the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
161
161
163
163
163
164
165
165
165
167
168
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Using the Flash Frequency Registers . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Read Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Write/Erase Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Controller Behavior in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
169
170
171
171
172
172
173
174
174
174
175
175
175
PS019926-1114
PRELIMINARY
Table of Contents
Z8 Encore! XP® F64xx Series
Product Specification
ix
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . .
177
177
178
179
Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Option Bit Configuration By Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Address 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Address 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
180
180
180
180
181
182
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Autobaud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
183
183
184
184
185
186
186
187
187
188
193
193
194
On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Operation with an External RC Network . . . . . . . . . . . . . . . . . . . . . . . .
196
196
196
198
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . . . . .
General-Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
200
200
202
211
216
217
218
219
220
221
222
223
PS019926-1114
PRELIMINARY
Table of Contents
Z8 Encore! XP® F64xx Series
Product Specification
x
eZ8 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ8 CPU Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
225
225
226
227
229
230
234
243
Op Code Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Appendix A. Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . .
Inter-Integrated Circuit (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
248
248
248
256
261
263
266
266
270
274
282
284
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Part Number Suffix Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
PS019926-1114
PRELIMINARY
Table of Contents
Z8 Encore! XP® F64xx Series
Product Specification
xi
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
PS019926-1114
Z8 Encore! XP F64xx Series Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Z8 Encore! XP F64xx Series in 40-Pin Dual Inline Package (PDIP) . . . . . . 8
Z8 Encore! XP F64xx Series in 44-Pin Plastic Leaded Chip Carrier (PLCC) 9
Z8 Encore! XP F64xx Series in 44-Pin Low-Profile Quad Flat
Package (LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Z8 Encore! XP F64xx Series in 64-Pin Low-Profile Quad Flat
Package (LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Z8 Encore! XP F64xx Series in 68-Pin Plastic Leaded Chip
Carrier (PLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Z8 Encore! XP F64xx Series in 80-Pin Quad Flat Package (QFP) . . . . . . . 13
Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . . . . . . 89
UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . . . . . . 89
UART Asynchronous Multiprocessor Mode Data Format . . . . . . . . . . . . . 93
UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity) . 95
UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . . . . . . 97
Infrared Data Communication System Block Diagram . . . . . . . . . . . . . . 109
Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Infrared Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
SPI Configured as a Master in a Single-Master, Single-Slave System . . . 113
SPI Configured as a Master in a Single-Master, Multiple-Slave System . 114
SPI Configured as a Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
SPI Timing When PHASE is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
SPI Timing When PHASE is 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
I2C Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7-Bit Address Only Transaction Format . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7-Bit Addressed Slave Data Transfer Format . . . . . . . . . . . . . . . . . . . . . . 134
10-Bit Address Only Transaction Format . . . . . . . . . . . . . . . . . . . . . . . . . 135
PRELIMINARY
List of Figures
Z8 Encore! XP® F64xx Series
Product Specification
xii
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
PS019926-1114
10-Bit Addressed Slave Data Transfer Format . . . . . . . . . . . . . . . . . . . . . 136
Receive Data Transfer Format for a 7-Bit Addressed Slave . . . . . . . . . . . 138
Receive Data Format for a 10-Bit Addressed Slave . . . . . . . . . . . . . . . . . 139
Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . 162
Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface,
#1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface,
#2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Recommended 20 MHz Crystal Oscillator Configuration . . . . . . . . . . . . . 197
Connecting the On-Chip Oscillator to an External RC Network . . . . . . . . 198
Typical RC Oscillator Frequency as a Function of the External
Capacitance with a 45 kΩ Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Typical Active Mode IDD vs. System Clock Frequency . . . . . . . . . . . . . . 205
Maximum Active Mode IDD vs. System Clock Frequency . . . . . . . . . . . . 206
Typical Halt Mode IDD vs. System Clock Frequency . . . . . . . . . . . . . . . . 207
Maximum Halt Mode Icc vs. System Clock Frequency . . . . . . . . . . . . . . 208
Maximum Stop Mode IDD with VBO Enabled vs. Power Supply
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Maximum Stop Mode IDD with VBO Disabled vs. Power Supply
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Analog-to-Digital Converter Frequency Response . . . . . . . . . . . . . . . . . . 215
Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
UART Timing without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Op Code Map Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
First Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Second Op Code Map after 1Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
PRELIMINARY
List of Figures
Z8 Encore! XP® F64xx Series
Product Specification
xiii
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
PS019926-1114
Z8 Encore! XP F64xx Series Part Selection Guide . . . . . . . . . . . . . . . . . . . . 2
Z8 Encore! XP F64xx Series Package Options . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pin Characteristics of the Z8 Encore! XP F64xx Series . . . . . . . . . . . . . . . 17
Z8 Encore! XP F64xx Series Program Memory Maps . . . . . . . . . . . . . . . . 19
Z8 Encore! XP F64xx Series Information Area Map . . . . . . . . . . . . . . . . . 21
Z8 Encore! XP F64xx Series Register File Address Map . . . . . . . . . . . . . . 22
Reset and Stop Mode Recovery Characteristics and Latency . . . . . . . . . . . 28
Reset Sources and Resulting Reset Type . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Stop Mode Recovery Sources and Resulting Action . . . . . . . . . . . . . . . . . . 33
Port Availability by Device and Package Type . . . . . . . . . . . . . . . . . . . . . . 36
Port Alternate Function Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
GPIO Port Registers and Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Port A–H GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . . 40
Port A–H Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Port A–H Data Direction Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Port A–H Alternate Function Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . 42
Port A–H Output Control Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Port A–H High Drive Enable Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . 44
Port A–H Stop Mode Recovery Source Enable Subregisters . . . . . . . . . . . 45
Port A–H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Port A–H Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . . 55
IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . . . 56
IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . . 57
IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . . . 57
IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PRELIMINARY
List of Tables
Z8 Encore! XP® F64xx Series
Product Specification
xiv
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
PS019926-1114
IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . . . . 58
IRQ2 Enable Low Bit Register (IRQ2ENL) . . . . . . . . . . . . . . . . . . . . . . . . 59
Interrupt Edge Select Register (IRQES) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Interrupt Port Select Register (IRQPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Timer 0–3 High Byte Register (TxH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Timer 0–3 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Timer 0–3 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . . . . . 74
Timer 0–3 Reload Low Byte Register (TxRL) . . . . . . . . . . . . . . . . . . . . . . 74
Timer 0–3 PWM High Byte Register (TxPWMH) . . . . . . . . . . . . . . . . . . . 75
Timer 0–3 PWM Low Byte Register (TxPWML) . . . . . . . . . . . . . . . . . . . . 75
Timer 0–3 Control 0 Register (TxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Timer 0–3 Control 1 Register (TxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Watchdog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . . . . . . 81
Watchdog Timer Control Register (WDTCTL) . . . . . . . . . . . . . . . . . . . . . 84
Watchdog Timer Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Watchdog Timer Reload Upper Byte Register (WDTU) . . . . . . . . . . . . . . 85
Watchdog Timer Reload High Byte Register (WDTH) . . . . . . . . . . . . . . . 86
Watchdog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . . . . . 86
UART Transmit Data Register (UxTXD) . . . . . . . . . . . . . . . . . . . . . . . . . . 99
UART Receive Data Register (UxRXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
UART Status 0 Register (UxSTAT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
UART Status 1 Register (UxSTAT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
UART Control 0 Register (UxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
UART Control 1 Register (UxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
UART Address Compare Register (UxADDR) . . . . . . . . . . . . . . . . . . . . . 105
UART Baud Rate High Byte Register (UxBRH) . . . . . . . . . . . . . . . . . . . 106
UART Baud Rate Low Byte Register (UxBRL) . . . . . . . . . . . . . . . . . . . . 106
UART Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation . . . 117
SPI Data Register (SPIDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SPI Control Register (SPICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SPI Status Register (SPISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SPI Mode Register (SPIMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SPI Diagnostic State Register (SPIDST) . . . . . . . . . . . . . . . . . . . . . . . . . . 126
SPI Baud Rate High Byte Register (SPIBRH) . . . . . . . . . . . . . . . . . . . . . 127
PRELIMINARY
List of Tables
Z8 Encore! XP® F64xx Series
Product Specification
xv
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
PS019926-1114
SPI Baud Rate Low Byte Register (SPIBRL) . . . . . . . . . . . . . . . . . . . . . .
I2C Data Register (I2CDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Status Register (I2CSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Control Register (I2CCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Baud Rate Low Byte Register (I2CBRL) . . . . . . . . . . . . . . . . . . . . . .
I2C Baud Rate High Byte Register (I2CBRH) . . . . . . . . . . . . . . . . . . . . .
I2C Diagnostic State Register (I2CDST) . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Diagnostic Control Register (I2CDIAG) . . . . . . . . . . . . . . . . . . . . . .
DMAx Control Register (DMAxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAx I/O Address Register (DMAxIO) . . . . . . . . . . . . . . . . . . . . . . . . .
DMAx Address High Nibble Register (DMAxH) . . . . . . . . . . . . . . . . . . .
DMAx Start/Current Address Low Byte Register (DMAxSTART) . . . . .
DMAx End Address Low Byte Register (DMAxEND) . . . . . . . . . . . . . .
DMA_ADC Register File Address Example . . . . . . . . . . . . . . . . . . . . . . .
DMA_ADC Control Register (DMAACTL) . . . . . . . . . . . . . . . . . . . . . . .
DMA_ADC Address Register (DMAA_ADDR) . . . . . . . . . . . . . . . . . . .
DMA_ADC Status Register (DMAA_STAT) . . . . . . . . . . . . . . . . . . . . . .
ADC Control Register (ADCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . . . . .
ADC Data Low Bits Register (ADCD_L) . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z8 Encore! XP F64xx Series Information Area Map . . . . . . . . . . . . . . . .
Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Sector Protect Register (FPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Frequency High Byte Register (FFREQH) . . . . . . . . . . . . . . . . . . .
Flash Frequency Low Byte Register (FFREQL) . . . . . . . . . . . . . . . . . . . .
Flash Option Bits At Flash Memory Address 0000h . . . . . . . . . . . . . . . . .
Options Bits at Flash Memory Address 0001h . . . . . . . . . . . . . . . . . . . . .
OCD Baud-Rate Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Control Register (OCDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Status Register (OCDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Crystal Oscillator Specifications (20 MHz Operation) . . .
PRELIMINARY
127
142
142
144
146
146
147
149
153
154
155
156
156
157
158
158
159
165
167
168
169
169
171
176
177
178
178
179
179
181
182
186
189
193
194
197
List of Tables
Z8 Encore! XP® F64xx Series
Product Specification
xvi
Table 106. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 107. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 108. Power-On Reset and Voltage Brown-Out Electrical Characteristics
and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 109. Reset and Stop Mode Recovery Pin Timing . . . . . . . . . . . . . . . . . . . . . . .
Table 110. External RC Oscillator Electrical Characteristics and Timing . . . . . . . . .
Table 111. Flash Memory Electrical Characteristics and Timing . . . . . . . . . . . . . . . .
Table 112. Watchdog Timer Electrical Characteristics and Timing . . . . . . . . . . . . . .
Table 113. Analog-to-Digital Converter Electrical Characteristics and Timing . . . . .
Table 114. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 115. GPIO Port Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 116. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 117. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 118. SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 119. SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 120. I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 121. UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 122. UART Timing without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 123. Assembly Language Syntax Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 124. Assembly Language Syntax Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 125. Notational Shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 126. Additional Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 127. Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 128. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 129. Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 130. Block Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 131. CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 132. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 133. Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 134. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 135. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 136. eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 137. Op Code Map Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 138. Timer 0–3 High Byte Register (TxH) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 139. Timer 0–3 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 140. Timer 0–3 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . . . .
PS019926-1114
PRELIMINARY
200
202
211
212
212
213
213
214
216
217
218
219
220
221
222
223
224
226
227
227
228
229
230
231
231
232
232
233
233
234
234
244
248
249
249
List of Tables
Z8 Encore! XP® F64xx Series
Product Specification
xvii
Table 141.
Table 142.
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
Table 149.
Table 150.
Table 151.
Table 152.
Table 153.
Table 154.
Table 155.
Table 156.
Table 157.
Table 158.
Table 159.
Table 160.
Table 161.
Table 162.
Table 163.
Table 164.
Table 165.
Table 166.
Table 167.
Table 168.
Table 169.
Table 170.
Table 171.
Table 172.
Table 173.
Table 174.
Table 175.
Table 176.
PS019926-1114
Timer 0–3 Reload Low Byte Register (TxRL) . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 PWM High Byte Register (TxPWMH) . . . . . . . . . . . . . . . . . .
Timer 0–3 PWM Low Byte Register (TxPWML) . . . . . . . . . . . . . . . . . . .
Timer 0–3 Control 0 Register (TxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 Control 1 Register (TxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 High Byte Register (TxH) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 Reload Low Byte Register (TxRL) . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 PWM High Byte Register (TxPWMH) . . . . . . . . . . . . . . . . . .
Timer 0–3 PWM Low Byte Register (TxPWML) . . . . . . . . . . . . . . . . . . .
Timer 0–3 Control 0 Register (TxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 Control 1 Register (TxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 High Byte Register (TxH) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 Reload Low Byte Register (TxRL) . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 PWM High Byte Register (TxPWMH) . . . . . . . . . . . . . . . . . .
Timer 0–3 PWM Low Byte Register (TxPWML) . . . . . . . . . . . . . . . . . . .
Timer 0–3 Control 0 Register (TxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 Control 1 Register (TxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 High Byte Register (TxH) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 Reload Low Byte Register (TxRL) . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 PWM High Byte Register (TxPWMH) . . . . . . . . . . . . . . . . . .
Timer 0–3 PWM Low Byte Register (TxPWML) . . . . . . . . . . . . . . . . . . .
Timer 0–3 Control 0 Register (TxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0–3 Control 1 Register (TxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . .
UART Transmit Data Register (UxTXD) . . . . . . . . . . . . . . . . . . . . . . . . .
UART Receive Data Register (UxRXD) . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Status 0 Register (UxSTAT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Control 0 Register (UxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Control 1 Register (UxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Status 1 Register (UxSTAT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Address Compare Register (UxADDR) . . . . . . . . . . . . . . . . . . . . .
PRELIMINARY
249
249
250
250
250
250
251
251
251
251
252
252
252
252
253
253
253
253
254
254
254
254
255
255
255
255
256
256
256
257
257
257
257
258
258
258
List of Tables
Z8 Encore! XP® F64xx Series
Product Specification
xviii
Table 177.
Table 178.
Table 179.
Table 180.
Table 181.
Table 182.
Table 183.
Table 184.
Table 185.
Table 186.
Table 187.
Table 188.
Table 189.
Table 190.
Table 191.
Table 192.
Table 193.
Table 194.
Table 195.
Table 196.
Table 197.
Table 198.
Table 199.
Table 200.
Table 201.
Table 202.
Table 203.
Table 204.
Table 205.
Table 206.
Table 207.
Table 208.
Table 209.
Table 210.
Table 211.
Table 212.
PS019926-1114
UART Baud Rate High Byte Register (UxBRH) . . . . . . . . . . . . . . . . . . .
UART Baud Rate Low Byte Register (UxBRL) . . . . . . . . . . . . . . . . . . . .
UART Transmit Data Register (UxTXD) . . . . . . . . . . . . . . . . . . . . . . . . .
UART Receive Data Register (UxRXD) . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Status 0 Register (UxSTAT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Control 0 Register (UxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Control 1 Register (UxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Status 1 Register (UxSTAT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Address Compare Register (UxADDR) . . . . . . . . . . . . . . . . . . . . .
UART Baud Rate High Byte Register (UxBRH) . . . . . . . . . . . . . . . . . . .
UART Baud Rate Low Byte Register (UxBRL) . . . . . . . . . . . . . . . . . . . .
I2C Data Register (I2CDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Status Register (I2CSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Control Register (I2CCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Baud Rate High Byte Register (I2CBRH) . . . . . . . . . . . . . . . . . . . . .
I2C Baud Rate Low Byte Register (I2CBRL) . . . . . . . . . . . . . . . . . . . . . .
I2C Diagnostic State Register (I2CDST) . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Diagnostic Control Register (I2CDIAG) . . . . . . . . . . . . . . . . . . . . . .
SPI Data Register (SPIDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Control Register (SPICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Status Register (SPISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Mode Register (SPIMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Diagnostic State Register (SPIDST) . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Baud Rate High Byte Register (SPIBRH) . . . . . . . . . . . . . . . . . . . . .
SPI Baud Rate Low Byte Register (SPIBRL) . . . . . . . . . . . . . . . . . . . . . .
ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . . . . .
ADC Data Low Bits Register (ADCD_L) . . . . . . . . . . . . . . . . . . . . . . . . .
DMAx Control Register (DMAxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAx I/O Address Register (DMAxIO) . . . . . . . . . . . . . . . . . . . . . . . . .
DMAx Address High Nibble Register (DMAxH) . . . . . . . . . . . . . . . . . . .
DMAx Start/Current Address Low Byte Register (DMAxSTART) . . . . .
DMAx End Address Low Byte Register (DMAxEND) . . . . . . . . . . . . . .
DMAx Control Register (DMAxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAx I/O Address Register (DMAxIO) . . . . . . . . . . . . . . . . . . . . . . . . .
DMAx Address High Nibble Register (DMAxH) . . . . . . . . . . . . . . . . . . .
DMAx Start/Current Address Low Byte Register (DMAxSTART) . . . . .
PRELIMINARY
258
259
259
259
259
260
260
260
260
261
261
261
262
262
262
262
263
263
263
264
264
264
265
265
265
266
266
267
267
267
267
268
268
268
269
269
List of Tables
Z8 Encore! XP® F64xx Series
Product Specification
xix
Table 213.
Table 214.
Table 215.
Table 216.
Table 217.
Table 218.
Table 219.
Table 220.
Table 221.
Table 222.
Table 223.
Table 224.
Table 225.
Table 226.
Table 227.
Table 228.
Table 229.
Table 230.
Table 231.
Table 232.
Table 233.
Table 234.
Table 235.
Table 236.
Table 237.
Table 238.
Table 239.
Table 240.
Table 241.
Table 242.
Table 243.
Table 244.
Table 245.
Table 246.
Table 247.
Table 248.
PS019926-1114
DMAx End Address Low Byte Register (DMAxEND) . . . . . . . . . . . . . .
DMA_ADC Address Register (DMAA_ADDR) . . . . . . . . . . . . . . . . . . .
DMA_ADC Control Register (DMAACTL) . . . . . . . . . . . . . . . . . . . . . . .
DMA_ADC Status Register (DMAA_STAT) . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . .
IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . .
IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . . .
IRQ2 Enable Low Bit Register (IRQ2ENL) . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Edge Select Register (IRQES) . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Port Select Register (IRQPS) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . .
Port A–H Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . .
Port A–H Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . .
Port A–H Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . .
Port A–H Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . .
Port A–H Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . .
PRELIMINARY
269
269
270
270
270
271
271
271
271
272
272
272
272
273
273
273
274
274
274
275
275
275
275
276
276
276
276
277
277
277
277
278
278
278
278
279
List of Tables
Z8 Encore! XP® F64xx Series
Product Specification
xx
Table 249.
Table 250.
Table 251.
Table 252.
Table 253.
Table 254.
Table 255.
Table 256.
Table 257.
Table 258.
Table 259.
Table 260.
Table 261.
Table 262.
Table 263.
Table 264.
Table 265.
Table 266.
Table 267.
Table 268.
Table 269.
Table 270.
Table 271.
PS019926-1114
Port A–H GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . .
Port A–H Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . .
Port A–H Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . .
Port A–H Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer Control Register (WDTCTL) . . . . . . . . . . . . . . . . . . . .
Watchdog Timer Reload Upper Byte Register (WDTU) . . . . . . . . . . . . .
Watchdog Timer Reload High Byte Register (WDTH) . . . . . . . . . . . . . .
Watchdog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . . . .
Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Frequency High Byte Register (FFREQH) . . . . . . . . . . . . . . . . . . .
Flash Frequency Low Byte Register (FFREQL) . . . . . . . . . . . . . . . . . . . .
Flash Sector Protect Register (FPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z8 Encore! XP F64xx Series Ordering Matrix . . . . . . . . . . . . . . . . . . . . .
PRELIMINARY
279
279
279
280
280
280
280
281
281
281
281
282
282
282
283
283
284
284
284
285
285
285
287
List of Tables
Z8 Encore! XP® F64xx Series
Product Specification
1
Introduction
Zilog’s Z8 Encore! XP F64xx Series MCU family of products are a line of Zilog microcontroller products based upon the 8-bit eZ8 CPU. The Z8 Encore! XP F64xx Series adds
Flash memory to Zilog’s extensive line of 8-bit microcontrollers. The Flash in-circuit programming capability allows for faster development time and program changes in the field.
The new eZ8 CPU is upward-compatible with existing Z8 instructions. The rich-peripheral set of the Z8 Encore! XP F64xx Series makes it suitable for a variety of applications
including motor control, security systems, home appliances, personal electronic devices,
and sensors.
Features
The features of Z8 Encore! XP F64xx Series include:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PS019926-1114
20 MHz eZ8 CPU
Up to 64 KB Flash with in-circuit programming capability
Up to 4 KB register RAM
12-channel, 10-bit Analog-to-Digital Converter (ADC)
Two full-duplex 9-bit UARTs with bus transceiver Driver Enable control
Inter-integrated circuit (I2C)
Serial Peripheral Interface (SPI)
Two Infrared Data Association (IrDA)-compliant infrared encoder/decoders
Up to four 16-bit timers with capture, compare and PWM capability
Watchdog Timer (WDT) with internal RC oscillator
Three-channel DMA
Up to 60 input/output (I/O) pins
24 interrupts with configurable priority
On-Chip Debugger
Voltage Brown-Out (VBO) Protection
Power-On Reset (POR)
Operating voltage of 3.0 V to 3.6 V with 5 V-tolerant inputs
0°C to +70°C, –40°C to +105°C, and –40°C to +125°C operating temperature ranges
PRELIMINARY
Introduction
Z8 Encore! XP® F64xx Series
Product Specification
2
Part Selection Guide
Table 1 identifies the basic features and package styles available for each device within the
Z8 Encore! XP product line.
Table 1. Z8 Encore! XP F64xx Series Part Selection Guide
Part
Number
Flash RAM
(KB) (KB)
I/O
40-/
16-bit
44-Pin 64/68-Pin 80-Pin
Timers
ADC
UARTs
with PWM Inputs with IrDA I2C SPI Package Package Package
Z8F1621
16
2
31
3
8
2
1
1
Z8F1622
16
2
46
4
12
2
1
1
Z8F2421
24
2
31
3
8
2
1
1
Z8F2422
24
2
46
4
12
2
1
1
Z8F3221
32
2
31
3
8
2
1
1
Z8F3222
32
2
46
4
12
2
1
1
Z8F4821
48
4
31
3
8
2
1
1
Z8F4822
48
4
46
4
12
2
1
1
Z8F4823
48
4
60
4
12
2
1
1
Z8F6421
64
4
31
3
8
2
1
1
Z8F6422
64
4
46
4
12
2
1
1
Z8F6423
64
4
60
4
12
2
1
1
X
X
X
X
X
X
X
X
X
X
X
X
Note: For die form sales, contact your local Zilog Sales Office.
PS019926-1114
PRELIMINARY
Part Selection Guide
Z8 Encore! XP® F64xx Series
Product Specification
3
Block Diagram
Figure 1 displays the architecture of the Z8 Encore! XP F64xx Series.
XTAL/RC
Oscillator
On-Chip
Debugger
eZ8TM
CPU
Interrupt
Controller
System
Clock
POR/VBO
and Reset
Controller
WDT with
RC Oscillator
Memory Busses
Register Bus
Timers
UARTs
I2C
SPI
ADC
IrDA
DMA
Flash
Controller
RAM
Controller
Flash
Memory
RAM
GPIO
Figure 1. Z8 Encore! XP F64xx Series Block Diagram
CPU and Peripheral Overview
The latest 8-bit eZ8 CPU meets the continuing demand for faster and more code-efficient
microcontrollers. The eZ8 CPU executes a superset of the original Z8 instruction set.
eZ8 CPU features include:
•
PS019926-1114
Direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required program memory
PRELIMINARY
Block Diagram
Z8 Encore! XP® F64xx Series
Product Specification
4
•
Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks
•
•
•
Compatible with existing Z8 code
•
•
Pipelined instruction fetch and execution
•
•
•
•
New instructions support 12-bit linear addressing of the register file
Expanded internal register file allows access of up to 4 KB
New instructions improve execution efficiency for code developed using higher-level
programming languages, including C
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
LDCI, LEA, MULT and SRL
Up to 10 MIPS operation
C-Compiler friendly
2 to 9 clock cycles per instruction
For more information about the eZ8 CPU, refer to the eZ8 CPU Core User Manual
(UM0128), which is available for download on www.zilog.com.
General-Purpose Input/Output
The Z8 Encore! XP F64xx Series features seven 8-bit ports (ports A–G) and one 4-bit port
(Port H) for general-purpose input/output (GPIO). Each pin is individually programmable.
All ports (except B and H) support 5 V-tolerant inputs.
Flash Controller
The Flash Controller programs and erases the contents of Flash memory.
10-Bit Analog-to-Digital Converter
The Analog-to-Digital Converter converts an analog input signal to a 10-bit binary number. The ADC accepts inputs from up to 12 different analog input sources.
UARTs
Each UART is full-duplex and capable of handling asynchronous data transfers. The
UARTs support 8- and 9-bit data modes, selectable parity, and an efficient bus transceiver
Driver Enable signal for controlling a multitransceiver bus, such as RS-485.
PS019926-1114
PRELIMINARY
CPU and Peripheral Overview
Z8 Encore! XP® F64xx Series
Product Specification
5
I2C
The I2C controller makes the Z8 Encore! XP F64xx Series compatible with the I2C protocol. The I2C controller consists of two bidirectional bus lines, a serial data (SDA) line and
a serial clock (SCL) line.
Serial Peripheral Interface
The serial peripheral interface allows the Z8 Encore! XP F64xx Series to exchange data
between other peripheral devices such as EEPROMs, A/D converters and ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire
interface.
Timers
Up to four 16-bit reloadable timers can be used for timing/counting events or for motor
control operations. These timers provide a 16-bit programmable reload counter and operate in One-Shot, Continuous, Gated, Capture, Compare, Capture/Compare and PWM
modes. Only 3 timers (Timer 0–2) are available in the 44-pin package.
Interrupt Controller
The Z8 Encore! XP F64xx Series products support up to 24 interrupts. These interrupts
consist of 12 internal and 12 GPIO pins. The interrupts have 3 levels of programmable
interrupt priority.
Reset Controller
The Z8 Encore! XP F64xx Series can be reset using the RESET pin, Power-On Reset,
Watchdog Timer, Stop Mode exit, or Voltage Brown-Out (VBO) warning signal.
On-Chip Debugger
The Z8 Encore! XP F64xx Series features an integrated On-Chip Debugger. The OCD
provides a rich set of debugging capabilities, such as reading and writing registers, programming the Flash, setting breakpoints and executing code. A single-pin interface provides communication to the OCD.
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DMA Controller
The Z8 Encore! XP F64xx Series feature three channels of DMA. Two of the channels are
for register RAM to and from I/O operations. The third channel automatically controls the
transfer of data from the ADC to the memory.
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Signal and Pin Descriptions
The Z8 Encore! XP F64xx Series product are available in a variety of packages styles and
pin configurations. This chapter describes the signals and available pin configurations for
each of the package styles. For information about physical package specifications, see the
Packaging chapter on page 286.
Available Packages
Table 2 identifies the package styles that are available for each device within the Z8
Encore! XP F64xx Series product line.
Table 2. Z8 Encore! XP F64xx Series Package Options
Part Number
Z8F1621
40-Pin
PDIP
44-Pin
LQFP
44-Pin
PLCC
X
X
X
Z8F1622
Z8F2421
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Z8F4822
Z8F4823
Z8F6421
X
X
X
X
Z8F6422
X
Z8F6423
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80-Pin
QFP
X
Z8F3222
Z8F4821
68-Pin
PLCC
X
Z8F2422
Z8F3221
64-Pin
LQFP
X
X
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Pin Configurations
Figures 2 through 7 display the pin configurations for all of the packages available in the
Z8 Encore! XP F64xx Series. For signal descriptions, see Table 3 on page 14.
PD4/RXD1
1
40
PD5/TXD1
PD3/DE1
PC4/MOSI
PC5/MISO
PA3/CTS0
PA2/DE0
PA4/RXD0
PA5/TXD0
PA6/SCL
5
35
PA1/T0OUT
PA0/T0IN
PC2/SS
RESET
VDD
PC3/SCK
VSS
VDD
10
30
VSS
PD1
PC1/T1OUT
PC0/T1IN
15
25
AVSS
VREF
PB2/ANA2
PB0/ANA0
PB1/ANA1
PB4/ANA4
PB5/ANA5
PC6/T2IN
DBG
PD0
XOUT
XIN
AVDD
PA7/SDA
PD6/CTS1
PB3/ANA3
20
21
PB7/ANA7
PB6/ANA6
Figure 2. Z8 Encore! XP F64xx Series in 40-Pin Dual Inline Package (PDIP)
Note: Timer 3 and T2OUT are not supported in the 40-pin PDIP package.
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PA0/T0IN
1
PA6/SCL
PA4/RXD0
PA5/TXD0
PD3/DE1
PD4/RXD1
PD5/TXD1
PC4/MOSI
PA3/CTS0
PC5/MISO
PA1/T0OUT
PA2/DE0
9
40
39
7
PD6/CTS1
PD2
PC3/SCK
VSS
VDD
PC2/SS
RESET
VDD
VSS
PD1
34
12
PC7/T2OUT
PC6/T2IN
PD0
XOUT
DBG
PC1/T1OUT
XIN
29
28
PB2/ANA2
VREF
PB7/ANA7
PB3/ANA3
PB6/ANA6
PB4/ANA4
PB5/ANA5
23
PC0/T1IN
VSS
AVSS
17
18
AVDD
PB0/ANA0
PB1/ANA1
VDD
PA7/SDA
Figure 3. Z8 Encore! XP F64xx Series in 44-Pin Plastic Leaded Chip Carrier (PLCC)
Note: Timer 3 is not available in the 44-pin PLCC package.
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PA0/T0IN
33
34
PA6/SCL
PA4/RXD0
PA5/TXD0
PD3/DE1
PD4/RXD1
PD5/TXD1
PC4/MOSI
PA3/CTS0
PC5/MISO
PA1/T0OUT
PA2/DE0
10
23
22
28
PD6/CTS1
PD2
PC2/SS
RESET
VDD
VSS
PD1
PC3/SCK
VSS
39
17
VDD
PC7/T2OUT
PC6/T2IN
PD0
XOUT
XIN
DBG
12
11
PB2/ANA2
VREF
PB7/ANA7
PB3/ANA3
PB6/ANA6
6
PC1/T1OUT
PC0/T1IN
VSS
AVSS
1
PB4/ANA4
PB5/ANA5
44
AVDD
PB0/ANA0
PB1/ANA1
VDD
PA7/SDA
Figure 4. Z8 Encore! XP F64xx Series in 44-Pin Low-Profile Quad Flat Package (LQFP)
Note: Timer 3 is not available in the 44-pin LQFP package.
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PA0/T0IN
PA4/RXD0
PA5/TXD0
PA6/SCL
VDD
VSS
PC4/MOSI
PD4/RXD1
PD5/TXD1
VDD
PF7
PC5/MISO
PD3/DE1
PA3/CTS0
VSS
PA1/T0OUT
PA2/DE0
11
40
48
49
33
32
PD6/CTS1
PD2
PC2/SS
RESET
VDD
PE4
PE3
VSS
PC3/SCK
PD7/RCOUT
VSS
PE5
PE6
25
56
PE7
VDD
PE2
PE1
PE0
VSS
PD1/T3OUT
PG3
VDD
PC7/T2OUT
PC6/T2IN
DBG
17
16
PH3/ANA11
VREF
PB6/ANA6
PB7/ANA7
PB3/ANA3
PB2/ANA2
PH2/ANA10
PB4/ANA4
PB5/ANA5
PB1/ANA1
8
PC1/T1OUT
PC0/T1IN
AVSS
1
PH1/ANA9
PB0/ANA0
64
VSS
AVDD
PH0/ANA8
PD0/T3IN
XOUT
XIN
PA7/SDA
Figure 5. Z8 Encore! XP F64xx Series in 64-Pin Low-Profile Quad Flat Package (LQFP)
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PA0/T0IN
VSS
PA4/RXD0
PA5/TXD0
PA6/SCL
VDD
PC4/MOSI
VDD
PD4/RXD1
PD5/TXD1
PF7
PC5/MISO
PD3/DE1
VDD
PA3/CTS0
VSS
PA1/T0OUT
PA2/DE0
12
1
61
60
10
PD6/CTS1
PD2
PC2/SS
RESET
VDD
PC3/SCK
PD7/RCOUT
VSS
PE5
PE6
PE4
PE3
VSS
VDD
PG3
VDD
PC7/T2OUT
PC6/T2IN
DBG
44
43
PH3/ANA11
VREF
AVSS
PB6/ANA6
PB7/ANA7
PB3/ANA3
PB2/ANA2
PH2/ANA10
PB4/ANA4
PB5/ANA5
PB1/ANA1
PH1/ANA9
PB0/ANA0
35
PC1/T1OUT
PC0/T1IN
VSS
AVSS
26
27
VSS
PD1/T3OUT
PD0/T3IN
XOUT
XIN
PE7
52
18
AVDD
PH0/ANA8
PE2
PE1
PE0
VSS
VDD
PA7/SDA
Figure 6. Z8 Encore! XP F64xx Series in 68-Pin Plastic Leaded Chip Carrier (PLCC)
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PA0/T0IN
PD2
PC2/SS
PF6
RESET
1
80
75
70
PA4/RXD0
PA5/TXD0
PA6/SCL
VDD
VSS
PC4/MOSI
PD4/RXD1
PD5/TXD1
VDD
PF7
PC5/MISO
PD3/DE1
PA3/CTS0
VSS
PA1/T0OUT
PA2/DE0
13
65
64
PD6/CTS1
PC3/SCK
PD7/RCOUT
60
5
VDD
PF5
PF4
PF3
PE4
PE3
VSS
PE2
PE1
PE0
VSS
PF2
PF1
PF0
VDD
PG0
VSS
PG1
PG2
PE5
10
55
PE6
PE7
VDD
PG3
PG4
15
50
20
45
PG5
PG6
VDD
PG7
PC7/T2OUT
PC6/T2IN
DBG
PD1/T3OUT
PC1/T1OUT
PC0/T1IN
41
40
VSS
PH3/ANA11
VREF
AVSS
PB6/ANA6
PB7/ANA7
PB3/ANA3
PB2/ANA2
PH2/ANA10
35
PB4/ANA4
PB5/ANA5
PB1/ANA1
30
PH1/ANA9
PB0/ANA0
VSS
24
25
AVDD
PH0/ANA8
PD0/T3IN
XOUT
XIN
PA7/SDA
Figure 7. Z8 Encore! XP F64xx Series in 80-Pin Quad Flat Package (QFP)
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Signal Descriptions
Table 3 lists the Z8 Encore! XP signals. To determine the available signals for a specific
package style, see the Pin Configurations section on page 8.
Table 3. Signal Descriptions
Signal
Mnemonic
I/O
Description
General-Purpose I/O Ports A–H
PA[7:0]
I/O
Port A[7:0]. These pins are used for general-purpose I/O and support 5 V-tolerant inputs.
PB[7:0]
I/O
Port B[7:0]. These pins are used for general-purpose I/O.
PC[7:0]
I/O
Port C[7:0]. These pins are used for general-purpose I/O. These pins are used
for general-purpose I/O and support 5 V-tolerant inputs
PD[7:0]
I/O
Port D[7:0]. These pins are used for general-purpose I/O. These pins are used
for general-purpose I/O and support 5 V-tolerant inputs
PE[7:0]
I/O
Port E[7:0]. These pins are used for general-purpose I/O. These pins are used
for general-purpose I/O and support 5 V-tolerant inputs.
PF[7:0]
I/O
Port F[7:0]. These pins are used for general-purpose I/O. These pins are used
for general-purpose I/O and support 5 V-tolerant inputs.
PG[7:0]
I/O
Port G[7:0]. These pins are used for general-purpose I/O. These pins are used
for general-purpose I/O and support 5 V-tolerant inputs.
PH[3:0]
I/O
Port H[3:0]. These pins are used for general-purpose I/O.
SCL
O
Serial Clock. This is the output clock for the I2C. This pin is multiplexed with a
general-purpose I/O pin. When the general-purpose I/O pin is configured for
alternate function to enable the SCL function, this pin is open-drain.
SDA
I/O
Serial Data. This open-drain pin transfers data between the I2C and a slave.
This pin is multiplexed with a general-purpose I/O pin. When the general-purpose I/O pin is configured for alternate function to enable the SDA function,
this pin is open-drain.
SS
I/O
Slave Select. This signal can be an output or an input. If the Z8 Encore! XP
F64xx Series is the SPI master, this pin may be configured as the Slave Select
output. If the Z8 Encore! XP F64xx Series is the SPI slave, this pin is the input
slave select. It is multiplexed with a general-purpose I/O pin.
SCK
I/O
SPI Serial Clock. The SPI master supplies this pin. If the Z8 Encore! XP F64xx
Series is the SPI master, this pin is an output. If the Z8 Encore! XP F64xx
Series is the SPI slave, this pin is an input. It is multiplexed with a general-purpose I/O pin.
2
I C Controller
SPI Controller
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Table 3. Signal Descriptions (Continued)
Signal
Mnemonic
I/O
Description
SPI Controller (continued)
MOSI
I/O
Master-Out/Slave-In. This signal is the data output from the SPI master device
and the data input to the SPI slave device. It is multiplexed with a general-purpose I/O pin.
MISO
I/O
Master-In/Slave-Out. This pin is the data input to the SPI master device and
the data output from the SPI slave device. It is multiplexed with a
general-purpose I/O pin.
UART Controllers
TXD0/TXD1
O
Transmit Data. These signals are the transmit outputs from the UARTs. The
TxD signals are multiplexed with general-purpose I/O pins.
RXD0/RXD1
I
Receive Data. These signals are the receiver inputs for the UARTs and IrDAs.
The RxD signals are multiplexed with general-purpose I/O pins.
CTS0/CTS1
I
Clear To Send. These signals are control inputs for the UARTs. The CTS signals are multiplexed with general-purpose I/O pins.
DE0/DE1
O
Driver Enable. This signal allows automatic control of external RS-485 drivers.
This signal is approximately the inverse of the Transmit Empty (TXE) bit in the
UART Status 0 Register. The DE signal may be used to ensure an external
RS-485 driver is enabled when data is transmitted by the UART.
T0OUT/
T1OUT/
T2OUT/
T3OUT
O
Timer Output 0-3. These signals are output pins from the timers. The timer
output signals are multiplexed with general-purpose I/O pins. T3OUT is not
available in 44-pin package devices.
T0IN/T1IN/
T2IN/T3IN
I
Timer Input 0-3. These signals are used as the capture, gating and counter
inputs. The timer input signals are multiplexed with general-purpose I/O pins.
T3IN is not available in 44-pin package devices.
ANA[11:0]
I
Analog Input. These signals are inputs to the ADC. The ADC analog inputs are
multiplexed with general-purpose I/O pins.
VREF
I
Analog-to-Digital converter reference voltage input. The VREF pin must be left
unconnected (or capacitively coupled to analog ground) if the internal voltage
reference is selected as the ADC reference voltage.
Timers
Analog
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Table 3. Signal Descriptions (Continued)
Signal
Mnemonic
I/O
Description
XIN
I
External Crystal Input. This is the input pin to the crystal oscillator. A crystal
can be connected between it and the XOUT pin to form the oscillator. This signal is usable with external RC networks and an external clock driver.
XOUT
O
External Crystal Output. This pin is the output of the crystal oscillator. A crystal
can be connected between it and the XIN pin to form the oscillator. When the
system clock is referred to in this manual, it refers to the frequency of the signal at this pin. This pin must be left unconnected when not using a crystal.
RCOUT
O
RC Oscillator Output. This signal is the output of the RC oscillator. It is multiplexed with a general-purpose I/O pin. This signal must be left unconnected
when not using a crystal.
Oscillators
On-Chip Debugger
DBG
I/O
Debug. This pin is the control and data input and output to and from the OnChip Debugger. This pin is open-drain.
Caution: For operation of the On-Chip Debugger, all power pins (VDD and
AVDD) must be supplied with power and all ground pins (VSS and AVSS) must
be properly grounded. The DBG pin is open-drain and must have an external
pull-up resistor to ensure proper operation.
Reset
RESET
I
RESET. Generates a Reset when asserted (driven Low).
VDD
I
Power Supply.
AVDD
I
Analog Power Supply.
VSS
I
Ground.
AVSS
I
Analog Ground.
Power Supply
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Pin Characteristics
Table 4 lists the characteristics for each pin available on the Z8 Encore! XP F64xx Series
products and the data is sorted alphabetically by the pin symbol mnemonic.
Table 4. Pin Characteristics of the Z8 Encore! XP F64xx Series
Symbol
Mnemonic
Active Low
Reset
or
Direction Direction Active High
Tri-State
Output
Internal
Pull-Up or
Pull-Down
SchmittTrigger
Input
Open-Drain
Output
AVSS
N/A
N/A
N/A
N/A
No
No
N/A
AVDD
N/A
N/A
N/A
N/A
No
No
N/A
DBG
I/O
I
N/A
Yes
No
Yes
Yes
VSS
N/A
N/A
N/A
N/A
No
No
N/A
PA[7:0]
I/O
I
N/A
Yes
No
Yes
Yes,
programmable
PB[7:0]
I/O
I
N/A
Yes
No
Yes
Yes,
programmable
PC[7:0]
I/O
I
N/A
Yes
No
Yes
Yes,
programmable
PD[7:0]
I/O
I
N/A
Yes
No
Yes
Yes,
programmable
PE7:0]
I/O
I
N/A
Yes
No
Yes
Yes,
programmable
PF[7:0]
I/O
I
N/A
Yes
No
Yes
Yes,
programmable
PG[7:0]
I/O
I
N/A
Yes
No
Yes
Yes,
programmable
PH[3:0]
I/O
I
N/A
Yes
No
Yes
Yes,
programmable
RESET
I
I
Low
N/A
Pull-up
Yes
N/A
VDD
N/A
N/A
N/A
N/A
No
No
N/A
XIN
I
I
N/A
N/A
No
No
N/A
XOUT
O
O
N/A
Yes, in
Stop Mode
No
No
No
Note: x represents integer 0, 1,... to indicate multiple pins with symbol mnemonics that differ only by the integer.
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Address Space
The eZ8 CPU can access three distinct address spaces:
•
The register file contains addresses for the general-purpose registers and the eZ8 CPU,
peripheral and general-purpose I/O port control registers
•
The program memory contains addresses for all memory locations having executable
code and/or data
•
The Data Memory consists of the addresses for all memory locations that hold only data
These three address spaces are covered briefly in the following sections. For more information about the eZ8 CPU and its address space, refer to the eZ8 CPU Core User Manual
(UM0128), which is available for download on www.zilog.com.
Register File
The register file address space in the Z8 Encore! XP F64xx Series is 4 KB (4096 bytes).
The register file is composed of two sections: control registers and general-purpose registers. When instructions are executed, registers are read from when defined as sources and
written to when defined as destinations. The architecture of the eZ8 CPU allows all general-purpose registers to function as accumulators, address pointers, index registers, stack
areas, or scratch pad memory.
The upper 256 bytes of the 4 KB register file address space are reserved for control of the
eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at
addresses from F00h to FFFh. Some of the addresses within the 256-byte control register
section are reserved (unavailable). Reading from an reserved register file addresses returns
an undefined value. Writing to reserved register file addresses is not recommended and
can produce unpredictable results.
The on-chip RAM always begins at address 000h in the register file address space. The Z8
Encore! XP F64xx Series provide 2 KB to 4 KB of on-chip RAM depending upon the
device. Reading from register file addresses outside the available RAM addresses (and not
within the control register address space) returns an undefined value. Writing to these register file addresses produces no effect. To determine the amount of RAM available for the
specific Z8 Encore! XP F64xx Series device, see the Part Selection Guide section on
page 2.
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Program Memory
The eZ8 CPU supports 64 KB of program memory address space. The Z8 Encore! XP
F64xx Series contains 16 KB to 64 KB of on-chip Flash in the program memory address
space, depending upon the device. Reading from program memory addresses outside the
available Flash memory addresses returns FFh. Writing to these unimplemented program
memory addresses produces no effect. Table 5 describes the program memory maps for
the Z8 Encore! XP F64xx Series products.
Table 5. Z8 Encore! XP F64xx Series Program Memory Maps
Program Memory Address (Hex)
Function
Z8F162x Products
0000-0001
Option Bits
0002-0003
Reset Vector
0004-0005
WDT Interrupt Vector
0006-0007
Illegal Instruction Trap
0008-0037
Interrupt Vectors*
0038-3FFF
Program Memory
Z8F242x Products
0000-0001
Option Bits
0002-0003
Reset Vector
0004-0005
WDT Interrupt Vector
0006-0007
Illegal Instruction Trap
0008-0037
Interrupt Vectors*
0038-5FFF
Program Memory
Z8F322x Products
0000-0001
Option Bits
0002-0003
Reset Vector
0004-0005
WDT Interrupt Vector
0006-0007
Illegal Instruction Trap
0008-0037
Interrupt Vectors*
0038-7FFF
Program Memory
Z8F482x Products
0000-0001
Option Bits
0002-0003
Reset Vector
0004-0005
WDT Interrupt Vector
Note: *See Table 23 on page 48 for a list of the interrupt vectors.
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Table 5. Z8 Encore! XP F64xx Series Program Memory Maps (Continued)
Program Memory Address (Hex)
Function
0006-0007
Illegal Instruction Trap
0008-0037
Interrupt Vectors*
0038-BFFF
Program Memory
Z8F642x Products
0000-0001
Option Bits
0002-0003
Reset Vector
0004-0005
WDT Interrupt Vector
0006-0007
Illegal Instruction Trap
0008-0037
Interrupt Vectors*
0038-FFFF
Program Memory
Note: *See Table 23 on page 48 for a list of the interrupt vectors.
Data Memory
The Z8 Encore! XP F64xx Series does not use the eZ8 CPU’s 64 KB data memory address
space.
Information Area
Table 6 describes the Z8 Encore! XP F64xx Series’ Information Area. This 512-byte
Information Area is accessed by setting bit 7 of the Page Select Register to 1. When access
is enabled, the Information Area is mapped into program memory and overlays the 512
bytes at addresses FE00h to FFFFh. When the Information Area access is enabled, execution of the LDC and LDCI instructions from these program memory addresses return the
Information Area data rather than the program memory data. Reads of these addresses
through the On-Chip Debugger also returns the Information Area data. Execution of code
from these addresses continues to correctly use program memory. Access to the Information Area is read-only.
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Table 6. Z8 Encore! XP F64xx Series Information Area Map
Program Memory
Address (Hex)
Function
FE00h–FE3Fh
Reserved
FE40h–FE53h
Part Number
20-character ASCII alphanumeric code
Left-justified and filled with zeros (ASCII Null character)
FE54h–FFFFh
Reserved
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Register File Address Map
Table 7 provides the address map for the register file of the Z8 Encore! XP F64xx Series
products. Not all devices and package styles in the Z8 Encore! XP F64xx Series support
Timer 3 and all of the GPIO ports. Consider registers for unimplemented peripherals to be
reserved.
Table 7. Z8 Encore! XP F64xx Series Register File Address Map
Address (Hex) Register Description
Mnemonic
Reset (Hex)
—
XX
Page
General-Purpose RAM
000–EFF
General-Purpose Register File RAM
Timer 0
F00
Timer 0 High Byte
T0H
00
72
F01
Timer 0 Low Byte
T0L
01
72
F02
Timer 0 Reload High Byte
T0RH
FF
74
F03
Timer 0 Reload Low Byte
T0RL
FF
74
F04
Timer 0 PWM High Byte
T0PWMH
00
75
F05
Timer 0 PWM Low Byte
T0PWML
00
75
F06
Timer 0 Control 0
T0CTL0
00
76
F07
Timer 0 Control 1
T0CTL1
00
77
F08
Timer 1 High Byte
T1H
00
72
F09
Timer 1 Low Byte
T1L
01
72
F0A
Timer 1 Reload High Byte
T1RH
FF
74
F0B
Timer 1 Reload Low Byte
T1RL
FF
74
F0C
Timer 1 PWM High Byte
T1PWMH
00
75
F0D
Timer 1 PWM Low Byte
T1PWML
00
75
F0E
Timer 1 Control 0
T1CTL0
00
76
F0F
Timer 1 Control 1
T1CTL1
00
77
F10
Timer 2 High Byte
T2H
00
72
F11
Timer 2 Low Byte
T2L
01
72
F12
Timer 2 Reload High Byte
T2RH
FF
74
F13
Timer 2 Reload Low Byte
T2RL
FF
74
Timer 1
Timer 2
Note: XX = Undefined.
PS019926-1114
PRELIMINARY
Register File Address Map
Z8 Encore! XP® F64xx Series
Product Specification
23
Table 7. Z8 Encore! XP F64xx Series Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
Reset (Hex)
Page
Timer 2 (continued)
F14
Timer 2 PWM High Byte
T2PWMH
00
75
F15
Timer 2 PWM Low Byte
T2PWML
00
75
F16
Timer 2 Control 0
T2CTL0
00
76
F17
Timer 2 Control 1
T2CTL1
00
77
Timer 3 (Unavailable in the 44-Pin Package)
F18
Timer 3 High Byte
T3H
00
72
F19
Timer 3 Low Byte
T3L
01
72
F1A
Timer 3 Reload High Byte
T3RH
FF
74
F1B
Timer 3 Reload Low Byte
T3RL
FF
74
F1C
Timer 3 PWM High Byte
T3PWMH
00
75
F1D
Timer 3 PWM Low Byte
T3PWML
00
75
F1E
Timer 3 Control 0
T3CTL0
00
76
F1F
Timer 3 Control 1
T3CTL1
00
77
20–3F
Reserved
—
XX
UART0 Transmit Data
U0TXD
XX
98
UART0 Receive Data
U0RXD
XX
99
UART 0
F40
F41
UART0 Status 0
U0STAT0
0000011Xb
100
F42
UART0 Control 0
U0CTL0
00
102
F43
UART0 Control 1
U0CTL1
00
102
F44
UART0 Status 1
U0STAT1
00
100
F45
UART0 Address Compare Register
U0ADDR
00
105
F46
UART0 Baud Rate High Byte
U0BRH
FF
105
F47
UART0 Baud Rate Low Byte
U0BRL
FF
105
UART1 Transmit Data
U1TXD
XX
98
UART1 Receive Data
U1RXD
XX
99
UART 1
F48
F49
UART1 Status 0
U1STAT0
0000011Xb
100
F4A
UART1 Control 0
U1CTL0
00
102
F4B
UART1 Control 1
U1CTL1
00
102
F4C
UART1 Status 1
U1STAT1
00
100
Note: XX = Undefined.
PS019926-1114
PRELIMINARY
Register File Address Map
Z8 Encore! XP® F64xx Series
Product Specification
24
Table 7. Z8 Encore! XP F64xx Series Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
Reset (Hex)
Page
U1ADDR
00
105
UART 1 (continued)
F4D
UART1 Address Compare Register
F4E
UART1 Baud Rate High Byte
U1BRH
FF
105
F4F
UART1 Baud Rate Low Byte
U1BRL
FF
105
I2CDATA
00
141
I2C
F50
I2C Data
2
F51
I C Status
I2CSTAT
80
142
F52
I 2C
I2CCTL
00
144
F53
2
I2CBRH
FF
145
2
Control
I C Baud Rate High Byte
F54
I C Baud Rate Low Byte
I2CBRL
FF
145
F55
I 2C
I2CDST
C0
147
F56
2
I C Diagnostic Control
I2CDIAG
00
149
F57–F5F
Reserved
—
XX
SPIDATA
XX
121
Diagnostic State
Serial Peripheral Interface (SPI)
F60
SPI Data
F61
SPI Control
SPICTL
00
122
F62
SPI Status
SPISTAT
01
123
F63
SPI Mode
SPIMODE
00
125
F64
SPI Diagnostic State
SPIDST
00
126
F65
Reserved
—
XX
F66
SPI Baud Rate High Byte
SPIBRH
FF
126
F67
SPI Baud Rate Low Byte
SPIBRL
FF
126
F68–F6F
Reserved
—
XX
ADCCTL
20
—
XX
Analog-to-Digital Converter
F70
ADC Control
165
F71
Reserved
F72
ADC Data High Byte
ADCD_H
XX
167
F73
ADC Data Low Bits
ADCD_L
XX
168
F74–FAF
Reserved
—
XX
DMA0CTL
00
153
DMA0IO
XX
154
DMA 0
FB0
DMA0 Control
FB1
DMA0 I/O Address
Note: XX = Undefined.
PS019926-1114
PRELIMINARY
Register File Address Map
Z8 Encore! XP® F64xx Series
Product Specification
25
Table 7. Z8 Encore! XP F64xx Series Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
Reset (Hex)
Page
DMA0H
XX
155
DMA 0 (continued)
FB2
DMA0 End/Start Address High Nibble
FB3
DMA0 Start Address Low Byte
DMA0START
XX
156
FB4
DMA0 End Address Low Byte
DMA0END
XX
156
FB8
DMA1 Control
DMA1CTL
00
153
FB9
DMA1 I/O Address
DMA1IO
XX
154
FBA
DMA1 End/Start Address High Nibble
DMA1H
XX
155
FBB
DMA1 Start Address Low Byte
DMA1START
XX
156
FBC
DMA1 End Address Low Byte
DMA1END
XX
156
DMA 1
DMA ADC
FBD
DMA_ADC Address
DMAA_ADDR
XX
157
FBE
DMA_ADC Control
DMAACTL
00
158
FBF
DMA_ADC Status
DMAASTAT
00
159
IRQ0
00
51
Interrupt Controller
FC0
Interrupt Request 0
FC1
IRQ0 Enable High Bit
IRQ0ENH
00
55
FC2
IRQ0 Enable Low Bit
IRQ0ENL
00
55
FC3
Interrupt Request 1
IRQ1
00
53
FC4
IRQ1 Enable High Bit
IRQ1ENH
00
56
FC5
IRQ1 Enable Low Bit
IRQ1ENL
00
56
FC6
Interrupt Request 2
IRQ2
00
54
FC7
IRQ2 Enable High Bit
IRQ2ENH
00
58
FC8
IRQ2 Enable Low Bit
IRQ2ENL
00
58
FC9–FCC
Reserved
—
XX
FCD
Interrupt Edge Select
IRQES
00
60
FCE
Interrupt Port Select
IRQPS
00
60
FCF
Interrupt Control
IRQCTL
00
61
FD0
Port A Address
PAADDR
00
40
FD1
Port A Control
PACTL
00
41
FD2
Port A Input Data
PAIN
XX
46
GPIO Port A
Note: XX = Undefined.
PS019926-1114
PRELIMINARY
Register File Address Map
Z8 Encore! XP® F64xx Series
Product Specification
26
Table 7. Z8 Encore! XP F64xx Series Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
Reset (Hex)
Page
PAOUT
00
46
GPIO Port A (continued)
FD3
Port A Output Data
GPIO Port B
FD4
Port B Address
PBADDR
00
40
FD5
Port B Control
PBCTL
00
41
FD6
Port B Input Data
PBIN
XX
46
FD7
Port B Output Data
PBOUT
00
46
GPIO Port C
FD8
Port C Address
PCADDR
00
40
FD9
Port C Control
PCCTL
00
41
FDA
Port C Input Data
PCIN
XX
46
FDB
Port C Output Data
PCOUT
00
46
GPIO Port D
FDC
Port D Address
PDADDR
00
40
FDD
Port D Control
PDCTL
00
41
FDE
Port D Input Data
PDIN
XX
46
FDF
Port D Output Data
PDOUT
00
46
GPIO Port E
FE0
Port E Address
PEADDR
00
40
FE1
Port E Control
PECTL
00
41
FE2
Port E Input Data
PEIN
XX
46
FE3
Port E Output Data
PEOUT
00
46
GPIO Port F
FE4
Port F Address
PFADDR
00
40
FE5
Port F Control
PFCTL
00
41
FE6
Port F Input Data
PFIN
XX
46
FE7
Port F Output Data
PFOUT
00
46
GPIO Port G
FE8
Port G Address
PGADDR
00
40
FE9
Port G Control
PGCTL
00
41
FEA
Port G Input Data
PGIN
XX
46
FEB
Port G Output Data
PGOUT
00
46
Note: XX = Undefined.
PS019926-1114
PRELIMINARY
Register File Address Map
Z8 Encore! XP® F64xx Series
Product Specification
27
Table 7. Z8 Encore! XP F64xx Series Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
Reset (Hex)
Page
GPIO Port H
FEC
Port H Address
PHADDR
00
40
FED
Port H Control
PHCTL
00
41
FEE
Port H Input Data
PHIN
XX
46
FEF
Port H Output Data
PHOUT
00
46
WDTCTL
XXX00000b
83
Watchdog Timer
FF0
Watchdog Timer Control
FF1
Watchdog Timer Reload Upper Byte
WDTU
FF
85
FF2
Watchdog Timer Reload High Byte
WDTH
FF
85
FF3
Watchdog Timer Reload Low Byte
WDTL
FF
85
FF4–FF7
Reserved
—
XX
Flash Memory Controller
FF8
Flash Control
FCTL
00
175
FF8
Flash Status
FSTAT
00
177
FF9
Page Select
FPS
00
177
FF9 (if
enabled)
Flash Sector Protect
FPROT
00
178
FFA
Flash Programming Frequency High Byte
FFREQH
00
179
FFB
Flash Programming Frequency Low Byte
FFREQL
00
179
Refer to the
eZ8 CPU
Core User
Manual
(UM0128)
eZ8 CPU
FFC
Flags
—
XX
FFD
Register Pointer
RP
XX
FFE
Stack Pointer High Byte
SPH
XX
FFF
Stack Pointer Low Byte
SPL
XX
Note: XX = Undefined.
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Reset and Stop Mode Recovery
The Reset Controller within the Z8 Encore! XP F64xx Series controls Reset and Stop
Mode Recovery operation. In typical operation, the following events cause a Reset to
occur:
•
•
•
•
•
Power-On Reset
Voltage Brown-Out
Watchdog Timer time-out (when configured via the WDT_RES option bit to initiate a
Reset)
External RESET pin assertion
On-Chip Debugger initiated Reset (OCDCTL[0] set to 1)
When the Z8 Encore! XP F64xx Series devices are in Stop Mode, a Stop Mode Recovery
is initiated by either of the following events:
•
•
•
Watchdog Timer time-out
GPIO port input pin transition on an enabled Stop Mode Recovery source
DBG pin driven Low
Reset Types
The Z8 Encore! XP F64xx Series provides two different types of reset operation (system
reset and Stop Mode Recovery). The type of Reset is a function of both the current operating mode of the Z8 Encore! XP F64xx Series devices and the source of the Reset. Table 8
lists the types of Reset and their operating characteristics.
Table 8. Reset and Stop Mode Recovery Characteristics and Latency
Reset Characteristics and Latency
Reset Type
Control Registers
System reset
Reset (as applicable) Reset
66 WDT Oscillator cycles + 16 System Clock cycles
Stop Mode
Recovery
Unaffected, except
WDT_CTL Register
66 WDT Oscillator cycles + 16 System Clock cycles
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Reset
Reset Latency (Delay)
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System Reset
During a system reset, the Z8 Encore! XP F64xx Series devices are held in Reset for 66
cycles of the Watchdog Timer oscillator followed by 16 cycles of the system clock. At the
beginning of Reset, all GPIO pins are configured as inputs.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watchdog Timer oscillator continue to run. The system clock begins operating following the Watchdog Timer oscillator cycle count. The eZ8 CPU and on-chip
peripherals remain idle through the 16 cycles of the system clock.
Upon Reset, control registers within the register file that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer, Register Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8
CPU fetches the Reset vector at program memory addresses 0002h and 0003h and loads
that value into the program counter. Program execution begins at the Reset vector address.
Reset Sources
Table 9 lists the reset sources as a function of the operating mode. The text following provides more detailed information about the individual Reset sources. A Power-On Reset/
Voltage Brown-Out event always takes priority over all other possible reset sources to
ensure a full system reset occurs.
Table 9. Reset Sources and Resulting Reset Type
Operating Mode
Reset Source
Reset Type
NORMAL or Halt
modes
Power-On Reset/Voltage BrownOut
system reset
Watchdog Timer time-out
when configured for Reset
system reset
RESET pin assertion
system reset
On-Chip Debugger initiated Reset system reset except the On-Chip Debugger is
(OCDCTL[0] set to 1)
unaffected by the reset
Stop Mode
Power-On Reset/Voltage BrownOut
system reset
RESET pin assertion
system reset
DBG pin driven Low
system reset
Power-On Reset
Each device in the Z8 Encore! XP F64xx Series contains an internal Power-On Reset circuit. The POR circuit monitors the supply voltage and holds the device in the Reset state
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until the supply voltage reaches a safe operating level. After the supply voltage exceeds
the POR voltage threshold (VPOR), the POR counter is enabled and counts 66 cycles of the
Watchdog Timer oscillator. After the POR counter times out, the XTAL counter is enabled
to count a total of 16 system clock pulses. The devices are held in the Reset state until both
the POR counter and XTAL counter have timed out. After the Z8 Encore! XP F64xx
Series devices exit the Power-On Reset state, the eZ8 CPU fetches the Reset vector. Following Power-On Reset, the POR status bit in the Watchdog Timer Control (WDTCTL)
Register is set to 1.
Figure 8 displays Power-On Reset operation. For the POR threshold voltage (VPOR), see
the Electrical Characteristics chapter on page 200.
VCC = 3.3V
VPOR
VVBO
Program
Execution
VCC = 0.0 V
WDT Clock
Primary
Oscillator
Internal RESET
signal
Oscillator
Start-up
POR
Counter Delay
XTAL
Counter Delay
Figure 8. Power-On Reset Operation
Voltage Brown-Out Reset
The devices in the Z8 Encore! XP F64xx Series provide low Voltage Brown-Out protection. The VBO circuit senses when the supply voltage drops to an unsafe level (below the
VBO threshold voltage) and forces the device into the Reset state. While the supply voltage remains below the Power-On Reset voltage threshold (VPOR), the VBO block holds
the device in the Reset state.
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After the supply voltage again exceeds the Power-On Reset voltage threshold, the devices
progress through a full system reset sequence, as described in the Power-On Reset section.
Following Power-On Reset, the POR status bit in the Watchdog Timer Control
(WDTCTL) Register is set to 1. Figure 9 displays Voltage Brown-Out operation. For the
VBO and POR threshold voltages (VVBO and VPOR), see the Electrical Characteristics
chapter on page 200.
The Voltage Brown-Out circuit can be either enabled or disabled during Stop Mode. Operation during Stop Mode is set by the VBO_AO option bit. For information about configuring VBO_AO, see the Option Bits chapter on page 180.
VCC = 3.3V
VCC = 3.3V
VPOR
VVBO
Program
Execution
Voltage
Brown-Out
Program
Execution
WDT Clock
Primary
Oscillator
Internal RESET
Signal
POR
Counter Delay
XTAL
Counter Delay
Figure 9. Voltage Brown-Out Reset Operation
Watchdog Timer Reset
If the device is in normal or Halt Mode, the Watchdog Timer can initiate a system reset at
time-out if the WDT_RES option bit is set to 1. This capability is the default (unprogrammed) setting of the WDT_RES option bit. The WDT status bit in the WDT Control
Register is set to signify that the reset was initiated by the Watchdog Timer.
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External Pin Reset
The RESET pin has a Schmitt-triggered input, an internal pull-up, an analog filter and a
digital filter to reject noise. Once the RESET pin is asserted for at least 4 system clock
cycles, the devices progress through the system reset sequence. While the RESET input
pin is asserted Low, the Z8 Encore! XP F64xx Series devices continue to be held in the
Reset state. If the RESET pin is held Low beyond the system reset time-out, the devices
exit the Reset state immediately following RESET pin deassertion. Following a system
reset initiated by the external RESET pin, the EXT status bit in the Watchdog Timer Control (WDTCTL) Register is set to 1.
On-Chip Debugger Initiated Reset
A Power-On Reset can be initiated using the On-Chip Debugger by setting the RST bit in
the OCD Control Register. The On-Chip Debugger block is not reset but the rest of the
chip goes through a normal system reset. The RST bit automatically clears during the system reset. Following the system reset the POR bit in the WDT Control Register is set.
Stop Mode Recovery
Stop Mode is entered by the eZ8 executing a stop instruction. For detailed Stop Mode
information, see the Low-Power Modes chapter on page 34. During Stop Mode Recovery,
the devices are held in reset for 66 cycles of the Watchdog Timer oscillator followed by 16
cycles of the system clock. Stop Mode Recovery only affects the contents of the Watchdog
Timer Control Register. Stop Mode Recovery does not affect any other values in the register file, including the Stack Pointer, Register Pointer, Flags, peripheral control registers,
and general-purpose RAM.
The eZ8 CPU fetches the Reset vector at program memory addresses 0002h and 0003h
and loads that value into the program counter. Program execution begins at the Reset vector address. Following Stop Mode Recovery, the stop bit in the Watchdog Timer Control
Register is set to 1. Table 10 lists the Stop Mode Recovery sources and resulting actions.
Table 10. Stop Mode Recovery Sources and Resulting Action
Operating Mode
Stop Mode Recovery Source
Action
Stop Mode
Watchdog Timer time-out when configured
for Reset.
Stop Mode Recovery.
Watchdog Timer time-out when configured
for interrupt.
Stop Mode Recovery followed by
interrupt (if interrupts are enabled).
Data transition on any GPIO port pin enabled Stop Mode Recovery.
as a Stop Mode Recovery source.
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Stop Mode Recovery Using Watchdog Timer Time-Out
If the Watchdog Timer times out during Stop Mode, the device undergoes a Stop Mode
Recovery sequence. In the Watchdog Timer Control Register, the WDT and stop bits are
set to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and
the Z8 Encore! XP F64xx Series devices are configured to respond to interrupts, the eZ8
CPU services the Watchdog Timer interrupt request following the normal Stop Mode
Recovery sequence.
Stop Mode Recovery Using a GPIO Port Pin Transition HALT
Each of the GPIO port pins may be configured as a Stop Mode Recovery input source. On
any GPIO pin enabled as a Stop Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery. The GPIO Stop
Mode Recovery signals are filtered to reject pulses less than 10 ns (typical) in duration. In
the Watchdog Timer Control Register, the stop bit is set to 1.
Caution: In Stop Mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input
Data registers record the Port transition only if the signal stays on the Port pin through
the end of the Stop Mode Recovery delay. Thus, short pulses on the Port pin can initiate
Stop Mode Recovery without being written to the Port Input Data Register or without initiating an interrupt (if enabled for that pin).
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Low-Power Modes
The Z8 Encore! XP F64xx Series products contain power-saving features. The highest
level of power reduction is provided by Stop Mode. The next level of power reduction is
provided by Halt Mode.
Stop Mode
Execution of the eZ8 CPU’s stop instruction places the device into Stop Mode. In Stop
Mode, the operating characteristics are:
•
Primary crystal oscillator is stopped; the XIN pin is driven High and the XOUT pin is
driven Low
•
•
•
•
System clock is stopped
•
The Voltage Brown-Out protection circuit continues to operate, if enabled for operation
in Stop Mode using the associated option bit
•
All other on-chip peripherals are idle
eZ8 CPU is stopped
Program counter (PC) stops incrementing
The Watchdog Timer and its internal RC oscillator continue to operate, if enabled for
operation during Stop Mode
To minimize current in Stop Mode, all GPIO pins that are configured as digital inputs must
be driven to one of the supply rails (VCC or GND), the Voltage Brown-Out protection must
be disabled, and the Watchdog Timer must be disabled. The devices can be brought out of
Stop Mode using Stop Mode Recovery. For more information about Stop Mode Recovery,
see the Reset and Stop Mode Recovery chapter on page 28.
Caution: Stop Mode must not be used when driving the Z8 Encore! XP F64xx Series devices with
an external clock driver source.
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Halt Mode
Execution of the eZ8 CPU’s HALT instruction places the device into Halt Mode. In Halt
Mode, the operating characteristics are:
•
•
•
•
•
•
•
Primary crystal oscillator is enabled and continues to operate
System clock is enabled and continues to operate
eZ8 CPU is stopped
Program counter stops incrementing
Watchdog Timer’s internal RC oscillator continues to operate
The Watchdog Timer continues to operate, if enabled
All other on-chip peripherals continue to operate
The eZ8 CPU can be brought out of Halt Mode by any of the following operations:
•
•
•
•
•
Interrupt
Watchdog Timer time-out (interrupt or reset)
Power-On Reset
Voltage Brown-Out Reset
External RESET pin assertion
To minimize current in Halt Mode, all GPIO pins which are configured as inputs must be
driven to one of the supply rails (VCC or GND).
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General-Purpose I/O
The Z8 Encore! XP F64xx Series products support a maximum of seven 8-bit ports (ports
A–G) and one 4-bit port (Port H) for general-purpose input/output (GPIO) operations.
Each port consists of control and data registers. The GPIO control registers are used to
determine data direction, open-drain, output drive current and alternate pin functions.
Each port pin is individually programmable. All ports (except B and H) support 5 V-tolerant inputs.
GPIO Port Availability By Device
Table 11 lists the port pins available with each device and package type.
Table 11. Port Availability by Device and Package Type
Device
Packages
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Port H
Z8X1621
40-pin
[7:0]
[7:0]
[7:0]
[6:3,1:0]
–
–
–
–
44-pin
[7:0]
[7:0]
[7:0]
[6:0]
–
–
–
–
Z8X1622
64- and 68-pin
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7]
[3]
[3:0]
Z8X2421
40-pin
[7:0]
[7:0]
[7:0]
[6:3,1:0]
–
–
–
–
44-pin
[7:0]
[7:0]
[7:0]
[6:0]
–
–
–
–
Z8X2422
64- and 68-pin
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7]
[3]
[3:0]
Z8X3221
40-pin
[7:0]
[7:0]
[7:0]
[6:3,1:0]
–
–
–
–
44-pin
[7:0]
[7:0]
[7:0]
[6:0]
–
–
–
–
Z8X3222
64- and 68-pin
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7]
[3]
[3:0]
Z8X4821
40-pin
[7:0]
[7:0]
[7:0]
[6:3,1:0]
–
–
–
–
44-pin
[7:0]
[7:0]
[7:0]
[6:0]
–
–
–
–
Z8X4822
64- and 68-pin
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7]
[3]
[3:0]
Z8X4823
80-pin
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[3:0]
Z8X6421
40-pin
[7:0]
[7:0]
[7:0]
[6:3,1:0]
–
–
–
–
44-pin
[7:0]
[7:0]
[7:0]
[6:0]
–
–
–
–
Z8X6422
64- and 68-pin
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7]
[3]
[3:0]
Z8X6423
80-pin
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[3:0]
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General-Purpose I/O
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Product Specification
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Architecture
Figure 10 displays a simplified block diagram of a GPIO port pin. In this figure, the ability
to accommodate alternate functions and variable port current drive strength are not illustrated.
Port Input
Data Register
Q
Schmitt-Trigger
D
System
Clock
VDD
Port Output Control
Port Output
Data Register
DATA
Bus
D
Q
Port
Pin
System
Clock
Port Data Direction
GND
Figure 10. GPIO Port Pin Block Diagram
GPIO Alternate Functions
Many of the GPIO port pins can be used as both general-purpose I/O and to provide access
to on-chip peripheral functions such as the timers and serial communication devices. The
Port A–H Alternate Function subregisters configure these pins for either general-purpose
I/O or alternate function operation. When a pin is configured for alternate function, control
of the port pin direction (input/output) is passed from the Port A–H Data Direction registers to the alternate function assigned to this pin. Table 12 lists the alternate functions
associated with each port pin.
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Table 12. Port Alternate Function Mapping
Port
Pin
Mnemonic
Alternate Function Description
Port A
PA0
T0IN
Timer 0 Input
PA1
T0OUT
Timer 0 Output
PA2
DE0
UART 0 Driver Enable
PA3
CTS0
UART 0 Clear to Send
PA4
RXD0/IRRX0
UART 0/IrDA 0 Receive Data
PA5
TXD0/IRTX0
UART 0/IrDA 0 Transmit Data
PA6
SCL
I2C Clock (automatically open-drain)
PA7
SDA
I2C Data (automatically open-drain)
PB0
ANA0
ADC analog input 0
PB1
ANA1
ADC analog input 1
PB2
ANA2
ADC analog input 2
PB3
ANA3
ADC analog input 3
PB4
ANA4
ADC analog input 4
PB5
ANA5
ADC analog input 5
PB6
ANA6
ADC analog input 6
PB7
ANA7
ADC analog input 7
PC0
T1IN
Timer 1 Input
PC1
T1OUT
Timer 1 Output
PC2
SS
SPI Slave Select
PC3
SCK
SPI Serial Clock
PC4
MOSI
SPI Master Out/Slave In
PC5
MISO
SPI Master In/Slave Out
PC6
T2IN
Timer 2 In
PC7
T2OUT
Timer 2 Out
PD0
T3IN
Timer 3 In (unavailable in the 44-pin package)
PD1
T3OUT
Timer 3 Out (unavailable in the 44-pin package)
PD2
N/A
No alternate function
PD3
DE1
UART 1 Driver Enable
PD4
RXD1/IRRX1
UART 1/IrDA 1 Receive Data
PD5
TXD1/IRTX1
UART 1/IrDA 1 Transmit Data
PD6
CTS1
UART 1 Clear to Send
PD7
RCOUT
Watchdog Timer RC Oscillator Output
Port B
Port C
Port D
Port E
PS019926-1114
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No alternate functions
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Table 12. Port Alternate Function Mapping (Continued)
Port
Pin
Mnemonic
Alternate Function Description
Port F
PF[7:0] N/A
No alternate functions
Port G
PG[7:0] N/A
No alternate functions
Port H
PH0
ANA8
ADC analog input 8
PH1
ANA9
ADC analog input 9
PH2
ANA10
ADC analog input 10
PH3
ANA11
ADC analog input 11
GPIO Interrupts
Many of the GPIO port pins can be used as interrupt sources. Some port pins may be configured to generate an interrupt request on either the rising edge or falling edge of the pin
input signal. Other port pin interrupts generate an interrupt when any edge occurs (both
rising and falling). For more information about interrupts using the GPIO pins, see the
Interrupt Controller chapter on page 47.
GPIO Control Register Definitions
Four registers for each Port provide access to GPIO control, input data, and output data.
Table 13 lists these Port registers. Use the Port A–H Address and Control registers
together to provide access to subregisters for Port configuration and control.
Table 13. GPIO Port Registers and Subregisters
Port Register
Mnemonic
Port Register Name
PxADDR
Port A–H Address Register (selects subregisters)
PxCTL
Port A–H Control Register (provides access to subregisters)
PxIN
Port A–H Input Data Register
PxOUT
Port A–H Output Data Register
Port Subregister
Mnemonic
Port Register Name
PxDD
Data Direction
PxAF
Alternate Function
PxOC
Output Control (Open-Drain)
PxDD
High Drive Enable
PxSMRE
Stop Mode Recovery Source Enable
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Port A–H Address Registers
The Port A–H Address registers, shown in Table 14, select the GPIO port functionality
accessible through the Port A–H Control registers. The Port A–H Address and Control
registers combine to provide access to all GPIO port control.
Table 14. Port A–H GPIO Address Registers (PxADDR)
Bit
7
Field
6
5
4
3
2
1
0
PADDR[7:0]
RESET
00h
R/W
R/W
Address
FD0h, FD4h, FD8h, FDCh, FE0h, FE4h, FE8h, FECh
Bit
Description
[7:0]
PADDR
Port Address
This port address selects one of the subregisters accessible through the Port A–H Control
Registers.
00h = No function. Provides some protection against accidental port reconfiguration.
01h = Data Direction.
02h = Alternate Function.
03h = Output Control (Open-Drain).
04h = High Drive Enable.
05h = Stop Mode Recovery Source Enable.
06h–FFh = No function.
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Port A–H Control Registers
The Port A–H Control registers, shown in Table 15, set the GPIO port operation. The
value in the corresponding Port A–H Address Register determines the control subregisters
accessible using the Port A–H Control Register.
Table 15. Port A–H Control Registers (PxCTL)
Bit
7
6
5
4
3
Field
2
1
0
PCTL
RESET
00h
R/W
R/W
Address
FD1h, FD5h, FD9h, FDDh, FE1h, FE5h, FE9h, FEDh
Bit
Description
[7:0]
PCTL
Port Control
The Port Control Register provides access to all subregisters that configure the GPIO Port
operation.
Port A–H Data Direction Subregisters
The Port A–H Data Direction Subregister, shown in Table 16, is accessed through the Port
A–H Control Register by writing 01h to the Port A–H Address Register.
Table 16. Port A–H Data Direction Subregisters
Bit
Field
7
6
5
4
3
2
1
0
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
RESET
1
R/W
R/W
Address
See note.
Note: If a 01h exists in the Port A–H Address Register, it is accessible through the Port A–H Control Register.
Bit
Description
[7:0]
DDx
Data Direction
These bits control the direction of the associated port pin. Port Alternate Function operation
overrides the Data Direction Register setting.
0 = Output. Data in the Port A–H Output Data Register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A–H Input Data Register.
The output driver is tri-stated.
Note: x indicates register bits in the range [7:0].
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Port A–H Alternate Function Subregisters
The Port A–H Alternate Function Subregister, shown in Table 17, is accessed through the
Port A–H Control Register by writing 02h to the Port A–H Address Register. The Port
A–H Alternate Function subregisters select the alternate functions for the selected pins. To
determine the alternate function associated with each port pin, see the GPIO Alternate
Functions section on page 37.
Caution: Do not enable alternate function for GPIO port pins which do not have an associated alternate function. Failure to follow this guideline may result in unpredictable operation.
Table 17. Port A–H Alternate Function Subregisters
Bit
Field
7
6
5
4
3
2
1
0
AF7
AF6
AF5
AF4
AF3
AF2
AF1
AF0
RESET
0
R/W
R/W
Address
See note.
Note: If a 02h exists in the Port A–H Address Register, it is accessible through the Port A–H Control Register.
Bit
Description
[7:0]
AFx
Port Alternate Function Enabled
0 = The port pin is in Normal Mode and the DDx bit in the Port A–H Data Direction Subregister
determines the direction of the pin.
1 = The alternate function is selected. Port pin operation is controlled by the alternate function.
Note: x indicates register bits in the range [7:0].
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Port A–H Output Control Subregisters
The Port A–H Output Control Subregister, shown in Table 18, is accessed through the Port
A–H Control Register by writing 03h to the Port A–H Address Register. Setting the bits in
the Port A–H Output Control subregisters to 1 configures the specified port pins for opendrain operation. These subregisters affect the pins directly and, as a result, alternate functions are also affected.
Table 18. Port A–H Output Control Subregisters
Bit
Field
7
6
5
4
3
2
1
0
POC7
POC6
POC5
POC4
POC3
POC2
POC1
POC0
RESET
0
R/W
R/W
Address
See note.
Note: If a 03h exists in the Port A–H Address Register, it is accessible through the Port A–H Control Register.
Bit
Description
[7:0]
POCx
Port Output Control
These bits function independently of the alternate function bit and disables the drains if set to 1.
0 = The drains are enabled for any output mode.
1 = The drain of the associated pin is disabled (open-drain mode).
Note: x indicates register bits in the range [7:0].
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Port A–H High Drive Enable Subregisters
The Port A–H High Drive Enable Subregister, shown in Table 19, is accessed through the
Port A–H Control Register by writing 04h to the Port A–H Address Register. Setting the
bits in the Port A–H High Drive Enable subregisters to 1 configures the specified port pins
for high-current output drive operation. The Port A–H High Drive Enable Subregister
affects the pins directly and, as a result, alternate functions are also affected.
Table 19. Port A–H High Drive Enable Subregisters
Bit
Field
7
6
5
4
3
2
1
0
PHDE7
PHDE6
PHDE5
PHDE4
PHDE3
PHDE2
PHDE1
PHDE0
RESET
0
R/W
R/W
Address
See note.
Note: If a 04h exists in the Port A–H Address Register, it is accessible through the Port A–H Control Register.
Bit
Description
[7:0]
PHDEx
Port High Drive Enabled
0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Note: x indicates register bits in the range [7:0].
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Port A–H Stop Mode Recovery Source Enable Subregisters
The Port A–H Stop Mode Recovery Source Enable Subregister, shown in Table 20, is
accessed through the Port A–H Control Register by writing 05h to the Port A–H Address
Register. Setting the bits in the Port A–H Stop Mode Recovery Source Enable subregisters
to 1 configures the specified Port pins as a Stop Mode Recovery source. During Stop
Mode, any logic transition on a Port pin enabled as a Stop Mode Recovery source initiates
Stop Mode Recovery.
Table 20. Port A–H Stop Mode Recovery Source Enable Subregisters
Bit
Field
7
6
5
4
3
2
1
0
PSMRE7
PSMRE6
PSMRE5
PSMRE4
PSMRE3
PSMRE2
PSMRE1
PSMRE0
RESET
0
R/W
R/W
Address
See note.
Note: If a 05h exists in the Port A–H Address Register, it is accessible through the Port A–H Control Register.
Bit
Description
[7:0]
PSMRE
Port Stop Mode Recovery Source Enabled
0 = The port pin is not configured as a Stop Mode Recovery source. Transitions on this pin during Stop Mode do not initiate Stop Mode Recovery.
1 = The port pin is configured as a Stop Mode Recovery source. Any logic transition on this pin
during Stop Mode initiates Stop Mode Recovery.
Note: x indicates register bits in the range [7:0].
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Port A–H Input Data Registers
Reading from the Port A–H Input Data registers, shown in Table 21, returns the sampled
values from the corresponding port pins. The Port A–H Input Data registers are read-only.
Table 21. Port A–H Input Data Registers (PxIN)
Bit
Field
7
6
5
4
3
2
1
0
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
RESET
X
R/W
R
Address
FD2h, FD6h, FDAh, FDEh, FE2h, FE6h, FEAh, FEEh
Bit
Description
[7:0]
PxIN
Port Input Data
Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low).
1 = Input data is logical 1 (High).
Note: x indicates register bits in the range [7:0].
Port A–H Output Data Register
The Port A–H Output Data Register, shown in Table 22, writes output data to the pins.
Table 22. Port A–H Output Data Register (PxOUT)
Bit
Field
7
6
5
4
3
2
1
0
POUT7
POUT6
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
RESET
0
R/W
R/W
Address
FD3h, FD7h, FDBh, FDFh, FE3h, FE7h, FEBh, FEFh
Bit
Description
[7:0]
PxOUT
Port Output Data
These bits contain the data to be driven out from the port pins. The values are only driven if the
corresponding pin is configured as an output and the pin is not configured for alternate function
operation.
0 = Drive a logical 0 (Low).
1 = Drive a logical 1 (High). High value is not driven if the drain has been disabled by setting
the corresponding Port Output Control Register bit to 1.
Note: x indicates register bits in the range [7:0].
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Interrupt Controller
The interrupt controller on the Z8 Encore! XP F64xx Series products prioritizes the interrupt requests from the on-chip peripherals and the GPIO port pins. The features of the
interrupt controller include:
•
24 unique interrupt vectors:
– 12 GPIO port pin interrupt sources
– 12 on-chip peripheral interrupt sources
•
Flexible GPIO interrupts
– Eight selectable rising and falling edge GPIO interrupts
– Four dual-edge interrupts
•
•
Three levels of individually programmable interrupt priority
Watchdog Timer can be configured to generate an interrupt
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt
service routine is involved with the exchange of data, status information, or control information between the CPU and the interrupting peripheral. When the service routine is completed, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt control has no effect on operation. For more information about interrupt servicing by the eZ8 CPU, refer to the eZ8 CPU Core User Manual (UM0128), which is
available for download on www.zilog.com.
Interrupt Vector Listing
Table 23 lists all of the interrupts available in order of priority. The interrupt vector is
stored with the most significant byte (MSB) at the even program memory address and the
least significant byte (LSB) at the following odd program memory address.
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Table 23. Interrupt Vectors in Order of Priority
Priority
Program Memory
Vector Address
Interrupt Source
Highest
0002h
Reset (not an interrupt)
0004h
Watchdog Timer (see the Watchdog Timer chapter on page 80)
0006h
Illegal Instruction Trap (not an interrupt)
0008h
Timer 2
000Ah
Timer 1
000Ch
Timer 0
000Eh
UART 0 receiver
0010h
UART 0 transmitter
0012h
I 2C
0014h
SPI
0016h
ADC
0018h
Port A7 or Port D7, rising or falling input edge
001Ah
Port A6 or Port D6, rising or falling input edge
001Ch
Port A5 or Port D5, rising or falling input edge
001Eh
Port A4 or Port D4, rising or falling input edge
0020h
Port A3 or Port D3, rising or falling input edge
0022h
Port A2 or Port D2, rising or falling input edge
0024h
Port A1 or Port D1, rising or falling input edge
0026h
Port A0 or Port D0, rising or falling input edge
0028h
Timer 3 (not available in the 44-pin package)
002Ah
UART 1 receiver
002Ch
UART 1 transmitter
002Eh
DMA
0030h
Port C3, both input edges
0032h
Port C2, both input edges
0034h
Port C1, both input edges
0036h
Port C0, both input edges
Lowest
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Architecture
Figure 11 displays a block diagram of the interrupt controller.
High
Priority
Internal Interrupts
Interrupt Request Latches and Control
Port Interrupts
Vector
Medium
Priority
Priority
Mux
IRQ Request
Low
Priority
Figure 11. Interrupt Controller Block Diagram
Operation
This section describes the operational aspects of the following functions.
Master Interrupt Enable: see page 49
Interrupt Vectors and Priority: see page 50
Interrupt Assertion: see page 50
Software Interrupt Assertion: see page 51
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control Register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
•
•
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Executing an Return from Interrupt (IRET) instruction
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•
Writing a 1 to the IRQE bit in the Interrupt Control Register
Interrupts are globally disabled by any of the following operations:
•
•
•
•
•
•
Execution of a Disable Interrupt (DI) instruction
eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller
Writing a 0 to the IRQE bit in the Interrupt Control Register
Reset
Executing a trap instruction
Illegal instruction trap
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all of
the interrupts were enabled with identical interrupt priority (all as Level 2 interrupts, for
example), then the interrupt priority would be assigned from highest to lowest, as specified in Table 23. Level 3 interrupts always have higher priority than Level 2 interrupts
which, in turn, always have higher priority than Level 1 interrupts. Within each interrupt
priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in Table 23.
Resets, Watchdog Timer interrupts (if enabled), and illegal instruction traps always have
highest priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period (single pulse). When the interrupt request is acknowledged by the eZ8 CPU, the corresponding bit in the Interrupt Request Register is cleared until the next interrupt occurs. Writing a
0 to the corresponding bit in the Interrupt Request Register likewise clears the interrupt
request.
Caution: Zilog recommends not using a coding style that clears bits in the Interrupt Request registers. All incoming interrupts received between execution of the first LDX command
and the final LDX command are lost. See Example 1, which follows.
Example 1. A poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
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To avoid missing interrupts, use the coding style in Example 2 to clear bits in the Interrupt
Request 0 Register:
Example 2. A good coding style that avoids lost interrupt requests:
ANDX IRQ0, MASK
Software Interrupt Assertion
Program code can generate interrupts directly. Writing a 1 to the appropriate bit in the
Interrupt Request Register triggers an interrupt (assuming that interrupt is enabled). When
the interrupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request
Register is automatically cleared to 0.
Caution: Zilog recommends not using a coding style to generate software interrupts by setting bits
in the Interrupt Request registers. All incoming interrupts received between execution of
the first LDX command and the final LDX command are lost. See Example 3, which follows.
Example 3. A poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, use the coding style in Example 4 to set bits in the Interrupt
Request registers:
Example 4. A good coding style that avoids lost interrupt requests:
ORX IRQ0, MASK
Interrupt Control Register Definitions
For all interrupts other than the Watchdog Timer interrupt, the interrupt control registers
enable individual interrupts, set interrupt priorities, and indicate interrupt requests.
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) Register, shown in Table 24, stores the interrupt requests
for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ0 Register becomes 1. If interrupts are globally
enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8
CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the
Interrupt Request 0 Register to determine if any interrupt requests are pending.
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Table 24. Interrupt Request 0 Register (IRQ0)
Bit
Field
7
6
5
4
3
2
1
0
T2I
T1I
T0I
U0RXI
U0TXI
I2CI
SPII
ADCI
RESET
0
R/W
R/W
Address
FC0h
Bit
Description
[7]
T2I
Timer 2 Interrupt Request
0 = No interrupt request is pending for Timer 2.
1 = An interrupt request from Timer 2 is awaiting service.
[6]
T1I
Timer 1 Interrupt Request
0 = No interrupt request is pending for Timer 1.
1 = An interrupt request from Timer 1 is awaiting service.
[5]
T0I
Timer 0 Interrupt Request
0 = No interrupt request is pending for Timer 0.
1 = An interrupt request from Timer 0 is awaiting service.
[4]
U0RXI
UART 0 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 0 receiver.
1 = An interrupt request from the UART 0 receiver is awaiting service.
[3]
U0TXI
UART 0 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 0 transmitter.
1 = An interrupt request from the UART 0 transmitter is awaiting service.
[2]
I2CI
I2C Interrupt Request
0 = No interrupt request is pending for the I2C.
1 = An interrupt request from the I2C is awaiting service.
[1]
SPII
SPI Interrupt Request
0 = No interrupt request is pending for the SPI.
1 = An interrupt request from the SPI is awaiting service.
[0]
ADCI
ADC Interrupt Request
0 = No interrupt request is pending for the Analog-to-Digital Converter.
1 = An interrupt request from the Analog-to-Digital Converter is awaiting service.
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Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) Register, shown in Table 25, stores interrupt requests for
both vectored and polled interrupts. When a request is presented to the interrupt controller,
the corresponding bit in the IRQ1 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 1 Register to determine if any interrupt requests are pending.
For each pin, only 1 of either Port A or Port D can be enabled for interrupts at any one
time. Port selection (A or D) is determined by the values in the Interrupt Port Select Register (IRQPS): see page 60.
Table 25. Interrupt Request 1 Register (IRQ1)
Bit
Field
7
6
5
4
3
2
1
0
PAD7I
PAD6I
PAD5I
PAD4I
PAD3I
PAD2I
PAD1I
PAD0I
RESET
0
R/W
R/W
Address
FC3h
Bit
Description
[7:0]
PADxI
Port A or Port D Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port A or Port D pin x.
1 = An interrupt request from GPIO Port A or Port D pin x is awaiting service.
Note: x indicates the specific GPIO Port A or D pin in the range [7:0].
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Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) Register, shown in Table 26, stores interrupt requests for
both vectored and polled interrupts. When a request is presented to the interrupt controller,
the corresponding bit in the IRQ2 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 1 Register to determine if any interrupt requests are pending.
Table 26. Interrupt Request 2 Register (IRQ2)
Bit
Field
7
6
5
4
3
2
1
0
T3I
U1RXI
U1TXI
DMAI
PC3I
PC2I
PC1I
PC0I
RESET
0
R/W
R/W
Address
FC6h
Bit
Description
[7]
T3I
Timer 3 Interrupt Request
0 = No interrupt request is pending for Timer 3.
1 = An interrupt request from Timer 3 is awaiting service.
[6]
U1RXI
UART 1 Receive Interrupt Request
0 = No interrupt request is pending for the UART1 receiver.
1 = An interrupt request from UART1 receiver is awaiting service.
[5]
U1TXI
UART 1 Transmit Interrupt Request
0 = No interrupt request is pending for the UART 1 transmitter.
1 = An interrupt request from the UART 1 transmitter is awaiting service.
[4]
DMAI
DMA Interrupt Request
0 = No interrupt request is pending for the DMA.
1 = An interrupt request from the DMA is awaiting service.
[3:0]
PCxI
Port C Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
Note: x indicates the specific GPIO Port C pin in the range [3:0].
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IRQ0 Enable High and Low Bit Registers
Table 27 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit registers, shown in Tables 28 and 29, form a priority-encoded enabling for interrupts in the
Interrupt Request 0 Register. Priority is generated by setting bits in each register.
Table 27. IRQ0 Enable and Priority Encoding
IRQ0ENH[x]
IRQ0ENL[x]
Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
Note: x indicates register bits in the range [7:0].
Table 28. IRQ0 Enable High Bit Register (IRQ0ENH)
Bit
Field
7
6
5
4
3
2
1
0
T2ENH
T1ENH
T0ENH
U0RENH
U0TENH
I2CENH
SPIENH
ADCENH
RESET
0
R/W
R/W
Address
FC1h
Bit
Description
[7]
T2ENH
Timer 2 Interrupt Request Enable High Bit
[6]
T1ENH
Timer 1 Interrupt Request Enable High Bit
[5]
T0ENH
Timer 0 Interrupt Request Enable High Bit
[4]
UART 0 Receive Interrupt Request Enable High Bit
U0RENH
[3]
UART 0 Transmit Interrupt Request Enable High Bit
U0TENH
[2]
I2CENH
I2C Interrupt Request Enable High Bit
[1]
SPIENH
SPI Interrupt Request Enable High Bit
[0]
ADC Interrupt Request Enable High Bit
ADCENH
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Table 29. IRQ0 Enable Low Bit Register (IRQ0ENL)
Bit
Field
7
6
5
4
3
2
1
0
T2ENL
T1ENL
T0ENL
U0RENL
U0TENL
I2CENL
SPIENL
ADCENL
RESET
0
R/W
R/W
Address
FC2h
Bit
Description
[7]
T2ENL
Timer 2 Interrupt Request Enable Low Bit
[6]
T1ENL
Timer 1 Interrupt Request Enable Low Bit
[5]
T0ENL
Timer 0 Interrupt Request Enable Low Bit
[4]
UART 0 Receive Interrupt Request Enable Low Bit
U0RENL
[3]
UART 0 Transmit Interrupt Request Enable Low Bit
U0TENL
[2]
I2CENL
I2C Interrupt Request Enable Low Bit
[1]
SPIENL
SPI Interrupt Request Enable Low Bit
[0]
ADC Interrupt Request Enable Low Bit
ADCENL
IRQ1 Enable High and Low Bit Registers
Table 30 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit registers, shown in Tables 31 and 32, form a priority-encoded enabling for interrupts in the
Interrupt Request 1 Register. Priority is generated by setting bits in each register.
Table 30. IRQ1 Enable and Priority Encoding
IRQ1ENH[x]
IRQ1ENL[x]
Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
Note: x indicates register bits in the range [7:0].
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Table 31. IRQ1 Enable High Bit Register (IRQ1ENH)
Bit
Field
RESET
R/W
7
6
5
4
3
2
1
0
PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC4h
Bit
Description
[7:0]
PADxENH
Port A or Port D Bit[x] Interrupt Request Enable High Bit
To select either Port A or Port D as the interrupt source, see the Interrupt Port Select Register on page 60.
Note: x indicates register bits in the range [7:0].
Table 32. IRQ1 Enable Low Bit Register (IRQ1ENL)
Bit
Field
RESET
R/W
7
6
5
4
3
2
1
0
PAD7ENL PAD6ENL PAD5ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL PAD0ENL
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC5h
Bit
Description
[7:0]
PADxENL
Port A or Port D Bit[x] Interrupt Request Enable Low Bit
To select either Port A or Port D as the interrupt source, see the Interrupt Port Select Register on page 60.
Note: x indicates register bits in the range [7:0].
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IRQ2 Enable High and Low Bit Registers
Table 33 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit registers, shown in Tables 34 and 35, form a priority-encoded enabling for interrupts in the
Interrupt Request 2 Register. Priority is generated by setting bits in each register.
Table 33. IRQ2 Enable and Priority Encoding
IRQ2ENH[x]
IRQ2ENL[x]
Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
Note: x indicates register bits in the range [7:0].
Table 34. IRQ2 Enable High Bit Register (IRQ2ENH)
Bit
Field
7
6
5
4
3
2
1
0
T3ENH
U1RENH
U1TENH
DMAENH
C3ENH
C2ENH
C1ENH
C0ENH
RESET
0
R/W
R/W
Address
FC7h
Bit
Description
[7]
T3ENH
Timer 3 Interrupt Request Enable High Bit
[6]
UART 1 Receive Interrupt Request Enable High Bit
U1RENH
[5]
UART 1 Transmit Interrupt Request Enable High Bit
U1TENH
[4]
DMA Interrupt Request Enable High Bit
DMAENH
[3]
C3ENH
Port C3 Interrupt Request Enable High Bit
[2]
C2ENH
Port C2 Interrupt Request Enable High Bit
[1]
C1ENH
Port C1 Interrupt Request Enable High Bit
[0]
C0ENH
Port C0 Interrupt Request Enable High Bit
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Table 35. IRQ2 Enable Low Bit Register (IRQ2ENL)
Bit
Field
7
6
5
4
3
2
1
0
T3ENL
U1RENL
U1TENL
DMAENL
C3ENL
C2ENL
C1ENL
C0ENL
RESET
0
R/W
R/W
Address
FC8h
Bit
Description
[7]
T3ENL
Timer 3 Interrupt Request Enable Low Bit
[6]
UART 1 Receive Interrupt Request Enable Low Bit
U1RENL
[5]
UART 1 Transmit Interrupt Request Enable Low Bit
U1TENL
[4]
DMA Interrupt Request Enable Low Bit
DMAENL
[3]
C3ENL
Port C3 Interrupt Request Enable Low Bit
[2]
C2ENL
Port C2 Interrupt Request Enable Low Bit
[1]
C1ENL
Port C1 Interrupt Request Enable Low Bit
[0]
C0ENL
Port C0 Interrupt Request Enable Low Bit
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Interrupt Edge Select Register
The Interrupt Edge Select (IRQES) Register, shown in Table 36, determines whether an
interrupt is generated for the rising edge or falling edge on the selected GPIO port input
pin. The Interrupt Port Select Register selects between Port A and Port D for the individual interrupts.
Table 36. Interrupt Edge Select Register (IRQES)
Bit
Field
7
6
5
4
3
2
1
0
IES7
IES6
IES5
IES4
IES3
IES2
IES1
IES0
RESET
0
R/W
R/W
Address
FCDh
Bit
Description
[7:0]
IESx
Interrupt Edge Select x
The minimum pulse width should be greater than 1 system clock to guarantee capture of the
edge triggered interrupt. Shorter pulses may be captured but not guaranteed.
0 = An interrupt request is generated on the falling edge of the PAx/PDx input.
1 = An interrupt request is generated on the rising edge of the PAx/PDx input.
Note: x indicates specific GPIO port pins in the range [7:0].
Interrupt Port Select Register
The Port Select (IRQPS) Register, shown in Table 37, determines the port pin that generates the PAx/PDx interrupts. This register allows either Port A or Port D pins to be used as
interrupts. The Interrupt Edge Select Register controls the active interrupt edge.
Table 37. Interrupt Port Select Register (IRQPS)
Bit
Field
7
6
5
4
3
2
1
0
PAD7S
PAD6S
PAD5S
PAD4S
PAD3S
PAD2S
PAD1S
PAD0S
RESET
0
R/W
R/W
Address
FCEh
Bit
Description
[7:0]
PADxS
PAx/PDx Selection
0 = PAx is used for the interrupt for PAx/PDx interrupt request.
1 = PDx is used for the interrupt for PAx/PDx interrupt request.
Note: x indicates specific GPIO port pins in the range [7:0].
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Interrupt Control Register
The Interrupt Control (IRQCTL) Register, shown in Table 38, contains the master enable
bit for all interrupts.
Table 38. Interrupt Control Register (IRQCTL)
Bit
Field
7
5
4
3
IRQE
RESET
R/W
6
2
1
0
Reserved
0
R/W
Address
R
FCFh
Bit
Description
[7]
IRQE
Interrupt Request Enable
This bit is set to 1 by execution of an EI or IRET instruction, or by a direct register write of a 1
to this bit. It is reset to 0 by executing a DI instruction, eZ8 CPU acknowledgement of an interrupt request, or a Reset.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
[6:0]
Reserved
These pins are reserved and must be programmed to 000000.
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Timers
The Z8 Encore! XP F64xx Series products contain up to four 16-bit reloadable timers that
can be used for timing, event counting or generation of pulse-width modulated signals.
The timers’ features include:
•
•
•
•
•
16-bit reload counter
•
•
Timer output pin
Programmable prescaler with prescale values from 1 to 128
PWM output generation
Capture and compare capability
External input pin for timer input, clock gating, or capture signal. External input pin
signal frequency is limited to a maximum of one-fourth the system clock frequency.
Timer interrupt
In addition to the timers described in this chapter, the baud rate generators for any unused
UART, SPI or I2C peripherals can also be used to provide basic timing functionality. For
information about using the baud rate generators as timers, see the respective serial communication peripheral. Timer 3 is unavailable in the 44-pin package devices.
Architecture
Figure 12 displays the architecture of the timers.
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Timer Block
Block
Control
16-Bit
Reload Register
System
Clock
Compare
Timer
Control
Data
Bus
Interrupt,
PWM,
and
Timer Output
Control
Timer
Input
Gate
Input
16-Bit
PWM/Compare
Timer
Output
Compare
16-Bit Counter
with Prescaler
Timer
Interrupt
Capture
Input
Figure 12. Timer Block Diagram
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value
0001h into the Timer Reload High and Low Byte registers and setting the prescale value
to 1. Maximum time-out delay is set by loading the value 0000h into the Timer Reload
High and Low Byte registers and setting the prescale value to 128. If the Timer reaches
FFFFh, the timer rolls over to 0000h and continues counting.
Timer Operating Modes
The timers can be configured to operate in the following modes:
One-Shot Mode
In One-Shot Mode, the timer counts up to the 16-bit reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. Upon reaching
the reload value, the timer generates an interrupt and the count value in the Timer High
and Low Byte registers is reset to 0001h. Then, the timer is automatically disabled and
stops counting.
Also, if the timer output alternate function is enabled, the timer output pin changes state
for one system clock cycle (from Low to High or from High to Low) upon timer reload. If
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it is appropriate to have the timer output make a permanent state change upon a One-Shot
time-out, first set the TPOL bit in the Timer Control 1 Register to the start value before
beginning One-Shot Mode. Then, after starting the timer, set TPOL to the opposite bit
value.
Observe the following procedure for configuring a timer for One-Shot Mode and initiating
the count:
1. Write to the Timer Control 1 Register to:
– Disable the timer
– Configure the timer for One-Shot Mode
– Set the prescale value
– If using the timer output alternate function, set the initial output level (High or
Low)
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the timer output function, configure the associated GPIO port pin for the timer
output alternate function.
6. Write to the Timer Control 1 Register to enable the timer and initiate counting.
In One-Shot Mode, the system clock always provides the timer input. The timer period is
calculated using the following equation:
Reload Value – Start Value Prescale
ONE-SHOT Mode Time-Out Period (s) = ------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
Continuous Mode
In Continuous Mode, the timer counts up to the 16-bit reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. Upon reaching
the reload value, the timer generates an interrupt, the count value in the Timer High and
Low Byte registers is reset to 0001h and counting resumes. Also, if the timer output alternate function is enabled, the timer output pin changes state (from Low to High or from
High to Low) upon timer reload.
Observe the following procedure for configuring a timer for Continuous Mode and initiating the count:
1. Write to the Timer Control 1 Register to:
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–
–
–
–
Disable the timer
Configure the timer for Continuous Mode
Set the prescale value
If using the timer output alternate function, set the initial output level (High or
Low)
2. Write to the Timer High and Low Byte registers to set the starting count value (usually
0001h), affecting only the first pass in Continuous Mode. After the first timer reload
in Continuous Mode, counting always begins at the reset value of 0001h.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the timer output function, configure the associated GPIO port pin for the timer
output alternate function.
6. Write to the Timer Control 1 Register to enable the timer and initiate counting.
In Continuous Mode, the system clock always provides the timer input. The timer period
is calculated using the following equation:
Reload Value Prescale
CONTINUOUS Mode Time-Out Period (s) = -----------------------------------------------------------------------System Clock Frequency (Hz)
If an initial starting value other than 0001h is loaded into the Timer High and Low Byte
registers, the One-Shot Mode equation must be used to determine the first time-out period.
Counter Mode
In Counter Mode, the timer counts input transitions from a GPIO port pin. The timer input
is taken from the GPIO port pin timer input alternate function. The TPOL bit in the Timer
Control 1 Register selects whether the count occurs on the rising edge or the falling edge
of the timer input signal. In Counter Mode, the prescaler is disabled.
Caution: The input frequency of the timer input signal must not exceed one-fourth the system
clock frequency.
Upon reaching the reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001h and counting resumes. Also, if the timer output alternate function is
enabled, the timer output pin changes state (from Low to High or from High to Low) at
timer reload.
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Observe the following procedure for configuring a timer for Counter Mode and initiating
the count:
1. Write to the Timer Control 1 Register to:
– Disable the timer.
– Configure the timer for Counter Mode.
– Select either the rising edge or falling edge of the timer input signal for the count.
This also sets the initial logic level (High or Low) for the timer output alternate
function. However, the timer output function does not have to be enabled.
2. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in Counter Mode. After the first timer reload in Counter
Mode, counting always begins at the reset value of 0001h. Generally, in Counter
Mode the Timer High and Low Byte registers must be written with the value 0001h.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. Configure the associated GPIO port pin for the timer input alternate function.
6. If using the timer output function, configure the associated GPIO port pin for the timer
output alternate function.
7. Write to the Timer Control 1 Register to enable the timer.
In Counter Mode, the number of timer input transitions since the timer start is calculated
using the following equation:
COUNTER Mode Timer Input Transitions = Current Count Value – Start Value
PWM Mode
In PWM Mode, the timer outputs a Pulse-Width Modulator (PWM) output signal through
a GPIO port pin. The timer input is the system clock. The timer first counts up to the 16bit PWM match value stored in the Timer PWM High and Low Byte registers. When the
timer count value matches the PWM value, the timer output toggles. The timer continues
counting until it reaches the reload value stored in the Timer Reload High and Low Byte
registers. Upon reaching the reload value, the timer generates an interrupt, the count value
in the Timer High and Low Byte registers is reset to 0001h and counting resumes.
If the TPOL bit in the Timer Control 1 Register is set to 1, the timer output signal begins
as a High (1) and then transitions to a Low (0) when the timer value matches the PWM
value. The timer output signal returns to a High (1) after the timer reaches the reload value
and is reset to 0001h.
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If the TPOL bit in the Timer Control 1 Register is set to 0, the timer output signal begins
as a Low (0) and then transitions to a High (1) when the timer value matches the PWM
value. The timer output signal returns to a Low (0) after the timer reaches the reload value
and is reset to 0001h.
Observe the following procedure for configuring a timer for PWM Mode and initiating the
PWM operation:
1. Write to the Timer Control 1 Register to:
– Disable the timer
– Configure the timer for PWM Mode
– Set the prescale value
– Set the initial logic level (High or Low) and PWM High/Low transition for the
timer output alternate function
2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001h). This only affects the first pass in PWM Mode. After the first timer reset
in PWM Mode, counting always begins at the reset value of 0001h.
3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM
period). The reload value must be greater than the PWM value.
5. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
6. Configure the associated GPIO port pin for the timer output alternate function.
7. Write to the Timer Control 1 Register to enable the timer and initiate counting.
The PWM period is calculated using the following equation:
Reload Value Prescale
PWM Period (s) = -----------------------------------------------------------------------System Clock Frequency (Hz)
If an initial starting value other than 0001h is loaded into the Timer High and Low Byte
registers, the One-Shot Mode equation must be used to determine the first PWM time-out
period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is calculated
using the following equation:
Reload Value – PWM Value
PWM Output High Time Ratio (%) = --------------------------------------------------------------------- 100
Reload Value
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If TPOL is set to 1, the ratio of the PWM output High time to the total period is calculated
using the following equation:
PWM Value
PWM Output High Time Ratio (%) = -------------------------------- 100
Reload Value
Capture Mode
In Capture Mode, the current timer count value is recorded when the appropriate external
timer input transition occurs. The capture count value is written to the Timer PWM High
and Low Byte Registers. The timer input is the system clock. The TPOL bit in the Timer
Control 1 Register determines if the capture occurs on a rising edge or a falling edge of the
timer input signal. When the capture event occurs, an interrupt is generated and the timer
continues counting.
The timer continues counting up to the 16-bit reload value stored in the Timer Reload
High and Low Byte registers. Upon reaching the reload value, the timer generates an interrupt and continues counting.
Observe the following procedure for configuring a timer for Capture Mode and initiating
the count:
1. Write to the Timer Control 1 Register to:
– Disable the timer
– Configure the timer for Capture Mode
– Set the prescale value
– Set the capture edge (rising or falling) for the timer input
2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001h).
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. Clear the Timer PWM High and Low Byte registers to 0000h. This allows the software to determine if interrupts were generated by either a capture event or a reload. If
the PWM High and Low Byte registers still contain 0000h after the interrupt, then the
interrupt was generated by a reload.
5. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
6. Configure the associated GPIO port pin for the timer input alternate function.
7. Write to the Timer Control 1 Register to enable the timer and initiate counting.
In Capture Mode, the elapsed time from timer start to capture event can be calculated
using the following equation:
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Capture Value – Start Value Prescale
Capture Elapsed Time (s) = --------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
Compare Mode
In Compare Mode, the timer counts up to the 16-bit maximum compare value stored in the
Timer Reload High and Low Byte registers. The timer input is the system clock. Upon
reaching the compare value, the timer generates an interrupt and counting continues (the
timer value is not reset to 0001h). Also, if the timer output alternate function is enabled,
the timer output pin changes state (from Low to High or from High to Low) upon compare.
If the Timer reaches FFFFh, the timer rolls over to 0000h and continue counting.
Observe the following procedure for configuring a timer for Compare Mode and initiating
the count:
1. Write to the Timer Control 1 Register to:
– Disable the timer
– Configure the timer for Compare Mode
– Set the prescale value
– Set the initial logic level (High or Low) for the timer output alternate function, if
appropriate
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the compare value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the timer output function, configure the associated GPIO port pin for the timer
output alternate function.
6. Write to the Timer Control 1 Register to enable the timer and initiate counting.
In Compare Mode, the system clock always provides the timer input. The compare time is
calculated using the following equation:
Compare Value – Start Value PrescaleCOMPARE Mode Time (s) = ----------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
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Gated Mode
In Gated Mode, the timer counts only when the timer input signal is in its active state
(asserted), as determined by the TPOL bit in the Timer Control 1 Register. When the timer
input signal is asserted, counting begins. A timer interrupt is generated when the timer
input signal is deasserted or a timer reload occurs. To determine if a timer input signal
deassertion generated the interrupt, read the associated GPIO input value and compare to
the value stored in the TPOL bit.
The timer counts up to the 16-bit reload value stored in the Timer Reload High and Low
Byte registers. The timer input is the system clock. When reaching the reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to 0001h and counting resumes (assuming the timer input signal is still asserted).
Also, if the timer output alternate function is enabled, the timer output pin changes state
(from Low to High or from High to Low) at timer reset.
Observe the following procedure for configuring a timer for Gated Mode and initiating the
count:
1. Write to the Timer Control 1 Register to:
– Disable the timer
– Configure the timer for Gated Mode
– Set the prescale value
2. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in Gated Mode. After the first timer reset in Gated Mode,
counting always begins at the reset value of 0001h.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. Configure the associated GPIO port pin for the timer input alternate function.
6. Write to the Timer Control 1 Register to enable the timer.
7. Assert the timer input signal to initiate the counting.
Capture/Compare Mode
In Capture/Compare Mode, the timer begins counting on the first external timer input transition. The appropriate transition (rising edge or falling edge) is set by the TPOL bit in the
Timer Control 1 Register. The timer input is the system clock.
Every subsequent appropriate transition (after the first) of the timer input signal captures
the current count value. The capture value is written to the Timer PWM High and Low
Byte Registers. When the capture event occurs, an interrupt is generated, the count value
in the Timer High and Low Byte registers is reset to 0001h, and counting resumes.
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If no capture event occurs, the timer counts up to the 16-bit compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the compare value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001h and counting resumes.
Observe the following procedure for configuring a timer for Capture/Compare Mode and
initiating the count:
1. Write to the Timer Control 1 Register to:
– Disable the timer
– Configure the timer for Capture/Compare Mode
– Set the prescale value
– Set the capture edge (rising or falling) for the timer input
2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001h).
3. Write to the Timer Reload High and Low Byte registers to set the compare value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. Configure the associated GPIO port pin for the timer input alternate function.
6. Write to the Timer Control 1 Register to enable the timer.
7. Counting begins on the first appropriate transition of the timer input signal. No interrupt is generated by this first edge.
In Compare Mode, the elapsed time from timer start to capture event can be calculated
using the following equation:
Capture Value – Start Value Prescale
Capture Elapsed Time (s) = --------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
Reading the Timer Count Values
The current count value in the timers can be read while counting (enabled). This capability
has no effect on timer operation. When the timer is enabled and the Timer High Byte Register is read, the contents of the Timer Low Byte Register are placed in a holding register.
A subsequent read from the Timer Low Byte Register returns the value in the holding register. This operation allows accurate reads of the full 16-bit timer count value while
enabled. When the timers are not enabled, a read from the Timer Low Byte Register
returns the actual value in the counter.
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72
Timer Output Signal Operation
A timer output is a GPIO port pin alternate function. Generally, the timer output is toggled
every time the counter is reloaded.
Timer Control Register Definitions
This section defines the features of the following Timer Control registers.
Timer 0–3 High and Low Byte Registers: see page 72
Timer Reload High and Low Byte Registers: see page 74
Timer 0–3 PWM High and Low Byte Registers: see page 75
Timer 0–3 Control 0 Registers: see page 76
Timer 0–3 Control 1 Registers: see page 77
Timers 0–2 are available in all packages. Timer 3 is only available in 64-, 68- and 80-pin
packages.
Timer 0–3 High and Low Byte Registers
The Timer 0–3 High and Low Byte (TxH and TxL) registers, shown in Tables 39 and 40,
contain the current 16-bit timer count value. When the timer is enabled, a read from TxH
causes the value in TxL to be stored in a temporary holding register. A read from TMRL
always returns this temporary register when the timers are enabled. When the timer is disabled, reads from the TMRL read the register directly.
Writing to the Timer High and Low Byte registers while the timer is enabled is not recommended. There are no temporary holding registers available for write operations, so simultaneous 16-bit writes are not possible. If either the Timer High or Low Byte registers are
written during counting, the 8-bit written value is placed in the counter (High or Low
Byte) at the next clock edge. The counter continues counting from the new value.
Timer 3 is unavailable in 44-pin packages.
Table 39. Timer 0–3 High Byte Register (TxH)
Bit
7
Field
RESET
R/W
Address
PS019926-1114
6
5
4
3
2
1
0
TH
0
R/W
F00h, F08h, F10h, F18h
PRELIMINARY
Timer Control Register Definitions
Z8 Encore! XP® F64xx Series
Product Specification
73
Table 40. Timer 0–3 Low Byte Register (TxL)
Bit
7
6
5
4
Field
3
2
1
0
TL
RESET
0
R/W
1
R/W
Address
F01h, F09h, F11h, F19h
Bit
Description
[7:0]
TH, TL
Timer High and Low Bytes
These 2 bytes, {TMRH[7:0], TMRL[7:0]}, contain the current 16-bit timer count value.
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Z8 Encore! XP® F64xx Series
Product Specification
74
Timer Reload High and Low Byte Registers
The Timer 0–3 Reload High and Low Byte (TxRH and TxRL) registers, shown in
Tables 41 and 42, store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the
Timer Reload High Byte Register are stored in a temporary holding register. When a write
to the Timer Reload Low Byte Register occurs, the temporary holding register value is
written to the Timer High Byte Register. This operation allows simultaneous updates of
the 16-bit timer reload value.
In Compare Mode, the Timer Reload High and Low Byte registers store the 16-bit compare value.
Table 41. Timer 0–3 Reload High Byte Register (TxRH)
Bit
7
6
5
4
Field
3
2
1
0
1
0
TRH
RESET
1
R/W
R/W
Address
F02h, F0Ah, F12h, F1Ah
Table 42. Timer 0–3 Reload Low Byte Register (TxRL)
Bit
7
Field
6
5
4
3
2
TRL
RESET
1
R/W
R/W
Address
F03h, F0Bh, F13h, F1Bh
Bit
Description
[7:0]
TRH,
TRL
Timer Reload Register High and Low
These two bytes form the 16-bit reload value, {TRH[7:0], TRL[7:0]}. This value sets the maximum count value which initiates a timer reload to 0001h. In Compare Mode, these two bytes
form the 16-bit compare value.
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Z8 Encore! XP® F64xx Series
Product Specification
75
Timer 0–3 PWM High and Low Byte Registers
The Timer 0–3 PWM High and Low Byte (TxPWMH and TxPWML) registers, shown in
Tables 43 and 44, are used for Pulse-Width Modulator (PWM) operations. These registers
also store the capture values for the Capture and Capture/Compare modes.
Table 43. Timer 0–3 PWM High Byte Register (TxPWMH)
Bit
7
6
5
4
Field
3
2
1
0
1
0
PWMH
RESET
0
R/W
R/W
Address
F04h, F0Ch, F14h, F1Ch
Table 44. Timer 0–3 PWM Low Byte Register (TxPWML)
Bit
7
Field
6
5
4
3
2
PWML
RESET
0
R/W
R/W
Address
F05h, F0Dh, F15h, F1Dh
Bit
Description
[7:0]
PWMH,
PWML
Pulse-Width Modulator High and Low Bytes
These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the current
16-bit timer count. When a match occurs, the PWM output changes state. The PWM output
value is set by the TPOL bit in the Timer Control 1 Register (TxCTL1) Register. The TxPWMH
and TxPWML registers also store the 16-bit captured timer value when operating in Capture or
Capture/Compare modes.
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Z8 Encore! XP® F64xx Series
Product Specification
76
Timer 0–3 Control 0 Registers
The Timer 0–3 Control 0 (TxCTL0) registers, shown in Tables 45 and 46, allow cascading
of the timers.
Table 45. Timer 0–3 Control 0 Register (TxCTL0)
Bit
7
Field
6
Reserved
RESET
5
4
3
CSC
2
1
0
Reserved
0
R/W
R/W
Address
F06h, F0Eh, F16h, F1Eh
Bit
Description
[7:5]
Reserved
These bits are reserved and must be programmed to 000.
[4]
CSC
Cascade Timers
0 = Timer input signal comes from the pin.
1 = For Timer 0, the input signal is connected to Timer 3 output.
For Timer 1, the input signal is connected to the Timer 0 output.
For Timer 2, the input signal is connected to the Timer 1 output.
For Timer 3, the input signal is connected to the Timer 2 output.
[3:0]
Reserved
These bits are reserved and must be programmed to 0000.
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Z8 Encore! XP® F64xx Series
Product Specification
77
Timer 0–3 Control 1 Registers
The Timer 0–3 Control 1 (TxCTL1) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
Table 46. Timer 0–3 Control 1 Register (TxCTL1)
Bit
Field
7
6
TEN
TPOL
RESET
R/W
Address
PS019926-1114
5
4
3
PRES
2
1
0
TMODE
0
R/W
F07h, F0Fh, F17h, F1Fh
PRELIMINARY
Timer Control Register Definitions
Z8 Encore! XP® F64xx Series
Product Specification
78
Bit
Description
[7]
TEN
Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
[6]
TPOL
Timer Input/Output Polarity
Operation of this bit is a function of the current operating mode of the timer.
One-Shot Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled, the timer output signal is complemented upon timer reload.
Continuous Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled, the timer output signal is complemented upon timer reload.
Counter Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled, the timer output signal is complemented upon timer reload.
0 = Count occurs on the rising edge of the timer input signal.
1 = Count occurs on the falling edge of the timer input signal.
PWM Mode
0 = timer output is forced Low (0) when the timer is disabled. When enabled, the timer output is
forced High (1) upon PWM count match and forced Low (0) upon reload.
1 = timer output is forced High (1) when the timer is disabled. When enabled, the timer output
is forced Low (0) upon PWM count match and forced High (1) upon reload.
Capture Mode
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
Compare Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled, the timer output signal is complemented upon timer reload.
Gated Mode
0 = Timer counts when the timer input signal is High (1) and interrupts are generated on the
falling edge of the timer input.
1 = Timer counts when the timer input signal is Low (0) and interrupts are generated on the rising edge of the timer input.
Capture/Compare Mode
0 = Counting is started on the first rising edge of the timer input signal. The current count is
captured on subsequent rising edges of the timer input signal.
1 = Counting is started on the first falling edge of the timer input signal. The current count is
captured on subsequent falling edges of the timer input signal.
Caution: When the timer output alternate function TxOUT on a GPIO port pin is enabled,
TxOUT will change to whatever state the TPOL bit is in. The timer does not need to be enabled
for that to happen. Also, the Port Data Direction Subregister is not needed to be set to output
on TxOUT. Changing the TPOL bit with the timer enabled and running does not immediately
change the TxOUT.
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Bit
Description (Continued)
[5:3]
PRES
Prescale Value
The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7. The prescaler is
reset each time the timer is disabled to ensure proper clock division each time the timer is
restarted.
000 = Divide by 1.
001 = Divide by 2.
010 = Divide by 4.
011 = Divide by 8.
100 = Divide by 16.
101 = Divide by 32.
110 = Divide by 64.
111 = Divide by 128.
[2:0]
TMODE
TIMER Mode
000 = One-Shot Mode.
001 = Continuous Mode.
010 = Counter Mode.
011 = PWM Mode.
100 = Capture Mode.
101 = Compare Mode.
110 = Gated Mode.
111 = Capture/Compare Mode.
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Z8 Encore! XP® F64xx Series
Product Specification
80
Watchdog Timer
The Watchdog Timer (WDT) helps protect against corrupt or unreliable software, power
faults and other system-level problems which can place the Z8 Encore! XP F64xx Series
MCU into unsuitable operating states. The features of the Watchdog Timer include:
•
•
•
•
On-chip RC oscillator
A selectable time-out response
WDT time-out response: Reset or interrupt
24-bit programmable time-out value
Operation
The Watchdog Timer is a retriggerable one-shot timer that resets or interrupts the Z8
Encore! XP F64xx Series devices when the WDT reaches its terminal count. The Watchdog Timer uses its own dedicated on-chip RC oscillator as its clock source. The Watchdog
Timer has only two modes of operation: ON and OFF. After it is enabled, it always counts
and must be refreshed to prevent a time-out. An enable can be performed by executing the
WDT instruction or by setting the WDT_AO option bit. This WDT_AO bit enables the
Watchdog Timer to operate continuously, even if a WDT instruction has not been executed.
The Watchdog Timer is a 24-bit reloadable downcounter that uses three 8-bit registers in
the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is
calculated using the following equation:
WDT Reload Value
WDT Time-out Period (ms) = -----------------------------------------------10
In the above equation, the WDT reload value is the decimal value of the 24-bit value provided by {WDTU[7:0], WDTH[7:0], WDTL[7:0]}; the typical Watchdog Timer RC oscillator frequency is 10 kHz. The Watchdog Timer cannot be refreshed after it reaches
000002h. The WDT reload value must not be set to values below 000004h.
Table 47 lists approximate time-out delays for the minimum and maximum WDT reload
values.
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Z8 Encore! XP® F64xx Series
Product Specification
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Table 47. Watchdog Timer Approximate Time-Out Delays
WDT Reload
Value
(Hex)
WDT Reload
Value
(Decimal)
000004
FFFFFF
Approximate Time-Out Delay
(with 10 kHz typical WDT Oscillator Frequency)
Typical
Description
4
400 µs
Minimum time-out delay
16,777,215
1677.5 s
Maximum time-out delay
Watchdog Timer Refresh
When first enabled, the Watchdog Timer is loaded with the value in the Watchdog Timer
Reload registers. The Watchdog Timer then counts down to 000000h unless a WDT
instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes the
downcounter to be reloaded with the WDT reload value stored in the Watchdog Timer
Reload registers. Counting resumes following the reload operation.
When the Z8 Encore! XP F64xx Series devices are operating in Debug Mode (through the
On-Chip Debugger), the Watchdog Timer is continuously refreshed to prevent spurious
Watchdog Timer time-outs.
Watchdog Timer Time-Out Response
The Watchdog Timer times out when the counter reaches 000000h. A time-out of the
Watchdog Timer generates either an interrupt or a Reset. The WDT_RES option bit determines the time-out response of the Watchdog Timer. For information about programming
of the WDT_RES option bit, see the Option Bits chapter on page 180.
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the Watchdog Timer issues
an interrupt request to the interrupt controller and sets the WDT status bit in the Watchdog
Timer Control Register. If interrupts are enabled, the eZ8 CPU responds to the interrupt
request by fetching the Watchdog Timer interrupt vector and executing code from the vector address. After time-out and interrupt generation, the Watchdog Timer counter rolls
over to its maximum value of FFFFFh and continues counting. The Watchdog Timer
counter is not automatically returned to its reload value.
WDT Interrupt in Stop Mode
If configured to generate an interrupt when a time-out occurs and the Z8 Encore! XP
F64xx Series devices are in Stop Mode, the Watchdog Timer automatically initiates a Stop
Mode Recovery and generates an interrupt request. Both the WDT status bit and the stop
bit in the Watchdog Timer Control Register are set to 1 following WDT time-out in Stop
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Mode. For more information about Stop Mode Recovery, see the Reset and Stop Mode
Recovery chapter on page 28.
If interrupts are enabled, following completion of the Stop Mode Recovery the eZ8 CPU
responds to the interrupt request by fetching the Watchdog Timer interrupt vector and executing code from the vector address.
WDT Reset in Normal Operation
If configured to generate a Reset when a time-out occurs, the Watchdog Timer forces the
device into the Reset state. The WDT status bit in the Watchdog Timer Control Register is
set to 1. For more information about Reset, see the Reset and Stop Mode Recovery chapter
on page 28.
WDT Reset in Stop Mode
If enabled in Stop Mode and configured to generate a Reset when a time-out occurs and
the device is in Stop Mode, the Watchdog Timer initiates a Stop Mode Recovery. Both the
WDT status bit and the stop bit in the Watchdog Timer Control Register are set to 1 following WDT time-out in Stop Mode. Default operation is for the WDT and its RC oscillator to be enabled during Stop Mode.
WDT RC Disable in Stop Mode
To minimize power consumption in Stop Mode, the WDT and its RC oscillator can be disabled in Stop Mode. The following sequence configures the WDT to be disabled when the
Z8 Encore! XP F64xx Series devices enter Stop Mode following execution of a stop
instruction:
1. Write 55h to the Watchdog Timer Control Register (WDTCTL).
2. Write AAh to the Watchdog Timer Control Register (WDTCTL).
3. Write 81h to the Watchdog Timer Control Register (WDTCTL) to configure the WDT
and its oscillator to be disabled during Stop Mode. Alternatively, write 00h to the
Watchdog Timer Control Register (WDTCTL) as the third step in this sequence to
reconfigure the WDT and its oscillator to be enabled during Stop Mode.
This sequence only affects WDT operation in Stop Mode.
Watchdog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watchdog Timer (WDTCTL) Control Register address
unlocks the three Watchdog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to
allow changes to the time-out period. These write operations to the WDTCTL Register
address produce no effect on the bits in the WDTCTL Register. The locking mechanism
prevents spurious writes to the Reload registers. Observe the following procedure to
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Product Specification
83
unlock the Watchdog Timer Reload Byte registers (WDTU, WDTH, and WDTL) for write
access.
1. Write 55h to the Watchdog Timer Control Register (WDTCTL).
2. Write AAh to the Watchdog Timer Control Register (WDTCTL).
3. Write the Watchdog Timer Reload Upper Byte Register (WDTU).
4. Write the Watchdog Timer Reload High Byte Register (WDTH).
5. Write the Watchdog Timer Reload Low Byte Register (WDTL).
All steps of the Watchdog Timer reload unlock sequence must be written in the sequence
described above; there must be no other register writes between each of these operations.
If a register write occurs, the lock state machine resets and no further writes can occur,
unless the sequence is restarted. The value in the Watchdog Timer Reload registers is
loaded into the counter when the Watchdog Timer is first enabled and every time a WDT
instruction is executed.
Watchdog Timer Control Register Definitions
This section defines the features of the following Watchdog Timer Control registers.
Watchdog Timer Control Register: see page 83
Watchdog Timer Reload Upper, High and Low Byte Registers: see page 85
Watchdog Timer Control Register
The Watchdog Timer Control (WDTCTL) Register, shown in Table 48, is a read-only register that indicates the source of the most recent Reset event, indicates a Stop Mode
Recovery event, and indicates a Watchdog Timer time-out. Reading this register resets the
upper four bits to 0.
Writing the 55h, AAh unlock sequence to the Watchdog Timer Control (WDTCTL) Register address unlocks the three Watchdog Timer Reload Byte registers (WDTU, WDTH, and
WDTL) to allow changes to the time-out period. These write operations to the WDTCTL
Register address produce no effect on the bits in the WDTCTL Register. The locking
mechanism prevents spurious writes to the Reload registers.
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Z8 Encore! XP® F64xx Series
Product Specification
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Table 48. Watchdog Timer Control Register (WDTCTL)
Bit
Field
7
6
5
4
POR
STOP
WDT
EXT
RESET
3
Reserved
See Table 49.
R/W
2
1
0
SM
0
R
Address
FF0h
Bit
Description
[7]
POR
Power-On Reset Indicator
If this bit is set to 1, a Power-On Reset event occurred. This bit is reset to 0 if a WDT time-out
or Stop Mode Recovery occurs. This bit is also reset to 0 when the register is read.
[6]
STOP
Stop Mode Recovery Indicator
If this bit is set to 1, a Stop Mode Recovery occurred. If the stop and WDT bits are both set to
1, the Stop Mode Recovery occurred due to a WDT time-out. If the stop bit is 1 and the WDT
bit is 0, the Stop Mode Recovery was not caused by a WDT time-out. This bit is reset by a
Power-On Reset or a WDT time-out that occurred while not in Stop Mode. Reading this register
also resets this bit.
[5]
WDT
Watchdog Timer Time-Out Indicator
If this bit is set to 1, a WDT time-out occurred. A Power-On Reset resets this pin. A Stop Mode
Recovery from a change in an input pin also resets this bit. Reading this register resets this bit.
[4]
EXT
External Reset Indicator
If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A Power-On Reset
or a Stop Mode Recovery from a change in an input pin resets this bit. Reading this register
resets this bit.
[3:1]
Reserved
These bits are reserved and must be programmed to 000.
[0]
SM
Stop Mode Configuration Indicator
0 = Watchdog Timer and its internal RC oscillator will continue to operate in Stop Mode.
1 = Watchdog Timer and its internal RC oscillator will be disabled in Stop Mode.
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Z8 Encore! XP® F64xx Series
Product Specification
85
Table 49. Watchdog Timer Events
Reset or Stop Mode Recovery Event
POR
STOP
WDT
EXT
Power-On Reset
1
0
0
0
Reset using RESET pin assertion
0
0
0
1
Reset using Watchdog Timer time-out
0
0
1
0
Reset using the On-Chip Debugger (OCDCTL[1] set to 1)
1
0
0
0
Reset from Stop Mode using DBG Pin driven Low
1
0
0
0
Stop Mode Recovery using GPIO pin transition
0
1
0
0
Stop Mode Recovery using Watchdog Timer time-out
0
1
1
0
Watchdog Timer Reload Upper, High and Low Byte Registers
The Watchdog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) registers, shown in Tables 50 through 52, form the 24-bit reload value that is loaded into the
Watchdog Timer when a WDT instruction executes. The 24-bit reload value is
{WDTU[7:0], WDTH[7:0], WDTL[7:0]}. Writing to these registers sets the appropriate
reload value. Reading from these registers returns the current Watchdog Timer count
value.
Caution: The 24-bit WDT reload value must not be set to a value less than 000004h.
Table 50. Watchdog Timer Reload Upper Byte Register (WDTU)
Bit
7
Field
6
5
4
3
2
1
0
WDTU
RESET
1
R/W
R/W*
Address
FF1h
Note: *R/W = Read returns the current WDT count value; write sets the appropriate reload value.
Bit
Description
[7:0]
WDTU
WDT Reload Upper Byte
Most significant byte, bits[23:16] of the 24-bit WDT reload value.
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Z8 Encore! XP® F64xx Series
Product Specification
86
Table 51. Watchdog Timer Reload High Byte Register (WDTH)
Bit
7
6
5
4
Field
3
2
1
0
WDTH
RESET
1
R/W
R/W*
Address
FF2h
Note: *R/W = Read returns the current WDT count value; write sets the appropriate reload value.
Bit
Description
[7:0]
WDTH
WDT Reload High Byte
Middle byte, bits[15:8] of the 24-bit WDT reload value.
Table 52. Watchdog Timer Reload Low Byte Register (WDTL)
Bit
7
Field
6
5
4
3
2
1
0
WDTL
RESET
1
R/W
R/W*
Address
FF3h
Note: *R/W = Read returns the current WDT count value; write sets the appropriate reload value.
Bit
Description
[7:0]
WDTL
WDT Reload Low
Least significant byte, bits[7:0] of the 24-bit WDT reload value.
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Z8 Encore! XP® F64xx Series
Product Specification
87
Universal Asynchronous Receiver/
Transmitter
The Universal Asynchronous Receiver/Transmitter (UART) is a full-duplex communication channel capable of handling asynchronous data transfers. The UART uses a single
8-bit data mode with selectable parity. Features of the UART include:
•
•
•
•
•
•
•
•
•
•
8-bit asynchronous data transfer
Selectable even- and odd-parity generation and checking
Option of one or two stop bits
Separate transmit and receive interrupts
Framing, parity, overrun and break detection
Separate transmit and receive enables
16-bit Baud Rate Generator (BRG)
Selectable Multiprocessor (9-Bit) Mode with three configurable interrupt schemes
Baud Rate Generator timer mode
Driver Enable output for external bus transceivers
Architecture
The UART consists of three primary functional blocks: Transmitter, Receiver and Baud
Rate Generator. The UART’s transmitter and receiver function independently, but employ
the same baud rate and data format. Figure 13 displays the UART architecture.
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Universal Asynchronous Receiver/
Z8 Encore! XP® F64xx Series
Product Specification
88
Parity Checker
Receiver Control
with address compare
RxD
Receive Shifter
Receive Data
Register
Control Registers
System Bus
Transmit Data
Register
Status Register
Baud Rate
Generator
Transmit Shift
Register
TxD
Transmitter Control
Parity Generator
CTS
DE
Figure 13. UART Block Diagram
Operation
The UART always transmits and receives data in an 8-bit data format, least significant bit
first. An even or odd parity bit can be optionally added to the data stream. Each character
begins with an active Low start bit and ends with either 1 or 2 active High stop bits.
Figures 14 and 15 display the asynchronous data format employed by the UART without
parity and with parity, respectively.
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Z8 Encore! XP® F64xx Series
Product Specification
89
Data Field
Idle State
of Line
Stop Bit(s)
lsb
msb
1
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
0
1
2
Figure 14. UART Asynchronous Data Format without Parity
Data Field
Idle State
of Line
Stop Bit(s)
lsb
msb
1
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Parity
0
1
2
Figure 15. UART Asynchronous Data Format with Parity
Transmitting Data using the Polled Method
Observe the following procedure to transmit data using the polled method of operation:
1. Write to the UART Baud Rate High and Low Byte registers to set the appropriate baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. If Multiprocessor Mode is appropriate, write to the UART Control 1 Register to
enable Multiprocessor (9-Bit) Mode functions.
– Set the Multiprocessor Mode Select (MPEN) to Enable Multiprocessor Mode
4. Write to the UART Control 0 Register to:
– Set the transmit enable bit (TEN) to enable the UART for data transmission
– If parity is appropriate and Multiprocessor Mode is not enabled, set the parity
enable bit (PEN) and select either Even or Odd parity (PSEL)
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90
–
Set or clear the CTSE bit to enable or disable control from the remote receiver
using the CTS pin
5. Check the TDRE bit in the UART Status 0 Register to determine if the Transmit Data
Register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit Data
Register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit
Data Register becomes available to receive new data.
6. Write the UART Control 1 Register to select the outgoing address bit.
7. Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte; clear it if
sending a data byte.
8. Write the data byte to the UART Transmit Data Register. The transmitter automatically transfers the data to the Transmit Shift Register and transmits the data.
9. If appropriate and Multiprocessor Mode is enabled, make any changes to the Multiprocessor Bit Transmitter (MPBT) value.
10. To transmit additional bytes, return to Step 5.
Transmitting Data using the Interrupt-Driven Method
The UART transmitter interrupt indicates the availability of the Transmit Data Register to
accept new data for transmission. Observe the following procedure to configure the UART
for interrupt-driven data transmission:
1. Write to the UART Baud Rate High and Low Byte registers to set the appropriate baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the UART Transmitter interrupt and
set the appropriate priority.
5. If Multiprocessor Mode is appropriate, write to the UART Control 1 Register to
enable Multiprocessor (9-Bit) Mode functions.
6. Set the Multiprocessor Mode Select (MPEN) to Enable Multiprocessor Mode.
7. Write to the UART Control 0 Register to:
– Set the transmit enable bit (TEN) to enable the UART for data transmission
– Enable parity, if appropriate and if Multiprocessor Mode is not enabled, and select
either even or odd parity
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–
Set or clear the CTSE bit to enable or disable control from the remote receiver via
the CTS pin
8. Execute an EI instruction to enable interrupts.
The UART is now configured for interrupt-driven data transmission. Because the UART
Transmit Data Register is empty, an interrupt is generated immediately. When the UART
transmit interrupt is detected, the associated interrupt service routine performs the following functions:
1. Write the UART Control 1 Register to select the outgoing address bit:
– Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte; clear it
if sending a data byte.
2. Write the data byte to the UART Transmit Data Register. The transmitter automatically transfers the data to the Transmit Shift Register and transmits the data.
3. Clear the UART transmit interrupt bit in the applicable Interrupt Request Register.
4. Execute the IRET instruction to return from the interrupt service routine and wait for
the Transmit Data Register to again become empty.
Receiving Data using the Polled Method
Observe the following procedure to configure the UART for polled data reception:
1. Write to the UART Baud Rate High and Low Byte registers to set the appropriate baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Write to the UART Control 1 Register to enable Multiprocessor Mode functions, if
appropriate.
4. Write to the UART Control 0 Register to:
– Set the receive enable bit (REN) to enable the UART for data reception
– Enable parity, if appropriate and if Multiprocessor Mode is not enabled, and select
either even or odd parity
5. Check the RDA bit in the UART Status 0 Register to determine if the Receive Data
Register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indicate
available data, continue to Step 6. If the Receive Data Register is empty (indicated by
a 0), continue to monitor the RDA bit awaiting reception of the valid data.
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6. Read data from the UART Receive Data Register. If operating in Multiprocessor (9Bit) Mode, further actions may be required depending on the Multiprocessor Mode
bits MPMD[1:0].
7. Return to Step 5 to receive additional data.
Receiving Data using the Interrupt-Driven Method
The UART Receiver interrupt indicates the availability of new data (as well as error conditions). Observe the following procedure to configure the UART receiver for interruptdriven operation:
1. Write to the UART Baud Rate High and Low Byte registers to set the appropriate baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set
the appropriate priority.
5. Clear the UART Receiver interrupt in the applicable Interrupt Request Register.
6. Write to the UART Control 1 Register to enable Multiprocessor (9-Bit) Mode functions, if appropriate.
– Set the Multiprocessor Mode Select (MPEN) to enable Multiprocessor Mode.
– Set the Multiprocessor Mode bits, MPMD[1:0], to select the appropriate address
matching scheme.
– Configure the UART to interrupt on received data and errors or errors only (interrupt on errors only is unlikely to be useful for Z8 Encore! XP devices without a
DMA block).
7. Write the device address to the Address Compare Register (automatic multiprocessor
modes only).
8. Write to the UART Control 0 Register to:
– Set the receive enable bit (REN) to enable the UART for data reception
– Enable parity, if appropriate and if Multiprocessor Mode is not enabled, and select
either even or odd parity
9. Execute an EI instruction to enable interrupts.
The UART is now configured for interrupt-driven data reception. When the UART
Receiver interrupt is detected, the associated interrupt service routine performs the following functions:
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1. Check the UART Status 0 Register to determine the source of the interrupt: error,
break, or received data.
2. If the interrupt was caused by data available, read the data from the UART Receive
Data Register. If operating in Multiprocessor (9-Bit) Mode, further actions may be
required depending on the Multiprocessor Mode bits MPMD[1:0].
3. Clear the UART Receiver interrupt in the applicable Interrupt Request Register.
4. Execute the IRET instruction to return from the interrupt service routine and await
more data.
Clear To Send (CTS) Operation
The CTS pin, if enabled by the CTSE bit of the UART Control 0 Register, performs flow
control on the outgoing transmit datastream. The Clear To Send (CTS) input pin is sampled one system clock before beginning any new character transmission. To delay transmission of the next data character, an external receiver must deassert CTS at least one
system clock cycle before a new data transmission begins. For multiple character transmissions, this would typically be done during stop bit transmission. If CTS deasserts in the
middle of a character transmission, the current character is sent completely.
Multiprocessor (9-Bit) Mode
The UART has a Multiprocessor (9-Bit) Mode that uses an extra (9th) bit for selective
communication when a number of processors share a common UART bus. In Multiprocessor Mode (also referred to as 9-bit mode), the multiprocessor bit (MP) is transmitted
immediately following the 8 bits of data and immediately preceding the stop bit(s); the
character format is displayed in Figure 16.
Data Field
Idle State
of Line
Stop Bit(s)
lsb
msb
1
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
MP
0
1
2
Figure 16. UART Asynchronous Multiprocessor Mode Data Format
In Multiprocessor (9-Bit) Mode, the parity bit location (9th bit) becomes the Multiprocessor control bit. The UART Control 1 and Status 1 registers provide Multiprocessor (9-Bit)
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Mode control and status information. If an automatic address matching scheme is enabled,
the UART Address Compare Register holds the network address of the device.
Multiprocessor (9-Bit) Mode Receive Interrupts
When Multiprocessor Mode is enabled, the UART only processes frames addressed to it.
The determination of whether a frame of data is addressed to the UART can be made in
hardware, software or some combination of the two, depending on the multiprocessor configuration bits. In general, the address compare feature reduces the load on the CPU, since
it does not need to access the UART when it receives data directed to other devices on the
multinode network. The following three Multiprocessor modes are available in hardware:
•
•
•
Interrupt on all address bytes
Interrupt on matched address bytes and correctly framed data bytes
Interrupt only on correctly framed data bytes
These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all Multiprocessor modes, bit MPEN of the UART Control 1 Register must be set to 1.
The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming
address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt
service routine must manually check the address byte that caused triggered the interrupt. If
it matches the UART address, the software clears MPMD[0]. At this point, each new
incoming byte interrupts the CPU. The software is then responsible for determining the
end of the frame. It checks for end-of-frame by reading the MPRX bit of the UART Status
1 Register for each incoming byte. If MPRX=1, a new frame has begun. If the address of
this new frame is different from the UART’s address, then set MPMD[0] to 1 causing the
UART interrupts to go inactive until the next address byte. If the new frame’s address
matches the UART’s, the data in the new frame is processed as well.
The second scheme is enabled by setting MPMD[1:0] to 10b and writing the UART’s
address into the UART Address Compare Register. This mode introduces more hardware
control, interrupting only on frames that match the UART’s address. When an incoming
address byte does not match the UART’s address, it is ignored. All successive data bytes in
this frame are also ignored. When a matching address byte occurs, an interrupt is issued
and further interrupts now occur on each successive data byte. The first data byte in the
frame contains the NEWFRM = 1 in the UART Status 1 Register. When the next address
byte occurs, the hardware compares it to the UART’s address. If there is a match, the interrupts continue sand the NEWFRM bit is set for the first byte of the new frame. If there is
no match, then the UART ignores all incoming bytes until the next address match.
The third scheme is enabled by setting MPMD[1:0] to 11b and by writing the UART’s
address into the UART Address Compare Register. This mode is identical to the second
scheme, except that there are no interrupts on address bytes. The first data byte of each
frame is still accompanied by a NEWFRM assertion.
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External Driver Enable
The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This feature reduces the software overhead associated with using a GPIO pin to control the transceiver when communicating on a multitransceiver bus, such as RS-485.
Driver Enable is an active High signal that envelopes the entire transmitted data frame
including parity and stop bits as displayed in Figure 17. The Driver Enable signal asserts
when a byte is written to the UART Transmit Data Register. The Driver Enable signal
asserts at least one UART bit period and no greater than two UART bit periods before the
start bit is transmitted. This timing allows a setup time to enable the transceiver. The
Driver Enable signal deasserts one system clock period after the last stop bit is transmitted. This one system clock delay allows both time for data to clear the transceiver before
disabling it, as well as the ability to determine if another character follows the current
character. In the event of back to back characters (new data must be written to the Transmit Data Register before the previous character is completely transmitted) the DE signal is
not deasserted between characters. The DEPOL bit in the UART Control Register 1 sets
the polarity of the Driver Enable signal.
1
DE
0
Data Field
Idle State
of Line
Stop Bit
lsb
msb
1
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Parity
0
1
Figure 17. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
The Driver Enable-to-start-bit set-up time is calculated as:
1
2
------------------------------------ DE to Start Bit Setup Time (s) -------------------------------------
Baud Rate (Hz)
Baud Rate (Hz)
UART Interrupts
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the Baud Rate Generator can also function as a basic timer with interrupt capability.
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Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for transmission. The TDRE interrupt occurs after the Transmit Shift Register has shifted the first
bit of data out. At this point, the Transmit Data Register can be written with the next character to send. This provides 7 bit-periods of latency to load the Transmit Data Register
before the Transmit Shift Register completes shifting the current character. Writing to the
UART Transmit Data Register clears the TDRE bit to 0.
Receiver Interrupts
The receiver generates an interrupt when any of the following events occurs:
•
A data byte has been received and is available in the UART Receive Data Register. This
interrupt can be disabled independent of the other receiver interrupt sources. The received data interrupt occurs once the receive character has been received and placed in
the Receive Data Register. Software must respond to this received data available condition before the next character is completely received to avoid an overrun error.
Note: In Multiprocessor Mode (MPEN = 1), the receive data interrupts are dependent on the multiprocessor configuration and the most recent address byte.
•
•
•
A break is received
An overrun is detected
A data framing error is detected
UART Overrun Errors
When an overrun error condition occurs the UART prevents overwriting of the valid data
currently in the Receive Data Register. The Break Detect and Overrun status bits are not
displayed until after the valid data has been read.
After the valid data has been read, the UART Status 0 Register is updated to indicate the
overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that
the Receive Data Register contains a data byte. However, because the overrun error
occurred, this byte may not contain valid data and should be ignored. The BRKD bit indicates if the overrun was caused by a break condition on the line. After reading the status
byte indicating an overrun error, the Receive Data Register must be read again to clear the
error bits is the UART Status 0 Register. Updates to the Receive Data Register occur only
when the next data word is received.
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UART Data and Error Handling Procedure
Figure 18 displays the recommended procedure for use in UART receiver interrupt service
routines.
Receiver
Ready
Receiver
Interrupt
Read Status
No
Errors?
Yes
Read Data which
clears RDA bit and
resets error bits
Read Data
Discard Data
Figure 18. UART Receiver Interrupt Service Routine Flow
Baud Rate Generator Interrupts
If the Baud Rate Generator interrupt enable is set, the UART Receiver interrupt asserts
when the UART Baud Rate Generator reloads. This action allows the Baud Rate Generator to function as an additional counter if the UART functionality is not employed.
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UART Baud Rate Generator
The UART Baud Rate Generator creates a lower frequency baud rate clock for data transmission. The input to the Baud Rate Generator is the system clock. The UART Baud Rate
High and Low Byte registers combine to create a 16-bit baud rate divisor value
(BRG[15:0]) that sets the data transmission rate (baud rate) of the UART. The UART data
rate is calculated using the following equation:
System Clock Frequency (Hz)
UART Data Rate (bits/s) = -----------------------------------------------------------------------------------------16 UART Baud Rate Divisor Value
When the UART is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 Register
to 0.
2. Load the appropriate 16-bit count value into the UART Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BRGCTL bit in the UART Control 1 Register to 1.
When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval s = System Clock Period (s) BRG 15:0
UART Control Register Definitions
The UART control registers support the UART and the associated Infrared Encoder/
Decoders. For more information about the infrared operation, see the Infrared Encoder/
Decoder chapter on page 109.
UART Transmit Data Register
Data bytes written to the UART Transmit Data Register, shown in Table 53, are shifted out
on the TXDx pin. The write-only UART Transmit Data Register shares a register file
address with the read-only UART Receive Data Register.
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Table 53. UART Transmit Data Register (UxTXD)
Bit
7
6
5
4
Field
3
2
1
0
TXD
RESET
X
R/W
W
Address
F40h and F48h
Bit
Description
[7:0]
TXD
Transmit Data
UART transmitter data byte to be shifted out through the TXDx pin.
UART Receive Data Register
Data bytes received through the RXDx pin are stored in the UART Receive Data Register,
shown in Table 54. The read-only UART Receive Data Register shares a register file
address with the write-only UART Transmit Data Register.
Table 54. UART Receive Data Register (UxRXD)
Bit
7
6
5
4
Field
3
2
1
0
RXD
RESET
X
R/W
R
Address
F40h and F48h
Bit
Description
[7:0]
RXD
Receive Data
UART receiver data byte from the RXDx pin.
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UART Status 0 Register
The UART Status 0 Register, shown in Table 55, identifies the current UART operating
configuration and status.
Table 55. UART Status 0 Register (UxSTAT0)
Bit
Field
7
6
5
4
3
2
1
0
RDA
PE
OE
FE
BRKD
TDRE
TXE
CTS
1
X
RESET
0
R/W
R
Address
F41h and F49h
Bit
Description
[7]
RDA
Receive Data Available
This bit indicates that the UART Receive Data Register has received data. Reading the UART
Receive Data Register clears this bit.
0 = The UART Receive Data Register is empty.
1 = There is a byte in the UART Receive Data Register.
[6]
PE
Parity Error
This bit indicates that a parity error has occurred. Reading the UART Receive Data Register
clears this bit.
0 = No parity error occurred.
1 = A parity error occurred.
[5]
OE
Overrun Error
This bit indicates that an overrun error has occurred. An overrun occurs when new data is
received and the UART Receive Data Register has not been read. If the RDA bit is reset to 0,
then reading the UART Receive Data Register clears this bit.
0 = No overrun error occurred.
1 = An overrun error occurred.
[4]
FE
Framing Error
This bit indicates that a framing error (no stop bit following data reception) was detected. Reading the UART Receive Data Register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
[3]
BRKD
Break Detect
This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and stop bit(s)
are all zeros then this bit is set to 1. Reading the UART Receive Data Register clears this bit.
0 = No break occurred.
1 = A break occurred.
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Bit
Description (Continued)
[2]
TDRE
Transmitter Data Register Empty
This bit indicates that the UART Transmit Data Register is empty and ready for additional data.
Writing to the UART Transmit Data Register resets this bit.
0 = Do not write to the UART Transmit Data Register.
1 = The UART Transmit Data Register is ready to receive an additional byte to be transmitted.
[1]
TXE
Transmitter Empty
This bit indicates that the Transmit Shift Register is empty and character transmission is finished.
0 = Data is currently transmitting.
1 = Transmission is complete.
[0]
CTS
CTS Signal
When this bit is read, it returns the level of the CTS signal.
UART Status 1 Register
The UART Status 1 Register, shown in Table 56, contains multiprocessor control and
UART status bits.
Table 56. UART Status 1 Register (UxSTAT1)
Bit
7
6
5
Field
4
3
2
Reserved
RESET
1
0
NEWFRM
MPRX
0
R/W
R
Address
R/W
R
F44h and F4Ch
Bit
Description
[7:2]
Reserved
These bits are reserved and must be programmed to 000000.
[1]
NEWFRM
New Frame
Status bit denoting the start of a new frame. Reading the UART Receive Data Register
resets this bit to 0.
0 = The current byte is not the first data byte of a new frame.
1 = The current byte is the first data byte of a new frame.
[0]
MPRX
Multiprocessor Receive
Returns the value of the last multiprocessor bit received. Reading from the UART Receive
Data Register resets this bit to 0.
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UART Control 0 and Control 1 Registers
The UART Control 0 and Control 1 Registers, shown in Tables 57 and 58, configure the
properties of the UART’s transmit and receive operations. The UART Control registers
must not been written while the UART is enabled.
Table 57. UART Control 0 Register (UxCTL0)
Bit
Field
7
6
5
4
3
2
1
0
TEN
REN
CTSE
PEN
PSEL
SBRK
STOP
LBEN
RESET
0
R/W
R/W
Address
F42h and F4Ah
Bit
Description
[7]
TEN
Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
[6]
REN
Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
[5]
CTSE
CTS Enable
0 = The CTS signal has no effect on the transmitter.
1 = The UART recognizes the CTS signal as an enable control from the transmitter.
[4]
PEN
Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit. It is overridden
by the MPEN bit.
0 = Parity is disabled.
1 = The transmitter sends data with an additional parity bit and the receiver receives an additional parity bit.
[3]
PSEL
Parity Select
0 = Even parity is transmitted and expected on all received data.
1 = Odd parity is transmitted and expected on all received data.
[2]
SBRK
Send Break
This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so ensure that the transmitter has finished sending data before setting this bit.
0 = No break is sent.
1 = The output of the transmitter is zero.
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Bit
Description (Continued)
[1]
STOP
Stop Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
[0]
LBEN
Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver.
Table 58. UART Control 1 Register (UxCTL1)
Bit
Field
7
6
5
4
3
2
1
0
MPMD[1]
MPEN
MPMD[0]
MPBT
DEPOL
BRGCTL
RDAIRQ
IREN
RESET
0
R/W
R/W
Address
F43h and F4Bh
Bit
Description
[7,5]
MPMD[1,0]
Multiprocessor Mode
If Multiprocessor (9-Bit) Mode is enabled,
00 = The UART generates an interrupt request on all received bytes (data and address).
01 = The UART generates an interrupt request only on received address bytes.
10 = The UART generates an interrupt request when a received address byte matches the
value stored in the Address Compare Register and on all successive data bytes until
an address mismatch occurs.
11 = The UART generates an interrupt request on all received data bytes for which the most
recent address byte matched the value in the Address Compare Register.
[6]
MPEN
Multiprocessor (9-Bit) Enable
This bit is used to enable Multiprocessor (9-Bit) Mode.
0 = Disable Multiprocessor (9-Bit) Mode.
1 = Enable Multiprocessor (9-Bit) Mode.
[4]
MPBT
Multiprocessor Bit Transmit
This bit is applicable only when Multiprocessor (9-Bit) Mode is enabled.
0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit).
1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit).
[3]
DEPOL
Driver Enable Polarity
0 = DE signal is Active High.
1 = DE signal is Active Low.
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Bit
Description (Continued)
[2]
BRGCTL
Baud Rate Control
This bit causes different UART behavior depending on whether the UART receiver is
enabled (REN = 1 in the UART Control 0 Register). When the UART receiver is not enabled,
this bit determines whether the Baud Rate Generator issues interrupts.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG reload value
1 = The Baud Rate Generator generates a receive interrupt when it counts down to 0.
Reads from the Baud Rate High and Low Byte registers return the current BRG count
value.
When the UART receiver is enabled, this bit allows reads from the Baud Rate Registers to
return the BRG count value instead of the reload value.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG reload value.
1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count
value. Unlike the timers, there is no mechanism to latch the High Byte when the Low
Byte is read.
[1]
RDAIRQ
Receive Data Interrupt Enable
0 = Received data and receiver errors generates an interrupt request to the Interrupt Controller.
1 = Received data does not generate an interrupt request to the Interrupt Controller. Only
receiver errors generate an interrupt request.
[0]
IREN
Infrared Encoder/Decoder Enable
0 = Infrared Encoder/Decoder is disabled. UART operates normally operation.
1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data through
the Infrared Encoder/Decoder.
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UART Address Compare Register
The UART Address Compare Register, shown in Table 59, stores the multinode network
address of the UART. When the MPMD[1] bit of UART Control Register 0 is set, all
incoming address bytes are compared to the value stored in the Address Compare Register. Receive interrupts and RDA assertions only occur in the event of a match.
Table 59. UART Address Compare Register (UxADDR)
Bit
7
6
Field
5
4
3
2
1
0
COMP_ADDR
RESET
0
R/W
R/W
Address
F45h and F4Dh
Bit
Description
[7:0]
Compare Address
COMP_ADDR This 8-bit value is compared to the incoming address bytes.
UART Baud Rate High and Low Byte Registers
The UART Baud Rate High and Low Byte registers, shown in Tables 60 and 61, combine
to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate
(baud rate) of the UART. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 Register
to 0.
2. Load the appropriate 16-bit count value into the UART Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BRGCTL bit in the UART Control 1 Register to 1.
When configured as a general-purpose timer, the UART BRG interrupt interval is calculated using the following equation:
UART BRG Interrupt Interval s = System Clock Period (s) BRG 15:0
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Table 60. UART Baud Rate High Byte Register (UxBRH)
Bit
7
6
5
4
Field
3
2
1
0
1
0
BRH
RESET
1
R/W
R/W
Address
F46h and F4Eh
Table 61. UART Baud Rate Low Byte Register (UxBRL)
Bit7
7
Field
6
5
4
3
2
BRL
RESET
1
R/W
R/W
Address
F47h and F4Fh
For a given UART data rate, the integer baud rate divisor value is calculated using the following equation:
System Clock Frequency (Hz)
UART Baud Rate Divisor Value (BRG) = Round ------------------------------------------------------------------------
16 UART Data Rate (bits/s)
The baud rate error relative to the appropriate baud rate is calculated using the following
equation:
Actual Data Rate – Desired Data Rate
UART Baud Rate Error (%) = 100 -------------------------------------------------------------------------------------------
Desired Data Rate
For reliable communication, the UART baud rate error must never exceed 5 percent.
Table 62 lists data rate errors for popular baud rates and commonly used crystal oscillator
frequencies.
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Table 62. UART Baud Rates
20.0 MHz System Clock
18.432 MHz System Clock
Desired
Rate
(kHz)
BRG
Divisor
(Decimal)
Actual Rate
(kHz)
Error
(%)
Desired
Rate
(kHz)
BRG
Divisor
(Decimal)
Actual Rate
(kHz)
Error
(%)
1250.0
1
1250.0
0.00
1250.0
1
1152.0
–7.84%
625.0
2
625.0
0.00
625.0
2
576.0
–7.84%
250.0
5
250.0
0.00
250.0
5
230.4
–7.84%
115.2
11
113.6
–1.36
115.2
10
115.2
0.00
57.6
22
56.8
–1.36
57.6
20
57.6
0.00
38.4
33
37.9
–1.36
38.4
30
38.4
0.00
19.2
65
19.2
0.16
19.2
60
19.2
0.00
9.60
130
9.62
0.16
9.60
120
9.60
0.00
4.80
260
4.81
0.16
4.80
240
4.80
0.00
2.40
521
2.40
–0.03
2.40
480
2.40
0.00
1.20
1042
1.20
–0.03
1.20
960
1.20
0.00
0.60
2083
0.60
0.02
0.60
1920
0.60
0.00
0.30
4167
0.30
–0.01
0.30
3840
0.30
0.00
16.667 MHz System Clock
11.0592 MHz System Clock
Desired
Rate
(kHz)
BRG
Divisor
(Decimal)
Actual Rate
(kHz)
Error
(%)
Desired
Rate
(kHz)
BRG
Divisor
(Decimal)
Actual Rate
(kHz)
Error
(%)
1250.0
1
1041.69
–16.67
1250.0
N/A
N/A
N/A
625.0
2
520.8
–16.67
625.0
1
691.2
10.59
250.0
4
260.4
4.17
250.0
3
230.4
–7.84
115.2
9
115.7
0.47
115.2
6
115.2
0.00
57.6
18
57.87
0.47
57.6
12
57.6
0.00
38.4
27
38.6
0.47
38.4
18
38.4
0.00
19.2
54
19.3
0.47
19.2
36
19.2
0.00
9.60
109
9.56
–0.45
9.60
72
9.60
0.00
4.80
217
4.80
–0.83
4.80
144
4.80
0.00
2.40
434
2.40
0.01
2.40
288
2.40
0.00
1.20
868
1.20
0.01
1.20
576
1.20
0.00
0.60
1736
0.60
0.01
0.60
1152
0.60
0.00
0.30
3472
0.30
0.01
0.30
2304
0.30
0.00
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Table 62. UART Baud Rates (Continued)
10.0 MHz System Clock
5.5296 MHz System Clock
Desired
Rate
(kHz)
BRG
Divisor
(Decimal)
Actual Rate
(kHz)
Error
(%)
Desired
Rate
(kHz)
BRG
Divisor
(Decimal)
Actual Rate
(kHz)
Error
(%)
1250.0
N/A
N/A
N/A
1250.0
N/A
N/A
N/A
625.0
1
625.0
0.00
625.0
N/A
N/A
N/A
250.0
3
208.33
–16.67
250.0
1
345.6
38.24
115.2
5
125.0
8.51
115.2
3
115.2
0.00
57.6
11
56.8
–1.36
57.6
6
57.6
0.00
38.4
16
39.1
1.73
38.4
9
38.4
0.00
19.2
33
18.9
0.16
19.2
18
19.2
0.00
9.60
65
9.62
0.16
9.60
36
9.60
0.00
4.80
130
4.81
0.16
4.80
72
4.80
0.00
2.40
260
2.40
–0.03
2.40
144
2.40
0.00
1.20
521
1.20
–0.03
1.20
288
1.20
0.00
0.60
1042
0.60
–0.03
0.60
576
0.60
0.00
0.30
2083
0.30
0.2
0.30
1152
0.30
0.00
3.579545 MHz System Clock
1.8432 MHz System Clock
Desired
Rate
(kHz)
BRG
Divisor
(Decimal)
Actual Rate
(kHz)
Error
(%)
Desired
Rate
(kHz)
BRG
Divisor
(Decimal)
Actual Rate
(kHz)
Error
(%)
1250.0
N/A
N/A
N/A
1250.0
N/A
N/A
N/A
625.0
N/A
N/A
N/A
625.0
N/A
N/A
N/A
250.0
1
223.72
–10.51
250.0
N/A
N/A
N/A
115.2
2
111.9
–2.90
115.2
1
115.2
0.00
57.6
4
55.9
–2.90
57.6
2
57.6
0.00
38.4
6
37.3
–2.90
38.4
3
38.4
0.00
19.2
12
18.6
–2.90
19.2
6
19.2
0.00
9.60
23
9.73
1.32
9.60
12
9.60
0.00
4.80
47
4.76
–0.83
4.80
24
4.80
0.00
2.40
93
2.41
0.23
2.40
48
2.40
0.00
1.20
186
1.20
0.23
1.20
96
1.20
0.00
0.60
373
0.60
–0.04
0.60
192
0.60
0.00
0.30
746
0.30
–0.04
0.30
384
0.30
0.00
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Infrared Encoder/Decoder
The Z8 Encore! XP F64xx Series products contain two fully-functional, high-performance
UART-to-infrared encoders/decoders (endecs). Each infrared endec is integrated with an
on-chip UART to allow easy communication between the Z8 Encore! XP F64xx Series
and IrDA Physical Layer Specification Version 1.3-compliant infrared transceivers. Infrared communication provides secure, reliable, low-cost, point-to-point communication
between PCs, PDAs, cell phones, printers, and other infrared enabled devices.
Architecture
Figure 19 displays the architecture of the infrared endec.
System
Clock
Zilog
ZHX1810
RxD
RxD
RxD
TxD
UART
Baud Rate
Clock
Interrupt
I/O
Signal Address
Infrared
Encoder/Decoder
(Endec)
TxD
TxD
Infrared
Transceiver
Data
Figure 19. Infrared Data Communication System Block Diagram
Operation
When the infrared endec is enabled, the transmit data from the associated on-chip UART
is encoded as digital signals in accordance with the IrDA standard and output to the infrared transceiver via the TxD pin. Likewise, data received from the infrared transceiver is
passed to the infrared endec via the RxD pin, decoded by the infrared endec, and then
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passed to the UART. Communication is half-duplex, which means simultaneous data
transmission and reception is not allowed.
The baud rate is set by the UART’s Baud Rate Generator and supports IrDA standard baud
rates from 9600 baud to 115.2 KBaud. Higher baud rates are possible, but do not meet
IrDA specifications. The UART must be enabled to use the infrared endec. The infrared
endec data rate is calculated using the following equation:
System Clock Frequency (Hz)
Infrared Data Rate (bits/s) = -----------------------------------------------------------------------------------------16 UART Baud Rate Divisor Value
Transmitting IrDA Data
The data to be transmitted using the infrared transceiver is first sent to the UART. The
UART’s transmit signal (TxD) and baud rate clock are used by the IrDA to generate the
modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared
data bit is 16-clock wide. If the data to be transmitted is 1, the IR_TXD signal remains low
for the full 16-clock period. If the data to be transmitted is 0, a 3-clock high pulse is output
following a 7-clock low period. After the 3-clock high pulse, a 6-clock low pulse is output
to complete the full 16-clock data period. Figure 20 displays IrDA data transmission.
When the infrared endec is enabled, the UART’s TxD signal is internal to the Z8 Encore!
XP F64xx Series products while the IR_TXD signal is output through the TxD pin.
16-clock
period
Baud Rate
Clock
UART’s
TxD
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
3-clock
pulse
IR_TXD
7-clock
delay
Figure 20. Infrared Data Transmission
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Receiving IrDA Data
Data received from the infrared transceiver via the IR_RXD signal through the RxD pin is
decoded by the infrared endec and passed to the UART. The UART’s baud rate clock is
used by the infrared endec to generate the demodulated signal (RxD) that drives the
UART. Each UART/Infrared data bit is 16-clocks wide. Figure 21 displays data reception.
When the infrared endec is enabled, the UART’s RxD signal is internal to the Z8 Encore!
XP F64xx Series products while the IR_RXD signal is received through the RxD pin.
16-clock
period
Baud Rate
Clock
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_RXD
min. 1.6µs
pulse
UART’s
RxD
Start Bit = 0
8-clock
delay
16-clock
period
Data Bit 0 = 1
Data Bit 1 = 0
16-clock
period
16-clock
period
Data Bit 2 = 1
Data Bit 3 = 1
16-clock
period
Figure 21. Infrared Data Reception
Caution: The system clock frequency must be at least 1.0 MHz to ensure proper reception of the
1.6 µs minimum width pulses allowed by the IrDA standard.
Endec Receiver Synchronization
The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate
an input stream for the UART and to create a sampling window for detection of incoming
pulses. The generated UART input (UART RxD) is delayed by 8 baud rate clock periods
with respect to the incoming IrDA data stream. When a falling edge in the input data
stream is detected, the endec counter is reset. When the count reaches a value of 8, the
UART RxD value is updated to reflect the value of the decoded data. When the count
reaches 12 baud clock periods, the sampling window for the next incoming pulse opens.
The window remains open until the count again reaches 8 (i.e., 24 baud clock periods
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since the previous pulse was detected). This gives the endec a sampling window of minus
four baud rate clocks to plus eight baud rate clocks around the expected time of an incoming pulse. If an incoming pulse is detected inside this window this process is repeated. If
the incoming data is a logical 1 (no pulse), the endec returns to the initial state and waits
for the next falling edge. As each falling edge is detected, the endec clock counter is reset,
resynchronizing the endec to the incoming signal. This action allows the endec to tolerate
jitter and baud rate errors in the incoming data stream. Resynchronizing the endec does
not alter the operation of the UART, which ultimately receives the data. The UART is only
synchronized to the incoming data stream when a start bit is received.
Infrared Encoder/Decoder Control Register Definitions
All infrared endec configuration and status information is set by the UART control registers as defined in the UART Control Register Definitions section on page 98.
Caution: To prevent spurious signals during IrDA data transmission, set the IREN bit in the
UARTx Control 1 Register to 1 to enable the Infrared Encoder/Decoder before enabling
the GPIO Port alternate function for the corresponding pin.
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Serial Peripheral Interface
The Serial Peripheral Interface is a synchronous interface allowing several SPI-type
devices to be interconnected. SPI-compatible devices include EEPROMs, Analog-to-Digital Converters, and ISDN devices. Features of the SPI include:
•
•
•
•
•
Full-duplex, synchronous, character-oriented communication
Four-wire interface
Data transfers rates up to a maximum of one-half the system clock frequency
Error detection
Dedicated Baud Rate Generator
Architecture
The SPI may be configured as either a Master (in single or multimaster systems) or a Slave
as displayed in Figures 22 through 24.
SPI Master
To Slave’s SS Pin
From Slave
To Slave
To Slave
SS
MISO
8-bit Shift Register
Bit 0
Bit 7
MOSI
SCK
Baud Rate
Generator
Figure 22. SPI Configured as a Master in a Single-Master, Single-Slave System
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VCC
SPI Master
SS
To Slave #2’s SS Pin
GPIO
To Slave #1’s SS Pin
GPIO
8-bit Shift Register
From Slave
MISO
Bit 0
Bit 7
MOSI
To Slave
SCK
To Slave
Baud Rate
Generator
Figure 23. SPI Configured as a Master in a Single-Master, Multiple-Slave System
SPI Slave
From Master
To Master
From Master
From Master
SS
MISO
8-bit Shift Register
Bit 7
Bit 0
MOSI
SCK
Figure 24. SPI Configured as a Slave
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Operation
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire
interface (serial clock, transmit, receive and Slave select). The SPI block consists of a
transmit/receive shift register, a baud rate (clock) generator and a control unit.
During an SPI transfer, data is sent and received simultaneously by both the Master and
the Slave SPI devices. Separate signals are required for data and the serial clock. When an
SPI transfer occurs, a multibit (typically 8-bit) character is shifted out one data pin and an
multibit character is simultaneously shifted in on a second data pin. An 8-bit shift register
in the Master and another 8-bit shift register in the Slave are connected as a circular buffer.
The SPI Shift Register is single-buffered in the transmit and receive directions. New data
to be transmitted cannot be written into the shift register until the previous transmission is
complete and receive data (if valid) has been read.
SPI Signals
The four basic SPI signals are:
•
•
•
•
Master-In/Slave-Out
Master-Out/Slave-In
Serial Clock
Slave Select
Each signal is described in both Master and Slave modes.
Master-In/Slave-Out
The Master-In/Slave-Out (MISO) pin is configured as an input in a Master device and as
an output in a Slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. The MISO pin of a Slave device is placed in a high-impedance
state if the Slave is not selected. When the SPI is not enabled, this signal is in a highimpedance state.
Master-Out/Slave-In
The Master-Out/Slave-In (MOSI) pin is configured as an output in a Master device and as
an input in a Slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance
state.
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Serial Clock
The Serial Clock (SCK) synchronizes data movement both in and out of the device
through its MOSI and MISO pins. In MASTER Mode, the SPI’s Baud Rate Generator creates the serial clock. The Master drives the serial clock out its own SCK pin to the Slave’s
SCK pin. When the SPI is configured as a Slave, the SCK pin is an input and the clock signal from the Master synchronizes the data transfer between the Master and Slave devices.
Slave devices ignore the SCK signal, unless the SS pin is asserted. When configured as a
slave, the SPI block requires a minimum SCK period of greater than or equal to 8 times
the system (XIN) clock period.
The Master and Slave are each capable of exchanging a character of data during a
sequence of NUMBITS clock cycles (see the NUMBITS field in the SPI Mode Register
section on page 125). In both Master and Slave SPI devices, data is shifted on one edge of
the SCK and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI phase and polarity control.
Slave Select
The active Low Slave Select (SS) input signal selects a Slave SPI device. SS must be Low
prior to all data communication to and from the Slave device. SS must stay Low for the
full duration of each character transferred. The SS signal may stay Low during the transfer
of multiple characters or may deassert between each character.
When the SPI is configured as the only Master in an SPI system, the SS pin can be set as
either an input or an output. Other GPIO output pins can also be employed to select external SPI Slave devices.
When the SPI is configured as one Master in a multimaster SPI system, the SS pin must be
set as an input. The SS input signal on the Master must be High. If the SS signal goes Low
(indicating another Master is driving the SPI bus), a collision error flag is set in the SPI
Status Register.
SPI Clock Phase and Polarity Control
The SPI supports four combinations of serial clock phase and polarity using two bits in the
SPI Control Register. The clock polarity bit, CLKPOL, selects an active high or active
Low clock and has no effect on the transfer format. Table 63 lists the SPI Clock Phase and
Polarity Operation parameters. The clock phase bit, PHASE, selects one of two fundamentally different transfer formats. For proper data transmission, the clock phase and polarity
must be identical for the SPI Master and the SPI Slave. The Master always places data on
the MOSI line a half-cycle before the receive clock edge (SCK signal), in order for the
Slave to latch the data.
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Table 63. SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation
PHASE
CLKPOL
SCK Transmit
Edge
SCK Receive
Edge
SCK Idle
State
0
0
Falling
Rising
Low
0
1
Rising
Falling
High
1
0
Rising
Falling
Low
1
1
Falling
Rising
High
Transfer Format PHASE Equals Zero
Figure 25 displays the timing diagram for an SPI transfer in which PHASE is cleared to 0.
The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set to
one. The diagram may be interpreted as either a Master or Slave timing diagram because
the SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly
connected between the Master and the Slave.
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MISO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Input Sample Time
SS
Figure 25. SPI Timing When PHASE is 0
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Transfer Format PHASE Equals One
Figure 26 displays the timing diagram for an SPI transfer in which PHASE is 1. Two
waveforms are depicted for SCK, one for CLKPOL reset to 0 and another for CLKPOL
set to 1.
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MISO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Input Sample Time
SS
Figure 26. SPI Timing When PHASE is 1
Multimaster Operation
In a multimaster SPI system, all SCK pins are tied together, all MOSI pins are tied
together and all MISO pins are tied together. All SPI pins must then be configured in
Open-Drain Mode to prevent bus contention. At any one time, only one SPI device is configured as the Master and all other SPI devices on the bus are configured as Slaves. The
Master enables a single Slave by asserting the SS pin on that Slave only. Then, the single
Master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the Slaves
(including those which are not enabled). The enabled Slave drives data out its MISO pin to
the MISO Master pin.
For a Master device operating in a multimaster system, if the SS pin is configured as an
input and is driven Low by another Master, the COL bit is set to 1 in the SPI Status Register. The COL bit indicates the occurrence of a multimaster collision (mode fault error condition).
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Slave Operation
The SPI block is configured for SLAVE Mode operation by setting the SPIEN bit to 1 and
the MMEN bit to 0 in the SPICTL Register and setting the SSIO bit to 0 in the SPIMODE
Register. The IRQE, PHASE, CLKPOL, WOR bits in the SPICTL Register and the
NUMBITS field in the SPIMODE Register must be set to be consistent with the other SPI
devices. The STR bit in the SPICTL Register may be used if appropriate to force a startup interrupt. The BIRQ bit in the SPICTL Register and the SSV bit in the SPIMODE Register are not used in SLAVE Mode. The SPI baud rate generator is not used in SLAVE
Mode so the SPIBRH and SPIBRL registers need not be initialized.
If the slave has data to send to the master, the data must be written to the SPIDAT Register
before the transaction starts (first edge of SCK when SS is asserted). If the SPIDAT Register is not written prior to the slave transaction, the MISO pin outputs whatever value is
currently in the SPIDAT Register.
Due to the delay resulting from synchronization of the SPI input signals to the internal system clock, the maximum SPICLK baud rate that can be supported in SLAVE Mode is the
system clock frequency (XIN) divided by 8. This rate is controlled by the SPI master.
Error Detection
The SPI contains error detection logic to support SPI communication protocols and recognize when communication errors have occurred. The SPI Status Register indicates when a
data transmission error has been detected.
Overrun (Write Collision)
An overrun error (write collision) indicates that a write to the SPI Data Register was
attempted while a data transfer was in progress (in either MASTER or SLAVE modes). An
overrun sets the OVR bit in the SPI Status Register to 1. Writing a 1 to OVR clears this
error flag. The data register is not altered when a write occurs while data transfer is in
progress.
Mode Fault (Multimaster Collision)
A mode fault indicates when more than one Master is trying to communicate at the same
time (a multimaster collision). The mode fault is detected when the enabled Master’s SS
pin is asserted. A mode fault sets the COL bit in the SPI Status Register to 1. Writing a 1 to
COL clears this error flag.
Slave Mode Abort
In the SLAVE Mode of operation, if the SS pin deasserts before all bits in a character have
been transferred, the transaction is aborted. When this condition occurs, the ABT bit is set
in the SPISTAT Register as well as the IRQ bit (indicating the transaction is complete).
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The next time SS asserts, the MISO pin outputs SPIDAT[7], regardless of where the previous transaction left off. Writing a 1 to ABT clears this error flag.
SPI Interrupts
When SPI interrupts are enabled, the SPI generates an interrupt after character transmission/reception completes in both MASTER and SLAVE modes. A character can be
defined to be 1 through 8 bits by the NUMBITS field in the SPI Mode Register. In Slave
Mode, it is not necessary for SS to deassert between characters to generate the interrupt.
The SPI in Slave mode can also generate an interrupt if the SS signal deasserts prior to
transfer of all the bits in a character (see description of slave abort error above). Writing a
1 to the IRQ bit in the SPI Status Register clears the pending SPI interrupt request. The
IRQ bit must be cleared to 0 by the Interrupt Service Routine to generate future interrupts.
To start the transfer process, an SPI interrupt may be forced by software writing a 1 to the
STR bit in the SPICTL Register.
If the SPI is disabled, an SPI interrupt can be generated by a Baud Rate Generator timeout. This timer function must be enabled by setting the BIRQ bit in the SPICTL Register.
This Baud Rate Generator time-out does not set the IRQ bit in the SPISTAT Register, just
the SPI interrupt bit in the interrupt controller.
SPI Baud Rate Generator
In SPI Master Mode, the Baud Rate Generator creates a lower frequency serial clock
(SCK) for data transmission synchronization between the Master and the external Slave.
The input to the Baud Rate Generator is the system clock. The SPI Baud Rate High and
Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the SPI Baud
Rate Generator. The SPI baud rate is calculated using the following equation:
System Clock Frequency (Hz)
SPI Baud Rate (bits/s) = -----------------------------------------------------------------------2 BRG[15:0]
Minimum baud rate is obtained by setting BRG[15:0] to 0000h for a clock divisor value
of (2 X 65536 = 131072).
When the SPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. Observe the following procedure to configure the Baud Rate
Generator as a timer with interrupt on time-out:
1. Disable the SPI by clearing the SPIEN bit in the SPI Control Register to 0.
2. Load the appropriate 16-bit count value into the SPI Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BIRQ bit in the SPI Control Register to 1.
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When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval (s) = System Clock Period (s) BRG[15:0]
SPI Control Register Definitions
This section defines the features of the following Serial Peripheral Interface registers.
SPI Data Register: see page 121
SPI Control Register: see page 122
SPI Status Register: see page 123
SPI Mode Register: see page 125
SPI Diagnostic State Register: see page 126
SPI Baud Rate High and Low Byte Registers: see page 126
SPI Data Register
The SPI Data Register, shown in Table 64, stores both the outgoing (transmit) data and the
incoming (receive) data. Reads from the SPI Data Register always return the current contents of the 8-bit shift register. Data is shifted out starting with bit 7. The last bit received
resides in bit position 0.
With the SPI configured as a Master, writing a data byte to this register initiates the data
transmission. With the SPI configured as a Slave, writing a data byte to this register loads
the shift register in preparation for the next data transfer with the external Master. In either
the Master or Slave modes, if a transmission is already in progress, writes to this register
are ignored and the overrun error flag, OVR, is set in the SPI Status Register.
When the character length is less than 8 bits (as set by the NUMBITS field in the SPI
Mode Register), the transmit character must be left justified in the SPI Data Register. A
received character of less than 8 bits is right justified (last bit received is in bit position 0).
For example, if the SPI is configured for 4-bit characters, the transmit characters must be
written to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0].
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Table 64. SPI Data Register (SPIDATA)
Bit
7
6
5
4
Field
3
2
1
0
DATA
RESET
X
R/W
R/W
Address
F60h
Bit
Description
[7:0]
DATA
Data
Transmit and/or receive data.
SPI Control Register
The SPI Control Register, shown in Table 65, configures the SPI for transmit and receive
operations.
Table 65. SPI Control Register (SPICTL)
Bit
Field
7
6
5
4
3
2
1
0
IRQE
STR
BIRQ
PHASE
CLKPOL
WOR
MMEN
SPIEN
RESET
0
R/W
R/W
Address
F61h
Bit
Description
[7]
IRQE
Interrupt Request Enable
0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller.
1 = SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller.
[6]
STR
Start an SPI Interrupt Request
0 = No effect.
1 = Setting this bit to 1 also sets the IRQ bit in the SPI Status Register to 1. Setting this bit
forces the SPI to send an interrupt request to the Interrupt Control. This bit can be used by
software for a function similar to transmit buffer empty in a UART. Writing a 1 to the IRQ bit
in the SPI Status Register clears this bit to 0.
[5]
BIRQ
BRG Timer Interrupt Request
If the SPI is enabled, this bit has no effect. If the SPI is disabled:
0 = The Baud Rate Generator timer function is disabled.
1 = The Baud Rate Generator timer function and time-out interrupt are enabled.
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Bit
Description (Continued)
[4]
PHASE
Phase Select
Sets the phase relationship of the data to the clock. For more information about operation of
the PHASE bit, see the SPI Clock Phase and Polarity Control section on page 116.
[3]
Clock Polarity
CLKPOL 0 = SCK idles Low (0).
1 = SCK idle High (1).
[2]
WOR
Wire-OR (Open-Drain) Mode Enabled
0 = SPI signal pins not configured for open-drain.
1 = All four SPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain function. This
setting is typically used for multimaster and/or multislave configurations.
[1]
MMEN
SPI Master Mode Enable
0 = SPI configured in SLAVE Mode.
1 = SPI configured in MASTER Mode.
[0]
SPIEN
SPI Enable
0 = SPI disabled.
1 = SPI enabled.
SPI Status Register
The SPI Status Register, shown in Table 66, indicates the current state of the SPI. All bits
revert to their reset state if the SPIEN bit in the SPICTL Register = 0.
Table 66. SPI Status Register (SPISTAT)
Bit
Field
7
6
5
4
IRQ
OVR
COL
ABT
RESET
3
2
Reserved
0
R/W
1
0
TXST
SLAS
1
R/W*
R
Address
F62h
Note: R/W* = Read access. Write a 1 to clear the bit to 0.
Bit
Description
[7]
IRQ
Interrupt Request
If SPIEN = 1, this bit is set if the STR bit in the SPICTL Register is set, or upon completion of
an SPI master or slave transaction. This bit does not set if SPIEN = 0 and the SPI Baud Rate
Generator is used as a timer to generate the SPI interrupt.
0 = No SPI interrupt request pending.
1 = SPI interrupt request is pending.
[6]
OVR
Overrun
0 = An overrun error has not occurred.
1 = An overrun error has been detected.
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Bit
Description (Continued)
[5]
COL
Collision
0 = A multimaster collision (mode fault) has not occurred.
1 = A multimaster collision (mode fault) has been detected.
[4]
ABT
Slave Mode Transaction Abort
This bit is set if the SPI is configured in Slave Mode, a transaction is occurring and SS deasserts before all bits of a character have been transferred as defined by the NUMBITS field of
the SPIMODE Register. The IRQ bit also sets, indicating the transaction has completed.
0 = A Slave Mode transaction abort has not occurred.
1 = A Slave Mode transaction abort has been detected.
[3:2]
Reserved
These bits are reserved and must be programmed to 00.
[1]
TXST
Transmit Status
0 = No data transmission currently in progress.
1 = Data transmission currently in progress.
[0]
SLAS
Slave Select
If SPI enabled as a Slave, then the following conditions are true:
0 = SS input pin is asserted (Low).
1 = SS input is not asserted (High).
If SPI enabled as a Master, this bit is not applicable.
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SPI Mode Register
The SPI Mode Register, shown in Table 67, configures the character bit width and the
direction and value of the SS pin.
Table 67. SPI Mode Register (SPIMODE)
Bit
7
Field
6
Reserved
RESET
R/W
5
4
DIAG
3
2
NUMBITS[2:0]
1
0
SSIO
SSV
0
R
Address
R/W
F63h
Bit
Description
[7:6]
Reserved
These bits are reserved and must be programmed to 00.
[5]
DIAG
Diagnostic Mode Control bit
This bit is for SPI diagnostics. Setting this bit allows the Baud Rate Generator value to be
read using the SPIBRH and SPIBRL Register locations.
0 = Reading SPIBRH, SPIBRL returns the value in the SPIBRH and SPIBRL registers.
1 = Reading SPIBRH returns bits [15:8] of the SPI Baud Rate Generator; and reading
SPIBRL returns bits [7:0] of the SPI Baud Rate Counter. The Baud Rate Counter High
and Low byte values are not buffered.
Caution: Exercise caution if reading the values while the BRG is counting.
[4]
Number of Data Bits Per Character to Transfer
NUMBITS[2:0] This field contains the number of bits to shift for each character transfer. For information
about valid bit positions when the character length is less than 8 bits, see the SPI Data
Register (SPIDATA) description.
000 = 8 bits.
001 = 1 bit.
010 = 2 bits.
011 = 3 bits.
100 = 4 bits.
101 = 5 bits.
110 = 6 bits.
111 = 7 bits.
[1]
SSIO
Slave Select I/O
0 = SS pin configured as an input.
1 = SS pin configured as an output (Master Mode only).
[0]
SSV
Slave Select Value
If SSIO = 1 and SPI is configured as a Master, the following conditions are true:
0 = SS pin driven Low (0).
1 = SS pin driven High (1).
This bit has no effect if SSIO = 0 or if SPI is configured as a Slave.
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SPI Diagnostic State Register
The SPI Diagnostic State Register, shown in Table 68, provides observability of internal
state. This register is a read-only register that is used for SPI diagnostics.
Table 68. SPI Diagnostic State Register (SPIDST)
Bit
Field
7
6
SCKEN
TCKEN
5
4
3
1
0
SPISTATE
RESET
0
R/W
R
Address
2
F64h
Bit
Description
[7]
SCKEN
Shift Clock Enable
0 = The internal Shift Clock Enable signal is deasserted.
1 = The internal Shift Clock Enable signal is asserted (shift register is updates on next system clock).
[6]
TCKEN
Transmit Clock Enable
0 = The internal Transmit Clock Enable signal is deasserted.
1 = The internal Transmit Clock Enable signal is asserted. When this is asserted the serial
data out is updated on the next system clock (MOSI or MISO).
[5:0]
SPISTATE
SPI State Machine
Defines the current state of the internal SPI State Machine.
SPI Baud Rate High and Low Byte Registers
The SPI Baud Rate High and Low Byte registers, shown in Tables 69 and 70, combine to
form a 16-bit reload value, BRG[15:0], for the SPI Baud Rate Generator.
When configured as a general purpose timer, the SPI BRG interrupt interval is calculated
using the following equation:
SPI BRG Interrupt Interval (s) = System Clock Period (s) BRG[15:0]
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Table 69. SPI Baud Rate High Byte Register (SPIBRH)
Bit
7
6
5
4
Field
3
2
1
0
BRH
RESET
1
R/W
R/W
Address
F66h
Bit
Description
[7:0]
BRH
SPI Baud Rate High Byte
Most significant byte, BRG[15:8], of the SPI Baud Rate Generator’s reload value.
Table 70. SPI Baud Rate Low Byte Register (SPIBRL)
Bit
7
Field
6
5
4
3
2
1
0
BRL
RESET
1
R/W
R/W
Address
F67h
Bit
Description
[7:0]
BRL
SPI Baud Rate Low Byte
Least significant byte, BRG[7:0], of the SPI Baud Rate Generator’s reload value.
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I2C Controller
The I2C Controller makes the Z8 Encore! XP F64xx Series products bus-compatible with
the I2C protocol. The I2C Controller consists of two bidirectional bus lines: a serial data
signal (SDA) and a serial clock signal (SCL). Features of the I2C Controller include:
•
•
•
•
Transmit and Receive Operation in MASTER Mode
Maximum data rate of 400 kilobit/sec
7- and 10-bit addressing modes for Slaves
Unrestricted number of data bytes transmitted per transfer
The I2C Controller in the Z8 Encore! XP F64xx Series products does not operate in
SLAVE Mode.
Architecture
Figure 27 displays the architecture of the I2C Controller.
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SDA
SCL
Shift
ISHIFT
Load
I2CDATA
Baud Rate Generator
I2CBRH
Receive
I2CBRL
Tx/Rx State Machine
I2CCTL
I2C Interrupt
I2CSTAT
Register Bus
Figure 27. I2C Controller Block Diagram
Operation
The I2C Controller operates in MASTER Mode to transmit and receive data. Only a single
master is supported. Arbitration between two masters must be accomplished in software.
I2C supports the following operations:
•
•
•
•
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Master transmits to a 10-bit slave
Master receives from a 7-bit slave
Master receives from a 10-bit slave
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SDA and SCL Signals
I2C sends all addresses, data and acknowledge signals over the SDA line, most significant
bit first. SCL is the common clock for the I2C Controller. When the SDA and SCL pin
alternate functions are selected for their respective GPIO ports, the pins are automatically
configured for open-drain operation.
The master (I2C) is responsible for driving the SCL clock signal, although the clock signal
can become skewed by a slow slave device. During the low period of the clock, the slave
pulls the SCL signal Low to suspend the transaction. The master releases the clock at the
end of the low period and notices that the clock remains low instead of returning to a High
level. When the slave releases the clock, the I2C Controller continues the transaction. All
data is transferred in bytes and there is no limit to the amount of data transferred in one
operation. When transmitting data or acknowledging read data from the slave, the SDA
signal changes in the middle of the low period of SCL and is sampled in the middle of the
High period of SCL.
I2C Interrupts
The I2C Controller contains four sources of interrupts—Transmit, Receive, Not Acknowledge and baud rate generator. These four interrupt sources are combined into a single
interrupt request signal to the Interrupt Controller. The transmit interrupt is enabled by the
IEN and TXI bits of the Control Register. The Receive and Not Acknowledge interrupts
are enabled by the IEN bit of the Control Register. The baud rate generator interrupt is
enabled by the BIRQ and IEN bits of the Control Register.
Not Acknowledge interrupts occur when a Not Acknowledge condition is received from
the slave or sent by the I2C Controller and neither the start or stop bit is set. The Not
Acknowledge event sets the NCKI bit of the I2C Status Register and can only be cleared
by setting the start or stop bit in the I2C Control Register. When this interrupt occurs, the
I2C Controller waits until either the stop or start bit is set before performing any action. In
an interrupt service routine, the NCKI bit should always be checked prior to servicing
transmit or receive interrupt conditions because it indicates the transaction is being terminated.
Receive interrupts occur when a byte of data has been received by the I2C Controller
(master reading data from slave). This procedure sets the RDRF bit of the I2C Status Register. The RDRF bit is cleared by reading the I2C Data Register. The RDRF bit is set during the acknowledge phase. The I2C Controller pauses after the acknowledge phase until
the receive interrupt is cleared before performing any other action.
Transmit interrupts occur when the TDRE bit of the I2C Status Register sets and the TXI
bit in the I2C Control Register is set. transmit interrupts occur under the following conditions when the transmit data register is empty:
•
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•
The first bit of the byte of an address is shifting out and the RD bit of the I2C Status
Register is deasserted.
•
•
The first bit of a 10-bit address shifts out
The first bit of write data shifts out
Note: Writing to the I2C Data Register always clears the TRDE bit to 0. When TDRE is asserted,
the I2C Controller pauses at the beginning of the Acknowledge cycle of the byte currently
shifting out. It does not resume until the Data Register is written with the next value to
send or until the stop or start bits are set, indicating that the current byte is the last one to
send.
The fourth interrupt source is the baud rate generator. If the I2C Controller is disabled
(IEN bit in the I2CCTL Register = 0) and the BIRQ bit in the I2CCTL Register = 1, an
interrupt is generated when the baud rate generator counts down to 1. This allows the I2C
baud rate generator to be used by software as a general purpose timer when IEN = 0.
Software Control of I2C Transactions
Software can control I2C transactions by using the I2C Controller interrupt, by polling the
I2C Status Register or by DMA. Note that not all products include a DMA Controller.
To use interrupts, the I2C interrupt must be enabled in the Interrupt Controller. The TXI bit
in the I2C Control Register must be set to enable transmit interrupts.
To control transactions by polling, the interrupt bits (TDRE, RDRF and NCKI) in the I2C
Status Register should be polled. The TDRE bit asserts regardless of the state of the TXI
bit.
Either or both transmit and receive data movement can be controlled by the DMA Controller. The DMA Controller channel(s) must be initialized to select the I2C transmit and
receive requests. Transmit DMA requests require that the TXI bit in the I2C Control Register be set.
Caution: A transmit (write) DMA operation hangs if the slave responds with a Not Acknowledge
before the last byte has been sent. After receiving the Not Acknowledge, the I2C Controller sets the NCKI bit in the Status Register and pauses until either the stop or start bits in
the Control Register are set.
For a receive (read) DMA transaction to send a Not Acknowledge on the last byte, the
receive DMA must be set up to receive n-1 bytes, then software must set the NAK bit and
receive the last (nth) byte directly.
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Start and Stop Conditions
The master (I2C) drives all start and stop signals and initiates all transactions. To start a
transaction, the I2C Controller generates a start condition by pulling the SDA signal Low
while SCL is High. To complete a transaction, the I2C Controller generates a stop condition by creating a low-to-High transition of the SDA signal while the SCL signal is High.
The start and stop bits in the I2C Control Register control the sending of the start and stop
conditions. A master is also allowed to end one transaction and begin a new one by issuing
a Restart. This is accomplished by setting the start bit at the end of a transaction, rather
than the stop bit. Note that a start condition not sent until the start bit is set and data has
been written to the I2C Data Register.
Master Write and Read Transactions
The following sections provide a recommended procedure for performing I2C write and
read transactions from the I2C Controller (master) to slave I2C devices. In general software should rely on the TDRE, RDRF and NCKI bits of the status register (these bits generate interrupts) to initiate software actions. When using interrupts or DMA, the TXI bit is
set to start each transaction and cleared at the end of each transaction to eliminate a trailing transmit interrupt.
Caution should be used in using the ACK status bit within a transaction because it is difficult for software to tell when it is updated by hardware.
When writing data to a slave, the I2C pauses at the beginning of the Acknowledge cycle if
the data register has not been written with the next value to be sent (TDRE bit in the I2C
Status Register = 1). In this scenario where software is not keeping up with the I2C bus
(TDRE asserted longer than one byte time), the Acknowledge clock cycle for byte n is
delayed until the Data Register is written with byte n + 1, and appears to be grouped with
the data clock cycles for byte n+1. If either the start or stop bit is set, the I2C does not
pause prior to the Acknowledge cycle because no additional data is sent.
When a Not Acknowledge condition is received during a write (either during the address
or data phases), the I2C Controller generates the Not Acknowledge interrupt (NCKI = 1)
and pause until either the stop or start bit is set. Unless the Not Acknowledge was received
on the last byte, the Data Register will already have been written with the next address or
data byte to send. In this case the flush bit of the Control Register should be set at the same
time the stop or start bit is set to remove the stale transmit data and enable subsequent
transmit interrupts.
When reading data from the slave, the I2C pauses after the data Acknowledge cycle until
the receive interrupt is serviced and the RDRF bit of the status register is cleared by reading the I2C Data Register. Once the I2C data register has been read, the I2C reads the next
data byte.
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Address Only Transaction with a 7-bit Address
In the situation where software determines if a slave with a 7-bit address is responding
without sending or receiving data, a transaction can be done which only consists of an
address phase. Figure 28 displays this address only transaction to determine if a slave with
a 7-bit address will acknowledge. As an example, this transaction can be used after a write
has been performed to an EEPROM to determine when the EEPROM completes its internal write operation and is again responding to I2C transactions. If the slave does not
Acknowledge, the transaction can be repeated until the slave does Acknowledge.
S
Slave Address
W=0
A/A
P
Figure 28. 7-Bit Address Only Transaction Format
Observe the following procedure for an address only transaction to a 7-bit addressed slave:
1. Software asserts the IEN bit in the I2C Control Register.
2. Software asserts the TXI bit of the I2C Control Register to enable transmit interrupts.
3. The I2C interrupt asserts, because the I2C Data Register is empty (TDRE = 1)
4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (= 0)
to the I2C Data Register. As an alternative this could be a read operation instead of a
write operation.
5. Software sets the start and stop bits of the I2C Control Register and clears the TXI bit.
6. The I2C Controller sends the start condition to the I2C slave.
7. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Register.
8. Software polls the stop bit of the I2C Control Register. Hardware deasserts the stop bit
when the address only transaction is completed.
9.
Software checks the ACK bit of the I2C Status Register. If the slave acknowledged,
the ACK bit is = 1. If the slave does not acknowledge, the ACK bit is = 0. The NCKI
interrupt does not occur in the not acknowledge case because the stop bit was set.
Write Transaction with a 7-Bit Address
Figure 29 displays the data transfer format for a 7-bit addressed slave. Shaded regions
indicate data transferred from the I2C Controller to slaves and unshaded regions indicate
data transferred from the slaves to the I2C Controller.
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S
Slave Address
W=0
A
Data
A
Data
A
Data
A/A
P/S
Figure 29. 7-Bit Addressed Slave Data Transfer Format
Observe the following procedure for a transmit operation to a 7-bit addressed slave:
1. Software asserts the IEN bit in the I2C Control Register.
2. Software asserts the TXI bit of the I2C Control Register to enable transmit interrupts.
3. The I2C interrupt asserts, because the I2C Data Register is empty
4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (=0)
to the I2C Data Register.
5. Software asserts the start bit of the I2C Control Register.
6. The I2C Controller sends the start condition to the I2C slave.
7. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Register.
8. After one bit of address has been shifted out by the SDA signal, the transmit interrupt
is asserted (TDRE = 1).
9. Software responds by writing the transmit data into the I2C Data Register.
10. The I2C Controller shifts the rest of the address and write bit out by the SDA signal.
11. If the I2C slave sends an acknowledge (by pulling the SDA signal Low) during the
next High period of SCL the I2C Controller sets the ACK bit in the I2C Status Register. Continue with Step 12.
If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is
set in the Status Register, ACK bit is cleared). Software responds to the Not Acknowledge interrupt by setting the stop and flush bits and clearing the TXI bit. The I2C Controller sends the stop condition on the bus and clears the stop and NCKI bits. The
transaction is complete (ignore the following steps).
12. The I2C Controller loads the contents of the I2C Shift Register with the contents of the
I2C Data Register.
13. The I2C Controller shifts the data out of using the SDA signal. After the first bit is
sent, the transmit interrupt is asserted.
14. If more bytes remain to be sent, return to Step 9.
15. Software responds by setting the stop bit of the I2C Control Register (or start bit to initiate a new transaction). In the stop case, software clears the TXI bit of the I2C Control
Register at the same time.
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16. The I2C Controller completes transmission of the data on the SDA signal.
17. The slave may either Acknowledge or Not Acknowledge the last byte. Because either
the stop or start bit is already set, the NCKI interrupt does not occur.
18. The I2C Controller sends the stop (or RESTART) condition to the I2C bus. The stop or
start bit is cleared.
Address Only Transaction with a 10-bit Address
In the situation where software wants to determine if a slave with a 10-bit address is
responding without sending or receiving data, a transaction can be done which only consists of an address phase. Figure 30 displays this address only transaction to determine if a
slave with 10-bit address will acknowledge. As an example, this transaction can be used
after a write has been performed to an EEPROM to determine when the EEPROM completes its internal write operation and is again responding to I2C transactions. If the slave
does not Acknowledge the transaction can be repeated until the slave is able to Acknowledge.
S
Slave Address
1st 7 bits
W=0
A/A
Slave Address
2nd Byte
A/A P
Figure 30. 10-Bit Address Only Transaction Format
Observe the following procedure for an address only transaction to a 10-bit addressed
slave:
1. Software asserts the IEN bit in the I2C Control Register.
2. Software asserts the TXI bit of the I2C Control Register to enable transmit interrupts.
3. The I2C interrupt asserts, because the I2C Data Register is empty (TDRE = 1)
4. Software responds to the TDRE interrupt by writing the first slave address byte. The
least significant bit must be 0 for the write operation.
5. Software asserts the start bit of the I2C Control Register.
6. The I2C Controller sends the start condition to the I2C slave.
7. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Register.
8. After one bit of address is shifted out by the SDA signal, the transmit interrupt is
asserted.
9. Software responds by writing the second byte of address into the contents of the I2C
Data Register.
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10. The I2C Controller shifts the rest of the first byte of address and write bit out the SDA
signal.
11. If the I2C slave sends an acknowledge by pulling the SDA signal Low during the next
High period of SCL the I2C Controller sets the ACK bit in the I2C Status Register.
Continue with Step 12.
If the slave does not acknowledge the first address byte, the I2C Controller sets the
NCKI bit and clears the ACK bit in the I2C Status Register. Software responds to the
Not Acknowledge interrupt by setting the stop and flush bits and clearing the TXI bit.
The I2C Controller sends the stop condition on the bus and clears the stop and NCKI
bits. The transaction is complete (ignore following steps).
12. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Register (2nd byte of address).
13. The I2C Controller shifts the second address byte out the SDA signal. After the first
bit has been sent, the transmit interrupt is asserted.
14. Software responds by setting the stop bit in the I2C Control Register. The TXI bit can
be cleared at the same time.
15. Software polls the stop bit of the I2C Control Register. Hardware deasserts the stop bit
when the transaction is completed (stop condition has been sent).
16. Software checks the ACK bit of the I2C Status Register. If the slave acknowledged,
the ACK bit is = 1. If the slave does not acknowledge, the ACK bit is = 0. The NCKI
interrupt do not occur because the stop bit was set.
Write Transaction with a 10-Bit Address
Figure 31 displays the data transfer format for a 10-bit addressed slave. Shaded regions
indicate data transferred from the I2C Controller to slaves and unshaded regions indicate
data transferred from the slaves to the I2C Controller.
S
Slave Address
1st 7 bits
W=0
A
Slave Address
2nd Byte
A
Data
A
Data
A/A
P/S
Figure 31. 10-Bit Addressed Slave Data Transfer Format
The first seven bits transmitted in the first byte are 11110XX. The two bits XX are the two
most significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
read/write control bit (=0). The transmit operation is carried out in the same manner as 7bit addressing.
Observe the following procedure for a transmit operation on a 10-bit addressed slave:
1. Software asserts the IEN bit in the I2C Control Register.
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2. Software asserts the TXI bit of the I2C Control Register to enable transmit interrupts.
3. The I2C interrupt asserts because the I2C Data Register is empty.
4. Software responds to the TDRE interrupt by writing the first slave address byte to the
I2C Data Register. The least significant bit must be 0 for the write operation.
5. Software asserts the start bit of the I2C Control Register.
6. The I2C Controller sends the start condition to the I2C slave.
7. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Register.
8. After one bit of address is shifted out by the SDA signal, the transmit interrupt is
asserted.
9. Software responds by writing the second byte of address into the contents of the I2C
Data Register.
10. The I2C Controller shifts the rest of the first byte of address and write bit out the SDA
signal.
11. If the I2C slave acknowledges the first address byte by pulling the SDA signal Low
during the next High period of SCL, the I2C Controller sets the ACK bit in the I2C
Status Register. Continue with Step 12.
If the slave does not acknowledge the first address byte, the I2C Controller sets the
NCKI bit and clears the ACK bit in the I2C Status Register. Software responds to the
Not Acknowledge interrupt by setting the stop and flush bits and clearing the TXI bit.
The I2C Controller sends the stop condition on the bus and clears the stop and NCKI
bits. The transaction is complete (ignore the following steps).
12. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Register.
13. The I2C Controller shifts the second address byte out the SDA signal. After the first
bit has been sent, the transmit interrupt is asserted.
14. Software responds by writing a data byte to the I2C Data Register.
15. The I2C Controller completes shifting the contents of the shift register on the SDA
signal.
16. If the I2C slave sends an acknowledge by pulling the SDA signal Low during the next
High period of SCL, the I2C Controller sets the ACK bit in the I2C Status Register.
Continue with Step 17.
If the slave does not acknowledge the second address byte or one of the data bytes, the
I2C Controller sets the NCKI bit and clears the ACK bit in the I2C Status Register.
Software responds to the Not Acknowledge interrupt by setting the stop and flush bits
and clearing the TXI bit. The I2C Controller sends the stop condition on the bus and
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clears the stop and NCKI bits. The transaction is complete (ignore the following
steps).
17. The I2C Controller shifts the data out by the SDA signal. After the first bit is sent, the
transmit interrupt is asserted.
18. If more bytes remain to be sent, return to Step 14.
19. If the last byte is currently being sent, software sets the stop bit of the I2C Control
Register (or start bit to initiate a new transaction). In the stop case, software also clears
the TXI bit of the I2C Control Register at the same time.
20. The I2C Controller completes transmission of the last data byte on the SDA signal.
21. The slave may either Acknowledge or Not Acknowledge the last byte. Because either
the stop or start bit is already set, the NCKI interrupt does not occur.
22. The I2C Controller sends the stop (or RESTART) condition to the I2C bus and clears
the stop (or start) bit.
Read Transaction with a 7-Bit Address
Figure 32 displays the data transfer format for a read operation to a 7-bit addressed slave.
The shaded regions indicate data transferred from the I2C Controller to slaves and
unshaded regions indicate data transferred from the slaves to the I2C Controller.
S
Slave Address
R=1
A
Data
A
Data
A
P/S
Figure 32. Receive Data Transfer Format for a 7-Bit Addressed Slave
Observe the following procedure for a read operation to a 7-bit addressed slave:
1. Software writes the I2C Data Register with a 7-bit slave address plus the read bit (= 1).
2. Software asserts the start bit of the I2C Control Register.
3. If this is a single byte transfer, Software asserts the NAK bit of the I2C Control Register so that after the first byte of data has been read by the I2C Controller, a Not
Acknowledge is sent to the I2C slave.
4. The I2C Controller sends the start condition.
5. The I2C Controller shifts the address and read bit out the SDA signal.
6. If the I2C slave acknowledges the address by pulling the SDA signal Low during the
next High period of SCL, the I2C Controller sets the ACK bit in the I2C Status Register. Continue with Step 7.
If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is
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set in the Status Register, ACK bit is cleared). Software responds to the Not Acknowledge interrupt by setting the stop bit and clearing the TXI bit. The I2C Controller
sends the stop condition on the bus and clears the stop and NCKI bits. The transaction
is complete (ignore the following steps).
7. The I2C Controller shifts in the byte of data from the I2C slave on the SDA signal. The
I2C Controller sends a Not Acknowledge to the I2C slave if the NAK bit is set (last
byte), else it sends an Acknowledge.
8. The I2C Controller asserts the receive interrupt (RDRF bit set in the Status Register).
9. Software responds by reading the I2C Data Register which clears the RDRF bit. If
there is only one more byte to receive, set the NAK bit of the I2C Control Register.
10. If there are more bytes to transfer, return to Step 7.
11. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I2C
Controller.
12. Software responds by setting the stop bit of the I2C Control Register.
13. A stop condition is sent to the I2C slave, the stop and NCKI bits are cleared.
Read Transaction with a 10-Bit Address
Figure 33 displays the read transaction format for a 10-bit addressed slave. The shaded
regions indicate data transferred from the I2C Controller to slaves and unshaded regions
indicate data transferred from the slaves to the I2C Controller.
S
Slave Address
Slave Address
W=0 A
A
1st 7 bits
2nd Byte
S
Slave Address
R=1
1st 7 bits
A
Data
A
Data
A
P
Figure 33. Receive Data Format for a 10-Bit Addressed Slave
The first seven bits transmitted in the first byte are 11110XX. The two (XX) bits are the two
most significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
Observe the following procedure for the data transfer for a read operation to a 10-bit
addressed slave:
1. Software writes 11110B followed by the two address bits and a 0 (write) to the I2C
Data Register.
2. Software asserts the start and TXI bits of the I2C Control Register.
3. The I2C Controller sends a start condition.
4. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Register.
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5. After the first bit has been shifted out, a transmit interrupt is asserted.
6. Software responds by writing the lower eight bits of address to the I2C Data Register.
7. The I2C Controller completes shifting of the two address bits and a 0 (write).
8. If the I2C slave acknowledges the first address byte by pulling the SDA signal Low
during the next High period of SCL, the I2C Controller sets the ACK bit in the I2C
Status Register. Continue with Step 9.
If the slave does not acknowledge the first address byte, the I2C Controller sets the
NCKI bit and clears the ACK bit in the I2C Status Register. Software responds to the
Not Acknowledge interrupt by setting the stop and flush bits and clearing the TXI bit.
The I2C Controller sends the stop condition on the bus and clears the stop and NCKI
bits. The transaction is complete (ignore following steps).
9. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Register (second address byte).
10. The I2C Controller shifts out the second address byte. After the first bit is shifted, the
I2C Controller generates a transmit interrupt.
11. Software responds by setting the start bit of the I2C Control Register to generate a
repeated start by clearing the TXI bit.
12. Software responds by writing 11110B followed by the 2-bit slave address and a 1
(read) to the I2C Data Register.
13. If only one byte is to be read, software sets the NAK bit of the I2C Control Register.
14. After the I2C Controller shifts out the 2nd address byte, the I2C slave sends an
acknowledge by pulling the SDA signal Low during the next High period of SCL, the
I2C Controller sets the ACK bit in the I2C Status Register. Continue with Step 15.
If the slave does not acknowledge the second address byte, the I2C Controller sets the
NCKI bit and clears the ACK bit in the I2C Status Register. Software responds to the
Not Acknowledge interrupt by setting the stop and flush bits and clearing the TXI bit.
The I2C Controller sends the stop condition on the bus and clears the stop and NCKI
bits. The transaction is complete (ignore the following steps).
15. The I2C Controller sends the repeated start condition.
16. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Register (third address transfer).
17. The I2C Controller sends 11110B followed by the two most significant bits of the
slave read address and a 1 (read).
18. The I2C slave sends an acknowledge by pulling the SDA signal Low during the next
High period of SCL
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If the slave were to Not Acknowledge at this point (this should not happen because the
slave did acknowledge the first two address bytes), software would respond by setting
the stop and flush bits and clearing the TXI bit. The I2C Controller sends the stop condition on the bus and clears the stop and NCKI bits. The transaction is complete
(ignore the following steps).
19. The I2C Controller shifts in a byte of data from the I2C slave on the SDA signal. The
I2C Controller sends a Not Acknowledge to the I2C slave if the NAK bit is set (last
byte), else it sends an Acknowledge.
20. The I2C Controller asserts the receive interrupt (RDRF bit set in the Status Register).
21. Software responds by reading the I2C Data Register which clears the RDRF bit. If
there is only one more byte to receive, set the NAK bit of the I2C Control Register.
22. If there are one or more bytes to transfer, return to Step 19.
23. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I2C
Controller.
24. Software responds by setting the stop bit of the I2C Control Register.
25. A stop condition is sent to the I2C slave and the stop and NCKI bits are cleared.
I2C Control Register Definitions
This section defines the features of the following I2C Control registers.
I2C Data Register: see page 141
I2C Status Register: see page 142
I2C Control Register: see page 144
I2C Baud Rate High and Low Byte Registers: see page 145
I2C Diagnostic State Register: see page 147
I2C Diagnostic Control Register: see page 149
I2C Data Register
The I2C Data Register, shown in Table 71, holds the data that is to be loaded into the I2C
Shift Register during a write to a slave. This register also holds data that is loaded from the
I2C Shift Register during a read from a slave. The I2C Shift Register is not accessible in
the register file address space, but is used only to buffer incoming and outgoing data.
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Table 71. I2C Data Register (I2CDATA)
Bit
7
6
5
4
Field
3
2
1
0
DATA
RESET
0
R/W
R/W
Address
F50h
I2C Status Register
The read-only I2C Status Register, shown in Table 72, indicates the status of the I2C Controller.
Table 72. I2C Status Register (I2CSTAT)
Bit
Field
RESET
7
6
5
4
3
2
1
0
TDRE
RDRF
ACK
10B
RD
TAS
DSS
NCKI
1
R/W
0
R
Address
F51h
Bit
Description
[7]
TDRE
Transmit Data Register Empty
When the I2C Controller is enabled, this bit is 1 when the I2C Data Register is empty. When this
bit is set, an interrupt is generated if the TXI bit is set, except when the I2C Controller is shifting
in data during the reception of a byte or when shifting an address and the RD bit is set. This bit
is cleared by writing to the I2CDATA Register.
[6]
RDRF
Receive Data Register Full
This bit is set = 1 when the I2C Controller is enabled and the I2C Controller has received a byte
of data. When asserted, this bit causes the I2C Controller to generate an interrupt. This bit is
cleared by reading the I2C Data Register (unless the read is performed using execution of the
On-Chip Debugger’s Read Register command).
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Bit
Description (Continued)
[5]
ACK
Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received. When
set, this bit indicates that an Acknowledge occurred for the last byte transmitted or received.
This bit is cleared when IEN = 0 or when a Not Acknowledge occurred for the last byte transmitted or received. It is not reset at the beginning of each transaction and is not reset when this
register is read.
Caution: When making decisions based on this bit within a transaction, software cannot determine when the bit is updated by hardware. In the case of write transactions, the I2C pauses at
the beginning of the Acknowledge cycle if the next transmit data or address byte has not been
written (TDRE = 1) and stop and start = 0. In this case the ACK bit is not updated until the
transmit interrupt is serviced and the Acknowledge cycle for the previous byte completes. For
examples of how the ACK bit can be used, see the Address Only Transaction with a 7-bit
Address section on page 133 and the Address Only Transaction with a 10-bit Address section
on page 135.
[4]
10B
10-Bit Address
This bit indicates whether a 10- or 7-bit address is being transmitted. After the start bit is set, if
the five most significant bits of the address are 11110B, this bit is set. When set, it is reset
once the first byte of the address has been sent.
[3]
RD
Read
This bit indicates the direction of transfer of the data. It is active High during a read. The status
of this bit is determined by the least significant bit of the I2C Shift Register after the start bit is
set.
[2]
TAS
Transmit Address State
This bit is active High while the address is being shifted out of the I2C Shift Register.
[1]
DSS
Data Shift State
This bit is active High while data is being shifted to or from the I2C Shift Register.
[0]
NCKI
NACK Interrupt
This bit is set High when a Not Acknowledge condition is received or sent and neither the start
nor the stop bit is active. When set, this bit generates an interrupt that can only be cleared by
setting the start or stop bit, allowing you to specify whether to perform a stop or a repeated
start.
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I2C Control Register
The I2C Control Register, shown in Table 73, enables I2C operation.
Table 73. I2C Control Register (I2CCTL)
Bit
Field
7
6
5
4
3
2
1
0
IEN
START
STOP
BIRQ
TXI
NAK
FLUSH
FILTEN
R/W
R/W1
W1
R/W
RESET
R/W
0
R/W
Address
R/W1
R/W1
R/W
F52h
Bit
Description
[7]
IEN
I2C Enable
1 = The I2C transmitter and receiver are enabled.
0 = The I2C transmitter and receiver are disabled.
[6]
START
Send Start Condition
This bit sends a start condition. Once asserted, it is cleared by the I2C Controller after it sends
a start condition or if the IEN bit is deasserted. If this bit is 1, it cannot be cleared to 0 by writing
to the register. After this bit is set, a start condition is sent if there is data in the I2C Data Register or I2C Shift Register. If there is no data in one of these registers, the I2C Controller waits
until the Data Register is written. If this bit is set while the I2C Controller is shifting out data, it
generates a start condition after the byte shifts and the acknowledge phase completes. If the
stop bit is also set, it also waits until the stop condition is sent before the sending the start condition.
[5]
STOP
Send Stop Condition
This bit causes the I2C Controller to issue a stop condition after the byte in the I2C Shift Register has completed transmission or after a byte has been received in a receive operation. AFter
it is set, this bit is reset by the I2C Controller after a stop condition has been sent or by deasserting the IEN bit. If this bit is 1, it cannot be cleared to 0 by writing to the register.
[4]
BIRQ
Baud Rate Generator Interrupt Request
This bit allows the I2C Controller to be used as an additional timer when the I2C Controller is
disabled. This bit is ignored when the I2C Controller is enabled.
1 = An interrupt occurs every time the baud rate generator counts down to one.
0 = No baud rate generator interrupt occurs.
[3]
TXI
Enable TDRE Interrupts
This bit enables the transmit interrupt when the I2C Data Register is empty (TDRE = 1).
1 = Transmit interrupt (and DMA transmit request) is enabled.
0 = Transmit interrupt (and DMA transmit request) is disabled.
[2]
NAK
Send NAK
This bit sends a Not Acknowledge condition after the next byte of data has been read from the
I2C slave. Once asserted, it is deasserted after a Not Acknowledge is sent or the IEN bit is
deasserted. If this bit is 1, it cannot be cleared to 0 by writing to the register.
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Bit
Description (Continued)
[1]
FLUSH
Flush Data
Setting this bit to 1 clears the I2C Data Register and sets the TDRE bit to 1. This bit allows
flushing of the I2C Data Register when a Not Acknowledge interrupt is received after the data
has been sent to the I2C Data Register. Reading this bit always returns 0.
[0]
FILTEN
I2C Signal Filter Enable
This bit enables low-pass digital filters on the SDA and SCL input signals. These filters reject
any input pulse with periods less than a full system clock cycle. The filters introduce a 3-system clock cycle latency on the inputs.
1 = low-pass filters are enabled.
0 = low-pass filters are disabled.
I2C Baud Rate High and Low Byte Registers
The I2C Baud Rate High and Low Byte registers, shown in Tables 74 and 75, combine to
form a 16-bit reload value, BRG[15:0], for the I2C Baud Rate Generator.
When the I2C is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the I2C by clearing the IEN bit in the I2C Control Register to 0.
2. Load the appropriate 16-bit count value into the I2C Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BIRQ bit in the I2C Control Register to 1.
When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval (s) = System Clock Period (s) BRG 15:0
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Table 74. I2C Baud Rate High Byte Register (I2CBRH)
Bit
7
6
5
4
3
Field
BRH
RESET
FFh
R/W
R/W
Address
F53h
2
1
0
Bit
Description
[7:0]
BRH
I2C Baud Rate High Byte
Most significant byte, BRG[15:8], of the I2C Baud Rate Generator’s reload value.
Note: If the DIAG bit in the I2C Diagnostic Control Register is set to 1, a read of the I2CBRH
Register returns the current value of the I2C Baud Rate Counter[15:8].
Table 75. I2C Baud Rate Low Byte Register (I2CBRL)
Bit
7
6
5
4
3
Field
BRL
RESET
FFh
R/W
R/W
Address
F54h
2
1
0
Bit
Description
[7:0]
BRL
I2C Baud Rate Low Byte
Least significant byte, BRG[7:0], of the I2C Baud Rate Generator’s reload value.
Note: If the DIAG bit in the I2C Diagnostic Control Register is set to 1, a read of the I2CBRL
Register returns the current value of the I2C Baud Rate Counter[7:0].
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I2C Diagnostic State Register
The I2C Diagnostic State Register, shown in Table 76, provides observability into the
internal state. This register is read-only; it is used for I2C diagnostics and manufacturing
test purposes.
Table 76. I2C Diagnostic State Register (I2CDST)
Bit
Field
7
6
5
SCLIN
SDAIN
STPCNT
RESET
4
3
1
0
TXRXSTATE
X
0
R/W
R
Address
F55h
Bit
Description
[7]
SCLIN
Serial Clock Input
Value of the Serial Clock input signal.
[6]
SDAIN
Serial Data Input
Value of the Serial Data input signal.
[5]
STPCNT
Stop Count
Value of the internal Stop Count control signal.
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Bit
Description (Continued)
[4:0]
TXRXSTATE
Internal State
Value of the internal I2C state machine.
[4:0]
TXRXSTATE
(continued)
TXRXSTATE
State Description
0_0000
0_0001
0_0010
0_0011
0_0100
0_0101
0_0110
0_0111
0_1000
0_1001
0_1010
0_1011
0_1100
0_1101
0_1110
Idle State.
Start State.
Send/Receive data bit 7.
Send/Receive data bit 6.
Send/Receive data bit 5.
Send/Receive data bit 4.
Send/Receive data bit 3.
Send/Receive data bit 2.
Send/Receive data bit 1.
Send/Receive data bit 0.
Data Acknowledge State.
Second half of data Acknowledge State used only for not acknowledge.
First part of stop state.
Second part of stop state.
10-bit addressing: Acknowledge State for 2nd address byte
7-bit addressing: Address Acknowledge State.
10-bit address: Bit 0 (Least significant bit) of 2nd address byte
7-bit address: Bit 0 (Least significant bit) (R/W) of address byte.
10-bit addressing: Bit 7 (Most significant bit) of 1st address byte.
10-bit addressing: Bit 6 of 1st address byte.
10-bit addressing: Bit 5 of 1st address byte.
10-bit addressing: Bit 4 of 1st address byte.
10-bit addressing: Bit 3 of 1st address byte.
10-bit addressing: Bit 2 of 1st address byte.
10-bit addressing: Bit 1 of 1st address byte.
10-bit addressing: Bit 0 (R/W) of 1st address byte.
10-bit addressing: Acknowledge state for 1st address byte.
10-bit addressing: Bit 7 of 2nd address byte
7-bit addressing: Bit 7 of address byte.
10-bit addressing: Bit 6 of 2nd address byte
7-bit addressing: Bit 6 of address byte.
10-bit addressing: Bit 5 of 2nd address byte
7-bit addressing: Bit 5 of address byte.
10-bit addressing: Bit 4 of 2nd address byte
7-bit addressing: Bit 4 of address byte.
10-bit addressing: Bit 3 of 2nd address byte
7-bit addressing: Bit 3 of address byte.
10-bit addressing: Bit 2 of 2nd address byte
7-bit addressing: Bit 2 of address byte.
10-bit addressing: Bit 1 of 2nd address byte
7-bit addressing: Bit 1 of address byte.
0_1111
1_0000
1_0001
1_0010
1_0011
1_0100
1_0101
1_0110
1_0111
1_1000
1_1001
1_1010
1_1011
1_1100
1_1101
1_1110
1_1111
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I2C Diagnostic Control Register
The I2C Diagnostic Register, shown in Table 77, provides control over diagnostic modes.
This register is a read/write register that is used for I2C diagnostics purposes.
Table 77. I2C Diagnostic Control Register (I2CDIAG)
Bit
7
Field
6
5
4
3
Reserved
RESET
2
1
0
DIAG
0
R/W
R
Address
R/W
F56h
Bit
Description
[7:1]
Reserved
These bits are reserved and must be programmed to 0000000.
[0]
DIAG
Diagnostic Control Bit
Selects read back value of the Baud Rate Reload registers.
0 = Normal Mode. Reading the Baud Rate High and Low Byte registers returns the baud rate
reload value.
1 = DIAGNOSTIC Mode. Reading the Baud Rate High and Low Byte registers returns the baud
rate counter value.
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Direct Memory Access Controller
The Z8 Encore! XP F64xx Series Direct Memory Access (DMA) Controller provides
three independent Direct Memory Access channels. Two of the channels, DMA0 and
DMA1, transfer data between the on-chip peripherals and the register file. The third channel, DMA_ADC, controls the ADC operation and transfers SINGLE-SHOT Mode ADC
output data to the register file.
Operation
DMA0 and DMA1, referred to collectively as DMAx, transfer data either from the on-chip
peripheral control registers to the register file, or from the register file to the on-chip
peripheral control registers. The sequence of operations in a DMAx data transfer is:
1. DMAx trigger source requests a DMA data transfer.
2. DMAx requests control of the system bus (address and data) from the eZ8 CPU.
3. After the eZ8 CPU acknowledges the bus request, DMAx transfers either a single byte
or a two-byte word (depending upon configuration) and then returns system bus control to the eZ8 CPU.
4. If the Current Address equals the End Address, then the following conditions are true:
– DMAx reloads the original Start Address
– If configured to generate an interrupt, DMAx sends an interrupt request to the
Interrupt Controller
– If configured for single-pass operation, DMAx resets the DEN bit in the DMAx
Control Register to 0 and the DMA is disabled
If the Current Address does not equal the End Address, then the Current Address
increments by 1 (single-byte transfer) or 2 (two-byte word transfer).
Configuring DMA0 and DMA1 for Data Transfer
Observe the following procedure to configure and enable DMA0 or DMA1:
1. Write to the DMAx I/O Address Register to set the register file address identifying the
on-chip peripheral control register. The upper nibble of the 12-bit address for on-chip
peripheral control registers is always Fh. The full address is {Fh, DMAx_IO[7:0]}.
2. Determine the 12-bit starting and ending register file addresses. The 12-bit Start
Address is provided by {DMAx_H[3:0], DMA_START[7:0]}. The 12-bit End
Address is provided by {DMAx_H[7:4], DMA_END[7:0]}.
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3. Write the start and end register file address high nibbles to the DMAx End/Start
Address High Nibble Register.
4. Write the lower byte of the Start Address to the DMAx Start/Current Address Register.
5. Write the lower byte of the End Address to the DMAx End Address Register.
6. Write to the DMAx Control Register to complete the following operations:
– Select loop or single-pass mode operation
– Select the data transfer direction (either from the register file RAM to the on-chip
peripheral control register; or from the on-chip peripheral control register to the
register file RAM)
– Enable the DMAx interrupt request, if appropriate
– Select Word or Byte mode
– Select the DMAx request trigger
– Enable the DMAx channel
DMA_ADC Operation
DMA_ADC transfers data from the ADC to the register file. The sequence of operations
in a DMA_ADC data transfer is:
1. ADC completes conversion on the current ADC input channel and signals the DMA
controller that two-bytes of ADC data are ready for transfer.
2. DMA_ADC requests control of the system bus (address and data) from the eZ8 CPU.
3. After the eZ8 CPU acknowledges the bus request, DMA_ADC transfers the two-byte
ADC output value to the register file and then returns system bus control back to the
eZ8 CPU.
4. If the current ADC analog input is the highest-numbered input to be converted:
– The DMA_ADC resets the ADC analog input number to 0 and initiates data conversion on ADC analog input 0
– If configured to generate an interrupt, the DMA_ADC sends an interrupt request
to the Interrupt Controller
If the current ADC analog input is not the highest-numbered input to be converted,
then the DMA_ADC initiates data conversion in the next higher-numbered ADC
analog input.
Configuring DMA_ADC for Data Transfer
Observe the following procedure to configure and enable the DMA_ADC:
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1. Write the DMA_ADC Address Register with the 7 most significant bits of the register
file address for data transfers.
2. Write to the DMA_ADC Control Register to complete the following operations:
– Enable the DMA_ADC interrupt request, if appropriate
– Select the number of ADC analog inputs to convert
– Enable the DMA_ADC channel
Caution: When using the DMA_ADC to perform conversions on multiple ADC inputs, the Analog-to-Digital Converter must be configured for SINGLE-SHOT Mode. If the ADC_IN
field in the DMA_ADC Control Register is greater than 000b, the ADC must be in SINGLE-SHOT Mode.
Continuous Mode operation of the ADC can only be used in conjunction with the
DMA_ADC if the ADC_IN field in the DMA_ADC Control Register is reset to 000b to
enable conversion on ADC analog input 0 only.
DMA Control Register Definitions
This section defines the features of the following DMA Control registers.
DMAx Control Register: see page 152
DMAx I/O Address Register: see page 154
DMAx Address High Nibble Register: see page 155
DMAx Start/Current Address Low Byte Register: see page 156
DMAx End Address Low Byte Register: see page 156
DMA_ADC Address Register: see page 157
DMA_ADC Control Register: see page 158
DMA_ADC Status Register: see page 159
DMAx Control Register
The DMAx Control Register, shown in Table 78, enables and selects the mode of operation for DMAx.
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Table 78. DMAx Control Register (DMAxCTL)
Bit
Field
7
6
5
4
3
DEN
DLE
DDIR
IRQEN
WSEL
RESET
2
1
0
RSS
0
R/W
R/W
Address
FB0h, FB8h
Bit
Description
[7]
DEN
DMAx Enable
0 = DMAx is disabled and data transfer requests are disregarded.
1 = DMAx is enabled and initiates a data transfer upon receipt of a request from the trigger
source.
[6]
DLE
DMAx Loop Enable
0 = DMAx reloads the original Start Address and is then disabled after the End Address data is
transferred.
1 = DMAx, after the End Address data is transferred, reloads the original Start Address and
continues operating.
[5]
DDIR
DMAx Data Transfer Direction
0 = Register file → on-chip peripheral control register.
1 = On-chip peripheral control → register file.
[4]
IRQEN
DMAx Interrupt Enable
0 = DMAx does not generate any interrupts.
1 = DMAx generates an interrupt when the End Address data is transferred.
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Bit
Description (Continued)
[3]
WSEL
Word Select
0 = DMAx transfers a single byte per request.
1 = DMAx transfers a two-byte word per request. The address for the on-chip peripheral control register must be an even address.
[2:0]
RSS
Request Trigger Source Select
The Request Trigger Source Select field determines the peripheral that can initiate a DMA
transfer. The corresponding interrupts do not need to be enabled within the Interrupt Controller
to initiate a DMA transfer. However, if the Request Trigger Source can enable or disable the
interrupt request sent to the Interrupt Controller, the interrupt request must be enabled within
the Request Trigger Source block.
000 = Timer 0.
001 = Timer 1.
010 = Timer 2.
011 = Timer 3.
100 = DMA0 Control Register: UART0 Received Data Register contains valid data. DMA1
Control Register: UART0 Transmit Data Register empty.
101 = DMA0 Control Register: UART1 Received Data Register contains valid data. DMA1
Control Register: UART1 Transmit Data Register empty.
110 = DMA0 Control Register: I2C Receiver Interrupt. DMA1 Control Register: I2C Transmitter
Interrupt Register empty.
111 = Reserved.
DMAx I/O Address Register
The DMAx I/O Address Register, shown in Table 79, contains the low byte of the on-chip
peripheral address for data transfer. The full 12-bit register file address is provided by {Fh,
DMAx_IO[7:0]}. When the DMA is configured for two-byte word transfers, the DMAx I/
O Address Register must contain an even-numbered address.
Table 79. DMAx I/O Address Register (DMAxIO)
Bit
7
Field
5
4
3
2
1
0
DMA_IO
RESET
X
R/W
R/W
Address
Bit
6
FB1h, FB9h
Description
[7:0]
DMA On-Chip Peripheral Control Register Address
DMA_IO This byte sets the low byte of the on-chip peripheral control register address on register file
page Fh (addresses F00h to FFFh).
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DMAx Address High Nibble Register
The DMAx Address High Register, shown in Table 80, specifies the upper four bits of
address for the Start/Current and End addresses of DMAx.
Table 80. DMAx Address High Nibble Register (DMAxH)
Bit
7
Field
6
5
4
3
DMA_END_H
RESET
2
1
0
DMA_START_H
X
R/W
R/W
Address
FB2h, FBAh
Bit
Description
[7:4]
DMA_END_H
DMAx End Address High Nibble
These bits, used with the DMAx End Address Low Register, form a 12-bit End Address.
The full 12-bit address is provided by {DMA_END_H[3:0], DMA_END[7:0]}.
[3:0]
DMAx Start/Current Address High Nibble
DMA_START_H These bits, used with the DMAx Start/Current Address Low Register, form a 12-bit Start/
Current Address. The full 12-bit address is provided by {DMA_START_H[3:0],
DMA_START[7:0]}.
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DMAx Start/Current Address Low Byte Register
The DMAx Start/Current Address Low Byte Register, shown in Table 81, in conjunction
with the DMAx Address High Nibble Register, shown in Table 80, forms a 12-bit Start/
Current Address. Writes to this register set the Start Address for DMA operations. Each
time the DMA completes a data transfer, the 12-bit Start/Current Address increments by
either 1 (single-byte transfer) or 2 (two-byte word transfer). Reads from this register return
the low byte of the current address to be used for the next DMA data transfer.
Table 81. DMAx Start/Current Address Low Byte Register (DMAxSTART)
Bit
7
6
5
Field
4
3
2
1
0
DMA_START
RESET
X
R/W
R/W
Address
FB3h, FBBh
Bit
Description
[7:0]
DMA_START
DMAx Start/Current Address Low
These bits, with the four lower bits of the DMAx_H Register, form the 12-bit Start/Current
address. The full 12-bit address is provided by {DMA_START_H[3:0], DMA_START[7:0]}.
DMAx End Address Low Byte Register
The DMAx End Address Low Byte Register, shown in Table 82, forms a 12-bit End
Address.
Table 82. DMAx End Address Low Byte Register (DMAxEND)
Bit
7
Field
6
5
4
3
2
1
0
DMA_END
RESET
X
R/W
R/W
Address
FB4h, FBCh
Bit
Description
[7]
DMA_END
DMAx End Address Low
These bits, with the four upper bits of the DMAx_H Register, form a 12-bit address. This
address is the ending location of the DMAx transfer. The full 12-bit address is provided by
{DMA_END_H[3:0], DMA_END[7:0]}.
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DMA_ADC Address Register
The DMA_ADC Address Register, shown in Table 84, points to a block of the register file
to store the ADC conversion values displayed in Table 83. This register contains the seven
most significant bits of the 12-bit register file addresses. The five least significant bits are
calculated from the ADC analog input number (5-bit base address is equal to twice the
ADC analog input number). The 10-bit ADC conversion data is stored as two bytes with
the most significant byte of the ADC data stored at the even-numbered register file
address.
Table 83 provides an example of the register file addresses if the DMA_ADC Address
Register contains the value 72h.
Table 83. DMA_ADC Register File Address Example
ADC Analog Input
Register File Address
(Hex)*
0
720h–721h
1
722h–723h
2
724h–725h
3
726h–727h
4
728h–729h
5
72Ah–72Bh
6
72Ch–72Dh
7
72Eh–72Fh
8
730h–731h
9
732h–733h
10
734h–735h
11
736h–737h
Note: *DMAA_ADDR is set to 72h.
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Table 84. DMA_ADC Address Register (DMAA_ADDR)
Bit
7
6
5
Field
4
3
2
1
DMAA_ADDR
RESET
0
Reserved
X
R/W
R/W
Address
FBDh
Bit
Description
[7:1]
DMA_ADC Address
DMAA_ADDR These bits specify the seven most significant bits of the 12-bit register file addresses
used for storing the ADC output data. The ADC analog input Number defines the five
least significant bits of the register file address. Full 12-bit address is {DMAA_ADDR[7:1],
4-bit ADC analog input Number, 0}.
0
Reserved
This bit is reserved and must be programmed to 0.
DMA_ADC Control Register
The DMA_ADC Control Register, shown in Table 85, enables and sets options (DMA
enable and interrupt enable) for ADC operation.
Table 85. DMA_ADC Control Register (DMAACTL)
Bit
Field
7
6
DAEN
IRQEN
RESET
5
4
3
Reserved
2
1
0
ADC_IN
0
R/W
R/W
Address
FBEh
Bit
Description
[7]
DAEN
DMA_ADC Enable
0 = DMA_ADC is disabled and the ADC analog input Number (ADC_IN) is reset to 0.
1 = DMA_ADC is enabled.
[6]
IRQEN
Interrupt Enable
0 = DMA_ADC does not generate any interrupts.
1 = DMA_ADC generates an interrupt after transferring data from the last ADC analog input
specified by the ADC_IN field.
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Bit
Description (Continued)
[5:4]
Reserved
These bits are reserved and must be programmed to 00.
[3:0]
ADC_IN
ADC Analog Input Number
These bits set the number of ADC analog inputs to be used in the continuous update (data
conversion followed by DMA data transfer). The conversion always begins with ADC analog
input 0 and then progresses sequentially through the other selected ADC analog inputs.
0000 = ADC analog input 0 updated.
0001 = ADC analog inputs 0–1 updated.
0010 = ADC analog inputs 0–2 updated.
0011 = ADC analog inputs 0–3 updated.
0100 = ADC analog inputs 0–4 updated.
0101 = ADC analog inputs 0–5 updated.
0110 = ADC analog inputs 0–6 updated.
0111 = ADC analog inputs 0–7 updated.
1000 = ADC analog inputs 0–8 updated.
1001 = ADC analog inputs 0–9 updated.
1010 = ADC analog inputs 0–10 updated.
1011 = ADC analog inputs 0–11 updated.
1100–1111 = Reserved.
DMA_ADC Status Register
The DMA Status Register, shown in Table 86, indicates the DMA channel that generated
the interrupt and the ADC analog input that is currently undergoing conversion. Reads
from this register reset the Interrupt Request Indicator bits (IRQA, IRQ1, and IRQ0) to 0.
Therefore, software interrupt service routines that read this register must process all three
interrupt sources from the DMA.
Table 86. DMA_ADC Status Register (DMAA_STAT)
Bit
7
Field
6
5
4
CADC[3:0]
RESET
0
R/W
R
Address
3
2
1
0
Reserved
IRQA
IRQ1
IRQ0
FBFh
Bit
Description
[7:4]
CADC[3:0]
Current ADC Analog Input
This field identifies the Analog Input that the ADC is currently converting.
[3]
Reserved
This bit is reserved and must be programmed to 0.
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Bit
Description (Continued)
[2]
IRQA
DMA_ADC Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
0 = DMA_ADC is not the source of the interrupt from the DMA Controller.
1 = DMA_ADC completed transfer of data from the last ADC analog input and generated an
interrupt.
[1]
IRQ1
DMA1 Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
0 = DMA1 is not the source of the interrupt from the DMA Controller.
1 = DMA1 completed transfer of data to/from the End Address and generated an interrupt.
[0]
IRQ0
DMA0 Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
0 = DMA0 is not the source of the interrupt from the DMA Controller.
1 = DMA0 completed transfer of data to/from the End Address and generated an interrupt.
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Analog-to-Digital Converter
The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary
number. The features of the sigma-delta ADC include:
•
•
•
•
12 analog input sources are multiplexed with general-purpose I/O ports
Interrupt upon completion of conversion
Internal voltage reference generator
A Direct Memory Access (DMA) controller that can automatically initiate data conversion and transfer the data from 1 to 12 analog inputs
Architecture
Figure 34 displays the three major functional blocks (converter, analog multiplexer, and
voltage reference generator) of the ADC. The ADC converts an analog input signal to its
digital representation. The 12-input analog multiplexer selects one of the 12 analog input
sources. The ADC requires an input reference voltage for the conversion. The voltage reference for the conversion may be input through the external VREF pin or generated internally by the voltage reference generator.
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VREF
Internal Voltage
Reference Generator
Analog Input
Multiplexer
ANA0
ANA1
ANA2
Analog-to-Digital
Converter
ANA3
ANA4
ANA5
Reference Input
ANA6
ANA7
ANA8
Analog Input
ANA9
ANA10
ANA11
ANAIN[3:0]
Figure 34. Analog-to-Digital Converter Block Diagram
The sigma-delta ADC architecture provides alias and image attenuation below the amplitude resolution of the ADC in the frequency range of DC to one-half the ADC clock rate
(one-fourth the system clock rate). The ADC provides alias free conversion for frequencies up to one-half the ADC clock rate. Therefore, the sigma-delta ADC exhibits high
noise immunity, which makes it ideal for embedded applications. In addition, monotonicity (no missing codes) is guaranteed by design.
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Operation
This section describes the operational aspects of the ADC’s power-down and conversion
features.
Automatic Power-Down
If the ADC is idle (i.e., no conversions are in progress) for 160 consecutive system clock
cycles, portions of the ADC are automatically powered down. From this powered-down
state, the ADC requires 40 system clock cycles to power up. The ADC powers up when a
conversion is requested using the ADC Control Register.
Single-Shot Conversion
When configured for single-shot conversion, the ADC performs a single analog-to-digital
conversion on the selected analog input channel. After completion of the conversion, the
ADC shuts down. Observe the following procedure for setting up the ADC and initiating a
single-shot conversion:
1. Enable the appropriate analog inputs by configuring the general-purpose I/O pins for
alternate function. This configuration disables the digital input and output drivers.
2. Write to the ADC Control Register to configure the ADC and begin the conversion.
The bit fields in the ADC Control Register can be written simultaneously:
– Write to the ANAIN[3:0] field to select one of the 12 analog input sources
– Clear CONT to 0 to select a single-shot conversion
– Write to the VREF bit to enable or disable the internal voltage reference generator
– Set CEN to 1 to start the conversion
3. CEN remains 1 while the conversion is in progress. A single-shot conversion requires
5129 system clock cycles to complete. If a single-shot conversion is requested from an
ADC powered-down state, the ADC uses 40 additional clock cycles to power up
before beginning the 5129 cycle conversion.
4. When the conversion is complete, the ADC control logic performs the following operations:
– 10-bit data result written to {ADCD_H[7:0], ADCD_L[7:6]}
– CEN resets to 0 to indicate the conversion is complete
– An interrupt request is sent to the Interrupt Controller
5. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
powered down.
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Continuous Conversion
When configured for continuous conversion, the ADC continuously performs an analogto-digital conversion on the selected analog input. Each new data value over-writes the
previous value stored in the ADC Data registers. An interrupt is generated after each conversion.
Caution: In Continuous Mode, you must be aware that ADC updates are limited by the input signal
bandwidth of the ADC and the latency of the ADC and its digital filter. Step changes at
the input are not seen at the next output from the ADC. The response of the ADC (in all
modes) is limited by the input signal bandwidth and the latency.
Observe the following procedure for setting up the ADC and initiating continuous conversion:
1. Enable the appropriate analog input by configuring the general-purpose I/O pins for
alternate function. This disables the digital input and output driver.
2. Write to the ADC Control Register to configure the ADC for continuous conversion.
The bit fields in the ADC Control Register may be written simultaneously:
– Write to the ANAIN[3:0] field to select one of the 12 analog input sources
– Set CONT to 1 to select continuous conversion
– Write to the VREF bit to enable or disable the internal voltage reference generator
– Set CEN to 1 to start the conversions
3. When the first conversion in continuous operation is complete (after 5129 system
clock cycles, plus the 40 cycles required to power up, if necessary), the ADC control
logic performs the following operations:
– CEN resets to 0 to indicate the first conversion is complete. CEN remains 0 for all
subsequent conversions in continuous operation
– An interrupt request is sent to the Interrupt Controller to indicate the conversion is
complete
4. Thereafter, the ADC writes a new 10-bit data result to {ADCD_H[7:0],
ADCD_L[7:6]} every 256 system clock cycles. An interrupt request is sent to the
Interrupt Controller when each conversion is complete.
5. To disable continuous conversion, clear the CONT bit in the ADC Control Register to
0.
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DMA Control of the ADC
The Direct Memory Access (DMA) Controller can control operation of the ADC including analog input selection and conversion enable. For more information about the DMA
and configuring for ADC operations, see the Direct Memory Access Controller chapter on
page 150.
ADC Control Register Definitions
This section defines the features of the following ADC Control registers.
ADC Control Register: see page 165
ADC Data High Byte Register: see page 167
ADC Data Low Bits Register: see page 168
ADC Control Register
The ADC Control Register selects the analog input channel and initiates the analog-to-digital conversion.
Table 87. ADC Control Register (ADCCTL)
Bit
Field
7
6
5
4
CEN
Reserved
VREF
CONT
RESET
0
3
2
1
0
ANAIN[3:0]
1
0
R/W
R/W
Address
F70h
Bit
Description
[7]
CEN
Conversion Enable
0 = Conversion is complete. Writing a 0 produces no effect. The ADC automatically clears
this bit to 0 when a conversion has been completed.
1 = Begin conversion. Writing a 1 to this bit starts a conversion. If a conversion is already in
progress, the conversion restarts. This bit remains 1 until the conversion is complete.
[6]
Reserved
This bit is reserved and must be programmed to 0.
[5]
VREF
Voltage Reference
0 = Internal voltage reference generator enabled. The VREF pin should be left unconnected
(or capacitively coupled to analog ground) if the internal voltage reference is selected as
the ADC reference voltage.
1 = Internal voltage reference generator disabled. An external voltage reference must be
provided through the VREF pin.
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Bit
Description (Continued)
[4]
CONT
Conversion
0 = Single-shot conversion. ADC data is output once at completion of the 5129 system clock
cycles.
1 = Continuous conversion. ADC data updated every 256 system clock cycles.
[3:0]
ANAIN[3:0]
Analog Input Select
These bits select the analog input for conversion. For information about the Port pins available with each package style, see the Signal and Pin Descriptions chapter on page 7. Do
not enable unavailable analog inputs.
0000 = ANA0.
0001 = ANA1.
0010 = ANA2.
0011 = ANA3.
0100 = ANA4.
0101 = ANA5.
0110 = ANA6.
0111 = ANA7.
1000 = ANA8.
1001 = ANA9.
1010 = ANA10.
1011 = ANA11.
11xx = Reserved.
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ADC Data High Byte Register
The ADC Data High Byte Register, shown in Table 88, contains the upper eight bits of the
10-bit ADC output. During a single-shot conversion, this value is invalid. Access to the
ADC Data High Byte Register is read-only. The full 10-bit ADC result is provided by
{ADCD_H[7:0], ADCD_L[7:6]}. Reading the ADC Data High Byte Register latches data
in the ADC Low Bits Register.
Table 88. ADC Data High Byte Register (ADCD_H)
Bit
7
Field
6
5
4
3
1
0
ADCD_H
RESET
X
R/W
R
Address
Bit
2
F72h
Description
[7:0]
ADC Data High Byte
ADCD_H This byte contains the upper eight bits of the 10-bit ADC output. These bits are not valid during
a single-shot conversion. During a continuous conversion, the last conversion output is held in
this register. These bits are undefined after a Reset.
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ADC Data Low Bits Register
The ADC Data Low Bits Register, Table 89, contains the lower two bits of the conversion
value. The data in the ADC Data Low Bits Register is latched each time the ADC Data
High Byte Register is read. Reading this register always returns the lower two bits of the
conversion last read into the ADC High Byte Register. Access to the ADC Data Low Bits
Register is read-only. The full 10-bit ADC result is provided by {ADCD_H[7:0],
ADCD_L[7:6]}.
Table 89. ADC Data Low Bits Register (ADCD_L)
Bit
7
Field
6
5
4
3
ADCD_L
X
R/W
R
Bit
1
0
Reserved
RESET
Address
2
F73h
Description
[7:6]
ADC Data Low Bits
ADCD_L These are the least significant two bits of the 10-bit ADC output. These bits are undefined after
a Reset.
[5:0]
Reserved
These bits are reserved and are always undefined.
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Flash Memory
The products in the Z8 Encore! XP F64xx Series feature up to 64 KB (65,536 bytes) of
non-volatile Flash memory with read/write/erase capability. The Flash memory can be
programmed and erased in-circuit by either user code or through the On-Chip Debugger.
The Flash memory array is arranged in 512 byte per page. The 512 byte page is the minimum Flash block size that can be erased. The Flash memory is also divided into 8 sectors
which can be protected from programming and erase operations on a per sector basis.
Table 90 describes the Flash memory configuration for each device in the Z8 Encore! XP
F64xx Series. Table 91 lists the sector address ranges. Figure 35 displays the Flash memory arrangement.
Table 90. Flash Memory Configurations
Part
Number
Flash Size
Number of
Pages
Flash Memory
Addresses
Sector Size
Number of
Sectors
Pages per
Sector
Z8F162x
16K (16,384)
32
0000h–3FFFh
2K (2048)
8
4
Z8F242x
24K (24,576)
48
0000h–5FFFh
4K (4096)
6
8
Z8F322x
32K (32,768)
64
0000h–7FFFh
4K (4096)
8
8
Z8F482x
48K (49,152)
96
0000h–BFFFh
8K (8192)
6
16
Z8F642x
64K (65,536)
128
0000h–FFFFh
8K (8192)
8
16
Table 91. Flash Memory Sector Addresses
Flash Sector Address Ranges
Sector
Number
Z8F162x
Z8F242x
Z8F322x
Z8F482x
Z8F642x
0
0000h–07FFh
0000h–0FFFh
0000h–0FFFh
0000h–1FFFh
0000h–1FFFh
1
0800h–0FFFh
1000h–1FFFh
1000h–1FFFh
2000h–3FFFh
2000h–3FFFh
2
1000h–17FFh
2000h–2FFFh
2000h–2FFFh
4000h–5FFFh
4000h–5FFFh
3
1800h–1FFFh
3000h–3FFFh
3000h–3FFFh
6000h–7FFFh
6000h–7FFFh
4
2000h–27FFh
4000h–4FFFh
4000h–4FFFh
8000h–9FFFh
8000h–9FFFh
5
2800h–2FFFh
5000h–5FFFh
5000h–5FFFh
A000h–BFFFh
A000h–BFFFh
6
3000h–37FFh
N/A
6000h–6FFFh
N/A
C000h–DFFFh
7
3800h–3FFFh
N/A
7000h–7FFFh
N/A
E000h–FFFFh
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64KB Flash
Program Memory
Addresses
FFFFh
FE00h
FDFFh
FC00h
FBFFh
FA00h
128 Pages
512 Bytes per Page
05FFh
0400h
03FFh
0200h
01FFh
0000h
Figure 35. Flash Memory Arrangement
Information Area
Table 92 describes the Z8 Encore! XP F64xx Series Information Area. This 512-byte
Information Area is accessed by setting bit 7 of the Page Select Register to 1. When access
is enabled, the Information Area is mapped into Flash memory and overlays the 512 bytes
at addresses FE00h to FFFFh. When the Information Area access is enabled, LDC instructions return data from the Information Area. CPU instruction fetches always comes from
Flash memory regardless of the Information Area access bit. Access to the Information
Area is read-only.
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Table 92. Z8 Encore! XP F64xx Series Information Area Map
Flash Memory
Address (Hex)
Function
FE00h–FE3Fh
Reserved
FE40h–FE53h
Part Number
20-character ASCII alphanumeric code
Left-justified and filled with zeros
FE54h–FFFFh
Reserved
Operation
The Flash Controller provides the proper signals and timing for the Byte Programming,
Page Erase, and Mass Erase operations within Flash memory. The Flash Controller contains a protection mechanism, via the Flash Control Register (FCTL), to prevent accidental programming or erasure. The following subsections provide details about the Lock,
Unlock, Sector Protect, Byte Programming, Page Erase and Mass Erase operations.
Timing Using the Flash Frequency Registers
Before performing a program or erase operation in Flash memory, you must first configure
the Flash Frequency High and Low Byte registers. The Flash Frequency registers allow
programming and erasure of the Flash with system clock frequencies ranging from 20 kHz
through 20 MHz (the valid range is limited to the device operating frequencies).
The Flash Frequency High and Low Byte registers combine to form a 16-bit value,
FFREQ, to control timing for Flash program and erase operations. The 16-bit Flash Frequency value must contain the system clock frequency in kHz. This value is calculated
using the following equation:.
System Clock Frequency (Hz)
FFREQ[15:0] = -----------------------------------------------------------------------1000
Caution: Flash programming and erasure are not supported for system clock frequencies below
20 kHz, above 20 MHz, or outside of the devices’ operating frequency range. The Flash
Frequency High and Low Byte registers must be loaded with the correct value to ensure
proper Flash programming and erase operations.
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Flash Read Protection
The user code contained within Flash memory can be protected from external access. Programming the Flash Read Protect option bit prevents reading of user code by the On-Chip
Debugger or by using the Flash Controller Bypass Mode. For more information, see the
Option Bits chapter on page 180 and the On-Chip Debugger chapter on page 183.
Flash Write/Erase Protection
The Z8 Encore! XP F64xx Series provides several levels of protection against accidental
program and erasure of the Flash memory contents. This protection is provided by the
Flash Controller unlock mechanism, the Flash Sector Protect Register, and the Flash Write
Protect option bit.
Flash Controller Unlock Mechanism
At Reset, the Flash Controller locks to prevent accidental program or erasure of Flash
memory. To program or erase Flash memory, the Flash Controller must be unlocked. After
unlocking the Flash Controller, the Flash can be programmed or erased. Any value written
by user code to the Flash Control Register or Page Select Register out of sequence will
lock the Flash Controller.
Observe the following procedure to unlock the Flash Controller from user code:
1. Write 00h to the Flash Control Register to reset the Flash Controller.
2. Write the page to be programmed or erased to the Page Select Register.
3. Write the first unlock command 73h to the Flash Control Register.
4. Write the second unlock command 8Ch to the Flash Control Register.
5. Rewrite the page written in Step 2 to the Page Select Register.
Flash Sector Protection
The Flash Sector Protect Register can be configured to prevent sectors from being programmed or erased. After a sector is protected, it cannot be unprotected by user code. The
Flash Sector Protect Register is cleared after reset and any previously written protection
values is lost. User code must write this register in their initialization routine if they want
to enable sector protection.
The Flash Sector Protect Register shares its register file address with the Page Select Register. The Flash Sector Protect Register is accessed by writing the Flash Control Register
with 5Eh. After the Flash Sector Protect Register is selected, it can be accessed at the Page
Select Register address. When user code writes the Flash Sector Protect Register, bits can
only be set to 1. Thus, sectors can be protected, but not unprotected, via register write
operations. Writing a value other than 5Eh to the Flash Control Register deselects the
Flash Sector Protect Register and reenables access to the Page Select Register.
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Observe the following procedure to setup the Flash Sector Protect Register from user
code:
1. Write 00h to the Flash Control Register to reset the Flash Controller.
2. Write 5Eh to the Flash Control Register to select the Flash Sector Protect Register.
3. Read and/or write the Flash Sector Protect Register which is now at register file
address FF9h.
4. Write 00h to the Flash Control Register to return the Flash Controller to its reset state.
Flash Write Protection Option Bit
The Flash Write Protect option bit can be enabled to block all program and erase operations from user code. For more information, see the Option Bits chapter on page 180.
Byte Programming
When the Flash Controller is unlocked, writes to Flash memory from user code will program a byte into the Flash if the address is located in the unlocked page. An erased Flash
byte contains all ones (FFh). The programming operation can only be used to change bits
from one to zero. To change a Flash bit (or multiple bits) from zero to one requires a Page
Erase or Mass Erase operation.
Byte programming can be accomplished using the eZ8 CPU’s LDC or LDCI instructions.
For a description of the LDC and LDCI instructions, refer to the eZ8 CPU Core User Manual (UM0128), which is available for download on www.zilog.com.
While the Flash Controller programs Flash memory, the eZ8 CPU idles but the system
clock and on-chip peripherals continue to operate. Interrupts that occur when a programming operation is in progress are serviced after the programming operation is complete. To
exit programming mode and lock the Flash Controller, write 00h to the Flash Control
Register.
User code cannot program Flash memory on a page that resides in a protected sector.
When user code writes memory locations, only addresses located in the unlocked page are
programmed. Memory writes outside of the unlocked page are ignored.
Caution: Each memory location must not be programmed more than twice before an erase occurs.
Observe the following procedure to program the Flash from user code:
1. Write 00h to the Flash Control Register to reset the Flash Controller.
2. Write the page of memory to be programmed to the Page Select Register.
3. Write the first unlock command 73h to the Flash Control Register.
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4. Write the second unlock command 8Ch to the Flash Control Register.
5. Rewrite the page written in Step 2 to the Page Select Register.
6. Write Flash memory using LDC or LDCI instructions to program the Flash.
7. Repeat Step 6 to program additional memory locations on the same page.
8. Write 00h to the Flash Control Register to lock the Flash Controller.
Page Erase
Flash memory can be erased one page (512 bytes) at a time. Page-erasing Flash memory
sets all bytes in a page to the value FFh. The Page Select Register identifies the page to be
erased. While the Flash Controller executes the Page Erase operation, the eZ8 CPU idles;
however, the system clock and on-chip peripherals continue to operate. The eZ8 CPU
resumes operation after the Page Erase operation completes. Interrupts that occur when
the Page Erase operation is in progress are serviced after the Page Erase operation is complete. When the Page Erase operation is complete, the Flash Controller returns to its
locked state. Only pages located in unprotected sectors can be erased.
Observe the following procedure to perform a Page Erase operation:
1. Write 00h to the Flash Control Register to reset the Flash Controller.
2. Write the page to be erased to the Page Select Register.
3. Write the first unlock command 73h to the Flash Control Register.
4. Write the second unlock command 8Ch to the Flash Control Register.
5. Rewrite the page written in Step 2 to the Page Select Register.
6. Write the Page Erase command 95h to the Flash Control Register.
Mass Erase
The Flash memory cannot be mass-erased by user code.
Flash Controller Bypass
The Flash Controller can be bypassed and the control signals for Flash memory can be
brought out to the GPIO pins. Bypassing the Flash Controller allows faster programming
algorithms by controlling the Flash programming signals directly.
Flash Controller Bypass is recommended for gang programming applications and large
volume customers who do not require in-circuit programming of Flash memory.
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For more information about bypassing the Flash Controller, refer to the Third Party Flash
Programming Support for Z8 Encore! MCUs Application Note (AN0117), which is available for download at www.zilog.com.
Flash Controller Behavior in Debug Mode
The following changes in Flash Controller behavior occur when the Flash Controller is
accessed using the On-Chip Debugger:
•
•
•
•
•
The Flash Write Protect option bit is ignored
•
•
The Page Select Register can be written when the Flash Controller is unlocked
The Flash Sector Protect Register is ignored for programming and erase operations
Programming operations are not limited to the page selected in the Page Select Register
Bits in the Flash Sector Protect Register can be written to one or zero
The second write of the Page Select Register to unlock the Flash Controller is not necessary
The Mass Erase command is enabled through the Flash Control Register
Caution: For security reasons, the Flash Controller allows only a single page to be opened for
write/erase operations. When writing multiple Flash pages, the Flash Controller must go
through the unlock sequence again to select another page.
Flash Control Register Definitions
This section defines the features of the following Flash Control registers.
Flash Control Register: see page 175
Flash Status Register: see page 177
Page Select Register: see page 177
Flash Sector Protect Register: see page 178
Flash Frequency High and Low Byte Registers: see page 179
Flash Control Register
The Flash Control Register, shown in Table 93, unlocks the Flash Controller for programming and erase operations, or to select the Flash Sector Protect Register.
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The write-only Flash Control Register shares its register file address with the read-only
Flash Status Register.
Table 93. Flash Control Register (FCTL)
Bit
7
6
5
4
Field
3
2
1
0
FCMD
RESET
0
R/W
W
Address
FF8h
Bit
Description
[7:0]
FCMD
Flash Command*
73h = First unlock command.
8Ch = Second unlock command.
95h = Page erase command.
63h = Mass erase command
5Eh = Flash Sector Protect Register select.
Note: *All other commands, or any command out of sequence, lock the Flash Controller.
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Flash Status Register
The Flash Status Register, shown in Table 94, indicates the current state of the Flash Controller. This register can be read at any time. The read-only Flash Status Register shares its
register file address with the write-only Flash Control Register.
Table 94. Flash Status Register (FSTAT)
Bit
7
Field
6
5
4
3
Reserved
1
0
FSTAT
RESET
0
R/W
R
Address
2
FF8h
Bit
Description
[7:6]
Reserved
These bits are reserved and must be programmed to 00.
[5:0]
FSTAT
Flash Controller Status
00_0000 = Flash Controller locked.
00_0001 = First unlock command received.
00_0010 = Second unlock command received.
00_0011 = Flash Controller unlocked.
00_0100 = Flash Sector Protect Register selected.
00_1xxx = Program operation in progress.
01_0xxx = Page erase operation in progress.
10_0xxx = Mass erase operation in progress.
Page Select Register
The Page Select (FPS) Register, shown in Table 95, selects one of the 128 available Flash
memory pages to be erased or programmed. Each Flash page contains 512 bytes of Flash
memory. During a Page Erase operation, all Flash memory locations with the 7 most significant bits of the address provided by the PAGE field are erased to FFh.
The Page Select Register shares its register file address with the Flash Sector Protect Register. The Page Select Register cannot be accessed when the Flash Sector Protect Register
is enabled.
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Table 95. Page Select Register (FPS)
Bit
Field
7
6
5
4
3
INFO_EN
2
1
0
PAGE
RESET
0
R/W
R/W
Address
FF9h
Bit
Description
[7]
INFO_EN
Information Area Enable
0 = Information Area is not selected.
1 = Information Area is selected. The Information area is mapped into the Flash memory
address space at addresses FE00h through FFFFh.
[6:0]
PAGE
Page Select
This 7-bit field selects the Flash memory page for programming and Page Erase operations.
Flash Memory Address[15:9] = PAGE[6:0].
Flash Sector Protect Register
The Flash Sector Protect Register, shown in Table 96, protects Flash memory sectors from
being programmed or erased from user code. The Flash Sector Protect Register shares its
register file address with the Page Select Register. The Flash Sector Protect Register can
be accessed only after writing the Flash Control Register with 5Eh.
User code can only write bits in this register to 1 (bits cannot be cleared to 0 by user code).
To determine the appropriate Flash memory sector address range and sector number for
your Z8F64xx Series product, please refer to Table 91 on page 169.
Table 96. Flash Sector Protect Register (FPROT)
Bit
Field
7
6
5
4
3
2
1
0
SECT7
SECT6
SECT5
SECT4
SECT3
SECT2
SECT1
SECT0
RESET
0
R/W
R/W*
Address
FF9h
Note: *R/W = This register is accessible for read operations; it can be written to 1 only via user code.
Bit
Description
[7:0]
SECTn
Sector Protect**
0 = Sector n can be programmed or erased from user code.
1 = Sector n is protected and cannot be programmed or erased from user code.
Note: **User code can only write bits from 0 to 1.
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Flash Frequency High and Low Byte Registers
The Flash Frequency High and Low Byte registers, shown in Tables 97 and 98, combine
to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations.
The 16-bit Flash Frequency registers must be written with the system clock frequency in
kHz for Program and Erase operations. Calculate the Flash Frequency value using the following equation:
System Clock Frequency
FFREQ[15:0] = FFREQH[7:0],FFREQL[7:0] = -----------------------------------------------------------1000
Caution: Flash programming and erasure is not supported for system clock frequencies below
20 kHz, above 20 MHz, or outside of the valid operating frequency range for the device.
The Flash Frequency High and Low Byte registers must be loaded with the correct value
to ensure proper program and erase times.
Table 97. Flash Frequency High Byte Register (FFREQH)
Bit
7
6
5
4
Field
3
2
1
0
1
0
FFREQH
RESET
0
R/W
R/W
Address
FFAh
Table 98. Flash Frequency Low Byte Register (FFREQL)
Bit
7
Field
6
5
4
3
FFREQL
RESET
0
R/W
R/W
Address
FFBh
Bit
2
Description
[7:0]
Flash Frequency High and Low Bytes
FFREQH, These 2 bytes, {FFREQH[7:0], FFREQL[7:0]}, contain the 16-bit Flash Frequency value.
FFREQL
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Option Bits
Option bits allow user configuration of certain aspects of the Z8 Encore! XP F64xx Series
operation. The feature configuration data is stored in the Flash memory and read during
Reset. The features available for control via the option bits are:
•
•
•
•
Watchdog Timer time-out response selection–interrupt or Reset
•
Voltage Brown-Out configuration is always enabled or disabled during Stop Mode to
reduce Stop Mode power consumption
•
Oscillator mode selection for high-, medium-, and low-power crystal oscillators or an
external RC oscillator
Watchdog Timer enabled at Reset
The ability to prevent unwanted read access to user code in Flash memory
The ability to prevent accidental programming and erasure of the user code in Flash
memory
Operation
This section describes the type and configuration of the programmable Flash option bits.
Option Bit Configuration By Reset
Each time the option bits are programmed or erased, the device must be Reset for the
change to take place. During any reset operation (System Reset, Reset, or Stop Mode
Recovery), the option bits are automatically read from the Flash memory and written to
Option Configuration registers. The Option Configuration registers control operation of
the devices within the Z8 Encore! XP F64xx Series. Option bit control is established
before the device exits Reset and the eZ8 CPU begins code execution. The Option Configuration registers are not part of the register file and are not accessible for read or write
access.
Option Bit Address Space
The first two bytes of Flash memory at addresses 0000h (see Table 99) and 0001h (see
Table 100) are reserved for the user option bits. The byte at Flash memory address 0000h
configures user options. The byte at Flash memory address 0001h is reserved for future
use and must remain unprogrammed.
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Flash Memory Address 0000h
Table 99. Flash Option Bits At Flash Memory Address 0000h
Bit
Field
7
6
WDT_RES WDT_AO
5
4
OSC_SEL[1:0]
RESET
3
2
1
0
VBO_AO
RP
Reserved
FWP
U
R/W
R/W
Address
Program Memory 0000h
Note: U = Unchanged by Reset; R/W = Read/Write.
Bit
Description
[7]
WDT_RES
Watchdog Timer Reset
0 = Watchdog Timer time-out generates an interrupt request. Interrupts must be globally
enabled for the eZ8 CPU to acknowledge the interrupt request.
1 = Watchdog Timer time-out causes a Short Reset. This setting is the default for unprogrammed (erased) Flash.
[6]
WDT_AO
Watchdog Timer Always On
0 = Watchdog Timer is automatically enabled upon application of system power. Watchdog Timer can not be disabled except during Stop Mode (if configured to power down
during Stop Mode).
1 = Watchdog Timer is enabled upon execution of the WDT instruction. Once enabled,
the Watchdog Timer can only be disabled by a Reset or Stop Mode Recovery. This
setting is the default for unprogrammed (erased) Flash.
[5:4]
Oscillator Mode Selection
OSC_SEL[1:0] 00 = On-chip oscillator configured for use with external RC networks (< 4 MHz).
01 = Minimum power for use with very low frequency crystals (32 kHz to 1.0 MHz).
10 = Medium power for use with medium frequency crystals or ceramic resonators
(0.5 MHz to 10.0 MHz).
11 = Maximum power for use with high frequency crystals (8.0 MHz to 20.0 MHz). This
setting is the default for unprogrammed (erased) Flash.
[3]
VBO_AO
Voltage Brown-Out Protection Always On
0 = Voltage Brown-Out Protection is disabled in Stop Mode to reduce total power consumption.
1 = Voltage Brown-Out Protection is always enabled including during Stop Mode. This
setting is the default for unprogrammed (erased) Flash.
[2]
RP
Read Protect
0 = User program code is inaccessible. Limited control features are available through the
On-Chip Debugger.
1 = User program code is accessible. All On-Chip Debugger commands are enabled.
This setting is the default for unprogrammed (erased) Flash.
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Bit
Description (Continued)
[1]
Reserved
This bit is reserved and must be programmed to 0.
[0]
FWP
Flash Write Protect (Flash version only)
0 = Programming, Page Erase, and Mass Erase through User Code is disabled. Mass
Erase is available through the On-Chip Debugger.
1 = Programming, and Page Erase are enabled for all of Flash program memory.
Flash Memory Address 0001h
Table 100. Options Bits at Flash Memory Address 0001h
Bit
7
6
5
4
Field
3
2
1
0
Reserved
RESET
U
R/W
R/W
Address
Program Memory 0001h
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
Description
[7:0]
Reserved
These option bits are reserved for future use and must always be 1. This setting is the default
for unprogrammed (erased) Flash.
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On-Chip Debugger
The Z8 Encore! XP F64xx Series products contain an integrated On-Chip Debugger
(OCD) that provides advanced debugging features including:
•
•
•
•
Reading and writing of the register file
Reading and writing of Program and Data memory
Setting of breakpoints
Execution of eZ8 CPU instructions
Architecture
The On-Chip Debugger consists of four primary functional blocks: transmitter, receiver,
autobaud generator, and debug controller. Figure 36 displays the architecture of the OnChip Debugger.
System
Clock
eZ8TM CPU
Control
Autobaud
Detector/Generator
Transmitter
Debug Controller
DBG
Pin
Receiver
Figure 36. On-Chip Debugger Block Diagram
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Operation
The following section describes the operation of the OCD.
OCD Interface
The On-Chip Debugger uses the DBG pin for communication with an external host. This
one-pin interface is a bidirectional open-drain interface that transmits and receives data.
Data transmission is half-duplex, meaning that transmit and receive operations cannot
occur simultaneously. The serial data on the DBG pin is sent using the standard asynchronous data format defined in RS-232. This pin can interface the Z8 Encore! XP F64xx
Series products to the serial port of a host PC using minimal external hardware.Two different methods for connecting the DBG pin to an RS-232 interface are depicted in Figures 37
and 38.
Caution: For proper operation of the On-Chip Debugger, all power pins (VDD and AVDD) must be
supplied with power, and all ground pins (VSS and AVSS) must be properly grounded.
The DBG pin is open-drain and must always be connected to VDD through an external
pull-up resistor to ensure proper operation.
VDD
RS-232
Transceiver
10kΩ
Diode
RS-232 TX
DBG Pin
RS-232 RX
Figure 37. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, #1 of 2
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VDD
RS-232
Transceiver
RS-232 TX
Open-Drain
Buffer
10kΩ
DBG Pin
RS-232 RX
Figure 38. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, #2 of 2
Debug Mode
The operating characteristics of the Z8 Encore! XP F64xx Series devices in Debug Mode
are:
•
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to execute specific instructions
•
•
•
•
The system clock operates unless in Stop Mode
All enabled on-chip peripherals operate unless in Stop Mode
Automatically exits Halt Mode
Constantly refreshes the Watchdog Timer, if enabled
Entering Debug Mode
The device enters Debug Mode following any of the following operations:
•
•
•
Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface
eZ8 CPU execution of a breakpoint (BRK) instruction (when enabled)
If the DBG pin is Low when the device exits Reset, the On-Chip Debugger automatically puts the device into Debug Mode
Exiting Debug Mode
The device exits Debug Mode following any of the following operations:
•
•
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Power-On Reset
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•
•
•
Voltage Brown-Out reset
Asserting the RESET pin Low to initiate a Reset
Driving the DBG pin Low while the device is in Stop Mode initiates a system reset
OCD Data Format
The OCD interface uses the asynchronous data format defined for RS-232. Each character
is transmitted as 1 start bit, 8 data bits (least significant bit first), and 1 stop bit, as shown
in Figure 39.
START
D0
D1
D2
D3
D4
D5
D6
D7
STOP
Figure 39. OCD Data Format
OCD Autobaud Detector/Generator
To run over a range of baud rates (bits per second) with various system clock frequencies,
the On-Chip Debugger has an Autobaud Detector/Generator. After a reset, the OCD is idle
until it receives data. The OCD requires that the first character sent from the host is the
character 80h. The character 80h has eight continuous bits Low (one start bit plus 7 data
bits). The Autobaud Detector measures this period and sets the OCD Baud Rate Generator
accordingly.
The Autobaud Detector/Generator is clocked by the system clock. The minimum baud rate
is the system clock frequency divided by 512. For optimal operation, the maximum recommended baud rate is the system clock frequency divided by 8. The theoretical maximum baud rate is the system clock frequency divided by 4. This theoretical maximum is
possible for low noise designs with clean signals. Table 101 lists minimum and recommended maximum baud rates for sample crystal frequencies.
Table 101. OCD Baud-Rate Limits
Recommended
Maximum Baud Rate
(kbits/s)
Minimum Baud Rate
(kbits/s)
20.0
2500
39.1
1.0
125.0
1.96
0.032768 (32 kHz)
4.096
0.064
System Clock
Frequency (MHz)
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If the OCD receives a serial break (nine or more continuous bits Low) the Autobaud
Detector/Generator resets. The Autobaud Detector/Generator can then be reconfigured by
sending 80h.
OCD Serial Errors
The On-Chip Debugger can detect any of the following error conditions on the DBG pin:
•
•
•
Serial break (a minimum of nine continuous bits Low)
Framing error (received stop bit is Low)
Transmit collision (OCD and host simultaneous transmission detected by the OCD)
When the OCD detects one of these errors, it aborts any command currently in progress,
transmits a serial break 4096 system clock cycles long back to the host, and resets the
Autobaud Detector/Generator. A framing error or transmit collision may be caused by the
host sending a serial break to the OCD. Because of the open-drain nature of the interface,
returning a serial break back to the host only extends the length of the serial break if the
host releases the serial break early.
The host transmits a serial break on the DBG pin when first connecting to the Z8 Encore!
XP F64xx Series devices or when recovering from an error. A serial break from the host
resets the Autobaud Generator/Detector but does not reset the OCD Control Register. A
serial break leaves the device in Debug Mode if that is the current mode. The OCD is held
in Reset until the end of the serial break when the DBG pin returns High. Because of the
open-drain nature of the DBG pin, the host can send a serial break to the OCD even if the
OCD is transmitting a character.
Breakpoints
Execution breakpoints are generated using the BRK instruction (op code 00h). When the
eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If breakpoints are
enabled, the OCD idles the eZ8 CPU and enters Debug Mode. If breakpoints are not
enabled, the OCD ignores the BRK signal and the BRK instruction operates as an NOP.
If breakpoints are enabled, the OCD can be configured to automatically enter Debug
Mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK
instruction, then the CPU is still enabled to service DMA and interrupt requests.
The loop on BRK instruction can be used to service interrupts in the background. For
interrupts to be serviced in the background, there cannot be any breakpoints in the interrupt service routine. Otherwise, the CPU stops on the breakpoint in the interrupt routine.
For interrupts to be serviced in the background, interrupts must also be enabled. Debugging software should not automatically enable interrupts when using this feature, since
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interrupts are typically disabled during critical sections of code where interrupts should
not occur (such as adjusting the stack pointer or modifying shared data).
Software can poll the IDLE bit of the OCDSTAT Register to determine if the OCD is looping on a BRK instruction. When software stops the CPU on the BRK instruction that it is
looping on, it should not set the DBGMODE bit of the OCDCTL Register. The CPU may
have vectored to and be in the middle of an interrupt service routine when this bit gets set.
Instead, software must clear the BRKLP bit. This action allows the CPU to finish the interrupt service routine it may be in and return the BRK instruction. When the CPU returns to
the BRK instruction it was previously looping on, it automatically sets the DBGMODE bit
and enters Debug Mode.
Software detects that the majority of the OCD commands are still disabled when the eZ8
CPU is looping on a BRK instruction. The eZ8 CPU must be stopped and the part must be
in Debug Mode before these commands can be issued.
Breakpoints in Flash Memory
The BRK instruction is op code 00h, which corresponds to the fully programmed state of
a byte in Flash memory. To implement a breakpoint, write 00h to the appropriate address,
overwriting the current instruction. To remove a breakpoint, the corresponding page of
Flash memory must be erased and reprogrammed with the original data.
On-Chip Debugger Commands
The host communicates to the On-Chip Debugger by sending OCD commands using the
DBG interface. During normal operation, only a subset of the OCD commands are available. In Debug Mode, all OCD commands become available unless the user code and control registers are protected by programming the Read Protect option bit (RP). The Read
Protect option bit prevents the code in memory from being read out of the Z8 Encore! XP
F64xx Series products. When this option is enabled, several of the OCD commands are
disabled.
Table 102 contains a summary of the On-Chip Debugger commands. Table 102 lists those
commands that operate when the device is not in Debug Mode (normal operation) and
those commands that are disabled by programming the Read Protect option bit.
Each OCD command is further described in the list that follows the table.
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Table 102. On-Chip Debugger Commands
Command
Byte
Enabled when
NOT in Debug
Mode?
Read OCD Revision
00h
Yes
—
Read OCD Status
Register
02h
Yes
—
Read Runtime Counter
03h
—
—
Write OCD Control
Register
04h
Yes
Cannot clear DBGMODE bit
Read OCD Control
Register
05h
Yes
—
Write Program Counter
06h
—
Disabled
Read Program Counter
07h
—
Disabled
Write Register
08h
—
Only writes of the Flash memory control
registers are allowed. Additionally, only the
Mass Erase command is allowed to be
written to the Flash Control Register.
Read Register
09h
—
Disabled
Write Program Memory
0Ah
—
Disabled
Read Program Memory
0Bh
—
Disabled
Write Data Memory
0Ch
—
Disabled
Read Data Memory
0Dh
—
Disabled
Read Program Memory
CRC
0Eh
—
—
Reserved
0Fh
—
—
Step Instruction
10h
—
Disabled
Stuff Instruction
11h
—
Disabled
Execute Instruction
12h
—
Disabled
13h–FFh
—
—
Debug Command
Reserved
Disabled by Read Protect Option Bit
In the following list of OCD commands, data and commands sent from the host to the OnChip Debugger are identified by DBG ← Command/Data. Data sent from the On-Chip
Debugger back to the host is identified by DBG → Data.
Read OCD Revision (00h). The Read OCD Revision command determines the version of
the On-Chip Debugger. If OCD commands are added, removed, or changed, this revision
number changes.
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DBG ← 00h
DBG OCDREV[15:8] (Major revision number)
DBG OCDREV[7:0] (Minor revision number)
Read OCD Status Register (02h). The Read OCD Status Register command reads the
OCDSTAT Register.
DBG ← 02h
DBG OCDSTAT[7:0]
Write OCD Control Register (04h). The Write OCD Control Register command writes
the data that follows to the OCDCTL Register. When the Read Protect option bit is
enabled, the DBGMODE bit (OCDCTL[7]) can only be set to 1, it cannot be cleared to 0
and the only method of putting the device back into normal operating mode is to reset the
device.
DBG ← 04h
DBG ← OCDCTL[7:0]
Read OCD Control Register (05h). The Read OCD Control Register command reads the
value of the OCDCTL Register.
DBG ← 05h
DBG OCDCTL[7:0]
Write Program Counter (06h). The Write Program Counter command writes the data that
follows to the eZ8 CPU’s program counter (PC). If the device is not in Debug Mode or if
the Read Protect option bit is enabled, the PC values are discarded.
DBG ← 06h
DBG ← ProgramCounter[15:8]
DBG ← ProgramCounter[7:0]
Read Program Counter (07h). The Read Program Counter command reads the value in
the eZ8 CPU’s program counter (PC). If the device is not in Debug Mode or if the Read
Protect option bit is enabled, this command returns FFFFh.
DBG ← 07h
DBG ProgramCounter[15:8]
DBG ProgramCounter[7:0]
Write Register (08h). The Write Register command writes data to the register file. Data
can be written 1-256 bytes at a time (256 bytes can be written by setting size to zero). If
the device is not in Debug Mode, the address and data values are discarded. If the Read
Protect option bit is enabled, then only writes to the Flash Control Registers are allowed
and all other register write data values are discarded.
DBG
DBG
DBG
DBG
DBG
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←
←
←
←
08h
{4’h0,Register Address[11:8]}
Register Address[7:0]
Size[7:0]
1-256 data bytes
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Read Register (09h). The Read Register command reads data from the register file. Data
can be read 1-256 bytes at a time (256 bytes can be read by setting size to zero). If the
device is not in Debug Mode or if the Read Protect option bit is enabled, this command
returns FFh for all the data values.
DBG
DBG
DBG
DBG
DBG
←
←
←
←
09h
{4’h0,Register Address[11:8]
Register Address[7:0]
Size[7:0]
1-256 data bytes
Write Program Memory (0Ah). The Write Program Memory command writes data to
program memory. This command is equivalent to the LDC and LDCI instructions. Data
can be written 1-65536 bytes at a time (65536 bytes can be written by setting size to zero).
The on-chip Flash Controller must be written to and unlocked for the programming operation to occur. If the Flash Controller is not unlocked, the data is discarded. If the device is
not in Debug Mode or if the Read Protect option bit is enabled, the data is discarded.
DBG
DBG
DBG
DBG
DBG
DBG
←
←
←
←
←
←
0Ah
Program Memory Address[15:8]
Program Memory Address[7:0]
Size[15:8]
Size[7:0]
1-65536 data bytes
Read Program Memory (0Bh). The Read Program Memory command reads data from
program memory. This command is equivalent to the LDC and LDCI instructions. Data
can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). If the
device is not in Debug Mode or if the Read Protect option bit is enabled, this command
returns FFh for the data.
DBG
DBG
DBG
DBG
DBG
DBG
←
←
←
←
←
0Bh
Program Memory Address[15:8]
Program Memory Address[7:0]
Size[15:8]
Size[7:0]
1-65536 data bytes
Write Data Memory (0Ch). The Write Data Memory command writes data to Data Mem-
ory. This command is equivalent to the LDE and LDEI instructions. Data can be written 165536 bytes at a time (65536 bytes can be written by setting size to zero). If the device is
not in Debug Mode or if the Read Protect option bit is enabled, the data is discarded.
DBG
DBG
DBG
DBG
DBG
DBG
←
←
←
←
←
←
0Ch
Data Memory Address[15:8]
Data Memory Address[7:0]
Size[15:8]
Size[7:0]
1-65536 data bytes
Read Data Memory (0Dh). The Read Data Memory command reads from Data Memory.
This command is equivalent to the LDE and LDEI instructions. Data can be read 1-65536
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bytes at a time (65536 bytes can be read by setting size to zero). If the device is not in
Debug Mode, this command returns FFh for the data.
DBG
DBG
DBG
DBG
DBG
DBG
←
←
←
←
←
0Dh
Data Memory Address[15:8]
Data Memory Address[7:0]
Size[15:8]
Size[7:0]
1-65536 data bytes
Read Program Memory CRC (0Eh). The Read Program Memory CRC command com-
putes and returns the CRC (cyclic redundancy check) of program memory using the 16-bit
CRC-CCITT polynomial. If the device is not in Debug Mode, this command returns
FFFFh for the CRC value. Unlike most other OCD Read commands, there is a delay from
issuing of the command until the OCD returns the data. The OCD reads program memory,
calculates the CRC value, and returns the result. The delay is a function of the program
memory size and is approximately equal to the system clock period multiplied by the number of bytes in program memory.
DBG ← 0Eh
DBG CRC[15:8]
DBG CRC[7:0]
Step Instruction (10h). The Step Instruction command steps one assembly instruction at
the current program counter (PC) location. If the device is not in Debug Mode or the Read
Protect option bit is enabled, the OCD ignores this command.
DBG ← 10h
Stuff Instruction (11h). The Stuff Instruction command steps one assembly instruction
and allows specification of the first byte of the instruction. The remaining 0-4 bytes of the
instruction are read from program memory. This command is useful for stepping over
instructions where the first byte of the instruction has been overwritten by a breakpoint. If
the device is not in Debug Mode or the Read Protect option bit is enabled, the OCD
ignores this command.
DBG ← 11h
DBG ← opcode[7:0]
Execute Instruction (12h). The Execute Instruction command allows sending an entire
instruction to be executed to the eZ8 CPU. This command can also step over breakpoints.
The number of bytes to send for the instruction depends on the op code. If the device is not
in Debug Mode or the Read Protect option bit is enabled, the OCD ignores this command
DBG ← 12h
DBG ← 1-5 byte opcode
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On-Chip Debugger Control Register Definitions
This section describes the features of the On-Chip Debugger Control and Status registers.
OCD Control Register
The OCD Control Register, shown in Table 103, controls the state of the On-Chip Debugger. This register enters or exits Debug Mode and enables the BRK instruction.
A reset and stop function can be achieved by writing 81h to this register. A reset and go
function can be achieved by writing 41h to this register. If the device is operating in
Debug Mode, a run function can be implemented by writing 40h to this register.
Table 103. OCD Control Register (OCDCTL)
Bit
Field
7
6
DBGMODE
BRKEN
RESET
4
3
2
DBGACK BRKLOOP
Reserved
1
0
RST
0
R/W
Bit
5
R/W
R
R/W
Description
Debug Mode
[7]
DBGMODE Setting this bit to 1 causes the device to enter Debug Mode. When in Debug Mode, the eZ8
CPU stops fetching new instructions. Clearing this bit causes the eZ8 CPU to start running
again. This bit is automatically set when a BRK instruction is decoded and breakpoints are
enabled. If the Read Protect option bit is enabled, this bit can only be cleared by resetting
the device, it cannot be written to 0.
0 = TheZ8 Encore! XP F64xx Series device is operating in Normal Mode.
1 = The Z8 Encore! XP F64xx Series device is in Debug Mode.
[6]
BRKEN
Breakpoint Enable
This bit controls the behavior of the BRK instruction (op code 00h). By default, breakpoints
are disabled and the BRK instruction behaves like a NOP. If this bit is set to 1 and a BRK
instruction is decoded, the OCD takes action dependent upon the BRKLOOP bit.
0 = BRK instruction is disabled.
1 = BRK instruction is enabled.
[5]
DBGACK
Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends
an Debug Acknowledge character (FFh) to the host when a breakpoint occurs.
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
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Bit
Description (Continued)
[4]
BRKLOOP
Breakpoint Loop
This bit determines what action the OCD takes when a BRK instruction is decoded if breakpoints are enabled (BRKEN is 1). If this bit is 0, then the DBGMODE bit is automatically set
to 1 and the OCD entered Debug Mode. If BRKLOOP is set to 1, then the
eZ8 CPU loops on the BRK instruction.
0 = BRK instruction sets DBGMODE to 1.
1 = eZ8 CPU loops on BRK instruction.
[3:1]
Reserved
These bits are reserved and must be programmed to 000.
[0]
RST
Reset
Setting this bit to 1 resets the Z8 Encore! XP F64xx Series devices. The devices go through
a normal Power-On Reset sequence with the exception that the On-Chip Debugger is not
reset. This bit is automatically cleared to 0 when the reset finishes.
0 = No effect.
1 = Reset the Z8 Encore! XP F64xx Series device.
OCD Status Register
The OCD Status Register, shown in Table 104, reports status information about the current
state of the debugger and the system.
Table 104. OCD Status Register (OCDSTAT)
Bit
Field
7
6
5
4
IDLE
HALT
RPEN
3
2
1
0
Reserved
RESET
0
R/W
R
Bit
Description
[7]
IDLE
CPU Idle
This bit is set if the part is in Debug Mode (DBGMODE is 1), or if a BRK instruction occurred
since the last time OCDCTL was written. This can be used to determine if the CPU is running
or if it is idling.
0 = The eZ8 CPU is running.
1 = The eZ8 CPU is either stopped or looping on a BRK instruction.
[6]
HALT
Halt Mode
0 = The device is not in Halt Mode.
1 = The device is in Halt Mode.
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Bit
Description (Continued)
[5]
RPEN
Read Protect Option Bit Enabled
0 = The Read Protect option bit is disabled (1).
1 = The Read Protect option bit is enabled (0), disabling many OCD commands.
[4:0]
Reserved
These bits are reserved and must be programmed to 00000.
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On-Chip Oscillator
The products in the Z8 Encore! XP F64xx Series feature an on-chip oscillator for use with
external crystals with frequencies from 32 kHz to 20 MHz. In addition, the oscillator can
support external RC networks with oscillation frequencies up to 4 MHz or ceramic resonators with oscillation frequencies up to 20 MHz. This oscillator generates the primary system clock for the internal eZ8 CPU and the majority of the on-chip peripherals.
Alternatively, the XIN input pin can also accept a CMOS-level clock input signal
(32 kHz–20 MHz). If an external clock generator is used, the XOUT pin must be left unconnected.
When configured for use with crystal oscillators or external clock drivers, the frequency of
the signal on the XIN input pin determines the frequency of the system clock (that is, no
internal clock divider). In RC operation, the system clock is driven by a clock divider
(divide by 2) to ensure 50% duty cycle.
Operating Modes
The Z8 Encore! XP F64xx Series products support four different oscillator modes:
•
•
•
On-chip oscillator configured for use with external RC networks (< 4 MHz)
•
Maximum power for use with high frequency crystals or ceramic resonators (8.0 MHz
to 20.0 MHz)
Minimum power for use with very low frequency crystals (32 kHz to 1.0 MHz)
Medium power for use with medium frequency crystals or ceramic resonators (0.5 MHz
to 10.0 MHz)
The oscillator mode is selected through user-programmable option bits. For more information, see the Option Bits chapter on page 180.
Crystal Oscillator Operation
Figure 40 displays a recommended configuration for connection with an external fundamental-mode, parallel-resonant crystal operating at 20 MHz. Recommended 20 MHz crystal specifications are provided in Table 105. Resistor R1 is optional and limits total power
dissipation by the crystal. The printed circuit board layout must add no more than 4 pF of
stray capacitance to either the XIN or XOUT pins. If oscillation does not occur, reduce the
values of capacitors C1 and C2 to decrease loading.
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On-Chip Oscillator
XIN
XOUT
R1 = 220Ω
Crystal
C1 = 22pF
C2 = 22pF
Figure 40. Recommended 20 MHz Crystal Oscillator Configuration
Table 105. Recommended Crystal Oscillator Specifications (20 MHz Operation)
Parameter
Value
Units
Frequency
20
MHz
Resonance
Parallel
Mode
Comments
Fundamental
Series Resistance (RS)
25
W
Maximum
Load Capacitance (CL)
20
pF
Maximum
Shunt Capacitance (C0)
7
pF
Maximum
Drive Level
1
mW
Maximum
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Oscillator Operation with an External RC Network
The External RC Oscillator Mode is applicable to timing-insensitive applications.
Figure 41 displays a recommended configuration for connection with an external resistorcapacitor (RC) network.
VDD
R
XIN
C
Figure 41. Connecting the On-Chip Oscillator to an External RC Network
An external resistance value of 45 kΩ is recommended for oscillator operation with an
external RC network. The minimum resistance value to ensure operation is 40 kΩThe
typical oscillator frequency can be estimated from the values of the resistor (R in kΩ) and
capacitor (C in pF) elements using the following equation:
6
1 10
Oscillator Frequency (kHz) = -------------------------------------------------------- 0.4 R C + 4 C
Figure 42 displays the typical (3.3 V and 25°C) oscillator frequency as a function of the
capacitor (C in pF) employed in the RC network assuming a 45 kΩ external resistor. For
very small values of C, the parasitic capacitance of the oscillator XIN pin and the printed
circuit board should be included in the estimation of the oscillator frequency.
It is possible to operate the RC oscillator using only the parasitic capacitance of the package and printed circuit board. To minimize sensitivity to external parasitics, external
capacitance values in excess of 20 pF are recommended.
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4000
3750
3500
3250
3000
2750
Frequency (kHz)
2500
2250
2000
1750
1500
1250
1000
750
500
250
0
0
20
40
60
80
100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500
C (pF)
Figure 42. Typical RC Oscillator Frequency as a Function of the External Capacitance
with a 45 kΩ Resistor
Caution: When using the external RC oscillator mode, the oscillator may stop oscillating if the
power supply drops below 2.7 V, but before the power supply drops to the voltage brownout threshold. The oscillator will resume oscillation as soon as the supply voltage exceeds
2.7 V.
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Electrical Characteristics
The data in this chapter represents all known data prior to qualification and characterization of the Z8 Encore! XP F64xx Series of products, and is therefore subject to change.
Additional electrical characteristics may be found in the individual chapters of this document.
Absolute Maximum Ratings
Stresses greater than those listed in Table 106 may cause permanent damage to the device.
These ratings are stress ratings only. Operation of the device at any condition outside those
indicated in the operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
For improved reliability, unused inputs must be tied to one of the supply voltages (VDD or
VSS).
Table 106. Absolute Maximum Ratings
Parameter
Minimum Maximum
Units
Ambient temperature under bias
–40
+125
C
Storage temperature
–65
+150
C
Voltage on any pin with respect to VSS
–0.3
+5.5
V
Voltage on VDD pin with respect to VSS
–0.3
+3.6
V
Maximum current on input and/or inactive output pin
–5
+5
µA
Maximum output current from active output pin
–25
+25
mA
Total power dissipation
550
mW
Maximum current into VDD or out of VSS
150
mA
Total power dissipation
200
mW
Maximum current into VDD or out of VSS
56
mA
Total power dissipation
1000
mW
Maximum current into VDD or out of VSS
275
mA
Total power dissipation
500
mW
Maximum current into VDD or out of VSS
140
mA
Notes
1
80-pin QFP maximum ratings at –40°C to 70°C
80-pin QFP maximum ratings at 70°C to 125°C
68-pin PLCC maximum ratings at –40°C to 70°C
68-pin PLCC maximum ratings at 70°C to 125°C
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Table 106. Absolute Maximum Ratings (Continued)
Parameter
Minimum Maximum
Units
Notes
64-pin LQFP maximum ratings at –40°C to 70°C
Total power dissipation
1000
mW
Maximum current into VDD or out of VSS
275
mA
Total power dissipation
540
mW
Maximum current into VDD or out of VSS
150
mA
Total power dissipation
750
mW
Maximum current into VDD or out of VSS
200
mA
Total power dissipation
295
mW
Maximum current into VDD or out of VSS
83
mA
Total power dissipation
750
mW
Maximum current into VDD or out of VSS
200
mA
Total power dissipation
360
mW
Maximum current into VDD or out of VSS
100
mA
64-pin LQFP maximum ratings at 70°C to 125°C
44-pin PLCC maximum ratings at –40°C to 70°C
44-pin PLCC maximum ratings at 70°C to 125°C
44-pin LQFP maximum ratings at –40°C to 70°C
44-pin LQFP maximum ratings at 70°C to 125°C
Note: This voltage applies to all pins, with the exception of VDD, AVDD, pins supporting analog input (ports B and H),
RESET, and where noted otherwise.
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DC Characteristics
Table 107 lists the DC characteristics of the Z8 Encore! XP F64xx Series products. All
voltages are referenced to VSS, the primary system ground.
Table 107. DC Characteristics
TA = –40°C to 125°C
Minimum
Typical
Supply Voltage
3.0
–
3.6
V
VIL1
Low Level Input
Voltage
–0.3
–
0.3*VDD
V
For all input pins except
RESET, DBG, XIN
VIL2
Low Level Input
Voltage
–0.3
–
0.2*VDD
V
For RESET, DBG, and
XIN.
VIH1
High Level Input
Voltage
0.7*VDD
–
5.5
V
Port A, C, D, E, F, and G
pins.
VIH2
High Level Input
Voltage
0.7*VDD
–
VDD+0.3
V
Port B and H pins.
VIH3
High Level Input
Voltage
0.8*VDD
–
VDD+0.3
V
RESET, DBG, and XIN
pins
VOL1
Low Level Output
Voltage Standard Drive
–
–
0.4
V
IOL = 2 mA; VDD = 3.0 V
High Output Drive disabled.
VOH1
High Level Output
Voltage Standard Drive
2.4
–
–
V
IOH = –2 mA; VDD = 3.0 V
High Output Drive disabled.
VOL2
Low Level Output
Voltage High Drive
–
–
0.6
V
IOL = 20 mA; VDD = 3.3 V
High Output Drive
enabled
TA = –40°C to +70°C
VOH2
High Level Output
Voltage
High Drive
2.4
–
–
V
IOH = –20 mA; VDD = 3.3 V
High Output Drive
enabled;
TA = –40°C to +70°C
VOL3
Low Level Output
Voltage
High Drive
–
–
0.6
V
IOL = 15 mA; VDD = 3.3 V
High Output Drive
enabled;
TA = +70°C to +105°C
Symbol
Parameter
VDD
Maximum Units Conditions
Notes:
1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.
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Table 107. DC Characteristics (Continued)
TA = –40°C to 125°C
Minimum
Typical
High Level Output
Voltage
High Drive
2.4
–
–
V
VRAM
RAM Data Retention
0.7
–
–
V
IIL
Input Leakage Current
–5
–
+5
µA
VDD = 3.6 V;
VIN = VDD or VSS1
ITL
Tri-State Leakage
Current
–5
–
+5
µA
VDD = 3.6 V
CPAD
GPIO Port Pad
Capacitance
–
8.02
–
pF
CXIN
XIN Pad Capacitance
–
8.02
–
pF
–
pF
Symbol
Parameter
VOH3
Maximum Units Conditions
IOH = 15 mA; VDD = 3.3 V
High Output Drive
enabled;
TA = +70°C to +105°C
CXOUT
XOUT Pad Capacitance
–
9.52
IPU
Weak Pull-up Current
30
100
350
µA
VDD = 3.0–3.6 V
IDDA
Active Mode Supply
Current; GPIO pins are
configured as outputs
(see Figure 43 on page
205 and Figure 44 on
page 206)
–
11
16
mA
VDD = 3.6 V, FSYSCLK =
20 MHz
–
–
12
mA
VDD = 3.3 V
–
9
11
mA
VDD = 3.6 V, FSYSCLK =
10 MHz
–
–
9
mA
VDD = 3.3 V
–
4
7
mA
VDD = 3.6 V, FSYSCLK =
20 MHz
–
–
5
mA
VDD = 3.3 V
–
3
5
mA
VDD = 3.6 V, FSYSCLK =
10 MHz
–
–
4
mA
VDD = 3.3 V
IDDH
Halt Mode Supply
Current; GPIO pins
configured as outputs
(see Figure 45 on page
207 and Figure 46 on
page 208)
Notes:
1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.
PS019926-1114
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Table 107. DC Characteristics (Continued)
TA = –40°C to 125°C
Symbol
Parameter
IDDS
Stop Mode Supply
Current; GPIO pins
configured as outputs
(see Figure 47 on page
209 and Figure 48 on
page 210)
Minimum
Typical
Maximum Units Conditions
–
520
µA
–
–
–
VBO and WDT enabled
700
VDD = 3.6 V
650
VDD = 3.3 V
10
µA
VBO disabled,
WDT enabled,
TA = 0 to 70ºC
25
VDD = 3.6 V
20
VDD = 3.3 V
–
µA
VBO disabled,
WDT enabled,
TA = –40 to +105ºC
80
VDD = 3.6 V
70
VDD = 3.3 V
–
µA
VBO disabled,
WDT enabled,
TA = –40 to +125ºC
250
VDD = 3.6 V
150
VDD = 3.3 V
Notes:
1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.
PS019926-1114
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Figure 43 displays the typical active mode current consumption while operating at 25 ºC
plotted opposite the system clock frequency. All GPIO pins are configured as outputs and
driven High.
15
Idd (mA)
12
9
6
3
0
0
5
10
15
20
System Clock Frequency (MHz)
3.0V
3.3V
3.6V
Figure 43. Typical Active Mode IDD vs. System Clock Frequency
PS019926-1114
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Figure 44 displays the maximum active mode current consumption across the full operating temperature range of the device and plotted opposite the system clock frequency. All
GPIO pins are configured as outputs and driven High.
15
Idd (mA)
12
9
6
3
0
0
5
10
15
20
System Clock Frequency (MHz)
3.0V
3.3V
3.6V
Figure 44. Maximum Active Mode IDD vs. System Clock Frequency
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Figure 45 displays the typical current consumption in Halt Mode while operating at 25ºC
plotted opposite the system clock frequency. All GPIO pins are configured as outputs and
driven High.
5
HALT Idd (mA)
4
3
2
1
0
0
5
10
15
20
System Clock Frequency (MHz)
3.0V
3.3V
3.6V
Figure 45. Typical Halt Mode IDD vs. System Clock Frequency
PS019926-1114
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Z8 Encore! XP® F64xx Series
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Figure 46 displays the maximum Halt Mode current consumption across the full operating
temperature range of the device and plotted opposite the system clock frequency. All
GPIO pins are configured as outputs and driven High.
6
Halt Idd (mA)
5
4
3
2
1
0
0
5
10
15
20
System Clock Frequency (MHz)
3.0V
3.3V
3.6V
Figure 46. Maximum Halt Mode ICC vs. System Clock Frequency
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Figure 47 displays the maximum current consumption in Stop Mode with the VBO and
Watchdog Timer enabled plotted opposite the power supply voltage. All GPIO pins are
configured as outputs and driven High.
STOP Idd (microamperes)
700
650
600
550
500
450
400
3.0
3.2
3.4
3.6
Vdd (V)
-40/105C
0/70C
25C Typical
Figure 47. Maximum Stop Mode IDD with VBO Enabled vs. Power Supply Voltage
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Figure 48 displays the maximum current consumption in Stop Mode with the VBO disabled and Watchdog Timer enabled plotted opposite the power supply voltage. All GPIO
pins are configured as outputs and driven High. Disabling the Watchdog Timer and its
internal RC oscillator in Stop Mode will provide some additional reduction in Stop Mode
current consumption. This small current reduction would be indistinguishable on the scale
shown in the figure.
120.00
STOP Idd (microamperes)
100.00
80.00
60.00
40.00
20.00
0.00
3.0
3.2
3.4
3.6
Vdd (V)
25C Typical
0/70C
-40/105C
-40/+125C
Figure 48. Maximum Stop Mode IDD with VBO Disabled vs. Power Supply Voltage
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On-Chip Peripheral AC and DC Electrical Characteristics
Table 108. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing
TA = –40°C to 125°C
Minimum
Typical*
Power-On Reset
Voltage Threshold
2.40
2.70
2.90
V
VDD = VPOR
Voltage Brown-Out
Reset Voltage
Threshold
2.30
2.60
2.85
V
VDD = VVBO
VPOR to VVBO
hysteresis
50
100
–
mV
Starting VDD voltage to
ensure valid Power-On
Reset.
–
VSS
–
V
TANA
Power-On Reset
Analog Delay
–
50
–
µs
VDD > VPOR; TPOR Digital
Reset delay follows TANA
TPOR
Power-On Reset Digital
Delay
–
6.6
–
ms
66 WDT Oscillator cycles
(10 kHz) + 16 System
Clock cycles (20 MHz)
TVBO
Voltage Brown-Out
Pulse Rejection Period
–
10
–
µs
VDD < VVBO to generate a
Reset.
TRAMP
Time for VDD to
transition from VSS to
VPOR to ensure valid
Reset
0.10
–
100
ms
Symbol
Parameter
VPOR
VVBO
Maximum Units Conditions
Note: *Data in the typical column is from characterization at 3.3 V and 0°C. These values are provided for design guidance only and are not tested in production.
PS019926-1114
P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical
Z8 Encore! XP® F64xx Series
Product Specification
212
Table 109. External RC Oscillator Electrical Characteristics and Timing
TA = –40°C to 125°C
Symbol
Parameter
Minimum
Typical*
2.701
Maximum Units
–
–
V
VDD
Operating Voltage
Range
REXT
External Resistance
from XIN to VDD
40
45
200
kΩ
CEXT
External Capacitance
from XIN to VSS
0
20
1000
pF
FOSC
External RC Oscillation
Frequency
–
–
4
MHz
Conditions
VDD = VVBO
Note: *When using the external RC oscillator mode, the oscillator may stop oscillating if the power supply drops below
2.7 V, but before the power supply drops to the voltage brown-out threshold. The oscillator will resume oscillation as soon as the supply voltage exceeds 2.7 V.
Table 110. Reset and Stop Mode Recovery Pin Timing
TA = –40°C to 125°C
Minimum
Typical
RESET pin assertion to
initiate a system reset.
4
–
–
Stop Mode Recovery
pin Pulse Rejection
Period
10
20
40
Symbol
Parameter
TRESET
TSMR
PS019926-1114
Maximum Units
Conditions
TCLK Not in Stop Mode.
TCLK = System Clock
period.
ns
RESET, DBG, and GPIO
pins configured as SMR
sources.
P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical
Z8 Encore! XP® F64xx Series
Product Specification
213
Table 111 list the Flash memory electrical characteristics and timing.
Table 111. Flash Memory Electrical Characteristics and Timing
VDD = 3.0–3.6 V
TA = –40°C to 125°C
Minimum
Typical
Flash Byte Read Time
50
–
–
ns
Flash Byte Program
Time
20
–
40
µs
Flash Page Erase Time
10
–
–
ms
Flash Mass Erase Time
200
–
–
ms
Writes to Single
Address Before Next
Erase
–
–
2
Flash Row Program
Time
–
–
8
100
–
–
years 25°C
Endurance, –40°C to
105°C
10,000
–
–
cycles Program/erase cycles
Endurance, 106°C to
125°C
1,000
–
–
cycles Program/erase cycles
Parameter
Data Retention
Maximum Units
Notes
ms
Cumulative program time for single
row cannot exceed limit before next
erase. This parameter is only an
issue when bypassing the Flash
Controller.
Table 112 lists the Watchdog Timer electrical characteristics and timing.
Table 112. Watchdog Timer Electrical Characteristics and Timing
VDD = 3.0–3.6 V
TA = –40°C to 125°C
Symbol
Parameter
FWDT
IWDT
Minimum
Typical
WDT Oscillator
Frequency
5
10
20
kHz
WDT Oscillator Current
including internal RC
Oscillator
–
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