High Performance 8-Bit Microcontrollers
Z8 Encore! XP® 64K Series
Flash Microcontrollers
Product Specification
PS019919-1207
Copyright ©2007 by Zilog®, Inc. All rights reserved.
www.zilog.com
Warning:
DO NOT USE IN LIFE SUPPORT
LIFE SUPPORT POLICY
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A
critical component is any component in a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system or to affect its safety or
effectiveness.
Document Disclaimer
©2007 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.
Z I L O G A L S O D O E S N O T A S S U M E L I A B I L I T Y F O R I N T E L L E C T U A L P R O P E RT Y
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this
document has been verified according to the general principles of electrical and mechanical engineering.
Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered
trademarks of Zilog, Inc. All other product or service names are the property of their respective owners.
PS019919-1207
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Product Specification
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Revision History
Each instance in the Revision History reflects a change to this document from its previous
revision. For more details, refer to the corresponding pages or appropriate links given in
the table below.
Date
PS019919-1207
Revision
Level
Description
Page
No
December 19
2007
Updated Zilog logo, Disclaimer section, and implemented All
style guide. Updated Table 112. Changed Z8 Encore! 64K
Series to Z8 Encore! XP 64K Series Flash
Microcontrollers throughout the document.
December 18
2006
Updated Table 110 and Ordering Information.
228,
270
November 17
2006
Updated Part Number Suffix Designations.
275
June 2006 16
Updated Timer 0-3 Control 1 Registers.
94
October
2005
The paragraph tag for Ordering Information has been
changed from H1 Heading to Chapter Title.
270
15
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
iv
Table of Contents
Manual Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Manual Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Safeguards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ8™ CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
3
3
3
4
4
4
4
5
5
5
5
5
5
5
Signal and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Control Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reset and Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Brownout Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode Recovery Using Watchdog Timer Time-Out . . . . . . . . . . . . . . .
Stop Mode Recovery Using a GPIO Port Pin Transition HALT . . . . . . . . . .
47
47
48
49
50
51
51
52
52
52
53
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Port Availability By Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A–H Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
57
58
59
60
61
61
62
66
66
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Edge Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Port Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
70
70
70
71
71
72
73
74
75
76
78
78
79
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Output Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0-3 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0-3 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . .
Timer 0-3 Control 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0-3 Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
81
82
82
90
90
90
90
91
92
93
94
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Watchdog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Watchdog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Watchdog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . 99
Watchdog Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 100
Watchdog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Watchdog Timer Reload Upper, High and Low Byte Registers . . . . . . . . . 101
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UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitting Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . .
Transmitting Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . .
Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . .
Receiving Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . .
Clear To Send (CTS) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MULTIPROCESSOR (9-bit) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Status 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Control 0 and Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . .
UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . .
103
103
104
104
105
106
107
108
109
109
110
111
113
114
114
115
115
116
117
120
120
Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Infrared Encoder/Decoder Control Register Definitions . . . . . . . . . . . . . . . . .
125
125
126
126
127
128
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Clock Phase and Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . .
135
135
136
137
137
137
139
140
141
142
I2C Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDA and SCL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Control of I2C Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Write and Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Only Transaction with a 7-bit Address . . . . . . . . . . . . . . . . . . . .
Write Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Only Transaction with a 10-bit Address . . . . . . . . . . . . . . . . . . .
Write Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . .
I2C Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Diagnostic Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
143
144
144
145
145
146
147
147
148
149
150
151
153
154
156
156
157
158
160
161
163
Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA0 and DMA1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuring DMA0 and DMA1 for Data Transfer . . . . . . . . . . . . . . . . . . . .
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165
165
166
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DMA_ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuring DMA_ADC for Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAx Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAx I/O Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAx Address High Nibble Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAx Start/Current Address Low Byte Register . . . . . . . . . . . . . . . . . . . .
DMAx End Address Low Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA_ADC Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA_ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
166
167
167
167
168
169
170
170
171
172
173
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Shot Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Control of the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
175
176
176
177
177
178
179
179
180
180
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Using the Flash Frequency Registers . . . . . . . . . . . . . . . . . . . . .
Flash Read Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Write/Erase Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Controller Behavior in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . .
Flash Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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185
185
186
186
186
187
188
189
189
189
190
190
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Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . . .
190
191
192
192
Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Option Bit Configuration By Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
195
195
195
195
196
197
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DEBUG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Auto-Baud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . .
OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
199
199
200
200
201
202
202
203
203
204
209
209
210
On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Operation with an External RC Network . . . . . . . . . . . . . . . . . . . . .
211
211
211
213
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . .
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217
226
231
232
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Z8 Encore! XP® 64K Series Flash Microcontrollers
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xi
General-Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
233
234
235
236
237
238
eZ8™ CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . . . . .
Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ8 CPU Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
241
242
242
244
245
250
259
Opcode Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Part Number Suffix Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
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Z8 Encore! XP® 64K Series Flash Microcontrollers
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xii
Manual Objectives
This Product Specification provides detailed operating information for the Flash devices
within Zilog’s Z8 Encore! XP® 64K Series Flash Microcontrollers Microcontroller
(MCU) products. Within this document, the Z8F642x, Z8F482x, Z8F322x, Z8F242x, and
Z8F162x devices are referred to collectively as the Z8 Encore! XP® 64K Series Flash
Microcontrollers unless specifically stated otherwise.
About This Manual
Zilog® recommends that you read and understand everything in this manual before setting
up and using the product. However, we recognize that there are different styles of learning.
Therefore, we have designed this Product Specification to be used either as a how to
procedural manual or a reference guide to important data.
Intended Audience
This document is written for Zilog customers who are experienced at working with microcontrollers, integrated circuits, or printed circuit assemblies.
Manual Conventions
The following assumptions and conventions are adopted to provide clarity and ease of use:
Courier Typeface
Commands, code lines and fragments, bits, equations, hexadecimal addresses, and various
executable items are distinguished from general text by the use of the Courier typeface.
Where the use of the font is not indicated, as in the Index, the name of the entity is
presented in upper case.
•
Example: FLAGS[1] is smrf.
Hexadecimal Values
Hexadecimal values are designated by uppercase H suffix and appear in the Courier
typeface.
•
Example: R1 is set to F8H.
Brackets
The square brackets, [ ], indicate a register or bus.
•
PS019919-1207
Example: For the register R1[7:0], R1 is an 8-bit register, R1[7] is the most significant
bit, and R1[0] is the least significant bit.
Manual Objectives
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
xiii
Braces
The curly braces, { }, indicate a single register or bus created by concatenating some
combination of smaller registers, buses, or individual bits.
•
Example: The 12-bit register address {0H, RP[7:4], R1[3:0]} is composed of a 4-bit
hexadecimal value (0H) and two 4-bit register values taken from the Register Pointer
(RP) and Working Register R1. 0H is the most-significant nibble (4-bit value) of the
12-bit register, and R1[3:0] is the least significant nibble of the 12-bit register.
Parentheses
The parentheses, ( ), indicate an indirect register address lookup.
•
Example: (R1) is the memory location referenced by the address contained in the
Working Register R1.
Parentheses/Bracket Combinations
The parentheses, ( ), indicate an indirect register address lookup and the square brackets,
[ ], indicate a register or bus.
•
Example: Assume PC[15:0] contains the value 1234h. (PC[15:0]) then refers to the
contents of the memory location at address 1234h.
Use of the Words Set, Reset and Clear
The word set implies that a register bit or a condition contains a logical 1. The words reset
or clear imply that a register bit or a condition contains a logical 0. When either of these
terms is followed by a number, the word logical may not be included; however, it is
implied.
Notation for Bits and Similar Registers
A field of bits within a register is designated as: Register[n:n].
•
Example: ADDR[15:0] refers to bits 15 through bit 0 of the Address.
Use of the Terms LSB, MSB, lsb, and msb
In this document, the terms LSB and MSB, when appearing in upper case, mean least
significant byte and most significant byte, respectively. The lowercase forms, lsb and msb,
mean least significant bit and most significant bit, respectively.
Use of Initial Uppercase Letters
Initial uppercase letters designate settings and conditions in general text.
•
•
PS019919-1207
Example 1: The receiver forces the SCL line to Low.
Example 2: The Master can generate a Stop condition to abort the transfer.
Manual Objectives
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
xiv
Use of All Uppercase Letters
The use of all uppercase letters designates the names of states, modes, and commands.
•
•
•
Example 1: The bus is considered BUSY after the Start condition.
Example 2: A START command triggers the processing of the initialization sequence.
Example 3: STOP mode.
Bit Numbering
Bits are numbered from 0 to n–1 where n indicates the total number of bits. For example,
the 8 bits of a register are numbered from 0 to 7.
Safeguards
It is important that you understand the following safety terms, which are defined here.
Caution:
PS019919-1207
Indicates a procedure or file may become corrupted if you do not follow
directions.
Manual Objectives
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
1
Introduction
Zilog’s Z8 Encore! XP MCU family of products are a line of Zilog® microcontroller
products based upon the 8-bit eZ8 CPU. The Z8 Encore! XP® 64K Series Flash
Microcontrollers, hereafter referred to collectively as the Z8 Encore! XP or the 64K Series
adds Flash memory to Zilog’s extensive line of 8-bit microcontrollers. The Flash in-circuit
programming capability allows for faster development time and program changes in the
field. The new eZ8™ CPU is upward compatible with existing Z8® instructions. The richperipheral set of the Z8 Encore! XP makes it suitable for a variety of applications
including motor control, security systems, home appliances, personal electronic devices,
and sensors.
Features
The features of Z8 Encore! XP 64K Series Flash Microcontrollers include:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PS019919-1207
20 MHz eZ8 CPU
Up to 64 KB Flash with in-circuit programming capability
Up to 4 KB register RAM
12-channel, 10-bit Analog-to-Digital Converter (ADC)
Two full-duplex 9-bit UARTs with bus transceiver Driver Enable control
Inter-integrated circuit (I2C)
Serial Peripheral Interface (SPI)
Two Infrared Data Association (IrDA)-compliant infrared encoder/decoders
Up to four 16-bit timers with capture, compare, and PWM capability
Watchdog Timer (WDT) with internal RC oscillator
Three-channel DMA
Up to 60 input/output (I/O) pins
24 interrupts with configurable priority
On-Chip Debugger
Voltage Brownout (VBO) Protection
Power-On Reset (POR)
Operating voltage of 3.0 V to 3.6 V with 5 V-tolerant inputs
0 °C to +70 °C, –40 °C to +105 °C, and –40 °C to +125 °C operating temperature
ranges
Introduction
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
2
Part Selection Guide
Table 1 identifies the basic features and package styles available for each device within the
Z8 Encore! XP product line.
Table 1. Z8 Encore! XP 64K Series Flash Microcontrollers Part Selection Guide
16-bit
RAM
Timers
ADC UARTs
40/44-pin 64/68-pin 80-pin
(KB) I/O with PWM Inputs with IrDA I2C SPI packages packages package
Part
Number
Flash
(KB)
Z8F1621
16
2
31
3
8
2
1
1
Z8F1622
16
2
46
4
12
2
1
1
Z8F2421
24
2
31
3
8
2
1
1
Z8F2422
24
2
46
4
12
2
1
1
Z8F3221
32
2
31
3
8
2
1
1
Z8F3222
32
2
46
4
12
2
1
1
Z8F4821
48
4
31
3
8
2
1
1
Z8F4822
48
4
46
4
12
2
1
1
Z8F4823
48
4
60
4
12
2
1
1
Z8F6421
64
4
31
3
8
2
1
1
Z8F6422
64
4
46
4
12
2
1
1
Z8F6423
64
4
60
4
12
2
1
1
X
X
X
X
X
X
X
X
X
X
X
X
Die Form Contact
Sales
Zilog®
PS019919-1207
Introduction
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
3
Block Diagram
Figure 1 displays the block diagram of the architecture of the Z8 Encore! XP 64K Series
Flash Microcontrollers.
XTAL/RC
Oscillator
On-Chip
Debugger
eZ8TM
CPU
Interrupt
Controller
System
Clock
POR/VBO
and Reset
Controller
WDT with
RC Oscillator
Memory Busses
Register Bus
Timers
UARTs
I2C
IrDA
SPI
ADC
DMA
Flash
Controller
RAM
Controller
Flash
Memory
RAM
GPIO
Figure 1. Z8 Encore! XP 64K Series Flash Microcontrollers Block Diagram
CPU and Peripheral Overview
eZ8™ CPU Features
The latest 8-bit eZ8 CPU meets the continuing demand for faster and more code-efficient
microcontrollers. The eZ8 CPU executes a superset of the original Z8® instruction set.
PS019919-1207
Introduction
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
4
The eZ8 CPU features include:
•
Direct register-to-register architecture allows each register to function as an
accumulator, improving execution time and decreasing the required Program Memory
•
Software stack allows much greater depth in subroutine calls and interrupts than
hardware stacks
•
•
•
Compatible with existing Z8 code
•
•
Pipelined instruction fetch and execution
•
•
•
•
New instructions support 12-bit linear addressing of the Register File
Expanded internal Register File allows access of up to 4 KB
New instructions improve execution efficiency for code developed using higher-level
programming languages, including C
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
LDCI, LEA, MULT, and SRL
Up to 10 MIPS operation
C-Compiler friendly
2 to 9 clock cycles per instruction
For more information on the eZ8 CPU, refer to eZ8™ CPU Core User Manual (UM0128)
available for download at www.zilog.com.
General-Purpose Input/Output
The 64K Series features seven 8-bit ports (Ports A-G) and one 4-bit port (Port H) for
general-purpose input/output (GPIO). Each pin is individually programmable. All ports
(except B and H) support 5 V-tolerant inputs.
Flash Controller
The Flash Controller programs and erases the Flash memory.
10-Bit Analog-to-Digital Converter
The Analog-to-Digital Converter converts an analog input signal to a 10-bit binary
number. The ADC accepts inputs from up to 12 different analog input sources.
UARTs
Each UART is full-duplex and capable of handling asynchronous data transfers. The
UARTs support 8- and 9-bit data modes, selectable parity, and an efficient bus transceiver
Driver Enable signal for controlling a multi-transceiver bus, such as RS-485.
PS019919-1207
Introduction
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
5
I2C
The I2C controller makes the Z8 Encore! XP compatible with the I2C protocol. The I2C
controller consists of two bidirectional bus lines, a serial data (SDA) line and a serial clock
(SCL) line.
Serial Peripheral Interface
The serial peripheral interface allows the Z8 Encore! XP to exchange data between other
peripheral devices such as EEPROMs, A/D converters and ISDN devices. The SPI is a
full-duplex, synchronous, character-oriented channel that supports a four-wire interface.
Timers
Up to four 16-bit reloadable timers can be used for timing/counting events or for motor
control operations. These timers provide a 16-bit programmable reload counter and
operate in One-Shot, Continuous, Gated, Capture, Compare, Capture and Compare, and
PWM modes. Only 3 timers (Timers 0-2) are available in the 44-pin packages.
Interrupt Controller
The 64K Series products support up to 24 interrupts. These interrupts consist of 12
internal and 12 GPIO pins. The interrupts have 3 levels of programmable interrupt
priority.
Reset Controller
The Z8 Encore! can be reset using the RESET pin, Power-On Reset, Watchdog Timer,
STOP mode exit, or Voltage Brownout (VBO) warning signal.
On-Chip Debugger
The Z8 Encore! XP features an integrated On-Chip Debugger. The OCD provides a rich
set of debugging capabilities, such as reading and writing registers, programming the
Flash, setting breakpoints and executing code. A single-pin interface provides
communication to the OCD.
DMA Controller
The 64K Series features three channels of DMA. Two of the channels are for register
RAM to and from I/O operations. The third channel automatically controls the transfer of
data from the ADC to the memory.
PS019919-1207
Introduction
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
6
PS019919-1207
Introduction
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
7
Signal and Pin Descriptions
Overview
The Z8 Encore! XP 64K Series Flash Microcontrollers product are available in a variety of
packages styles and pin configurations. This chapter describes the signals and available
pin configurations for each of the package styles. For information on physical package
specifications, see Packaging on page 265.
Available Packages
Table 2 identifies the package styles that are available for each device within the
Z8 Encore! XP 64K Series Flash Microcontrollers product line.
Table 2. Z8 Encore! XP 64K Series Flash Microcontrollers Package Options
Part Number
40-Pin
PDIP
44-pin
LQFP
44-pin
PLCC
Z8F1621
X
X
X
Z8F1622
Z8F2421
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Z8F4822
Z8F4823
Z8F6421
Z8F6422
Z8F6423
PS019919-1207
80-pin
QFP
X
Z8F3222
Z8F4821
68-pin
PLCC
X
Z8F2422
Z8F3221
64-pin
LQFP
X
X
X
X
X
X
X
Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
8
Pin Configurations
Figure 2 through Figure 7 on page 13 display the pin configurations for all of the packages
available in the Z8 Encore! XP 64K Series Flash Microcontrollers. For description of the
signals, see Table 3 on page 14. Timer 3 is not available in the 40-pin and 44-pin packages.
PD4/RXD1
1
40
PC4 / MOSI
PC5 / MISO
PA3 / CTS0
PA2/DE0
PA4 / RXD0
PA5 / TXD0
PA6 / SCL
5
35
PA1 /T0OUT
PA0 / T0IN
PC2 / SS
RESET
VDD
VSS
VDD
10
30
PC1 / T1OUT
PC0 / T1IN
15
25
AVSS
VREF
PB2 / ANA2
PB0 / ANA0
PB1 / ANA1
PB4 / ANA4
PB5 / ANA5
PC6 / T2IN *
DBG
PD0
XOUT
XIN
AVDD
PA7 / SDA
PD6 / CTS1
PC3 / SCK
VSS
PD1
Note: Timer 3 is not supported.
PD5 / TXD1
PD3 / DE1
PB3 / ANA3
20
21
PB7 / ANA7
PB6 / ANA6
* T2OUT is not supported.
Figure 2. Z8 Encore! XP 64K Series Flash Microcontrollers in 40-Pin Dual Inline Package (PDIP)
PS019919-1207
Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
PA0 / T0IN
6
7
1
PA6 / SCL
PA4 / RXD0
PA5 / TXD0
PD3 / DE1
PD4 / RXD1
PD5 / TXD1
PC4 / MOSI
PA3 / CTS0
PC5 / MISO
PA1 / T0OUT
PA2 / DE0
9
40
39
PC3 / SCK
VSS
VDD
PC2 / SS
RESET
VDD
VSS
PD1
34
12
PC7 / T2OUT
PC6 / T2IN
PD0
XOUT
DBG
PC1 / T1OUT
XIN
PC0 / T1IN
29
28
PB7 / ANA7
PB3 / ANA3
PB6 / ANA6
PB4 / ANA4
PB5 / ANA5
23
VSS
PB2 / ANA2
VREF
AVSS
17
18
AVDD
PB0 / ANA0
PB1 / ANA1
VDD
PA7 / SDA
PD6 / CTS1
PD2
Figure 3. Z8 Encore! XP 64K Series Flash Microcontrollers in 44-Pin Plastic Leaded Chip Carrier
(PLCC)
PS019919-1207
Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
PA0 / T0IN
33
34
PA6 / SCL
PA4 / RXD0
PA5 / TXD0
PD3 / DE1
PD4 / RXD1
PD5 / TXD1
PC4 / MOSI
PA3 / CTS0
PC5 / MISO
PA1 / T0OUT
PA2 / DE0
10
23
22
28
PD6 / CTS1
PD2
PC2 / SS
RESET
PC3 / SCK
VSS
VDD
VSS
PD1
39
17
VDD
PC7 / T2OUT
PC6 / T2IN
PD0
XOUT
XIN
DBG
12
11
PB7 / ANA7
PB3 / ANA3
PB6 / ANA6
6
PC1 / T1OUT
PC0 / T1IN
VSS
PB2 / ANA2
VREF
AVSS
1
PB4 / ANA4
PB5 / ANA5
44
AVDD
PB0 / ANA0
PB1 / ANA1
VDD
PA7 / SDA
Figure 4. Z8 Encore! XP 64K Series Flash Microcontrollers in 44-Pin Low-Profile Quad Flat Package
(LQFP)
PS019919-1207
Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
PA0 / T0IN
40
48
49
PA4 / RXD0
PA5 / TXD0
PA6 / SCL
VDD
VSS
PC4 / MOSI
PD4 / RXD1
PD5 / TXD1
VDD
PF7
PC5 / MISO
PD3 / DE1
PA3 / CTS0
VSS
PA1 / T0OUT
PA2 / DE0
11
33
32
PD6 / CTS1
PD2
PC2 / SS
RESET
VDD
PE4
PE3
VSS
PC3 / SCK
PD7 / RCOUT
VSS
PE5
PE6
25
56
PE7
VDD
PE2
PE1
PE0
VSS
PD1 / T3OUT
PG3
VDD
PC7 / T2OUT
PC6 / T2IN
DBG
17
16
PB6 / ANA6
PB7 / ANA7
PB3 / ANA3
PB2 / ANA2
PH2 / ANA10
PB4 / ANA4
PB5 / ANA5
PB1 / ANA1
8
PC1 / T1OUT
PC0 / T1IN
PH3 / ANA11
VREF
AVSS
1
PH1 / ANA9
PB0 / ANA0
64
VSS
AVDD
PH0 / ANA8
PD0 / T3IN
XOUT
XIN
PA7 / SDA
Figure 5. Z8 Encore! XP 64K Series Flash Microcontrollers in 64-Pin Low-Profile Quad Flat Package
(LQFP)
PS019919-1207
Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
9
PA0 / T0IN
1
10
VSS
PA4 / RXD0
PA5 / TXD0
PA6 / SCL
VDD
PC4 / MOSI
VDD
PD4 / RXD1
PD5 / TXD1
PF7
PC5 / MISO
PD3 / DE1
VDD
PA3 / CTS0
VSS
PA1 / T0OUT
PA2 / DE0
12
61
60
PC3 / SCK
PD7 / RCOUT
VSS
PE5
PE6
PE4
PE3
VSS
VDD
PG3
VDD
PC7 / T2OUT
PC6 / T2IN
DBG
PB6 / ANA6
PB7 / ANA7
PB3 / ANA3
PB2 / ANA2
PH2 / ANA10
PB4 / ANA4
PB5 / ANA5
PB1 / ANA1
PH1 / ANA9
PB0 / ANA0
35
44
43
PC1 / T1OUT
PC0 / T1IN
VSS
PH3 / ANA11
VREF
AVSS
AVSS
26
27
VSS
PD1 / T3OUT
PD0 / T3IN
XOUT
XIN
PE7
52
18
AVDD
PH0 / ANA8
PE2
PE1
PE0
VSS
VDD
PA7 / SDA
PD6 / CTS1
PD2
PC2 / SS
RESET
VDD
Figure 6. Z8 Encore! XP 64K Series Flash Microcontrollers in 68-Pin Plastic Leaded Chip Carrier
(PLCC)
PS019919-1207
Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
PA0 / T0IN
PD2
PC2 / SS
PF6
RESET
1
80
75
70
PA4 / RXD0
PA5 / TXD0
PA6 / SCL
VDD
VSS
PC4 / MOSI
PD4 / RXD1
PD5 / TXD1
VDD
PF7
PC5 / MISO
PD3 / DE1
PA3 / CTS0
VSS
PA1 / T0OUT
PA2 / DE0
13
65
64
PD6 / CTS1
PC3 / SCK
PD7 / RCOUT
60
5
VDD
PF5
PF4
PE6
PE7
VDD
PG3
PG4
15
50
20
45
PG5
PG6
VDD
PG7
PC7 / T2OUT
PC6 / T2IN
DBG
PC1 / T1OUT
PC0 / T1IN
PB4 / ANA4
PB5 / ANA5
35
41
40
VSS
PH3 / ANA11
VREF
AVSS
30
PB6 / ANA6
PB7 / ANA7
PB3 / ANA3
PB2 / ANA2
PH2 / ANA10
24
25
VSS
PD1 / T3OUT
PD0 / T3IN
XOUT
XIN
55
PB1 / ANA1
PF1
PF0
VDD
PE5
10
PH1 / ANA9
PB0 / ANA0
PE1
PE0
VSS
PF2
PG0
VSS
PG1
PG2
AVDD
PH0 / ANA8
PF3
PE4
PE3
VSS
PE2
PA7 / SDA
Figure 7. Z8 Encore! XP 64K Series Flash Microcontrollers in 80-Pin Quad Flat Package (QFP)
PS019919-1207
Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
14
Signal Descriptions
Table 3 describes the Z8 Encore! XP signals. To determine the signals available for the
specific package styles, see Pin Configurations on page 8.
Table 3. Signal Descriptions
Signal
Mnemonic
I/O
Description
General-Purpose I/O Ports A-H
PA[7:0]
I/O
Port A[7:0]. These pins are used for general-purpose I/O and support
5 V-tolerant inputs.
PB[7:0]
I/O
Port B[7:0]. These pins are used for general-purpose I/O.
PC[7:0]
I/O
Port C[7:0]. These pins are used for general-purpose I/O. These pins are
used for general-purpose I/O and support 5 V-tolerant inputs
PD[7:0]
I/O
Port D[7:0]. These pins are used for general-purpose I/O. These pins are
used for general-purpose I/O and support 5 V-tolerant inputs
PE[7:0]
I/O
Port E[7:0]. These pins are used for general-purpose I/O. These pins are
used for general-purpose I/O and support 5 V-tolerant inputs.
PF[7:0]
I/O
Port F[7:0]. These pins are used for general-purpose I/O. These pins are
used for general-purpose I/O and support 5 V-tolerant inputs.
PG[7:0]
I/O
Port G[7:0]. These pins are used for general-purpose I/O. These pins are
used for general-purpose I/O and support 5 V-tolerant inputs.
PH[3:0]
I/O
Port H[3:0]. These pins are used for general-purpose I/O.
SCL
O
Serial Clock. This is the output clock for the I2C. This pin is multiplexed with a
general-purpose I/O pin. When the general-purpose I/O pin is configured for
alternate function to enable the SCL function, this pin is open-drain.
SDA
I/O
Serial Data. This open-drain pin transfers data between the I2C and a slave.
This pin is multiplexed with a general-purpose I/O pin. When the
general-purpose I/O pin is configured for alternate function to enable the
SDA function, this pin is open-drain.
I2C Controller
SPI Controller
SS
PS019919-1207
I/O
Slave Select. This signal can be an output or an input. If the Z8 Encore! XP
64K Series Flash Microcontrollers is the SPI master, this pin may be
configured as the Slave Select output. If the Z8 Encore! XP 64K Series Flash
Microcontrollers is the SPI slave, this pin is the input slave select. It is
multiplexed with a general-purpose I/O pin.
Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
15
Table 3. Signal Descriptions (Continued)
Signal
Mnemonic
I/O
Description
SCK
I/O
SPI Serial Clock. The SPI master supplies this pin. If the Z8 Encore! XP 64K
Series Flash Microcontrollers is the SPI master, this pin is an output. If the Z8
Encore! XP 64K Series Flash Microcontrollers is the SPI slave, this pin is an
input. It is multiplexed with a general-purpose I/O pin.
MOSI
I/O
Master-Out/Slave-In. This signal is the data output from the SPI master
device and the data input to the SPI slave device. It is multiplexed with a
general-purpose I/O pin.
MISO
I/O
Master-In/Slave-Out. This pin is the data input to the SPI master device and
the data output from the SPI slave device. It is multiplexed with a
general-purpose I/O pin.
TXD0 / TXD1
O
Transmit Data. These signals are the transmit outputs from the UARTs. The
TXD signals are multiplexed with general-purpose I/O pins.
RXD0 / RXD1
I
Receive Data. These signals are the receiver inputs for the UARTs and
IrDAs. The RXD signals are multiplexed with general-purpose I/O pins.
CTS0 / CTS1
I
Clear To Send. These signals are control inputs for the UARTs. The CTS
signals are multiplexed with general-purpose I/O pins.
DE0 / DE1
O
Driver Enable. This signal allows automatic control of external RS-485
drivers. This signal is approximately the inverse of the Transmit Empty (TXE)
bit in the UART Status 0 register. The DE signal may be used to ensure an
external RS-485 driver is enabled when data is transmitted by the UART.
T0OUT/T1OUT/
T2OUT/T3OUT
O
Timer Output 0-3. These signals are output pins from the timers. The Timer
Output signals are multiplexed with general-purpose I/O pins. T3OUT is not
available in 44-pin package devices.
T0IN/T1IN/
T2IN/T3IN
I
Timer Input 0-3. These signals are used as the capture, gating and counter
inputs. The Timer Input signals are multiplexed with general-purpose I/O
pins. T3IN is not available in 44-pin package devices.
ANA[11:0]
I
Analog Input. These signals are inputs to the ADC. The ADC analog inputs
are multiplexed with general-purpose I/O pins.
VREF
I
Analog-to-Digital converter reference voltage input. The VREF pin must be
left unconnected (or capacitively coupled to analog ground) if the internal
voltage reference is selected as the ADC reference voltage.
UART Controllers
Timers
Analog
Oscillators
PS019919-1207
Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
16
Table 3. Signal Descriptions (Continued)
Signal
Mnemonic
I/O
Description
XIN
I
External Crystal Input. This is the input pin to the crystal oscillator. A crystal
can be connected between it and the XOUT pin to form the oscillator. This
signal is usable with external RC networks and an external clock driver.
XOUT
O
External Crystal Output. This pin is the output of the crystal oscillator. A
crystal can be connected between it and the XIN pin to form the oscillator.
When the system clock is referred to in this manual, it refers to the frequency
of the signal at this pin. This pin must be left unconnected when not using a
crystal.
RCOUT
O
RC Oscillator Output. This signal is the output of the RC oscillator. It is
multiplexed with a general-purpose I/O pin. This signal must be left
unconnected when not using a crystal.
On-Chip Debugger
DBG
I/O
Debug. This pin is the control and data input and output to and from the OnChip Debugger. This pin is open-drain.
Caution: For operation of the On-Chip Debugger, all power pins (VDD and
AVDD) must be supplied with power and all ground pins (VSS and
AVSS) must be properly grounded.
The DBG pin is open-drain and must have an external pull-up resistor
to ensure proper operation.
Reset
RESET
I
RESET. Generates a Reset when asserted (driven Low).
VDD
I
Power Supply.
AVDD
I
Analog Power Supply.
VSS
I
Ground.
AVSS
I
Analog Ground.
Power Supply
Pin Characteristics
Table 4 on page 17 provides detailed information on the characteristics for each pin
available on the 64K Series products and the data is sorted alphabetically by the pin
symbol mnemonic.
PS019919-1207
Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
17
Table 4. Pin Characteristics of the Z8 Encore! XP 64K Series Flash Microcontrollers
Symbol
Reset
Mnemonic Direction Direction
Active Low
or
Active High
Internal SchmittTri-State Pull-up or Trigger
Output Pull-down
Input
Open Drain
Output
AVSS
N/A
N/A
N/A
N/A
No
No
N/A
AVDD
N/A
N/A
N/A
N/A
No
No
N/A
DBG
I/O
I
N/A
Yes
No
Yes
Yes
VSS
N/A
N/A
N/A
N/A
No
No
N/A
PA[7:0]
I/O
I
N/A
Yes
No
Yes
Yes,
Programmable
PB[7:0]
I/O
I
N/A
Yes
No
Yes
Yes,
Programmable
PC[7:0]
I/O
I
N/A
Yes
No
Yes
Yes,
Programmable
PD[7:0]
I/O
I
N/A
Yes
No
Yes
Yes,
Programmable
PE7:0]
I/O
I
N/A
Yes
No
Yes
Yes,
Programmable
PF[7:0]
I/O
I
N/A
Yes
No
Yes
Yes,
Programmable
PG[7:0]
I/O
I
N/A
Yes
No
Yes
Yes,
Programmable
PH[3:0]
I/O
I
N/A
Yes
No
Yes
Yes,
Programmable
RESET
I
I
Low
N/A
Pull-up
Yes
N/A
VDD
N/A
N/A
N/A
N/A
No
No
N/A
XIN
I
I
N/A
N/A
No
No
N/A
XOUT
O
O
N/A
Yes, in
STOP
mode
No
No
No
Note: x represents integer 0, 1,... to indicate multiple pins with symbol mnemonics that differ only by the integer.
PS019919-1207
Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
18
PS019919-1207
Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
19
Address Space
Overview
The eZ8™ CPU can access three distinct address spaces:
•
The Register File contains addresses for the general-purpose registers and the
eZ8 CPU, peripheral, and general-purpose I/O port control registers.
•
The Program Memory contains addresses for all memory locations having executable
code and/or data.
•
The Data Memory consists of the addresses for all memory locations that hold only
data.
These three address spaces are covered briefly in the following subsections. For more
information on eZ8 CPU and its address space, refer to eZ8™ CPU Core User Manual
(UM0128) available for download at www.zilog.com.
Register File
The Register File address space in the 64K Series is 4 KB (4096 bytes). The Register File
is composed of two sections—control registers and general-purpose registers. When
instructions are executed, registers are read from when defined as sources and written to
when defined as destinations. The architecture of the eZ8 CPU allows all general-purpose
registers to function as accumulators, address pointers, index registers, stack areas, or
scratch pad memory.
The upper 256 bytes of the 4 KB Register File address space are reserved for control of the
eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at
addresses from F00H to FFFH. Some of the addresses within the 256-byte control register
section are reserved (unavailable). Reading from an reserved Register File addresses
returns an undefined value. Writing to reserved Register File addresses is not
recommended and can produce unpredictable results.
The on-chip RAM always begins at address 000H in the Register File address space. The
64K Series provide 2 KB to 4 KB of on-chip RAM depending upon the device. Reading
from Register File addresses outside the available RAM addresses (and not within the
control register address space) returns an undefined value. Writing to these Register File
addresses produces no effect. To determine the amount of RAM available for the specific
64K Series device, see Part Selection Guide on page 2.
PS019919-1207
Address Space
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
20
Program Memory
The eZ8™ CPU supports 64 KB of Program Memory address space. The Z8 Encore! XP
64K Series Flash Microcontrollers contains 16 KB to 64 KB of on-chip Flash in the
Program Memory address space, depending upon the device. Reading from Program
Memory addresses outside the available Flash memory addresses returns FFH. Writing to
these unimplemented Program Memory addresses produces no effect. Table 5 describes
the Program Memory maps for the 64K Series products.
Table 5. Z8 Encore! XP 64K Series Flash Microcontrollers Program Memory
Maps
Program Memory Address (Hex) Function
Z8F162x Products
0000-0001
Option Bits
0002-0003
Reset Vector
0004-0005
WDT Interrupt Vector
0006-0007
Illegal Instruction Trap
0008-0037
Interrupt Vectors*
0038-3FFF
Program Memory
Z8F242x Products
0000-0001
Option Bits
0002-0003
Reset Vector
0004-0005
WDT Interrupt Vector
0006-0007
Illegal Instruction Trap
0008-0037
Interrupt Vectors*
0038-5FFF
Program Memory
Z8F322x Products
0000-0001
Option Bits
0002-0003
Reset Vector
0004-0005
WDT Interrupt Vector
0006-0007
Illegal Instruction Trap
0008-0037
Interrupt Vectors*
0038-7FFF
Program Memory
Z8F482x Products
PS019919-1207
Address Space
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
21
Table 5. Z8 Encore! XP 64K Series Flash Microcontrollers Program Memory
Maps (Continued)
Program Memory Address (Hex) Function
0000-0001
Option Bits
0002-0003
Reset Vector
0004-0005
WDT Interrupt Vector
0006-0007
Illegal Instruction Trap
0008-0037
Interrupt Vectors*
0038-BFFF
Program Memory
Z8F642x Products
0000-0001
Option Bits
0002-0003
Reset Vector
0004-0005
WDT Interrupt Vector
0006-0007
Illegal Instruction Trap
0008-0037
Interrupt Vectors*
0038-FFFF
Program Memory
*See Table 23 on page 68 for a list of the interrupt vectors.
Data Memory
The Z8 Encore! XP 64K Series Flash Microcontrollers does not use the eZ8 CPU’s 64 KB
Data Memory address space.
Information Area
Table 6 on page 22 describes the Z8 Encore! XP 64K Series Flash Microcontrollers
Information Area. This 512 byte Information Area is accessed by setting bit 7 of the Page
Select Register to 1. When access is enabled, the Information Area is mapped into the
Program Memory and overlays the 512 bytes at addresses FE00H to FFFFH. When the
Information Area access is enabled, execution of LDC and LDCI instruction from these
Program Memory addresses return the Information Area data rather than the Program
Memory data. Reads of these addresses through the On-Chip Debugger also returns the
Information Area data. Execution of code from these addresses continues to correctly use
the Program Memory. Access to the Information Area is read-only.
PS019919-1207
Address Space
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
22
Table 6. Z8 Encore! XP 64K Series Flash Microcontrollers Information Area Map
PS019919-1207
Program Memory
Address (Hex)
Function
FE00H-FE3FH
Reserved
FE40H-FE53H
Part Number
20-character ASCII alphanumeric code
Left justified and filled with zeros (ASCII Null character)
FE54H-FFFFH
Reserved
Address Space
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
23
Register File Address Map
Table 7 provides the address map for the Register File of the 64K Series products. Not all
devices and package styles in the 64K Series support Timer 3 and all of the GPIO Ports.
Consider registers for unimplemented peripherals as Reserved.
Table 7. Z8 Encore! XP 64K Series Flash Microcontrollers Register File Address Map
Address (Hex) Register Description
Mnemonic
Reset (Hex)
General-Purpose RAM
000-EFF
General-Purpose Register File RAM
—
XX
Timer 0
F00
F01
F02
F03
F04
F05
F06
F07
Timer 0 High Byte
Timer 0 Low Byte
Timer 0 Reload High Byte
Timer 0 Reload Low Byte
Timer 0 PWM High Byte
Timer 0 PWM Low Byte
Timer 0 Control 0
Timer 0 Control 1
T0H
T0L
T0RH
T0RL
T0PWMH
T0PWML
T0CTL0
T0CTL1
00
01
FF
FF
00
00
00
00
90
90
91
91
92
92
93
94
Timer 1
F08
F09
F0A
F0B
F0C
F0D
F0E
F0F
Timer 1 High Byte
Timer 1 Low Byte
Timer 1 Reload High Byte
Timer 1 Reload Low Byte
Timer 1 PWM High Byte
Timer 1 PWM Low Byte
Timer 1 Control 0
Timer 1 Control 1
T1H
T1L
T1RH
T1RL
T1PWMH
T1PWML
T1CTL0
T1CTL1
00
01
FF
FF
00
00
00
00
90
90
91
91
92
92
93
94
Timer 2
F10
F11
F12
F13
F14
F15
F16
F17
Timer 2 High Byte
Timer 2 Low Byte
Timer 2 Reload High Byte
Timer 2 Reload Low Byte
Timer 2 PWM High Byte
Timer 2 PWM Low Byte
Timer 2 Control 0
Timer 2 Control 1
T2H
T2L
T2RH
T2RL
T2PWMH
T2PWML
T2CTL0
T2CTL1
00
01
FF
FF
00
00
00
00
90
90
91
91
92
92
93
94
PS019919-1207
Page No
Register File Address Map
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
24
Table 7. Z8 Encore! XP 64K Series Flash Microcontrollers Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
Reset (Hex)
Page No
Timer 3 (unavailable in the 44-pin packages)
F18
Timer 3 High Byte
F19
Timer 3 Low Byte
F1A
Timer 3 Reload High Byte
F1B
Timer 3 Reload Low Byte
F1C
Timer 3 PWM High Byte
F1D
Timer 3 PWM Low Byte
F1E
Timer 3 Control 0
F1F
Timer 3 Control 1
20-3F
Reserved
T3H
T3L
T3RH
T3RL
T3PWMH
T3PWML
T3CTL0
T3CTL1
—
00
01
FF
FF
00
00
00
00
XX
90
90
91
91
92
92
93
94
UART0 Transmit Data
UART0 Receive Data
UART0 Status 0
UART0 Control 0
UART0 Control 1
UART0 Status 1
UART0 Address Compare Register
UART0 Baud Rate High Byte
UART0 Baud Rate Low Byte
U0TXD
U0RXD
U0STAT0
U0CTL0
U0CTL1
U0STAT1
U0ADDR
U0BRH
U0BRL
XX
XX
0000011Xb
00
00
00
00
FF
FF
114
115
115
117
117
115
120
120
120
F49
F4A
F4B
F4C
F4D
F4E
F4F
UART1 Transmit Data
UART1 Receive Data
UART1 Status 0
UART1 Control 0
UART1 Control 1
UART1 Status 1
UART1 Address Compare Register
UART1 Baud Rate High Byte
UART1 Baud Rate Low Byte
U1TXD
U1RXD
U1STAT0
U1CTL0
U1CTL1
U1STAT1
U1ADDR
U1BRH
U1BRL
XX
XX
0000011Xb
00
00
00
00
FF
FF
114
115
115
117
117
115
120
120
120
I2C
F50
F51
F52
F53
F54
F55
F56
F57-F5F
I2C Data
I2C Status
I2C Control
I2C Baud Rate High Byte
I2C Baud Rate Low Byte
I2C Diagnostic State
I2C Diagnostic Control
Reserved
I2CDATA
I2CSTAT
I2CCTL
I2CBRH
I2CBRL
I2CDST
I2CDIAG
—
00
80
00
FF
FF
C0
00
XX
156
157
158
160
160
161
163
SPIDATA
XX
137
UART 0
F40
F41
F42
F43
F44
F45
F46
F47
UART 1
F48
Serial Peripheral Interface (SPI)
F60
SPI Data
PS019919-1207
Register File Address Map
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
25
Table 7. Z8 Encore! XP 64K Series Flash Microcontrollers Register File Address Map (Continued)
Address (Hex)
F61
F62
F63
F64
F65
F66
F67
F68-F6F
Register Description
SPI Control
SPI Status
SPI Mode
SPI Diagnostic State
Reserved
SPI Baud Rate High Byte
SPI Baud Rate Low Byte
Reserved
Mnemonic
SPICTL
SPISTAT
SPIMODE
SPIDST
—
SPIBRH
SPIBRL
—
Reset (Hex)
00
01
00
00
XX
FF
FF
XX
Page No
137
139
140
141
Analog-to-Digital Converter
F70
ADC Control
F71
Reserved
F72
ADC Data High Byte
F73
ADC Data Low Bits
F74-FAF
Reserved
ADCCTL
—
ADCD_H
ADCD_L
—
20
XX
XX
XX
XX
179
DMA 0
FB0
FB1
FB2
FB3
FB4
DMA0 Control
DMA0 I/O Address
DMA0 End/Start Address High Nibble
DMA0 Start Address Low Byte
DMA0 End Address Low Byte
DMA0CTL
DMA0IO
DMA0H
DMA0START
DMA0END
00
XX
XX
XX
XX
167
169
169
170
170
DMA 1
FB8
FB9
FBA
FBB
FBC
DMA1 Control
DMA1 I/O Address
DMA1 End/Start Address High Nibble
DMA1 Start Address Low Byte
DMA1 End Address Low Byte
DMA1CTL
DMA1IO
DMA1H
DMA1START
DMA1END
00
XX
XX
XX
XX
167
169
169
170
170
DMA ADC
FBD
FBE
FBF
DMA_ADC Address
DMA_ADC Control
DMA_ADC Status
DMAA_ADDR XX
DMAACTL
00
DMAASTAT 00
171
172
173
IRQ0
IRQ0ENH
IRQ0ENL
IRQ1
IRQ1ENH
IRQ1ENL
IRQ2
IRQ2ENH
IRQ2ENL
—
71
74
74
72
75
75
73
76
76
Interrupt Controller
FC0
Interrupt Request 0
FC1
IRQ0 Enable High Bit
FC2
IRQ0 Enable Low Bit
FC3
Interrupt Request 1
FC4
IRQ1 Enable High Bit
FC5
IRQ1 Enable Low Bit
FC6
Interrupt Request 2
FC7
IRQ2 Enable High Bit
FC8
IRQ2 Enable Low Bit
FC9-FCC
Reserved
PS019919-1207
00
00
00
00
00
00
00
00
00
XX
142
142
180
180
Register File Address Map
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
26
Table 7. Z8 Encore! XP 64K Series Flash Microcontrollers Register File Address Map (Continued)
Address (Hex)
FCD
FCE
FCF
Register Description
Interrupt Edge Select
Interrupt Port Select
Interrupt Control
Mnemonic
IRQES
IRQPS
IRQCTL
Reset (Hex)
00
00
00
Page No
78
78
79
GPIO Port A
FD0
FD1
FD2
FD3
Port A Address
Port A Control
Port A Input Data
Port A Output Data
PAADDR
PACTL
PAIN
PAOUT
00
00
XX
00
61
62
66
66
GPIO Port B
FD4
FD5
FD6
FD7
Port B Address
Port B Control
Port B Input Data
Port B Output Data
PBADDR
PBCTL
PBIN
PBOUT
00
00
XX
00
61
62
66
66
GPIO Port C
FD8
FD9
FDA
FDB
Port C Address
Port C Control
Port C Input Data
Port C Output Data
PCADDR
PCCTL
PCIN
PCOUT
00
00
XX
00
61
62
66
66
GPIO Port D
FDC
FDD
FDE
FDF
Port D Address
Port D Control
Port D Input Data
Port D Output Data
PDADDR
PDCTL
PDIN
PDOUT
00
00
XX
00
61
62
66
66
GPIO Port E
FE0
FE1
FE2
FE3
Port E Address
Port E Control
Port E Input Data
Port E Output Data
PEADDR
PECTL
PEIN
PEOUT
00
00
XX
00
61
62
66
66
GPIO Port F
FE4
FE5
FE6
FE7
Port F Address
Port F Control
Port F Input Data
Port F Output Data
PFADDR
PFCTL
PFIN
PFOUT
00
00
XX
00
61
62
66
66
GPIO Port G
FE8
FE9
FEA
FEB
Port G Address
Port G Control
Port G Input Data
Port G Output Data
PGADDR
PGCTL
PGIN
PGOUT
00
00
XX
00
61
62
66
66
GPIO Port H
FEC
FED
FEE
Port H Address
Port H Control
Port H Input Data
PHADDR
PHCTL
PHIN
00
00
XX
61
62
66
PS019919-1207
Register File Address Map
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
27
Table 7. Z8 Encore! XP 64K Series Flash Microcontrollers Register File Address Map (Continued)
Address (Hex) Register Description
FEF
Port H Output Data
Mnemonic
PHOUT
Reset (Hex)
00
Page No
66
Watchdog Timer
FF0
Watchdog Timer Control
FF1
Watchdog Timer Reload Upper Byte
FF2
Watchdog Timer Reload High Byte
FF3
Watchdog Timer Reload Low Byte
FF4-FF7
Reserved
WDTCTL
WDTU
WDTH
WDTL
—
XXX00000b
FF
FF
FF
XX
100
101
101
101
Flash Memory Controller
FF8
Flash Control
FF8
Flash Status
FF9
Page Select
FF9 (if enabled) Flash Sector Protect
FFA
Flash Programming Frequency High Byte
FFB
Flash Programming Frequency Low Byte
FF4-FF8
Reserved
FCTL
FSTAT
FPS
FPROT
FFREQH
FFREQL
—
00
00
00
00
00
00
XX
190
190
191
192
192
192
Read-Only Memory Controller
FF9
Page Select
FFA-FFB
Reserved
RPS
—
00
XX
eZ8 CPU
FFC
FFD
FFE
FFF
—
RP
SPH
SPL
XX
XX
XX
XX
Flags
Register Pointer
Stack Pointer High Byte
Stack Pointer Low Byte
Refer to eZ8™
CPU Core
User Manual
(UM0128)
Note: XX=Undefined
PS019919-1207
Register File Address Map
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
28
Control Register
Summary
Timer 0 Control 1
T0CTL1 (F07H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer Mode
000 = One-Shot mode
001 = CONTINUOUS mode
010 = COUNTER mode
011 = PWM mode
100 = CAPTURE mode
101 = COMPARE mode
110 = GATED mode
111 = Capture/COMPARE mode
Timer 0 High Byte
T0H (F00H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 current count value [15:8]
Prescale Value
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
Timer 0 Low Byte
T0L (F01H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 current count value [7:0]
Timer 0 Reload High Byte
T0RH (F02H - Read/Write)
Timer Input/Output Polarity
Operation of this bit is a function of
the current operating mode of the
timer
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 reload value [15:8]
Timer 0 Reload Low Byte
T0RL (HF03 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 reload value [7:0]
Timer Enable
0 = Timer is disabled
1 = Timer is enabled
Timer 1 High Byte
T1H (F08H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 current count value [15:8]
Timer 0 PWM High Byte
T0PWMH (F04H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 PWM value [15:8]
Timer 1 Low Byte
T1L (F09H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 current count value [7:0]
Timer 0 Control 0
T0CTL0 (F06H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Timer 1 Reload High Byte
T1RH (F0AH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Cascade Timer
0 = Timer 0 Input signal is GPIO pin
1 = Timer 0 Input signal is Timer 3
out
Reserved
Timer 1 reload value [15:8]
Timer 1 Reload Low Byte
T1RL (F0BH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 reload value [7:0]
PS019919-1207
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
29
Timer 1 PWM High Byte
T1PWMH (F0CH - Read/Write)
Timer 2 High Byte
T2H (F10H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 PWM value [15:8]
Timer 2 current count value [15:8]
Timer 1 PWM Low Byte
T1PWML (F0DH - Read/Write)
Timer 2 Low Byte
T2L (F11H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 PWM value [7:0]
Timer 2 current count value [7:0]
Timer 1 Control 0
T1CTL0 (F0EH - Read/Write)
Timer 2 Reload High Byte
T2RH (F12H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Cascade Timer
0 = Timer 1 Input signal is GPIO pin
1 = Timer 1 Input signal is Timer 0
out
Reserved
Timer 2 reload value [15:8]
Timer 2 Reload Low Byte
T2RL (F13H- Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 2 reload value [7:0]
Timer 1 Control 1
T1CTL1 (F0FH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer Mode
000 = One-Shot mode
001 = CONTINUOUS mode
010 = COUNTER mode
011 = PWM mode
100 = CAPTURE mode
101 = COMPARE mode
110 = GATED mode
111 = Capture/COMPARE mode
Prescale Value
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
Timer Input/Output Polarity
Operation of this bit is a function of
the current operating mode of the
timer
Timer Enable
0 = Timer is disabled
1 = Timer is enabled
PS019919-1207
Timer 2 PWM High Byte
T2PWMH (F14H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 2 PWM value [15:8]
Timer 2 PWM Low Byte
T2PWML (F15H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 2 PWM value [7:0]
Timer 2 Control 0
T2CTL0 (F16H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Cascade Timer
0 = Timer 2 Input signal is GPIO pin
1 = Timer 2 Input signal is Timer 1
out
Reserved
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
30
Timer 2 Control 1
T2CTL1 (F17H - Read/Write)
Timer 3 PWM High Byte
T3PWMH (F1CH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Timer Mode
000 = One-Shot mode
001 = CONTINUOUS mode
010 = COUNTER mode
011 = PWM mode
100 = CAPTURE mode
101 = COMPARE mode
110 = GATED mode
111 = CAPTURE/COMPARE mode
Prescale Value
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
Timer 3 PWM value [15:8]
Timer 3 PWM Low Byte
T3PWML (F1DH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 3 PWM value [7:0]
Timer 3 Control 0
T3CTL0 (F1EH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Cascade Timer
0 = Timer 3 Input signal is GPIO pin
1 = Timer 3 Input signal is Timer 2
out
Timer Input/Output Polarity
Operation of this bit is a function of
the current operating mode of the
timer
Timer Enable
0 = Timer is disabled
1 = Timer is enabled
Timer 3 High Byte
T3H (F18H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 3 current count value [15:8]
Timer 3 Low Byte
T3L (F19H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 3 current count value [7:0]
Timer 3 Reload High Byte
T3RH (F1AH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 3 reload value [15:8]
Timer 3 Reload Low Byte
T3RL (F1BH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Timer 3 Control 1
T3CTL1 (F1FH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer Mode
000 = One-Shot mode
001 = CONTINUOUS mode
010 = COUNTER mode
011 = PWM mode
100 = CAPTURE mode
101 = COMPARE mode
110 = GATED mode
111 = Capture/COMPARE mode
Prescale Value
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
Timer Input/Output Polarity
Operation of this bit is a function of
the current operating mode of the
timer
Timer Enable
0 = Timer is disabled
1 = Timer is enabled
Timer 3 reload value [7:0]
PS019919-1207
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
31
UART0 Transmit Data
U0TXD (F40H - Write Only)
UART0 Control 0
U0CTL0 (F42H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
UART0 transmitter data byte [7:0]
UART0 Receive Data
U0RXD (F40H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 receiver data byte [7:0]
UART0 Status 0
U0STAT0 (F41H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
CTS signal
Returns the level of the CTS signal
Transmitter Empty
0 = Data is currently transmitting
1 = Transmission is complete
Loop Back Enable
0 = Normal operation
1 = Transmit data is looped back to
the receiver
Stop Bit Select
0 = Transmitter sends 1 Stop bit
1 = Transmitter sends 2 Stop bits
Send Break
0 = No break is sent
1 = Output of the transmitter is zero
Parity Select
0 = Even parity
1 = Odd parity
Parity Enable
0 = Parity is disabled
1 = Parity is enabled
Transmitter Data Register Empty
0 = Transmit Data Register is full
1 = Transmit Data register is empty
CTS Enable
0 = CTS signal has no effect on the
transmitter
1 = UART recognizes CTS signal as
a
transmit enable control signal
Break Detect
0 = No break occurred
1 = A break occurred
Receive Enable
0 = Receiver disabled
1 = Receiver enabled
Framing Error
0 = No framing error occurred
1 = A framing occurred
Transmit Enable
0 = Transmitter disabled
1 = Transmitter enabled
Overrun Error
0 = No overrun error occurred
1 = An overrun error occurred
Parity Error
0 = No parity error occurred
1 = A parity error occurred
Receive Data Available
0 = Receive Data Register is empty
1 = A byte is available in the Receive
Data Register
PS019919-1207
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
32
UART0 Control 1
U0CTL1 (F43H - Read/Write)
UART0 Address Compare
U0ADDR (F45H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
UART0 Address Compare [7:0]
Infrared Encoder/Decoder Enable
0 = Infrared endec is disabled
1 = Infrared endec is enabled
Received Data Interrupt Enable
0 = Received data and errors
generate
interrupt requests
1 = Only errors generate interrupt
requests. Received data does
not.
UART0 Baud Rate Generator High Byte
U0BRH (F46H - Read/Write)
Baud Rate Registers Control
Refer to UART chapter for operation
UART0 Baud Rate Generator Low Byte
U0BRL (F47H - Read/Write)
Driver Enable Polarity
0 = DE signal is active High
1 = DE signal is active Low
D7 D6 D5 D4 D3 D2 D1 D0
Multiprocessor Bit Transmit
0 = Send a 0 as the multiprocessor
bit
1 = Send a 1 as the multiprocessor
bit
D7 D6 D5 D4 D3 D2 D1 D0
UART0 Baud Rate divisor [15:8]
UART0 Baud Rate divisor [7:0]
UART1 Transmit Data
U1TXD (F48H - Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Multiprocessor Mode [0]
See Multiprocessor Mode [1] below
Multiprocessor (9-bit) Enable
0 = Multiprocessor mode is disabled
1 = Multiprocessor mode is enabled
Multiprocessor Mode [1]
with Multiprocess Mode bit 0:
00 = Interrupt on all received bytes
01 = Interrupt only on address bytes
10 = Interrupt on address match and
following data
11 = Interrupt on data following an
address match
UART1 transmitter data byte[7:0]
UART1 Receive Data
U1RXD (F48H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
UART receiver data byte [7:0]
UART0 Status 1
U0STAT1 (F44H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Mulitprocessor Receive
Returns value of last multiprocessor
bit
New Frame
0 = Current byte is not start of frame
1 = Current byte is start of new
frame
Reserved
PS019919-1207
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
33
UART1 Status 0
U1STAT0 (F49H - Read Only)
UART1 Control 0
U1CTL0 (F4AH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CTS signal
Returns the level of the CTS signal
Transmitter Empty
0 = Data is currently transmitting
1 = Transmission is complete
Transmitter Data Register Empty
0 = Transmit Data Register is full
1 = Transmit Data register is empty
Break Detect
0 = No break occurred
1 = A break occurred
Framing Error
0 = No framing error occurred
1 = A framing occurred
Overrun Error
0 = No overrun error occurred
1 = An overrun error occurred
Parity Error
0 = No parity error occurred
1 = A parity error occurred
Receive Data Available
0 = Receive Data Register is empty
1 = A byte is available in the Receive
Data Register
Loop Back Enable
0 = Normal operation
1 = Transmit data is looped back to
the receiver
Stop Bit Select
0 = Transmitter sends 1 Stop bit
1 = Transmitter sends 2 Stop bits
Send Break
0 = No break is sent
1 = Output of the transmitter is zero
Parity Select
0 = Even parity
1 = Odd parity
Parity Enable
0 = Parity is disabled
1 = Parity is enabled
CTS Enable
0 = CTS signal has no effect on the
transmitter
1 = UART recognizes CTS signal as
a
transmit enable control signal
Receive Enable
0 = Receiver disabled
1 = Receiver enabled
Transmit Enable
0 = Transmitter disabled
1 = Transmitter enabled
PS019919-1207
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
34
UART1 Control 1
U0CTL1 (F4BH - Read/Write)
UART1 Address Compare
U0ADDR (F4DH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
UART1 Address Compare [7:0]
Infrared Encoder/Decoder Enable
0 = Infrared endec is disabled
1 = Infrared endec is enabled
Received Data Interrupt Enable
0 = Received data and errors
generate
interrupt requests
1 = Only errors generate interrupt
requests. Received data does
not.
UART1 Baud Rate Generator High Byte
U0BRH (F4EH - Read/Write)
Baud Rate Registers Control
Refer to UART chapter for operation
UART1 Baud Rate Generator Low Byte
U1BRL (F4FH - Read/Write)
Driver Enable Polarity
0 = DE signal is active High
1 = DE signal is active Low
D7 D6 D5 D4 D3 D2 D1 D0
Multiprocessor Bit Transmit
0 = Send a 0 as the multiprocessor
bit
1 = Send a 1 as the multiprocessor
bit
Multiprocessor Mode [0]
See Multiprocessor Mode [1] below
D7 D6 D5 D4 D3 D2 D1 D0
UART1 Baud Rate divisor [15:8]
UART1 Baud Rate divisor [7:0]
I2C Data
I2CDATA (F50H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
I2C data [7:0]
Multiprocessor (9-bit) Enable
0 = Multiprocessor mode is disabled
1 = Multiprocessor mode is enabled
Multiprocessor Mode [1]
with Multiprocess Mode bit 0:
00 = Interrupt on all received bytes
01 = Interrupt only on address bytes
10 = Interrupt on address match and
following data
11 = Interrupt on data following an
address match
UART1 Status 1
U0STAT1 (F4CH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Mulitprocessor Receive
Returns value of last multiprocessor
bit
New Frame
0 = Current byte is not start of frame
1 = Current byte is start of new
frame
Reserved
PS019919-1207
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
35
I2C Status
I2CSTAT (F51H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
NACK Interrupt
0 = No action required to service
NAK
1 = START/STOP not set after NAK
I2C Control
I2CCTL (F52H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
I2C Signal Filter Enable
0 = Digital filtering disabled
1 = Low-pass digital filters enabled
on SDA and SCL input signals
Data Shift State
0 = Data is not being transferred
1 = Data is being transferred
Flush Data
0 = No effect
1 = Clears I2C Data register
Transmit Address State
0 = Address is not being transferred
1 = Address is being transferred
Send NAK
0 = Do not send NAK
1 = Send NAK after next byte
received
from slave
Read
0 = Write operation
1 = Read operation
Enable TDRE Interrupts
0 = Do not generate an interrupt
when
the I2C Data register is empty
1 = Generate an interrupt when the
I2C
Transmit Data register is empty
10-Bit Address
0 = 7-bit address being transmitted
1 = 10-bit address being transmitted
Acknowledge
0 = Acknowledge not
transmitted/received
1 = For last byte, Acknowledge was
transmitted/received
Baud Rate Generator Interrupt
0 = Interrupts behave as set by I2C
control
1 = BRG generates an interrupt
when
it counts down to zero
Receive Data Register Full
0 = I2C has not received data
1 = Data register contains received
data
Send Stop Condition
0 = Do not issue Stop condition after
data transmission is complete
1 = Issue Stop condition after data
transmission is complete
Transmit Data Register Empty
0 = Data register is full
1 = Data register is empty
Send Start Condition
0 = Do not send Start Condition
1 = Send Start Condition
I2C Enable
0 = I2C is disabled
1 = I2C is enabled
I2C Baud Rate Generator High Byte
I2CBRH (F53H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
I2C Baud Rate divisor [15:8]
I2C Baud Rate Generator Low Byte
I2CBRL (F54H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
I2C Baud Rate divisor [7:0]
PS019919-1207
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
36
SPI Data
SPIDATA (F60H - Read/Write)
SPI Status
SPISTAT (F62H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SPI Data [7:0]
Slave Select
0 = If Slave, SS pin is asserted
1 = If Slave, SS pin is not asserted
SPI Control
SPICTL (F61H - Read/Write)
Transmit Status
0 = No data transmission in progress
1 = Data transmission now in
progress
D7 D6 D5 D4 D3 D2 D1 D0
SPI Enable
0 = SPI disabled
1 = SPI enabled
Reserved
Slave Mode Transaction Abort
0 = No slave mode transaction abort
detected
1 = Slave mode transaction abort
was
detected
Master Mode Enabled
0 = SPI configured in Slave mode
1 = SPI configured in Master mode
Wire-OR (open-drain) Mode
0 = SPI signals not configured for
open-drain
1 = SPI signals (SCK, SS, MISO,
and
MOSI) configured for opendrain
Clock Polarity
0 = SCK idles Low
1 = SPI idles High
Overrun
0 = No overrun error detected
1 = Overrun error was detected
Phase Select
Sets the phase relationship of the
data
to the clock.
Interrupt Request
0 = No SPI interrupt request pending
1 = SPI interrupt request is pending
BRG Timer Interrupt Request
0 = BRG timer function is disabled
1 = BRG time-out interrupt is
enabled
PS019919-1207
Collision
0 = No multi-master collision
detected
1 = Multi-master collision was
detected
SPI Mode
SPIMODE (F63H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Start an SPI Interrupt Request
0 = No effect
1 = Generate an SPI interrupt
request
Slave Select Value
If Master and SPIMODE[1] = 1:
0 = SS pin driven Low
1 = SS pin driven High
Interrupt Request Enable
0 = SPI interrupt requests are
disabled
1 = SPI interrupt requests are
enabled
Slave Select I/O
0 = SS pin configured as an input
1 = SS pin configured as an output
(Master mode only)
Number of Data Bits Per Character
000 = 8 bits
001 = 1 bit
010 = 2 bits
011 = 3 bits
100 = 4 bits
101 = 5 bit
110 = 6 bits
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
37
SPI Mode
SPIMODE (F63H - Read/Write)
ADC Control
ADCCTL (F70H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
111 = 7 bits
Analog Input Select
0000 = ANA0
0001 = ANA1
0010 = ANA2
0011 = ANA3
0100 = ANA4
0101 = ANA5
0110 = ANA6
0111 = ANA7
1000 = ANA8
1001 = ANA9
1010 = ANA10 1011 = ANA11
11xx = Reserved
Diagnostic Mode Control
0 = Reading from SPIBRH, SPIBRL
returns reload values
1 = Reading from SPIBRH, SPIBRL
returns current BRG count value
Reserved
Continuous Mode Select
0 = Single-shot conversion
1 = Continuous conversion
SPI Diagnostic State
SPIDST (F64H - Read Only)
External VREF select
0 = Internal voltage reference
selected
1 = External voltage reference
selected
D7 D6 D5 D4 D3 D2 D1 D0
SPI State
Transmit Clock Enable
0 = Internal transmit clock enable
signal is deasserted
1 = Internal transmit clock enable
signal is asserted
Shift Clock Enable
0 = Internal shift clock enable signal
is deasserted
1 = Internal shift clock enable signal
is asserted
Reserved
Conversion Enable
0 = Conversion is complete
1 = Begin conversion
ADC Data High Byte
ADCD_H (F72H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
SPI Baud Rate Generator High Byte
SPIBRH (F66H - Read/Write)
ADC Data [9:2]
D7 D6 D5 D4 D3 D2 D1 D0
SPI Baud Rate divisor [15:8]
ADC Data Low Bits
ADCD_L (F73H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
SPI Baud Rate Generator Low Byte
SPIBRL (F67H - Read/Write)
Reserved
D7 D6 D5 D4 D3 D2 D1 D0
ADC Data [1:0]
SPI Baud Rate divisor [7:0]
PS019919-1207
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
38
DMA0 Control
DMA0CTL (FB0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Request Trigger Source Select
000 = Timer 0
001 = Timer 1
010 = Timer 2
011 = Timer 3
100 = UART0 Received Data
register
contains valid data
101 = UART1 Received Data
register
contains valid data
110 = I2C receiver contains valid
data
111 = Reserved
Word Select
0 = DMA transfers 1 byte per
request
1 = DMA transfers 2 bytes per
request
DMA0 Interrupt Enable
0 = DMA0 does not generate
interrupts
1 = DMA0 generates an interrupt
when
End Address data is transferred
DMA0 Address High Nibble
DMA0H (FB2H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 Start Address [11:8]
DMA0 End Address [11:8]
DMA0 Start/Current Address Low Byte
DMA0START (FB3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 Start Address [7:0]
DMA0 End Address Low Byte
DMA0END (FB4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 End Address [7:0]
DMA0 Data Transfer Direction
0 = Register File to peripheral
registers
1 = Peripheral registers to Register
File
DMA0 Loop Enable
0 = DMA disables after End Address
1 = DMA reloads Start Address after
End Address and continues to
run
DMA0 Enable
0 = DMA0 is disabled
1 = DMA0 is enabled
DMA0 I/O Address
DMA0IO (FB1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 Peripheral Register Address
Low byte of on-chip peripheral
control
registers on Register File page FH
PS019919-1207
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
39
DMA1 Control
DMA1CTL (FB8H - Read/Write)
DMA1 Address High Nibble
DMA1H (FBAH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Request Trigger Source Select
000 = Timer 0
001 = Timer 1
010 = Timer 2
011 = Timer 3
100 = UART0 Transmit Data register
is empty
101 = UART1 Transmit Data register
is empty
110 = I2C Transmit Data register
is empty
111 = Reserved
Word Select
0 = DMA transfers 1 byte per
request
1 = DMA transfers 2 bytes per
request
DMA1 Interrupt Enable
0 = DMA1 does not generate
interrupts
1 = DMA1 generates an interrupt
when
End Address data is transferred
DMA1 Data Transfer Direction
0 = Register File to peripheral
registers
1 = Peripheral registers to Register
File
DMA1 Start Address [11:8]
DMA1 End Address [11:8]
DMA1 Start/Current Address Low Byte
DMA1START (FBBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA1 Start Address [7:0]
DMA1 End Address Low Byte
DMA1END (FBCH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA1 End Address [7:0]
DMA_ADC Address
DMAA_ADDR (FBDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
DMA_ADC Address
DMA1 Loop Enable
0 = DMA disables after End Address
1 = DMA reloads Start Address after
End Address and continues to
run
DMA1 Enable
0 = DMA1 is disabled
1 = DMA1 is enabled
DMA1 I/O Address
DMA1IO (FB9H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA1 Peripheral Register Address
Low byte of on-chip peripheral
control
registers on Register File page FH
PS019919-1207
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
40
DMA_ADC Control
DMAACTL (FBEH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Request 0
IRQ0 (FC0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
ADC Analog Input Number
0000 = Analog input 0 updated
0001 = Analog input 0-1 updated
0010 = Analog input 0-2 updated
0011 = Analog input 0-3 updated
0100 = Analog input 0-4 updated
0101 = Analog input 0-5 updated
0100 = Analog input 0-6 updated
0101 = Analog input 0-7 updated
1000 = Analog input 0-8 updated
1001 = Analog input 0-9 updated
1010 = Analog input 0-10 updated
1011 = Analog inputs 0-11 updated
11xx = Reserved
ADC Interrupt Request
Reserved
Timer 2 Interrupt Request
Interrupt request enable
0 = DMA_ADC does not generate
interrupt requests
1 = DMA_ADC generates interrupt
requests after last analog input
For all of the above peripherals:
0 = Peripheral IRQ is not pending
1 = Peripheral IRQ is awaiting
service
DMA_ADC Enable
0 = DMA_ADC is disabled
1 = DMA_ADC is enabled
SPI Interrupt Request
I2C Interrupt Request
UART 0 Transmitter Interrupt
UART 0 Receiver Interrupt Request
Timer 0 Interrupt Request
Timer 1 Interrupt Request
IRQ0 Enable High Bit
IRQ0ENH (FC1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA Status
DMAA_STAT (FBFH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
ADC IRQ Enable Hit Bit
SPI IRQ Enable High Bit
I2C IRQ Enable High Bit
DMA0 Interrupt Request Indicator
0 = DMA0 is not the source of the
IRQ
1 = DMA0 is the source of the IRQ
DMA1 Interrupt Request Indicator
0 = DMA1 is not the source of the
IRQ
1 = DMA1 is the source of the IRQ
UART 0 Transmitter IRQ Enable
UART 0 Receiver IRQ Enable High
Timer 0 IRQ Enable High Bit
Timer 1 IRQ Enable High Bit
Timer 2 IRQ Enable High Bit
DMA_ADC Interrupt Request
0 = DMA_ADC is not the source of
the
IRQ
1 = DMA_ADC is the source of the
IRQ
Reserved
Current ADC analog input
Identifies the analog input the ADC
is
currently converting
PS019919-1207
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
41
IRQ0 Enable Low Bit
IRQ0ENL (FC2H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Request 2
IRQ2 (FC6H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
I2C IRQ Enable Low Bit
Port C Pin Interrupt Request
0 = IRQ from corresponding pin [3:0]
is not pending
1 = IRQ from corresponding pin [3:0]
is awaiting service
UART 0 Transmitter IRQ Enable
DMA Interrupt Request
UART 0 Receiver IRQ Enable Low
UART 1 Transmitter Interrupt
Timer 0 IRQ Enable Low Bit
UART 1 Receiver Interrupt Request
Timer 1 IRQ Enable Low Bit
Timer 3 Interrupt Request
Timer 2 IRQ Enable Low Bit
For all of the above peripherals:
0 = Peripheral IRQ is not pending
1 = Peripheral IRQ is awaiting
service
ADC IRQ Enable Hit Bit
SPI IRQ Enable Low Bit
Interrupt Request 1
IRQ1 (FC3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A or D Pin Interrupt Request
0 = IRQ from corresponding pin [7:0]
is not pending
1 = IRQ from corresponding pin [7:0]
is awaiting service
IRQ2 Enable High Bit
IRQ2ENH (FC7H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Pin IRQ Enable High Bit
DMA IRQ Enable High Bit
UART 1 Transmitter IRQ Enable
IRQ1 Enable High Bit
IRQ1ENH (FC4H - Read/Write)
UART 1 Receiver IRQ Enable High
D7 D6 D5 D4 D3 D2 D1 D0
Timer 3 IRQ Enable High Bit
Port A or D Pin IRQ Enable High Bit
IRQ1 Enable Low Bit
IRQ1ENL (FC5H - Read/Write)
IRQ2 Enable Low Bit
IRQ2ENL (FC8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Port C Pin IRQ Enable Low Bit
Port A or D Pin IRQ Enable Low Bit
DMA IRQ Enable Low Bit
UART 1 Transmitter IRQ Enable
UART 1 Receiver IRQ Enable Low
Timer 3 IRQ Enable Low Bit
Interrupt Edge Select
IRQES (FCDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A or D Interrupt Edge Select
0 = Falling edge
1 = Rising edge
PS019919-1207
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
42
Interrupt Port Select
IRQPS (FCEH - Read/Write)
Port B Address
PBADDR (FD4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Port A or D Port Pin Select [7:0]
0 = Port A pin is the interrupt source
1 = Port D pin is the interrupt source
Port B Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = Stop Mode Recovery enable
06H-FFH = No function
Interrupt Control
IRQCTL (FCFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Interrupt Request Enable
0 = Interrupts are disabled
1 = Interrupts are enabled
Port B Control
PBCTL (FD5H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port B Control[7:0]
Provides Access to Port SubRegisters
Port A Address
PAADDR (FD0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = Stop Mode Recovery enable
06H-FFH = No function
Port A Control
PACTL (FD1H - Read/Write)
Port B Input Data
PBIN (FD6H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port B Input Data [7:0]
Port B Output Data
PBOUT (FD7H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port B Output Data [7:0]
D7 D6 D5 D4 D3 D2 D1 D0
Port A Control[7:0]
Provides Access to Port SubRegisters
Port A Input Data
PAIN (FD2H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Input Data [7:0]
Port C Address
PCADDR (FD8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = Stop Mode Recovery enable
06H-FFH = No function
Port A Output Data
PAOUT (FD3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Output Data [7:0]
PS019919-1207
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
43
Port C Control
PCCTL (FD9H - Read/Write)
Port D Output Data
PDOUT (FDFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Port C Control[7:0]
Provides Access to Port SubRegisters
Port C Input Data
PCIN (FDAH - Read Only)
Port D Output Data [7:0]
Port E Address
PEADDR (FE0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port E Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = Stop Mode Recovery enable
06H-FFH = No function
D7 D6 D5 D4 D3 D2 D1 D0
Port C Input Data [7:0]
Port C Output Data
PCOUT (FDBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Output Data [7:0]
Port D Address
PDADDR (FDCH - Read/Write)
Port E Control
PECTL (FE1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port E Control[7:0]
Provides Access to Port SubRegisters
D7 D6 D5 D4 D3 D2 D1 D0
Port D Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = Stop Mode Recovery enable
06H-FFH = No function
Port E Input Data
PEIN (FE2H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port E Input Data [7:0]
Port D Control
PDCTL (FDDH - Read/Write)
Port E Output Data
PEOUT (FE3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Port D Control[7:0]
Provides Access to Port SubRegisters
Port D Input Data
PDIN (FDE H- Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port D Input Data [7:0]
PS019919-1207
Port E Output Data [7:0]
Port F Address
PFADDR (FE4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port F Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = Stop Mode Recovery enable
06H-FFH = No function
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
44
Port F Control
PFCTL (FE5H - Read/Write)
Port G Output Data
PGOUT (FEBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Port F Control[7:0]
Provides Access to Port SubRegisters
Port F Input Data
PFIN (FE6H - Read Only)
Port G Output Data [7:0]
Port H Address
PHADDR (FECH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port H Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = Stop Mode Recovery enable
06H-FFH = No function
D7 D6 D5 D4 D3 D2 D1 D0
Port F Input Data [7:0]
Port F Output Data
PFOUT (FE7H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port F Output Data [7:0]
Port G Address
PGADDR (FE8H - Read/Write)
Port H Control
PHCTL (FEDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port H Control [3:0]
Provides Access to Port SubRegisters
D7 D6 D5 D4 D3 D2 D1 D0
Port G Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = Stop Mode Recovery enable
06H-FFH = No function
Reserved
Port H Input Data
PHIN (FEEH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port H Input Data [3:0]
Port G Control
PGCTL (FE9H - Read/Write)
Reserved
D7 D6 D5 D4 D3 D2 D1 D0
Port G Control[7:0]
Provides Access to Port SubRegisters
Port H Output Data
PHOUT (FEFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port H Output Data [3:0]
Port G Input Data
PGIN (FEAH - Read Only)
Reserved
D7 D6 D5 D4 D3 D2 D1 D0
Port G Input Data [7:0]
PS019919-1207
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
45
Watchdog Timer Control
WDTCTL (FF0H - Read Only)
Flash Status
FSTAT (FF8H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SM Configuration Indicator
Reserved
EXT
0 = Reset not generated by RESET
pin
1 = Reset generated by RESET pin
Flash Controller Status
00_0000 = Flash controller locked
00_0001 = First unlock received
00_0010 = Second unlock received
00_0011 = Flash controller unlocked
00_0100 = Flash Sector Protect
register
selected
00_1xxx = Programming in progress
01_0xxx = Page erase in progress
10_0xxx = Mass erase in progress
WDT
0 = WDT timeout has not occurred
1 = WDT timeout occurred
STOP
0 = SMR has not occurred
1 = SMR has occurred
POR
0 = POR has not occurred
1 = POR has occurred
Reserved
Page Select
FPS (FF9H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Watchdog Timer Reload Upper Byte
WDTU (FF1H - Read/Write)
Page Select [6:0]
Identifies the Flash memory page for
Page Erase operation.
D7 D6 D5 D4 D3 D2 D1 D0
Information Area Enable
0 = Information Area access is
disabled
1 = Information Area access is
enabled
WDT reload value [23:16]
Watchdog Timer Reload Middle Byte
WDTH (FF2 H- Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
WDT reload value [15:8]
Flash Sector Protect
FPROT (FF9H - Read/Write to 1’s)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Sector Protect [7:0]
0 = Sector can be programmed or
erased from user code
1 = Sector is protected and cannot
be
programmed or erased from
user
code
Watchdog Timer Reload Low Byte
WDTL (FF3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
WDT reload value [7:0]
Flash Control
FCTL (FF8H - Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Command
73H = First unlock command
8CH = Second unlock command
95H = Page erase command
63H = Mass erase command
5EH = Flash Sector Protect reg
select
Flash Frequency High Byte
FFREQH (FFAH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Frequency value [15:8]
Flash Frequency Low Byte
FFREQL (FFBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Frequency value [7:0]
PS019919-1207
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
46
Flags
FLAGS (FFC - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
F1 - User Flag 1
F2 - User Flag 2
H - Half Carry
D - Decimal Adjust
V - Overflow Flag
S - Sign Flag
Z - Zero Flag
C - Carry Flag
Register Pointer
RP (FFDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Working Register Page Address
Working Register Group Address
Stack Pointer High Byte
SPH (FFEH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer [15:8]
Stack Pointer Low Byte
SPL (FFFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer [7:0]
PS019919-1207
Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
47
Reset and Stop Mode Recovery
Overview
The Reset Controller within the Z8 Encore! XP 64K Series Flash Microcontrollers controls Reset and Stop Mode Recovery operation. In typical operation, the following events
cause a Reset to occur:
•
•
•
Power-On Reset
•
•
External RESET pin assertion
Voltage Brownout
Watchdog Timer time-out (when configured via the WDT_RES Option Bit to initiate
a Reset)
On-Chip Debugger initiated Reset (OCDCTL[0] set to 1)
When the 64K Series devices are in STOP mode, a Stop Mode Recovery is initiated by
either of the following:
•
•
•
Watchdog Timer time-out
GPIO Port input pin transition on an enabled Stop Mode Recovery source
DBG pin driven Low
Reset Types
The 64K Series provides two different types of reset operation (system reset and Stop
Mode Recovery). The type of Reset is a function of both the current operating mode of the
64K Series devices and the source of the Reset. Table 8 lists the types of Reset and their
operating characteristics.
PS019919-1207
Reset and Stop Mode Recovery
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
48
Table 8. Reset and Stop Mode Recovery Characteristics and Latency
Reset Characteristics and Latency
eZ8™ CPU Reset Latency (Delay)
Reset Type
Control Registers
System reset
Reset (as applicable) Reset
66 WDT Oscillator cycles + 16 System Clock cycles
Stop Mode
Recovery
Unaffected, except
WDT_CTL register
66 WDT Oscillator cycles + 16 System Clock cycles
Reset
System Reset
During a system reset, the 64K Series devices are held in Reset for 66 cycles of the
Watchdog Timer oscillator followed by 16 cycles of the system clock. At the beginning of
Reset, all GPIO pins are configured as inputs.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watchdog Timer oscillator continue to run. The system clock begins
operating following the Watchdog Timer oscillator cycle count. The eZ8 CPU and on-chip
peripherals remain idle through the 16 cycles of the system clock.
Upon Reset, control registers within the Register File that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer,
Register Pointer, and Flags) and general-purpose RAM are undefined following Reset.
The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H
and loads that value into the Program Counter. Program execution begins at the Reset
vector address.
Reset Sources
Table 9 lists the reset sources as a function of the operating mode. The text following provides more detailed information on the individual Reset sources. A Power-On Reset/Voltage Brownout event always takes priority over all other possible reset sources to ensure a
full system reset occurs.
PS019919-1207
Reset and Stop Mode Recovery
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
49
Table 9. Reset Sources and Resulting Reset Type
Operating Mode
Reset Source
Reset Type
NORMAL or HALT
modes
Power-On Reset/Voltage
Brownout
system reset
Watchdog Timer time-out
when configured for Reset
system reset
RESET pin assertion
system reset
On-Chip Debugger initiated Reset system reset except the On-Chip Debugger is
(OCDCTL[0] set to 1)
unaffected by the reset
STOP mode
Power-On Reset/Voltage
Brownout
system reset
RESET pin assertion
system reset
DBG pin driven Low
system reset
Power-On Reset
Each device in the 64K Series contains an internal Power-On Reset circuit. The POR circuit monitors the supply voltage and holds the device in the Reset state until the supply
voltage reaches a safe operating level. After the supply voltage exceeds the POR voltage
threshold (VPOR), the POR Counter is enabled and counts 66 cycles of the Watchdog
Timer oscillator. After the POR counter times out, the XTAL Counter is enabled to count a
total of 16 system clock pulses. The devices are held in the Reset state until both the POR
Counter and XTAL counter have timed out. After the 64K Series devices exit the PowerOn Reset state, the eZ8 CPU fetches the Reset vector. Following Power-On Reset, the
POR status bit in the Watchdog Timer Control (WDTCTL) register is set to 1.
Figure 8 displays Power-On Reset operation. For the POR threshold voltage (VPOR), see
Electrical Characteristics on page 215.
PS019919-1207
Reset and Stop Mode Recovery
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
50
VCC = 3.3 V
VPOR
VVBO
Program
Execution
VCC = 0.0 V
WDT Clock
Primary
Oscillator
Internal RESET
signal
Oscillator
Start-up
POR
counter delay
Not to Scale
XTAL
counter delay
Figure 8. Power-On Reset Operation
Voltage Brownout Reset
The devices in the 64K Series provide low Voltage Brownout protection. The VBO circuit
senses when the supply voltage drops to an unsafe level (below the VBO threshold
voltage) and forces the device into the Reset state. While the supply voltage remains
below the Power-On Reset voltage threshold (VPOR), the VBO block holds the device in
the Reset state.
After the supply voltage again exceeds the Power-On Reset voltage threshold, the devices
progress through a full system reset sequence, as described in the Power-On Reset section.
Following Power-On Reset, the POR status bit in the Watchdog Timer Control
(WDTCTL) register is set to 1. Figure 9 displays Voltage Brownout operation. For the
VBO and POR threshold voltages (VVBO and VPOR), see Electrical Characteristics on
page 215.
The Voltage Brownout circuit can be either enabled or disabled during STOP mode. Operation during STOP mode is set by the VBO_AO Option Bit. For information on configuring
VBO_AO, see Option Bits page 195.
PS019919-1207
Reset and Stop Mode Recovery
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
51
VCC = 3.3 V
VCC = 3.3 V
VPOR
VVBO
Program
Execution
Voltage
Brownout
Program
Execution
WDT Clock
Primary
Oscillator
Internal RESET
Signal
POR
Counter Delay
XTAL
Counter Delay
Figure 9. Voltage Brownout Reset Operation
Watchdog Timer Reset
If the device is in normal or HALT mode, the Watchdog Timer can initiate a system reset
at time-out if the WDT_RES Option Bit is set to 1. This capability is the default
(unprogrammed) setting of the WDT_RES Option Bit. The WDT status bit in the WDT
Control register is set to signify that the reset was initiated by the Watchdog Timer.
External Pin Reset
The RESET pin has a Schmitt-triggered input, an internal pull-up, an analog filter and a
digital filter to reject noise. Once the RESET pin is asserted for at least 4 system clock
cycles, the devices progress through the system reset sequence. While the RESET input
pin is asserted Low, the 64K Series devices continue to be held in the Reset state. If the
RESET pin is held Low beyond the system reset time-out, the devices exit the Reset state
immediately following RESET pin deassertion. Following a system reset initiated by the
external RESET pin, the EXT status bit in the Watchdog Timer Control (WDTCTL) register is set to 1.
PS019919-1207
Reset and Stop Mode Recovery
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
52
On-Chip Debugger Initiated Reset
A Power-On Reset can be initiated using the On-Chip Debugger by setting the RST bit in
the OCD Control register. The On-Chip Debugger block is not reset but the rest of the chip
goes through a normal system reset. The RST bit automatically clears during the system
reset. Following the system reset the POR bit in the WDT Control register is set.
Stop Mode Recovery
STOP mode is entered by the eZ8 executing a STOP instruction. For detailed STOP mode
information, see Low-Power Modes on page 47. During Stop Mode Recovery, the devices
are held in reset for 66 cycles of the Watchdog Timer oscillator followed by 16 cycles of
the system clock. Stop Mode Recovery only affects the contents of the Watchdog Timer
Control register. Stop Mode Recovery does not affect any other values in the Register File,
including the Stack Pointer, Register Pointer, Flags, peripheral control registers, and
general-purpose RAM.
The eZ8™ CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H
and loads that value into the Program Counter. Program execution begins at the Reset
vector address. Following Stop Mode Recovery, the STOP bit in the Watchdog Timer
Control Register is set to 1. Table 10 lists the Stop Mode Recovery sources and resulting
actions.
Table 10. Stop Mode Recovery Sources and Resulting Action
Operating Mode
Stop Mode Recovery Source
Action
STOP mode
Watchdog Timer time-out
when configured for Reset
Stop Mode Recovery
Watchdog Timer time-out
when configured for interrupt
Stop Mode Recovery followed by interrupt
(if interrupts are enabled)
Data transition on any GPIO Port pin
enabled as a Stop Mode Recovery
source
Stop Mode Recovery
Stop Mode Recovery Using Watchdog Timer Time-Out
If the Watchdog Timer times out during STOP mode, the device undergoes a Stop Mode
Recovery sequence. In the Watchdog Timer Control register, the WDT and STOP bits are
set to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and
the 64K Series devices are configured to respond to interrupts, the eZ8 CPU services the
Watchdog Timer interrupt request following the normal Stop Mode Recovery sequence.
PS019919-1207
Reset and Stop Mode Recovery
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
53
Stop Mode Recovery Using a GPIO Port Pin Transition HALT
Each of the GPIO Port pins may be configured as a Stop Mode Recovery input source. On
any GPIO pin enabled as a Stop Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery. The GPIO Stop
Mode Recovery signals are filtered to reject pulses less than 10 ns (typical) in duration. In
the Watchdog Timer Control register, the STOP bit is set to 1.
Caution: In STOP mode, the GPIO Port Input Data registers (PxIN) are disabled. The
Port Input Data registers record the Port transition only if the signal stays on
the Port pin through the end of the Stop Mode Recovery delay. Thus, short pulses on the Port pin can initiate Stop Mode Recovery without being written to the
Port Input Data register or without initiating an interrupt (if enabled for that
pin).
PS019919-1207
Reset and Stop Mode Recovery
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
54
PS019919-1207
Reset and Stop Mode Recovery
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
55
Low-Power Modes
Overview
The 64K Series products contain power-saving features. The highest level of power reduction is provided by STOP mode. The next level of power reduction is provided by the
HALT mode.
STOP Mode
Execution of the eZ8™ CPU’s STOP instruction places the device into STOP mode. In
STOP mode, the operating characteristics are:
•
Primary crystal oscillator is stopped; the XIN pin is driven High and the XOUT pin is
driven Low.
•
•
•
•
System clock is stopped.
•
The Voltage Brownout protection circuit continues to operate, if enabled for operation
in STOP mode using the associated Option Bit.
•
All other on-chip peripherals are idle.
eZ8 CPU is stopped.
Program counter (PC) stops incrementing.
The Watchdog Timer and its internal RC oscillator continue to operate, if enabled for
operation during STOP mode.
To minimize current in STOP mode, all GPIO pins that are configured as digital inputs
must be driven to one of the supply rails (VCC or GND), the Voltage Brownout protection
must be disabled, and the Watchdog Timer must be disabled. The devices can be brought
out of STOP mode using Stop Mode Recovery. For more information on Stop Mode
Recovery, see Reset and Stop Mode Recovery on page 47.
Caution: STOP mode must not be used when driving the 64K Series devices with an
external clock driver source.
PS019919-1207
Low-Power Modes
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
56
HALT Mode
Execution of the eZ8 CPU’s HALT instruction places the device into HALT mode. In
HALT mode, the operating characteristics are:
•
•
•
•
•
•
•
Primary crystal oscillator is enabled and continues to operate.
System clock is enabled and continues to operate.
eZ8 CPU is stopped.
Program Counter stops incrementing.
Watchdog Timer’s internal RC oscillator continues to operate.
The Watchdog Timer continues to operate, if enabled.
All other on-chip peripherals continue to operate.
The eZ8 CPU can be brought out of HALT mode by any of the following operations:
•
•
•
•
•
Interrupt
Watchdog Timer time-out (interrupt or reset)
Power-On Reset
Voltage Brownout Reset
External RESET pin assertion
To minimize current in HALT mode, all GPIO pins which are configured as inputs must be
driven to one of the supply rails (VCC or GND).
PS019919-1207
Low-Power Modes
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
57
General-Purpose I/O
Overview
The 64K Series products support a maximum of seven 8-bit ports (Ports A–G) and
one 4-bit port (Port H) for general-purpose input/output (GPIO) operations. Each port consists of control and data registers. The GPIO control registers are used to determine data
direction, open-drain, output drive current and alternate pin functions. Each port pin is
individually programmable. All ports (except B and H) support 5 V-tolerant inputs.
GPIO Port Availability By Device
Table 11 lists the port pins available with each device and package type.
Table 11. Port Availability by Device and Package Type
Device
Packages
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Port H
Z8X1621
40-pin
[7:0]
[7:0]
[6:0]
[6:3,
1:0]
-
-
-
-
Z8X1621
44-pin
[7:0]
[7:0]
[7:0]
[6:0]
-
-
-
-
Z8X1622
64- and 68-pin [7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7]
[3]
[3:0]
Z8X2421
40-pin
[7:0]
[7:0]
[6:0]
[6:3,
1:0]
-
-
-
-
Z8X2421
44-pin
[7:0]
[7:0]
[7:0]
[6:0]
-
-
-
-
Z8X2422
64- and 68-pin [7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7]
[3]
[3:0]
Z8X3221
40-pin
[7:0]
[7:0]
[6:0]
[6:3,
1:0]
-
-
-
-
Z8X3221
44-pin
[7:0]
[7:0]
[7:0]
[6:0]
-
-
-
-
Z8X3222
64- and 68-pin [7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7]
[3]
[3:0]
Z8X4821
40-pin
[7:0]
[7:0]
[6:0]
[6:3,
1:0]
-
-
-
-
Z8X4821
44-pin
[7:0]
[7:0]
[7:0]
[6:0]
-
-
-
-
Z8X4822
64- and 68-pin [7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7]
[3]
[3:0]
PS019919-1207
General-Purpose I/O
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
58
Table 11. Port Availability by Device and Package Type (Continued)
Device
Packages
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Port H
Z8X4823
80-pin
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[3:0]
Z8X6421
40-pin
[7:0]
[7:0]
[6:0]
[6:3,
1:0]
-
-
-
-
Z8X6421
44-pin
[7:0]
[7:0]
[7:0]
[6:0]
-
-
-
-
Z8X6422
64- and 68-pin [7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7]
[3]
[3:0]
Z8X6423
80-pin
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[3:0]
[7:0]
Architecture
Figure 10 displays a simplified block diagram of a GPIO port pin. In Figure 10, the ability
to accommodate alternate functions and variable port current drive strength are not illustrated.
Port Input
Data Register
Q
Schmitt-Trigger
D
System
Clock
VDD
Port Output Control
Port Output
Data Register
DATA
Bus
D
Q
Port
Pin
System
Clock
Port Data Direction
GND
Figure 10. GPIO Port Pin Block Diagram
PS019919-1207
General-Purpose I/O
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
59
GPIO Alternate Functions
Many of the GPIO port pins can be used as both general-purpose I/O and to provide access
to on-chip peripheral functions such as the timers and serial communication devices. The
Port A–H Alternate Function sub-registers configure these pins for either general-purpose
I/O or alternate function operation. When a pin is configured for alternate function, control
of the port pin direction (input/output) is passed from the Port A–H Data Direction registers to the alternate function assigned to this pin. Table 12 lists the alternate functions
associated with each port pin.
Table 12. Port Alternate Function Mapping
Port
Pin
Mnemonic
Alternate Function Description
Port A
PA0
T0IN
Timer 0 Input
PA1
T0OUT
Timer 0 Output
PA2
DE0
UART 0 Driver Enable
PA3
CTS0
UART 0 Clear to Send
PA4
RXD0/IRRX0
UART 0/IrDA 0 Receive Data
PA5
TXD0/IRTX0
UART 0/IrDA 0 Transmit Data
PA6
SCL
I2C Clock (automatically open-drain)
PA7
SDA
I2C Data (automatically open-drain)
PB0
ANA0
ADC Analog Input 0
PB1
ANA1
ADC Analog Input 1
PB2
ANA2
ADC Analog Input 2
PB3
ANA3
ADC Analog Input 3
PB4
ANA4
ADC Analog Input 4
PB5
ANA5
ADC Analog Input 5
PB6
ANA6
ADC Analog Input 6
PB7
ANA7
ADC Analog Input 7
Port B
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Product Specification
60
Table 12. Port Alternate Function Mapping (Continued)
Port
Pin
Mnemonic
Alternate Function Description
Port C
PC0
T1IN
Timer 1 Input
PC1
T1OUT
Timer 1 Output
PC2
SS
SPI Slave Select
PC3
SCK
SPI Serial Clock
PC4
MOSI
SPI Master Out/Slave In
PC5
MISO
SPI Master In/Slave Out
PC6
T2IN
Timer 2 In
PC7
T2OUT
Timer 2 Out
PD0
T3IN
Timer 3 In (unavailable in 44-pin packages)
PD1
T3OUT
Timer 3 Out (unavailable in 44-pin packages)
PD2
N/A
No alternate function
PD3
DE1
UART 1 Driver Enable
PD4
RXD1/IRRX1
UART 1/IrDA 1 Receive Data
PD5
TXD1/IRTX1
UART 1/IrDA 1 Transmit Data
PD6
CTS1
UART 1 Clear to Send
PD7
RCOUT
Watchdog Timer RC Oscillator Output
Port D
Port E
PE[7:0] N/A
No alternate functions
Port F
PF[7:0] N/A
No alternate functions
Port G
PG[7:0] N/A
No alternate functions
Port H
PH0
ANA8
ADC Analog Input 8
PH1
ANA9
ADC Analog Input 9
PH2
ANA10
ADC Analog Input 10
PH3
ANA11
ADC Analog Input 11
GPIO Interrupts
Many of the GPIO port pins can be used as interrupt sources. Some port pins may be configured to generate an interrupt request on either the rising edge or falling edge of the pin
input signal. Other port pin interrupts generate an interrupt when any edge occurs (both
rising and falling). For more information on interrupts using the GPIO pins, see Interrupt
Controller on page 67.
PS019919-1207
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Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
61
GPIO Control Register Definitions
Four registers for each Port provide access to GPIO control, input data, and output data.
Table 13 lists these Port registers. Use the Port A–H Address and Control registers
together to provide access to sub-registers for Port configuration and control.
Table 13. GPIO Port Registers and Sub-Registers
Port Register Mnemonic
Port Register Name
PxADDR
Port A–H Address Register
(Selects sub-registers)
PxCTL
Port A–H Control Register
(Provides access to sub-registers)
PxIN
Port A–H Input Data Register
PxOUT
Port A–H Output Data Register
Port Sub-Register Mnemonic Port Register Name
PxDD
Data Direction
PxAF
Alternate Function
PxOC
Output Control (Open-Drain)
PxDD
High Drive Enable
PxSMRE
Stop Mode Recovery Source
Enable
Port A–H Address Registers
The Port A–H Address registers select the GPIO Port functionality accessible through the
Port A–H Control registers. The Port A–H Address and Control registers combine to provide access to all GPIO Port control (Table 14).
Table 14. Port A–H GPIO Address Registers (PxADDR)
BITS
7
6
5
4
3
FIELD
PADDR[7:0]
RESET
00H
R/W
R/W
ADDR
PS019919-1207
2
1
0
FD0H, FD4H, FD8H, FDCH, FE0H, FE4H, FE8H, FECH
General-Purpose I/O
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PADDR[7:0]—Port Address
The Port Address selects one of the sub-registers accessible through the Port Control register.
PADDR[7:0]
Port Control sub-register accessible using the Port A–H Control
Registers
00H
No function. Provides some protection against accidental Port
reconfiguration
01H
Data Direction
02H
Alternate Function
03H
Output Control (Open-Drain)
04H
High Drive Enable
05H
Stop Mode Recovery Source Enable
06H-FFH
No function
Port A–H Control Registers
The Port A–H Control registers set the GPIO port operation. The value in the corresponding Port A–H Address register determines the control sub-registers accessible using the
Port A–H Control register (Table 15).
Table 15. Port A–H Control Registers (PxCTL)
BITS
7
6
5
4
3
FIELD
PCTL
RESET
00H
R/W
R/W
ADDR
2
1
0
FD1H, FD5H, FD9H, FDDH, FE1H, FE5H, FE9H, FEDH
PCTL[7:0]—Port Control
The Port Control register provides access to all sub-registers that configure the GPIO Port
operation.
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Port A–H Data Direction Sub-Registers
The Port A–H Data Direction sub-register is accessed through the Port A–H Control register by writing 01H to the Port A–H Address register (Table 16).
Table 16. Port A–H Data Direction Sub-Registers
BITS
FIELD
7
6
5
4
3
2
1
0
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
1
RESET
R/W
R/W
If 01H in Port A–H Address Register, accessible through Port A–H Control Register
ADDR
DD[7:0]—Data Direction
These bits control the direction of the associated port pin. Port Alternate Function operation overrides the Data Direction register setting.
0 = Output. Data in the Port A–H Output Data register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A–H Input Data
Register. The output driver is tri-stated.
Port A–H Alternate Function Sub-Registers
The Port A–H Alternate Function sub-register (Table 17) is accessed through the
Port A–H Control register by writing 02H to the Port A–H Address register. The Port A–H
Alternate Function sub-registers select the alternate functions for the selected pins. To
determine the alternate function associated with each port pin, see GPIO Alternate Functions on page 59.
Caution: Do not enable alternate function for GPIO port pins which do not have an associated alternate function. Failure to follow this guideline may result in unpredictable operation.
Table 17. Port A–H Alternate Function Sub-Registers
BITS
FIELD
7
6
5
4
3
2
1
0
AF7
AF6
AF5
AF4
AF3
AF2
AF1
AF0
RESET
R/W
ADDR
PS019919-1207
0
R/W
If 02H in Port A–H Address Register, accessible through Port A–H Control Register
General-Purpose I/O
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AF[7:0]—Port Alternate Function enabled
0 = The port pin is in NORMAL mode and the DDx bit in the Port A–H Data Direction
sub-register determines the direction of the pin.
1 = The alternate function is selected. Port pin operation is controlled by the
alternate function.
Port A–H Output Control Sub-Registers
The Port A–H Output Control sub-register (Table 18) is accessed through the
Port A–H Control register by writing 03H to the Port A–H Address register. Setting the
bits in the Port A–H Output Control sub-registers to 1 configures the specified port pins
for open-drain operation. These sub-registers affect the pins directly and, as a result, alternate functions are also affected.
Table 18. Port A–H Output Control Sub-Registers
BITS
FIELD
7
6
5
4
3
2
1
0
POC7
POC6
POC5
POC4
POC3
POC2
POC1
POC0
RESET
R/W
ADDR
0
R/W
If 03H in Port A–H Address Register, accessible through Port A–H Control Register
POC[7:0]—Port Output Control
These bits function independently of the alternate function bit and disables the drains if set
to 1.
0 = The drains are enabled for any output mode.
1 = The drain of the associated pin is disabled (open-drain mode).
Port A–H High Drive Enable Sub-Registers
The Port A–H High Drive Enable sub-register (Table 19) is accessed through the Port A–
H Control register by writing 04H to the Port A–H Address register. Setting the bits in the
Port A–H High Drive Enable sub-registers to 1 configures the specified port pins for high
current output drive operation. The Port A–H High Drive Enable sub-register affects the
pins directly and, as a result, alternate functions are also affected.
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Table 19. Port A–H High Drive Enable Sub-Registers
BITS
FIELD
7
6
5
4
3
2
1
0
PHDE7
PHDE6
PHDE5
PHDE4
PHDE3
PHDE2
PHDE1
PHDE0
0
RESET
R/W
R/W
If 04H in Port A-H Address Register, accessible through Port A-H Control Register
ADDR
PHDE[7:0]—Port High Drive Enabled
0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Port A–H Stop Mode Recovery Source Enable Sub-Registers
The Port A–H Stop Mode Recovery Source Enable sub-register (Table 20) is accessed
through the Port A–H Control register by writing 05H to the Port A–H Address register.
Setting the bits in the Port A–H Stop Mode Recovery Source Enable sub-registers to 1
configures the specified Port pins as a Stop Mode Recovery source. During STOP Mode,
any logic transition on a Port pin enabled as a Stop Mode Recovery source initiates Stop
Mode Recovery.
Table 20. Port A–H Stop Mode Recovery Source Enable Sub-Registers
BITS
FIELD
7
6
5
4
3
2
1
0
PSMRE7
PSMRE6
PSMRE5
PSMRE4
PSMRE3
PSMRE2
PSMRE1
PSMRE0
RESET
R/W
ADDR
0
R/W
If 05H in Port A–H Address Register, accessible through Port A–H Control Register
PSMRE[7:0]—Port Stop Mode Recovery Source Enabled
0 = The Port pin is not configured as a Stop Mode Recovery source. Transitions on this
pin during STOP mode do not initiate Stop Mode Recovery.
1 = The Port pin is configured as a Stop Mode Recovery source. Any logic transition
on this pin during STOP mode initiates Stop Mode Recovery.
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General-Purpose I/O
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66
Port A–H Input Data Registers
Reading from the Port A–H Input Data registers (Table 21) returns the sampled values
from the corresponding port pins. The Port A–H Input Data registers are Read-only.
Table 21. Port A–H Input Data Registers (PxIN)
BITS
FIELD
7
6
5
4
3
2
1
0
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
RESET
X
R/W
R
FD2H, FD6H, FDAH, FDEH, FE2H, FE6H, FEAH, FEEH
ADDR
PIN[7:0]—Port Input Data
Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low).
1 = Input data is logical 1 (High).
Port A–H Output Data Register
The Port A–H Output Data register (Table 22) writes output data to the pins.
Table 22. Port A–H Output Data Register (PxOUT)
BITS
FIELD
7
6
5
4
3
2
1
0
POUT7
POUT6
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
RESET
R/W
ADDR
0
R/W
FD3H, FD7H, FDBH, FDFH, FE3H, FE7H, FEBH, FEFH
POUT[7:0]—Port Output Data
These bits contain the data to be driven out from the port pins. The values are only driven
if the corresponding pin is configured as an output and the pin is not configured for alternate function operation.
0 = Drive a logical 0 (Low).
1= Drive a logical 1 (High). High value is not driven if the drain has been disabled by
setting the corresponding Port Output Control register bit to 1.
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Interrupt Controller
Overview
The interrupt controller on the 64K Series products prioritizes the interrupt requests from
the on-chip peripherals and the GPIO port pins. The features of the interrupt controller
include the following:
•
24 unique interrupt vectors:
– 12 GPIO port pin interrupt sources
– 12 on-chip peripheral interrupt sources
•
Flexible GPIO interrupts
– Eight selectable rising and falling edge GPIO interrupts
– Four dual-edge interrupts
•
•
Three levels of individually programmable interrupt priority
Watchdog Timer can be configured to generate an interrupt
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt
service routine is involved with the exchange of data, status information, or control
information between the CPU and the interrupting peripheral. When the service routine is
completed, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt control has no effect on operation. For more information on interrupt
servicing by the eZ8 CPU, refer to eZ8™ CPU Core User Manual (UM0128) available for
download at www.zilog.com.
Interrupt Vector Listing
Table 23 lists all of the interrupts available in order of priority. The interrupt vector is
stored with the most-significant byte (MSB) at the even Program Memory address and the
least-significant byte (LSB) at the following odd Program Memory address.
PS019919-1207
Interrupt Controller
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
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Table 23. Interrupt Vectors in Order of Priority
Program Memory
Priority Vector Address
Interrupt Source
Highest 0002H
Lowest
PS019919-1207
Reset (not an interrupt)
0004H
Watchdog Timer (see Watchdog Timer on
page 97)
0006H
Illegal Instruction Trap (not an interrupt)
0008H
Timer 2
000AH
Timer 1
000CH
Timer 0
000EH
UART 0 receiver
0010H
UART 0 transmitter
0012H
I2C
0014H
SPI
0016H
ADC
0018H
Port A7 or Port D7, rising or falling input edge
001AH
Port A6 or Port D6, rising or falling input edge
001CH
Port A5 or Port D5, rising or falling input edge
001EH
Port A4 or Port D4, rising or falling input edge
0020H
Port A3 or Port D3, rising or falling input edge
0022H
Port A2 or Port D2, rising or falling input edge
0024H
Port A1 or Port D1, rising or falling input edge
0026H
Port A0 or Port D0, rising or falling input edge
0028H
Timer 3 (not available in 44-pin packages)
002AH
UART 1 receiver
002CH
UART 1 transmitter
002EH
DMA
0030H
Port C3, both input edges
0032H
Port C2, both input edges
0034H
Port C1, both input edges
0036H
Port C0, both input edges
Interrupt Controller
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69
Architecture
Figure 11 displays a block diagram of the interrupt controller.
Internal Interrupts
Interrupt Request Latches and Control
Port Interrupts
High
Priority
Vector
Medium
Priority
Priority
Mux
IRQ Request
Low
Priority
Figure 11. Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
•
•
•
Executing an Enable Interrupt (EI) instruction.
Executing an Return from Interrupt (IRET) instruction.
Writing a 1 to the IRQE bit in the Interrupt Control register.
Interrupts are globally disabled by any of the following actions:
PS019919-1207
•
•
Execution of a Disable Interrupt (DI) instruction.
•
•
Writing a 0 to the IRQE bit in the Interrupt Control register.
eZ8 CPU acknowledgement of an interrupt service request from the interrupt
controller.
Reset.
Interrupt Controller
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•
•
Executing a Trap instruction.
Illegal Instruction trap.
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all of
the interrupts were enabled with identical interrupt priority (all as Level 2 interrupts, for
example), then interrupt priority would be assigned from highest to lowest as specified in
Table 23 on page 68. Level 3 interrupts always have higher priority than Level 2 interrupts
which, in turn, always have higher priority than Level 1 interrupts. Within each interrupt
priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in Table 23 on
page 68. Reset, Watchdog Timer interrupt (if enabled), and Illegal Instruction Trap always
have highest priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period
(single pulse). When the interrupt request is acknowledged by the eZ8 CPU, the
corresponding bit in the Interrupt Request register is cleared until the next interrupt
occurs. Writing a 0 to the corresponding bit in the Interrupt Request register likewise
clears the interrupt request.
Caution: The following style of coding to clear bits in the Interrupt Request registers is
NOT recommended. All incoming interrupts that are received between
execution of the first LDX command and the last LDX command are lost.
Poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, the following style of coding to clear bits in
the Interrupt Request 0 register is recommended:
Good coding style that avoids lost interrupt requests:
ANDX IRQ0, MASK
Software Interrupt Assertion
Program code can generate interrupts directly. Writing a 1 to the desired bit in the Interrupt
Request register triggers an interrupt (assuming that interrupt is enabled). When the interrupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is
automatically cleared to 0.
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Caution: The following style of coding to generate software interrupts by setting bits in
the Interrupt Request registers is NOT recommended. All incoming interrupts
that are received between execution of the first LDX command and the last
LDX command are lost.
Poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, the following style of coding to set bits in the
Interrupt Request registers is recommended:
Good coding style that avoids lost interrupt requests:
ORX IRQ0, MASK
Interrupt Control Register Definitions
For all interrupts other than the Watchdog Timer interrupt, the interrupt control registers
enable individual interrupts, set interrupt priorities, and indicate interrupt requests.
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) register (Table 24) stores the interrupt requests for both
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8™ CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 0 register to determine if any interrupt requests are pending
Table 24. Interrupt Request 0 Register (IRQ0)
BITS
FIELD
RESET
R/W
ADDR
7
6
5
4
3
2
1
0
T2I
T1I
T0I
U0RXI
U0TXI
I2CI
SPII
ADCI
0
R/W
FC0H
T2I—Timer 2 Interrupt Request
0 = No interrupt request is pending for Timer 2.
1 = An interrupt request from Timer 2 is awaiting service.
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T1I—Timer 1 Interrupt Request
0 = No interrupt request is pending for Timer 1.
1 = An interrupt request from Timer 1 is awaiting service.
T0I—Timer 0 Interrupt Request
0 = No interrupt request is pending for Timer 0.
1 = An interrupt request from Timer 0 is awaiting service.
U0RXI—UART 0 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 0 receiver.
1 = An interrupt request from the UART 0 receiver is awaiting service.
U0TXI—UART 0 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 0 transmitter.
1 = An interrupt request from the UART 0 transmitter is awaiting service.
I2CI— I2C Interrupt Request
0 = No interrupt request is pending for the I2C.
1 = An interrupt request from the I2C is awaiting service.
SPII—SPI Interrupt Request
0 = No interrupt request is pending for the SPI.
1 = An interrupt request from the SPI is awaiting service.
ADCI—ADC Interrupt Request
0 = No interrupt request is pending for the Analog-to-Digital Converter.
1 = An interrupt request from the Analog-to-Digital Converter is awaiting service.
Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) register (Table 25) stores interrupt requests for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ1 register becomes 1. If interrupts are globally enabled (vectored
interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts
are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1
register to determine if any interrupt requests are pending.
Table 25. Interrupt Request 1 Register (IRQ1)
BITS
FIELD
7
6
5
4
3
2
1
0
PAD7I
PAD6I
PAD5I
PAD4I
PAD3I
PAD2I
PAD1I
PAD0I
RESET
R/W
ADDR
PS019919-1207
0
R/W
FC3H
Interrupt Controller
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PADxI—Port A or Port D Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port A or Port D pin x.
1 = An interrupt request from GPIO Port A or Port D pin x is awaiting service.
where x indicates the specific GPIO Port pin number (0 through 7). For each pin, only 1 of
either Port A or Port D can be enabled for interrupts at any one time. Port selection (A or
D) is determined by the values in the Interrupt Port Select Register.
Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) register (Table 26) stores interrupt requests for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ2 register becomes 1. If interrupts are globally enabled (vectored
interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts
are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1
register to determine if any interrupt requests are pending.
Table 26. Interrupt Request 2 Register (IRQ2)
BITS
FIELD
7
6
5
4
3
2
1
0
T3I
U1RXI
U1TXI
DMAI
PC3I
PC2I
PC1I
PC0I
RESET
R/W
ADDR
0
R/W
FC6H
T3I—Timer 3 Interrupt Request
0 = No interrupt request is pending for Timer 3.
1 = An interrupt request from Timer 3 is awaiting service.
U1RXI—UART 1 Receive Interrupt Request
0 = No interrupt request is pending for the UART1 receiver.
1 = An interrupt request from UART1 receiver is awaiting service.
U1TXI—UART 1 Transmit Interrupt Request
0 = No interrupt request is pending for the UART 1 transmitter.
1 = An interrupt request from the UART 1 transmitter is awaiting service.
DMAI—DMA Interrupt Request
0 = No interrupt request is pending for the DMA.
1 = An interrupt request from the DMA is awaiting service.
PCxI—Port C Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
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where x indicates the specific GPIO Port C pin number (0 through 3).
IRQ0 Enable High and Low Bit Registers
The IRQ0 Enable High and Low Bit registers (see Table 28 and Table 29 on page 75) form
a priority encoded enabling for interrupts in the Interrupt Request 0 register. Priority is
generated by setting bits in each register. Table 27 describes the priority control for IRQ0.
Table 27. IRQ0 Enable and Priority Encoding
IRQ0ENH[x] IRQ0ENL[x]
Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
Note: where x indicates the register bits from 0 through 7.
Table 28. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS
FIELD
7
6
5
4
3
2
1
0
T2ENH
T1ENH
T0ENH
U0RENH
U0TENH
I2CENH
SPIENH
ADCENH
RESET
R/W
ADDR
0
R/W
FC1H
T2ENH—Timer 2 Interrupt Request Enable High Bit
T1ENH—Timer 1 Interrupt Request Enable High Bit
T0ENH—Timer 0 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
I2CENH—I2C Interrupt Request Enable High Bit
SPIENH—SPI Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
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Table 29. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS
FIELD
7
6
5
4
3
2
1
0
T2ENL
T1ENL
T0ENL
U0RENL
U0TENL
I2CENL
SPIENL
ADCENL
0
RESET
R/W
R/W
FC2H
ADDR
T2ENL—Timer 2 Interrupt Request Enable Low Bit
T1ENL—Timer 1 Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
I2CENL—I2C Interrupt Request Enable Low Bit
SPIENL—SPI Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
IRQ1 Enable High and Low Bit Registers
The IRQ1 Enable High and Low Bit registers (see Table 31 and Table 32 on page 76) form
a priority encoded enabling for interrupts in the Interrupt Request 1 register. Priority is
generated by setting bits in each register. Table 30 describes the priority control for IRQ1.
Table 30. IRQ1 Enable and Priority Encoding
IRQ1ENH[x] IRQ1ENL[x]
Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
Note: where x indicates the register bits from 0 through 7.
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Table 31. IRQ1 Enable High Bit Register (IRQ1ENH)
BITS
FIELD
7
5
4
3
2
1
0
PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
R/W
6
FC4H
ADDR
PADxENH—Port A or Port D Bit[x] Interrupt Request Enable High Bit.
For selection of either Port A or Port D as the interrupt source, see Interrupt Port Select
Register on page 78.
Table 32. IRQ1 Enable Low Bit Register (IRQ1ENL)
BITS
FIELD
7
5
4
3
2
1
0
PAD7ENL PAD6ENL PAD5ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL PAD0ENL
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
R/W
6
FC5H
ADDR
PADxENL—Port A or Port D Bit[x] Interrupt Request Enable Low Bit
For selection of either Port A or Port D as the interrupt source, see Interrupt Port Select
Register on page 78.
IRQ2 Enable High and Low Bit Registers
The IRQ2 Enable High and Low Bit registers (see Table 34 and Table 35 on page 77) form
a priority encoded enabling for interrupts in the Interrupt Request 2 register. Priority is
generated by setting bits in each register. Table 33 describes the priority control for IRQ2.
Table 33. IRQ2 Enable and Priority Encoding
IRQ2ENH[x] IRQ2ENL[x]
PS019919-1207
Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
Interrupt Controller
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Table 33. IRQ2 Enable and Priority Encoding (Continued)
IRQ2ENH[x] IRQ2ENL[x]
1
1
Priority
Description
Level 3
High
Note: where x indicates the register bits from 0 through 7.
Table 34. IRQ2 Enable High Bit Register (IRQ2ENH)
BITS
FIELD
7
6
5
4
3
2
1
0
T3ENH
U1RENH
U1TENH
DMAENH
C3ENH
C2ENH
C1ENH
C0ENH
0
RESET
R/W
R/W
FC7H
ADDR
T3ENH—Timer 3 Interrupt Request Enable High Bit
U1RENH—UART 1 Receive Interrupt Request Enable High Bit
U1TENH—UART 1 Transmit Interrupt Request Enable High Bit
DMAENH—DMA Interrupt Request Enable High Bit
C3ENH—Port C3 Interrupt Request Enable High Bit
C2ENH—Port C2 Interrupt Request Enable High Bit
C1ENH—Port C1 Interrupt Request Enable High Bit
C0ENH—Port C0 Interrupt Request Enable High Bit
Table 35. IRQ2 Enable Low Bit Register (IRQ2ENL)
BITS
FIELD
7
6
5
4
3
2
1
0
T3ENL
U1RENL
U1TENL
DMAENL
C3ENL
C2ENL
C1ENL
C0ENL
RESET
R/W
ADDR
0
R/W
FC8H
T3ENL—Timer 3 Interrupt Request Enable Low Bit
U1RENL—UART 1 Receive Interrupt Request Enable Low Bit
U1TENL—UART 1 Transmit Interrupt Request Enable Low Bit
DMAENL—DMA Interrupt Request Enable Low Bit
C3ENL—Port C3 Interrupt Request Enable Low Bit
C2ENL—Port C2 Interrupt Request Enable Low Bit
PS019919-1207
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C1ENL—Port C1 Interrupt Request Enable Low Bit
C0ENL—Port C0 Interrupt Request Enable Low Bit
Interrupt Edge Select Register
The Interrupt Edge Select (IRQES) register (Table 36) determines whether an interrupt is
generated for the rising edge or falling edge on the selected GPIO Port input pin. The
Interrupt Port Select register selects between Port A and Port D for the individual interrupts.
Table 36. Interrupt Edge Select Register (IRQES)
BITS
FIELD
7
6
5
4
3
2
1
0
IES7
IES6
IES5
IES4
IES3
IES2
IES1
IES0
0
RESET
R/W
R/W
FCDH
ADDR
IESx—Interrupt Edge Select x
The minimum pulse width should be greater than 1 system clock to guarantee capture of
the edge triggered interrupt. Shorter pulses may be captured but not guaranteed.
0 = An interrupt request is generated on the falling edge of the PAx/PDx input.
1 = An interrupt request is generated on the rising edge of the PAx/PDx input.
where x indicates the specific GPIO Port pin number (0 through 7).
Interrupt Port Select Register
The Port Select (IRQPS) register (Table 37) determines the port pin that generates the
PAx/PDx interrupts. This register allows either Port A or Port D pins to be used as
interrupts. The Interrupt Edge Select register controls the active interrupt edge.
Table 37. Interrupt Port Select Register (IRQPS)
BITS
FIELD
7
6
5
4
3
2
1
0
PAD7S
PAD6S
PAD5S
PAD4S
PAD3S
PAD2S
PAD1S
PAD0S
RESET
R/W
ADDR
PS019919-1207
0
R/W
FCEH
Interrupt Controller
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PADxS—PAx/PDx Selection
0 = PAx is used for the interrupt for PAx/PDx interrupt request.
1 = PDx is used for the interrupt for PAx/PDx interrupt request.
where x indicates the specific GPIO Port pin number (0 through 7).
Interrupt Control Register
The Interrupt Control (IRQCTL) register (Table 38) contains the master enable bit for all
interrupts.
Table 38. Interrupt Control Register (IRQCTL)
BITS
FIELD
7
6
4
3
IRQE
2
1
0
Reserved
0
RESET
R/W
5
R/W
R
FCFH
ADDR
IRQE—Interrupt Request Enable
This bit is set to 1 by execution of an EI or IRET instruction, or by a direct register write of
a 1 to this bit. It is reset to 0 by executing a DI instruction, eZ8 CPU acknowledgement of
an interrupt request, or Reset.
0 = Interrupts are disabled
1 = Interrupts are enabled
Reserved—Must be 0.
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Timers
Overview
The 64K Series products contain up to four 16-bit reloadable timers that can be used for
timing, event counting, or generation of pulse width modulated signals. The timers’ features include:
•
•
•
•
•
16-bit reload counter
•
•
Timer output pin
Programmable prescaler with prescale values from 1 to 128
PWM output generation
Capture and compare capability
External input pin for timer input, clock gating, or capture signal. External input pin
signal frequency is limited to a maximum of one-fourth the system clock frequency.
Timer interrupt
In addition to the timers described in this chapter, the Baud Rate Generators for any
unused UART, SPI, or I2C peripherals may also be used to provide basic timing functionality. For information on using the Baud Rate Generators as timers, see the respective
serial communication peripheral. Timer 3 is unavailable in the 44-pin package devices.
Architecture
Figure 12 displays the architecture of the timers.
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Timer Block
Block
Control
16-Bit
Reload Register
System
Clock
Compare
Timer
Control
Data
Bus
Gate
Input
16-Bit
PWM/Compare
Capture
Input
Timer
Interrupt
Timer
Output
Compare
16-Bit Counter
with Prescaler
Timer
Input
Interrupt,
PWM,
and
Timer Output
Control
Figure 12. Timer Block Diagram
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value
0001H into the Timer Reload High and Low Byte registers and setting the prescale value
to 1. Maximum time-out delay is set by loading the value 0000H into the Timer Reload
High and Low Byte registers and setting the prescale value to 128. If the Timer reaches
FFFFH, the timer rolls over to 0000H and continues counting.
Timer Operating Modes
The timers can be configured to operate in the following modes:
ONE-SHOT Mode
In ONE-SHOT mode, the timer counts up to the 16-bit Reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. Upon reaching
the Reload value, the timer generates an interrupt and the count value in the Timer High
and Low Byte registers is reset to 0001H. Then, the timer is automatically disabled and
stops counting.
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
for one system clock cycle (from Low to High or from High to Low) upon timer Reload. If
it is desired to have the Timer Output make a permanent state change upon
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One-Shot time-out, first set the TPOL bit in the Timer Control 1 Register to the start value
before beginning ONE-SHOT mode. Then, after starting the timer, set TPOL to the opposite bit value.
Follow the steps below for configuring a timer for ONE-SHOT mode and initiating the
count:
1. Write to the Timer Control 1 register to:
– Disable the timer
– Configure the timer for ONE-SHOT mode
– Set the prescale value
– If using the Timer Output alternate function, set the initial output level (High or
Low)
2. Write to the Timer High and Low Byte registers to set the starting count value
3. Write to the Timer Reload High and Low Byte registers to set the Reload value
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function
6. Write to the Timer Control 1 register to enable the timer and initiate counting
In ONE-SHOT mode, the system clock always provides the timer input. The timer period
is given by the following equation:
( Reload Value – Start Value ) × Prescale
ONE-SHOT Mode Time-Out Period (s) = ------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
CONTINUOUS Mode
In CONTINUOUS mode, the timer counts up to the 16-bit Reload value stored in the
Timer Reload High and Low Byte registers. The timer input is the system clock. Upon
reaching the Reload value, the timer generates an interrupt, the count value in the Timer
High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer
Output alternate function is enabled, the Timer Output pin changes state (from Low to
High or from High to Low) upon timer Reload.
Follow the steps below for configuring a timer for CONTINUOUS mode and initiating the
count:
1. Write to the Timer Control 1 register to:
– Disable the timer
– Configure the timer for CONTINUOUS mode
– Set the prescale value
– If using the Timer Output alternate function, set the initial output level (High or
Low)
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2. Write to the Timer High and Low Byte registers to set the starting count value (usually
0001H), affecting only the first pass in CONTINUOUS mode. After the first timer
Reload in CONTINUOUS mode, counting always begins at the reset value of 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control 1 register to enable the timer and initiate counting.
In CONTINUOUS mode, the system clock always provides the timer input. The timer
period is given by the following equation:
Reload Value × Prescale
CONTINUOUS Mode Time-Out Period (s) = -----------------------------------------------------------------------System Clock Frequency (Hz)
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
registers, the ONE-SHOT mode equation must be used to determine the first time-out
period.
COUNTER Mode
In COUNTER mode, the timer counts input transitions from a GPIO port pin. The timer
input is taken from the GPIO Port pin Timer Input alternate function. The TPOL bit in the
Timer Control 1 Register selects whether the count occurs on the rising edge or the falling
edge of the Timer Input signal. In COUNTER mode, the prescaler is disabled.
Caution: The input frequency of the Timer Input signal must not exceed one-fourth the
system clock frequency.
Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is
enabled, the Timer Output pin changes state (from Low to High or from High to Low) at
timer Reload.
Follow the steps below for configuring a timer for COUNTER mode and initiating the
count:
1. Write to the Timer Control 1 register to:
– Disable the timer
– Configure the timer for COUNTER mode
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–
Select either the rising edge or falling edge of the Timer Input signal for the count.
This also sets the initial logic level (High or Low) for the Timer Output alternate
function. However, the Timer Output function does not have to be enabled
2. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in COUNTER mode. After the first timer Reload in
COUNTER mode, counting always begins at the reset value of 0001H. Generally, in
COUNTER mode the Timer High and Low Byte registers must be written with the
value 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
7. Write to the Timer Control 1 register to enable the timer.
In COUNTER mode, the number of Timer Input transitions since the timer start is given
by the following equation:
COUNTER Mode Timer Input Transitions = Current Count Value – Start Value
PWM Mode
In PWM mode, the timer outputs a Pulse-Width Modulator (PWM) output signal through
a GPIO Port pin. The timer input is the system clock. The timer first counts up to the 16bit PWM match value stored in the Timer PWM High and Low Byte registers. When the
timer count value matches the PWM value, the Timer Output toggles. The timer continues
counting until it reaches the Reload value stored in the Timer Reload High and Low Byte
registers. Upon reaching the Reload value, the timer generates an interrupt, the count
value in the Timer High and Low Byte registers is reset to 0001H and counting resumes.
If the TPOL bit in the Timer Control 1 register is set to 1, the Timer Output signal begins
as a High (1) and then transitions to a Low (0) when the timer value matches the PWM
value. The Timer Output signal returns to a High (1) after the timer reaches the Reload
value and is reset to 0001H.
If the TPOL bit in the Timer Control 1 register is set to 0, the Timer Output signal begins
as a Low (0) and then transitions to a High (1) when the timer value matches the PWM
value. The Timer Output signal returns to a Low (0) after the timer reaches the Reload
value and is reset to 0001H.
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Follow the steps below for configuring a timer for PWM mode and initiating the PWM
operation:
1. Write to the Timer Control 1 register to:
– Disable the timer
– Configure the timer for PWM mode
– Set the prescale value
– Set the initial logic level (High or Low) and PWM High/Low transition for the
Timer Output alternate function
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H). This only affects the first pass in PWM mode. After the first timer
reset in PWM mode, counting always begins at the reset value of 0001H.
3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM
period). The Reload value must be greater than the PWM value.
5. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
6. Configure the associated GPIO port pin for the Timer Output alternate function.
7. Write to the Timer Control 1 register to enable the timer and initiate counting.
The PWM period is given by the following equation:
Reload Value × Prescale
PWM Period (s) = -----------------------------------------------------------------------System Clock Frequency (Hz)
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
registers, the ONE-SHOT mode equation must be used to determine the first PWM timeout period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is given by:
Reload Value – PWM Value
PWM Output High Time Ratio (%) = --------------------------------------------------------------------- × 100
Reload Value
If TPOL is set to 1, the ratio of the PWM output High time to the total period is given by:
PWM Value
PWM Output High Time Ratio (%) = -------------------------------- × 100
Reload Value
CAPTURE Mode
In CAPTURE mode, the current timer count value is recorded when the desired external
Timer Input transition occurs. The Capture count value is written to the Timer PWM High
and Low Byte Registers. The timer input is the system clock. The TPOL bit in the Timer
Control 1 register determines if the Capture occurs on a rising edge or a falling edge of the
Timer Input signal. When the Capture event occurs, an interrupt is generated and the timer
continues counting.
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The timer continues counting up to the 16-bit Reload value stored in the Timer Reload
High and Low Byte registers. Upon reaching the Reload value, the timer generates an
interrupt and continues counting.
Follow the steps below for configuring a timer for CAPTURE mode and initiating the
count:
1. Write to the Timer Control 1 register to:
– Disable the timer
– Configure the timer for CAPTURE mode.
– Set the prescale value.
– Set the Capture edge (rising or falling) for the Timer Input.
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H).
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. Clear the Timer PWM High and Low Byte registers to 0000H. This allows the
software to determine if interrupts were generated by either a capture event or a
reload. If the PWM High and Low Byte registers still contain 0000H after the
interrupt, then the interrupt was generated by a Reload.
5. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
6. Configure the associated GPIO port pin for the Timer Input alternate function.
7. Write to the Timer Control 1 register to enable the timer and initiate counting.
In CAPTURE mode, the elapsed time from timer start to Capture event can be calculated
using the following equation:
( Capture Value – Start Value ) × PrescaleCapture Elapsed Time (s) = -------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
COMPARE Mode
In COMPARE mode, the timer counts up to the 16-bit maximum Compare value stored in
the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon
reaching the Compare value, the timer generates an interrupt and counting continues (the
timer value is not reset to 0001H). Also, if the Timer Output alternate function is enabled,
the Timer Output pin changes state (from Low to High or from High to Low) upon Compare.
If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting.
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Follow the steps below for configuring a timer for COMPARE mode and initiating the
count:
1. Write to the Timer Control 1 register to:
– Disable the timer
– Configure the timer for COMPARE mode
– Set the prescale value
– Set the initial logic level (High or Low) for the Timer Output alternate function, if
desired
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control 1 register to enable the timer and initiate counting.
In COMPARE mode, the system clock always provides the timer input. The Compare time
is given by the following equation:
Compare Value – Start Value ) × PrescaleCOMPARE Mode Time (s) = (----------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
GATED Mode
In GATED mode, the timer counts only when the Timer Input signal is in its active state
(asserted), as determined by the TPOL bit in the Timer Control 1 register. When the Timer
Input signal is asserted, counting begins. A timer interrupt is generated when the Timer
Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal
deassertion generated the interrupt, read the associated GPIO input value and compare to
the value stored in the TPOL bit.
The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low
Byte registers. The timer input is the system clock. When reaching the Reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to 0001H and counting resumes (assuming the Timer Input signal is still asserted).
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reset.
Follow the steps below for configuring a timer for GATED mode and initiating the count:
1. Write to the Timer Control 1 register to:
– Disable the timer
– Configure the timer for GATED mode
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–
Set the prescale value
2. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in GATED mode. After the first timer reset in GATED mode,
counting always begins at the reset value of 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. Write to the Timer Control 1 register to enable the timer.
7. Assert the Timer Input signal to initiate the counting.
CAPTURE/COMPARE Mode
In CAPTURE/COMPARE mode, the timer begins counting on the first external Timer
Input transition. The desired transition (rising edge or falling edge) is set by the TPOL bit
in the Timer Control 1 Register. The timer input is the system clock.
Every subsequent desired transition (after the first) of the Timer Input signal captures the
current count value. The Capture value is written to the Timer PWM High and Low Byte
Registers. When the Capture event occurs, an interrupt is generated, the count value in the
Timer High and Low Byte registers is reset to 0001H, and counting resumes.
If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001H and counting resumes.
Follow the steps below for configuring a timer for CAPTURE/COMPARE mode and initiating the count:
1. Write to the Timer Control 1 register to:
– Disable the timer
– Configure the timer for CAPTURE/COMPARE mode
– Set the prescale value
– Set the Capture edge (rising or falling) for the Timer Input
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H).
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
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6. Write to the Timer Control 1 register to enable the timer.
7. Counting begins on the first appropriate transition of the Timer Input signal. No
interrupt is generated by this first edge.
In m/COMPARE mode, the elapsed time from timer start to Capture event can be calculated using the following equation:
( Capture Value – Start Value ) × Prescale
Capture Elapsed Time (s) = --------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
Reading the Timer Count Values
The current count value in the timers can be read while counting (enabled). This capability
has no effect on timer operation. When the timer is enabled and the Timer High Byte
register is read, the contents of the Timer Low Byte register are placed in a holding
register. A subsequent read from the Timer Low Byte register returns the value in the
holding register. This operation allows accurate reads of the full 16-bit timer count value
while enabled. When the timers are not enabled, a read from the Timer Low Byte register
returns the actual value in the counter.
Timer Output Signal Operation
Timer Output is a GPIO Port pin alternate function. Generally, the Timer Output is toggled
every time the counter is reloaded.
Timer Control Register Definitions
Timers 0-2 are available in all packages. Timer 3 is only available in the 64-, 68-, and
80-pin packages.
Timer 0-3 High and Low Byte Registers
The Timer 0-3 High and Low Byte (TxH and TxL) registers (see Table 39 and Table 40 on
page 91) contain the current 16-bit timer count value. When the timer is enabled, a read
from TxH causes the value in TxL to be stored in a temporary holding register. A read
from TMRL always returns this temporary register when the timers are enabled. When the
timer is disabled, reads from the TMRL reads the register directly.
Writing to the Timer High and Low Byte registers while the timer is enabled is not
recommended. There are no temporary holding registers available for write operations, so
simultaneous 16-bit writes are not possible. If either the Timer High or Low Byte registers
are written during counting, the 8-bit written value is placed in the counter (High or Low
Byte) at the next clock edge. The counter continues counting from the new value.
Timer 3 is unavailable in the 40- and 44-pin packages.
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Table 39. Timer 0-3 High Byte Register (TxH)
BITS
7
6
5
4
3
FIELD
TH
RESET
0
2
1
0
2
1
0
R/W
R/W
F00H, F08H, F10H, F18H
ADDR
Table 40. Timer 0-3 Low Byte Register (TxL)
BITS
7
6
5
4
3
TL
FIELD
0
RESET
1
R/W
R/W
F01H, F09H, F11H, F19H
ADDR
TH and TL—Timer High and Low Bytes
These 2 bytes, {TMRH[7:0], TMRL[7:0]}, contain the current 16-bit timer count value.
Timer Reload High and Low Byte Registers
The Timer 0-3 Reload High and Low Byte (TxRH and TxRL) registers (see Table 41and
Table 42 on page 92) store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to
the Timer Reload High Byte register are stored in a temporary holding register. When a
write to the Timer Reload Low Byte register occurs, the temporary holding register value
is written to the Timer High Byte register. This operation allows simultaneous updates of
the 16-bit Timer Reload value.
In COMPARE mode, the Timer Reload High and Low Byte registers store the 16-bit
Compare value.
Table 41. Timer 0-3 Reload High Byte Register (TxRH)
BITS
7
6
5
4
3
FIELD
TRH
RESET
1
R/W
ADDR
PS019919-1207
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1
0
R/W
F02H, F0AH, F12H, F1AH
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Table 42. Timer 0-3 Reload Low Byte Register (TxRL)
BITS
7
6
5
4
3
FIELD
TRL
RESET
1
2
1
0
R/W
R/W
F03H, F0BH, F13H, F1BH
ADDR
TRH and TRL—Timer Reload Register High and Low
These two bytes form the 16-bit Reload value, {TRH[7:0], TRL[7:0]}. This value sets the
maximum count value which initiates a timer reload to 0001H. In COMPARE mode, these
two byte form the 16-bit Compare value.
Timer 0-3 PWM High and Low Byte Registers
The Timer 0-3 PWM High and Low Byte (TxPWMH and TxPWML) registers (see
Table 43 and Table 44 on page 92) are used for Pulse-Width Modulator (PWM) operations. These registers also store the Capture values for the Capture and Capture/COMPARE modes.
Table 43. Timer 0-3 PWM High Byte Register (TxPWMH)
BITS
7
6
5
4
3
FIELD
PWMH
RESET
0
2
1
0
2
1
0
R/W
R/W
F04H, F0CH, F14H, F1CH
ADDR
Table 44. Timer 0-3 PWM Low Byte Register (TxPWML)
BITS
7
6
5
4
3
FIELD
PWML
RESET
0
R/W
ADDR
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F05H, F0DH, F15H, F1DH
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PWMH and PWML—Pulse-Width Modulator High and Low Bytes
These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the
current 16-bit timer count. When a match occurs, the PWM output changes state. The
PWM output value is set by the TPOL bit in the Timer Control 1 Register (TxCTL1) register.
The TxPWMH and TxPWML registers also store the 16-bit captured timer value when
operating in CAPTURE or CAPTURE/COMPARE modes.
Timer 0-3 Control 0 Registers
The Timer 0-3 Control 0 (TxCTL0) registers (see Table 45 and Table 46) allow cascading
of the Timers.
Table 45. Timer 0-3 Control 0 Register (TxCTL0)
BITS
FIELD
RESET
R/W
ADDR
7
6
Reserved
5
4
3
CSC
2
1
0
Reserved
0
R/W
F06H, F0EH, F16H, F1EH
CSC—Cascade Timers
0 = Timer Input signal comes from the pin.
1 = For Timer 0, Input signal is connected to Timer 3 output.
For Timer 1, Input signal is connected to Timer 0 output.
For Timer 2, Input signal is connected to Timer 1 output.
For Timer 3, Input signal is connected to Timer 2 output.
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Timer 0-3 Control 1 Registers
The Timer 0-3 Control 1 (TxCTL1) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
Table 46. Timer 0-3 Control 1 Register (TxCTL1)
BITS
FIELD
7
6
TEN
TPOL
5
4
3
2
PRES
1
0
TMODE
0
RESET
R/W
R/W
F07H, F0FH, F17H, F1FH
ADDR
TEN—Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
TPOL—Timer Input/Output Polarity
Operation of this bit is a function of the current operating mode of the timer.
ONE-SHOT mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
CONTINUOUS mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
COUNTER mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
0 = Count occurs on the rising edge of the Timer Input signal.
1 = Count occurs on the falling edge of the Timer Input signal.
PWM mode
0 = Timer Output is forced Low (0) when the timer is disabled. When enabled,
the Timer Output is forced High (1) upon PWM count match and forced
Low (0) upon Reload.
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Timers
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
95
1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the
Timer Output is forced Low (0) upon PWM count match and forced High (1) upon
Reload.
CAPTURE mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
COMPARE mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
GATED mode
0 = Timer counts when the Timer Input signal is High (1) and interrupts are
generated on the falling edge of the Timer Input.
1 = Timer counts when the Timer Input signal is Low (0) and interrupts are
generated on the rising edge of the Timer Input.
CAPTURE/COMPARE mode
0 = Counting is started on the first rising edge of the Timer Input signal. The
current count is captured on subsequent rising edges of the Timer Input signal.
1 = Counting is started on the first falling edge of the Timer Input signal. The
current count is captured on subsequent falling edges of the Timer Input signal.
Caution: When the Timer Output alternate function TxOUT on a GPIO port pin is enabled, TxOUT will change to whatever state the TPOL bit is in. The timer does
not need to be enabled for that to happen. Also, the Port data direction sub register is not needed to be set to output on TxOUT. Changing the TPOL bit with
the timer enabled and running does not immediately change the TxOUT.
PRES—Prescale value.
The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7. The
prescaler is reset each time the Timer is disabled. This insures proper clock division
each time the Timer is restarted.
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
PS019919-1207
Timers
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
96
110 = Divide by 64
111 = Divide by 128
TMODE—TIMER mode
000 = ONE-SHOT mode
001 = CONTINUOUS mode
010 = COUNTER mode
011 = PWM mode
100 = CAPTURE mode
101 = COMPARE mode
110 = GATED mode
111 = CAPTURE/COMPARE mode
PS019919-1207
Timers
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
97
Watchdog Timer
Overview
The Watchdog Timer (WDT) helps protect against corrupt or unreliable software, power
faults, and other system-level problems which may place the Z8 Encore! XP into unsuitable operating states. The features of Watchdog Timer include:
•
•
•
•
On-chip RC oscillator.
A selectable time-out response.
WDT Time-out response: Reset or interrupt.
24-bit programmable time-out value.
Operation
The Watchdog Timer (WDT) is a retriggerable one-shot timer that resets or interrupts the
64K Series devices when the WDT reaches its terminal count. The Watchdog Timer uses
its own dedicated on-chip RC oscillator as its clock source. The Watchdog Timer has only
two modes of operation—ON and OFF. Once enabled, it always counts and must be
refreshed to prevent a time-out. An enable can be performed by executing the WDT
instruction or by setting the WDT_AO Option Bit. The WDT_AO bit enables the Watchdog
Timer to operate all the time, even if a WDT instruction has not been executed.
The Watchdog Timer is a 24-bit reloadable downcounter that uses three 8-bit registers in
the eZ8™ CPU register space to set the reload value. The nominal WDT time-out period is
given by the following equation:
WDT Reload Value
WDT Time-out Period (ms) = -----------------------------------------------10
where the WDT reload value is the decimal value of the 24-bit value given by
{WDTU[7:0], WDTH[7:0], WDTL[7:0]} and the typical Watchdog Timer RC oscillator
frequency is 10 kHz. The Watchdog Timer cannot be refreshed once it reaches 000002H.
The WDT Reload Value must not be set to values below 000004H. Table 47 provides
information on approximate time-out delays for the minimum and maximum WDT reload
values.
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Watchdog Timer
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
98
Table 47. Watchdog Timer Approximate Time-Out Delays
Approximate Time-Out Delay
(with 10 kHz typical WDT oscillator frequency)
WDT Reload Value
WDT Reload Value
(Hex)
(Decimal)
Typical
000004
4
400 µs
Minimum time-out delay
FFFFFF
16,777,215
1677.5 s
Maximum time-out delay
Description
Watchdog Timer Refresh
When first enabled, the Watchdog Timer is loaded with the value in the Watchdog Timer
Reload registers. The Watchdog Timer then counts down to 000000H unless a WDT
instruction is executed by the eZ8™ CPU. Execution of the WDT instruction causes the
downcounter to be reloaded with the WDT Reload value stored in the Watchdog Timer
Reload registers. Counting resumes following the reload operation.
When the 64K Series devices are operating in DEBUG Mode (through the On-Chip
Debugger), the Watchdog Timer is continuously refreshed to prevent spurious Watchdog
Timer time-outs.
Watchdog Timer Time-Out Response
The Watchdog Timer times out when the counter reaches 000000H. A time-out of the
Watchdog Timer generates either an interrupt or a Reset. The WDT_RES Option Bit
determines the time-out response of the Watchdog Timer. For information on
programming of the WDT_RES Option Bit, see Option Bits on page 195.
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the Watchdog Timer issues
an interrupt request to the interrupt controller and sets the WDT status bit in the Watchdog
Timer Control register. If interrupts are enabled, the eZ8 CPU responds to the interrupt
request by fetching the Watchdog Timer interrupt vector and executing code from the
vector address. After time-out and interrupt generation, the Watchdog Timer counter rolls
over to its maximum value of FFFFFH and continues counting. The Watchdog Timer
counter is not automatically returned to its Reload Value.
WDT Interrupt in STOP Mode
If configured to generate an interrupt when a time-out occurs and the 64K Series devices
are in STOP mode, the Watchdog Timer automatically initiates a Stop Mode Recovery and
generates an interrupt request. Both the WDT status bit and the STOP bit in the Watchdog
Timer Control register are set to 1 following WDT time-out in STOP mode. For more
information on Stop Mode Recovery, see Reset and Stop Mode Recovery on page 47.
PS019919-1207
Watchdog Timer
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
99
If interrupts are enabled, following completion of the Stop Mode Recovery the eZ8 CPU
responds to the interrupt request by fetching the Watchdog Timer interrupt vector and executing code from the vector address.
WDT Reset in Normal Operation
If configured to generate a Reset when a time-out occurs, the Watchdog Timer forces the
device into the Reset state. The WDT status bit in the Watchdog Timer Control register is
set to 1. For more information on Reset, see Reset and Stop Mode Recovery on page 47.
WDT Reset in STOP Mode
If enabled in STOP mode and configured to generate a Reset when a time-out occurs and
the device is in STOP mode, the Watchdog Timer initiates a Stop Mode Recovery. Both
the WDT status bit and the STOP bit in the Watchdog Timer Control register are set to 1
following WDT time-out in STOP mode. Default operation is for the WDT and its RC
oscillator to be enabled during STOP mode.
WDT RC Disable in STOP Mode
To minimize power consumption in STOP Mode, the WDT and its RC oscillator can be
disabled in STOP mode. The following sequence configures the WDT to be disabled when
the 64K Series devices enter STOP Mode following execution of a STOP instruction:
1. Write 55H to the Watchdog Timer Control register (WDTCTL).
2. Write AAH to the Watchdog Timer Control register (WDTCTL).
3. Write 81H to the Watchdog Timer Control register (WDTCTL) to configure the WDT
and its oscillator to be disabled during STOP Mode. Alternatively, write 00H to the
Watchdog Timer Control register (WDTCTL) as the third step in this sequence to
reconfigure the WDT and its oscillator to be enabled during STOP mode.
This sequence only affects WDT operation in STOP mode.
Watchdog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watchdog Timer (WDTCTL) Control register address
unlocks the three Watchdog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to
allow changes to the time-out period. These write operations to the WDTCTL register
address produce no effect on the bits in the WDTCTL register. The locking mechanism
prevents spurious writes to the Reload registers. Follow the steps below to unlock the
Watchdog Timer Reload Byte registers (WDTU, WDTH, and WDTL) for write access.
1. Write 55H to the Watchdog Timer Control register (WDTCTL).
2. Write AAH to the Watchdog Timer Control register (WDTCTL).
3. Write the Watchdog Timer Reload Upper Byte register (WDTU).
4. Write the Watchdog Timer Reload High Byte register (WDTH).
PS019919-1207
Watchdog Timer
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
100
5. Write the Watchdog Timer Reload Low Byte register (WDTL).
All steps of the Watchdog Timer Reload Unlock sequence must be written in the order just
listed. There must be no other register writes between each of these operations. If a register write occurs, the lock state machine resets and no further writes can occur, unless the
sequence is restarted. The value in the Watchdog Timer Reload registers is loaded into the
counter when the Watchdog Timer is first enabled and every time a WDT instruction is
executed.
Watchdog Timer Control Register Definitions
Watchdog Timer Control Register
The Watchdog Timer Control (WDTCTL) register (Table 48) is a Read-Only register that
indicates the source of the most recent Reset event, indicates a Stop Mode Recovery event,
and indicates a Watchdog Timer time-out. Reading this register resets the upper four bits
to 0.
Writing the 55H, AAH unlock sequence to the Watchdog Timer Control (WDTCTL) register address unlocks the three Watchdog Timer Reload Byte registers (WDTU, WDTH, and
WDTL) to allow changes to the time-out period. These write operations to the WDTCTL
register address produce no effect on the bits in the WDTCTL register. The locking mechanism prevents spurious writes to the Reload registers.
Table 48. Watchdog Timer Control Register (WDTCTL)
BITS
FIELD
7
6
5
4
POR
STOP
WDT
EXT
RESET
3
1
0
Reserved
See descriptions below
SM
0
R
R/W
FF0H
ADDR
PS019919-1207
2
Reset or Stop Mode Recovery Event
POR
STOP WDT
EXT
Power-On Reset
1
0
0
0
Reset using RESET pin assertion
0
0
0
1
Reset using Watchdog Timer time-out
0
0
1
0
Reset using the On-Chip Debugger (OCDCTL[1] set to 1) 1
0
0
0
Reset from STOP Mode using DBG Pin driven Low
1
0
0
0
Stop Mode Recovery using GPIO pin transition
0
1
0
0
Stop Mode Recovery using Watchdog Timer time-out
0
1
1
0
Watchdog Timer
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
101
POR—Power-On Reset Indicator
If this bit is set to 1, a Power-On Reset event occurred. This bit is reset to 0 if a WDT timeout or Stop Mode Recovery occurs. This bit is also reset to 0 when the register is read.
STOP—Stop Mode Recovery Indicator
If this bit is set to 1, a Stop Mode Recovery occurred. If the STOP and WDT bits are both
set to 1, the Stop Mode Recovery occurred due to a WDT time-out. If the STOP bit is 1
and the WDT bit is 0, the Stop Mode Recovery was not caused by a WDT time-out. This bit
is reset by a Power-On Reset or a WDT time-out that occurred while not in STOP mode.
Reading this register also resets this bit.
WDT—Watchdog Timer Time-Out Indicator
If this bit is set to 1, a WDT time-out occurred. A Power-On Reset resets this pin. A Stop
Mode Recovery from a change in an input pin also resets this bit. Reading this register
resets this bit.
EXT—External Reset Indicator
If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A Power-On
Reset or a Stop Mode Recovery from a change in an input pin resets this bit. Reading this
register resets this bit.
Reserved
These bits are reserved and must be 0.
SM—STOP Mode Configuration Indicator
0 = Watchdog Timer and its internal RC oscillator will continue to operate in STOP Mode.
1 = Watchdog Timer and its internal RC oscillator will be disabled in STOP Mode.
Watchdog Timer Reload Upper, High and Low Byte Registers
The Watchdog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) registers (see Table 49 on page 102 through Table 51 on page 102) form the 24-bit reload value
that is loaded into the Watchdog Timer when a WDT instruction executes. The 24-bit
reload value is {WDTU[7:0], WDTH[7:0], WDTL[7:0]}. Writing to these registers sets
the desired Reload Value. Reading from these registers returns the current Watchdog
Timer count value.
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Watchdog Timer
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
102
Caution: The 24-bit WDT Reload Value must not be set to a value less than 000004H.
Table 49. Watchdog Timer Reload Upper Byte Register (WDTU)
BITS
7
6
5
4
3
FIELD
WDTU
RESET
1
R/W
R/W*
ADDR
FF1H
2
1
0
1
0
Note: R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
WDTU—WDT Reload Upper Byte
Most significant byte, Bits[23:16], of the 24-bit WDT reload value.
Table 50. Watchdog Timer Reload High Byte Register (WDTH)
BITS
7
6
5
4
3
FIELD
WDTH
RESET
1
R/W
R/W*
ADDR
FF2H
2
Note: R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
WDTH—WDT Reload High Byte
Middle byte, Bits[15:8], of the 24-bit WDT reload value.
Table 51. Watchdog Timer Reload Low Byte Register (WDTL)
BITS
7
6
5
4
3
FIELD
WDTL
RESET
1
R/W
R/W*
ADDR
FF3H
2
1
0
Note: R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
WDTL—WDT Reload Low
Least significant byte, Bits[7:0], of the 24-bit WDT reload value.
PS019919-1207
Watchdog Timer
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
103
UART
Overview
The Universal Asynchronous Receiver/Transmitter (UART) is a full-duplex communication channel capable of handling asynchronous data transfers. The UART uses a single
8-bit data mode with selectable parity. Features of the UART include:
•
•
•
•
•
•
•
•
•
•
8-bit asynchronous data transfer
Selectable even- and odd-parity generation and checking
Option of one or two Stop bits
Separate transmit and receive interrupts
Framing, parity, overrun and break detection
Separate transmit and receive enables
16-bit Baud Rate Generator (BRG)
Selectable MULTIPROCESSOR (9-bit) mode with three configurable interrupt
schemes
Baud Rate Generator timer mode
Driver Enable output for external bus transceivers
Architecture
The UART consists of three primary functional blocks: Transmitter, Receiver, and Baud
rate generator. The UART’s transmitter and receiver function independently, but employ
the same baud rate and data format. Figure 13 on page 104 displays the UART architecture.
PS019919-1207
UART
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
104
Parity Checker
Receiver Control
with address compare
RXD
Receive Shifter
Receive Data
Register
Control Registers
System Bus
Transmit Data
Register
Status Register
Baud Rate
Generator
Transmit Shift
Register
TXD
Transmitter Control
Parity Generator
CTS
DE
Figure 13. UART Block Diagram
Operation
Data Format
The UART always transmits and receives data in an 8-bit data format, least-significant bit
first. An even or odd parity bit can be optionally added to the data stream. Each character
begins with an active Low Start bit and ends with either 1 or 2 active High Stop bits.
Figure 14 and Figure 15 on page 105 displays the asynchronous data format employed by
the UART without parity and with parity, respectively.
PS019919-1207
UART
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
105
1
Stop Bit(s)
Data Field
Idle State
of Line
lsb
Start
msb
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
0
1
2
Figure 14. UART Asynchronous Data Format without Parity
1
Stop Bit(s)
Data Field
Idle State
of Line
lsb
Start
Bit0
msb
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Parity
0
1
2
Figure 15. UART Asynchronous Data Format with Parity
Transmitting Data using the Polled Method
Follow the steps below to transmit data using the polled method of operation:
1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. If MULTIPROCESSOR mode is desired, write to the UART Control 1 register to
enable MULTIPROCESSOR (9-bit) mode functions.
– Set the MULTIPROCESSOR Mode Select (MPEN) to Enable
MULTIPROCESSOR mode.
4. Write to the UART Control 0 register to:
– Set the transmit enable bit (TEN) to enable the UART for data transmission
– If parity is desired and MULTIPROCESSOR mode is not enabled, set the parity
enable bit (PEN) and select either Even or Odd parity (PSEL).
PS019919-1207
UART
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
106
–
Set or clear the CTSE bit to enable or disable control from the remote receiver
using the CTS pin.
5. Check the TDRE bit in the UART Status 0 register to determine if the Transmit Data
register is empty (indicated by a 1). If empty, continue to step 6. If the Transmit Data
register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit
Data register becomes available to receive new data.
6. Write the UART Control 1 register to select the outgoing address bit.
7. Set the MULTIPROCESSOR Bit Transmitter (MPBT) if sending an address byte, clear
it if sending a data byte.
8. Write the data byte to the UART Transmit Data register. The transmitter automatically
transfers the data to the Transmit Shift register and transmits the data.
9. If desired and MULTIPROCESSOR mode is enabled, make any changes to the
MULTIPROCESSOR Bit Transmitter (MPBT) value.
10. To transmit additional bytes, return to step 5.
Transmitting Data using the Interrupt-Driven Method
The UART transmitter interrupt indicates the availability of the Transmit Data register to
accept new data for transmission. Follow the steps below to configure the UART for interrupt-driven data transmission:
1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the UART Transmitter interrupt and
set the desired priority.
5. If MULTIPROCESSOR mode is desired, write to the UART Control 1 register to
enable MULTIPROCESSOR (9-bit) mode functions.
6. Set the MULTIPROCESSOR Mode Select (MPEN) to Enable MULTIPROCESSOR
mode.
7. Write to the UART Control 0 register to:
– Set the transmit enable bit (TEN) to enable the UART for data transmission.
– Enable parity, if desired and if MULTIPROCESSOR mode is not enabled, and
select either even or odd parity.
– Set or clear the CTSE bit to enable or disable control from the remote receiver via
the CTS pin.
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Z8 Encore! XP® 64K Series Flash Microcontrollers
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8. Execute an EI instruction to enable interrupts.
The UART is now configured for interrupt-driven data transmission. Because the UART
Transmit Data register is empty, an interrupt is generated immediately. When the UART
Transmit interrupt is detected, the associated interrupt service routine performs the following:
1. Write the UART Control 1 register to select the outgoing address bit:
– Set the MULTIPROCESSOR Bit Transmitter (MPBT) if sending an address byte,
clear it if sending a data byte.
2. Write the data byte to the UART Transmit Data register. The transmitter automatically
transfers the data to the Transmit Shift register and transmits the data.
3. Clear the UART Transmit interrupt bit in the applicable Interrupt Request register.
4. Execute the IRET instruction to return from the interrupt-service routine and wait for
the Transmit Data register to again become empty.
Receiving Data using the Polled Method
Follow the steps below to configure the UART for polled data reception:
1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. Write to the UART Control 1 register to enable MULTIPROCESSOR mode functions,
if desired.
4. Write to the UART Control 0 register to:
– Set the receive enable bit (REN) to enable the UART for data reception.
– Enable parity, if desired and if MULTIPROCESSOR mode is not enabled, and
select either even or odd parity.
5. Check the RDA bit in the UART Status 0 register to determine if the Receive Data
register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indicate
available data, continue to step 6. If the Receive Data register is empty (indicated by a
0), continue to monitor the RDA bit awaiting reception of the valid data.
6. Read data from the UART Receive Data register. If operating in MULTIPROCESSOR
(9-bit) mode, further actions may be required depending on the MULTIPROCESSOR
Mode bits MPMD[1:0].
7. Return to step 5 to receive additional data.
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Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
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Receiving Data using the Interrupt-Driven Method
The UART Receiver interrupt indicates the availability of new data (as well as error conditions). Follow the steps below to configure the UART receiver for interrupt-driven operation:
1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set
the desired priority.
5. Clear the UART Receiver interrupt in the applicable Interrupt Request register.
6. Write to the UART Control 1 Register to enable MULTIPROCESSOR (9-bit) mode
functions, if desired.
– Set the MULTIPROCESSOR Mode Select (MPEN) to Enable
MULTIPROCESSOR mode.
– Set the MULTIPROCESSOR Mode Bits, MPMD[1:0], to select the desired
address matching scheme.
– Configure the UART to interrupt on received data and errors or errors only
(interrupt on errors only is unlikely to be useful for Z8 Encore! devices without a
DMA block).
7. Write the device address to the Address Compare Register (automatic multiprocessor
modes only).
8. Write to the UART Control 0 register to:
– Set the receive enable bit (REN) to enable the UART for data reception.
– Enable parity, if desired and if MULTIPROCESSOR mode is not enabled, and
select either even or odd parity.
9. Execute an EI instruction to enable interrupts.
The UART is now configured for interrupt-driven data reception. When the UART
Receiver interrupt is detected, the associated interrupt service routine performs the following:
1. Check the UART Status 0 register to determine the source of the interrupt - error,
break, or received data.
2. If the interrupt was caused by data available, read the data from the UART Receive
Data register. If operating in MULTIPROCESSOR (9-bit) mode, further actions may
be required depending on the MULTIPROCESSOR Mode bits MPMD[1:0].
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Product Specification
109
3. Clear the UART Receiver interrupt in the applicable Interrupt Request register.
4. Execute the IRET instruction to return from the interrupt-service routine and await
more data.
Clear To Send (CTS) Operation
The CTS pin, if enabled by the CTSE bit of the UART Control 0 register, performs flow
control on the outgoing transmit datastream. The Clear To Send (CTS) input pin is sampled one system clock before beginning any new character transmission. To delay transmission of the next data character, an external receiver must deassert CTS at least one
system clock cycle before a new data transmission begins. For multiple character transmissions, this would typically be done during Stop Bit transmission. If CTS deasserts in
the middle of a character transmission, the current character is sent completely.
MULTIPROCESSOR (9-bit) Mode
The UART has a MULTIPROCESSOR (9-bit) mode that uses an extra (9th) bit for selective communication when a number of processors share a common UART bus. In MULTIPROCESSOR mode (also referred to as 9-Bit mode), the multiprocessor bit (MP) is
transmitted immediately following the 8-bits of data and immediately preceding the Stop
bit(s) as displayed in Figure 16. The character format is:
1
Stop Bit(s)
Data Field
Idle State
of Line
lsb
Start
Bit0
msb
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
MP
0
1
2
Figure 16. UART Asynchronous MULTIPROCESSOR Mode Data Format
In MULTIPROCESSOR (9-bit) mode, the Parity bit location (9th bit) becomes the MULTIPROCESSOR control bit. The UART Control 1 and Status 1 registers provide MULTIPROCESSOR (9-bit) mode control and status information. If an automatic address
matching scheme is enabled, the UART Address Compare register holds the network
address of the device.
MULTIPROCESSOR (9-bit) Mode Receive Interrupts
When MULTIPROCESSOR mode is enabled, the UART only processes frames addressed
to it. The determination of whether a frame of data is addressed to the UART can be made
in hardware, software or some combination of the two, depending on the multiprocessor
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110
configuration bits. In general, the address compare feature reduces the load on the CPU,
since it does not need to access the UART when it receives data directed to other devices
on the multi-node network. The following three MULTIPROCESSOR modes are available in hardware:
•
•
•
Interrupt on all address bytes.
Interrupt on matched address bytes and correctly framed data bytes.
Interrupt only on correctly framed data bytes.
These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all
MULTIPROCESSOR modes, bit MPEN of the UART Control 1 Register must be set to 1.
The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming
address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt
service routine must manually check the address byte that caused triggered the interrupt. If
it matches the UART address, the software clears MPMD[0]. At this point, each new
incoming byte interrupts the CPU. The software is then responsible for determining the
end of the frame. It checks for end-of-frame by reading the MPRX bit of the UART Status
1 Register for each incoming byte. If MPRX=1, a new frame has begun. If the address of
this new frame is different from the UART’s address, then set MPMD[0] to 1 causing the
UART interrupts to go inactive until the next address byte. If the new frame’s address
matches the UART’s, the data in the new frame is processed as well.
The second scheme is enabled by setting MPMD[1:0] to 10b and writing the UART’s
address into the UART Address Compare Register. This mode introduces more hardware
control, interrupting only on frames that match the UART’s address. When an incoming
address byte does not match the UART’s address, it is ignored. All successive data bytes in
this frame are also ignored. When a matching address byte occurs, an interrupt is issued
and further interrupts now occur on each successive data byte. The first data byte in the
frame contains the NEWFRM=1 in the UART Status 1 Register. When the next address byte
occurs, the hardware compares it to the UART’s address. If there is a match, the interrupts
continue sand the NEWFRM bit is set for the first byte of the new frame. If there is no
match, then the UART ignores all incoming bytes until the next address match.
The third scheme is enabled by setting MPMD[1:0] to 11b and by writing the UART’s
address into the UART Address Compare Register. This mode is identical to the second
scheme, except that there are no interrupts on address bytes. The first data byte of each
frame is still accompanied by a NEWFRM assertion.
External Driver Enable
The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This feature
reduces the software overhead associated with using a GPIO pin to control the transceiver
when communicating on a multi-transceiver bus, such as RS-485.
Driver Enable is an active High signal that envelopes the entire transmitted data frame
including parity and Stop bits as displayed in Figure 17. The Driver Enable signal asserts
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when a byte is written to the UART Transmit Data register. The Driver Enable signal
asserts at least one UART bit period and no greater than two UART bit periods before the
Start bit is transmitted. This timing allows a setup time to enable the transceiver. The
Driver Enable signal deasserts one system clock period after the last Stop bit is transmitted. This one system clock delay allows both time for data to clear the transceiver before
disabling it, as well as the ability to determine if another character follows the current
character. In the event of back to back characters (new data must be written to the Transmit Data Register before the previous character is completely transmitted) the DE signal is
not deasserted between characters. The DEPOL bit in the UART Control Register 1 sets the
polarity of the Driver Enable signal.
1
DE
0
1
Data Field
Idle State
of Line
Stop Bit
lsb
Start
Bit0
msb
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Parity
0
1
Figure 17. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
The Driver Enable to Start bit setup time is calculated as follows:
1
2
------------------------------------ ≤ DE to Start Bit Setup Time (s) ≤ ------------------------------------
Baud Rate (Hz)
Baud Rate (Hz)
UART Interrupts
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the Baud Rate Generator can also function as a basic timer with interrupt capability.
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for transmission. The TDRE interrupt occurs after the Transmit shift register has shifted the first bit
of data out. At this point, the Transmit Data register may be written with the next character
to send. This provides 7 bit periods of latency to load the Transmit Data register before the
Transmit shift register completes shifting the current character. Writing to the UART
Transmit Data register clears the TDRE bit to 0.
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Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
•
A data byte has been received and is available in the UART Receive Data register.
This interrupt can be disabled independent of the other receiver interrupt sources. The
received data interrupt occurs once the receive character has been received and placed
in the Receive Data register. Software must respond to this received data available
condition before the next character is completely received to avoid an overrun error.
Note: In MULTIPROCESSOR mode (MPEN = 1), the receive data interrupts are dependent on
the multiprocessor configuration and the most recent address byte.
•
•
•
A break is received
An overrun is detected
A data framing error is detected
UART Overrun Errors
When an overrun error condition occurs the UART prevents overwriting of the valid data
currently in the Receive Data register. The Break Detect and Overrun status bits are not
displayed until after the valid data has been read.
After the valid data has been read, the UART Status 0 register is updated to indicate the
overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that
the Receive Data register contains a data byte. However, because the overrun error
occurred, this byte may not contain valid data and should be ignored. The BRKD bit indicates if the overrun was caused by a break condition on the line. After reading the status
byte indicating an overrun error, the Receive Data register must be read again to clear the
error bits is the UART Status 0 register. Updates to the Receive Data register occur only
when the next data word is received.
UART Data and Error Handling Procedure
Figure 18 on page 113 displays the recommended procedure for use in UART receiver
interrupt service routines.
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113
Receiver
Ready
Receiver
Interrupt
Read Status
No
Errors?
Yes
Read Data which
clears RDA bit and
resets error bits
Read Data
Discard Data
Figure 18. UART Receiver Interrupt Service Routine Flow
Baud Rate Generator Interrupts
If the Baud Rate Generator interrupt enable is set, the UART Receiver interrupt asserts
when the UART Baud Rate Generator reloads. This action allows the Baud Rate Generator to function as an additional counter if the UART functionality is not employed.
UART Baud Rate Generator
The UART Baud Rate Generator creates a lower frequency baud rate clock for data transmission. The input to the Baud Rate Generator is the system clock. The UART Baud Rate
High and Low Byte registers combine to create a 16-bit baud rate divisor value
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(BRG[15:0]) that sets the data transmission rate (baud rate) of the UART. The UART data
rate is calculated using the following equation:
System Clock Frequency (Hz)
UART Data Rate (bits/s) = -----------------------------------------------------------------------------------------16 × UART Baud Rate Divisor Value
When the UART is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 register
to 0.
2. Load the desired 16-bit count value into the UART Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BRGCTL bit in the UART Control 1 register to 1.
When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval ( s ) = System Clock Period (s) × BRG [ 15:0 ]
UART Control Register Definitions
The UART control registers support the UART and the associated Infrared Encoder/
Decoders. For more information on the infrared operation, see Infrared Encoder/Decoder
on page 125.
UART Transmit Data Register
Data bytes written to the UART Transmit Data register (Table 52) are shifted out on the
TXDx pin. The Write-only UART Transmit Data register shares a Register File address
with the Read-only UART Receive Data register.
Table 52. UART Transmit Data Register (UxTXD)
BITS
7
6
5
4
3
FIELD
TXD
RESET
X
R/W
W
ADDR
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F40H and F48H
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TXD—Transmit Data
UART transmitter data byte to be shifted out through the TXDx pin.
UART Receive Data Register
Data bytes received through the RXDx pin are stored in the UART Receive Data register
(Table 53). The Read-only UART Receive Data register shares a Register File address
with the Write-only UART Transmit Data register.
Table 53. UART Receive Data Register (UxRXD)
BITS
7
6
5
4
3
FIELD
RXD
RESET
X
R/W
R
2
1
0
F40H and F48H
ADDR
RXD—Receive Data
UART receiver data byte from the RXDx pin
UART Status 0 Register
The UART Status 0 and Status 1 registers (Table 54 and Table 55 on page 117) identify the
current UART operating configuration and status.
Table 54. UART Status 0 Register (UxSTAT0)
BITS
FIELD
7
6
5
4
3
2
1
0
RDA
PE
OE
FE
BRKD
TDRE
TXE
CTS
1
X
RESET
R/W
ADDR
0
R
F41H and F49H
RDA—Receive Data Available
This bit indicates that the UART Receive Data register has received data. Reading the
UART Receive Data register clears this bit.
0 = The UART Receive Data register is empty.
1 = There is a byte in the UART Receive Data register.
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PE—Parity Error
This bit indicates that a parity error has occurred. Reading the UART Receive Data register clears this bit.
0 = No parity error occurred.
1 = A parity error occurred.
OE—Overrun Error
This bit indicates that an overrun error has occurred. An overrun occurs when new data is
received and the UART Receive Data register has not been read. If the RDA bit is reset to
0, then reading the UART Receive Data register clears this bit.
0 = No overrun error occurred.
1 = An overrun error occurred.
FE—Framing Error
This bit indicates that a framing error (no Stop bit following data reception) was detected.
Reading the UART Receive Data register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
BRKD—Break Detect
This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and Stop
bit(s) are all zeros then this bit is set to 1. Reading the UART Receive Data register clears
this bit.
0 = No break occurred.
1 = A break occurred.
TDRE—Transmitter Data Register Empty
This bit indicates that the UART Transmit Data register is empty and ready for additional
data. Writing to the UART Transmit Data register resets this bit.
0 = Do not write to the UART Transmit Data register.
1 = The UART Transmit Data register is ready to receive an additional byte to be transmitted.
TXE—Transmitter Empty
This bit indicates that the transmit shift register is empty and character transmission is finished.
0 = Data is currently transmitting.
1 = Transmission is complete.
CTS—CTS signal
When this bit is read it returns the level of the CTS signal.
UART Status 1 Register
This register contains multiprocessor control and status bits.
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Table 55. UART Status 1 Register (UxSTAT1)
BITS
7
6
5
4
3
2
Reserved
FIELD
1
0
NEWFRM
MPRX
0
RESET
R
R/W
R/W
R
F44H and F4CH
ADDR
Reserved—Must be 0.
NEWFRM—Status bit denoting the start of a new frame. Reading the UART Receive
Data register resets this bit to 0.
0 = The current byte is not the first data byte of a new frame.
1 = The current byte is the first data byte of a new frame.
MPRX—Multiprocessor Receive
Returns the value of the last multiprocessor bit received. Reading from the UART Receive
Data register resets this bit to 0.
UART Control 0 and Control 1 Registers
The UART Control 0 and Control 1 registers (see Table 56 and Table 57 on page 118) configure the properties of the UART’s transmit and receive operations. The UART Control
registers must not been written while the UART is enabled.
Table 56. UART Control 0 Register (UxCTL0)
BITS
FIELD
7
6
5
4
3
2
1
0
TEN
REN
CTSE
PEN
PSEL
SBRK
STOP
LBEN
RESET
R/W
ADDR
0
R/W
F42H and F4AH
TEN—Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is
enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
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REN—Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
CTSE—CTS Enable
0 = The CTS signal has no effect on the transmitter.
1 = The UART recognizes the CTS signal as an enable control from the transmitter.
PEN—Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit. It is overridden by the MPEN bit.
0 = Parity is disabled.
1 = The transmitter sends data with an additional parity bit and the receiver receives an
additional parity bit.
PSEL—Parity Select
0 = Even parity is transmitted and expected on all received data.
1 = Odd parity is transmitted and expected on all received data.
SBRK—Send Break
This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so ensure that the transmitter has finished sending data before setting this bit.
0 = No break is sent.
1 = The output of the transmitter is zero.
STOP—Stop Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
LBEN—Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver.
Table 57. UART Control 1 Register (UxCTL1)
BITS
FIELD
7
6
5
4
3
2
1
0
MPMD[1]
MPEN
MPMD[0]
MPBT
DEPOL
BRGCTL
RDAIRQ
IREN
RESET
R/W
ADDR
0
R/W
F43H and F4BH
MPMD[1:0]—MULTIPROCESSOR Mode
If MULTIPROCESSOR (9-bit) mode is enabled,
00 = The UART generates an interrupt request on all received bytes (data and address).
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01 = The UART generates an interrupt request only on received address bytes.
10 = The UART generates an interrupt request when a received address byte matches
the value stored in the Address Compare Register and on all successive data
bytes until an address mismatch occurs.
11 = The UART generates an interrupt request on all received data bytes for which
the most recent address byte matched the value in the Address Compare Register.
MPEN—MULTIPROCESSOR (9-bit) Enable
This bit is used to enable MULTIPROCESSOR (9-bit) mode.
0 = Disable MULTIPROCESSOR (9-bit) mode.
1 = Enable MULTIPROCESSOR (9-bit) mode.
MPBT—MULTIPROCESSOR Bit Transmit
This bit is applicable only when MULTIPROCESSOR (9-bit) mode is enabled.
0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit).
1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit).
DEPOL—Driver Enable Polarity
0 = DE signal is Active High.
1 = DE signal is Active Low.
BRGCTL—Baud Rate Control
This bit causes different UART behavior depending on whether the UART receiver is
enabled (REN = 1 in the UART Control 0 Register).
When the UART receiver is not enabled, this bit determines whether the Baud Rate Generator issues interrupts.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value
1 = The Baud Rate Generator generates a receive interrupt when it counts down to 0.
Reads from the Baud Rate High and Low Byte registers return the current BRG count
value.
When the UART receiver is enabled, this bit allows reads from the Baud Rate Registers to
return the BRG count value instead of the Reload Value.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value.
1 = Reads from the Baud Rate High and Low Byte registers return the current BRG
count value. Unlike the Timers, there is no mechanism to latch the High Byte
when the Low Byte is read.
RDAIRQ—Receive Data Interrupt Enable
0 = Received data and receiver errors generates an interrupt request to the Interrupt
Controller.
1 = Received data does not generate an interrupt request to the Interrupt Controller.
Only receiver errors generate an interrupt request.
IREN—Infrared Encoder/Decoder Enable
0 = Infrared Encoder/Decoder is disabled. UART operates normally operation.
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1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data
through the Infrared Encoder/Decoder.
UART Address Compare Register
The UART Address Compare register (Table 58) stores the multi-node network address of
the UART. When the MPMD[1] bit of UART Control Register 0 is set, all incoming
address bytes are compared to the value stored in the Address Compare register. Receive
interrupts and RDA assertions only occur in the event of a match.
Table 58. UART Address Compare Register (UxADDR)
BITS
7
6
5
4
3
FIELD
COMP_ADDR
RESET
0
2
1
0
R/W
R/W
F45H and F4DH
ADDR
COMP_ADDR—Compare Address
This 8-bit value is compared to the incoming address bytes.
UART Baud Rate High and Low Byte Registers
The UART Baud Rate High and Low Byte registers (see Table 59 and Table 60 on
page 121) combine to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data
transmission rate (baud rate) of the UART. To configure the Baud Rate Generator as a
timer with interrupt on time-out, complete the following procedure:
1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 register
to 0.
2. Load the desired 16-bit count value into the UART Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BRGCTL bit in the UART Control 1 register to 1.
When configured as a general purpose timer, the UART BRG interrupt interval is calculated using the following equation:
UART BRG Interrupt Interval ( s ) = System Clock Period (s) × BRG [ 15:0 ]
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Table 59. UART Baud Rate High Byte Register (UxBRH)
BITS
7
6
5
4
3
FIELD
BRH
RESET
1
2
1
0
2
1
0
R/W
R/W
F46H and F4EH
ADDR
Table 60. UART Baud Rate Low Byte Register (UxBRL)
BITS
7
6
5
4
3
FIELD
BRL
RESET
1
R/W
ADDR
R/W
F47H and F4FH
For a given UART data rate, the integer baud rate divisor value is calculated using the
following equation:
System Clock Frequency (Hz)
UART Baud Rate Divisor Value (BRG) = Round ------------------------------------------------------------------------
16 × UART Data Rate (bits/s)
The baud rate error relative to the desired baud rate is calculated using the following
equation:
Actual Data Rate – Desired Data Rate
UART Baud Rate Error (%) = 100 × -------------------------------------------------------------------------------------------
Desired Data Rate
For reliable communication, the UART baud rate error must never exceed 5 percent.
Table 61 provides information on data rate errors for popular baud rates and commonly
used crystal oscillator frequencies.
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Table 61. UART Baud Rates
20.0 MHz System Clock
18.432 MHz System Clock
Desired Rate BRG Divisor Actual Rate Error
Desired
Rate
BRG
Divisor
Actual Rate Error
(kHz)
(Decimal)
(kHz)
(%)
(kHz)
(Decimal)
(kHz)
(%)
1250.0
1
1250.0
0.00
1250.0
1
1152.0
-7.84%
625.0
2
625.0
0.00
625.0
2
576.0
-7.84%
250.0
5
250.0
0.00
250.0
5
230.4
-7.84%
115.2
11
113.6
-1.36
115.2
10
115.2
0.00
57.6
22
56.8
-1.36
57.6
20
57.6
0.00
38.4
33
37.9
-1.36
38.4
30
38.4
0.00
19.2
65
19.2
0.16
19.2
60
19.2
0.00
9.60
130
9.62
0.16
9.60
120
9.60
0.00
4.80
260
4.81
0.16
4.80
240
4.80
0.00
2.40
521
2.40
-0.03
2.40
480
2.40
0.00
1.20
1042
1.20
-0.03
1.20
960
1.20
0.00
0.60
2083
0.60
0.02
0.60
1920
0.60
0.00
0.30
4167
0.30
-0.01
0.30
3840
0.30
0.00
16.667 MHz System Clock
11.0592 MHz System Clock
Desired Rate BRG Divisor Actual Rate Error
Desired
Rate
BRG
Divisor
Actual Rate Error
(kHz)
(Decimal)
(kHz)
(%)
(kHz)
(Decimal)
(kHz)
(%)
1250.0
1
1041.69
-16.67
1250.0
N/A
N/A
N/A
625.0
2
520.8
-16.67
625.0
1
691.2
10.59
250.0
4
260.4
4.17
250.0
3
230.4
-7.84
115.2
9
115.7
0.47
115.2
6
115.2
0.00
57.6
18
57.87
0.47
57.6
12
57.6
0.00
38.4
27
38.6
0.47
38.4
18
38.4
0.00
19.2
54
19.3
0.47
19.2
36
19.2
0.00
9.60
109
9.56
-0.45
9.60
72
9.60
0.00
4.80
217
4.80
-0.83
4.80
144
4.80
0.00
2.40
434
2.40
0.01
2.40
288
2.40
0.00
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123
Table 61. UART Baud Rates (Continued)
1.20
868
1.20
0.01
1.20
576
1.20
0.00
0.60
1736
0.60
0.01
0.60
1152
0.60
0.00
0.30
3472
0.30
0.01
0.30
2304
0.30
0.00
10.0 MHz System Clock
5.5296 MHz System Clock
Desired Rate BRG Divisor Actual Rate Error
Desired
Rate
BRG
Divisor
Actual Rate Error
(kHz)
(Decimal)
(kHz)
(%)
(kHz)
(Decimal)
(kHz)
(%)
1250.0
N/A
N/A
N/A
1250.0
N/A
N/A
N/A
625.0
1
625.0
0.00
625.0
N/A
N/A
N/A
250.0
3
208.33
-16.67
250.0
1
345.6
38.24
115.2
5
125.0
8.51
115.2
3
115.2
0.00
57.6
11
56.8
-1.36
57.6
6
57.6
0.00
38.4
16
39.1
1.73
38.4
9
38.4
0.00
19.2
33
18.9
0.16
19.2
18
19.2
0.00
9.60
65
9.62
0.16
9.60
36
9.60
0.00
4.80
130
4.81
0.16
4.80
72
4.80
0.00
2.40
260
2.40
-0.03
2.40
144
2.40
0.00
1.20
521
1.20
-0.03
1.20
288
1.20
0.00
0.60
1042
0.60
-0.03
0.60
576
0.60
0.00
0.30
2083
0.30
0.2
0.30
1152
0.30
0.00
3.579545 MHz System Clock
1.8432 MHz System Clock
Desired Rate BRG Divisor Actual Rate Error
Desired
Rate
BRG
Divisor
Actual Rate Error
(kHz)
(Decimal)
(kHz)
(%)
(kHz)
(Decimal)
(kHz)
(%)
1250.0
N/A
N/A
N/A
1250.0
N/A
N/A
N/A
625.0
N/A
N/A
N/A
625.0
N/A
N/A
N/A
250.0
1
223.72
-10.51
250.0
N/A
N/A
N/A
115.2
2
111.9
-2.90
115.2
1
115.2
0.00
57.6
4
55.9
-2.90
57.6
2
57.6
0.00
38.4
6
37.3
-2.90
38.4
3
38.4
0.00
19.2
12
18.6
-2.90
19.2
6
19.2
0.00
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Table 61. UART Baud Rates (Continued)
9.60
23
9.73
1.32
9.60
12
9.60
0.00
4.80
47
4.76
-0.83
4.80
24
4.80
0.00
2.40
93
2.41
0.23
2.40
48
2.40
0.00
1.20
186
1.20
0.23
1.20
96
1.20
0.00
0.60
373
0.60
-0.04
0.60
192
0.60
0.00
0.30
746
0.30
-0.04
0.30
384
0.30
0.00
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Infrared Encoder/Decoder
Overview
The 64K Series products contain two fully-functional, high-performance UART to Infrared Encoder/Decoders (Endecs). Each Infrared Endec is integrated with an on-chip UART
to allow easy communication between the 64K Series and IrDA Physical Layer Specification, Version 1.3-compliant infrared transceivers. Infrared communication provides
secure, reliable, low-cost, point-to-point communication between PCs, PDAs, cell phones,
printers, and other infrared enabled devices.
Architecture
Figure 19 displays the architecture of the Infrared Endec.
System
Clock
RxD
TxD
UART
Interrupt
I/O
Signal Address
Baud Rate
Clock
RXD
Infrared
Encoder/Decoder
(Endec)
TXD
Zilog
ZHX1810
RXD
TXD
Infrared
Transceiver
Data
Figure 19. Infrared Data Communication System Block Diagram
PS019919-1207
Infrared Encoder/Decoder
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Operation
When the Infrared Endec is enabled, the transmit data from the associated on-chip UART
is encoded as digital signals in accordance with the IrDA standard and output to the infrared transceiver via the TXD pin. Likewise, data received from the infrared transceiver is
passed to the Infrared Endec via the RXD pin, decoded by the Infrared Endec, and then
passed to the UART. Communication is half-duplex, which means simultaneous data
transmission and reception is not allowed.
The baud rate is set by the UART’s Baud Rate Generator and supports IrDA standard baud
rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet
IrDA specifications. The UART must be enabled to use the Infrared Endec. The Infrared
Endec data rate is calculated using the following equation:
System Clock Frequency (Hz)
Infrared Data Rate (bits/s) = -----------------------------------------------------------------------------------------16 × UART Baud Rate Divisor Value
Transmitting IrDA Data
The data to be transmitted using the infrared transceiver is first sent to the UART. The
UART’s transmit signal (TXD) and baud rate clock are used by the IrDA to generate the
modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared
data bit is 16-clock wide. If the data to be transmitted is 1, the IR_TXD signal remains low
for the full 16-clock period. If the data to be transmitted is 0, a 3-clock high pulse is output
following a 7-clock low period. After the 3-clock high pulse, a 6-clock low pulse is output
to complete the full 16-clock data period. Figure 20 displays IrDA data transmission.
When the Infrared Endec is enabled, the UART’s TXD signal is internal to the 64K Series
products while the IR_TXD signal is output through the TXD pin.
16-clock
period
Baud Rate
Clock
UART’s
TXD
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
3-clock
pulse
IR_TXD
7-clock
delay
Figure 20. Infrared Data Transmission
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Receiving IrDA Data
Data received from the infrared transceiver via the IR_RXD signal through the RXD pin is
decoded by the Infrared Endec and passed to the UART. The UART’s baud rate clock is
used by the Infrared Endec to generate the demodulated signal (RXD) that drives the
UART. Each UART/Infrared data bit is 16-clocks wide. Figure 21 displays data reception.
When the Infrared Endec is enabled, the UART’s RXD signal is internal to the 64K Series
products while the IR_RXD signal is received through the RXD pin.
16-clock
period
Baud Rate
Clock
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_RXD
min. 1.6µs
pulse
UART’s
RXD
Start Bit = 0
8-clock
delay
16-clock
period
Data Bit 0 = 1
16-clock
period
Data Bit 1 = 0
16-clock
period
Data Bit 2 = 1
Data Bit 3 = 1
16-clock
period
Figure 21. Infrared Data Reception
Caution: The system clock frequency must be at least 1.0 MHz to ensure proper reception of the 1.6 µs minimum width pulses allowed by the IrDA standard.
Endec Receiver Synchronization
The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate
an input stream for the UART and to create a sampling window for detection of incoming
pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods
with respect to the incoming IrDA data stream. When a falling edge in the input data
stream is detected, the Endec counter is reset. When the count reaches a value of 8, the
UART RXD value is updated to reflect the value of the decoded data. When the count
reaches 12 baud clock periods, the sampling window for the next incoming pulse opens.
The window remains open until the count again reaches 8 (or in other words 24 baud clock
periods since the previous pulse was detected). This gives the Endec a sampling window
of minus four baudrate clocks to plus eight baudrate clocks around the expected time of an
incoming pulse. If an incoming pulse is detected inside this window this process is
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repeated. If the incoming data is a logical 1 (no pulse), the Endec returns to the initial state
and waits for the next falling edge. As each falling edge is detected, the Endec clock
counter is reset, resynchronizing the Endec to the incoming signal. This action allows the
Endec to tolerate jitter and baud rate errors in the incoming data stream. Resynchronizing
the Endec does not alter the operation of the UART, which ultimately receives the data.
The UART is only synchronized to the incoming data stream when a Start bit is received.
Infrared Encoder/Decoder Control Register Definitions
All Infrared Endec configuration and status information is set by the UART control registers as defined in UART Control Register Definitions on page 114.
Caution: To prevent spurious signals during IrDA data transmission, set the IREN bit
in the UARTx Control 1 register to 1 to enable the Infrared Encoder/Decoder
before enabling the GPIO Port alternate function for the corresponding pin.
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Serial Peripheral Interface
Overview
The Serial Peripheral Interface is a synchronous interface allowing several SPI-type
devices to be interconnected. SPI-compatible devices include EEPROMs, Analog-toDigital Converters, and ISDN devices. Features of the SPI include:
•
•
•
•
•
Full-duplex, synchronous, character-oriented communication
Four-wire interface
Data transfers rates up to a maximum of one-half the system clock frequency
Error detection
Dedicated Baud Rate Generator
Architecture
The SPI may be configured as either a Master (in single or multi-master systems) or a
Slave as displayed in Figure 22 through Figure 24.
SPI Master
To Slave’s SS Pin
From Slave
To Slave
To Slave
SS
MISO
8-bit Shift Register
Bit 0
Bit 7
MOSI
SCK
Baud Rate
Generator
Figure 22. SPI Configured as a Master in a Single Master, Single Slave System
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VCC
SPI Master
SS
To Slave #2’s SS Pin
GPIO
To Slave #1’s SS Pin
GPIO
8-bit Shift Register
From Slave
Bit 0
MISO
Bit 7
MOSI
To Slave
Baud Rate
Generator
SCK
To Slave
Figure 23. SPI Configured as a Master in a Single Master, Multiple Slave System
SPI Slave
From Master
To Master
From Master
From Master
SS
MISO
8-bit Shift Register
Bit 7
Bit 0
MOSI
SCK
Figure 24. SPI Configured as a Slave
Operation
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire
interface (serial clock, transmit, receive and Slave select). The SPI block consists of a
transmit/receive shift register, a Baud Rate (clock) Generator and a control unit.
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During an SPI transfer, data is sent and received simultaneously by both the Master and
the Slave SPI devices. Separate signals are required for data and the serial clock. When an
SPI transfer occurs, a multi-bit (typically 8-bit) character is shifted out one data pin and an
multi-bit character is simultaneously shifted in on a second data pin. An 8-bit shift register
in the Master and another 8-bit shift register in the Slave are connected as a circular buffer.
The SPI shift register is single-buffered in the transmit and receive directions. New data to
be transmitted cannot be written into the shift register until the previous transmission is
complete and receive data (if valid) has been read.
SPI Signals
The four basic SPI signals are:
•
•
•
•
Master-In/Slave-Out
Master-Out/Slave-In
Serial Clock
Slave Select
Each signal is described in both Master and Slave modes.
Master-In/Slave-Out
The Master-In/Slave-Out (MISO) pin is configured as an input in a Master device and as
an output in a Slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. The MISO pin of a Slave device is placed in a high-impedance
state if the Slave is not selected. When the SPI is not enabled, this signal is in a highimpedance state.
Master-Out/Slave-In
The Master-Out/Slave-In (MOSI) pin is configured as an output in a Master device and as
an input in a Slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance
state.
Serial Clock
The Serial Clock (SCK) synchronizes data movement both in and out of the device
through its MOSI and MISO pins. In MASTER mode, the SPI’s Baud Rate Generator creates the serial clock. The Master drives the serial clock out its own SCK pin to the Slave’s
SCK pin. When the SPI is configured as a Slave, the SCK pin is an input and the clock signal from the Master synchronizes the data transfer between the Master and Slave devices.
Slave devices ignore the SCK signal, unless the SS pin is asserted. When configured as a
slave, the SPI block requires a minimum SCK period of greater than or equal to 8 times
the system (XIN) clock period.
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The Master and Slave are each capable of exchanging a character of data during a
sequence of NUMBITS clock cycles (see NUMBITS field in the SPI Mode Register on
page 140). In both Master and Slave SPI devices, data is shifted on one edge of the SCK
and is sampled on the opposite edge where data is stable. Edge polarity is determined by
the SPI phase and polarity control.
Slave Select
The active Low Slave Select (SS) input signal selects a Slave SPI device. SS must be Low
prior to all data communication to and from the Slave device. SS must stay Low for the
full duration of each character transferred. The SS signal may stay Low during the transfer
of multiple characters or may deassert between each character.
When the SPI is configured as the only Master in an SPI system, the SS pin can be set as
either an input or an output. For communication between the Z8F642x family Z8R642x
family device’s SPI Master and external Slave devices, the SS signal, as an output, can
assert the SS input pin on one of the Slave devices. Other GPIO output pins can also be
employed to select external SPI Slave devices.
When the SPI is configured as one Master in a multi-master SPI system, the SS pin must
be set as an input. The SS input signal on the Master must be High. If the SS signal goes
Low (indicating another Master is driving the SPI bus), a Collision error Flag is set in the
SPI Status register.
SPI Clock Phase and Polarity Control
The SPI supports four combinations of serial clock phase and polarity using two bits in the
SPI Control register. The clock polarity bit, CLKPOL, selects an active high or active Low
clock and has no effect on the transfer format. Table 62 lists the SPI Clock Phase and
Polarity Operation parameters. The clock phase bit, PHASE, selects one of two fundamentally different transfer formats. For proper data transmission, the clock phase and polarity
must be identical for the SPI Master and the SPI Slave. The Master always places data on
the MOSI line a half-cycle before the receive clock edge (SCK signal), in order for the
Slave to latch the data.
Table 62. SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation
PS019919-1207
PHASE
CLKPOL
SCK Transmit
Edge
SCK Receive
Edge
SCK Idle
State
0
0
Falling
Rising
Low
0
1
Rising
Falling
High
1
0
Rising
Falling
Low
1
1
Falling
Rising
High
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Transfer Format PHASE Equals Zero
Figure 25 displays the timing diagram for an SPI transfer in which PHASE is cleared to 0.
The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set to
one. The diagram may be interpreted as either a Master or Slave timing diagram because
the SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly
connected between the Master and the Slave.
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MISO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Input Sample Time
SS
Figure 25. SPI Timing When PHASE is 0
Transfer Format PHASE Equals One
Figure 26 on page 134 displays the timing diagram for an SPI transfer in which PHASE is
one. Two waveforms are depicted for SCK, one for CLKPOL reset to 0 and another for
CLKPOL set to 1.
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SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MISO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Input Sample Time
SS
Figure 26. SPI Timing When PHASE is 1
Multi-Master Operation
In a multi-master SPI system, all SCK pins are tied together, all MOSI pins are tied
together and all MISO pins are tied together. All SPI pins must then be configured in
OPEN-DRAIN mode to prevent bus contention. At any one time, only one SPI device is
configured as the Master and all other SPI devices on the bus are configured as Slaves.
The Master enables a single Slave by asserting the SS pin on that Slave only. Then, the
single Master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the
Slaves (including those which are not enabled). The enabled Slave drives data out its
MISO pin to the MISO Master pin.
For a Master device operating in a multi-master system, if the SS pin is configured as an
input and is driven Low by another Master, the COL bit is set to 1 in the SPI Status Register. The COL bit indicates the occurrence of a multi-master collision (mode fault error condition).
Slave Operation
The SPI block is configured for SLAVE mode operation by setting the SPIEN bit to 1 and
the MMEN bit to 0 in the SPICTL register and setting the SSIO bit to 0 in the SPIMODE
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register. The IRQE, PHASE, CLKPOL, WOR bits in the SPICTL register and the NUMBITS field in the SPIMODE register must be set to be consistent with the other SPI
devices. The STR bit in the SPICTL register may be used if desired to force a “startup”
interrupt. The BIRQ bit in the SPICTL register and the SSV bit in the SPIMODE register
are not used in SLAVE mode. The SPI baud rate generator is not used in SLAVE mode so
the SPIBRH and SPIBRL registers need not be initialized.
If the slave has data to send to the master, the data must be written to the SPIDAT register
before the transaction starts (first edge of SCK when SS is asserted). If the SPIDAT
register is not written prior to the slave transaction, the MISO pin outputs whatever value
is currently in the SPIDAT register.
Due to the delay resulting from synchronization of the SPI input signals to the internal
system clock, the maximum SPICLK baud rate that can be supported in SLAVE mode is
the system clock frequency (XIN) divided by 8. This rate is controlled by the SPI master.
Error Detection
The SPI contains error detection logic to support SPI communication protocols and
recognize when communication errors have occurred. The SPI Status register indicates
when a data transmission error has been detected.
Overrun (Write Collision)
An overrun error (write collision) indicates a write to the SPI Data register was attempted
while a data transfer is in progress (in either MASTER or SLAVE modes). An overrun sets
the OVR bit in the SPI Status register to 1. Writing a 1 to OVR clears this error Flag. The
data register is not altered when a write occurs while data transfer is in progress.
Mode Fault (Multi-Master Collision)
A mode fault indicates when more than one Master is trying to communicate at the same
time (a multi-master collision). The mode fault is detected when the enabled Master’s SS
pin is asserted. A mode fault sets the COL bit in the SPI Status register to 1. Writing a 1 to
COL clears this error Flag.
Slave Mode Abort
In SLAVE mode of operation if the SS pin deasserts before all bits in a character have
been transferred, the transaction is aborted. When this condition occurs the ABT bit is set
in the SPISTAT register as well as the IRQ bit (indicating the transaction is complete). The
next time SS asserts, the MISO pin outputs SPIDAT[7], regardless of where the previous
transaction left off. Writing a 1 to ABT clears this error Flag.
SPI Interrupts
When SPI interrupts are enabled, the SPI generates an interrupt after character transmission/reception completes in both MASTER and SLAVE modes. A character can be
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defined to be 1 through 8 bits by the NUMBITS field in the SPI Mode register. In slave
mode it is not necessary for SS to deassert between characters to generate the interrupt.
The SPI in Slave mode can also generate an interrupt if the SS signal deasserts prior to
transfer of all the bits in a character (see description of slave abort error above). Writing a
1 to the IRQ bit in the SPI Status Register clears the pending SPI interrupt request. The
IRQ bit must be cleared to 0 by the Interrupt Service Routine to generate future interrupts.
To start the transfer process, an SPI interrupt may be forced by software writing a 1 to the
STR bit in the SPICTL register.
If the SPI is disabled, an SPI interrupt can be generated by a Baud Rate Generator timeout. This timer function must be enabled by setting the BIRQ bit in the SPICTL register.
This Baud Rate Generator time-out does not set the IRQ bit in the SPISTAT register, just
the SPI interrupt bit in the interrupt controller.
SPI Baud Rate Generator
In SPI Master mode, the Baud Rate Generator creates a lower frequency serial clock
(SCK) for data transmission synchronization between the Master and the external Slave.
The input to the Baud Rate Generator is the system clock. The SPI Baud Rate High and
Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the SPI Baud
Rate Generator. The SPI baud rate is calculated using the following equation:
System Clock Frequency (Hz)
SPI Baud Rate (bits/s) = -----------------------------------------------------------------------2 × BRG[15:0]
Minimum baud rate is obtained by setting BRG[15:0] to 0000H for a clock divisor value
of (2 X 65536 = 131072).
When the SPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. Follow the steps below to configure the Baud Rate Generator
as a timer with interrupt on time-out:
1. Disable the SPI by clearing the SPIEN bit in the SPI Control register to 0.
2. Load the desired 16-bit count value into the SPI Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BIRQ bit in the SPI Control register to 1.
When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval (s) = System Clock Period (s) × BRG[15:0]
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SPI Control Register Definitions
SPI Data Register
The SPI Data register (Table 63) stores both the outgoing (transmit) data and the incoming
(receive) data. Reads from the SPI Data register always return the current contents of the
8-bit shift register. Data is shifted out starting with bit 7. The last bit received resides in bit
position 0.
With the SPI configured as a Master, writing a data byte to this register initiates the data
transmission. With the SPI configured as a Slave, writing a data byte to this register loads
the shift register in preparation for the next data transfer with the external Master. In either
the Master or Slave modes, if a transmission is already in progress, writes to this register
are ignored and the Overrun error Flag, OVR, is set in the SPI Status register.
When the character length is less than 8 bits (as set by the NUMBITS field in the SPI Mode
register), the transmit character must be left justified in the SPI Data register. A received
character of less than 8 bits is right justified (last bit received is in bit position 0). For
example, if the SPI is configured for 4-bit characters, the transmit characters must be written to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0].
Table 63. SPI Data Register (SPIDATA)
BITS
7
6
5
4
3
FIELD
DATA
RESET
X
R/W
R/W
ADDR
F60H
2
1
0
DATA—Data
Transmit and/or receive data.
SPI Control Register
The SPI Control register (see Table 64 on page 138) configures the SPI for transmit and
receive operations.
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Table 64. SPI Control Register (SPICTL)
BITS
FIELD
7
6
5
4
3
2
1
0
IRQE
STR
BIRQ
PHASE
CLKPOL
WOR
MMEN
SPIEN
0
RESET
R/W
R/W
ADDR
F61H
IRQE—Interrupt Request Enable
0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller.
1 = SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller.
STR—Start an SPI Interrupt Request
0 = No effect.
1 = Setting this bit to 1 also sets the IRQ bit in the SPI Status register to 1. Setting this
bit forces the SPI to send an interrupt request to the Interrupt Control. This bit can
be used by software for a function similar to transmit buffer empty in a UART.
Writing a 1 to the IRQ bit in the SPI Status register clears this bit to 0.
BIRQ—BRG Timer Interrupt Request
If the SPI is enabled, this bit has no effect. If the SPI is disabled:
0 = The Baud Rate Generator timer function is disabled.
1 = The Baud Rate Generator timer function and time-out interrupt are enabled.
PHASE—Phase Select
Sets the phase relationship of the data to the clock. For more information on operation of
the PHASE bit, see SPI Clock Phase and Polarity Control on page 132.
CLKPOL—Clock Polarity
0 = SCK idles Low (0).
1 = SCK idle High (1).
WOR—Wire-OR (OPEN-DRAIN) Mode Enabled
0 = SPI signal pins not configured for open-drain.
1 = All four SPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain function.
This setting is typically used for multi-master and/or multi-slave configurations.
MMEN—SPI Master Mode Enable
0 = SPI configured in Slave mode.
1 = SPI configured in Master mode.
SPIEN—SPI Enable
0 = SPI disabled.
1 = SPI enabled.
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SPI Status Register
The SPI Status register (Table 65) indicates the current state of the SPI. All bits revert to
their reset state if the SPIEN bit in the SPICTL register = 0.
Table 65. SPI Status Register (SPISTAT)
BITS
FIELD
7
6
5
4
IRQ
OVR
COL
ABT
2
Reserved
0
RESET
R/W
3
1
0
TXST
SLAS
1
R/W*
R
F62H
ADDR
Note: R/W* = Read access. Write a 1 to clear the bit to 0.
IRQ—Interrupt Request
If SPIEN = 1, this bit is set if the STR bit in the SPICTL register is set, or upon completion
of an SPI master or slave transaction. This bit does not set if SPIEN = 0 and the SPI Baud
Rate Generator is used as a timer to generate the SPI interrupt.
0 = No SPI interrupt request pending.
1 = SPI interrupt request is pending.
OVR—Overrun
0 = An overrun error has not occurred.
1 = An overrun error has been detected.
COL—Collision
0 = A multi-master collision (mode fault) has not occurred.
1 = A multi-master collision (mode fault) has been detected.
ABT—Slave mode transaction abort
This bit is set if the SPI is configured in slave mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the SPIMODE register. The IRQ bit also sets, indicating the transaction has completed.
0 = A slave mode transaction abort has not occurred.
1 = A slave mode transaction abort has been detected.
Reserved—Must be 0.
TXST—Transmit Status
0 = No data transmission currently in progress.
1 = Data transmission currently in progress.
SLAS—Slave Select
If SPI enabled as a Slave,
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0 = SS input pin is asserted (Low).
1 = SS input is not asserted (High).
If SPI enabled as a Master, this bit is not applicable.
SPI Mode Register
The SPI Mode register (Table 66) configures the character bit width and the direction and
value of the SS pin.
Table 66. SPI Mode Register (SPIMODE)
BITS
7
6
Reserved
FIELD
5
DIAG
4
3
NUMBITS[2:0]
1
0
SSIO
SSV
0
RESET
R
R/W
2
R/W
F63H
ADDR
Reserved—Must be 0.
DIAG—Diagnostic Mode Control bit
This bit is for SPI diagnostics. Setting this bit allows the Baud Rate Generator value to be
read using the SPIBRH and SPIBRL register locations.
0 = Reading SPIBRH, SPIBRL returns the value in the SPIBRH and SPIBRL registers
1 = Reading SPIBRH returns bits [15:8] of the SPI Baud Rate Generator; and reading
SPIBRL returns bits [7:0] of the SPI Baud Rate Counter. The Baud Rate Counter
High and Low byte values are not buffered.
Caution: Exercise caution if reading the values while the BRG is counting.
NUMBITS[2:0]—Number of Data Bits Per Character to Transfer
This field contains the number of bits to shift for each character transfer. For information
on valid bit positions when the character length is less than 8-bits, see SPI Data Register
description.
000 = 8 bits
001 = 1 bit
010 = 2 bits
011 = 3 bits
100 = 4 bits
101 = 5 bits
110 = 6 bits
111 = 7 bits
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SSIO—Slave Select I/O
0 = SS pin configured as an input.
1 = SS pin configured as an output (Master mode only).
SSV—Slave Select Value
If SSIO = 1 and SPI configured as a Master:
0 = SS pin driven Low (0).
1 = SS pin driven High (1).
This bit has no effect if SSIO = 0 or SPI configured as a Slave.
SPI Diagnostic State Register
The SPI Diagnostic State register (Table 67) provides observability of internal state. This
is a read only register used for SPI diagnostics.
Table 67. SPI Diagnostic State Register (SPIDST)
BITS
FIELD
7
6
SCKEN
TCKEN
5
4
3
1
0
SPISTATE
RESET
0
R/W
R
ADDR
2
F64H
SCKEN—Shift Clock Enable
0 = The internal Shift Clock Enable signal is deasserted
1 = The internal Shift Clock Enable signal is asserted (shift register is updates on next
system clock)
TCKEN—Transmit Clock Enable
0 = The internal Transmit Clock Enable signal is deasserted.
1 = The internal Transmit Clock Enable signal is asserted. When this is asserted the
serial data out is updated on the next system clock (MOSI or MISO).
SPISTATE—SPI State Machine
Defines the current state of the internal SPI State Machine.
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SPI Baud Rate High and Low Byte Registers
The SPI Baud Rate High and Low Byte registers (Table 68 and Table 69) combine to form
a 16-bit reload value, BRG[15:0], for the SPI Baud Rate Generator.
When configured as a general purpose timer, the SPI BRG interrupt interval is calculated
using the following equation:
SPI BRG Interrupt Interval (s) = System Clock Period (s) × BRG[15:0]
Table 68. SPI Baud Rate High Byte Register (SPIBRH)
BITS
7
6
5
4
3
FIELD
BRH
RESET
1
R/W
R/W
ADDR
F66H
2
1
0
BRH = SPI Baud Rate High Byte
Most significant byte, BRG[15:8], of the SPI Baud Rate Generator’s reload value.
Table 69. SPI Baud Rate Low Byte Register (SPIBRL)
BITS
7
6
5
4
3
FIELD
BRL
RESET
1
R/W
R/W
ADDR
F67H
2
1
0
BRL = SPI Baud Rate Low Byte
Least significant byte, BRG[7:0], of the SPI Baud Rate Generator’s reload value.
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I2C Controller
Overview
The I2C Controller makes the 64K Series products bus-compatible with the I2C protocol.
The I2C Controller consists of two bidirectional bus lines—a serial data signal (SDA) and
a serial clock signal (SCL). Features of the I2C Controller include:
•
•
•
•
Transmit and Receive Operation in MASTER mode
Maximum data rate of 400 kbit/sec
7- and 10-bit addressing modes for Slaves
Unrestricted number of data bytes transmitted per transfer
The I2C Controller in the 64K Series products does not operate in SLAVE mode.
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Architecture
Figure 27 displays the architecture of the I2C Controller.
SDA
SCL
Shift
ISHIFT
Load
I2CDATA
Baud Rate Generator
I2CBRH
Receive
I2CBRL
Tx/Rx State Machine
I2CCTL
I2CSTAT
Register Bus
I2C Interrupt
Figure 27. I2C Controller Block Diagram
Operation
The I2C Controller operates in MASTER mode to transmit and receive data. Only a single
master is supported. Arbitration between two masters must be accomplished in software.
I2C supports the following operations:
•
•
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Master transmits to a 7-bit slave
Master transmits to a 10-bit slave
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•
•
Master receives from a 7-bit slave
Master receives from a 10-bit slave
SDA and SCL Signals
I2C sends all addresses, data and acknowledge signals over the SDA line, most-significant
bit first. SCL is the common clock for the I2C Controller. When the SDA and SCL pin
alternate functions are selected for their respective GPIO ports, the pins are automatically
configured for open-drain operation.
The master (I2C) is responsible for driving the SCL clock signal, although the clock signal
can become skewed by a slow slave device. During the low period of the clock, the slave
pulls the SCL signal Low to suspend the transaction. The master releases the clock at the
end of the low period and notices that the clock remains low instead of returning to a high
level. When the slave releases the clock, the I2C Controller continues the transaction. All
data is transferred in bytes and there is no limit to the amount of data transferred in one
operation. When transmitting data or acknowledging read data from the slave, the SDA
signal changes in the middle of the low period of SCL and is sampled in the middle of the
high period of SCL.
I2C Interrupts
The I2C Controller contains four sources of interrupts—Transmit, Receive, Not
Acknowledge and baud rate generator. These four interrupt sources are combined into a
single interrupt request signal to the Interrupt Controller. The Transmit interrupt is enabled
by the IEN and TXI bits of the Control register. The Receive and Not Acknowledge
interrupts are enabled by the IEN bit of the Control register. The baud rate generator
interrupt is enabled by the BIRQ and IEN bits of the Control register.
Not Acknowledge interrupts occur when a Not Acknowledge condition is received from
the slave or sent by the I2C Controller and neither the START or STOP bit is set. The Not
Acknowledge event sets the NCKI bit of the I2C Status register and can only be cleared by
setting the START or STOP bit in the I2C Control register. When this interrupt occurs, the
I2C Controller waits until either the STOP or START bit is set before performing any
action. In an interrupt service routine, the NCKI bit should always be checked prior to
servicing transmit or receive interrupt conditions because it indicates the transaction is
being terminated.
Receive interrupts occur when a byte of data has been received by the I2C Controller
(master reading data from slave). This procedure sets the RDRF bit of the I2C Status
register. The RDRF bit is cleared by reading the I2C Data register. The RDRF bit is set
during the acknowledge phase. The I2C Controller pauses after the acknowledge phase
until the receive interrupt is cleared before performing any other action.
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Transmit interrupts occur when the TDRE bit of the I2C Status register sets and the TXI
bit in the I2C Control register is set. Transmit interrupts occur under the following conditions when the transmit data register is empty:
•
•
•
•
The I2C Controller is enabled.
The first bit of the byte of an address is shifting out and the RD bit of the I2C Status
register is deasserted.
The first bit of a 10-bit address shifts out.
The first bit of write data shifts out.
Note: Writing to the I2C Data register always clears the TRDE bit to 0. When TDRE is asserted,
the I2C Controller pauses at the beginning of the Acknowledge cycle of the byte currently
shifting out until the Data register is written with the next value to send or the STOP or
START bits are set indicating the current byte is the last one to send.
The fourth interrupt source is the baud rate generator. If the I2C Controller is disabled
(IEN bit in the I2CCTL register = 0) and the BIRQ bit in the I2CCTL register = 1, an interrupt is generated when the baud rate generator counts down to 1. This allows the I2C baud
rate generator to be used by software as a general purpose timer when IEN = 0.
Software Control of I2C Transactions
Software can control I2C transactions by using the I2C Controller interrupt, by polling the
I2C Status register or by DMA. Note that not all products include a DMA Controller.
To use interrupts, the I2C interrupt must be enabled in the Interrupt Controller. The TXI bit
in the I2C Control register must be set to enable transmit interrupts.
To control transactions by polling, the interrupt bits (TDRE, RDRF and NCKI) in the I2C
Status register should be polled. The TDRE bit asserts regardless of the state of the TXI
bit.
Either or both transmit and receive data movement can be controlled by the DMA
Controller. The DMA Controller channel(s) must be initialized to select the I2C transmit
and receive requests. Transmit DMA requests require that the TXI bit in the I2C Control
register be set.
Caution:
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A transmit (write) DMA operation hangs if the slave responds with a Not
Acknowledge before the last byte has been sent. After receiving the Not
Acknowledge, the I2C Controller sets the NCKI bit in the Status register and
pauses until either the STOP or START bits in the Control register are set.
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In order for a receive (read) DMA transaction to send a Not Acknowledge
on the last byte, the receive DMA must be set up to receive n-1 bytes, then
software must set the NAK bit and receive the last (nth) byte directly.
Start and Stop Conditions
The master (I2C) drives all Start and Stop signals and initiates all transactions. To start a
transaction, the I2C Controller generates a START condition by pulling the SDA signal
Low while SCL is High. To complete a transaction, the I2C Controller generates a Stop
condition by creating a low-to-high transition of the SDA signal while the SCL signal is
high. The START and STOP bits in the I2C Control register control the sending of the
Start and Stop conditions. A master is also allowed to end one transaction and begin a new
one by issuing a Restart. This is accomplished by setting the START bit at the end of a
transaction, rather than the STOP bit. Note that the Start condition not sent until the
START bit is set and data has been written to the I2C Data register.
Master Write and Read Transactions
The following sections provide a recommended procedure for performing I2C write and
read transactions from the I2C Controller (master) to slave I2C devices. In general
software should rely on the TDRE, RDRF and NCKI bits of the status register (these bits
generate interrupts) to initiate software actions. When using interrupts or DMA, the TXI
bit is set to start each transaction and cleared at the end of each transaction to eliminate a
‘trailing’ Transmit interrupt.
Caution should be used in using the ACK status bit within a transaction because it is
difficult for software to tell when it is updated by hardware.
When writing data to a slave, the I2C pauses at the beginning of the Acknowledge cycle if
the data register has not been written with the next value to be sent (TDRE bit in the I2C
Status register = 1). In this scenario where software is not keeping up with the I2C bus
(TDRE asserted longer than one byte time), the Acknowledge clock cycle for byte n is
delayed until the Data register is written with byte n + 1, and appears to be grouped with
the data clock cycles for byte n+1. If either the START or STOP bit is set, the I2C does not
pause prior to the Acknowledge cycle because no additional data is sent.
When a Not Acknowledge condition is received during a write (either during the address
or data phases), the I2C Controller generates the Not Acknowledge interrupt (NCKI = 1)
and pause until either the STOP or START bit is set. Unless the Not Acknowledge was
received on the last byte, the Data register will already have been written with the next
address or data byte to send. In this case the FLUSH bit of the Control register should be
set at the same time the STOP or START bit is set to remove the stale transmit data and
enable subsequent Transmit interrupts.
When reading data from the slave, the I2C pauses after the data Acknowledge cycle until
the receive interrupt is serviced and the RDRF bit of the status register is cleared by
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reading the I2C Data register. Once the I2C data register has been read, the I2C reads the
next data byte.
Address Only Transaction with a 7-bit Address
In the situation where software determines if a slave with a 7-bit address is responding
without sending or receiving data, a transaction can be done which only consists of an
address phase. Figure 28 displays this ‘address only’ transaction to determine if a slave
with a 7-bit address will acknowledge. As an example, this transaction can be used after a
‘write’ has been done to a EEPROM to determine when the EEPROM completes its internal write operation and is once again responding to I2C transactions. If the slave does not
Acknowledge, the transaction can be repeated until the slave does Acknowledge.
S
Slave Address
W = 0 A/A
P
Figure 28. 7-Bit Address Only Transaction Format
Follow the steps below for an address only transaction to a 7-bit addressed slave:
1. Software asserts the IEN bit in the I2C Control register.
2. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts.
3. The I2C interrupt asserts, because the I2C Data register is empty (TDRE = 1)
4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (=0)
to the I2C Data register. As an alternative this could be a read operation instead of a
write operation.
5. Software sets the START and STOP bits of the I2C Control register and clears the TXI
bit.
6. The I2C Controller sends the START condition to the I2C slave.
7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register.
8. Software polls the STOP bit of the I2C Control register. Hardware deasserts the STOP
bit when the address only transaction is completed.
9.
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Software checks the ACK bit of the I2C Status register. If the slave acknowledged, the
ACK bit is = 1. If the slave does not acknowledge, the ACK bit is = 0. The NCKI
interrupt does not occur in the not acknowledge case because the STOP bit was set.
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Write Transaction with a 7-Bit Address
Figure 29 displays the data transfer format for a 7-bit addressed slave. Shaded regions
indicate data transferred from the I2C Controller to slaves and unshaded regions indicate
data transferred from the slaves to the I2C Controller.
S
Slave Address
W=0
A
Data
A
Data
A
Data
A/A P/S
Figure 29. 7-Bit Addressed Slave Data Transfer Format
Follow the steps below for a transmit operation to a 7-bit addressed slave:
1. Software asserts the IEN bit in the I2C Control register.
2. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts.
3. The I2C interrupt asserts, because the I2C Data register is empty
4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (=0)
to the I2C Data register.
5. Software asserts the START bit of the I2C Control register.
6. The I2C Controller sends the START condition to the I2C slave.
7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register.
8. After one bit of address has been shifted out by the SDA signal, the Transmit interrupt
is asserted (TDRE = 1).
9. Software responds by writing the transmit data into the I2C Data register.
10. The I2C Controller shifts the rest of the address and write bit out by the SDA signal.
11. If the I2C slave sends an acknowledge (by pulling the SDA signal low) during the next
high period of SCL the I2C Controller sets the ACK bit in the I2C Status register.
Continue with step 12.
If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is
set in the Status register, ACK bit is cleared). Software responds to the Not
Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit.
The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore the following steps).
12. The I2C Controller loads the contents of the I2C Shift register with the contents of the
I2C Data register.
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13. The I2C Controller shifts the data out of using the SDA signal. After the first bit is
sent, the Transmit interrupt is asserted.
14. If more bytes remain to be sent, return to step 9.
15. Software responds by setting the STOP bit of the I2C Control register (or START bit
to initiate a new transaction). In the STOP case, software clears the TXI bit of the I2C
Control register at the same time.
16. The I2C Controller completes transmission of the data on the SDA signal.
17. The slave may either Acknowledge or Not Acknowledge the last byte. Because either
the STOP or START bit is already set, the NCKI interrupt does not occur.
18. The I2C Controller sends the STOP (or RESTART) condition to the I2C bus. The
STOP or START bit is cleared.
Address Only Transaction with a 10-bit Address
In the situation where software wants to determine if a slave with a 10-bit address is
responding without sending or receiving data, a transaction can be done which only consists of an address phase. Figure 30 displays this ‘address only’ transaction to determine if
a slave with 10-bit address will acknowledge. As an example, this transaction can be used
after a ‘write’ has been done to a EEPROM to determine when the EEPROM completes its
internal write operation and is once again responding to I2C transactions. If the slave does
not Acknowledge the transaction can be repeated until the slave is able to Acknowledge.
S
Slave Address
1st 7 bits
W = 0 A/A
Slave Address
2nd Byte
A/A P
Figure 30. 10-Bit Address Only Transaction Format
Follow the steps below for an address only transaction to a 10-bit addressed slave:
1. Software asserts the IEN bit in the I2C Control register.
2. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts.
3. The I2C interrupt asserts, because the I2C Data register is empty (TDRE = 1)
4. Software responds to the TDRE interrupt by writing the first slave address byte. The
least-significant bit must be 0 for the write operation.
5. Software asserts the START bit of the I2C Control register.
6. The I2C Controller sends the START condition to the I2C slave.
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7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register.
8. After one bit of address is shifted out by the SDA signal, the Transmit interrupt is
asserted.
9. Software responds by writing the second byte of address into the contents of the I2C
Data register.
10. The I2C Controller shifts the rest of the first byte of address and write bit out the SDA
signal.
11. If the I2C slave sends an acknowledge by pulling the SDA signal low during the next
high period of SCL the I2C Controller sets the ACK bit in the I2C Status register.
Continue with step 12.
If the slave does not acknowledge the first address byte, the I2C Controller sets the
NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore following steps).
12. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register (2nd byte of address).
13. The I2C Controller shifts the second address byte out the SDA signal. After the first
bit has been sent, the Transmit interrupt is asserted.
14. Software responds by setting the STOP bit in the I2C Control register. The TXI bit can
be cleared at the same time.
15. Software polls the STOP bit of the I2C Control register. Hardware deasserts the STOP
bit when the transaction is completed (STOP condition has been sent).
16. Software checks the ACK bit of the I2C Status register. If the slave acknowledged, the
ACK bit is = 1. If the slave does not acknowledge, the ACK bit is = 0. The NCKI
interrupt do not occur because the STOP bit was set.
Write Transaction with a 10-Bit Address
Figure 31 displays the data transfer format for a 10-bit addressed slave. Shaded regions
indicate data transferred from the I2C Controller to slaves and unshaded regions indicate
data transferred from the slaves to the I2C Controller.
S
Slave Address
W=0 A
1st 7 bits
Slave Address
2nd Byte
A Data A Data A/A P/S
Figure 31. 10-Bit Addressed Slave Data Transfer Format
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The first seven bits transmitted in the first byte are 11110XX. The two bits XX are the two
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
read/write control bit (=0). The transmit operation is carried out in the same manner as 7bit addressing.
Follow the steps below for a transmit operation on a 10-bit addressed slave:
1. Software asserts the IEN bit in the I2C Control register.
2. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts.
3. The I2C interrupt asserts because the I2C Data register is empty.
4. Software responds to the TDRE interrupt by writing the first slave address byte to the
I2C Data register. The least-significant bit must be 0 for the write operation.
5. Software asserts the START bit of the I2C Control register.
6. The I2C Controller sends the START condition to the I2C slave.
7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register.
8. After one bit of address is shifted out by the SDA signal, the Transmit interrupt is
asserted.
9. Software responds by writing the second byte of address into the contents of the I2C
Data register.
10. The I2C Controller shifts the rest of the first byte of address and write bit out the SDA
signal.
11. If the I2C slave acknowledges the first address byte by pulling the SDA signal low
during the next high period of SCL, the I2C Controller sets the ACK bit in the I2C
Status register. Continue with step 12.
If the slave does not acknowledge the first address byte, the I2C Controller sets the
NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore the following steps).
12. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register.
13. The I2C Controller shifts the second address byte out the SDA signal. After the first
bit has been sent, the Transmit interrupt is asserted.
14. Software responds by writing a data byte to the I2C Data register.
15. The I2C Controller completes shifting the contents of the shift register on the SDA
signal.
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16. If the I2C slave sends an acknowledge by pulling the SDA signal low during the next
high period of SCL, the I2C Controller sets the ACK bit in the I2C Status register.
Continue with step 17.
If the slave does not acknowledge the second address byte or one of the data bytes, the
I2C Controller sets the NCKI bit and clears the ACK bit in the I2C Status register.
Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH
bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus
and clears the STOP and NCKI bits. The transaction is complete (ignore the following
steps).
17. The I2C Controller shifts the data out by the SDA signal. After the first bit is sent, the
Transmit interrupt is asserted.
18. If more bytes remain to be sent, return to step 14.
19. If the last byte is currently being sent, software sets the STOP bit of the I2C Control
register (or START bit to initiate a new transaction). In the STOP case, software also
clears the TXI bit of the I2C Control register at the same time.
20. The I2C Controller completes transmission of the last data byte on the SDA signal.
21. The slave may either Acknowledge or Not Acknowledge the last byte. Because either
the STOP or START bit is already set, the NCKI interrupt does not occur.
22. The I2C Controller sends the STOP (or RESTART) condition to the I2C bus and clears
the STOP (or START) bit.
Read Transaction with a 7-Bit Address
Figure 32 displays the data transfer format for a read operation to a 7-bit addressed slave.
The shaded regions indicate data transferred from the I2C Controller to slaves and
unshaded regions indicate data transferred from the slaves to the I2C Controller.
S
Slave Address
R=1
A
Data
A
Data
A
P/S
Figure 32. Receive Data Transfer Format for a 7-Bit Addressed Slave
Follow the steps below for a read operation to a 7-bit addressed slave:
1. Software writes the I2C Data register with a 7-bit slave address plus the read bit (=1).
2. Software asserts the START bit of the I2C Control register.
3. If this is a single byte transfer, Software asserts the NAK bit of the I2C Control register
so that after the first byte of data has been read by the I2C Controller, a Not
Acknowledge is sent to the I2C slave.
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4. The I2C Controller sends the START condition.
5. The I2C Controller shifts the address and read bit out the SDA signal.
6. If the I2C slave acknowledges the address by pulling the SDA signal Low during the
next high period of SCL, the I2C Controller sets the ACK bit in the I2C Status register.
Continue with step 7.
If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is
set in the Status register, ACK bit is cleared). Software responds to the Not
Acknowledge interrupt by setting the STOP bit and clearing the TXI bit. The I2C
Controller sends the STOP condition on the bus and clears the STOP and NCKI bits.
The transaction is complete (ignore the following steps).
7. The I2C Controller shifts in the byte of data from the I2C slave on the SDA signal. The
I2C Controller sends a Not Acknowledge to the I2C slave if the NAK bit is set (last
byte), else it sends an Acknowledge.
8. The I2C Controller asserts the Receive interrupt (RDRF bit set in the Status register).
9. Software responds by reading the I2C Data register which clears the RDRF bit. If there
is only one more byte to receive, set the NAK bit of the I2C Control register.
10. If there are more bytes to transfer, return to step 7.
11. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I2C
Controller.
12. Software responds by setting the STOP bit of the I2C Control register.
13. A STOP condition is sent to the I2C slave, the STOP and NCKI bits are cleared.
Read Transaction with a 10-Bit Address
Figure 33 displays the read transaction format for a 10-bit addressed slave. The shaded
regions indicate data transferred from the I2C Controller to slaves and unshaded regions
indicate data transferred from the slaves to the I2C Controller.
S
Slave Address
W=0 A
1st 7 bits
Slave Address
2nd Byte
A S
Slave Address
1st 7 bits
R=1 A Data A Data A P
Figure 33. Receive Data Format for a 10-Bit Addressed Slave
The first seven bits transmitted in the first byte are 11110XX. The two bits XX are the two
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
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Follow the steps below for the data transfer for a read operation to a 10-bit addressed
slave:
1. Software writes 11110B followed by the two address bits and a 0 (write) to the I2C
Data register.
2. Software asserts the START and TXI bits of the I2C Control register.
3. The I2C Controller sends the Start condition.
4. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register.
5. After the first bit has been shifted out, a Transmit interrupt is asserted.
6. Software responds by writing the lower eight bits of address to the I2C Data register.
7. The I2C Controller completes shifting of the two address bits and a 0 (write).
8. If the I2C slave acknowledges the first address byte by pulling the SDA signal low
during the next high period of SCL, the I2C Controller sets the ACK bit in the I2C
Status register. Continue with step 9.
If the slave does not acknowledge the first address byte, the I2C Controller sets the
NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore following steps).
9. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register (second address byte).
10. The I2C Controller shifts out the second address byte. After the first bit is shifted, the
I2C Controller generates a Transmit interrupt.
11. Software responds by setting the START bit of the I2C Control register to generate a
repeated START and by clearing the TXI bit.
12. Software responds by writing 11110B followed by the 2-bit slave address and a 1
(read) to the I2C Data register.
13. If only one byte is to be read, software sets the NAK bit of the I2C Control register.
14. After the I2C Controller shifts out the 2nd address byte, the I2C slave sends an
acknowledge by pulling the SDA signal low during the next high period of SCL, the
I2C Controller sets the ACK bit in the I2C Status register. Continue with step 15.
If the slave does not acknowledge the second address byte, the I2C Controller sets the
NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore the following steps).
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15. The I2C Controller sends the repeated START condition.
16. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register (third address transfer).
17. The I2C Controller sends 11110B followed by the two most significant bits of the
slave read address and a 1 (read).
18. The I2C slave sends an acknowledge by pulling the SDA signal Low during the next
high period of SCL
If the slave were to Not Acknowledge at this point (this should not happen because the
slave did acknowledge the first two address bytes), software would respond by setting
the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the
STOP condition on the bus and clears the STOP and NCKI bits. The transaction is
complete (ignore the following steps).
19. The I2C Controller shifts in a byte of data from the I2C slave on the SDA signal. The
I2C Controller sends a Not Acknowledge to the I2C slave if the NAK bit is set (last
byte), else it sends an Acknowledge.
20. The I2C Controller asserts the Receive interrupt (RDRF bit set in the Status register).
21. Software responds by reading the I2C Data register which clears the RDRF bit. If there
is only one more byte to receive, set the NAK bit of the I2C Control register.
22. If there are one or more bytes to transfer, return to step 19.
23. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I2C
Controller.
24. Software responds by setting the STOP bit of the I2C Control register.
25. A STOP condition is sent to the I2C slave and the STOP and NCKI bits are cleared.
I2C Control Register Definitions
I2C Data Register
The I2C Data register (see Table 70 on page 157) holds the data that is to be loaded into
the I2C Shift register during a write to a slave. This register also holds data that is loaded
from the I2C Shift register during a read from a slave. The I2C Shift Register is not accessible in the Register File address space, but is used only to buffer incoming and outgoing
data.
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Table 70. I2C Data Register (I2CDATA)
BITS
7
6
5
4
3
FIELD
DATA
RESET
0
R/W
R/W
ADDR
F50H
2
1
0
I2C Status Register
The Read-only I2C Status register (Table 71) indicates the status of the I2C Controller.
Table 71. I2C Status Register (I2CSTAT)
BITS
7
6
5
4
3
2
1
0
FIELD
TDRE
RDRF
ACK
10B
RD
TAS
DSS
NCKI
RESET
1
R/W
ADDR
0
R
F51H
TDRE—Transmit Data Register Empty
When the I2C Controller is enabled, this bit is 1 when the I2C Data register is empty.
When this bit is set, an interrupt is generated if the TXI bit is set, except when the I2C
Controller is shifting in data during the reception of a byte or when shifting an address and
the RD bit is set. This bit is cleared by writing to the I2CDATA register.
RDRF—Receive Data Register Full
This bit is set = 1 when the I2C Controller is enabled and the I2C Controller has received a
byte of data. When asserted, this bit causes the I2C Controller to generate an interrupt.
This bit is cleared by reading the I2C Data register (unless the read is performed using execution of the On-Chip Debugger’s Read Register command).
ACK—Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received.
When set, this bit indicates that an Acknowledge occurred for the last byte transmitted or
received. This bit is cleared when IEN = 0 or when a Not Acknowledge occurred for the
last byte transmitted or received. It is not reset at the beginning of each transaction and is
not reset when this register is read.
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Caution: Software must be cautious in making decisions based on this bit within a transaction because software cannot tell when the bit is updated by hardware. In the
case of write transactions, the I2C pauses at the beginning of the Acknowledge
cycle if the next transmit data or address byte has not been written (TDRE = 1)
and STOP and START = 0. In this case the ACK bit is not updated until the
transmit interrupt is serviced and the Acknowledge cycle for the previous byte
completes. For examples of how the ACK bit can be used, see Address Only
Transaction with a 7-bit Address on page 148 and Address Only Transaction
with a 10-bit Address on page 150.
10B—10-Bit Address
This bit indicates whether a 10- or 7-bit address is being transmitted. After the START bit
is set, if the five most-significant bits of the address are 11110B, this bit is set. When set,
it is reset once the first byte of the address has been sent.
RD—Read
This bit indicates the direction of transfer of the data. It is active high during a read. The
status of this bit is determined by the least-significant bit of the I2C Shift register after the
START bit is set.
TAS—Transmit Address State
This bit is active high while the address is being shifted out of the I2C Shift register.
DSS—Data Shift State
This bit is active high while data is being shifted to or from the I2C Shift register.
NCKI—NACK Interrupt
This bit is set high when a Not Acknowledge condition is received or sent and neither the
START nor the STOP bit is active. When set, this bit generates an interrupt that can only
be cleared by setting the START or STOP bit, allowing you to specify whether to perform
a STOP or a repeated START.
I2C Control Register
The I2C Control register (Table 72) enables the I2C operation.
Table 72. I2C Control Register (I2CCTL)
BITS
FIELD
7
6
5
4
3
2
1
0
IEN
START
STOP
BIRQ
TXI
NAK
FLUSH
FILTEN
R/W
R/W1
W1
R/W
0
RESET
R/W
R/W
ADDR
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R/W1
R/W1
R/W
F52H
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IEN—I2C Enable
1 = The I2C transmitter and receiver are enabled.
0 = The I2C transmitter and receiver are disabled.
START—Send Start Condition
This bit sends the Start condition. Once asserted, it is cleared by the I2C Controller after it
sends the START condition or if the IEN bit is deasserted. If this bit is 1, it cannot be
cleared to 0 by writing to the register. After this bit is set, the Start condition is sent if there
is data in the I2C Data or I2C Shift register. If there is no data in one of these registers, the
I2C Controller waits until the Data register is written. If this bit is set while the I2C
Controller is shifting out data, it generates a START condition after the byte shifts and the
acknowledge phase completes. If the STOP bit is also set, it also waits until the STOP
condition is sent before the sending the START condition.
STOP—Send Stop Condition
This bit causes the I2C Controller to issue a Stop condition after the byte in the I2C Shift
register has completed transmission or after a byte has been received in a receive
operation. Once set, this bit is reset by the I2C Controller after a Stop condition has been
sent or by deasserting the IEN bit. If this bit is 1, it cannot be cleared to 0 by writing to the
register.
BIRQ—Baud Rate Generator Interrupt Request
This bit allows the I2C Controller to be used as an additional timer when the I2C
Controller is disabled. This bit is ignored when the I2C Controller is enabled.
1 = An interrupt occurs every time the baud rate generator counts down to one.
0 = No baud rate generator interrupt occurs.
TXI—Enable TDRE interrupts
This bit enables the transmit interrupt when the I2C Data register is empty (TDRE = 1).
1 = Transmit interrupt (and DMA transmit request) is enabled.
0 = Transmit interrupt (and DMA transmit request) is disabled.
NAK—Send NAK
This bit sends a Not Acknowledge condition after the next byte of data has been read from
the I2C slave. Once asserted, it is deasserted after a Not Acknowledge is sent or the IEN
bit is deasserted. If this bit is 1, it cannot be cleared to 0 by writing to the register.
FLUSH—Flush Data
Setting this bit to 1 clears the I2C Data register and sets the TDRE bit to 1. This bit allows
flushing of the I2C Data register when a Not Acknowledge interrupt is received after the
data has been sent to the I2C Data register. Reading this bit always returns 0.
FILTEN—I2C Signal Filter Enable
This bit enables low-pass digital filters on the SDA and SCL input signals. These filters
reject any input pulse with periods less than a full system clock cycle. The filters introduce
a 3-system clock cycle latency on the inputs.
1 = low-pass filters are enabled.
0 = low-pass filters are disabled.
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I2C Baud Rate High and Low Byte Registers
The I2C Baud Rate High and Low Byte registers (Tables 73 and 73) combine to form a
16-bit reload value, BRG[15:0], for the I2C Baud Rate Generator.
When the I2C is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the I2C by clearing the IEN bit in the I2C Control register to 0.
2. Load the desired 16-bit count value into the I2C Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BIRQ bit in the I2C Control register to 1.
When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval (s) = System Clock Period (s) × BRG [ 15:0 ]
Table 73. I2C Baud Rate High Byte Register (I2CBRH)
BITS
7
6
5
4
3
FIELD
BRH
RESET
FFH
R/W
R/W
ADDR
F53H
2
1
0
BRH = I2C Baud Rate High Byte
Most significant byte, BRG[15:8], of the I2C Baud Rate Generator’s reload value.
Note: If the DIAG bit in the I2C Diagnostic Control Register is set to 1, a read of the I2CBRH
register returns the current value of the I2C Baud Rate Counter[15:8].
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Table 74. I2C Baud Rate Low Byte Register (I2CBRL)
BITS
7
6
5
4
3
FIELD
BRL
RESET
FFH
R/W
R/W
ADDR
F54H
2
1
0
BRL = I2C Baud Rate Low Byte
Least significant byte, BRG[7:0], of the I2C Baud Rate Generator’s reload value.
Note: If the DIAG bit in the I2C Diagnostic Control Register is set to 1, a read of the I2CBRL
register returns the current value of the I2C Baud Rate Counter[7:0].
I2C Diagnostic State Register
The I2C Diagnostic State register (Table 75) provides observability of internal state. This
is a read only register used for I2C diagnostics and manufacturing test.
Table 75. I2C Diagnostic State Register (I2CDST)
BITS
FIELD
7
6
5
SCLIN
SDAIN
STPCNT
RESET
R/W
ADDR
4
3
2
1
0
TXRXSTATE
X
0
R
F55H
SCLIN—Value of Serial Clock input signal
SDAIN—Value of the Serial Data input signal
STPCNT—Value of the internal Stop Count control signal
TXRXSTATE—Value of the internal I2C state machine
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PS019919-1207
TXRXSTATE
State Description
0_0000
Idle State
0_0001
START State
0_0010
Send/Receive data bit 7
0_0011
Send/Receive data bit 6
0_0100
Send/Receive data bit 5
0_0101
Send/Receive data bit 4
0_0110
Send/Receive data bit 3
0_0111
Send/Receive data bit 2
0_1000
Send/Receive data bit 1
0_1001
Send/Receive data bit 0
0_1010
Data Acknowledge State
0_1011
Second half of data Acknowledge State used only for not
acknowledge
0_1100
First part of STOP state
0_1101
Second part of STOP state
0_1110
10-bit addressing: Acknowledge State for 2nd address byte
7-bit addressing: Address Acknowledge State
0_1111
10-bit address: Bit 0 (Least significant bit) of 2nd address byte
7-bit address: Bit 0 (Least significant bit) (R/W) of address byte
1_0000
10-bit addressing: Bit 7 (Most significant bit) of 1st address byte
1_0001
10-bit addressing: Bit 6 of 1st address byte
1_0010
10-bit addressing: Bit 5 of 1st address byte
1_0011
10-bit addressing: Bit 4 of 1st address byte
1_0100
10-bit addressing: Bit 3 of 1st address byte
1_0101
10-bit addressing: Bit 2 of 1st address byte
1_0110
10-bit addressing: Bit 1 of 1st address byte
1_0111
10-bit addressing: Bit 0 (R/W) of 1st address byte
1_1000
10-bit addressing: Acknowledge state for 1st address byte
1_1001
10-bit addressing: Bit 7 of 2nd address byte
7-bit addressing: Bit 7 of address byte
1_1010
10-bit addressing: Bit 6 of 2nd address byte
7-bit addressing: Bit 6 of address byte
1_1011
10-bit addressing: Bit 5 of 2nd address byte
7-bit addressing: Bit 5 of address byte
1_1100
10-bit addressing: Bit 4 of 2nd address byte
7-bit addressing: Bit 4 of address byte
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TXRXSTATE
State Description
1_1101
10-bit addressing: Bit 3 of 2nd address byte
7-bit addressing: Bit 3 of address byte
1_1110
10-bit addressing: Bit 2 of 2nd address byte
7-bit addressing: Bit 2 of address byte
1_1111
10-bit addressing: Bit 1 of 2nd address byte
7-bit addressing: Bit 1 of address byte
I2C Diagnostic Control Register
The I2C Diagnostic register (Table 76) provides control over diagnostic modes. This register is a read/write register used for I2C diagnostics.
Table 76. I2C Diagnostic Control Register (I2CDIAG)
BITS
FIELD
7
6
5
4
Reserved
ADDR
2
1
0
DIAG
0
RESET
R/W
3
R
R/W
F56H
DIAG = Diagnostic Control Bit - Selects read back value of the Baud Rate Reload registers.
0 = NORMAL mode. Reading the Baud Rate High and Low Byte registers returns the
baud rate reload value.
1 = DIAGNOSTIC mode. Reading the Baud Rate High and Low Byte registers returns
the baud rate counter value.
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Direct Memory Access Controller
Overview
The 64K Series Direct Memory Access (DMA) Controller provides three independent
Direct Memory Access channels. Two of the channels (DMA0 and DMA1) transfer data
between the on-chip peripherals and the Register File. The third channel (DMA_ADC)
controls the ADC operation and transfers SINGLE-SHOT mode ADC output data to the
Register File.
Operation
DMA0 and DMA1 Operation
DMA0 and DMA1, referred to collectively as DMAx, transfer data either from the on-chip
peripheral control registers to the Register File, or from the Register File to the on-chip
peripheral control registers. The sequence of operations in a DMAx data transfer is:
1. DMAx trigger source requests a DMA data transfer.
2. DMAx requests control of the system bus (address and data) from the eZ8 CPU.
3. After the eZ8 CPU acknowledges the bus request, DMAx transfers either a single byte
or a two-byte word (depending upon configuration) and then returns system bus
control back to the eZ8 CPU.
4. If Current Address equals End Address:
– DMAx reloads the original Start Address
– If configured to generate an interrupt, DMAx sends an interrupt request to the
Interrupt Controller
– If configured for single-pass operation, DMAx resets the DEN bit in the DMAx
Control register to 0 and the DMA is disabled.
If Current Address does not equal End Address, the Current Address increments by 1
(single-byte transfer) or 2 (two-byte word transfer).
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Configuring DMA0 and DMA1 for Data Transfer
Follow the steps below to configure and enable DMA0 or DMA1:
1. Write to the DMAx I/O Address register to set the Register File address identifying the
on-chip peripheral control register. The upper nibble of the 12-bit address for on-chip
peripheral control registers is always FH. The full address is {FH, DMAx_IO[7:0]}.
2. Determine the 12-bit Start and End Register File addresses. The 12-bit Start Address
is given by {DMAx_H[3:0], DMA_START[7:0]}. The 12-bit End Address is given by
{DMAx_H[7:4], DMA_END[7:0]}.
3. Write the Start and End Register File address high nibbles to the DMAx End/Start
Address High Nibble register.
4. Write the lower byte of the Start Address to the DMAx Start/Current Address register.
5. Write the lower byte of the End Address to the DMAx End Address register.
6. Write to the DMAx Control register to complete the following:
– Select loop or single-pass mode operation
– Select the data transfer direction (either from the Register File RAM to the onchip peripheral control register; or from the on-chip peripheral control register to
the Register File RAM)
– Enable the DMAx interrupt request, if desired
– Select Word or Byte mode
– Select the DMAx request trigger
– Enable the DMAx channel
DMA_ADC Operation
DMA_ADC transfers data from the ADC to the Register File. The sequence of operations
in a DMA_ADC data transfer is:
1. ADC completes conversion on the current ADC input channel and signals the DMA
controller that two-bytes of ADC data are ready for transfer.
2. DMA_ADC requests control of the system bus (address and data) from the eZ8 CPU.
3. After the eZ8 CPU acknowledges the bus request, DMA_ADC transfers the two-byte
ADC output value to the Register File and then returns system bus control back to the
eZ8 CPU.
4. If the current ADC Analog Input is the highest numbered input to be converted:
– DMA_ADC resets the ADC Analog Input number to 0 and initiates data
conversion on ADC Analog Input 0.
– If configured to generate an interrupt, DMA_ADC sends an interrupt request to
the Interrupt Controller
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If the current ADC Analog Input is not the highest numbered input to be converted,
DMA_ADC initiates data conversion in the next higher numbered ADC Analog Input.
Configuring DMA_ADC for Data Transfer
Follow the steps below to configure and enable DMA_ADC:
1. Write the DMA_ADC Address register with the 7 most-significant bits of the Register
File address for data transfers.
2. Write to the DMA_ADC Control register to complete the following:
– Enable the DMA_ADC interrupt request, if desired
– Select the number of ADC Analog Inputs to convert
– Enable the DMA_ADC channel
Caution: When using the DMA_ADC to perform conversions on multiple ADC inputs,
the Analog-to-Digital Converter must be configured for SINGLE-SHOT mode.
If the ADC_IN field in the DMA_ADC Control Register is greater than 000b,
the ADC must be in SINGLE-SHOT mode.
CONTINUOUS mode operation of the ADC can only be used in conjunction
with DMA_ADC if the ADC_IN field in the DMA_ADC Control Register is reset to 000b to enable conversion on ADC Analog Input 0 only.
DMA Control Register Definitions
DMAx Control Register
The DMAx Control register (see Table 77 on page 167) enables and selects the mode of
operation for DMAx.
Table 77. DMAx Control Register (DMAxCTL)
BITS
FIELD
7
6
5
4
3
DEN
DLE
DDIR
IRQEN
WSEL
RESET
R/W
ADDR
2
1
0
RSS
0
R/W
FB0H, FB8H
DEN—DMAx Enable
0 = DMAx is disabled and data transfer requests are disregarded.
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1 = DMAx is enabled and initiates a data transfer upon receipt of a request from the
trigger source.
DLE—DMAx Loop Enable
0 = DMAx reloads the original Start Address and is then disabled after the End
Address data is transferred.
1 = DMAx, after the End Address data is transferred, reloads the original Start
Address and continues operating.
DDIR—DMAx Data Transfer Direction
0 = Register File → on-chip peripheral control register.
1 = on-chip peripheral control register → Register File.
IRQEN—DMAx Interrupt Enable
0 = DMAx does not generate any interrupts.
1 = DMAx generates an interrupt when the End Address data is transferred.
WSEL—Word Select
0 = DMAx transfers a single byte per request.
1 = DMAx transfers a two-byte word per request. The address for the on-chip
peripheral control register must be an even address.
RSS—Request Trigger Source Select
The Request Trigger Source Select field determines the peripheral that can initiate a DMA
transfer. The corresponding interrupts do not need to be enabled within the Interrupt Controller to initiate a DMA transfer. However, if the Request Trigger Source can enable or
disable the interrupt request sent to the Interrupt Controller, the interrupt request must be
enabled within the Request Trigger Source block.
000 = Timer 0.
001 = Timer 1.
010 = Timer 2.
011 = Timer 3.
100 = DMA0 Control register: UART0 Received Data register contains valid data.
DMA1 Control register: UART0 Transmit Data register empty.
101 = DMA0 Control register: UART1 Received Data register contains valid data. DMA1
Control register: UART1 Transmit Data register empty.
110 = DMA0 Control register: I2C Receiver Interrupt. DMA1 Control register: I2C
Transmitter Interrupt register empty.
111 = Reserved.
DMAx I/O Address Register
The DMAx I/O Address register (Table 78) contains the low byte of the on-chip peripheral
address for data transfer. The full 12-bit Register File address is given by {FH,
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DMAx_IO[7:0]}. When the DMA is configured for two-byte word transfers, the
DMAx I/O Address register must contain an even numbered address.
Table 78. DMAx I/O Address Register (DMAxIO)
BITS
7
6
5
4
3
FIELD
DMA_IO
RESET
X
2
1
0
R/W
R/W
FB1H, FB9H
ADDR
DMA_IO—DMA on-chip peripheral control register address
This byte sets the low byte of the on-chip peripheral control register address on Register
File Page FH (addresses F00H to FFFH).
DMAx Address High Nibble Register
The DMAx Address High register (Table 79) specifies the upper four bits of address for
the Start/Current and End Addresses of DMAx.
Table 79. DMAx Address High Nibble Register (DMAxH)
BITS
FIELD
RESET
R/W
ADDR
7
6
5
4
3
DMA_END_H
2
1
0
DMA_START_H
X
R/W
FB2H, FBAH
DMA_END_H—DMAx End Address High Nibble
These bits, used with the DMAx End Address Low register, form a 12-bit End Address.
The full 12-bit address is given by {DMA_END_H[3:0], DMA_END[7:0]}.
DMA_START_H—DMAx Start/Current Address High Nibble
These bits, used with the DMAx Start/Current Address Low register, form a 12-bit
Start/Current Address. The full 12-bit address is given by {DMA_START_H[3:0],
DMA_START[7:0]}.
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DMAx Start/Current Address Low Byte Register
The DMAx Start/Current Address Low register, in conjunction with the DMAx Address
High Nibble register, forms a 12-bit Start/Current Address. Writes to this register set the
Start Address for DMA operations. Each time the DMA completes a data transfer, the
12-bit Start/Current Address increments by either 1 (single-byte transfer) or 2 (two-byte
word transfer). Reads from this register return the low byte of the Current Address to be
used for the next DMA data transfer.
Table 80. DMAx Start/Current Address Low Byte Register (DMAxSTART)
BITS
7
6
5
4
3
FIELD
DMA_START
RESET
X
2
1
0
R/W
R/W
FB3H, FBBH
ADDR
DMA_START—DMAx Start/Current Address Low
These bits, with the four lower bits of the DMAx_H register, form the 12-bit Start/Current
address. The full 12-bit address is given by {DMA_START_H[3:0], DMA_START[7:0]}.
DMAx End Address Low Byte Register
The DMAx End Address Low Byte register (Table 80), in conjunction with the DMAx_H
register (Table 81), forms a 12-bit End Address.
Table 81. DMAx End Address Low Byte Register (DMAxEND)
BITS
7
6
5
4
3
FIELD
DMA_END
RESET
X
R/W
ADDR
2
1
0
R/W
FB4H, FBCH
DMA_END—DMAx End Address Low
These bits, with the four upper bits of the DMAx_H register, form a 12-bit address. This
address is the ending location of the DMAx transfer. The full 12-bit address is given by
{DMA_END_H[3:0], DMA_END[7:0]}.
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DMA_ADC Address Register
The DMA_ADC Address register (Table 83) points to a block of the Register File to store
ADC conversion values as displayed in Table 82. This register contains the seven mostsignificant bits of the 12-bit Register File addresses. The five least-significant bits are calculated from the ADC Analog Input number (5-bit base address is equal to twice the ADC
Analog Input number). The 10-bit ADC conversion data is stored as two bytes with the
most significant byte of the ADC data stored at the even numbered Register File address.
Table 82 provides an example of the Register File addresses if the DMA_ADC Address
register contains the value 72H.
Table 82. DMA_ADC Register File Address Example
ADC Analog Input
Register File Address (Hex)1
0
720H-721H
1
722H-723H
2
724H-725H
3
726H-727H
4
728H-729H
5
72AH-72BH
6
72CH-72DH
7
72EH-72FH
8
730H-731H
9
732H-733H
10
734H-735H
11
736H-737H
1DMAA_ADDR
set to 72H.
Table 83. DMA_ADC Address Register (DMAA_ADDR)
BITS
FIELD
RESET
R/W
ADDR
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7
6
5
4
3
DMAA_ADDR
2
1
0
Reserved
X
R/W
FBDH
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DMAA_ADDR—DMA_ADC Address
These bits specify the seven most-significant bits of the 12-bit Register File addresses
used for storing the ADC output data. The ADC Analog Input Number defines the five
least-significant bits of the Register File address. Full 12-bit address is
{DMAA_ADDR[7:1], 4-bit ADC Analog Input Number, 0}.
Reserved
This bit is reserved and must be 0.
DMA_ADC Control Register
The DMA_ADC Control register (Table 84 on page 172) enables and sets options (DMA
enable and interrupt enable) for ADC operation.
Table 84. DMA_ADC Control Register (DMAACTL)
BITS
FIELD
7
6
DAEN
IRQEN
5
4
3
Reserved
2
1
0
ADC_IN
0
RESET
R/W
R/W
FBEH
ADDR
DAEN—DMA_ADC Enable
0 = DMA_ADC is disabled and the ADC Analog Input Number (ADC_IN) is reset to 0.
1 = DMA_ADC is enabled.
IRQEN—Interrupt Enable
0 = DMA_ADC does not generate any interrupts.
1 = DMA_ADC generates an interrupt after transferring data from the last ADC Analog
Input specified by the ADC_IN field.
Reserved
These bits are reserved and must be 0.
ADC_IN—ADC Analog Input Number
These bits set the number of ADC Analog Inputs to be used in the continuous update
(data conversion followed by DMA data transfer). The conversion always begins with
ADC Analog Input 0 and then progresses sequentially through the other selected ADC
Analog Inputs.
0000 = ADC Analog Input 0 updated.
0001 = ADC Analog Inputs 0-1 updated.
0010 = ADC Analog Inputs 0-2 updated.
0011 = ADC Analog Inputs 0-3 updated.
0100 = ADC Analog Inputs 0-4 updated.
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0101 = ADC Analog Inputs 0-5 updated.
0110 = ADC Analog Inputs 0-6 updated.
0111 = ADC Analog Inputs 0-7 updated.
1000 = ADC Analog Inputs 0-8 updated.
1001 = ADC Analog Inputs 0-9 updated.
1010 = ADC Analog Inputs 0-10 updated.
1011 = ADC Analog Inputs 0-11 updated.
1100-1111 = Reserved.
DMA Status Register
The DMA Status register (Table 85 on page 173) indicates the DMA channel that generated the interrupt and the ADC Analog Input that is currently undergoing conversion.
Reads from this register reset the Interrupt Request Indicator bits (IRQA, IRQ1, and
IRQ0) to 0. Therefore, software interrupt service routines that read this register must process all three interrupt sources from the DMA.
Table 85. DMA_ADC Status Register (DMAA_STAT)
BITS
FIELD
7
6
5
4
CADC[3:0]
RESET
0
R/W
R
3
2
1
0
Reserved
IRQA
IRQ1
IRQ0
FBFH
ADDR
CADC[3:0]—Current ADC Analog Input
This field identifies the Analog Input that the ADC is currently converting.
Reserved
This bit is reserved and must be 0.
IRQA—DMA_ADC Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
0 = DMA_ADC is not the source of the interrupt from the DMA Controller.
1 = DMA_ADC completed transfer of data from the last ADC Analog Input and generated
an interrupt.
IRQ1—DMA1 Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
0 = DMA1 is not the source of the interrupt from the DMA Controller.
1 = DMA1 completed transfer of data to/from the End Address and generated an interrupt.
IRQ0—DMA0 Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
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0 = DMA0 is not the source of the interrupt from the DMA Controller.
1 = DMA0 completed transfer of data to/from the End Address and generated an interrupt.
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Analog-to-Digital Converter
Overview
The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary
number. The features of the sigma-delta ADC include:
•
•
•
•
12 analog input sources are multiplexed with general-purpose I/O ports
Interrupt upon conversion complete
Internal voltage reference generator
Direct Memory Access (DMA) controller can automatically initiate data conversion
and transfer of the data from 1 to 12 of the analog inputs
Architecture
Figure 34 displays the three major functional blocks (converter, analog multiplexer, and
voltage reference generator) of the ADC. The ADC converts an analog input signal to its
digital representation. The 12-input analog multiplexer selects one of the 12 analog input
sources. The ADC requires an input reference voltage for the conversion. The voltage
reference for the conversion may be input through the external VREF pin or generated
internally by the voltage reference generator.
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VREF
Internal Voltage
Reference Generator
Analog Input
Multiplexer
ANA0
ANA1
ANA2
Analog-to-Digital
Converter
ANA3
ANA4
ANA5
Reference Input
ANA6
ANA7
ANA8
Analog Input
ANA9
ANA10
ANA11
ANAIN[3:0]
Figure 34. Analog-to-Digital Converter Block Diagram
The sigma-delta ADC architecture provides alias and image attenuation below the amplitude resolution of the ADC in the frequency range of DC to one-half the ADC clock rate
(one-fourth the system clock rate). The ADC provides alias free conversion for frequencies up to one-half the ADC clock rate. Thus the sigma-delta ADC exhibits high noise
immunity making it ideal for embedded applications. In addition, monotonicity (no missing codes) is guaranteed by design.
Operation
Automatic Power-Down
If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles,
portions of the ADC are automatically powered-down. From this power-down state, the
ADC requires 40 system clock cycles to power-up. The ADC powers up when a conversion is requested using the ADC Control register.
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Single-Shot Conversion
When configured for single-shot conversion, the ADC performs a single analog-to-digital
conversion on the selected analog input channel. After completion of the conversion, the
ADC shuts down. Follow the steps below for setting up the ADC and initiating a singleshot conversion:
1. Enable the desired analog inputs by configuring the general-purpose I/O pins for
alternate function. This configuration disables the digital input and output drivers.
2. Write to the ADC Control register to configure the ADC and begin the conversion.
The bit fields in the ADC Control register can be written simultaneously:
– Write to the ANAIN[3:0] field to select one of the 12 analog input sources.
– Clear CONT to 0 to select a single-shot conversion.
– Write to the VREF bit to enable or disable the internal voltage reference generator.
– Set CEN to 1 to start the conversion.
3. CEN remains 1 while the conversion is in progress. A single-shot conversion requires
5129 system clock cycles to complete. If a single-shot conversion is requested from an
ADC powered-down state, the ADC uses 40 additional clock cycles to power-up
before beginning the 5129 cycle conversion.
4. When the conversion is complete, the ADC control logic performs the following
operations:
– 10-bit data result written to {ADCD_H[7:0], ADCD_L[7:6]}.
– CEN resets to 0 to indicate the conversion is complete.
– An interrupt request is sent to the Interrupt Controller.
5. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
powered-down.
Continuous Conversion
When configured for continuous conversion, the ADC continuously performs an analogto-digital conversion on the selected analog input. Each new data value over-writes the
previous value stored in the ADC Data registers. An interrupt is generated after each conversion.
Caution: In CONTINUOUS mode, you must be aware that ADC updates are limited by
the input signal bandwidth of the ADC and the latency of the ADC and its digital filter. Step changes at the input are not seen at the next output from the
ADC. The response of the ADC (in all modes) is limited by the input signal
bandwidth and the latency.
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Follow the steps below for setting up the ADC and initiating continuous conversion:
1. Enable the desired analog input by configuring the general-purpose I/O pins for
alternate function. This disables the digital input and output driver.
2. Write to the ADC Control register to configure the ADC for continuous conversion.
The bit fields in the ADC Control register may be written simultaneously:
– Write to the ANAIN[3:0] field to select one of the 12 analog input sources.
– Set CONT to 1 to select continuous conversion.
– Write to the VREF bit to enable or disable the internal voltage reference generator.
– Set CEN to 1 to start the conversions.
3. When the first conversion in continuous operation is complete (after 5129 system
clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic
performs the following operations:
– CEN resets to 0 to indicate the first conversion is complete. CEN remains 0 for all
subsequent conversions in continuous operation.
– An interrupt request is sent to the Interrupt Controller to indicate the conversion is
complete.
4. Thereafter, the ADC writes a new 10-bit data result to {ADCD_H[7:0],
ADCD_L[7:6]} every 256 system clock cycles. An interrupt request is sent to the
Interrupt Controller when each conversion is complete.
5. To disable continuous conversion, clear the CONT bit in the ADC Control register
to 0.
DMA Control of the ADC
The Direct Memory Access (DMA) Controller can control operation of the ADC including analog input selection and conversion enable. For more information on the DMA and
configuring for ADC operations, see Direct Memory Access Controller on page 165.
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ADC Control Register Definitions
ADC Control Register
The ADC Control register selects the analog input channel and initiates the analog-to-digital conversion.
Table 86. ADC Control Register (ADCCTL)
BITS
FIELD
7
6
5
4
CEN
Reserved
VREF
CONT
RESET
0
3
2
1
0
ANAIN[3:0]
1
0
R/W
R/W
ADDR
F70H
CEN—Conversion Enable
0 = Conversion is complete. Writing a 0 produces no effect. The ADC automatically clears
this bit to 0 when a conversion has been completed.
1 = Begin conversion. Writing a 1 to this bit starts a conversion. If a conversion is already
in progress, the conversion restarts. This bit remains 1 until the conversion is complete.
Reserved—Must be 0.
VREF
0 = Internal voltage reference generator enabled. The VREF pin should be left unconnected (or capacitively coupled to analog ground) if the internal voltage reference is
selected as the ADC reference voltage.
1 = Internal voltage reference generator disabled. An external voltage reference must be
provided through the VREF pin.
CONT
0 = Single-shot conversion. ADC data is output once at completion of the 5129 system
clock cycles.
1 = Continuous conversion. ADC data updated every 256 system clock cycles.
ANAIN—Analog Input Select
These bits select the analog input for conversion. Not all Port pins in this list are available
in all packages for the Z8F642x family Z8R642x family of products. For information on
the Port pins available with each package style, see Signal and Pin Descriptions on page 7.
Do not enable unavailable analog inputs.
0000 = ANA0
0001 = ANA1
0010 = ANA2
0011 = ANA3
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0100 = ANA4
0101 = ANA5
0110 = ANA6
0111 = ANA7
1000 = ANA8
1001 = ANA9
1010 = ANA10
1011 = ANA11
11XX = Reserved.
ADC Data High Byte Register
The ADC Data High Byte register (Table 87) contains the upper eight bits of the 10-bit
ADC output. During a single-shot conversion, this value is invalid. Access to the ADC
Data High Byte register is read-only. The full 10-bit ADC result is given by
{ADCD_H[7:0], ADCD_L[7:6]}. Reading the ADC Data High Byte register latches data
in the ADC Low Bits register.
Table 87. ADC Data High Byte Register (ADCD_H)
BITS
7
6
5
4
3
FIELD
ADCD_H
RESET
X
R/W
R
2
1
0
F72H
ADDR
ADCD_H—ADC Data High Byte
This byte contains the upper eight bits of the 10-bit ADC output. These bits are not valid
during a single-shot conversion. During a continuous conversion, the last conversion output is held in this register. These bits are undefined after a Reset.
ADC Data Low Bits Register
The ADC Data Low Bits register (Table 88) contains the lower two bits of the conversion
value. The data in the ADC Data Low Bits register is latched each time the ADC Data
High Byte register is read. Reading this register always returns the lower two bits of the
conversion last read into the ADC High Byte register. Access to the ADC Data Low Bits
register is read-only. The full 10-bit ADC result is given by {ADCD_H[7:0],
ADCD_L[7:6]}.
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Table 88. ADC Data Low Bits Register (ADCD_L)
BITS
FIELD
7
6
5
4
3
ADCD_L
1
0
Reserved
RESET
X
R/W
R
ADDR
2
F73H
ADCD_L—ADC Data Low Bits
These are the least significant two bits of the 10-bit ADC output. These bits are undefined
after a Reset.
Reserved
These bits are reserved and are always undefined.
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Flash Memory
Overview
The products in the Z8 Encore! XP 64K Series Flash Microcontrollers feature up to 64 KB
(65,536 bytes) of non-volatile Flash memory with read/write/erase capability. The Flash
memory can be programmed and erased in-circuit by either user code or through the OnChip Debugger.
The Flash memory array is arranged in 512-byte per page. The 512-byte page is the
minimum Flash block size that can be erased. The Flash memory is also divided into 8
sectors which can be protected from programming and erase operations on a per sector
basis.
Table 89 describes the Flash memory configuration for each device in the 64K Series.
Table 90 on page 184 lists the sector address ranges. Figure 35 on page 184 displays the
Flash memory arrangement.
Table 89. Flash Memory Configurations
Sector Size
Pages
per
Sector
Part Number
Flash Size
Z8F162x
16K (16,384)
32
0000H - 3FFFH
2K (2048)
8
4
Z8F242x
24K (24,576)
48
0000H - 5FFFH
4K (4096)
6
8
Z8F322x
32K (32,768)
64
0000H - 7FFFH
4K (4096)
8
8
Z8F482x
48K (49,152)
96
0000H - BFFFH
8K (8192)
6
16
Z8F642x
64K (65,536)
128
0000H - FFFFH
8K (8192)
8
16
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Table 90. Flash Memory Sector Addresses
Flash Sector Address Ranges
Sector Number
Z8F162x
Z8F242x
Z8F322x
Z8F482x
Z8F642x
0
0000H-07FFH
0000H-0FFFH
0000H-0FFFH
0000H-1FFFH
0000H-1FFFH
1
0800H-0FFFH
1000H-1FFFH
1000H-1FFFH
2000H-3FFFH
2000H-3FFFH
2
1000H-17FFH
2000H-2FFFH
2000H-2FFFH
4000H-5FFFH
4000H-5FFFH
3
1800H-1FFFH
3000H-3FFFH
3000H-3FFFH
6000H-7FFFH
6000H-7FFFH
4
2000H-27FFH
4000H-4FFFH
4000H-4FFFH
8000H-9FFFH
8000H-9FFFH
5
2800H-2FFFH
5000H-5FFFH
5000H-5FFFH
A000H-BFFFH
A000H-BFFFH
6
3000H-37FFH
N/A
6000H-6FFFH
N/A
C000H-DFFFH
7
3800H-3FFFH
N/A
7000H-7FFFH
N/A
E000H-FFFFH
64 KB Flash
Program Memory
Addresses
FFFFH
FE00H
FDFFH
FC00H
FBFFH
FA00H
128 Pages
512 Bytes per Page
05FFH
0400H
03FFH
0200H
01FFH
0000H
Figure 35. Flash Memory Arrangement
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Information Area
Table 91 describes the 64K Series Information Area. This 512-byte Information Area is
accessed by setting bit 7 of the Page Select Register to 1. When access is enabled, the
Information Area is mapped into Flash Memory and overlays the 512 bytes at addresses
FE00H to FFFFH. When the Information Area access is enabled, LDC instructions return
data from the Information Area. CPU instruction fetches always comes from Flash Memory regardless of the Information Area access bit. Access to the Information Area is readonly.
Table 91. Z8 Encore! XP 64K Series Flash Microcontrollers Information Area Map
Flash Memory Address (Hex)
Function
FE00H-FE3FH
Reserved
FE40H-FE53H
Part Number
20-character ASCII alphanumeric code
Left justified and filled with zeros
FE54H-FFFFH
Reserved
Operation
The Flash Controller provides the proper signals and timing for Byte Programming, Page
Erase, and Mass Erase of the Flash memory. The Flash Controller contains a protection
mechanism, via the Flash Control register (FCTL), to prevent accidental programming or
erasure. The following subsections provide details on the various operations (Lock,
Unlock, Sector Protect, Byte Programming, Page Erase, and Mass Erase).
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Timing Using the Flash Frequency Registers
Before performing a program or erase operation on the Flash memory, you must first
configure the Flash Frequency High and Low Byte registers. The Flash Frequency
registers allow programming and erasure of the Flash with system clock frequencies
ranging from 20 kHz through 20 MHz (the valid range is limited to the device operating
frequencies).
The Flash Frequency High and Low Byte registers combine to form a 16-bit value,
FFREQ, to control timing for Flash program and erase operations. The 16-bit Flash
Frequency value must contain the system clock frequency in kHz. This value is calculated
using the following equation:.
System Clock Frequency (Hz)
FFREQ[15:0] = -----------------------------------------------------------------------1000
Caution: Flash programming and erasure are not supported for system clock frequencies
below 20 kHz, above 20 MHz, or outside of the device operating frequency
range. The Flash Frequency High and Low Byte registers must be loaded with
the correct value to insure proper Flash programming and erase operations.
Flash Read Protection
The user code contained within the Flash memory can be protected from external access.
Programming the Flash Read Protect Option Bit prevents reading of user code by the OnChip Debugger or by using the Flash Controller Bypass mode. For more information, see
Option Bits on page 195 and On-Chip Debugger on page 199.
Flash Write/Erase Protection
The 64K Series provides several levels of protection against accidental program and erasure of the Flash memory contents. This protection is provided by the Flash Controller
unlock mechanism, the Flash Sector Protect register, and the Flash Write Protect option
bit.
Flash Controller Unlock Mechanism
At Reset, the Flash Controller locks to prevent accidental program or erasure of the Flash
memory. To program or erase the Flash memory, the Flash controller must be unlocked.
After unlocking the Flash Controller, the Flash can be programmed or erased. Any value
written by user code to the Flash Control register or Page Select Register out of sequence
will lock the Flash Controller.
Follow the steps below to unlock the Flash Controller from user code:
1. Write 00H to the Flash Control register to reset the Flash Controller.
2. Write the page to be programmed or erased to the Page Select register.
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3. Write the first unlock command 73H to the Flash Control register.
4. Write the second unlock command 8CH to the Flash Control register.
5. Re-write the page written in step 2 to the Page Select register.
Flash Sector Protection
The Flash Sector Protect register can be configured to prevent sectors from being
programmed or erased. Once a sector is protected, it cannot be unprotected by user code.
The Flash Sector Protect register is cleared after reset and any previously written
protection values is lost. User code must write this register in their initialization routine if
they want to enable sector protection.
The Flash Sector Protect register shares its Register File address with the Page Select
register. The Flash Sector Protect register is accessed by writing the Flash Control register
with 5EH. Once the Flash Sector Protect register is selected, it can be accessed at the Page
Select Register address. When user code writes the Flash Sector Protect register, bits can
only be set to 1. Thus, sectors can be protected, but not unprotected, via register write
operations. Writing a value other than 5EH to the Flash Control register de-selects the
Flash Sector Protect register and re-enables access to the Page Select register.
Follow the steps below to setup the Flash Sector Protect register from user code:
1. Write 00H to the Flash Control register to reset the Flash Controller.
2. Write 5EH to the Flash Control register to select the Flash Sector Protect register.
3. Read and/or write the Flash Sector Protect register which is now at Register File
address FF9H.
4. Write 00H to the Flash Control register to return the Flash Controller to its reset state.
Flash Write Protection Option Bit
The Flash Write Protect option bit can be enabled to block all program and erase operations from user code. For more information, see Option Bits on page 195.
Byte Programming
When the Flash Controller is unlocked, writes to Flash Memory from user code will program a byte into the Flash if the address is located in the unlocked page. An erased Flash
byte contains all ones (FFH). The programming operation can only be used to change bits
from one to zero. To change a Flash bit (or multiple bits) from zero to one requires a Page
Erase or Mass Erase operation.
Byte Programming can be accomplished using the eZ8 CPU’s LDC or LDCI instructions.
For a description of the LDC and LDCI instructions, refer to eZ8™ CPU Core User Manual (UM0128).
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While the Flash Controller programs the Flash memory, the eZ8 CPU idles but the system
clock and on-chip peripherals continue to operate. Interrupts that occur when a Programming operation is in progress are serviced once the Programming operation is complete.
To exit Programming mode and lock the Flash Controller, write 00H to the Flash Control
register.
User code cannot program Flash Memory on a page that lies in a protected sector. When
user code writes memory locations, only addresses located in the unlocked page are programmed. Memory writes outside of the unlocked page are ignored.
Caution: Each memory location must not be programmed more than twice before an
erase occurs.
Follow the steps below to program the Flash from user code:
1. Write 00H to the Flash Control register to reset the Flash Controller.
2. Write the page of memory to be programmed to the Page Select register.
3. Write the first unlock command 73H to the Flash Control register.
4. Write the second unlock command 8CH to the Flash Control register.
5. Re-write the page written in step 2 to the Page Select register.
6. Write Flash Memory using LDC or LDCI instructions to program the Flash.
7. Repeat step 6 to program additional memory locations on the same page.
8. Write 00H to the Flash Control register to lock the Flash Controller.
Page Erase
The Flash memory can be erased one page (512 bytes) at a time. Page Erasing the Flash
memory sets all bytes in that page to the value FFH. The Page Select register identifies the
page to be erased. While the Flash Controller executes the Page Erase operation, the eZ8
CPU idles but the system clock and on-chip peripherals continue to operate. The eZ8 CPU
resumes operation after the Page Erase operation completes. Interrupts that occur when
the Page Erase operation is in progress are serviced once the Page Erase operation is complete. When the Page Erase operation is complete, the Flash Controller returns to its
locked state. Only pages located in unprotected sectors can be erased.
Follow the steps below to perform a Page Erase operation:
1. Write 00H to the Flash Control register to reset the Flash Controller.
2. Write the page to be erased to the Page Select register.
3. Write the first unlock command 73H to the Flash Control register.
4. Write the second unlock command 8CH to the Flash Control register.
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5. Re-write the page written in step 2 to the Page Select register.
6. Write the Page Erase command 95H to the Flash Control register.
Mass Erase
The Flash memory cannot be Mass Erased by user code.
Flash Controller Bypass
The Flash Controller can be bypassed and the control signals for the Flash memory
brought out to the GPIO pins. Bypassing the Flash Controller allows faster Programming
algorithms by controlling the Flash programming signals directly.
Flash Controller Bypass is recommended for gang programming applications and large
volume customers who do not require in-circuit programming of the Flash memory.
For more information on bypassing the Flash Controller, refer to Third-Party Flash Programming Support for Z8 Encore! available for download at www.zilog.com.
Flash Controller Behavior in Debug Mode
The following changes in behavior of the Flash Controller occur when the Flash Controller is accessed using the On-Chip Debugger:
•
•
•
The Flash Write Protect option bit is ignored.
•
•
Bits in the Flash Sector Protect register can be written to one or zero.
•
•
The Page Select register can be written when the Flash Controller is unlocked.
The Flash Sector Protect register is ignored for programming and erase operations.
Programming operations are not limited to the page selected in the Page Select
register.
The second write of the Page Select register to unlock the Flash Controller is not
necessary.
The Mass Erase command is enabled through the Flash Control register.
Caution: For security reasons, Flash controller allows only a single page to be opened for
write/erase. When writing multiple Flash pages, the Flash controller must go
through the unlock sequence again to select another page.
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Flash Control Register Definitions
Flash Control Register
The Flash Control register (Table 92) unlocks the Flash Controller for programming and
erase operations, or to select the Flash Sector Protect register.
The Write-only Flash Control Register shares its Register File address with the Read-only
Flash Status Register.
Table 92. Flash Control Register (FCTL)
BITS
7
6
5
4
3
FIELD
FCMD
RESET
0
R/W
W
2
1
0
FF8H
ADDR
FCMD—Flash Command
73H = First unlock command.
8CH = Second unlock command.
95H = Page erase command.
63H = Mass erase command
5EH = Flash Sector Protect register select.
* All other commands, or any command out of sequence, lock the Flash Controller.
Flash Status Register
The Flash Status register (Table 93) indicates the current state of the Flash Controller. This
register can be read at any time. The Read-only Flash Status Register shares its Register
File address with the Write-only Flash Control Register.
Table 93. Flash Status Register (FSTAT)
BITS
FIELD
7
6
5
4
3
Reserved
0
R/W
R
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ADDR
2
FF8H
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Reserved
These bits are reserved and must be 0.
FSTAT—Flash Controller Status
00_0000 = Flash Controller locked
00_0001 = First unlock command received
00_0010 = Second unlock command received
00_0011 = Flash Controller unlocked
00_0100 = Flash Sector Protect register selected
00_1xxx = Program operation in progress
01_0xxx = Page erase operation in progress
10_0xxx = Mass erase operation in progress
Page Select Register
The Page Select (FPS) register (Table 94) selects one of the 128 available Flash memory
pages to be erased or programmed. Each Flash Page contains 512 bytes of Flash memory.
During a Page Erase operation, all Flash memory locations with the 7 most significant bits
of the address given by the PAGE field are erased to FFH.
The Page Select register shares its Register File address with the Flash Sector Protect Register. The Page Select register cannot be accessed when the Flash Sector Protect register is
enabled.
Table 94. Page Select Register (FPS)
BITS
FIELD
7
6
5
4
3
INFO_EN
RESET
2
1
0
PAGE
0
R/W
R/W
ADDR
FF9H
INFO_EN—Information Area Enable
0 = Information Area is not selected.
1 = Information Area is selected. The Information area is mapped into the Flash Memory
address space at addresses FE00H through FFFFH.
PAGE—Page Select
This 7-bit field selects the Flash memory page for Programming and Page Erase operations. Flash Memory Address[15:9] = PAGE[6:0].
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Flash Sector Protect Register
The Flash Sector Protect register (Table 95) protects Flash memory sectors from being
programmed or erased from user code. The Flash Sector Protect register shares its Register File address with the Page Select register. The Flash Sector protect register can be
accessed only after writing the Flash Control register with 5EH.
User code can only write bits in this register to 1 (bits cannot be cleared to 0 by user code).
Table 95. Flash Sector Protect Register (FPROT)
BITS
FIELD
7
6
5
4
3
2
1
0
SECT7
SECT6
SECT5
SECT4
SECT3
SECT2
SECT1
SECT0
0
RESET
R/W
R/W1
ADDR
FF9H
Note: R/W1 = Register is accessible for Read operations. Register can be written to 1 only (via user code).
SECTn—Sector Protect
0 = Sector n can be programmed or erased from user code.
1 = Sector n is protected and cannot be programmed or erased from user code.
* User code can only write bits from 0 to 1.
Flash Frequency High and Low Byte Registers
The Flash Frequency High and Low Byte registers (Table 96 and Table 97) combine to
form a 16-bit value, FFREQ, to control timing for Flash program and erase operations.
The 16-bit Flash Frequency registers must be written with the system clock frequency in
kHz for Program and Erase operations. Calculate the Flash Frequency value using the following equation:
System Clock Frequency
FFREQ[15:0] = { FFREQH[7:0],FFREQL[7:0] } = -----------------------------------------------------------1000
Caution: Flash programming and erasure is not supported for system clock frequencies below 20 kHz, above 20 MHz, or outside of the valid operating frequency range for
the device. The Flash Frequency High and Low Byte registers must be loaded
with the correct value to insure proper program and erase times.
PS019919-1207
Flash Memory
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
193
Table 96. Flash Frequency High Byte Register (FFREQH)
BITS
7
6
5
4
3
FIELD
FFREQH
RESET
0
2
1
0
2
1
0
R/W
R/W
FFAH
ADDR
Table 97. Flash Frequency Low Byte Register (FFREQL)
BITS
7
6
5
4
3
FIELD
FFREQL
RESET
0
R/W
ADDR
R/W
FFBH
FFREQH and FFREQL—Flash Frequency High and Low Bytes
These 2 bytes, {FFREQH[7:0], FFREQL[7:0]}, contain the 16-bit Flash Frequency value.
PS019919-1207
Flash Memory
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
194
PS019919-1207
Flash Memory
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
195
Option Bits
Overview
Option Bits allow user configuration of certain aspects of the 64K Series operation. The
feature configuration data is stored in the Flash Memory and read during Reset. The features available for control via the Option Bits are:
•
•
•
•
Watchdog Timer time-out response selection–interrupt or Reset.
•
Voltage Brownout configuration-always enabled or disabled during STOP mode to
reduce STOP mode power consumption.
•
Oscillator mode selection-for high, medium, and low power crystal oscillators, or
external RC oscillator.
Watchdog Timer enabled at Reset.
The ability to prevent unwanted read access to user code in Flash Memory.
The ability to prevent accidental programming and erasure of the user code in Flash
Memory.
Operation
Option Bit Configuration By Reset
Each time the Option Bits are programmed or erased, the device must be Reset for the
change to take place. During any reset operation (System Reset, Reset, or Stop Mode
Recovery), the Option Bits are automatically read from the Flash Memory and written to
Option Configuration registers. The Option Configuration registers control operation of
the devices within the 64K Series. Option Bit control is established before the device exits
Reset and the eZ8 CPU begins code execution. The Option Configuration registers are not
part of the Register File and are not accessible for read or write access.
Option Bit Address Space
The first two bytes of Flash Memory at addresses 0000H (see Table 98 on page 196) and
0001H (see Table 99 on page 197) are reserved for the user Option Bits. The byte at Flash
Memory address 0000H configures user options. The byte at Flash Memory address
0001H is reserved for future use and must remain unprogrammed.
PS019919-1207
Option Bits
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
196
Flash Memory Address 0000H
Table 98. Flash Option Bits At Flash Memory Address 0000H
BITS
FIELD
7
6
WDT_RE
S
WDT_AO
5
4
OSC_SEL[1:0]
2
1
0
VBO_AO
RP
Reserved
FWP
U
RESET
R/W
R/W
ADDR
3
Program Memory 0000H
Note: U = Unchanged by Reset. R/W = Read/Write.
WDT_RES—Watchdog Timer Reset
0 = Watchdog Timer time-out generates an interrupt request. Interrupts must be globally
enabled for the eZ8 CPU to acknowledge the interrupt request.
1 = Watchdog Timer time-out causes a Short Reset. This setting is the default for unprogrammed (erased) Flash.
WDT_AO—Watchdog Timer Always On
0 = Watchdog Timer is automatically enabled upon application of system power. Watchdog Timer can not be disabled except during STOP Mode (if configured to power down
during STOP Mode).
1 = Watchdog Timer is enabled upon execution of the WDT instruction. Once enabled, the
Watchdog Timer can only be disabled by a Reset or Stop Mode Recovery. This setting is
the default for unprogrammed (erased) Flash.
OSC_SEL[1:0]—Oscillator Mode Selection
00 = On-chip oscillator configured for use with external RC networks (
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