Z8L18220AEC00TR

Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y P RELIMINARY P RODUCT S PECIFICATION Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™) FEATURES ■ Z8S180 MPU - Code Compatible with Zilog Z80®/Z180™ CPU - Extended Instructions - Operating Frequency: 33 MHz/5V or 20 MHz/3.3V - Two DMA Channels - On-Chip Wait State Generators - Two UART Channels - Two 16-Bit Timer Counters - On-Chip Interrupt Controller - On-Chip Clock Oscillator/Generator - Clocked Serial I/O Port - Fully Static - Low EMI Option ■ Two ESCC™ Channels with 32-Bit CRC ■ Three 8-Bit Parallel I/O Ports ■ 16550 Compatible MIMIC Interface for Direct Connection to PC, XT, AT Bus ■ 100-Pin Package Styles (QFP, VQFP) (0.8 Micron CMOS 5120 Technology) ■ Individual WSG for RAMCS and ROMCS GENERAL DESCRIPTION The Z80182/Z8L182 is a smart peripheral controller IC for modem (in particular V. Fast applications), fax, voice messaging and other communications applications. It uses the Z80180 microprocessor (Z8S180 MPU core) linked with two channels of the industry standard Z85230 ESCC (Enhanced Serial Communications Controller), 24 bits of parallel I/O, and a 16550 MIMIC for direct connection to the IBM PC, XT, AT bus. The Z80182/Z8L182 allows complete flexibility for both internal PC and external applications. Also current PC modem software compatibility can be maintained with the Z80182/Z8L182 ability to mimic the 16550 UART chip. The Z80180 acts as an interface between the ESCC™ and 16550 MIMIC interface when used in internal applications, and between the two ESCC channels in the external applications. This interface allows data compression and DS971820600 error correction on outgoing and incoming data. In external applications, three 8-bit parallel ports are available for driving LEDs or other devices. Figure 1 shows the Z80182/ Z8L182 block diagram, while the pin assignments for the QFP and the VQFP packages are shown in Figures 2 and 3, respectively. All references in this document to the Z80182, or Z182 refer to both the Z80182 and Z8L182. Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD PS009801-0301 VSS 3-1 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y GENERAL DESCRIPTION (Continued) D7-D0 Control EV1 GLU Logic A19-A0 EV2 Bus Transceiver Z8S180 (Static Z80180) MPU Core Tx Data Rx Data ESCC Control /ROMCS /RAMCS 85230 ESCC Channel A /TRxCB 16550 MIMIC Interface Address Decode 8-Bit Parallel Port C MUX 85230 ESCC Channel B 8-Bit Parallel Port B 8-Bit Parallel Port A MUX MUX 85230 ESCC Ch. A or Port C 16550 MIMIC or ESCC 85230 Ch. B and Port A Z180 Signals or Port B Note: Conventional use of the term "MPU side" refers to all interface through the Z180 MPU core and "PC side" refers to all interface through the16550 MIMIC interface. Figure 1. Z80182/Z8L182 Functional Block Diagram 3-2 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL /INT0 /INT1/PC6 /INT2/PC7 ST A0 1 100 90 95 85 RXDB/HA1 /MRD//MREQ /IORQ /RFSH /HALT /SYNCB//HCS /RTXCB/HA2 /M1 E PHI /RD /WR XTAL VSS /BUSREQ /BUSACK /WAIT EXTAL /NMI /RESET P R E L I M I N A R Y 80 TXDB//HDDIS /CTSB//HWR /DCDB//HRD TXDA 5 A1 A2 75 A3 A4 15 Z80182/Z8L182 100-Pin QFP 65 20 60 25 55 50 /TRXCA RXDA VDD IEI /IOCS/IEO VSS /RTXCA /SYNCA/PC4 /DCDA/PC0 /CTSA/PC1 /MWR/PC2//RTSA /DTR//REQA/PC3 /W//REQA/PC5 PA7/HD7 PA6/HD6 PA5/HD5 PA4/HD4 PA3/HD3 PA2/HD2 PA1/HD1 PA0/HD0 EV2 EV1 /ROMCS /RAMCS CKS//W//REQB//HTXRDY /DREQ1 VDD /TEND1//RTSB//HRXRDY 45 RXA1/PB6 RXS//CTS1/PB7 CKA0//DREQ0 VSS CKA1//TEND0 TXS//DTR//REQB//HINTR 40 TXA0/PB3 RXA0/PB4 TXA1/PB5 35 30 D4 D5 D6 A18/TOUT VDD A19 D0 D1 D2 D3 70 /RTS0/PB0 /CTS0/PB1 /DCD0/PB2 A7 A8 A9 A10 A11 A12 VSS A13 A14 A15 A16 A17 10 D7 A5 A6 /TRXCB/HA0 Figure 2. Z80182/Z8L182 100-Pin QFP Pin Configuration DS971820600 PS009801-0301 3-3 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y 75 TXDB//HDDIS /TRXCB/HA0 RXDB/HA1 /RTXCB/HA2 /SYNCB//HCS /HALT /RFSH /IORQ /MRD//MREQ E /M1 /WR /RD PHI VSS XTAL EXTAL /WAIT /BUSACK /BUSREQ /RESET /NMI /INT0 /INT1/PC6 /INT2/PC7 70 65 60 55 PA2/HD2 PA1/HD1 PA0/HD0 EV2 PA4/HD4 PA3/HD3 /CTSB//HWR /DCDB//HRD TXDA /TRXCA RXDA VDD IEI /IOCS/IEO VSS /RTXCA /SYNCA/PC4 /DCDA/PC0 /CTSA/PC1 /MWR/PC2//RTSA /DTR//REQA/PC3 /W//REQA/PC5 PA7/HD7 PA6/HD6 PA5/HD5 GENERAL DESCRIPTION (Continued) 51 50 76 80 45 85 40 Z80182/Z8L182 100-Pin VQFP 90 35 95 30 26 100 5 10 15 20 25 ST A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 VSS A13 A14 A15 A16 A17 A18/TOUT VDD A19 D0 D1 1 EV1 /ROMCS /RAMCS /TEND1//RTSB//HRXRDY VDD /DREQ1 CKS//W//REQB//HTXRDY TXS//DTR//REQB/HINTR CKA1//TEND0 VSS CKA0//DREQ0 RXS//CTS1/PB7 RXA1/PB6 TXA1/PB5 RXA0/PB4 TXA0/PB3 /DCD0/PB2 /CTS0/PB1 /RTS0/PB0 D7 D6 D5 D4 D3 D2 Figure 3. Z80182/Z8L182 100-Pin VQFP Pin Configuration 3-4 PS009801-0301 DS971820600 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL Z180 CPU SIGNALS A19-A0. Address Bus (input/output, active High, tri-state). A19-A0 form a 20-bit address bus. The Address Bus provides the address for memory data bus exchanges up to 1 Mbyte, and I/O data bus exchanges up to 64K. The address bus enters a high impedance state during reset and external bus acknowledge cycles, as well as during SLEEP and HALT states. This bus is an input when the external bus master is accessing the on-chip peripherals. Address line A18 is multiplexed with the output of PRT channel 1 (T OUT, selected as address output on reset). D7-D0. Data Bus (bi-directional, active High, tri-state). D7D0 constitute an 8-bit bi-directional data bus, used for the transfer of information to and from I/O and memory devices. The data bus enters the high impedance state during reset and external bus acknowledge cycles, as well as during SLEEP and HALT states. /RD. Read (input/output, active Low, tri-state). /RD indicates that the CPU wants to read data from memory or an I/O device. The addressed I/O or memory device should use this signal to gate data onto the CPU data bus. /WR. Write (input/output, active Low, tri-state). /WR indicates that the CPU data bus holds valid data to be stored at the addressed I/O or memory location. /IORQ. I/O Request (input/output, active Low, tri-state). /IORQ indicates that the address bus contains a valid I/O address for an I/O read or I/O write operation. /IORQ is also generated, along with /M1, during the acknowledgment of the /INT0 input signal to indicate that an interrupt response vector can be placed onto the data bus. This signal is analogous to the IOE signal of the Z64180. /M1. Machine Cycle 1 (input/output, active Low). Together with /MREQ, /M1 indicates that the current cycle is the opcode fetch cycle of an instruction execution; unless /M1E bit in the OMCR is cleared to 0. Together with /IORQ, /M1 indicates that the current cycle is for an interrupt acknowledge. It is also used with the /HALT and ST signals to decode status of the CPU machine cycle. This signal is analogous to the /LIR signal of the Z64180. /MREQ. Memory Request (input/output, active Low, tristate). /MREQ indicates that the address bus holds a valid address for a memory read or memory write operation. This signal is analogous to the /ME signal of the Z64180. /MREQ is multiplexed with /MRD on the /MRD//MREQ pin. The /MRD//MREQ pin is an input during adapter modes; is tri-state during bus acknowledge if the /MREQ function is selected; and is inactive High if /MRD function is selected. DS971820600 /MRD. Memory Read (input/output, active Low, tri-state). /MRD is active when both the internal /MREQ and /RD are active. /MRD is multiplexed with /MREQ on the /MRD //MREQ pin. The /MRD//MREQ pin is an input during adapter modes; is tri-state during bus acknowledge if /MREQ function is selected; and is inactive High if /MRD function is selected. The default function on power up is /MRD and may be changed by programming bit 3 of the Interrupt Edge/Pin MUX Register (xxDFH). /MWR. Memory Write (input/output, active Low, tri-state). /MWR is active when both the internal /MREQ and /WR are active. This /RTSA or PC2 combination is pin multiplexed with /MWR on the /MWR/PC2//RTSA pin. The default function of this pin on power up is /MWR, which may be changed by programming bit 3 in the Interrupt Edge/Pin MUX Register (xxDFH). /WAIT. (input/output active Low). /WAIT indicates to the MPU that the addressed memory or I/O devices are not ready for a data transfer. This input is used to induce additional clock cycles into the current machine cycle. The /WAIT input is sampled on the falling edge of T2 (and subsequent wait states). If the input is sampled Low, then additional wait states are inserted until the /WAIT input is sampled High, at which time execution will continue. /HALT. Halt/Sleep Status (input/output, active Low). This output is asserted after the CPU has executed either the HALT or SLEEP instruction, and is waiting for either nonmaskable or maskable interrupts before operation can resume. It is also used with the /M1 and ST signals to decode status of the CPU machine cycle. On exit of HALT/ SLEEP mode, the first instruction fetch can be delayed by 16 clock cycles after the /HALT pin goes High, if HALT 16 feature is selected. /BUSACK. Bus Acknowledge (input/output, active Low). /BUSACK indicates to the requesting device, the MPU address and data bus, and some control signals, have entered their high impedance state. /BUSREQ. Bus Request (input, active Low). This input is used by external devices (such as DMA controllers) to request access to the system bus. This request has a higher priority than /NMI and is always recognized at the end of the current machine cycle. This signal will stop the CPU from executing further instructions and places the address/data buses and other control signals, into the high impedance state. PS009801-0301 3-5 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL Z180 CPU SIGNALS (Continued) /NMI. Non-maskable interrupt (input, negative edge triggered). /NMI has a higher priority than /INT and is always recognized at the end of an instruction, regardless of the state of the interrupt enable flip-flops. This signal forces CPU execution to continue at location 0066H. /INT0. Maskable Interrupt Request 0 (input/output active Low). This signal is generated by external I/O devices. The CPU will honor this request at the end of the current instruction cycle as long as the /NMI and /BUSREQ signals are inactive. The CPU acknowledges this interrupt request with an interrupt acknowledge cycle. During this cycle, both the /M1 and /IORQ signals become active. The internal Z180 MPU’s /INT0 source is: /INT0 or ESCC or the MIMIC. This input is level triggered. /INT0 is an open-drain output, so you can connect other open-drain interrupts onto the circuit in addition to haveing a pull-up to VCC. /INT1, /INT2. Maskable Interrupt Requests 1 and 2 (inputs, active Low). This signal is generated by external I/O devices. The CPU will honor these requests at the end of the current instruction cycle as long as the /NMI, /BUSREQ, and /INT0 signals are inactive. The CPU acknowledges these interrupt requests with an interrupt acknowledge cycle. Unlike the acknowledgment for /INT0, during this cycle neither the /M1 or /IORQ signals become active. These pins may be programmed to provide an active Low level on rising or falling edge interrupts. The level of the external /INT1 and /INT2 pins may be read through bits PC6 and PC7 of parallel Port C. Pin /INT1/PC6 multiplexes /INT1 and PC6. Pin /INT2/PC7 multiplexes /INT2 and PC7. /RFSH. Refresh (input/output, active Low, tri-state). Together with /MREQ, /RFSH indicates that the current CPU machine cycle and the contents of the address bus should be used for refresh of dynamic memories. The low order 8 bits of the address bus (A7-A0) contain the refresh address. This signal is analogous to the /REF signal of the Z64180. Z180 MPU UART AND SIO SIGNALS CKA0, CKA1. Asynchronous Clocks 0 and 1 (bi-directional, active High). These pins are the transmit and receive clocks for the synchronous channels. CKA0 is multiplexed with /DREQ0 on the CKA0//DREQ0 pin. CKA1 is multiplexed with /TEND0 on the CKA1//TEND0 pin. CKS. Serial Clock (bi-directional, active High). This line is clock for the CSIO channel and is multiplexed with the ESCC signal (/W//REQB) and the 16550 MIMIC interface signal /HTxRDY on the CKS//W//REQB//HTxRDY pin. /DCD0. Data Carrier Detect 0 (input, active Low). This is a programmable modem control signal for ASCI channel 0. /DCD0 is multiplexed with the PB2 (parallel Port B, bit 2) on the /DCD0/PB2 pin. /RTS0. Request to Send 0 (output, active Low). This is a programmable modem control signal for ASCI channel 0. This pin is multiplexed with PB0 (parallel Port B, bit 0) on the /RTS0/PB0 pin. /CTS0. Clear to Send 0 (input, active Low). This line is a modem control signal for the ASCI channel 0. This pin is multiplexed with PB1 (parallel Port B, bit 1) on the /CTS0 /PB1 pin. 3-6 TxA0. Transmit Data 0 (output, active High). This signal is the transmitted data from the ASCI channel 0. This pin is multiplexed with PB3 (parallel Port B, bit 3) on the TxA0/PB3 pin. TxS. Clocked Serial Transmit Data (output, active High). This line is the transmitted data from the CSIO channel. TxS is multiplexed with the ESCC signal (/DTR//REQB) and the 16550 MIMIC interface signal HINTR on the TxS//DTR //REQB//HINTR pin. RxA0. Receive Data 0 (input, active High). This signal is the receive data to ASCI channel 0. This pin is multiplexed with PB4 (parallel Port B, bit 4) on the RxA0/PB4. RxS. Clocked Serial Receive Data (input, active High). This line is the receive data for the CSIO channel. RxS is multiplexed with the /CTS1 signal for ASCI channel 1 and with PB7 (parallel Port B, bit 7) on the RxS//CTS1/PB7 pin. RxA1. Received Data ASCI channel 1 (input, active High). This pin is multiplexed with PB6 (parallel Port B, bit 6) on the RxA1/PB6 pin. TxA1. Transmitted Data ASCI Channel 1 (output, active High). This pin is multiplexed with PB5 (parallel Port B, bit 5) on the TxA1/PB5 pin. PS009801-0301 DS971820600 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL Z180 MPU DMA SIGNALS /TEND0. Transfer End 0 (output, active Low). This output is asserted active during the last write cycle of a DMA operation. It is used to indicate the end of the block transfer. /TEND0 is multiplexed with CKA1 on the CKA1//TEND0 pin. /TEND1. Transfer End 1 (output, active Low). This output is asserted active during the last write cycle of a DMA operation. It is used to indicate the end of the block transfer. /TEND1 is multiplexed with the ESCC signal /RTSB and the 16550 MIMIC interface signal /HRxRDY on the /TEND1//RTSB//HRxRDY pin. /DREQ0. DMA request 0 (input, active Low). /DREQ0 is used to request a DMA transfer from DMA channel 0. The DMA channel monitors the input to determine when an external device is ready for a read or write operation. This input can be programmed to be either level or edge sensed. /DREQ0 is multiplexed with CKA0 on the CKA0//DREQ0 pin. /DREQ1. DMA request 1 (input, active Low). /DREQ1 is used to request a DMA transfer from DMA channel 1. The DMA channel monitors the input to determine when an external device is ready for a read or write operation. This input can be programmed to be either level or edge sensed. Z180™ MPU TIMER SIGNALS T OUT. Timer Out (output, active High). TOUT is the pulse output from PRT channel 1. This line is multiplexed with A18 of the address bus on the A18/TOUT pin. Z85230 ESCC™ SIGNALS TxDA. Transmit Data (output, active High). This output signal transmits channel A’s serial data at standard TTL levels. This output can be tri-stated during power down modes. TxDB. Transmit Data (output, active High). This output signal transmits channel B’s serial data at standard TTL levels. In Z80182/Z8L182 mode 1, TxDB is multiplexed with the 16550 MIMIC interface /HDDIS signal on the TxDB//HDDIS pin. RxDA. Receive Data (inputs, active High). These inputs receive channel A’s serial data at standard TTL levels. RxDB. Receive Data (input, active High). These inputs receive channel B’s serial data at standard TTL levels. In Z80182/Z8L182 mode 1 RxDB is multiplexed with the 16550 MIMIC HA1 input on the RxDB/HA1 pin. /TRxCA. Transmit/Receive Clock (input or output, active Low). The functions of this pin are under channel A program control. /TRxCA may supply the receive clock or the transmit clock in the Input mode or supply the output of the digital phase-locked loop, the crystal oscillator, the baud rate generator, or the transmit clock in the output mode. /TRxCB. Transmit/Receive Clock (input or output, active Low). The functions of this pin are under channel B program DS971820600 control. /TRxCB may supply the receive clock or the transmit clock in the input mode or supply the output of the Digital Phase-Locked Loop (DPLL), the crystal oscillator, the baud rate generator, or the transmit clock in output mode. In Z80182/Z8L182 mode 1 /TRxCB is multiplexed with the 16550 MIMIC interface HA0 input on the /TRxCB/HA0 pin. /RTxCA. Receive/Transmit Clock (input, active Low). The functions of this pin are under channel A program control. In channel A, /RTxCA may supply the receive clock, the transmit clock, the clock for the baud rate generator, or the clock for the DPLL. This pin can also be programmed for use by the /SYNCA pin as a crystal oscillator. The receive clock may be 1, 16, 32, or 64 times the data rate in asynchronous mode. /RTxCB. Receive/Transmit Clock (input, active Low). The functions of this pin are under channel B program control. In channel B, /RTxCB may supply the receive clock, the transmit clock, the clock for the baud rate generator, or the clock for the DPLL. This pin can also be programmed for use by the /SYNCB pin as a crystal oscillator. The receive clock may be 1, 16, 32, or 64 times the data rate in asynchronous mode. In Z80182/Z8L182 mode 1 the /RTxCB signal is multiplexed with 16550 MIMIC interface HA2 input on the /RTxCB/HA2 pin. PS009801-0301 3-7 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL Z85230 ESCC SIGNALS (Continued) /SYNCA, /SYNCB. Synchronization (inputs/outputs, active Low). These pins can act as either inputs, outputs, or as part of the crystal oscillator circuit. In the Asynchronous Receive mode (crystal oscillator option not selected), these pins are inputs similar to /CTS and /DCD. In this mode, transitions on these lines affect the state of the Sync /Hunt status bits in Read Register 0, but have no other function. /SYNCA is also multiplexed with PC4 (parallel Port C, bit 4) on the /SYNCA/PC4 pin. In External Synchronization mode with the crystal oscillator not selected, these lines also act as inputs. In this mode /SYNC must be driven Low two receive clock cycles after the last bit in the sync character is received. Character assembly begins on the rising edge of the receive clock immediately preceding the activation of /SYNC. In the Internal Synchronization mode, (Monosync and Bisync) with the crystal oscillator not selected, these pins act as outputs and are active only during the part of the receive clock cycle in which sync characters are recognized. The sync condition is not latched, so these outputs are active each time a sync character is recognized (regardless of the character boundaries). In SDLC mode, these pins act as outputs and are valid on receipt of a flag. In Z80182/Z8L182 mode 1 the /SYNCB signal is multiplexed with the 16550 MIMIC interface /HCS input on the /SYNCB //HCS pin. /CTSA. Clear To Send (input, active Low). If this pin is programmed as auto enable, a Low on this input enables the channel A transmitter. If not programmed as auto enable, it may be used as a general-purpose input. The input is Schmitt-trigger buffered to accommodate slow rise-time input. The ESCC™ detects transitions on this input and can interrupt the Z180™ MPU on either logic level transitions. /CTSA is multiplexed with PC1 (parallel Port C, bit 1) on the /CTSA/PC1 pin. /CTSB. Clear To Send (input, active Low). This pin is similar to /CTSA’s functionality but is applicable to the channel B transmitter. In Z80182/Z8L182 mode, the /CTSB signal is multiplexed with the 16550 MIMIC interface /HWR input on the /CTSB //HWR pin. /DCDA. Data Carrier Detect (input, active Low). This pin functions as receiver enables if it is programmed as an auto enable bit; otherwise, it may be used as a generalpurpose input pin. The pin is Schmitt-trigger buffered to accommodate slow rise-time signals. The ESCC detects transitions on this pin and can interrupt the Z180 MPU on either logic level transitions. /DCDA is also multiplexed with PC0 (parallel Port C, bit 0) on the /DCDA/PC0 pin. 3-8 /DCDB. Data Carrier Detect (input, active Low). This pin’s functionality is similar to /DCDA but applicable to the channel B receiver. In Z80182/Z8L182 mode 1, /DCDB is multiplexed with the 16550 MIMIC interface /HRD input on the /DCDB//HRD pin. /RTSA. Request to Send (output, active Low). When the Request to Send (RTS) bit in Write Register 5 channel A is set, the /RTSA signal goes Low. When the RTS bit is reset in the Asynchronous mode and auto enables is on, the signal goes High after the transmitter is empty. In Synchronous mode or in Asynchronous mode with auto enables off, the /RTSA pin strictly follows the state of the RTS bit. The pin can be used as general-purpose output. /RTSA is multiplexed with PC2 (parallel Port C bit 2). This /RTSA or PC2 combination is pin multiplexed with /MWR (active when both the internal /MREQ and /WR are active) on the /MWR/PC2//RTSA pin. The default function of this pin on power-up is /MWR which may be changed by programming bit 3 in the Interrupt Edge/Pin MUX Register (xxDFH). /RTSB. Request to Send (output, active Low). This pin is similar in functionality as /RTSA but is applicable on channel B. The /RTSB signal is multiplexed with the Z180 MPU /TEND1 signal and the 16550 MIMIC interface /HRxRDY signal on the /TEND1//RTSB//HRxRDY pin. /DTR//REQA. Data Terminal Ready (output, active Low). This pin functions as it is programmed into the DTR bit. It can also be used as general-purpose output (transmit) or as request lines for the DMA controller. The ESCC allows full duplex DMA transfers. /DTR//REQA is also multiplexed with PC3 (parallel Port C, bit 3) on the /DTR//REQA /PC3 pin. /DTR//REQB. Data Terminal Ready (output, active Low). This pin functions as it is programmed into the DTR bit. It can also be used as general-purpose output (transmit) or as request lines for the DMA controller. The ESCC allows full duplex DMA transfers. The /DTR//REQB signal is multiplexed with the Z180 MPU TxS signal and the 16550 MIMIC interface HINTR signal on the /TxS//DTR//REQB //HINTR pin. /W//REQA. Wait/Request (output, open drain when programmed for the Wait function, driven High or Low when programmed for a Request function). This dualpurpose output can be programmed as Request (receive) lines for a DMA controller or as Wait lines to synchronize the Z180 MPU to the ESCC data rate. The reset state is Wait. The ESCC allows full duplex DMA transfers. /W//REQA is also multiplexed with PC5 (parallel Port C, bit 5) on the /W//REQA/PC5 pin. PS009801-0301 DS971820600 Zilog P R E L I M I N A R Y /W//REQB. Wait/Request (output, open drain when programmed for the Wait function, driven High or Low when programmed for a Request function). This pin is similar in functionality to /W//REQA but is applicable on Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL channel B. The /W//REQB signal is multiplexed with the Z180 MPU CKS signal and the 16550 MIMIC interface /HTxRDY signal on the CKS//W//REQB//HTxRDY pin. 16550 MIMIC INTERFACE SIGNALS HD7-HD0. Host Data Bus (input/output, tri-state). In Z80182/ Z8L182 mode 1, the host data bus is used to communicate between the 16550 MIMIC interface and the PC/XT/AT. It is multiplexed with the PA7-PA0 of parallel Port A when the Z80182/Z8L182 is in mode 0. /HRD. Host Read (input, active Low). In Z80182/Z8L182 mode 1, this input is used by the PC/XT/AT to signal the 16550 MIMIC interface that a read operation is taking place. In Z80182/Z8L182 mode 0, this pin is multiplexed with the ESCC /DCDB signal on the /DCDB//HRD pin. /HDDIS. Host Driver Disable (output, active Low). In Z80182/ Z8L182 mode 1, this signal goes Low whenever the PC/XT/AT is reading data from the 16550 MIMIC interface. In Z80182/Z8L182 mode 0, this pin is multiplexed with the ESCC ™ TxDB signal on the TxDB//HDDIS pin. HINTR. Host Interrupt (output, active High). In Z80182/ Z8L182 mode 1, this output is used by the 16550 MIMIC interface to signal the PC/XT/AT that an interrupt is pending. In Z80182/Z8L182 mode 0, this pin is multiplexed with the ESCC (/DTR//REQB) signal and the Z180 MPU TxS signal on the TxS//DTR//REQB//HINTR pin. HA2-HA0. Host Address (input). In Z80182/Z8L182 mode 1, these pins are the address inputs to the 16550 MIMIC interface. This address determines which register the PC/XT/AT accesses. HA0 is multiplexed with /TRxCB on the /TRxCB/HA0 pin; HA1 is multiplexed with RxDB on the RxDB/HA1 pin; HA2 is multiplexed with /RTxCB on the /RTxCB/HA2 pin. /HCS. Host Chip Select (input, active Low). In Z80182/ Z8L182 mode 1, this input is used by the PC/XT/AT to select the 16550 MIMIC interface for an access. In Z80182/ Z8L182 mode 0, it is multiplexed with the ESCC /SYNCB signal on the SYNCB//HCS pin. /HWR. Host Write (Input, active Low). In Z80182/Z8L182 mode 1, this input is used by the PC/XT/AT to signal the 16550 MIMIC interface that a write operation is taking place. In Z80182/Z8L182 mode 0, this input is multiplexed with the ESCC /CTSB signal on the /CTSB//HWR pin. /HTxRDY. Host Transmit Ready (output, active Low). In Z80182/Z8L182 mode 1, this output is used by the 16550 MIMIC in DMA mode to signal the PC/XT/AT that the Transmit Holding Register is empty. In Z80182/Z8L182 mode 0, this pin is multiplexed with the ESCC (/W//REQB) signal and the Z180 MPU CKS signal on the CKS//W// REQB//HTxRDY pin. /HRxRDY. Host Receive Ready (output, active Low). In Z80182/Z8L182 mode 1, this output is used by the 16550 MIMIC interface in DMA mode to signal the PC/XT/AT that a data byte is ready in the Receive Buffer. In Z80182/ Z8L182 mode 0, this pin is multiplexed with the ESCC /RTSB signal and the Z180 MPU /TEND1 signal on the /TEND1/RTSB /HRxRDY pin. PARALLEL PORTS PA7-PA0. Parallel Port A (input/output). These lines can be configured as inputs or outputs on a bit-by-bit basis when the Z80182/Z8L182 is operated in mode 0. These pins are multiplexed with the HD7-HD0 when the Z80182/Z8L182 is in mode 1. PB7-PB0. Parallel Port B (input/output). These lines can be configured as inputs or outputs on a bit-by-bit basis when the Port function is selected in the System Configuration register. The pins are multiplexed with the following Z180 peripheral functions: /RTS0, /CTS0, /DCD0, TxA0, RxA0, TxA1, RxA1, (RxS//CTS1). DS971820600 PC7-PC0. Parallel Port C (input/output). These lines can be configured as inputs or outputs on a bit-by-bit basis for bits PC5-PC0. Bits PC7 and PC6 are input only and read the level of the external /INT2 and /INT1 pins. When /INT2 and/or /INT1 are in edge capture mode, writing a 1 to the respective PC7, PC6 bit clears the interrupt capture latch; writing a 0 has no effect. Bits PC5-PC0 are multiplexed with the following pins from ESCC channel A: (/W//REQA), /SYNCA, (/DTR//REQA), /RTSA, /MWR, /CTSA, /DCDA. The Port function is selected through a bit in the System Configuration Register. PS009801-0301 3-9 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL EMULATION SIGNALS EV1, EV2. Emulation Select (input). These two pins determine the emulation mode of the Z180 MPU (Table 1). Table 1. Evaluation Modes Mode EV2 EV1 0 1 2 3 0 0 1 1 0 1 0 1 Description Normal mode, on-chip Z180 bus master Emulation Adapter Mode Emulator Probe Mode Reserved for Test SYSTEM CONTROL SIGNALS ST. Status (output, active High). This signal is used with the /M1 and /HALT output to decode the status of the CPU machine cycle. If unused, this pin should be pulled to VDD. /RAMCS. RAM Chip Select (output, active Low). Signal used to access RAM based upon the Address and the RAMLBR and RAMUBR registers and /MREQ. /RESET. Reset Signal (input, active Low). /RESET signal is used for initializing the MPU and other devices in the system. It must be kept in the active state for a period of at least three system clock cycles. /ROMCS. ROM Chip Select (output, active Low). Signal used to access ROM based upon the address and the ROMBR register and /MREQ. IEI. Interrupt Enable Signal (input, active High). IEI is used with the IEO to form a priority daisy chain when there is more than one interrupt-driven peripheral. IEO. Interrupt Enable Output Signal (output, active High). In the daisy-chain interrupt control, IEO controls the interrupt of external peripherals. IEO is active when IEI is 1 and the CPU is not servicing an interrupt from the on-chip peripherals. This pin is multiplexed with /IOCS on the /IOCS/IEO pin. The /IOCS function is the default on Power On or Reset conditions and is changed by programming bit 2 in the Interrupt Edge/Pin MUX Register. /IOCS. Auxiliary Chip Select Output Signal (output, active Low). This pin is multiplexed with /IEO on the /IOCS/IEO pin. /IOCS is an auxiliary chip select that decodes A7, A6, /IORQ, /M1 and effectively decodes the address space xx80H to xxBFH for I/O transactions. A15 through A8 are not decoded so that the chip select is active in all pages of I/O address space. The /IOCS function is the default on the /IOCS/IEO pin after Power On or Reset conditions and is changed by programming bit 2 in the Interrupt Edge/Pin MUX Register. 3-10 E. Enable Clock (output, active High). Synchronous machine cycle clock output during bus transactions. XTAL. Crystal (input, active High). Crystal oscillator connection. This pin should be left open if an external clock is used instead of a crystal. The oscillator input is not a TTL level (reference DC characteristics). EXTAL. External Clock/Crystal (input, active High). Crystal oscillator connections to an external clock can be input to the Z80180 on this pin when a crystal is not used. This input is Schmitt triggered. PHI. System Clock (output, active High). The output is used as a reference clock for the MPU and the external system. The frequency of this output is reflective of the functional speed of the processor. In clock divide-by-two mode, the pHI frequency is half that of the crystal or input clock. If divide-by-one mode is enabled, the PHI frequency is equivalent to that of crystal or input frequency. The PHI frequency is also fed to the ESCC core. If running over 20 MHz (5V) or 10 MHz (3V) the PHI-ESCC frequency divider should be enabled to divide the PHI clock by two prior to feeding into the ESCC core. PS009801-0301 DS971820600 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL MULTIPLEXED PIN DESCRIPTIONS A18/TOUT. During Reset, this pin is initialized as an A18 pin. If either TOC1 or TOC0 bit of the Timer Control Register (TCR) is set to 1, The T OUT function is selected. If TOC1 and TOC0 bits are cleared to 0, the A18 function is selected. In normal user mode (on-chip bus master), the A18 signal for the chip select logic is obtained from the CPU before the external pin is muxed as A18/T OUT. Therefore, the selection of TOUT will not affect the operation of the 182 chip select logic. However, in adapter mode (off-chip bus master), the A18 signal MUST be provided by the external bus master. CKA0//DREQ0. During Reset, this pin is initialized as CKA0 pin. If either DM1 or SM1 in the DMA Mode Register (DMODE) is set to 1, /DREQ0 function is always selected. CKA1//TEND0. During Reset, this pin is initialized as CKA1 pin. If CKA1D bit in the ASCI control register Ch1(CNTLA1) is set to 1, /TEND0 function is selected. If CKA1D bit is set to 0, CKA1 function is selected. RxS//CTS1. During Reset, this pin is initialized as the RxS pin. If CTS1E bit in the ASCI status register Ch1 (STAT1) is set to 1, /CTS1 function is selected. If CTS1E bit is set to 0, RxS function is selected. This pin is also multiplexed with PB7 based on bit 6 in the System Configuration Register. The pins below are triple-multiplexed based upon the values of bit 1 and bit 2 of the System Configuration Register. The pins are configured as Table 2 specifies. On Reset, both bits 1 and 2 are 0, so /TEND1,TxS,CKS are selected. DS971820600 Table 2. Triple Multiplexed Pins Bit 1 Bit 2 0 0 1 1 0 1 0 1 Master Configuration Register /TEND1,TxS,CKS /RTSB,/DTR//REQB,/W//REQB /TEND1,TxS,CKS /HRxRDY,//HTxRDY,HINTR The pins below are multiplexed based upon the value of bit 1 of the System Configuration register. If bit 1 is 0, then the Z80182/Z8L182 Mode 0 (non-16550 MIMIC mode) signals are selected; if bit 1 is 1, then Z80182/Z8L182 Mode 1 (16550 MIMIC mode) signals are selected. On Reset, Z80182/Z8L182 Mode 0 is always selected as shown in Table 3. Table 3. Mode 0 and Mode 1 Multiplexed Pins Z80182/Z8L182 Mode 0 TxDB RxDB /TRxCB /RTxCB /SYNCB /CTSB /DCDB PA7-PA0 PS009801-0301 Z80182/Z8L182 Mode 1 /HDDIS HA1 HA0 HA2 /HCS /HWR /HRD HD7-HD0 3-11 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL Ports B and C Multiplexed Pin Descriptions Ports B and C are pin multiplexed with the Z180 ASCI functions and part of ESCC channel A. The MUX function is controlled by bits 7-5 in the System Configuration Register. The MUX is organized as shown in Table 4. Note 1: When the Port function (PB1) is selected, the internal Z180/ CTS0 is always driven Low. This ensures that the ASCI channel 0 of the Z180™ MPU is enabled to transmit data. Table 4. Multiplexed Port Pins Note 2: Interrupt Edge /Pin MUX register, bit 3 chooses between the /MWR or PC2//RTSA combination; the System Configuration Register bit 7 chooses between PC2 and /RTSA. Port Mode Function ASCI/ESCC Mode Function PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 RxS,/CTS1 RxA1 TxA1 RxA0 TxA0 /DCD0 /CTS0 (Note 1) /RTS0 Always Reads /INT2 Ext. Status Always Reads /INT1 Ext. Status /W//REQA /SYNCA /DTR//REQA /RTSA (Note 2) /CTSA /DCDA Select with bit 6=1 System Config Reg. Select with bit 5=1 System Config Reg. PC6 PC5 PC4 PC3 Select with bit 7=1 PC2 System Config Reg. PC1 PC0 3-12 Refer to Table 5 for the 1st, 2nd and 3rd pin functions. PS009801-0301 DS971820600 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL Table 5. Primary, Secondary and Tertiary Pin Functions Pin Number VQFP QFP 1st Function 1 2 3 4 5 4 5 6 7 8 ST A0 A1 A2 A3 6 7 8 9 10 9 10 11 12 13 A4 A5 A6 A7 A8 11 12 13 14 15 14 15 16 17 18 A9 A10 A11 A12 V SS 16 17 18 19 20 19 20 21 22 23 A13 A14 A15 A16 A17 21 22 23 24 25 24 25 26 27 28 A18/T OUT V DD A19 D0 D1 26 27 28 29 30 29 30 31 32 33 D2 D3 D4 D5 D6 31 32 33 34 35 34 35 36 37 38 D7 /RTS0 /CTS0 /DCD0 TxA0 36 37 38 39 40 39 40 41 42 43 RxA0 TxA1 RxA1 RxS//CTS1 CKA0//DREQ0 DS971820600 2nd Function 3rd Function MUX Control PB0 PB1 PB2 PB3 SYS CONF REG Bit 5 SYS CONF REG Bit 5 SYS CONF REG Bit 5 SYS CONF REG Bit 5 PB4 PB5 PB6 PB7 SYS CONF REG Bit 5 SYS CONF REG Bit 6 SYS CONF REG Bit 6 SYS CONF REG Bit 6 PS009801-0301 3-13 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y MULTIPLEXED PIN DESCRIPTIONS (Continued) Table 5. Primary, Secondary and Tertiary Pin Functions (Continued) Pin Number VQFP QFP 1st Function 41 42 43 44 45 44 45 46 47 48 VSS CKA1//TEND0 TxS CKS /DREQ1 46 47 48 49 50 49 50 51 52 53 VDD /TEND1 /RAMCS /ROMCS EV1 51 52 53 54 55 54 55 56 57 58 EV2 PA0 PA1 PA2 PA3 HD0 HD1 HD2 HD3 SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1 56 57 58 59 60 59 60 61 62 63 PA4 PA5 PA6 PA7 /W//REQA HD4 HD5 HD6 HD7 PC5 SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 7 61 62 63 64 65 64 65 66 67 68 /DTR//REQA /MWR /CTSA /DCDA /SYNCA PC3 PC2 PC1 PC0 PC4 66 67 68 69 70 69 70 71 72 73 /RTxCA VSS /IOCS IEI VDD IEO 3-14 2nd Function 3rd Function MUX Control /DTR//REQB /W//REQB HINTR /HTxRDY SYS CONF REG Bit 1,2 SYS CONF REG Bit 1,2 /RTSB /HRxRDY SYS CONF REG Bit 1,2 RTSA PS009801-0301 SYS CONF REG Bit 7 SYS CONF REG Bit 7 * SYS CONF REG Bit 7 SYS CONF REG Bit 7 SYS CONF REG Bit 7 INT EDG/PIN REG Bit 2 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y Table 5. Primary, Secondary and Tertiary Pin Functions (Continued) Pin Number VQFP QFP 1st Function 2nd Function 3rd Function MUX Control 71 72 73 74 75 74 75 76 77 78 RxDA /TRxCA TxDA /DCDB /CTSB /HRD /HWR SYS CONF REG Bit 1 SYS CONF REG Bit 1 76 77 78 79 80 79 80 81 82 83 TxDB /TRxCB RxDB /RTxCB /SYNCB /HDDIS HA0 HA1 HA2 /HCS SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1 81 82 83 84 85 84 85 86 87 88 /HALT /RFSH /IORQ /MRD E /MREQ INT EDG/PIN REG Bit 3 86 87 88 89 90 89 90 91 92 93 /M1 /WR /RD PHI V SS 91 92 93 94 95 94 95 96 97 98 XTAL EXTAL /WAIT /BUSACK /BUSREQ 96 97 98 99 100 99 100 1 2 3 /RESET /NMI /INT0 /INT1 /INT2 PC6** PC7** Notes: * Also controlled by Interrupt Edge/Pin MUX Register ** PC7 and PC6 are inputs only and can read values of /INT1 and /INT2. DS971820600 PS009801-0301 3-15 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y Z80182/Z8L182 FUNCTIONAL DESCRIPTION Functionally, the on-chip Z182 MPU and ESCC™ are the same as the discrete devices (Figure 1). Therefore, for a detailed description of each individual unit, refer to the Product Specification/Technical Manuals of each discrete product. The following subsections describe each of the individual units of the Z182. Z182 MPU FUNCTIONAL DESCRIPTION RxS//CTS CKS /INT2 /INT1 /INT0 /NMI ST /RFSH /BUSACK /BUSREQ /WAIT /HALT /MREQ /M1 /WR /RD E Interrupt CPU 16-Bit Programmable Reload Timers (2) DMACs (2) /DREQ1 /TEND TxA0 Clocked Serial I/O Port CKA0 /DREQ0 Data Bus (8-Bit) TxS Bus State Control Timing & Clock Generator Address Bus (16-Bit) A18 /TOUT /RESET EXTAL XTAL Ø /IORQ software compatibility with existing Z180™ (and Z80®) software. The following is an overview of the major functional units of the Z182. This unit provides all the capabilities and pins of the Zilog Z8S180 MPU (Static Z80180 MPU). Figure 4 shows the S180 MPU Block Diagram of the Z182. This allows 100% Asynchronous SCI (Channel 0) RxA0 /RTS0 /CTS0 /DCD0 TxA1 Asynchronous SCI (Channel 1) MMU A19-A0 CKA1 /TEND0 RxA1 D7-D0 Figure 4. S180 MPU Block Diagram of Z182 3-16 PS009801-0301 DS971820600 Zilog P R E L I M I N A R Y Z182 CPU The Z182 CPU is 100% software compatible with the Z80® CPU and has the following additional features: Faster Execution Speed. The Z182 CPU is “fine tuned,” making execution speed, on average, 10% to 20% faster than the Z80 CPU. Enhanced DRAM Refresh Circuit. Z182 CPU’s DRAM refresh circuit does periodic refresh and generates an 8-bit refresh address. It can be disabled or the refresh period adjusted, through software control. Enhanced Instruction Set. The Z182 CPU has seven additional instructions to those of the Z80 CPU, which include the MLT (Multiply) instruction. HALT and Low Power Modes of Operation. The Z182 CPU has HALT and Low Power modes of operation, which are ideal for the applications requiring low power consumption like battery operated portable terminals. System Stop Mode. When the Z182 is in System Stop mode, it is only the Z180 MPU that is in STOP mode. Standby and Idle Mode. Please refer to the Z8S180 Product Specification for additional information on these two additional Low Power modes. Instruction Set. The instruction set of the Z182 CPU is identical to the Z180. For more details about each transaction, please refer to the Product Specification/ Technical Manual for the Z180/Z80 CPU. Z182 CPU Basic Operation Z182 CPU’s basic operation consists of the following events. These are identical to the Z180 MPU. For more details about each operation, please refer to the Product Specification/Technical Manual for the Z180. ■ Operation Code Fetch Cycle ■ Memory Read/Write Operation ■ Input/Output Operation ■ Bus Request/Acknowledge Operation ■ Maskable Interrupt Request Operation ■ Trap and Non-Maskable Interrupt Request Operation ■ HALT and Low Power Modes of Operation ■ Reset Operation DS971820600 Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL Memory Management Unit (MMU) The Memory Management Unit (MMU) allows the user to map the memory used by the CPU (64 Kbytes of logical addressing space) into 1 Mbyte of physical addressing space. The organization of the MMU allows object code compatibility with the Z80 CPU while offering access to an extended memory space. This is accomplished by using an effective common area-banked area scheme. DMA Controller The Z182 MPU has two DMA controllers. Each DMA controller provides high-speed data transfers between memory and I/O devices. Transfer operations supported are memory-to-memory, memory-to/from-I/O, and I/O-toI/O. Transfer modes supported are request, burst, and cycle steal. The DMA can access the full 1 Mbytes addressing range with a block length up to 64 Kbytes and can cross over 64K boundaries. Asynchronous Serial Communication Interface (ASCI) This unit provides two individual full-duplex UARTs. Each channel includes a programmable baud rate generator and modem control signals. The ASCI channels also support a multiprocessor communication format. Programmable Reload Timer (PRT) The Z182 MPU has two separate Programmable Reload Timers, each containing a 16-bit counter (timer) and count reload register. The time base for the counters is system clock divided by 20. PRT channel 1 provides an optional output to allow for waveform generation. Clocked Serial I/O (CSI/O) The CSI/O channel provides a half-duplex serial transmitter and receiver. This channel can be used for simple highspeed data connection to another CPU or MPU. Programmable Wait State Generator To ease interfacing with slow memory and I/O devices, the Z182 MPU unit has a programmable wait state generator. By programming the DMA/WAIT Control Register (DCNTL), up to three wait states are automatically inserted in memory and I/O cycles. This unit also inserts wait states during onchip DMA transactions. When using RAMCS and ROMCS wait state generators, the wait state controller with the most programmed wait states will determine the number of wait states inserted. PS009801-0301 3-17 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL Z85230 ESCC™ FUNCTIONAL DESCRIPTION The Zilog Enhanced Serial Communication Controller ESCC™ is a dual channel, multiprotocol data communication peripheral. The ESCC functions as a serial-to-parallel, parallel-to-serial converter/controller. The ESCC can be software-configured to satisfy a wide variety of serial communications applications. The device contains a variety of new, sophisticated internal functions including on-chip baud rate generators, digital phase-lock loops, and crystal oscillators, which dramatically reduce the need for external logic. The ESCC (Enhanced SCC) is pin and software compatible to the CMOS SCC version. The following enhancements were made to the CMOS SCC: ■ Deeper Transmit FIFO (4 bytes) ■ Deeper Receive FIFO (8 bytes) ■ Programmable FIFO interrupt and DMA request level ■ Seven enhancements to improve SDLC link layer supports: - Automatic transmission of the opening flag - Automatic reset of Tx Underrun/EOM latch - Deactivation of /RTS pin after closing flag - Automatic CRC generator preset - Complete CRC reception - TxD pin automatically forced High with NRZI encoding when using mark idle - Status FIFO handles better frames with an ABORT - Receive FIFO automatically unlocked for special receive interrupts when using the SDLC status FIFO ■ Delayed bus latching for easier microprocessor interface ■ New programmable features added with Write Register 7' (WR seven prime) ■ Write registers, 3, 4, 5 and 10 are now readable ■ Read register 0 latched during access ■ DPLL counter output available as jitter-free transmitter clock source ■ Enhanced /DTR, /RTS deactivation timing The ESCC handles asynchronous formats, synchronous byte-oriented protocols such as IBM ® Bisync, and synchronous bit-oriented protocols such as HDLC and IBM SDLC. This versatile device supports virtually any serial data transfer application (telecommunication, LAN, etc.) The device can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The ESCC also has facilities for modem control in both channels in applications where these controls are not needed, the modem controls can be used for general-purpose I/O. With access to 14 Write registers and 7 Read registers per channel (number of the registers varies depending on the version), the user can configure the ESCC to handle all synchronous formats regardless of data size, number of stop bits, or parity requirements. The ESCC also accommodates all synchronous formats including character, byte, and bit-oriented protocols. Within each operating mode, the ESCC also allows for protocol variations by checking odd or even parity bits, character insertion or deletion, CRC generation, checking break and abort generation and detection, and many other protocol-dependent features. 3-18 PS009801-0301 DS971820600 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL The following features are common to both the ESCC and the CMOS SCC: ■ NRZ, NRZI or FM encoding/decoding. Manchester Code Decoding (Encoding with External Logic). ■ Two independent full-duplex channels ■ Baud Rate Generator in each Channel ■ Synchronous/Isochronous data rates: - Up to 1/4 of the PCLK using external clock source - Up to 5 Mbits/sec at 20 MHz PCLK (ESCC). ■ Digital Phase-Locked Loop (DPLL) for Clock Recovery ■ Crystal Oscillator Asynchronous capabilities - 5, 6, 7 or 8 bits/character (capable of handling 4 bits/character or less) - 1, 1.5, or 2 stop bits - Odd or even parity - Times 1, 16, 32 or 64 clock modes - Break generation and detection - Parity, overrun and framing error detection The following features are implemented in the ESCC™ for the Z80182/Z8L182 only: ■ ■ ■ Byte oriented synchronous capabilities: - Internal or external character synchronization - One or two sync characters (6 or 8 bits/sync character) in separate registers - Automatic Cyclic Redundancy Check (CRC) generation/detection SDLC/HDLC capabilities: - Abort sequence generation and checking - Automatic zero insertion and detection - Automatic flag insertion between messages - Address field recognition - I-field residue handling - CRC generation/detection - SDLC loop mode with EOP recognition/loop entry and exit DS971820600 ■ New 32-bit CRC-32 (Ethernet Polynomial) ■ ESCC Programmable Clock - programmed to be equal to system clock divided by one or two - programmed by Z80182 Enhancement Register Note: The ESCC ™ programmable clock must be programmed to divide-by-two mode when operating above the following conditions: – PHI > 20 MHz at 5.0V – PHI > 10 MHz at 3.0V PS009801-0301 3-19 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y Z85230 ESCC™ BLOCK DIAGRAM For a detailed description of the Z85230 ESCC, refer to the ESCC Technical Manual. The following figure is the block diagram of the discrete ESCC, which was integrated into the Z182. The /INT line is internally connected to "INTO of the Z182. Transmit Logic Transmit FIFO 4 Bytes Transmit MUX TxDA Data Encoding & CRC Generation Channel A Receive and Transmit Clock Multipexer Exploded View /TRxCA /RTxCA Digital Phase-Locked Loop Crystal Oscillator Amplifier Baud Rate Generator Modem/Control Logic /CTSA /DCDA /SYNCA /RTSA /DTRA//REQA Receive Logic Rec. Status* FIFO Rec. Data* FIFO SDLC Frame Status FIFO 10 x 19 Receive MUX RxDA CRC Checker, Data Decode & Sync Character Detection * 8 bytes each Databus Internal Control Logic Channel A Register Interrupt Control Logic Channel B Register Channel A CPU & DMA Bus Interface Control Interrupt Control /INT /INTACK IEI IEO Channel B Figure 5. ESCC Block Diagram 3-20 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y 16550 MIMIC INTERFACE FUNCTIONAL DESCRIPTION The Z80182/Z8L182 has a 16550 MIMIC interface that allows it to mimic the 16550 device. It has all the interface pins necessary to connect to the PC/XT/AT bus. It contains the complete register set of the part with the same interrupt structure. The data path allows parallel transfer of data to and from the register set by the internal Z80180 of the Z80182/Z8L182. There is no shift register associated with the mimic of the 16550 UART. This interface saves the application from doing a serial transfer before performing data compression or error correction on the data. Two eight-bit timers are also available to control the data transfer rate of the 16550 MIMIC interface. Their input is tied to the ESCC channel B divide clock, so a down count of 24 bits is possible. An additional two eight bit timers are available for programming the FIFO timeout feature (Four Character Time Emulation) for both Receive and Transmit FIFO’s. The 16550 MIMIC interface supports the PC/XT/AT interrupt structure as well as an additional mode that allows for a wired Logic AND interrupt structure. Control of the register set is maintained by six priority encoded interrupts to the Z80182/Z8L182. When the PC/ XT/AT writes to THR, MCR, LCR, DLL, DLM, FCR or reads the RBR, an interrupt to the Z80182/Z8L182 is generated. Each interrupt can be individually masked off or all interrupts can be disabled by writing a single bit. Both mode 0 and mode 2 interrupts are supported by the 16550 MIMIC interface. The 16550 MIMIC interface is also capable of high speed parallel DMA transfers by using two control lines and the transmit and receive registers of the 16550 MIMIC interface. All registers of the 16550 MIMIC interface are accessible in any page of I/O space since only the lowest eight address lines are decoded. See Figure 6 for a block diagram of the 16550 MIMIC interface. 16550 MIMIC Side or PC Side Interface PC Addr/Decode PC Databus MPU Side Interface Receive Timer 4 8 16550 MIMIC Register Set Transmit Timer Z80180 Address Control/ Config Register Z80180 IRQ Control 6 8 Databus Z80180 Databus 2 PC DMA CNTL PC IRQ 1 PC IRQ DMA Control 2 Z80180 DMA Control Figure 6. 16550 MIMIC Block Diagram DS971820600 PS009801-0301 3-21 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y 16550 MIMIC FIFO DESCRIPTION The receiver FIFO consists of a 16-word FIFO capable of storing eight data bits and three error bits for each character stored (Figure 7). Parity error, Framing error and Break detect bits are stored along with the data bits by copying their value from three shadow bits that are Write Only bits for the Z80180 MPU LSR address. The three shadow bits are cleared after they are copied to the FIFO memory. In FIFO mode, to write error bits into the receiver FIFO, the MPU must first write the Parity, Framing and Break detect status to the Line Status Register (shadow bits) and then write the character associated into the receiver buffer. The data and error bits will then move into the same address in MPU Write LSR Shadow B2-B4 MPU Databus (MPU Side Write) error 3 3 Internal Clock MPU CNTL Line the FIFO. The error bits become available to the PC side of the interface when that particular location becomes the next address to read (top of FIFO). At that time, they may either be read by the PC by accessing them in the LSR, or they may cause an interrupt to the PC interface if so enabled. The error bits are set by the error status of the byte at the top of the FIFO, but may only be cleared by reading the LSR. If successive reads of the receiver FIFO are performed without reading the LSR, the status bits will be set if any of the bytes read have the respective error bit set. See Table 6 for the setting and clearing of the Line Status Register bits. Sync 8 W R I T E 16x8 Data Bits 16x3 Error Bits R E A D B U F F E R B U F F E R PC Read LSR B2-B4 Internal Clock PC Cntrl Line Sync 8 5 Internal Clock Write Pointer ALU Read Pointer PC Side Databus (PC Side Read) FIFO Control Register PC IRQ MPU IRQ 16550 MIMIC or PC Side Interface MPU Side Interface Figure 7. 16550 MIMIC Receiver FIFO Block Diagram 3-22 PS009801-0301 DS971820600 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL Table 6. 16550 Line Status Register Error Description How to Set How to Clear Error in RCVR FIFO At least one data byte available in FIFO with one error At least one error in receiver FIFO When there are no more errors *TEMT Transmitter empty MPU writes a 1 MPU writes a 0 † *THRE Transmitter holding register is empty When MPU has read or emptied the holding register When holding register is not empty Break Detect Break occurs when received data input is held in logic-0 for longer than a full word transmission MPU writes 1 There is a PC-side read of the LSR Framing Error Received character did not have a valid stop bit MPU writes 1 There is a PC-side read of the LSR Parity Error Received character did not have correct even or odd parity MPU writes 1 There is a PC-side read of the LSR Overrun Error Overlapping received characters, thereby destroying the previous character MPU makes two writes to receiver buffer register There is a PC-side read of the LSR †Data Ready Indicates complete incoming data has been received MPU writes to RCVR FIFO or receiver buffer register Empty Receiver or Receiver FIFO Notes: * The TEMT and THRE bits take on different functions when TEMT/Double Buffer mode is enabled. † These signals are delayed to HOST when using character emulation delay. DS971820600 PS009801-0301 3-23 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y 16550 MIMIC FIFO DESCRIPTION (Continued) The PC interface may be interrupted when 1, 4, 8 or 14 bytes are available in the receiver FIFO by setting bits 6 and 7 in the FCR (FIFO Control Register, PC address 02H) to the appropriate value. If the FIFO is not empty, but below the above trigger value, a timeout interrupt is available if the receiver FIFO is not written by the MPU or read by the PC from an interval determined by the Character Timeout Timer. This is an additional Timer with MPU access only that is used to emulate the 16550 4 character timeout delay. The Receive FIFO timeout timers are designed to reload and begin countdown after every read or write of the Rx FIFO, regardless of the Rx trigger level or number of bytes in the FIFO. Therefore, it is possible to get Timeout interrupts more often than Receive data interrupts. In order to closely emulate a 16550, a receive timeout timer enhancement is provided. When enabling this feature, the timeout timer will not begin counting down until the character emulation timer for each byte of data in the Rx FIFO has expired. Note: Enabling this feature will facilitate increased 16550 compatibility but may impede throughput. If the Receive Timeout interrupt occurs, the PC HOST will only be allowed to read up to 4-5 consecutive characters before the Data Ready bit is forced to zero (even if there is still more data in FIFO). This is required to maintain character pacing. The timer receives the ESCC /TRxCB as its input clock. Software must determine the correct values to program into the Receiver Timeout register and the ESCC TRxCB to achieve the correct delay interval for timeout. These interrupts are cleared by the FIFO reaching the trigger point or by resetting the Timeout Interval Timer by FIFO MPU write or PC read access. With FIFO mode enabled, the MPU is interrupted when the receiver FIFO is empty, corresponding to bit 5 being set in the IUS/IP register (MPU access only). This bit corresponds to a PC read of the receive buffer in non-FIFO (16450) mode. The interrupt source is cleared when the FIFO becomes non-empty or the MPU reads the IUS/IP register. The transmitter FIFO is 16-byte FIFO with PC write and MPU read access (Figure 8). In FIFO mode, the PC receives an interrupt when the transmitter becomes empty corresponding to bit 5 being set in the LSR. This bit and the interrupt source are cleared when the transmit FIFO becomes non-empty or the Interrupt Identification Register (IIR) register is read by the PC. Internal Clock MPU CNTL Line Sync 8 MPU Databus (MPU Side Read) 5 FIFO Control Register Internal Clock R E A D W R I T E 16x8 Data Bits B U F F E R B U F F E R Read Pointer ALU Sync PC Cntrl Line 8 Write Pointer PC Side Databus (PC Side Write) Internal Clock PC IRQ MPU IRQ 16550 MIMIC or PC Side Interface MPU Side Interface Figure 8. 16550 MIMIC Transmitter FIFO Block Diagram 3-24 PS009801-0301 DS971820600 Zilog P R E L I M I N A R Y On the MPU interface, the transmitted data available can be programmed to interrupt the MPU on 1, 4, 8 or 14 bytes of available data by seeing the appropriate value in the MPU FSCR control register (MPU write only xxECH) bits 6 and 7. A timeout feature exists, Transmit Timeout Timer, Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL which is an additional 8-bit timer with SCC TxRCB as the input source. If the transmitter FIFO is non-empty and no PC write or MPU read of the FIFO has taken place within the timer interval, a timeout occurs causing a corresponding interrupt to the MPU. Z80182/Z8L182 MIMIC SYNCHRONIZATION CONSIDERATIONS Because of the asynchronous nature of the FIFO’s on the MIMIC, some synchronization plan must be provided to prevent conflict from the dual port accesses of the MPU and the PC. To solve this problem, I/O to the FIFO is buffered and the buffers allow both PC and MPU to access the FIFO asynchronously. Read and Write requests are then synchronized by means of the MPU clock. Incoming signals are buffered in such a way that metastable input levels are stabilized to valid 1 or 0 levels. Actual transfers to and from the buffers, from and to the FIFO memory, are timed by the MPU clock. ALU evaluation is performed on a different phase than the transfer to ensure stable pointer values. DS971820600 Another potential problem is that of simultaneous access of the MPU and PC to any of the various ‘mailbox’ type registers. This is solved by dual buffering of the various read/write registers. During a read access by either the MPU or PC to a mailbox register, the data in the output or slave portion of the buffered register is not permitted to change. Any write that might take place during this time will be stored in the input of master part of the register. The corresponding status/interrupt is reset appropriately based on the write having followed the read to the register. For example, the IUS/IP bit for the LCR write will not be cleared by the MPU read of the LCR if a simultaneous write to the LCR by the PC takes place. Instead the LSR data will change after the read access and IUS/IP bit 3 remains at logic 1. PS009801-0301 3-25 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL Z80182 MIMIC DOUBLE BUFFERING FOR THE TRANSMITTER The Z80182 Rev DA implements double buffering for the transmitter in 16450 mode and sets the TEMT bit in the LSR Register automatically. When this feature is enabled and character delay emulation is being used (see Figure 9): 1. The PC THRE bit in the LSR Register is set when the THR Register is empty; 2. PC Host writes to the 16450 THR Register; 3. Whenever the Z80182 TSR buffer is empty and one character delay timer is in a timed-out state, the byte from the THR Register is transferred to the TSR buffer; the timer is in timed-out state after FIFO Reset or after Host TEMT is set. This allows a dual write to THR when Host TEMT is set. 4. Restart character delay timer (timer reloads and counts down) with byte transfer from THR Register to the TSR buffer; 6. MPU reads TSR buffer; 7. TEMT bit in LSR Register for MPU is set with no delay whenever the TSR buffer is empty; 8. When the TSR buffer is read by MPU and THR Register is empty and one character delay timer reaches zero, the TEMT bit in the LSR Register for Host is set from 0 to 1. The PC THRE bit in the LSR Register is reset whenever the THR Register is full and set whenever THR Register is empty. MPU IREQ and DMA Request for the transmit data is trigger whenever TSR buffer is full and cleared whenever TSR buffer is empty. If character delay emulation is not used the TEMT bit in the LSR Register is set whenever both the THR Register and the TSR buffer are both empty. The Host TEMT bit is clear if there is data in either the TSR buffer of THR Register. 5. Whenever the TSR buffer is full, the TEMT bit in MPU LSR Register is reset with no delay; Host Write Empty/Full Host & MPU THRE = 1 0 16450 THR Register THR to TSR delay transfer Empty/Full (MPU TEMT) TSRE = 1 0 TSR Transmit Shift Reg. Emulation Byte Transfer if: - THRE=0; - TSR = 1; - Character delay timer is timed out. Note: Timer reloads and counts down whenever data is transferred from THR to TSR. Added TSR Buffer for the transmit data Host TEMT = 1 if - THRE = 1 - TSRE = 1 - Emulation delay timer is timed out Note: MPU sees TSR bit in the LSR Register as TEMT bit Figure 9. TEMT Emulation Logic Implementation 3-26 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y PARALLEL PORTS FUNCTIONAL DESCRIPTION The Z80182/Z8L182 has three 8-bit bi-directional Ports. Each bit is individually programmable for input or output (with the exception of PC6 and PC7 which are inputs only). The Ports are controlled through two registers: the Port Direction Control Register and the Port Data Register. (Please see register description for Ports A, B and C). PROGRAMMING The following subsections explain and define the parameters for I/O Address assignments. The three tables in this section describe the mapping of the common registers shared by the MPU and the 16550 MIMIC. The MPU address refers to the I/O address as accessed from the MPU side (the Z180™ MPU interface side of the 16550 MIMIC). Note that only the lowest eight address lines are decoded for Z182 peripheral access. The full sixteen address lines are decoded for on-chip Z180 MPU access. The PC address (coined because the UART is common in PCs) is the address needed to access the MIMIC registers through the MIMIC interface signals. The MIMIC interface signals are multiplexed with the ESCC channel B and the Port A signals, and must be activated through the System Configuration Register and the Interrupt Edge/Pin MUX Register. Table 7. Z80182/Z8L182 MPU Registers Register Name MPU Addr PC Addr Z80182/Z8L182 MPU Control Registers 0000H to 00x3FH (Relocatable to 0040H to 007FH or 0080H to 00BFH) None Note: “x” indicates don’t care condition Table 8. Z80182/Z8L182 MIMIC Register MAP Register Name MPU Addr/Access PC Addr/Access MMC MIMIC Master Control Register IUS/IP Interrupt Pending IE Interrupt Enable IVEC Interrupt Vector TTCR Transmit Time Constant RTCR Receive Time Constant FSCR FIFO Status and Control RTTC Receive Timeout Time Constant TTTC Transmit Timeout Time Constant RBR Receive Buffer Register THR Transmit Holding Register IER Interrupt Enable Register IIR Interrupt Identification FCR FIFO Control Register MM REGISTER LCR Line Control Register MCR Modem Control Register LSR Line Status Register MSR Modem Status Register SCR Scratch Register DLL Divisor Latch (LSByte) DLM Divisor Latch (MSByte) xxFFH xxFEH xxFDH xxFCH xxFAH xxFBH xxECH xxEAH xxEBH xxF0H xxF0H xxF1H None xxE9H XXE9H xxF3H xxF4H xxF5H xxF6H xxF7H xxF8H xxF9H None None None None None None None None None 00H 00H 01H 02H 02H None 03H 04H 05H 06H 07H 00H 01H DS971820600 R/W R/Wb7 R/W R/W R/W R/W R/W7-4 R/W R/W W only R only R only R only W only R only R only R/Wb6432 R/Wb7-4 R only R only R only PS009801-0301 DLAB=0 R only DLAB=0 W only DLAB=0 R/W R only W only R/W R/W R only R only R/W DLAB=1 R/W DLAB=1 R/W 3-27 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL PROGRAMMING (Continued) Table 9. Z80182/Z8L182 ESCC, PIA and MISC Registers Register Name MPU Addr/Access WSG Chip Select Register Z80182 Enhancements Register PC Data Direction Register PC Data Register Interrupt Edge/Pin MUX Control ESCC Chan A Control Register ESCC Chan A Data Register ESCC Chan B Control Register ESCC Chan B Data Register PB Data Direction Register PB Data Register RAMUBR RAM Upper Boundary Register RAMLBR RAM Lower Boundary Register ROM Address Boundary Register PA Data Direction Register PA Data Register System Configuration Register 3-28 xxD8H xxD9H xxDDH xxDEH xxDFH xxE0H xxE1H xxE2H xxE3H xxE4H xxE5H xxE6H xxE7H xxE8H xxEDH xxEEH xxEFH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PS009801-0301 PC Addr/Access None None None None None None None None None None None None None None None None None DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y Z182 MPU CONTROL REGISTERS Figures 10 through 50 refer to the Z80182/Z8L182 MPU Control registers. For additional information, refer to the Z8S180 Product Specification and Technical Manual. ASCI CHANNELS CONTROL REGISTERS CNTLA0 Bit Upon RESET R/W Addr 00H MPBR/ /RTS0 EFR MOD2 MOD1 MOD0 MPE RE TE 0 0 0 1 x 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MODE Selection Start + 7-Bit Data + 1 Stop Start + 7-Bit Data + 2 Stop Start + 7-Bit Data + Parity + 1 Stop Start + 7-Bit Data + Parity + 2 Stop Start + 8-Bit Data + 1 Stop Start + 8-Bit Data + 2 Stop Start + 8-Bit Data + Parity + 1 Stop Start + 8-Bit Data + Parity + 2 Stop Read - Multiprocessor Bit Receive Write - Error Flag Reset Request To Send Transmit Enable Receive Enable Multiprocessor Enable Figure 10a. ASCI Control Register A (Ch. 0) DS971820600 PS009801-0301 3-29 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y ASCI CHANNELS CONTROL REGISTERS (Continued) Addr 01H CNTLA1 Bit Upon RESET R/W CKA1D MPBR/ MOD2 MOD1 MOD0 EFR MPE RE TE 0 0 0 1 x 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MODE Selection Start + 7-Bit Data + 1 Stop Start + 7-Bit Data + 2 Stop Start + 7-Bit Data + Parity + 1 Stop Start + 7-Bit Data + Parity + 2 Stop Start + 8-Bit Data + 1 Stop Start + 8-Bit Data + 2 Stop Start + 8-Bit Data + Parity + 1 Stop Start + 8-Bit Data + Parity + 2 Stop Read - Multiprocessor Bit Receive Write - Error Flag Reset CKA1 Disable Transmit Enable Receive Enable Multiprocessor Enable Figure 10b. ASCI Control Register A (Ch. 1) 3-30 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y Addr 02H CNTLB0 /CTS/ PS Bit MPBT Upon Reset Invalid 0 † 0 0 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W MP PE0 DR SS2 SS1 SS0 Clock Source and Speed Select Divide Ratio Parity Even or Odd Clear To Send/Prescale Multiprocessor Multiprocessor Bit Transmit † /CTS - Depending on the condition of /CTS pin. PS - Cleared to 0. General Divide Ratio SS, 2, 1, 0 000 001 010 011 100 101 110 111 PS = 0 (Divide Ratio = 10) DR = 0 (x16) PS = 1 (Divide Ratio = 30) DR = 1 (x64) Ø ÷ 160 Ø ÷ 640 Ø ÷ 320 Ø ÷ 1280 Ø ÷ 640 Ø ÷ 2580 Ø ÷ 1280 Ø ÷ 5120 Ø ÷ 2560 Ø ÷ 10240 Ø ÷ 5120 Ø ÷ 20480 Ø ÷ 10240 Ø ÷ 40960 External Clock (Frequency < Ø ÷ 40) DR = 0 (x16) DR = 1 (x64) Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ 480 960 1920 3840 7680 15360 30720 1920 3840 7680 15360 30720 61440 122880 Figure 11. ASCI Control Register B (Ch. 0) DS971820600 PS009801-0301 3-31 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y ASCI CHANNELS CONTROL REGISTERS (Continued) Addr 03H CNTLB1 /CTS/ PS Bit MPBT MP Upon Reset Invalid 0 0 0 0 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W PE0 DR SS2 SS1 SS0 Clock Source and Speed Select Divide Ratio Parity Even or Odd Read - Status of /CTS pin Write - Select PS Multiprocessor Multiprocessor Bit Transmit General Divide Ratio SS, 2, 1, 0 000 001 010 011 100 101 110 *111 PS = 0 (Divide Ratio = 10) DR = 0 (x16) DR = 1 (x64) Ø ÷ 160 Ø ÷ 640 Ø ÷ 320 Ø ÷ 1280 Ø ÷ 640 Ø ÷ 2580 Ø ÷ 1280 Ø ÷ 5120 Ø ÷ 2560 Ø ÷ 10240 Ø ÷ 5120 Ø ÷ 20480 Ø ÷ 10240 Ø ÷ 40960 External Clock (Frequency < Ø ÷ 40) PS = 1 (Divide Ratio = 30) DR = 0 (x16) DR = 1 (x64) Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ Ø÷ 480 960 1920 3840 7680 15360 30720 1920 3840 7680 15360 30720 61440 122880 Note: * Baud rate is external clock rate ÷ 16; therefore, Ø ÷ (40 x 16) is maximum baud rate using external clocking. Figure 12. ASCI Control Register B (Ch. 1) 3-32 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y Addr 04H STAT0 Bit RDRF OVRN PE FE RIE /DCD0 TDRE TIE Upon Reset 0 0 0 0 0 † †† 0 R/W R R R R R/W R R R/W Transmit Interrupt Enable Transmit Data Register Empty Data Carrier Detect Receive Interrupt Enable Framing Error Parity Error Over Run Error Receive Data Register Full † /DCD0 - Depending on the condition of /DCD0 Pin. †† /CTS0 Pin TDRE L H 1 0 Figure 13. ASCI Status Register Addr 05H STAT1 Bit RDRF OVRN PE FE RIE CTS1E TDRE TIE Upon Reset 0 0 0 0 0 0 1 0 R/W R R R R R/W R/W R R/W Transmit Interrupt Enable Transmit Data Register Empty /CTS1 Enable Receive Interrupt Enable Framing Error Parity Error Over Run Error Receive Data Register Full Figure 14. ASCI Status Register (Ch. 1) DS971820600 PS009801-0301 3-33 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y ASCI CHANNELS CONTROL REGISTERS (Continued) TDR0 Write Only 7 6 5 TSR1 Read Only Addr 06H 4 3 2 1 0 x x x Addr 09H x x x x x Transmit Data Figure 15. ASCI Transmit Data Register (Ch. 0) 6 5 Figure 18. ASCI Receive Data Register (Ch. 1) BRK0 Read/Write TDR1 Write Only 7 Received Data 4 3 Addr 07H 2 1 0 7 6 Addr 12H 5 4 3 2 1 0 Break generate bit 0 = no break 1 = break Transmit Data Break detect bit 0 = no break 1 = break Figure 16. ASCI Transmit Data Register (Ch. 1) Break feature bit 0 = dissolve 1 = enable TSR0 Read Only x x x Figure 19. ASCI Break Control Register (Ch. 0) Addr 08H x x x x x Received Data Figure 17. ASCI Receive Data Register (Ch. 0) BRK1 Read/Write 7 6 Addr 13H 5 4 3 2 1 0 Break generate bit 0 = no break 1 = break Break detect bit 0 = no break 1 = break Break feature enable bit 0 = disable 1 = enable Figure 20. ASCI Break Control Register (Ch. 1) 3-34 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y CSI/O REGISTERS CNTR Bit Upon Reset R/W EF 0 R Addr 0AH EIE 0 R/W RE 0 R/W TE 0 R/W SS2 1 R/W 1 SS1 1 R/W SS0 1 R/W Speed Select Transmit Enable Receive Enable End Interrupt Enable End Flag SS2, 1, 0 Baud Rate SS2, 1, 0 Baud Rate 000 001 010 011 Ø÷ Ø÷ Ø÷ Ø÷ 100 101 110 111 Ø ÷ 320 Ø ÷ 640 Ø ÷ 1280 External Clock (Frequency < Ø ÷ 20) 20 40 80 100 Figure 21. CSI/O Control Register TRDR Read/Write 7 6 5 Addr 0BH 4 3 2 1 0 Read - Received Data Write - Transmit Data Figure 22. CSI/O Transmit/Receive Data Register DS971820600 PS009801-0301 3-35 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y TIMER DATA REGISTERS TMDR0L Read/Write 7 6 5 4 3 TMDR0H Read/Write Addr 0CH 2 1 0 Addr 0DH 15 14 13 12 11 10 9 Figure 23. Timer 0 Data Register L 8 When Read, read Data Register L before reading Data Register H. Figure 25. Timer 0 Data Register H TMDR1L Read/Write 7 6 5 4 3 Addr 14H 2 1 0 TMDR1H Read/Write Figure 24. Timer 1 Data Register L Addr 15H 15 14 13 12 11 10 9 8 When Read, read Data Register L before reading Data Register H. Figure 26. Timer 1 Data Register H TIMER RELOAD REGISTERS RLDR0L Read/Write 7 6 5 4 3 Addr 0EH RLDR0H Read/Write 2 15 14 13 12 11 10 9 1 0 Figure 27. Timer 0 Reload Register L RLDR1L Read/Write 7 6 5 3 2 1 Figure 29. Timer 0 Reload Register H Addr 17H 15 14 13 12 11 10 9 8 0 Figure 28. Timer 1 Reload Register L 3-36 8 RLDR1H Read/Write Addr 16H 4 Addr 0FH Figure 30. Timer 1 Reload Register H PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y TIMER CONTROL REGISTER Addr 10H TCR Bit Upon Reset R/W TIF1 TIF0 TIE1 TIE0 TOC1 TOC0 TDE1 TDE0 0 0 0 0 0 0 0 0 R R R/W R/W R/W R/W R/W R/W Timer Down Count Enable 1,0 Timer Output Control 1,0 Timer Interrupt Enable 1,0 Timer Interrupt Flag 1,0 TOC1,0 A15/TOUT 00 Inhibited 01 Toggle 10 0 11 1 Figure 31. Timer Control Register DS971820600 PS009801-0301 3-37 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL FREE RUNNING COUNTER FRC Read Only 7 6 5 Addr 18H 4 3 2 1 0 Figure 32. Free Running Counter CPU CONTROL REGISTER CPU Control Register (CCR) Addr 1FH D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Figure 33. CPU Note: See Figure 49 for full description. DMA REGISTERS SAR0L Read/Write SA7 Addr 20H SA0 SAR0H Read/Write SA15 Addr 21H SA8 SAR0B Read/Write SA19 - - - Addr 22H SA16 - Bits 0-2 (3) are used for SAR0B A19, A18, A17, A16 x x x x x x x x 0 0 1 1 0 1 0 1 DMA Transfer Request /DREQ0 (external) RDR0 (ASCI0) RDR1 (ASCI1) Not Used Figure 34. DMA 0 Source Address Registers 3-38 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y DMA REGISTERS DAR0L Read/Write DA7 Addr 23H DA0 MAR1L Read/Write MA7 Addr 28H MA0 DAR0H Read/Write DA15 Addr 24H DA8 MAR1H Read/Write MA15 Addr 29H MA8 Addr 25H DA19 DA16 MAR1B Read/Write DAR0B Read/Write - - - MA19 - - - - Addr 2AH MA16 - Bits 0-2 (3) are used for DAR0B A19, A18, A17, A16 x x x x x x x x 0 0 1 1 0 1 0 1 DMA Transfer Request Figure 37. DMA 1 Memory Address Registers /DREQ0 (external) TDR0 (ASCI0) TDR1 (ASCI1) Not Used IAR1L Read/Write IA7 Addr 2BH IA0 IAR1H Read/Write IA15 Addr 2CH IA8 Figure 35. DMA 0 Destination Address Registers BCR0L Read/Write BC7 Addr 26H BC0 Figure 38. DMA I/O Address Registers BCR0H Read/Write BC15 Addr 27H BC8 BCR1L Read/Write BC7 Addr 2EH BC0 BCR1H Read/Write BC15 Addr 2FH BC8 Figure 36. DMA 0 Byte Counter Registers Figure 39. DMA 1 Byte Count Registers DS971820600 PS009801-0301 3-39 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL DMA REGISTERS (Continued) DSTAT Bit Upon Reset R/W DE1 0 R/W Addr 30H DE0 /DWE1 /DWE0 DIE1 0 1 1 0 R/W W W R/W DIE0 - DIME 0 R/W 1 0 R DMA Master Enable DMA Interrupt Enable 1, 0 DMA Enable Bit Write Enable 1, 0 DMA Enable Ch 1, 0 Figure 40. DMA Status Register DMODE Bit Upon Reset R/W Addr 31H - - 1 1 DM1 DM0 SM1 SM0 0 0 0 0 R/W R/W R/W R/W MMOD - 0 1 R/W Memory MODE Select Ch 0 Source Mode 1, 0 Ch 0 Destination Mode 1, 0 DM1, 0 00 01 10 11 MMOD 0 1 Destination M M M I/O Address DAR0+1 DAR0-1 DAR0 Fixed DAR0 Fixed SM1, 0 00 01 10 11 Source M M M I/O Address SAR0+1 SAR0-1 SAR0 Fixed SAR0 Fixed Mode Cycle Steal Mode Burst Mode Figure 41. DMA Mode Registers 3-40 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y DCNTL Bit Upon Reset R/W Addr 32H MWI1 MWI0 IWI1 IWI0 DMS1 DMS0 DIM1 DIM0 1 1 1 1 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W DMA Ch 1 I/O Memory Mode Select /DREQi Select, i = 1, 0 I/0 Wait Insertion Memory Wait Insertion * MWI1, 0 No. of Wait States IWI1, 0 No. of Wait States 00 01 10 11 0 1 2 3 00 01 10 11 1 2 3 4 DMSi Sense 1 0 Edge Sense Level Sense DM1, 0 Transfer Mode 00 01 10 11 M - I/O M - I/O I/O - M I/O - M Address Increment/Decrement MAR1+1 MAR1-1 IAR1 Fixed IAR1 Fixed IAR1 Fixed IAR1 Fixed MAR1+1 MAR1-1 Note: * If using ROM/RAM Chip Select wait state generators, the Z180 wait state generator should be set to 0. Figure 42. DMA/WAIT Control Register DS971820600 PS009801-0301 3-41 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y MMU REGISTERS CBR Bit CB7 CB6 CB5 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Upon Reset R/W Addr 38H CB4 CB3 CB2 CB1 CB0 MMU Common Base Register Figure 43. MMU Common Base Register BBR Bit Upon Reset R/W Addr 39H BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W MMU Bank Base Register Figure 44. MMU Bank Base Register CBAR Bit Upon Reset R/W Addr 3AH CA3 CA2 CA1 CA0 BA3 BA2 BA1 BA0 1 1 1 1 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W MMU Bank Area Register MMU Common Area Register Figure 45. MMU Common/Bank Area Register 3-42 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y SYSTEM CONTROL REGISTERS IL Bit Upon Reset R/W IL7 0 R/W IL6 0 R/W IL5 0 R/W 0 0 0 Addr 33H 0 0 Interrupt Vector Low Figure 46. Interrupt Vector Low Register Bit Upon Reset R/W Addr 34H ITC TRAP UFO 0 0 R/W R 1 - - ITE2 ITE1 ITE0 1 1 0 R/W 0 R/W 1 R/W /INT Enable 2, 1, 0 Undefined Fetch Object TRAP Figure 47. INT/TRAP Control Register Addr 36H RCR Bit Upon Reset R/W REFE REFW 1 1 R/W R/W 1 - - - 1 1 1 CYC1 CYC0 0 0 R/W R/W Cycle Select Refresh Wait State Refresh Enable CYC1, 0 Interval of Refresh Cycle 00 01 10 11 10 states 20 states 40 states 80 states Figure 48. Refresh Control Register DS971820600 PS009801-0301 3-43 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL SYSTEM CONTROL REGISTERS (Continued) OMCR Bit Upon Reset R/W M1E /M1TE /IOC - - - Addr 3EH - 1 R/W 1 1 1 1 1 W 1 R/W 1 I/O Compatibility /M1 Temporary Enable /M1 Enable Note: This register should be programmed to 0x0xxxxxb (x = don't care) as a part of Initialization. Figure 49. Operation Mode Control Register ICR Bit Upon Reset IOA7 IOA6 IOSTP 0 0 0 R/W R/W R/W R/W - - - Addr 3FH - 1 1 1 1 1 I/O Stop I/O Address Combination of 11 is reserved Figure 50. I/O Control Register 3-44 PS009801-0301 DS971820600 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL ADDITIONAL FEATURES ON THE Z182 MPU The following is a detailed description of the enhancements to the Z8S180 from the standard Z80180 in the areas of STANDBY, IDLE, and STANDBY-QUICK RECOVERY modes. Add-On Features There are five different power-down modes. SLEEP and SYSTEM STOP are inherited from the Z80180. In SLEEP mode, the CPU is in a stopped state while the on-chip I/Os are still operating. In I/O STOP mode, the on-chip I/Os are in a stopped state while leaving the CPU running. In SYSTEM STOP mode, both the CPU and the on-chip I/Os are in the stopped state to reduce the current consumption. The Z8S180 has added two additional power-down modes, STANDBY and IDLE, to reduce the current consumption even further. The differences among these power-down modes are summarized in Table 10. Table 10. Power Down Modes Power-Down Modes CPU Core On-Chip I/O OSC. CLKOUT Recovery Source Recovery Time (Minimum) SLEEP I/O STOP SYSTEM STOP IDLE † STANDBY † Stop Running Stop Stop Stop Running Stop Stop Stop Stop Running Running Running Running Stop Running Running Running Stop Stop RESET, Interrupts By Programming RESET, Interrupts RESET, Interrupts, BUSREQ RESET, Interrupts, BUSREQ 1.5 Clock 1.5 Clock 8 +1.5 Clock 217 +1.5 Clock (Normal Recovery) 26 +1.5 Clock (Quick Recovery) Notes: † IDLE and STANDBY modes are only offered in Z8S180. Note that the minimum recovery time can be achieved if INTERRUPT is used as the Recovery Source. STANDBY Mode The Z8S180 has been designed to save power. Two lowpower programmable power-down modes have been added; STANDBY mode and IDLE mode. The STANDBY/IDLE mode is selected by multiplexing D6 and D3 of the CPU Control Register (CCR, I/O Address = 1FH). To enter STANDBY mode: 18-bit counter has been added in the Z8S180 to allow for oscillator stabilization. When the part receives an external IRQ or BUSREQ during STANDBY mode, the oscillator is restarted and the timer counts down 217 counts before acknowledgment is sent to the interrupt source. 1. Set D6 and D3 to 1 and 0, respectively. The recovery source needs to remain asserted for duration of the 217 count, otherwise standby will be resumed. 2. Set the I/O STOP bit (D5 of ICR, I/O Address = 3FH) to 1. The following is a description of how the part exits STANDBY for different interrupts and modes of operation. 3. Execute the SLEEP instruction. STANDBY Mode Exit with /RESET When the part is in STANDBY mode, it behaves similar to the SYSTEM STOP mode which currently exists on the Z80180, except that the STANDBY mode stops the external oscillator, internal clocks and reduces power consumption to typically 50 µA.. Since the clock oscillator has been stopped, a restart of the oscillator requires a period of time for stabilization. An DS971820600 The /RESET input needs to be asserted for a duration long enough for the crystal oscillator to stabilize and then exit from the STANDBY mode. When /RESET is de-asserted, it goes through the normal reset timing to start instruction execution at address (logical and physical) 0000H. The clocking is resumed within the Z8S180 and at the system clock output after /RESET is asserted when the crystal oscillator is restarted, but not yet stabilized. PS009801-0301 3-45 Zilog P R E L I M I N A R Y STANDBY Mode Exit with BUS REQUEST Optionally, if the BREXT bit (D5 of CPU Control Register) is set to 1, the Z8S180 exits STANDBY mode when the /BUSREQ input is asserted; the crystal oscillator is then restarted. An internal counter automatically provides time for the oscillator to stabilize, before the internal clocking and the system clock output of the Z8S180 are resumed. The Z8S180 relinquishes the system bus after the clocking is resumed by: - Tri-State the address outputs A19 through A0. - Tri-State the bus control outputs /MREQ, /IORQ, /RD and /WR. - Asserting /BUSACK The Z8S180 regains the system bus when /BUSREQ is deactivated. The address outputs and the bus control outputs are then driven High; the STANDBY mode is exited. If the BREXT bit of the CPU Control Register (CCR) is cleared, asserting the /BUSREQ would not cause the Z8S180 to exit STANDBY mode. If STANDBY mode is exited due to a reset or an external interrupt, the Z8S180 remains relinquished from the system bus as long as /BUSREQ is active. STANDBY Mode Exit with External Interrupts STANDBY mode can be exited by asserting input /NMI. The STANDBY mode may also exit by asserting /INT0, /INT1 or /INT2, depending on the conditions specified in the following paragraphs. /INT0 wake-up requires assertion throughout duration of clock stabilization time (217 clocks). If exit conditions are met, the internal counter provides time for the crystal oscillator to stabilize, before the internal clocking and the system clock output within the Z8S180 are resumed. Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL If an External Maskable Interrupt input is asserted, the CPU responds according to the status of the Global Interrupt Enable Flag IEF1 (determined by the ITE1 bit) and the settings of the corresponding interrupt enable bit in the Interrupt/Trap Control Register (ITC: I/O Address = 34H): a. If an interrupt source is disabled in the ITC, asserting the corresponding interrupt input would not cause the Z8S180 to exit STANDBY mode. This is true regardless of the state of the Global Interrupt Enable Flag IEF1. b. If the Global Interrupt Flag IEF1 is set to 1, and if an interrupt source is enabled in the ITC, asserting the corresponding interrupt input causes the Z8S180 to exit STANDBY mode. The CPU performs an interrupt acknowledge sequence appropriate to the input being asserted when clocking is resumed if: - The interrupt input follows the normal interrupt daisy chain protocol. - The interrupt source is active until the acknowledge cycle is completed. c. If the Global Interrupt Flag IEF1 is disabled, i.e., reset to 0, and if an interrupt source is enabled in the ITC, asserting the corresponding interrupt input will still cause the Z8S180 to exit STANDBY mode. The CPU will proceed to fetch and execute instructions that follow the SLEEP instruction when clocking is resumed. If the External Maskable Interrupt input is not active until clocking resumes, the Z8S180 will not exit STANDBY mode. If the Non-Maskable Interrupt (/NMI) is not active until clocking resumes, the Z8S180 still exits the STANDBY mode even if the interrupt sources go away before the timer times out, because /NMI is edge-triggered. The condition is latched internally once /NMI is asserted Low. IDLE Mode IDLE mode is another power-down mode offered by the Z8S180. To enter IDLE mode: 1. Set D6 and D3 to 0 and 1, respectively. 2. Set the I/O STOP bit (D5 of ICR, I/O Address = 3FH) to 1. 1. Exit with Non-Maskable Interrupts If /NMI is asserted, the CPU begins a normal NMI interrupt acknowledge sequence after clocking resumes. 3. Execute the SLEEP instruction. 2. Exit with External Maskable Interrupts 3-46 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y When the part is in IDLE mode, the clock oscillator is kept oscillating, but the clock to the rest of the internal circuit, including the CLKOUT, is stopped completely. IDLE mode is exited in a similar way as STANDBY mode, i.e., RESET, BUS REQUEST or EXTERNAL INTERRUPTS, except that the 217 bit wake-up timer is bypassed; all control signals are asserted eight clock cycles after the exit conditions are gathered. When the part is in STANDBY-QUICK RECOVERY mode, the operation is identical to STANDBY mode except when exit conditions are gathered, i.e., RESET, BUS REQUEST or EXTERNAL INTERRUPTS; the clock and other control signals are recovered sooner than the STANDBY mode. Note: If STANDBY-QUICK RECOVERY is enabled, the user must make sure stable oscillation is obtained within 64 clock cycles. STANDBY-QUICK RECOVERY Mode STANDBY-QUICK RECOVERY mode is an option offered in STANDBY mode to reduce the clock recovery time in STANDBY mode from 217 clock cycles (6.5 ms at 20 MHz) to 26 clock cycles (3.2 µs at 20 MHz). This feature can only be used when providing an oscillator as clock source. To enter STANDBY-QUICK RECOVERY mode: 1. Set D6 and D3 to 1 and 1, respectively. 2. Set the I/O STOP bit (D5 of ICR, I/O Address = 3FH) to 1. CPU Control Register The Z8S180 has an additional register which allows the programmer to select options that directly affect the CPU performance as well as controlling the STANDBY operating mode of the chip. The CPU Control Register (CCR) allows the programmer to change the divide-by-two internal clock to divide-by-one. In addition, applications where EMI noise is a problem, the Z8S180 can reduce the output drivers on selected groups of pins to 25% of normal pad driver capability which minimizes the EMI noise generated by the part. 3. Execute the SLEEP instruction. CPU Control Register (CCR) Addr 1FH D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Clock Divide 0 = XTAL/2 1 = XTAL/1 LNAD/DATA 0 = Standard Drive 1 = 25% Drive On A19-A0, D7-D0 Standby/Idle Enable 00 = No Standby 01 = Idle After Sleep 10 = Standby After Sleep 11 = Standby After Sleep 64 Cycle Exit (Quick Recovery) LNCPUCTL 0 = Standard Drive 1 = 25% Drive On CPU Control Signals Reserved LNPHI 0 = Standard Drive 1 = 25% Drive On EXT.PHI Clock BREXT 0 = Ignore BUSREQ In Standby/Idle 1 = Standby/Idle Exit on BUSREQ Figure 51. CPU Control Register DS971820600 PS009801-0301 3-47 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL CPU Control Register Bit 7. Clock Divide Select. Bit 7 of the CCR allows the programmer to set the internal clock to divide the external clock by 2 if the bit is 0 and divide-by-one if the bit is 1. Upon reset, this bit is set to 0 and the part is in divide-by-two mode. Since the on-board oscillator is not guaranteed to operate above 20 MHz, an external source must be used to achieve the maximum 33 MHz operation of the part, i.e., an external clock at 66 MHz with 50% duty cycle. recovery is reduced to 64 clock cycles after the exit conditions are gathered. Similarly, in STANDBY mode, the Z8S180 enters STANDBY after fetching the second opcode of a SLEEP instruction, if the I/O STOP bit is set. If an external oscillator is used in divide-by-one mode, the minimum pulse width requirement must be satisfied. Bit 4. LNPHI. This bit controls the drive capability on the PHI Clock output. If this bit is set to 1, the PHI Clock output is reduced to 25% of its drive capability. Bits 6 and 3. STANDBY/IDLE Enable. These two bits are used for enabling/disabling the IDLE and STANDBY mode. Setting D6, D3 to 0 and 1, respectively, enables the IDLE mode. In the IDLE mode, the clock oscillator is kept oscillating but the clock to the rest of the internal circuit, including the CLKOUT, is stopped. The Z8S180 enters IDLE mode after fetching the second opcode of a SLEEP instruction, if the I/O STOP bit is set. Setting D6, D3 to 1 and 0, respectively, enables the STANDBY mode. In the STANDBY mode, the clock oscillator is stopped completely. The Z8S180 enters STANDBY after fetching the second opcode of a SLEEP instruction, if the I/O STOP bit is set. Setting D6, D3 to 1 and 1, respectively, enables the STANDBY-QUICK RECOVERY mode. In this mode, its operations are identical to STANDBY except that the clock 3-48 Bit 5. BREXT. This bit controls the ability of the Z8S180 to honor a bus request during STANDBY mode. If this bit is set to 1 and the part is in STANDBY mode, a BUSREQ is honored after the clock stabilization timer is timed out. Bit 2. Reserved Bit 1. LNCPUCTL. This bit controls the drive capability of the CPU Control pins. When this bit is set to 1, the output drive capability of the following pins is reduced to 25% of the original drive capability: - /BUSACK - /RD - /WR - /M1 -E - /MREQ - /IORQ - /RFSH - /HALT - /TEND1 Bit 0. LNAD/DATA. This bit controls the drive capability of the Address/Data bus output drivers. If this bit is set to 1, the output drive capability of the Address and Data bus output is reduced to 25% of its original drive capability. PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y Z85230 ESCC™ CONTROL REGISTERS See Figures 52 and 53 for the ESCC Control registers. For additional information, refer to the ESCC Product Specification /Technical Manual. The Z80182/Z8L182 has two ESCC channels. They can be accessed in any page of I/O space since only the lowest eight address lines are decoded for access. Their Z180™ MPU Address locations are shown in Table 11. When the 16550 MIMIC interface is enabled, ESCC channel B is disconnected from the output pins. The channel B /TRxCB clock is connected to the Transmit and Receive timers of the 16550 MIMIC interface. It is recommended that /TRxCB be programmed as an output with proper baud rate values to timeout the transmitter and receiver of the 16550 MIMIC interface. Table 11. ESCC Control and Data Map ESCC Channel A Control Data Z180 MPU Address xxE0H Z180 MPU Address xxE1H ESCC Channel B Control Data Z180 MPU Address xxE2H Z180 MPU Address xxE3H DS971820600 PS009801-0301 3-49 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL PROGRAMMING THE ESCC™ The ESCC contains write registers in each channel that are programmed by the system separately to configure the functional uniqueness of the channels. In the ESCC, the data registers are directly addressed by selecting a High on the D//C pin. With all other registers (with the exception of WR0 and RR0), programming the write registers requires two write operations and reading the read registers, both a write and a read operation. The first write is to WR0 and contains three bits that point to the selected register. The second write is the actual control word for the selected read register accessed. All of the ESCC registers, including the data registers, may be accessed in this fashion. The pointer bits are automatically cleared after the read or write operation so that WR0 (or RR0) is addressed again. With the Z80182/Z8L182, a new feature is implemented in the ESCC. The Transmitter and Receiver is now capable of sending and comparing a 32-bit CRC-32 (Ethernet Polynomial): x32 + x26 +x23 +x22 + x16 + x12 + x11 +x10 + x8 + x7 + x5 + x4 + x2 + x + 1 This feature is enabled by access to WR7' Bit 7, which selects the 32-bit CRC polynomial for the transmitter and receiver and overrides any selection of SDLC/CRC-16 CRCs. When the 32-bit CRC override feature is enabled, the transmitter will only send 32-bit CRC when CRC is to be sent. On the receive side, the CRC comparison/calculation will be done only on 32-bit CRC values. The result of the 32-bit CRC comparison will be maintained in RR1 bit D6 in place of the 16-bit CRC comparison result. The 32-bit CRC compare result will also be maintained in the 10x19 FIFO for frames in which 32-bit CRC is enabled. The CRC still can be preset to all 0s or all 1s. 32-bit CRC is disabled upon power-up or reset. Note: The ESCC cannot do simultaneous calculation/ comparison using both 16-bit and 32-bit CRC. Also, for the Z80182/Z8L182 only, the clock provided to the ESCC core is equal to the system clock divided by 1 or 2. The divider is programmed in the Z80182 Enhancement Register bit 3. 3-50 Divide-by-two should be programmed when running the Z182 beyond: - 20 MHz, 5V - 10 MHz, 3V Note: Upon power-up or reset the system clock is equal to the ESCC clock. Initialization. The system program first issues a series of commands to initialize the basic mode of operation. This is followed by other commands to qualify conditions within the selected mode. For example, in the Asynchronous mode, character length, clock rate, number of stop bits, and even or odd parity should be set first. Then the interrupt mode is set, and finally, the receiver and transmitter are enabled. Write Registers. The ESCC contains 16 write registers (17 counting the transmit buffer) in each channel. These write registers are programmed separately to configure the functional "personality" of the channels. There are two registers (WR2 and WR9) shared by the two channels that are accessed through either of them. WR2 contains the interrupt vector for both channels, while WR9 contains the interrupt control bits and reset commands. A new register, WR7', was added to the ESCC and may be written to if WR15, D0 is set. Figure 50 shows the format of each write register. Read Registers. The ESCC contains ten read registers (eleven, counting the receive buffer (RR8) in each channel). Four of these may be read to obtain status information (RR0, RR1, RR10, and RR15). Two registers (RR12 and RR13) are read to learn the baud rate generator time constant. RR2 contains either the unmodified interrupt vector (channel A) or the vector modified by status information (channel B). RR3 contains the Interrupt Pending (IP) bits (channel A only). RR6 and RR7 contain the information in the SDLC Frame Status FIFO, but is only read when WR15, D2 is set. If WR7' D6 is set, Write Registers WR3, WR4, WR5, WR7, and WR10 can be read as RR9, RR4, RR5, and RR14, respectively. Figure 51 shows the format of each Read register. PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y CONTROL REGISTERS Write Register 2 Write Register 0 (non-multiplexed bus mode) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 V0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Register 8 Register 9 Register 10 Register 11 Register 12 Register 13 Register 14 Register 15 V1 V2 V3 V4 Interrupt Vector V5 V6 V7 * Write Register 3 D7 D6 D5 D4 D3 D2 D1 D0 Null Code Point High Reset Ext/Status Interrupts Send Abort (SDLC) Enable Int on Next Rx Character Reset Tx Int Pending Error Reset Reset Highest IUS Rx Enable Sync Character Load Inhibit Address Search Mode (SDLC) Rx CRC Enable 0 0 1 1 * 0 1 0 1 Enter Hunt Mode Null Code Reset Rx CRC Checker Reset Tx CRC Generator Reset Tx Underrun/EOM Latch Auto Enables 0 0 1 1 With Point High Command 0 1 0 1 Rx 5 Bits/Character Rx 7 Bits/Character Rx 6 Bits/Character Rx 8 Bits/Character Write Register 1 Write Register 4 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Ext Int Enable 0 0 1 1 0 1 0 1 Tx Int Enable Parity Enable Parity is Special Condition Parity EVEN//ODD 0 0 1 1 Rx Int Disable Rx Int On First Character or Special Condition Int On All Rx Characters or Special Condition Rx Int On Special Condition Only WAIT/DMA Request On Receive//Transmit 0 0 1 1 /WAIT/DMA Request Function 0 1 0 1 0 1 0 1 Sync Modes Enable 1 Stop Bit/Character 1 1/2 Stop Bits/Character 2 Stop Bits/Character 8-Bit Sync Character 16-Bit Sync Character SDLC Mode (01111110 Flag) External Sync Mode WAIT/DMA Request Enable 0 0 1 1 0 1 0 1 X1 Clock Mode X16 Clock Mode X32 Clock Mode X64 Clock Mode Figure 52. Write Register Bit Functions DS971820600 PS009801-0301 3-51 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y CONTROL REGISTERS (Continued) Write Register 5 D7 D6 D5 D4 D3 D2 D1 D0 Tx CRC Enable RTS /SDLC/CRC-16 Tx Enable Send Break 0 0 1 1 0 1 0 1 Tx 5 Bits(Or Less)/Character Tx 7 Bits/Character Tx 6 Bits/Character Tx 8 Bits/Character DTR Write Register 6 D7 D6 D5 D4 D3 D2 D1 D0 Sync7 Sync1 Sync7 Sync3 ADR7 ADR7 Sync5 Sync5 Sync5 Sync1 ADR5 ADR5 Sync6 Sync0 Sync6 Sync2 ADR6 ADR6 Sync4 Sync4 Sync4 Sync0 ADR4 ADR4 Sync3 Sync3 Sync3 1 ADR3 x Sync2 Sync2 Sync2 1 ADR2 x Sync1 Sync1 Sync1 1 ADR1 x Sync0 Sync0 Sync0 1 ADR0 x Monosync, 8 Bits Monosync, 6 Bits Bisync, 16 Bits Bisync, 12 Bits SDLC SDLC (Address Range) Write Register 7 D7 D6 D5 D4 D3 D2 D1 D0 Sync7 Sync5 Sync15 Sync11 0 Sync6 Sync4 Sync14 Sync10 1 Sync5 Sync3 Sync13 Sync9 1 Sync4 Sync2 Sync12 Sync8 1 Sync3 Sync1 Sync11 Sync7 1 Sync2 Sync1 Sync0 x Sync10 Sync9 Sync6 Sync5 1 1 Sync0 x Sync8 Sync4 0 Monosync, 8 Bits Monosync, 6 Bits Bisync, 16 Bits Bisync, 12 Bits SDLC Figure 52. Write Register Bit Functions (Continued) 3-52 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y Write Register 10 WR 7' Prime D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 D0 D0 Auto Tx Flag 6-Bit//8-Bit Sync Auto EOM Reset Loop Mode Auto RTS Deactivation Abort//Flag On Underrun Rx FIFO Int Level Mark//Flag Idle DTR/REQ Timing Mode Go Active On Poll Tx FIFO Int Level Extended Read Enable 32-bit CRC Enable 0 0 1 1 0 1 0 1 NRZ NRZI FM1 (Transition = 1) FM0 (Transition = 0) CRC Preset I//O Write Register 9 D7 D6 D5 D4 D3 D2 D1 D0 Write Register 11 D7 D6 D5 D4 D3 D2 D1 D0 VIS NV DLC 0 0 1 1 MIE Status High//Status Low Software INTACK Enable 0 0 1 1 0 1 0 1 0 1 0 1 /TRxC Out = Xtal Output /TRxC Out = Transmit Clock /TRxC Out = BR Generator Output /TRxC Out = DPLL Output /TRxC O/I 0 0 1 1 No Reset Not used Channel Reset Force Hardware Reset 0 0 1 1 0 1 0 1 0 1 0 1 Transmit Clock = /RTxC Pin Transmit Clock = /TRxC Pin Transmit Clock = BR Generator Output Transmit Clock = DPLL Output Receive Clock = /RTxC Pin Receive Clock = /TRxC Pin Receive Clock = BR Generator Output Receive Clock = DPLL Output /RTxC Xtal//No Xtal Figure 52. Write Register Bit Functions (Continued) DS971820600 PS009801-0301 3-53 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL CONTROL REGISTERS (Continued) Write Register 14 Write Register 12 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 TC0 BR Generator Enable TC1 BR Generator Source TC2 /DTR/Request Function TC3 TC4 Auto Echo Lower Byte of Time Constant TC5 Local Loopback 0 0 0 0 1 1 1 1 TC6 TC7 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Null Command Enter Search Mode Reset Missing Clock Disable DPLL Set Source = BR Generator Set Source = /RTxC Set FM Mode Set NRZI Mode Write Register 13 D7 D6 D5 D4 D3 D2 D1 D0 Write Register 15 D7 D6 D5 D4 D3 D2 D1 D0 TC8 TC9 TC10 WR7' SDLC Feature Enable TC11 Zero Count IE TC12 Upper Byte of Time Constant SDLC FIFO Enable TC13 DCD IE TC14 Sync/Hunt IE TC15 CTS IE Tx Underrun/EOM IE Break/Abort IE Figure 52. Write Register Bit Functions (Continued) 3-54 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y Read Register 0 Read Register 3 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Rx Character Available 0 Zero Count 0 Tx Buffer Empty 0 DCD Ext/Status IP Sync/Hunt Tx IP CTS Rx IP Tx Underrun/EOM 0 Break/Abort 0 Read Register 6* Read Register 1 D7 D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 BC0 All Sent BC1 Residue Code 2 BC2 Residue Code 1 BC3 Residue Code 0 BC4 Parity Error BC5 Rx Overrun Error BC6 CRC/Framing Error BC7 End of Frame (SDLC) *Can only be accessed if the SDLC FIFO enhancement is enabled (WR15 bit D2 set to 1) SDLC FIFO Status and Byte Count (LSB) Read Register 2 D7 D6 D5 D4 D3 D2 D1 D0 Read Register 7* V0 D7 D6 D5 D4 D3 D2 D1 D0 V1 V2 V3 V4 BC8 Interrupt Vector BC9 BC10 V5 BC11 V6 BC12 V7 BC13 FDA: FIFO Data Available 1 = Status Reads from FIFO 0 = Status Reads from EMSCC FOS: FIFO Overflow Status 1 = FIFO Overflowed 0 = Normal *Can only be accessed if the SDLC FIFO enhancement is enabled (WR15 bit D2 set to 1) SDLC FIFO Status and Byte Count (LSB) Figure 52. Write Register Bit Functions (Continued) DS971820600 PS009801-0301 3-55 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL CONTROL REGISTERS (Continued) Read Register 13 Read Register 10 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0 TC8 On Loop TC9 0 TC10 0 TC11 Loop Sending TC12 0 TC13 Two Clocks Missing TC14 One Clock Missing TC15 Upper Byte of Time Constant Read Register 15 Read Register 12 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 TC0 0 TC1 Zero Count IE TC2 SDLC Status FIFO Enable TC3 TC4 Lower Byte of Time Constant DCD IE Sync/Hunt IE TC5 CTS IE TC6 Tx Underrun/EOM IE TC7 Break/Abort IE Figure 53. Read Register Bit Functions 3-56 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS Figures 54 through 65 describe miscellaneous registers that control the Z182 configuration, RAM/ROM chip select, interrupt and various status and timers. D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Daisy Chain 0=ESCC > 16550 MIMIC 1=16550 MIMIC> ESCC ESCC/MIMIC 0=ESCC Channel B 1=16550 MIMIC Interface Tri-Muxed Pins 0=Z80180 1=ESCC Channel/16550 MIMIC Disable ROMs 0=ROM Sel Enabled 1=ROM Sel Disabled DOUT 0=No Data Out 1=Data Out Port PB4-PB0 Select 0=ASCI Channel 0 Func 1=PB4-PB0 Selected Port PB7-PB5 Select 0=RXA1, TXA1, (RXS,/CTS1) 1=PB7-PB5 Selected Port C Select 0=ESCC Channel A Func 1=Port C Selected Figure 54. System Configuration Register (Z180 MPU Read/Write, Address xxEFH) System Configuration Register Bit 7 Port C Select When this bit is set to 1, bit 8 parallel Port C is selected on the multiplexed pins. When this bit is reset to 0 then these multiplexed pins take ESCC™ Channel A functions. Bit 6 PB7-PB5 Select When this bit is set to 1, parallel Port B bits 7 through 5 are selected on the multiplexed pins. When this bit is reset to 0, these multiplexed pins become RxA1, TxA1 and RxS/ CTS1. Bit 5 PB4-PB0 Select When this bit is set to 1, parallel Port B bits 4 through 0 are selected on the multiplexed pins. When this bit is reset to 0, these multiplexed pins take ASCI channel 0 functions. Bit 4 DDOUT ROM Emulator Mode Enable When this bit is set to 1, the Z182 is in “ROM emulator mode”. In this mode, bus direction for certain transaction periods are set to the opposite direction to export internal bus transactions outside the Z80182/Z8L182. This allows the use of ROM emulators/logic analyzers for application development (see Tables 12a and 12b). Note: The word “Out” means that the Z182 data bus direction is in output mode, “In” means input mode, and “Z” means high impedance. DDOUT stands for Data Direction Out and is the status of the D4 bit in the System Configuration Register (SCR). Table 12a. Data Bus Direction (Z182 Bus Master) I/O And Memory Transactions I/O Write to On-Chip Peripherals I/O Read From On-Chip Peripherals I/O Write to Off-Chip Peripherals Z80182 /Z8L182 Data Bus (DDOUT =0) Out Z Out In Out In Z Z Z80182 /Z8L182 Data Bus (DDOUT =1) Out Out Out In Out In Z Z DS971820600 I/O Read Write From Off-Chip To Peripherals Memory PS009801-0301 Read From Mode Z80182 /Z8L182 Refresh Idle Mode 3-57 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS Table 12b. Data Bus Direction (Z182 Bus Master) Interrupt Acknowledge Transaction Intack For On-Chip Peripheral (IEI=1) Intack For Off-Chip Peripheral (IEI=0) Z80182/Z8L182 Data Bus (DDOUT=0) Z In Z80182/Z8L182 Data Bus (DDOUT=1) Out In Table 13a. Data Bus Direction (Z80182/Z8L182 is not Bus Master) I/O And Memory Transactions I/O Write to On-Chip Peripherals I/O Read From On-Chip Peripherals I/O Write to Off-Chip Peripherals I/O Read From Off-Chip Peripherals Write To Memory Read From Mode Refresh Z80182 Idle Mode Z80182 /Z8L182 Data Bus DDOUT=0) In Out Z Z Z In Z Z Z80182 /Z8L182 Data Bus (DDOUT=1) In Out Z Z Z In Z Z Table 13b. Data Bus Direction (Z80182/Z8L182 is not Bus Master) Interrupt Acknowledge Transaction Intack For On-Chip Peripheral Intack For Off-Chip Peripheral Z80182/Z8L182 Data Bus (DDOUT=0) Out In Z80182/Z8L182 Data Bus (DDOUT=1) Out In 3-58 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS Bit 3 Disable ROMs If this bit is 1, it disables the ROMCS pin. If it is 0, addresses below the ROM boundary set by the ROMBR register will cause the ROMCS pin to go Low. Bit 2 Tri-Muxed Pins Select The Z80182/Z8L182 has three pins that are triple multiplexed and controlled by bit 2 and bit 1. Table 14 shows the different modes. Table 14. SCR Control for Triple Multiplexed Pins Bit 2 Bit 1 System Configuration Register 0 0 1 1 0 1 0 1 /TEND1,TxS,CKS /TEND1,TxS,CKS /RTSB,(/DTR//REQB),(/W//REQB) /HRxRDY,//HTxRDY,HINTR Bit 1 ESCC™ Channel B/MIMIC If this bit is 0, Mode 0 is selected. If this bit is 1, Mode 1 is selected. Mode 0: Channel A ESCC Enabled Channel B ESCC Enabled PIA Port Enabled 16550 MIMIC Interface Disabled Mode 1: Channel A ESCC enabled Channel B outputs disabled PIA disabled 16550 MIMIC Interface Enabled Bit 0 Daisy Chain This bit is used to set interrupt priority of the ESCC and 16550 MIMIC interface. If it is 0, the ESCC is higher up in the daisy chain than the 16550 MIMIC interface. If it is 1, the 16550 interface is higher up than the ESCC. Note that /INT0 is used for both MIMIC and ESCC Interrupts. /RAMCS AND /ROMCS REGISTERS To assist decoding of ROM and RAM blocks of memory, three more registers and two pins have been added to the Z80182/Z8L182. The two pins are /ROMCS and /RAMCS. The three registers are RAMUBR, RAMLBR and ROMBR. D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Upon reset 1 1 1 1 1 1 1 Upon reset 1 DS971820600 1 1 1 1 1 1 1 A19-A12 A19-A12 Figure 55. RAMUBR (Z180 MPU Read/Write, Address xxE6H) 1 Figure 56. RAMLBR (Z180 MPU Read/Write, Address xxE7H) PS009801-0301 3-59 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y /RAMCS AND /ROMCS REGISTERS (Continued) RAMUBR, RAMLBR RAM Upper Boundary Range, RAM Lower Boundary Range These two registers specify the address range for the /RAMCS signal. When accessed memory addresses are less than or equal to the value programmed in the RAMUBR and greater than or equal to the value programmed in the RAMLBR, /RAMCS is asserted. The A18 signal from the CPU is taken before it is multiplexed with TOUT. In the case that these registers are programmed to overlap, /ROMCS takes priority over /RAMCS (/ROMCS is asserted and /RAMCS is inactive). Because /ROMCS takes priority over /RAMCS, the latter will never be asserted until the value in the ROMBR and RAMLBR registers are re-initialized to lower values. D7 D6 D5 D4 D3 D2 D1 D0 Upon reset These registers are set to FFH at POR, and the boundary addresses of ROM and RAM are as follows: ROM lower boundary address (fixed) = 00000H 1 1 1 1 1 1 1 A19-A12 Figure 57. ROMBR (Z180 MPU Read/Write, Address xxE8H) Chip Select signals are going active for the address range: /ROMCS: (ROMBR) >= A19-A12 >= 0 /RAMCS: (RAMUBR) >= A19-A12 >= (RAMLBR) 1 ROMBR ROM Address Boundary Register This register specifies the address range for the /ROMCS signal. When accessed, memory addresses are less than or equal to the value programmed in this register, the /ROMCS signal is asserted. The A18 signal from the CPU is obtained before it is multiplexed with TOUT. This signal can be forced to a “1” (inactive state) by setting bit 3 in the System Configuration Register, to allow the user to overlay the RAM area over the ROM area. ROM upper boundary address (ROMBR register) = 0FFFFFH RAM lower boundary address (RAMLBR register) = 0FFFFFH RAM upper boundary address (RAMUBR register) = 0FFFFFH Z80182 Improvement to the Wait State Generator A separate Wait State Generator is provided for access memory using /ROMCS and /RAMCS. A single 8-bit register is added to enable/disable this feature as well as provide two 3-bit fields that provide 1 to 8 waits for each chip select. There are two wait state generators in the Z182. The actual number of wait states inserted is the greatest number of both the Z180 WSG and the chip select WSG. In order to use the Chip Select WSG, the Z180 WSG should be programmed to 0 wait states. WSG Chip Select Register (Z80182 address D8H) Bit 7 Bits 6-4 Bit 3 Bits 2-0 /RAMCS Wait State Generator Enable. Disable on power-up or reset. D7 D6 0 /RAMCS Wait States 1 to 8. Eight wait states on power-up or reset. D5 D4 D3 D2 D1 D0 0 /ROMCS Wait States 1-8 /ROMCS Wait State Generator Enable /ROMCS Wait State Generator Enable. Disable on power-up or reset. /RAMCS Wait States 1-8 /RAMCS Wait State Generator Enable /ROMCS Wait States 1 to 8. Eight wait states on power-up or reset. Figure 58. WSG Chip Select Register (Z180 MPU Read/Write, Address xxD8H) 3-60 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y INTERRUPT EDGE/PIN MUX REGISTER D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 1 1 0 Halt Recovery Select 1 16 Cycle delay on Halt recovery 0 No wait delay on Halt recovery Low Noise Select 1 Select low noise for Z182(not Z180) 0 Select normal drive for Z182 pins IEO,/IOCS Select 1 Select/IOCS Function 0 Select IEO Function /MREQ, /MRD, PC2, /RTSA, /MWR Select 1 Select /MRD, /MWR 0 Select /MREQ, PC2, /RTSA /INT1 Mode Select 0X Normal Level Detect 10 Falling (Neg) Edge Det 11 Rising (Pos) Edge Det /INT2 Mode Select 0X Normal Level Detect 10 Falling (Neg) Edge Det 11 Rising (Pos) Edge Det Figure 59. Interrupt Edge/Pin MUX Register (Z180 MPU Read/Write, Address xxDFH) Bits 7-6. These bits control the interrupt capture logic for the external /INT2 PIN. When programmed as ‘0X’, the /INT2 pin performs as the normal level detecting interrupt pin. When programmed as 10 the negative edge detection is enabled. Any falling edge latches an active Low on the internal /INT2 of the Z180. This interrupt must be cleared by writing a 1 to bit 7 of the Port C Data Register. Programming these control bits to 11 enables rising edge interrupts to be latched. The latch is cleared in the same fashion as the falling edge. Bits 5-4. These bits control the interrupt capture logic for the external /INT1 PIN. When programmed as ‘0X’, the /INT1 pin performs as the normal level detecting interrupt pin. When programmed as 10, the negative edge detection is enabled. Any falling edge latches an active Low on the internal /INT1 of the Z180. This interrupt must be cleared by writing a 1 to bit 6 of the Port C Data Register. Programming these control bits to 11 enables rising edge interrupts to be latched. The latch is cleared in the same fashion as the falling edge. Edge detect logic cannot be used in Emulation Adaptor EV mode 1. Bit 3. Programming this bit to 1 selects the /MRD and the /MWR functions. The default for power up and /RESET conditions is 1, i.e., the /MRD and /MWR. By programming DS971820600 this bit to 0 the /MREQ Z180 function is enabled, as well as the PC2//RTSA function on the PC2//RTSA//MWR pin. If the /MREQ Z180 function is enabled, any external bus master must be prevented from asserting Z182's IRD signal unless accessing Z182's IO. Bit 2. This bit selects the /IOCS function which is the default for power up and /RESET conditions. By programming this bit to 0 the IEO function is enabled for this multiplexed pin. Bit 1. This bit selects the low noise or normal drive feature for the Z182 pins . The default at power up is normal drive for Z182 pins. By programming this bit to 1, low noise for the Z182 pins is chosen and the output drive capability of the following pins is reduced to 25% of the original drive capability: - CKS - RxS/CTS1 - TxS - CKA1/TEND0 - TxA1 - CKA0/DREQ0 - TxA0 Programming this bit to 0 selects normal drive for the Z182 pins. Refer to the Z8S180 Product Specification for Low noise control of Z180 pins. PS009801-0301 3-61 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL INTERRUPT EDGE/PIN MUX REGISTER (Continued) Bit 0. Programming this bit to 1 selects a 16 cycle wait delay on recovery from HALT. Halt Recovery is disabled if bit 5 of the enhancement register is set to 1. A 0 selects no wait delay on Halt recovery. If Halt Recovery is selected, the following pins assume the following states during halt and during the recovery, whether it is in HALT, SLP, IDLE or STBY Modes: Address Data Bus RD WR MREQ/MRD M1 ST IORQ BUSACK RFSH E IOCS MWR = = = = = = = = = = = = = Z Z Z Z Z 1 1 1 1 1 Note 3 Z 1 (Note 4) Notes: 1. This assumes that BUSREQ is not activated during the halt. 2. This assumes that the refresh is not enabled. This would not be a logical case since the address bus is tri-stated during the Halt mode. 3. There is no control on the E line during the halt recovery so transitions on the pin are possible. 4. This is only true if MWR function is enabled. The Halt recovery mode is implemented by applying wait states to the next CPU operation following the exit from halt. All signals listed above are forced to their specified state (unless otherwise noted) during halt and also during the recovery state. Sixteen cycles after the halt pin goes High the signals are released to their normal state, then eight wait states are inserted to allow proper access to accommodate slow memories. After the first memory access, the wait states will be inserted as programmed in the wait state generators. In addition, if bit 4 of the Z80182 Enhancement Register is set, the TxDA pin will be tri-stated during Halt and Recovery modes. 3-62 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y 16550 MIMIC INTERFACE REGISTERS MIMIC Master Control Register (MMC) The 16550 MIMIC interface is controlled by the MMC register. Setting it allows for different modes of operation such as using the 8-bit counters, DMA accesses, and which IRQ structure is used with the PC/XT/AT. D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Both counters are single pass and stop on a count of Zero. Their purpose is to delay data transfer just as if the 16550 UART had to shift the data in and out. This is provided to alleviate any software problems a high speed continuous data transfer might cause to existing software. If this is not a concern, then data can be read and written as fast as the two machines can access the devices. In FIFO mode of operation , the timers are used to delay the status to the PC interface by the time required to actually shift the characters out, or in, if an actual UART were present. VIS Vector Include Status 0 Mode 0 Interrupts 1 Mode 2 Interrupts Bit 5 Transmit DMA Enable (Read/Write) If this bit is set to 1, it enables the Transmit DMA function. HINTR 00 Normal 01 Wire And 10 Out 2 Control 11 Reserved Bit 4 Receive DMA Enable (Read/Write) If this bit is set to 1, it enables the Receive DMA function. Rx DMA Tx DMA 0=Chan 0 Z180 1=Chan 1 Z180 0=Chan 1 Z180 1=Chan 0 Z180 Rx DMA Enable Tx DMA Enable Bit 3 Receive DMA Channel Select (Read/Write) If bit 3 is set to 0, then Receive DMA transfer is done through Z180 DMA channel 0 and the Transmit DMA is done through DMA channel 1. If bit 3 is set to 1, then Receive DMA transfer is done through Z180 DMA channel 1 and the Transmit DMA is done through DMA channel 0. Rx Timer Enable Tx Timer Enable Figure 60. MIMIC Master Control Register (Z180 MPU Read/Write, Address xxFFH) Bit 7 Transmit Emulation Delay Counter Enable (Read/Write) If bit 7 is set to 1, it enables the transmit delay timer. When the Z180 reads the Transmit Register, it loads the transmit delay timer from the Transmit Time Constant Register and enables the timer to count down to zero. This timer delays setting the Transmit Holding Register Empty (THRE) bit until the timer times out. If this bit is 0, then THRE is set immediately on a Z180 read of the Transmit Register. This bit also enables the emulation timer used in Transmitter Double Buffering. Bit 6 Receive Emulation Delay Counter Enable (Read/Write) If bit 6 is set to 1, it enables the receive delay timer. When the Z180 writes to the Receive Buffer, it loads the receive delay timer from the Receive Time Constant Register and enables the timer to count down to zero. This timer delays setting the Data Ready (DR) bit in the LSR until the timer times out. If this bit is 0 then DR is set immediately on a Z180 write to the Receive Buffer. DS971820600 Bits 2,1 Interrupt Select (Read/Write). See Table 15. Bit 0 Vector Include Status (Read/Write) This bit is used to select the interrupt response mode of the Z180. A 0 in this bit enables Mode 0 interrupts; a 1 enables Mode 2 response. Table 15. MIMIC Master Control Register Interrupt Select Bit 2 Bit 1 0 0 HINTR is set to normal 16550 MIMIC mode. A fully driven output is required when external priority arbiters are used. 0 1 A wired AND condition on the HINTR pin is possible to the PC/XT/AT. The interrupt is active High with only the pull-up of the HINTR pin driving; otherwise this pin is tri-state. Wired AND is needed when an external arbiter is not available. 1 0 HINTR is driven when out 2 of the Modem Control Register is 1. HINTR is tri-state when MCR out 2 is 0. 1 1 RESERVED PS009801-0301 HINTR Function 3-63 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL IUS/IP Register The IUS/IP Register is used by the Z180™ MPU to determine the source of the interrupt. This register will have the appropriate bit set when an interrupt occurs. D7 0 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 Interrupt Pending 6 THR Write 5 TTO Transmitter Timeout 4 RBR Read 3 MCR Write 2 LCR Write 1 DLL Write 1 DLM Write 0 FCR Write or Tx Overrun Interrupt Under Service (RD) Reset Highest IUS (WR) Figure 61. IUS/IP Register (Z180 MPU, Address xxFEH) Bit 7 Interrupt Under Service (Read/Write) This bit represents a logical OR of each individual IUS bit for the internal MIMIC interrupt daisy chain. An IUS bit is set when an interrupt is registered (IP set) and enabled (IE set), the incoming IEI daisy chain is active (chain enabled) and an interrupt acknowledge cycle is entered. By writing a 1 to this bit the highest priority IUS bit that is set will be reset. Writing a 0 to this bit has no effect. This should be done at the end of every MIMIC Interrupt Service routine. Bit 6 Transmit Holding Register Written (Read Only) This bit is set when the PC/XT/AT writes to the Transmit Holding Register. It is reset when the Z180 MPU reads the Transmit Holding Register. In FIFO mode, this bit is set when the trigger level is reached (4,8,14 bytes available). Note: The THR bit is set (interrupts) when the transmitter FIFO reaches the data available trigger level set in the MPU FCR control register. The bit and interrupt source is cleared when the number of data bytes falls below the set trigger level. 3-64 Bit 5 Transmitter Timeout with Data in FIFO (Read Only) This bit is set when the transmitter FIFO has been idle (no read or write and timer decrements to zero) with data bytes below the trigger level. It is cleared when the FIFO is read or written. Bit 4 Receive Buffer Read (Read Only) This bit is set when the PC/XT/AT reads the Receive Buffer Register. It is reset when the Z180 MPU writes to the Receive Buffer Register. In FIFO mode, this bit is set upon the PC reading all the data in the receive FIFO. Note: RBR is set and interrupts when the receive FIFO has been emptied by the PC. This bit and interrupt are cleared when one or more bytes are written into the receive FIFO by the MPU. Bit 3 Modem Control Register Write (Read Only) This bit is set when the PC/XT/AT writes to the Modem Control Register. It is reset when the Z180™ MPU reads the Modem Control Register. Bit 2 Line Control Register Write (Read Only) This bit is set when the PC/XT/AT writes to the Line Control Register. It is reset when the Z180 MPU reads the Line Control Register. Bit 1 Divisor Latch LS/MS Write (Read Only) This bit is set when the PC/XT/AT writes to the Divisor Latch Least Significant or Most Significant bytes. It is reset when the PC reads the LS/MS register(s). To determine which byte(s) have been written, the Z180 must read either LS or MS locations and then repoll this bit. If only one location is interrupting, the interrupt is cleared when that location is read by the Z180. Bit 0 FIFO Control Register Write (Read Only) This bit is set when the PC/XT/AT writes to the FCR. This bit is also set when Transmit occurs. It is reset when the Z180 MPU reads this register. PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y Interrupt Enable Register The IE Register allows each of the 16550/8250 interrupts to the Z180™ MPU to be masked off individually or globally. Priority of interrupts are in this order: (Highest) D7 D6 0 0 6 5 4 3 2 1 1 0 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 Interrupt Enable 6 Enable THR IRQ 5 Enable TTO IRQ 4 RBR IRQ 3 Enable LCR IRQ 2 Enable MCR IRQ 1 Enable DLL/DLM IRQ 0 Enable FCR IRQ MIE Figure 62. IE Register (Z180 MPU, Address xxFDH) Bit 7 Master Interrupt Enable (Read/Write) If bit 7 is 0, all interrupts from the 16550 MIMIC are masked off. If this bit is 1, then interrupts are enabled individually by setting the appropriate bit. Bit 6 Enable THR Interrupt (Read/Write) If this bit is 1, it enables the Transmit Holding Register Interrupt. Bit 5 Enable TTO Interrupt (Read/Write) If this bit is 1, it enables the Transmitter Timeout Interrupt. This interrupts the CPU when characters remain in the FIFO below the trigger level and the FIFO is not read or written for the length of time in the transmitter timeout register. (Lowest) Interrupt Vector Register The Interrupt Vector Register contains either the opcode (Z180 Interrupt Mode 0) or the modified vector used as the lower address for a Z180 interrupt service routine (Z180 Interrupt Mode 2), depending upon the VIS bit in the MMC Register (MIMIC Master Control Register). If the VIS bit is 0, then Z180 Mode 0 interrupt is selected; if VIS is 1, then Z180 Mode 2 is selected. Note that in Z180 Interrupt Mode 0, the data input to the MPU during the interrupt acknowledge cycle is an instruction opcode; in Z180 Interrupt Mode 2, this data (modified depending on the source of the interrupt) becomes part of an address from which to get the starting address of the interrupt service routine. D7 D6 0 0 D5 D4 D3 D2 D1 D0 0 Bit 2 Enable MCR Interrupt (Read/Write) If this bit is 1, it enables the Modem Control Register Interrupt. Bit 1 Enable DLL/DLM Interrupt (Read/Write) If this bit is 1, it enables the Divisor Latch Least and Most Significant Byte interrupts. Bit 0 Enable FCR Interrupt (Read/Write) If this bit is 1 , then interrupts are enabled for a PC write to the FIFO control register (FCR) or for occurrence of Tx Overrun. DS971820600 0 0 0 0 0 0/Opcode Status/Opcode Upper Nibble IVEC Bit 4 Enable RBR Interrupt (Read/Write) If this bit is 1, it enables the Receive Buffer Register Interrupt. Bit 3 Enable LCR Interrupt (Read/Write) If this bit is 1, it enables the Line Control Register interrupt. THR IRQ TTO IRQ RBR IRQ MCR IRQ LCR IRQ DLL IRQ DLM IRQ FCR or Tx OVERRUN IRQ Figure 63. IVEC Register (Z180 MPU, Address xxFCH) Bits 7-4 Upper Nibble IVEC (Read/Write) These four bits generate either an opcode for Z180 Interrupt Mode 0, or the upper four bits of the interrupt modified vector used as an 8-bit address to support the Z180 Interrupt Mode 2. These bits are read/write and always read back what was last written to them. Bits 3-1 Interrupt Modified Vector/Opcode (Read/Write Table 16) These three bits are the Interrupt Status bits when VIS in the MMC register is 1 (Z180 Interrupt Mode 2). If VIS bit is 0, then this field contains bit 3-bit 1 of the opcode. If the VIS bit is 0, then these bits contain what was last written to them. PS009801-0301 3-65 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y Interrupt Vector Register (Continued) Table 16. Interrupt Status Bits Bits 3, 2, 1 Interrupt Request 000 001 010 011 100 101 110 111 NO IRQ FCR or Tx OVRN IRQ DLL/DLM IRQ LCR IRQ* MCR IRQ* RBR IRQ TTO IRQ THR IRQ Note: * The order of LCR and MCR does not follow that of the IE Register. Bit 0 0/Opcode (Read/Write) This bit is always 0 when the VIS bit is 1. If the VIS bit is 0, this bit reads back what was last written to it. The Interrupt Vector Register serves both interrupt modes. When the VIS bit is 0, the last value written to the register can be read back. If the VIS bit is 1, and an interrupt is pending, the value read is the last value written to the upper nibble plus the status for the interrupt that is pending. If no interrupt is pending, then the last value written to the upper nibble plus the lower nibble is read from the register. If the vector includes the status, then the lower four bits of the vector change asynchronously depending on the interrupting source. Since this vector changes asynchronously, then the interrupt service routine to read the IVEC register might read the source of the most recent IRQ/INTACK cycle if that IRQ does not have its IUS set. 0 0 0 0 0 0 Table 17. Transmitter Trigger Level b7 b6 0 0 1 1 0 1 0 1 Level (# bytes) 1 4 8 14 Bit 5 Receive Timeout Enable This bit enables the Z80182/Z8L182 Receive Timeout Timer that is used to emulate the four character timeout delay that is specified by the 16550. If no read or write to the RCVR FIFO has taken place and data bytes are available, but are below the PC trigger level. If this timer reaches zero, an interrupt is sent to the PC. Bit 4 Transmitter Timeout Enable This bit enables the Z80182/Z8L182 timer that is used to interrupt the Z180 MPU if characters are available, but are below the trigger level. The timer is enabled to count down if this bit is 1 and the number of bytes is below the set transmitter trigger level. The timer will timeout and interrupt the MPU if no read or write to the XMIT FIFO takes place within the timer interval. Bit 3 Reserved. Program to zero. Bit 2 (Reset value = 0) TEMT/Double Buffer When enabled the Tx buffer can hold one extra byte (2 bytes total in 16450 mode). (Do not enable in 16550 mode.) D7 D6 D5 D4 D3 D2 D1 D0 0 Bit 7 and Bit 6 XMIT Trigger MSB,LSB This field determines the number of bytes available to read in the transmitter FIFO before an interrupt occurs to the MPU (Table 17). 0 16450 MIMIC mode Enable RTO Timeout Enhancement TEMT Enable Reserved for Future Use Always write and read as 0 XMIT Timeout Enable RCVR Timeout Enable XMIT Trigger LSB XMIT Trigger MSB Figure 64. FIFO Status and Control Register (Z180 MPU Read/Write, Address xxECH) 3-66 TEMT Emulation If character delay emulation is not used the TEMT bit is automated. (Refer to page 26 for TEMT/Double Buffer information.) Bit 1 RTO Timeout Enhancement (Reset value = 0) Setting this bit will enable the RTO timeout to emulate the 16550 device. When enabling this feature, the receive timeout timer will not begin counting down until the character emulation timer for each byte of data in the Rx FIFO has expired. PS009801-0301 DS971820600 Zilog Bit 0 16450 MIMIC Mode Enable (Reset value=0) This bit = 1 will force the mimic into 16450 mode. Bit 0 in the FCR reg is forced to zero as well as the mimic internal FIFO enable. When used, this bit should be programmed at MIMIC initialization and not modified afterwards. D7 D6 D5 D4 D3 D2 D1 D0 1 1 Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y 1 1 1 1 1 1 This register contains an 8-bit constant for determining the interval for the Transmit Timeout Timer. If allowed to decrement to zero, this timer interrupts the MPU by setting the THR bit in the IUS/IP register. This timer receives its input from the /TRxCB Clock of the SCC. The timer is enabled to down count when the enable bit in the FSR register is set and the trigger level has not been reached on the XMIT FIFO. The counter reloads each time there is a read or write to the XMIT FIFO. Transmit And Receive Timers Rec Timeout Constant Figure 65. Receive Timeout Timer Constant (Z180 MPU Read/Write, Address xxEAH) This register contains an 8-bit constant for emulation of the 16550 four character timeout feature. Software must determine the value to load into this register based on the bit rate and word length specified by the MIMIC interface with the PC. This timer receives its input from the /TRxCB Clock of the ESCC. This timer is enabled to down count when the enable bit in the FSR register is set and the trigger level interrupt has not been activated on the RCVR FIFO. The counter reloads and counts down each time there is a read or write to the RCVR FIFO. The receive timeout timer is enhanced to emulate the actual 16550 when bit 1 of the FIFO status and control register is enabled. Under most circumstances, this register should be programmed for four character timers (40d, 8-N-1). D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 Because of the speed at which data transfers can take place between the Z180™ MPU and the PC/XT/AT, two timers have been added to alleviate any software problems that a high speed parallel data transfer might cause. These timers allow the programmer to slow down the data transfer just as if the 16550 MIMIC interface had to shift the data in and out serially. The Timers receive their input from the /TRxCB Clock since, in 16550 MIMIC mode, the ESCC channel B is disabled. For example, the clock source for the 8-bit registers: RTTC (Receive Timeout Time Constant, xxEAH), TTTC (Transmit Timeout Time Constant, xxEBH), TTCR (Transmit Time Constant Register, xxFAH) and RTCR (Receive Time Constant Register, xxFBH) uses the /TRxCB Clock output. The /TRxCB Clock output needs to be generated by the ESCC’s channel B's 16-bit BRG as its clock source, thus allowing the programmer to access a total of 24 bits as a timer to slow down the data transfer. In most cases, ESCC Ch. B BRG should be programmed to output at a frequency equivalent to the desired serial transfer rate. The output of the BRG should be routed to the /TRxCB pin. D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 Transmitter Time Constant Figure 66. Transmit Timeout Timer Constant (Z180 MPU Read/Write, Address xxEBH) DS971820600 1 1 1 1 1 XMIT Timeout Constant Figure 67. Transmitter Time Constant Register (Z180 MPU Read/Write, Address xxFAH) PS009801-0301 3-67 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y Transmit And Receive Timers (Continued) When a write from the PC/XT/AT is made to the Transmit Holding Register, an interrupt to the Z180 MPU is generated. The Z180 MPU then reads the data in the Transmit Holding Register. Upon this read, if the Transmitter timer is enabled, the time constant from the Transmitter Time Constant Register is loaded into the Transmitter timer and enables the count. After the timer reaches a count of zero the Transmit Holding Register Empty bit is set. However, the above is only true when the PC/XT/AT is reading the Transmit Holding Register Empty bit. To allow the Z180 MPU to know that it has already read the byte of data, immediately following a read from the Transmit Holding Register, a mirrored Transmit Holding Register, Empty bit is set. This mirrored bit is always read back to the Z180 MPU when it reads the Line Status Register. If the transmitter timer is not enabled when the Z180 MPU reads the Transmit Holding Register, both Transmit Holding Register Empty bits are set immediately. In FIFO mode of operation, the effect is similar as the status to PC is always delayed such that a PC interrupt for empty FIFO will not occur before the time required for each character read from the FIFO by the Z180 has elapsed. The effect is that the PC will not see data requests from an empty FIFO any faster than would occur with a true UART when the delay feature is enabled. This timer is also used to delay data transfer for TSR buffer to Z80182 THR in double buffer mode. 3-68 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 1 Receiver Time Constant Figure 68. Receive Time Constant Register (Z180 MPU Read/Write, Address xxFBH) When the Z180™ MPU writes to the Receive Buffer register and the Receive Timer is enabled, the Receive Timer is loaded with the Receive Time Constant, the timer is enabled and counts down to zero. When the timer reaches zero, the Data Ready bit in the Line Status Register is set. As with the Transmit Timer, the Data Ready bit is also mirrored. Immediately upon a write to the Receive Buffer, the mirrored bit is set to let the Z180 MPU know that the byte has already been written. If the timer is not enabled, then both Data Ready bits are set immediately upon a write to the Receive Buffer. The FIFO mode of operation is similar in that the status to the PC is always delayed by the time required for each character written to the FIFO by the Z180. The effect is that the PC will not see a FIFO trigger level or DMA request faster than would occur with a true UART when the delay feature is enabled. PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y 16550 MIMIC REGISTERS The Z80182/Z8L182 contains the following set of registers for interfacing with the PC/XT/AT. – – – – – – – – – – – – Receive Buffer Register Transmit Holding Register Interrupt Enable Register Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratch Register Divisor Latch Least/Most Significant Bytes FIFO Control Register These registers emulate the 16550 UART and enable the PC/XT/AT to interface with them as with an actual 16550 UART. This allows the Z80182/Z8L182 to be software compatible with existing modem software. D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Transmitter Holding Register Figure 70. Transmit Holding Register (PC Write Only, Address 00H, DLAB=0, R/W=Write) (Z180 MPU Read Only, Address xxF0H) Transmit Holding Register When the PC/XT/AT writes to the Transmit Holding Register, the Z80182/Z8L182 responds by setting the appropriate bit in the IP register and by generating an interrupt to the Z180 MPU if it is enabled. When the Z180 MPU reads this register the Transmit Holding Register empty flag is set (if the transmitter timer is enabled , this bit is set after the timer times out). In FIFO mode of operation, this address is used to read (Z180) and write (PC) the Transmitter FIFO. 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Receive Buffer Register FIFO Enable RCVR FIFO Reset Figure 69. Receive Buffer Register (PC Read Only, Address 00H, DLAB=0, R/W=Read) (Z180™ MPU Write Only, Address XXF0H) XMIT FIFO Reset DMA Mode Select Reserved (Tx Overrun, MPU only) Reserved (FCR Write, MPU only) RCVR Trigger (LSB) Receive Buffer Register RCVR Trigger (MSB) When the Z180 has assembled a byte of data to pass to the PC/XT/AT, it places it in the Receive Buffer Register. If the Received Data Available interrupt is enabled then an interrupt is generated for the PC/XT/AT and the Data Ready bit is set (if the Receive Timer is enabled, the interrupt and setting of the Data Ready bit is delayed until after the timer times out). Also the shadowed bits of the Line Status Register are transferred to their respective bits when the Z180 MPU writes to the Receive Buffer Register (See Line Status Register Bits 1, 2, 3 and 4). This allows a simultaneous setting of error bits when the data is written to the Receive Buffer Register. In FIFO, mode this address is used to read (PC) and write (Z180) the Receive FIFO. DS971820600 Figure 71. FIFO Control Register (PC Write Only, Address 02H) (Z180 MPU Read Only, Address xxE9H) PS009801-0301 3-69 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y 16550 MIMIC REGISTERS (Continued) FIFO Control Register Table 18. Receive Trigger Level Bit 6 and Bit 7 RCVR trigger LSB and MSB bits This 2-bit field determines the number of available bytes in the receiver FIFO before an interrupt to the PC occurs (see Table 18). Bit 4 and Bit 5 Reserved for future use (PC side). Note: From the MPU side, bit 4 and bit 5 flags two sources of interrupts. Bit 5 is a FIFO interrupt indicating that the FCR had changed; bit 4 is a Tx overrun interrupt, indicating transmit overrun. A read of the FCR from the MCU side will clear a previously set bit 4 or bit 5. Bit 3 DMA mode select Setting this bit to 1 will cause the MIMIC DMA mode to change from mode 0 to mode 1 (if bit 0 is 1, FIFO mode is enabled). This affects the DMA mode of the FIFO. A 1 in this bit enables multi-byte DMA). b7 b6 0 0 1 1 0 1 0 1 Trigger Level, Number of Bytes 1 4 8 14 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Fast Interrupt Resolution 16550/450 RCVR Overrun Figure 72. MIMIC Modification Register (Z180 MPU Write only, Address xxE9h) Bit 7-2 Reserved. Program to zero. Bit 2 XMIT FIFO Reset Setting this bit to 1 will cause the transmitter FIFO pointer logic to be reset; any data in the FIFO will be lost. This bit is self clearing; however a shadow bit exists that is cleared only when read by the Z180 MPU, allowing the MPU to monitor a FIFO reset by the PC. Bit 1 RCVR FIFO Reset Setting this bit to 1 will cause the receiver FIFO pointer logic to be reset; any data in the FIFO will be lost. This bit is self clearing, however a shadow bit exists that is cleared only when read by the Z180 MPU, allowing the MPU to monitor a FIFO reset by the PC. Bit 0 FIFO Enable The PC writes this bit to logic 1 to put the 16550 MIMIC into FIFO mode. This bit must be 1 when writing to the other bits in this register or they will not be programmed. When this bit changes state, any data in the FIFO’s or transmitter holding and Receive Buffer Registers is lost and any pending interrupts are cleared. This feature can be forced in a disabled state by the MPU. 3-70 Bit 1 RCVR Overrun Modification The actual 16450/16550 device allows the last position in FIFO to be overwritten by DCE during receiver overrun condition. When this bit is enabled (programmed to 1) the last position in FIFO can be overwritten by Z180 during receiver overrun. This feature is disabled by default. When this modification is not enabled, the MIMIC will ignore any write to RBR during an overrun condition. Bit 0 Fast MIMIC-ESCC Interrupt Resolution When enabling this modification, the internal MIMIC IEO signal into the ESCC IEI input is forced Low when the MIMIC Interrupt line becomes active. This is required to prevent the ESCC from putting it's vector on the databus during an INTACK cycle (given that the MIMIC is programmed to have higher interrupt priority). When disabled, the internal MIMIC IEO becomes deasserted only after an interrupt acknowledge cycle. In this case, it is possible for the ESCC to force it's interrupt vector onto the data bus even when the MIMIC has a pending interrupt and is higher in priority. PS009801-0301 DS971820600 Zilog Although this bit is disabled by default, it is advised that this bit is enabled to prevent interrupt conflict between MIMIC and ESCC interrupts. 0 0 0 0 0 0 Bits 3-1 Interrupt ID Bits This 3-bit field is used to determine the highest priority interrupt pending (see Table 19). Bit 0 Interrupt Pending This bit is logic 0 and interrupt is pending. D7 D6 D5 D4 D3 D2 D1 D0 0 Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y 0 0 if Interrupt Pending Interrupt ID bit (0) Interrupt ID bit (1) When the PC accesses the IIR, the contents of the register and all pending interrupts are frozen. Any new interrupts will be recorded, but not acknowledged, during the IIR access. Interrupt ID bit (2) Always '0' D7 D6 D5 D4 D3 D2 D1 D0 Always '0' 0 FIFO Enabled Flag 0 0 0 0 0 0 0 FIFO Enabled Flag Data Ready Overrun Error Parity Error Figure 73. Interrupt Identification Register (PC Read Only, Address 02H) (Z180 MPU no access) Framing Error Break Interrupt THRE TEMT Interrupt Identification Register Error in RCVR FIFO Bit 7 and Bit 6 FIFO’s Enabled These bits will read 1 if the FIFO mode is enabled on the MIMIC. Figure 74. Line Status Register (PC Read Only, Address 05H) (Z180 MPU Read/Write bits 6, 4, 3, 2, Address xxF5H) Bit 5 and Bit 4 Always Read 0 Reserved bits. Table 19. Interrupt Identification Field b3 b2 b1 Priority Interrupt Source INT Reset Control 0 1 1 Highest Overrun, Parity, Framing error or Break detect bits set by MPU Read Line Status Register 0 1 0 2nd Received Data trigger level RCVR FIFO drops below trigger level 1 1 0 2nd Receiver Timeout with data in RCVR FIFO. Read RCVR FIFO 0 0 1 3rd Transmitter Holding Register Empty. Writing to the Transmitter Holding Register or reading the Interrupt Identification Register when the THRE is the source of the interrupt. 0 0 0 4th MODEM status: CTS, DSR, RI or DCD Reading the MODEM status register. DS971820600 PS009801-0301 3-71 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y 16550 MIMIC REGISTERS (Continued) Line Status Register Bit 7 Error in RCVR FIFO In 16450 mode, this bit will read logic 0. In 16550 mode this bit is set if at least one data byte is available in the FIFO with one of its associated error bits set. This bit will clear when there are no more errors (or break detects) in the FIFO. Bit 6 Transmitter Empty This bit must be set or reset by the MPU by a write to this register bit. If Double Buffer Mode is enabled, the TEMT bit is set/reset automatically. The function of this bit is modified when TEMT/Double Buffer enhancement is selected. Refer to page 3-26 for TEMT/Double Buffer information. Bit 5 Transmit Holding Register Empty, THRE This bit is set to 1 when either the THR has been read (emptied) by the MPU (16450 mode) or the XMIT FIFO is empty (16550 mode). This bit is set to 0 when either the THR or XMIT FIFO become non-empty. A shadow bit exists so that the register bit setting to 1 is delayed by the Transmitter Timer if enabled. The MPU when reading this bit will not see the delay. Both shadow and register bits are cleared when the PC writes to the THR of XMIT FIFO. The function of this bit is modified when TEMT/Double Buffer enhancement is selected. Refer to page 3-26 for TEMT/Double Buffer information. Bit 2, 3, 4 Parity Error, Framing Error, Break Detect These bits are written, indirectly, by the MPU as follows: The bits are first written to shadow bit locations when the MPU write accesses the LSR. When the next character is written to the Receive Buffer or RCVR FIFO, the data in the shadow bits is then copied to the LSR (16450 mode) or FIFO RAM (16550 mode). In FIFO mode bits become available to the PC when the data byte associated with the bits is next to be read (top of FIFO). In FIFO mode, with successive reads of the receiver, the status bits will be set if an error occurs on any byte. Once the MPU writes to the Receive Buffer or RCVR FIFO, the shadow bits are auto cleared. The register bits are cleared upon the PC reading the LSR. In FIFO mode these bits will be set if any byte has the respective error bit set while the PC reads multiple characters from the FIFO. Bit 1 Overrun Error This bit is set if the Z180 MPU makes a second write to the Receive Buffer before the PC reads the data in the Buffer (16450 mode) or with a full RCVR FIFO (16550 mode.) No data will be transferred to the RCVR FIFO under these circumstances. This bit is reset when the PC reads the Line Status Register. 3-72 Bit 0 Data Ready This bit is set to 1 when received data is available, either in the RCVR FIFO (16550 mode) or Receive Buffer Register (16450 mode). This bit is set immediately upon the MPU writing data to the Receive Buffer or FIFO if the Receive Timer is not enabled but is delayed by the timer interval if the Receive Timer is enabled. For MPU read access a shadow bit exists so that the MPU does not see the delay the PC does. Both bits are cleared to logic zero immediately upon reading all the data in either the Receive Buffer or FIFO. D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Bit 0 Received Data Available Int. Bit 1 THRE Interrupt Bit 2 Receiver Line Status Int. Bit 3 MODEM Status Interrupt Bit 7, 6, 5, 4 Always 0 Figure 75. Interrupt Enable Register (PC Read/Write, Address 01H) (Z180 MPU Read Only, Address xxF1H) Interrupt Enable Register Bits 7, 6, 5, 4 Reserved These bits will always read 0 (PC and MPU). Bit 3 Modem Status IRQ If bits 0, 1, 2 or 3 of the Modem Status Register are set and this enable bit is a logic 1, then an interrupt to the PC is generated. Bit 2 Receive Line Status IRQ If bits 1, 2, 3 or 4 of the LSR are set and this enable bit is a logic 1, then an interrupt to the PC is generated. Bit 1 Transmit Holding Register Empty IRQ If bit 5 of the LSR is set and this enable bit is a logic 1, then an interrupt to the PC is generated. Bit 0 Received Data Available IRQ If bit 0 of the LSR is set or a Receive Timeout occurs and this enable bit is a logic 1, then an interrupt to the PC is generated. PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 Modem Control Register 0 Word Length Sel. Bit 7-5 Reserved Reserved for future use, always 0. # of Stop Bits Parity Enable Even Parity Sel. Stick Parity Bit 4 Loop When this bit is set to 1, D3-D0 field reflects the status of Modem Status Register, as follows: Set Break RI DCD DSR CTS DALB Figure 76. Line Control Register (PC Read/Write, Address 03H) (Z180 MPU Read Only, Address xxF3H) Line Control Register Bit 7 Divisor Latch Access Bit (DALB) This bit allow access to the divisor latch by the PC/XT/AT. If this bit is set to 1, access to the Transmitter, Receiver and Interrupt Enable Registers is disabled. When an access is made to address 0 the Divisor Latch Least Significant byte is accessed. If an access is made to address 1, the Divisor Latch Most Significant byte is accessed. Bit 6 - Bit 0 These bits do not affect the Z80182/Z8L182 directly, however they can be read by the Z180 MPU and the 16550 MIMIC modes can be emulated by the Z180 MPU. = = = = Out 1 Out 2 DTR RTS Emulation of the 16550 UART loop back feature must be done by the Z180 MPU, except in the above conditions. Bit 3 Out 2 This bit controls the tri-state on the HINTR pin if bits 2 and 1 are 10. Otherwise it can be read by the Z180 MPU. Bits 2, 1, 0 These bits have no direct control of the 16550 MIMIC interface and the Z180 MPU must emulate the function if it is to be implemented. D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 DCTS DDSR TERI D7 D6 D5 D4 D3 D2 D1 D0 DDCD 0 CTS 0 0 0 0 0 0 0 DSR DTR RI RTS DCD Out 1 Out 2 Loop Reserved Figure 78. Modem Status Register (PC Read Only, Address 06H) (Z180 MPU Read/Write bits 7-4, Address xxF6H) Figure 77. Modem Control Register (PC Read/Write, Address 04H) (Z180 MPU Read Only, Address xxF4H) DS971820600 PS009801-0301 3-73 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y 16550 MIMIC REGISTERS (Continued) Modem Status Register Scratch Register Bit 7 Data Carrier Detect This bit must be written by the Z180 MPU. Bits 7-0 Scratch Register This register is used by the PC/XT/AT programmer for temporary data storage. The Z180 MPU is able to read this register. If the PC/XT/AT writes to this register, no interrupt to the Z180 MPU is generated. Bit 6 Ring Indicator This bit must be written by the Z180 MPU. Bit 5 Data Set Ready This bit must be written by the Z180 MPU. D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Bit 4 Clear to Send This bit must be written by the Z180™ MPU. Divisor Latch (MS) Bit 3 Delta Data Carrier Detect This bit is set to 1 whenever the Data Carrier Detect bit changes state. This bit is reset when the PC/XT/AT reads the Modem Status Register. Bit 2 Trailing Edge Ring Indicator This bit is set to 1 on the falling edge of the Ring Indicator bit. This bit is reset when the PC/XT/AT reads the Modem Status Register. Bit 1 Delta Data Set Ready This bit is set to 1 whenever the Data Set Ready bit changes state. This bit is reset when the PC/XT/AT reads the Modem Status Register. Figure 80. Divisor Latch (LS) (PC Read/Write, Address 00H and DLAB=1) (Z180 MPU Read Only, Address xxF8H) Divisor Latch (LS) Bit 7-0 Divisor Latch Most Significant Byte (MS) This register contains the Low order byte of the Baud rate divisor. Writing to this register with the PC/XT/AT will generate an interrupt to the Z180 MPU. It can then read the Baud rate divisor and set up the application. D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 Bit 0 Delta Clear To Send This bit is set to 1 whenever the Clear To Send bit changes state. This bit is reset when the PC/XT/AT reads the Modem Status Register. 0 0 0 0 0 0 0 Divisor Latch (LS) Figure 79. Scratch Register (PC Read/Write, Address 07H) (Z180 MPU Read Only, Address xxF7H) 3-74 0 0 Scratch Register Figure 81. Divisor Latch (MS) (PC Read/Write, Address 01H and DLAB=1) (Z180 MPU Read Only, Address xxF9H) D7 D6 D5 D4 D3 D2 D1 D0 0 0 Divisor Latch (MS) Bit 7-0 Divisor Latch Most Significant Byte (MS) This register contains the High order byte of the Baud rate divisor. Writing to this register with the PC/XT/AT will generate an interrupt to the Z180 MPU. It can then read the Baud rate divisor and set up the application. PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y Z80182 ENHANCEMENTS REGISTER two. Upon power-up or reset, the ESCC clock frequency is equal to the Z180 core's PHI clock output. Bit Reserved Bit 5 Force Z180 Halt Mode If this bit is set to 1, it disables the 16 cycle halt recovery and halt control over the busses and pins. This bit is used to allow DMA and Refresh Access to take place during halt (like Z180). This bit is set to 0 on reset. Bit 4 TxDA Tri-state The TxDA pin can be tri-stated on assertion of the /HALT pin. This prevents the TxDA from driving and external device when /HALT output is used to force other devices into power-down modes. This feature is disabled on powerup or reset. It is also controlled by bit 5 in the enhancement register, this feature is disabled if bit 5 is set. Note: If operating above 20 MHz/5V or 10 MHz/3V, this bit should be set for ESCC divide-by-two mode. D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Reserved ESCC Clock Divider TxDA Tri-state Force Z180 Halt mode Reserved Bit 3 ESCC Clock Divider The ESCC clock can be provided with the Z180 core's PHI clock or by a PHI clock divide by 2 circuit. When this bit is set, the ESCC's clock will be Z180's PHI clock divided by DS971820600 Figure 82. Z80182 Enhancements Register (Z180 MPU Read/Write, Address xxD9H) PS009801-0301 3-75 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y PARALLEL PORTS REGISTERS The Z80182/Z8L182 has three 8-bit bi-directional Ports. Each bit is individually programmable for input or output. The Ports consist of two registers the Port Direction Control Register and the Port Data Register. The Port and direction register can be accessed in any page of I/O space since only the lowest eight address lines are decoded. Bits PC7 and PC6 are input only bits and have the special function of reading the external value of the /INT2 and /INT1 pins. Writing ‘1’ to these bits will clear the edge detect interrupt logic when operating /INT2 and/or /INT1 in edge detect mode. When Port B and Port C bits 5-0 are deselected in the System Configuration Register, the Data and Data Direction Registers are still available as read/write scratch registers. If a Port is deselected and if the DDR bit is a ‘0’, then the written value to that bit will be latched and this value can be read back. If a Port is deselected and if the DDR bit is a ‘1’, then you could read only the external pin value; any write to that bit is latched but can be read back only with DDR=0. data is stored in the internal buffer. The values of the PA Data Register are undefined after reset. Any bits that are output are then sent on to the output buffers. When the Z180 MPU reads the PA Data Register the data on the external pins is returned. D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 1 PB Data Direction Register 0=Output 1=Input Figure 85. PB, Port B, Data Direction Register (Z180 MPU Read/Write, Address xxE4H) The data direction register determines which are inputs and outputs in the PB Data Register. When a bit is set to 1 the corresponding bit in the PB Data Register is an input. If the bit is 0 then the corresponding bit is an output. D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 PA Data Direction Register 0=Output 1=Input X X X X X X X X X X X X Figure 86. PB, Port B, Data Register (Z180 MPU, Address xxE5H) When the Z180 MPU writes to the PB Data Register the data is stored in the internal buffer. The values of Port B data register are undefined after reset. Any bits that are output are then sent on to the output buffers. When the Z180 MPU reads the PB Data Register, the data on the external pins is returned. D7 D6 D5 D4 D3 D2 D1 D0 X X PB Data Register Figure 83. PA, Port A, Data Direction Register (Z180 MPU Read/Write, Address xxEDH) The data direction register determines which are inputs and outputs in the PA Data Register. When a bit is set to 1 the corresponding bit in the PA Data Register is an input. If the bit is 0, then the corresponding bit is an output. X X PA Data Register Figure 84. PA, Port A, Data Register (Z180 MPU Read/Write, Address xxEEH) D7 D6 D5 D4 D3 D2 D1 D0 X X 1 1 1 1 1 1 PC Direction Register When the Z180 MPU writes to the PA Data Register the 3-76 Figure 87. PC, Port C, Data Direction Register (Z180 MPU Read/Write, Address xxDDH) PS009801-0301 DS971820600 Zilog P R E L I M I N A R Y The data direction register determines which are inputs and outputs in the PC Data Register. When a bit is set to 1 the corresponding bit in the PC Data Register is an input. If the bit is 0, then the corresponding bit is an output. D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL When the Z180 MPU writes to the PC Data Register, the data is stored in the internal buffer. The values of Port C data register are undefined after reset. Any bits that are output are then sent on to the output buffers. When the Z180 MPU reads the PC Data Register, the data on the external pins is returned. PC Data Register /INT2, /INT1 Read Ext Data Write b7=1 Clears /INT2 Edge Write b6=1 Clears /INT1 Edge Figure 88. PC, Port C, Data Register (Z180 MPU Read/Write, Address xxDEH) Bits 6 and 7 serve the special function of reading the value of the external /INT2 and /INT1 lines. When operating either /INT2 or /INT1 in edge detection mode, the edge detect latch is reset by writing a 1 to bit 6 or 7 respectively. Writing a 0 has no effect. These latches should be reset at the end of an /INT1 or /INT2 interrupt service routine when using edge-triggered interrupt modes. 16550 MIMIC INTERFACE DMA The 16550 MIMIC is also able to do direct DMA with the PC/XT/AT. DMA is enabled by setting bits 3, 4 and 5 of the Master Control Register. DMA is accomplished by using the two DMA pins and the Transmitter Holding and Receive Data Registers. If bit 5 is 1, the /HTxRDY pin is equal to the complement of the Transmit Holding Register Empty bit. If bit 5 is 1 and bit 3 is 0 the external /DREQ1 pin of the Z180 MPU is disabled and the internal /DREQ1 is equal to the complement of the Transmit Holding Register Empty Shadow bit. If bit 5 is 1 and bit 3 is 1 the external /DREQ0 pin of the Z180 MPU is DS971820600 disabled and the internal /DREQ0 is equal to the complement of the Transmit Holding Register Empty Shadow bit. If bit 4 is 1, then the /HRxRDY pin is equal to the complement of the Data Ready bit. If bit 4 is 1 and bit 3 is 0 the external /DREQ0 pin of the Z180 MPU is disabled and the internal /DREQ0 is equal to the complement of the Data Ready Shadow bit. If bit 4 is 1 and bit 3 is 1 the external /DREQ1 pin of the Z180 MPU is disabled and the internal /DREQ1 is equal to the complement or the Data Ready Shadow bit. PS009801-0301 3-77 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL Z80182/Z8L182 MIMIC DMA CONSIDERATIONS For the PC Interface, the 16550 device has two modes of operation that need to be supported by the MIMIC. In single transfer mode, the DMA request line for the receiver goes active whenever there is at least one character in the RCVR FIFO. For the transmitter, the DMA request line is active on an empty XMIT FIFO and inactive on non-empty. In multi-transfer mode, the RCVR DMA goes active at the trigger level and inactive on RCVR FIFO empty. The XMIT DMA is active on non-full XMIT FIFO and inactive on a full XMIT FIFO. Bit 3 in the FCR controls the DMA mode for the PC interface. If a 1 is programmed into this bit, multi-byte DMA is enabled. A 0 in this bit (default) enables single byte DMA. As specified, the 16550 does not have any means of handling the error status bits in the FIFO in this multitransfer mode. Such DMA transfers would require blocks with some checksum or other error checking scheme. For the MPU interface, the DMA is controlled by a nonempty transmit FIFO and by a non-full receive FIFO conditions (THRE and the DR bits in the LSR). If the delay timers are enabled, the respective shadow bits are used for DMA control. The effect of the DMA logic is to request DMA service when at least one byte of data is available to be read or written to the FIFO’s by the Z180. The Z180's DMA channel can be programmed to trigger on edge or on level. EMULATION MODES The Z80182/Z8L182 provides four modes of operation. The modes are selected by the EV1 and EV2 pins. These four modes allow the system development and commercial production to be done with the same device. The four emulation modes are shown in Table 20. Table 20. EV2 and EV1, Emulation Mode Control Mode Mode Mode Mode 0 1 2 3 EV2 EV1 EV Description 0 0 1 1 0 1 0 1 Normal Mode, on-chip Z180 bus master Emulation Adapter Mode Emulator Probe Mode RESERVED, for Test Use Only Mode 0 Normal Mode This is the normal operating mode for the Z80182/Z8L182. Mode 1 Emulation Adapter Mode The Emulation Adaptor Mode enables system development for the Z182 with a readily available Z180 emulator. The Emulator provides the Z180™ MPU and Z180 peripheral functions to the target system, with their signals passing 3-78 through the emulation adapter. In Emulation Adaptor Mode the Z182s, Z180 MPU and Z180 peripheral signals are tristate or physically disconnected. The Z182 continues to provide its ESCC, MIMIC, chip select, and Port functions and signals to the target system. The Mode 1 effects on the Z182 are shown in Table 21. Note that INT1-2 Edge Detect Logic cannot be used in Emulation Adaptor EV Mode 2. PS009801-0301 DS971820600 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL EMULATION MODES (Continued) Table 21. Emulation Mode 1 Signal PHI /M1 /MREQ,/MRD /IORQ /RD /WR /RFSH /HALT ST E /BUSACK /WAIT A19,A18/TOUT A17-A0 D7-D0 TxA0 /RTS0 TxA1 /INT0 Normal Mode 0 Emulation Adaptor Mode 1 Output Output Output Output Output Output Output Output Output Output Output Input Output Output Input/Output Output Output Output Input Input Input Input Input Input Input Input Input Input Tri-state Input Output Input Input Input/Output Tri-state Tri-state Tri-state Output, Open-Drain Mode 2 Emulation Probe Mode In the Emulator Probe Mode all of the Z182 output signals are tri-state. This scheme allows a Z182 emulator probe to grab on to the Z182 package leads on the target system. Mode 3 RESERVED (for test purposes only) This mode is reserved for test purpose only, do not use. Notes: Z182 has two branches of reset. /RESET controls the Z182 overall configuration, RAM and ROM boundaries, plus the ESCC, Port and the 16550 MIMIC interface. In Normal Mode, a "one shot" circuit samples the input of the /RESET pin to assert the internal reset to its proper duration. In Adapter Mode, this "one shot" circuit is bypassed. Note also that the Z180’s crystal oscillator is disabled in Mode 1 and Mode 2. In Mode 1 the emulator must provide /MREQ on the (/MREQ,/MRD) Z80182/Z8L182 pin (not /MRD); and A18 (not TOUT) on the A18/TOUT pin. SLEEP, HALT EFFECT ON MIMIC AND 182 SIGNALS The following Z80182/Z8L182 signals are driven High when Z180™ MPU enters a SLEEP or HALT state: ■ /MRD when selected in the Interrupt Edge/Pin MUX Register. ■ /MWR when selected in the Interrupt Edge/Pin MUX Register. ■ /ROMCS,/RAMCS always High in SLEEP or HALT. The following signals are High-Z during SLEEP and HALT: ■ /IOCS when so selected in the Interrupt Edge/Pin MUX Register. ■ /RD and /WR. A0-A19 (A18 if selected) always High-Z in power down. D0-D7 always High-Z in power down modes. The MIMIC logic of the 182 is disabled during power down modes of the Z180. DS971820600 PS009801-0301 3-79 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y ABSOLUTE MAXIMUM RATINGS Voltage on V CC with respect to VSS ........... –0.3V to +7.0V Voltages on all inputs with respect to VSS ........................... –0.3V to VCC +0.3V Operating Ambient Temperature ................... 0 to +70°C Storage Temperature ............................ –55°C to +150°C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. STANDARD TEST CONDITIONS The DC Characteristics and capacitance sections below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND (0V). Positive current flows into the referenced pin (Figure 89). Available operating temperature range is: S = 0°C to +70°C +5V 2.1 kΩ From Output Under Test Voltage Supply Range: +4.50V ≤ VCC ≤ + 5.50V Z80182 +3.0V ≤ VCC ≤ + 3.60V Z8L182 100 pF All AC parameters assume a load capacitance of 100 pF. Add 10 ns delay for each 50 pF increase in load up to a maximum of 150 pF for the data bus and 100 pF for address and control lines. AC timing measurements are referenced to 1.5 volts (except for clock, which is referenced to the 10% and 90% points). Maximum capacitive load for CLK is 125 pF. 250 µA Figure 89. Test Load Diagram Note: The ESCC™ Core is only guaranteed to operate at 20 MHz 5.0 volts or 10 MHz 3.3 volts. Upon reset, the Z182 system clock is "divided by one" before clocking the ESCC. When Z182 is operated above 20 MHz 5.0 volts or 10 MHz 3.3 volts, the ESCC should be programmed to "divide-by-two" mode. 3-80 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y DC CHARACTERISTICS Z80182/Z8L182 (VCC = 5V ± 10%, VSS = 0V, over specified temperature range unless otherwise notes.) Symbol Parameter VIH1 Input H Voltage /RESET, EXTAL, NMI Input H Voltage Except /RESET, EXTAL, NMI Input L Voltage /RESET, EXTAL, NMI Input L Voltage Except /RESET, EXTAL, NMI VIH2 VIL1 VIL2 VOH1 VOH2 VOL1 VOL2 IIL ITL ICC* Output H Voltage All outputs Output H PHI Typ Max Unit VCC –0.6 VCC +0.3 V 2.0 VCC +0.3 V –0.3 0.6 V –0.3 0.8 V V 0.40 V IOL = 2.2 mA 0.40 V IOL= 2.2 mA 1.0 µA VIN = 0.5 - VCC –0.5 1.0 µA VIN = 0.5 - VCC –0.5 V Input Leakage Current All Inputs Except XTAL, EXTAL Tri-state Leakage Current Condition IOH = –200 µA IOH = –200 µA IOH = –200 µA 2.4 VCC –1.2 VCC –0.6 Output L Voltage All outputs Output L PHI Power Dissipation* (Normal Operation) Power Dissipation* (SLEEP) Power Dissipation* (I/O STOP) Power Dissipation* (SYSTEM STOP mode) 60 100 TBD TBD TBD TBD 5 9 120 200 TBD TBD TBD TBD 10 17 mA mA mA mA mA mA mA mA f = 20 MHz f = 33 MHz f= 20 MHz f= 33 MHz f= 20 MHz f= 33 MHz f = 20 MHz f = 33 MHz IDLE Mode TBD TBD 50 TBD TBD mA mA µA f = 20 MHz f = 33 MHz f = 0 MHz † 12 pF VIN = 0V, f = 1 MHz TA = 25°C STANDBY Mode Cp Min Pin Capacitance Notes: These I CC values are preliminary and subject to change without notice. * VIH Min = VCC -1.0V, VIL Max = 0.8V (all output terminals are at no load) VCC = 5.0V; (IOH Low EMI) = -50 µA, IOL (Low EMI) = 500 µA † Device may take up to two seconds before stabilizing to steady state standby current. DS971820600 PS009801-0301 3-81 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y DC CHARACTERISTICS Z80182/Z8L182 (VCC = 3.3V ± 10%, VSS = 0V, over specified temperature range unless otherwise notes.) Symbol Parameter VIH1 Input H Voltage /RESET, EXTAL, NMI Input H Voltage Except /RESET, EXTAL, NMI VIH2 VIL1 VIL2 VOH1 VOH2 VOL1 VOL2 IIL ITL ICC* Max Unit VCC –0.6 VCC +0.3 V 2.0 VCC +0.3 V Input L Voltage /RESET, EXTAL, NMI Input L Voltage Except /RESET, EXTAL, NMI –0.3 0.6 V –0.3 0.8 V Output H Voltage All outputs Output H PHI 2.15 V IOH = –200 µA VCC –0.6 V IOH= –200 µA Typ 0.40 V IOL = 2.2 mA 0.40 V IOL= 2.2 mA 10 µA VIN = 0.5 - VCC –0.5 10 µA VIN = 0.5 - VCC –0.5 40 80 mA f = 20 MHz TBD TBD mA f= 20 MHz TBD TBD mA f= 20 MHz 4 8 mA f = 20 MHz TBD 50 TBD mA µA f = 20 MHz f = 0 MHz † 12 pF VIN = 0V, f = 1 MHz TA = 25°C Output L Voltage All outputs Output L PHI Input Leakage Current All Inputs Except XTAL, EXTAL Tri-state Leakage Current Power Dissipation* (Normal Operation) Power Dissipation* (SLEEP) Power Dissipation* (I/O STOP) Power Dissipation* (SYSTEM STOP mode) IDLE Mode STANDBY Mode Cp Min Pin Capacitance Condition Notes: These I CC values are preliminary and subject to change without notice. * VIH Min = VCC -1.0V, VIL Max = 0.8V (all output terminals are at no load) VCC = 3.3V † Device may take up to two seconds before stabilizing to steady state current. 3-82 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y TIMING DIAGRAMS Z180 MPU Timing Opcode Fetch Cycle T1 T2 TW T3 I/O Write Cycle † I/O Read Cycle † T2 TW T1 T3 T1 5 4 2 3 ø 1 6 Address 20 20 19 19 /WAIT 11 12 7 /MREQ 7 29 11 8 /IORQ 11 13 28 13 /RD 9 11 9 22 25 26 and 26a /WR 14 /M1 10 18 ST 16 17 15 16 21 15 Data IN 27 23 24 Data OUT 63 63 62 62 /RESET 68 67 67 68 Figure 90. CPU Timing (Opcode Fetch Cycle, Memory Read/Write Cycle I/O Read/Write Cycle) DS971820600 PS009801-0301 3-83 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y TIMING DIAGRAMS (Continued) Ø 32 31 /INTI 33 /NMI C7 /INTSCC [4] /M1 [1] 29 /IORQ [1] 16 15 /Data IN [1] 39 /MREQ [2] 41 40 43 /RFSH [2] 35 35 34 34 /BUSREQ 36 37 /BUSACK 38 38 Address Data /MREQ, /RD, /WR, /IORQ 43 [3] 44 /HALT Notes: [1] During /INT0 acknowledge cycle [2] During refresh cycle [3] Output buffer is off at this point [4] Refer to Table C, parameter 7 Figure 91. CPU Timing (/INT0 Acknowledge Cycle, Refresh Cycle, BUS RELEASE Mode HALT Mode, SLEEP Mode, SYSTEM STOP Mode) 3-84 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y I/O Read Cycle T1 T2 I/O Write Cycle TW T3 T1 T2 TW T3 0 Address 28 29 9 13 28 29 /IROQ /RD 22 25 /WR Figure 92. CPU Timing CPU or DMA Read/Write Cycle (Only DMA Write Cycle for /TENDi) T1 T2 Tw T3 T1 Ø 45 46 [1] /DREQi (At level sense) 45 45 [2] /DREQi (At edge sence) 18 [4] 47 48 /TENDi [3] 17 ST DMA Control Signals tDRQS and tDRQH are specified for the rising edge of clock followed by T3. [2] tDRQS and tDRQH are specified for the rising edge of clock. [3] DMA cycle starts. [4] CPU cycle starts. [1] Figure 93. DMA Control Signals DS971820600 PS009801-0301 3-85 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y TIMING DIAGRAMS (Continued) T1 T2 Tw Tw T3 Ø 49 50 49 50 49 50 15 16 D7-D0 Figure 94. E Clock Timing (Memory Read/Write Cycle I/O Read/Write Cycle) Ø 49 50 BUS RELEASE Mode E SLEEP Mode SYSTEM STOP Mode Figure 95. E Clock Timing 3-86 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y T2 Tw T3 T1 T2 Ø 50 49 52 E (Example: I/O Read Opcode Fetch) 50 49 54 53 51 E (I/O Write) 53 54 Figure 96. E Clock Timing (Minimum timing example of PWEL and PWEH) Ø Timer Data Reg = 0000H A18/TOUT 55 Figure 97. Timer Output Timing DS971820600 PS009801-0301 3-87 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y TIMING DIAGRAMS (Continued) SLP Instruction Fetch T3 Next Opcode Fetch T1 T2 TS TS T1 T2 Ø 32 31 /INTi /NMI 33 A18-A0 /MREQ, /M1 /RD 43 44 /HALT Figure 98. SLEEP Execution Cycle 3-88 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y CSI/O Clock 56 56 Transmit Data (Internal Clock) 57 57 11 tcyc 11 tcyc Transmit Data (External Clock) 58 59 58 59 Receive Data (Internal Clock) 11.5 tcyc 11.5 tcyc 16.5 tcyc 16.5 tcyc Receive Data (External Clock) 60 61 60 61 Figure 99. CSI/O Receive/Transmit Timing /MREQ 71 72 72 73 /RAMCS /ROMCS /IORQ /IOCS Figure 100 /ROMCS and /RAMCS Timing DS971820600 PS009801-0301 3-89 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y TIMING DIAGRAMS (Continued) T1 T2 TW T3 T1 0 Address Valid Address 7 8 11 /MREQ 9 13 /RD 24 /WR 22 7 13 11 /MRD 9 7 24 /MWR 11 22 Figure 101. /MWR and /MRD Timing 65 EXTAL VIL1 VIH1 66 VIH1 69 VIL1 Figure 102. External Clock Rise Time and Fall Time 3-90 70 Figure 103. Input Rise and Fall Time (Except EXTAL, /RESET) PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y Z8S180 AC CHARACTERISTICS Table A. Z8L180 and Z8S180 Timings Z8L180 20 MHz Min Max Z8S180 33 MHz Min Max 50 15 15 30 10 10 No. Sym Parameter 1 2 3 4 5 tcyc tCHW tCLW tcf tcr Clock Cycle Time Clock Pulse Width (High) Clock Pulse Width (Low) Clock Fall Time Clock Rise Time 6 7 8 9 tAD tAS tMED1 tRDD1 10 tM1D1 Address Valid from Clock Rise Address Valid to /MREQ, /IORQ, /MRD Fall Clock Fall to /MREQ Fall Delay Clock Fall to /RD, /MRD (/IOC=1) Clock Rise to /RD, /MRD Fall (/IOC=0) Clock Rise to /M1 Fall delay 11 12 13 14 15 tAH tMED2 tRDD2 tM1D2 tDRS Address Hold time (/MREQ, /IORQ, /RD, /WR/MRD) Clock Fall to /MREQ Rise Delay Clock Fall to /RD, /MRD Rise Delay Clock Rise to /M1 Rise Delay Data Read Setup Time 5 16 17 18 19 20 tDRH tSTD1 tSTD2 tWS tWH Data Read Hold Time Clock Edge to ST Fall Clock Edge to ST Rise /WAIT Setup Time to Clock Fall /WAIT Hold Time from Clock Fall 0 21 22 23 24 25 tWDZ tWRD1 tWDD tWDS tWRD2 Clock Rise to Data Float Delay Clock Rise to /WR,/MWR Fall Delay Clock Fall to Write Data Delay Write Data Setup Time to /WR,/MWR Fall Clock Fall to /WR Rise 26 26a 27 28 tWRP 75 130 10 29 tIOD2 /WR Pulse Width (Memory Write Cycles) /WR Pulse Width (I/O Write Cycles) Write Data Hold Time from /WR Rise Clock Fall to /IORQ Fall Delay (/IOC=1) Clock Rise to /IORQ Fall Delay (/IOC=0) Clock Fall /IOQR Rise Delay 30 31 32 33 34 tIOD3 tINTS tINTH tNMIW tBRS /M1 Fall to /IORQ Fall Delay /INT Setup Time to Clock Fall /INT Hold Time from Clock Fall /NMI Pulse Width /BUSREQ Setup Time to Clock Fall 100 20 10 35 10 35 36 37 38 39 40 tBRH tBAD1 tBAD2 tBZD tMEWH tMEWL /BUSREQ Hold Time from Clock Fall Clock Rise to /BUSACK Fall Delay Clock Fall to /BUSACK Rise Delay Clock Rise to Bus Floating Delay Time /MREQ Pulse Width (High) /MREQ Pulse Width (Low) 10 tWDH tIOD1 DS971820600 2000 10 10 5 5 15 5 15 5 15 25 35 35 10 15 15 15 5 25 25 40 15 15 15 15 15 0 30 30 15 10 15 15 10 5 35 25 25 10 20 15 15 PS009801-0301 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 15 15 [2] ns ns ns ns ns 10 15 15 30 25 25 [1] [1] [1] [1] [1] ns ns ns ns ns ns 80 15 10 25 10 25 25 40 ns ns ns ns ns 15 45 70 5 25 25 25 Note ns ns ns ns ns 10 25 35 35 2000 Unit ns ns ns ns ns ns 3-91 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y Z8S180 AC CHARACTERISTICS (Continued) Z8L180 20 MHz Min Max No. Sym Parameter 41 42 43 44 45 tRFD1 tRFD2 tHAD1 tHAD2 tDRQS Clock Rise to /RFSH Fall Delay Clock Rise to /RFSH Rise Delay Clock Rise to /HALT Fall Delay Clock Rise to /HALT Rise Delay /DREQi Setup Time to Clock Rise 46 47 48 49 50 tDRQH tTED1 tTED2 tED1 tED2 /DREQi Hold Time from Clock Rise Clock Fall to /TENDi Fall Delay Clock Fall to /TENDi Rise Delay Clock Rise to E Rise Delay Clock Edge to E Fall Delay 20 51 52 53 54 55 PWEH PWEL tEr tEf tTOD E Pulse Width (High) E Pulse Width (Low) Enable Rise Time Enable Fall Time Clock Fall to Timer Output Delay 25 50 56 tSTDI 57 tSTDE 58 tSRSI 59 tSRHI 60 tSRSE 61 tSRHE 62 63 64 65 tRES tREH tOSC tEXr /RESET Setup time to Clock Fall /RESET Hold time from Clock Fall Oscillator Stabilization Time External Clock Rise Time (EXTAL) 66 67 68 69 70 71 72 tEXf tRr tRf tIr tIf TdCS TdIOCS External Clock Fall Time (EXTAL) /RESET Rise Time /RESET Fall Time Input Rise Time (Except EXTAL, /RESET) Input Fall Time (Except EXTAL, /RESET) /MREQ Valid to /ROMCS, /RAMCS Valid Delay /IORQ Valid to /IOCS Valid Delay Z8S180 33 MHz Min Max 20 20 15 15 20 15 15 15 15 15 15 Unit ns ns ns ns ns 15 15 15 15 ns ns ns ns ns 10 10 75 10 10 50 ns ns ns ns ns CSI/O Tx Data Delay Time (Internal Clock Operation) CSI/O Tx Data Delay Time (External Clock Operation) CSI/O Rx Data Setup Time (Internal Clock Operation) 75 60 ns 7.5 tcyc+100 7.5 tcyc+100 ns 1 1 tcyc CSI/O Rx Data Hold Time (Internal Clock Operation) CSI/O Rx Data Setup Time (External Clock Operation) CSI/O Rx Data Hold Time (External Clock Operation) 1 1 tcyc 1 1 tcyc 1 1 tcyc 25 15 25 25 30 30 20 40 40 25 Note 20 10 20 5 ns ns ms ns 10 50 50 50 50 15 15 5 50 50 50 50 10 10 ns ms ms ns ns ns ns [2] [2] [2] [2] Notes: These AC parameters values are preliminary and subject to change without notice. [1] All specifications reflect 100% output drive (disabled slew rate limiting feature). [2] Specification 1 through 5 refer to PHI clock output. [3] Exceeds characterization (data propagation delay needs to be analyzed). 3-92 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y ESCC Timing Ø /WR /RD 1 /W//REQ Wait 2 /W//REQ Request 3 4 /DTR//REQ Request 5 /INT 6 Figure 104. ESCC AC Parameter Table B. ESCC Timing Parameters No. Symbol Parameter 1 2 3 TdWR(W) TdRD(W) TdWRf(REQ) /WR Fall to Wait Valid Delay /RD Fall to Wait Valid Delay /WR Fall to /W//REQ Not Valid Delay 4 TdRDf(REQ) 5 TdRdr(REQ) 6 TdPC(INT) DS971820600 /RD Fall to /W//REQ Not Valid Delay /RD Rise to /DTR//REQ Not Valid Delay Clock to /INT Valid Delay PS009801-0301 Min 20 MHz Max 50 50 Unit ns 65 65 TBD 160 3-93 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y AC CHARACTERISTICS (Continued) Z85230 General Timing Diagram PCLK 1 /W//REQ Request 2 /W//REQ Wait 3 /RTxC, /TRxC Receive 4 5 6 7 RxD 8 9 /SYNC External 10 /TRxC, /RTxC Transmit 11 12 TxD 13 /TRxC Output 14 15 /RTxC 16 17 /TRxC 18 19 20 /CTS, /DCD 21 21 22 22 /SYNC Input Figure 105. General Timing Diagram 3-94 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y Table C. Z85230 General Timing Table Min 20 MHz Max No. Symbol Parameter Notes 1 2 3 4 TdPC(REQ) TdPC(W) TsRxC(PC) TsRxD(RxCr) /PCLK to W/REQ Valid /PCLK to Wait Inactive /RxC to /PCLK Setup Time RxD to /RxC Setup Time 5 6 7 8 ThRxD(RxCr) TsRxD(RxCf) ThRxD(RxCf) TsSY(RxC) RxD to /RxC Hold Time RxD to /RxC Setup Time RxD to /RxC Hold Time /SYNC to /RxC Setup Time 45 0 45 –90 [1] [1,5] [1,5] [1] 9 10 11 12 ThSY(RXC) TsTxC(PC) TdTxCf(TXD) TdTxCr(TXD) /SYNC to/RxC Hold Time /TxC to /PCLK Setup Time /TxC to TxD Delay /TxC to TxD Delay 5TcPc N/A [1] [2,4] [2] [2,5] 13 14 15 16a TdTxD(TRX) TwRTxh TwRTxI TcRTx TxD to TRxC Delay RTxC High Width TRxC Low Width RTxC Cycle Time 70 70 200 16b 17 18 19 TxRx(DPLL) TcRTxx TwTRxh TwTRxl DPLL Cycle Time Min Crystal Osc. Period TRxC High Width TRxC Low Width 50 61 70 70 20 21 22 TcTRx TwExT TwSY TRxC Cycle Time DCD or CTS Pulse Width SYNC Pulse Width 200 60 60 70 170 N/A 0 70 70 [1,4] [1] 70 [6] [6] [6,7] 1000 [7,8] [3] [6] [6] [6,7] Notes: These AC parameter values are preliminary and subject to change without notice. [1] RxC is /RTxC or /TRxC, whichever is supplying the receive clock. [2] TxC is /TRxC or /RTxC, whichever is supplying the transmit clock. [3] Both /RTxC and /SYNC have 30 pF capacitors to ground connected to them. [4] Synchronization of RxC to PCLK is eliminated in divide by four operation. [5] Parameter applies only to FM encoding/decoding. [6] Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to case PCLK requirements. [7] The maximum receive or transmit data rate is 1/4 PCLK. [8] Applies to DPLL clock source only. Maximum data rate of 1/4 PCLK still applies. DPLL clock should have a 50% duty cycle. DS971820600 PS009801-0301 3-95 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL AC CHARACTERISTICS (Continued) Z85230 System Timing Diagram /RTxC, /TRxC Receive /W/REQ Request 1 /W/REQ Wait 2 /SYNC Output 3 /INT 4 /RTxC, /TRxC Transmit /W//REQ Request 5 /W//REQ Wait 6 /DTR//REQ Request 7 /INT 8 /CTS, /DCD /SYNC Input 9 /INT 10 Figure 106. Z85230 System Timing 3-96 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y Table D. Z85230 System Timing Table No. Symbol Parameter 20 MHz Min Max 1 2 3 4 5 TdRxC(REQ) TdRxC(W) TdRxC(SY) TdRxC(INT) TdTxC(REQ) /RxC to /W//REQ Valid /RxC to /Wait Inactive /RxC to /SYNC Valid /RxC to /INT Valid /TxC to /W//REQ Valid 13 13 9 15 8 18 18 13 22 12 [2] [1,2] [2] [1,2] [3] 6 7 8 9 10 TdTxC(W) TdTxC(DRQ) TdTxC(INT) TdSY(INT) TdExT(INT) /TxC to /Wait Inactive /TxC to /DTR//REQ Valid /TxC to /INT Valid /SYNC to /INT Valid /DCD or /CTS to /INT Valid 8 7 9 2 3 15 11 14 6 9 [1,3] [3] [1,3] [1] [1] Notes [4] Notes: These AC parameters values are preliminary and subject to change without notice. [1] Open-drain output, measured with open-drain test load. [2] /RxC is /RTxC or /TRxC, whichever is supplying the receive clock. [3] /TxC is /TRxC or /RTxC, whichever is supplying the transmit clock. [4] Units equal to TcPc Table E. I/O Port Timing No. Symbol Parameter 1 2 3 4 TsPIA(RD) ThPIA(RD) TdWRF(PIA) TFWRF(PIA) Port Data Input Setup to /RD Fall Port Data Input Hold From /RD Rise Port Data Output Delay From /WR Fall Port Data Output Float From /WR Fall Z8L182 20 MHz Min Max 20 0 Z80182 33 MHz Min Max 20 0 60 0 60 0 Table F. External Bus Master Timing Z8L182 20 MHz Min Max No. Symbol Parameter 1 2 3 4 TsA(IORQf) TsIOf(WRf) TsIOf(RDf) ThIOR(WRR) Address to /IORQ Fall Setup /IORQ Fall to /WR Fall Setup /IORQ Fall to /RD Fall Setup /IORQ Rise From /WR Rise Hold 10 0 0 0 5 6 7 8 9 ThIOR(RDR) TdRDf(DO) THRDR (DO) TSD(WR R) THD(WRR) /IORQ Rise From /RD Rise Hold /RD Fall to Data Out Valid Delay /RD Rise to Data Out Valid Hold Data In to /WR Fall Setup Data In From /WR Rise Hold 0 DS971820600 PS009801-0301 Z80182 33 MHz Min Max 5 0 0 0 0 50 0 50 10 8 45 0 50 10 3-97 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y General-Purpose I/O Port Timing This figure shows the timing for the Ports A, B and C. Parameters referred to in this figure appear in Tables D and E. I/O Port Timing (Output) T1 TW T2 T3 T1 TW T2 T3 T1 TW T2 T3 0 Port Data Dir. Reg. Addr. (Input) Port Data Reg. Addr. (Input) Port Data Reg. Addr. (Input) A0-A7 F1 F1 F1 F4 /IORQ F4 F4 Port Output Data 1 (In) (In) 'OO'H (Change Port To Output) Port Output Data 2 (In) D0-D7 F9 F8 F9 F8 F8 F2 F2 F2 /WR E3 E3 E3 Port Output Data 1 (Out) Port (Output) Port Output Data 2 (Out) Port I/O Port Timing (Input) Port Data Reg. Addr. (Input) Port Data Dir. Reg. Addr. (Input) Port Data Reg. A0-A7 F4 F5 F5 /IORQ (In) 'FF'H (Change Port To Input) Port Data 1 (Out) Port Data 2 Out D0-D7 /WR F3 F3 F6 F6 E2 /RD E4 Previous Output E1 E2 Port Input Data 1 (In) E1 Port Input Data 2 (In) Port Figure 107. PORT Timing 3-98 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y Read Write External Bus Master Timing Address A7-A0 /IORQ F1 /RD F5 F3 F6 F7 Data Data Out F2 F4 /WR F8 F9 Data Data In Figure 108. Read/Write External Bus Master Timing DS971820600 PS009801-0301 3-99 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y ESCC External Bus Master Timing Valid ESCC Addr * IORQ 1 /RD or /WR 2 DTR/REQ Request Figure 109. ESCC External Bus Master Timing Table G. External Bus Master Interface Timing (SCC Related Timing) Z8L182 20 MHz Min Max No. Symbol Parameter 1 2 TrC TdRDr(REQ) Valid Access Recovery Time /RD Rise to /DTR//REQ Not Valid Delay 4TcC 4TcC Z80182 33 MHz Min Max 4TcC 4TcC Units Notes ns ns [1] Notes: These AC parameter values are preliminary and are subject to change without notice. [1] Applies only between transactions involving the ESCC. TCC = ESCC clock period time 3-100 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y 16550 MIMIC TIMING Refer to Figures 106 thru 112 for MIMIC AC Timing. HA2, HA1, HA0 Valid /HCS /HRD 1 2 /HWR 3 4 5 6 Figure 110. PC Host /RD /WR Timing Table H. PC Host /RD /WR Timing No Symbol Parameter Z8L182 20 MHz Min Max 1 2 3 4 5 6 tAR tCSR tAW tCSW tAh tCSh /HRD Delay from Address /HRD Delay from /HCS /HWR Delay from Address /HWR Delay from /HCS Address Hold Time /HCS Hold Time 30 30 30 30 20 20 Z80182 33 MHz Min Max 30 30 30 30 20 20 Units ns ns ns ns ns ns Note: These AC parameter values are preliminary and are subject to change without notice. DS971820600 PS009801-0301 3-101 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y 16550 MIMIC TIMING (Continued) HD7-HD0 Valid /HWR 7 8 9 Figure 111. Data Setup and Hold, Output Delay, Write Cycle HD7-HD0 Valid /HRD 11 10 12 Figure 112. Data Setup and Hold, Output Delay, Read Cycle Table I. Data Setup and Hold, Output Delay, Read Cycle Z8L182 20 MHz No. Sym Parameter Min 7 8 9 tDs tDh tWc Data Setup Time Data Hold Time Write Cycle Delay 30 30 2.5 MPU Clock Cycles 10 11 12 tRvD tHz tRc Delay from /HRD to Data /HRD to Floating Delay Read Cycle Delay Z80182 33 MHz Max Min Max 30 30 2.5 MPU Clock Cycles 125 100 125 ns ns ns 125 100 125 Units ns ns ns Note: These AC parameter values are preliminary and are subject to change without notice. 3-102 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y /HRD /HDDIS 13 Figure 113. Driver Enable Timing Table J. Driver Enable Timing Z8L182 20 MHz Min Max No. Sym Parameter 13 tRDD /HRD to Driver Enable/Disable Z80182 33 MHz Min Max 60 60 Units ns Note: These AC parameter values are preliminary and are subject to change without notice. /WR (MPU) RBR 14 HINTR (Trigger Level) 14 HINTR (Line Status RDR /HRD LSR 15 /HRD RBR 15 Figure 114. Interrupt Timing RCVR FIFO DS971820600 PS009801-0301 3-103 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y 16550 MIMIC TIMING (Continued) Table K. Interrupt Timing RCVR FIFO Z8L182 20 MHz Min Max Z80182 33 MHz Min Max No. Sym Parameter 14 tSINT Delay from Stop to Set Interrupt 2 MPU Clock Cycles 2 MPU Clock Cycles 15 tRINT Delay from /HRD (RD RBR or RD LSR) to Reset Interrupt 2 MPU Clock Cycles 2 MPU Clock Cycles Note: These AC parameter values are preliminary and are subject to change without notice. /RD (MPU) TxFIFO 17 HINTR THRE 16 /WR (Host) THR 18 /RD (Host) 11R Figure 115. Interrupt Timing Transmitter FIFO 3-104 PS009801-0301 DS971820600 Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y Table L. Interrupt Timing Transmitter FIFO Z8L182 20 MHz No. Sym Parameter Min 16 tHR Delay from /WR (WR THR) to Reset Interrupt 17 TSTI Delay from Stop to Interrupt (THRE) 18 TIR Delay from /RD (RD IIR) to Reset Interrupt (THRIE) Max Z80182 33 MHz Min Max 2.5 MPU Clock Cycles 2 MPU Clock Cycles 2.5 MPU Clock Cycles 2 MPU Clock Cycles 75 75 /HRD RD_RBR /WR (MPU) RCVR FIFO (First Byte that reaches Trigger Level) 19 /HRXRDY 14 /HWR (Host) THR RD (MPU) THR (Last Byte Model) 20 21 /HTxRDY Note: If FCR0-1 TSINT=3 CPU Clock Cycles Figure 116 RCVR FIFO Bytes Other Than First DS971820600 PS009801-0301 3-105 Zilog Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL P R E L I M I N A R Y 16550 MIMIC TIMING (Continued) Table M. RCVR FIFO Bytes Other Than First No Sym Parameter 19 tRXi 20 TWxi 21 tSXa Delay from /HRD RBR to /HRxRDY Inactive Delay from Write to /HTxRDY Inactive Delay From Start to /HTxRDY Active Z8L182 20 MHz Min Max Z80182 33 MHz Min Max 290 290 125 125 3 MPU Clock Cycles 3 MPU Clock Cycles Units ns Note: These AC parameter values are preliminary and are subject to change without notice. Clock Generator The Z80182/Z8L182 ZIP™ uses the Z182 MPUs on-chip clock generator to supply system clock. The required clock is easily generated by connection a crystal to the external terminals (XTAL,EXTAL). The clock output runs at half the crystal frequency for X2 mode. Recommended characteristics of the crystal and the values for the capacitor are as follows (the values will change with crystal frequency). Type of crystal: Fundamental, parallel type crystal (AT cut is recommended). RS, equivalent-series resistance: ≤ 60 Ohms CIN=COUT=15~22 pF. For PHI > 15 MHz (X2 Mode), it is recommended that an oscillator be used as input to EXTAL. C1 XTAL Crystal Inputs C2 EXTAL Frequency tolerance: Application dependent. CL, Load capacitance: Approximately 22 pF (acceptable range is 20-30 pF). 3-106 Figure 117. Circuit Configuration For Crystal PS009801-0301 DS971820600 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL PACKAGE INFORMATION 100-Pin VQFP Package Diagram DS971820600 PS009801-0301 3-107 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL PACKAGE INFORMATION (Continued) 100-Pin QFP Package Diagram 3-108 PS009801-0301 DS971820600 Zilog P R E L I M I N A R Y Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL ORDERING INFORMATION Z8L182 Z80182 20 MHz Z8L18220ASC Z8L18220FSC 33 MHz Z8018233ASC Z8018233FSC For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired. Preferred Package A = VQFP (Very Small QFP) F = Plastic Quad Flatpack Preferred Temperature S = 0°C to +70°C Speeds 20 = 20 MHz 33 = 33 MHZ Environmental C = Plastic Standard D = Plastic Stressed E = Hermetric Standard Example: Z 80182 20 F S C is a Z80182, 20 MHz, QFP, 0°C to +70°C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. DS971820600 Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com PS009801-0301 3-109