U6264AS1A07

U6264ASA07 Automotive 8K x 8 SRAM Features Description The U6264ASA07 is a static RAM manufactured using a CMOS process technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6-transistor cell. The circuit is activated by the rising edge of E2 (at E1 = L), or the falling edge of E1 (at E2 = H). The address and control inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. During the active state (E1 = L and E2 = H), each address change leads to a new Read or Write cycle. In a Read cycle, the data outputs are activated by the falling edge of G, afterwards the data word read will be available at the outputs DQ0 - DQ7. After the address change, the data outputs go High-Z until the new read information is available. The full CMOS data outputs have no preferred state. If the memory is driven by CMOS levels in the active state, and if there is no change of the address, data input and control signals W or G, the operating current (at IO = 0 mA) drops to the value of the operating current in the Standby mode. The Read cycle is finished by the falling edge of E2 or W, or by the rising edge of E1, respectively. Data retention is guaranteed down to 2 V. With the exception of E2, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. This gate circuit allows to achieve low power standby requirements by activation with TTL-levels too. If the circuit is inactivated by E2 = L, the standby current (TTL) drops to 150 µA typ. F 8192 x 8 bit static CMOS RAM F 70 ns Access Time F Common data inputs and outputs F Three-state outputs F Typ. operating supply current: 30 mA F TTL/CMOS-compatible F Automatic reduction of power F F F F F F dissipation in long Read or Write cycles Power supply voltage 5 V Operating temperature ranges -40 to 125 °C Quality assessment according to CECC 90000, CECC 90100 and CECC 90111 ESD protection > 2000 V (MIL STD 883C M3015.7) Latch-up immunity > 100 mA Packages: SOP28 (300 mil) SOP28 (330 mil) Pin Configuration n.c. A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 VCC W (WE) E2 (CE2) A8 A9 A11 G (OE) A10 E1 (CE1) DQ7 DQ6 DQ5 DQ4 DQ3 Pin Description Signal Name A0 - A12 DQ0 - DQ7 E1 E2 G W VCC VSS n.c. Signal Description Address Inputs Data In/Outputs Chip Enable 1 Chip Enable 2 Output Enable Read/Write Enable Power Supply Voltage Ground not connected SOP 22 21 20 19 18 17 16 15 Top View December 12, 1997 1 U6264ASA07 Block Diagram A4 A5 A6 A7 A8 A9 A11 A12 A0 A1 A2 A3 A10 Row Address Inputs Row Decoder Memory Cell Array 256 Rows x 256 Columns Column Address Inputs Column Decoder DQ0 Common Data I/O Sense Amplifier/ Write Control Logic DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC VSS W G Address Change Detector Clock Generator E2 E1 1 Truth Table Operating Mode Standby/not selected Internal Read Read Write * H or L E1 * H L L L E2 L * H H H W * * H H L G * * H L * DQ0 - DQ7 High-Z High-Z High-Z Data Outputs, Low-Z Data Inputs, High-Z Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI , as well as input levels of V IL = 0 V a nd VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the t dis -times, in which cases transition is measured ± 200 mV from steady-state voltage. Maximum Ratings Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VCC VI VO PD Ta Tstg Min. -0.3 -0.3 -0.3 Max. 7 VCC + 0.5 VCC + 0.5 1 Unit V V V W °C °C -40 -65 125 150 2 December 12, 1997 U6264ASA07 Recommended Operating Conditions Power Supply Voltage Data Retention Voltage Input Low Voltage* Input High Voltage * -2 V at Pulse Width 10 ns Symbol VCC V CC(DR) VIL VIH Conditions Min. 4.5 2.0 -0.3 2.2 Max. 5.5 Unit V V V V 0.8 VCC+0.3 Electrical Characteristics Supply Current - Operating Mode Symbol ICC(OP) VCC VIL VIH tcW Conditions = = = = 5.5 V 0.8 V 2.2 V 70 ns Min. Max. 55 Unit mA Supply Current - Standby Mode (TTL level) Output High Voltage TTL compatible CMOS compatible Output Low Voltage Output High Current Output Low Current Supply Current - Standby Mode (CMOS level) ICC(SB)1 VCC VE1 = VE2 or VE2 VCC IOH = 5.5 V = 2.2 V = 0.8 V = 4.5 V = -1.0 mA 2.4 0.85*VCC 3 mA VOH VOH VOL IOH IOL ICC(SB) VCC IOL VCC VOH VCC VOL = 4.5 V = 3.2 mA = = = = 4.5 2.4 4.5 0.4 V V V V 0.4 -1 30 V V V mA mA µA 3.2 VCC = 5.5 V VE1 = VE2 = VCC - 0.2 V = 0.2 V or VE2 VCC(DR) VE1 = VE2 or VE2 VCC VIH VCC VIL VCC VOH VCC VOL = 3V = VCC(DR) 0.2 V = 0.2 V = 5.5 V = 5.5 V = 5.5 V = 0V = 5.5 V = 5.5 V = 5.5 V = 0V -2 Supply Current - Data Retention Mode ICC(DR) 10 µA Input High Leakage Current Input Low Leakage Current Output Leakage Current High at Three-State Outputs Low at Three-State Outputs IIH IIL 2 - µA µA IOHZ IOLZ -2 2 - µA µA December 12, 1997 3 U6264ASA07 Symbol Switching Characteristics Alt. Time to Output in Low-Z Cycle Time Write Cycle Time Read Cycle Time Access Time E1 L OW or E2 HIGH to Data Valid G L OW to Data Valid Address to Data Valid Pulse Widths Write Pulse Width Chip Enable to End of Write Setup Times Address Setup Time Chip Enable to End of Write Write Pulse Width Data Setup Time Data Hold Time Address Hold from End of Write Output Hold Time from Address Change E1 HIGH or E2 LOW to Output in High-Z W L OW to Output in High-Z G HIGH to Output in High-Z tLZ tWC tRC tACE tOE tAA tWP tCW tAS tCW tWP tDS tDH tAH tOH tHZCE tHZWE tHZOE IEC tt(QX) tcW tcR ta(E) ta(G) ta(A) tw(W) tw(E) tsu(A) tsu(E) tsu(W) tsu(D) th(D) th(A) tv(A) tdis(E) tdis(W) tdis(G) 5 10 ns Min. Max. Unit 70 70 50 65 70 40 70 - ns ns ns ns ns ns ns 0 65 50 35 0 0 5 - ns ns ns ns ns ns ns 0 0 0 25 30 25 ns ns ns Data Retention Mode E1-Controlled VCC 4.5 V VCC(DR) ≥ 2 V 2.2 V tDR 0V Data Retention trec 2.2 V E1 0V Data Retention Mode E2-Controlled VCC VCC(DR) ≥ 2 V tDR 0.8 V Data Retention VE2(DR) ≤ 0 .2 V trec 0.8 V 4.5 V E2 VE2(DR) ≥ VCC(DR) - 0.2 V or VE2(DR) ≤ 0.2 V V CC(DR) - 0 .2 V ≤ VE1(DR) ≤ VCC(DR) + 0.3 V Chip Deselect to Data Retention Time Operating Recovery Time tDR: trec: min 0 ns min tcR 4 December 12, 1997 U6264ASA07 Test Configuration for Functional Check (for TTL output levels) 5V A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 VCC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Input level according to the relevant test measurement VIH VIL Simultaneous measurement of all 8 output pins 960 VO E1 E2 W G 30 pF1) 510 VSS 1) In measurement of tdis(E), tdis(W), tdis(G) the capacitance is 5 pF. Capacitance Input Capacitance Output Capacitance Conditions VCC = 5.0 V VI = VSS f Ta = 1 MHz = 25 °C Symbol CI CO Min. Max. 8 10 Unit pF pF All pins not under test must be connected with ground by capacitors. IC Code Numbers Example U6264A S A 07 Type Package S1 = SOP28 (300 mil) S = SOP28 (330 mil) Operating Temperature Range A = -40 to 125 °C Access Time 07 = 70 ns Internal Code The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2 digits the calendar week. December 12, 1997 5 U6264ASA07 Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH) tcR Ai DQi Output Addresses Valid ta(A ) Previous Data Valid tv(A) AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA Output Data Valid AAAAAAA AAAAAAA AAAAAAA AAAAAAA Read Cycle 2 (during Read cycle: W = VIH) tcR Ai tsu(A) Addresses Valid ta(E) tt(QX) tdis(E) tsu(A) ta(E) tt(QX) ta(G) tt(QX) tdis(E) E1 E2 G DQi Output High-Z tdis(G) AAAAAAAAAAAA AAAAAAAAAAAA Output Data AAAAAAAAAAAA Valid AAAAAAAAAAAA Write Cycle 1 (W-controlled) tcW Ai AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA t su(A) Addresses Valid tsu(E) E1 E2 W tsu(E) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA th(A) tw(W) tsu(D) th(D) DQi Input tdis(W) Input Data Valid tt(QX ) High-Z DQi Output AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA G AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA 6 December 12, 1997 U6264ASA07 Write Cycle 2 (E1-controlled) tcW Ai tsu(A) Addresses Valid tw(E) th(A ) E1 E2 W DQi Input tt(QX ) tdis(W) AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA tsu(E) tsu(W) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA t h(D) tsu(D) Input Data Valid High-Z DQi Output G AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Write Cycle 3 (E2-controlled) tcW Ai AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA tsu(A ) Addresses Valid tsu(E) E1 E2 W DQi Input tw(E) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA th(A ) AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA tsu(W) tsu(D) tdis(W) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA th(D) Input Data Valid High-Z DQi Output tt(QX ) G AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA undefined AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA L- or H-level AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA December 12, 1997 7 Memory Products 1998 Automotive 8K x 8 SRAM U6264ASA07 LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intend for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Zentrum Mikroelektronik Dresden GmbH Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany Phone: +49 351 88 22-3 06 • Fax: +49 351 88 22-3 37 • Email: sales@zmd.de Internet Web Site: http://www.zmd.de