NRED-1

N RED-1 N oise Reduction Processor DVD Digital Camera Driving the Digital Lifestyle Digital TV Imaging IP Cores Product Brief Description Zoran Corporation 1390 Kifer Road Sunnyvale, CA 94086-5305 Te l 408.523.6500 Fax 408.523.6501 www.zoran.com Zoran's NRED-1 Noise Reduction Processor is a silicon efficient, high performance Intellectual Property Core for video IC designs requiring noise reduction. NRED-1 is based on Zoran's extensive experience delivering high quality, high volume video ICs to major consumer products manufacturers worldwide. NRED-1 employs impulse, spatial and temporal noise reduction techniques along with robust motion detection to achieve the highest quality video possible in the presence of noise. NRED-1 enables display processors to provide superior video output and is useful for video compression systems where reducing noise is essential for eliminating unwanted artifacts. The NRED-1 Noise Reduction Processor greatly reduces the risk and time involved when integrating the video noise reduction function into an IC. Expensive, discrete components can be eliminated from system designs. When used in conjuntion with Zoran's FrameIt-1 Deinterlacer, a silicon and memory efficient implementation can be achieved for systems requiring progressive output. VIP-II Demonstration System Zoran offers the VIP-II FPGA demonstration system for evaluation of the NRED-1 Noise Reduction Processor. The VIP-II allows customers to input composite, s-video or component video to test NRED-1's performance. Features • • • • • Impulse Noise Reduction Adaptive Spatial Noise Reduction Motion Adaptive Temporal Noise Reduction Robust Motion Detection 3:2 and 2:2 pulldown detection • • • • Silicon efficient, fully synchronous design Requires only a single clock input ranging from 20 to 30 MHz Combinable with Zoran's Deinterlacers for efficient implementation Process technology independent "softcore" Integrated Circuit Applications • LCD display controllers • PDP-TV • Digital TV • LCD-TV • Projector TV Systems • Video compression systems Deliverables • Compilable Verilog source code • Bit accurate, cycle accurate C++ model • Synopsis synthesis scripts • Test input files • Documentation • VIP-II demonstration system available Figure 1. NRED-1 Noise Processor Block Diagram NRED-1 Noise Reduction IP Core Line Buffers Motion Detector Field Buffers Video In 4:2:2 or 4:2:0 Field Buffer Control Input Control Impulse Noise Reduction Filter Spatial Filter Temporal Filter Reduced Noise Video Out Noise Detector Output Control Film-mode Flag Film-mode/ Scene-cut Detector Scene-cut Flag 7/16/04-TS NRED-1-PB-1.0 NRED-1 N oise Reduction Processor Driving the Digital Lifestyle Product Brief Figure 2. NRED-1 Noise Reduction Processor Pinout Diagram reg_ack reg_rd_rdy reg_rd_data[7:0] hactive_out vactive_out field_out y_out[7:0] c_out[7:0] cr_valid_out[7:0] cb_valid_out[7:0] y_fbuf_rrst/y_fbuf_radr[17:0] y_fbuf_wrst/y_fbuf_wadr[17:0] y_fbuf_ren y_fbuf_wen y_fbuf_wdata[7:0] c_fbuf_rrst/c_fbuf_radr[17:0] c_fbuf_wrst/c_fbuf_wadr[17:0] c_fbuf_ren c_fbuf_wen c_fbuf_wdata[7:0] y_lbuf_rrst/y_lbuf_radr[17:0] y_lbuf_wrst/y_lbuf_wadr[17:0] y_lbuf_ren y_lbuf_wen y_lbuf_wdata[7:0] c_lbuf_rrst/c_lbuf_radr[17:0] c_lbuf_wrst/c_lbuf_wadr[17:0] c_lbuf_ren c_lbuf_wen c_lbuf_wdata[7:0] ext_clk ext_reset_1 reg_addr[7:0] reg_rd_wtn reg_rdy reg_wt_data[7:0] clk reset_l enable (optional)† cenable (optional)† hactive_in vactive_in field ext_noise_in y_in[7:0] c_in[7:0] y_fbuf_rdata[7:0] c_fbuf_rdata[7:0] y_lbuf_rdata[7:0] c_lbuf_rdata[7:0] y_curr_lbuf_A_rdata[7:0] y_prev_lbuf_B-rdata[7:0] y_prev_lbuf_A_rdata[7:0] y_prev_lbuf_B_rdata[7:0] c_curr_lbuf_A_rdata[7:0] c_curr_lbuf_B_rdata[7:0] c_prev_lbuf_A_rdata[7:0] c_prev_lbuf_B_rdata[7:0] y_fbuf_rdata_field[7:0](optional) NRED-1 Video Noise Reduction IP Core y_field_lbuf_A_rdata[7:0](optional)* y_field_lbuf_rdata[7:0](optional)* hist_a_ram_rdata[17:0](optional)‡ hist_b_ram_rdata[17:0](optional)‡ idh_a_ram_rdata[17:0](optional)‡ y_cp_lbuf_rrst/y_cp_lbuf_radr[17:0] y_cp_lbuf_wrst/y_cp_lbuf_wadr[17:0] y_cp_lbuf_ren y_cp_lbuf_A_wen y_cp_lbuf_B_wen y_curr_lbuf_wdata[7:0] y_prev_lbuf_wdata[7:0] c_cp_lbuf_rrst/c_cp_lbuf_radr[17:0] c_cp_lbuf_wrst/c_cp_lbuf_wadr[17:0] c_cp_lbuf_ren c_cp_lbuf_A_wen c_cp_lbuf_B_wen c_curr_lbuf_wdata[7:0] c_prev_lbuf_wdata[7:0] y_field_lbuf_wdata[7:0](optional)* hist_a_ram_rst/inc/rd(optional)‡ hist_a_ram_adr[4:0](optional)‡ hist_b_ram_rst/inc/rd(optional)‡ hist_b_ram_adr[4:0](optional)‡ idh_b_ram_rst/inc/rd(optional)‡ idh_ram_adr[3:0](optional)‡ scene_cut(optional)‡ dbg_dmux[7:0] *Required for AFM Detector †Required for Enabled Flops ‡Reserved for Scene Cut Detector For more information, contact Zoran's Sunnyvale office or the office nearest you: Canada Zoran Toronto Lab Te l : (416) 690-3356 Fax: (416) 690-3363 China Zoran China Office Tel: 86-755-83993777 Fax: 86-755-83220889 Hong Kong Zoran Asia Pacific Ltd. Tel: +852-2-620-5838 Fax: +852-2-620-5238 Israel Zoran Microelectronics Ltd. Te l : +972-4-8545-777 Fax: +972-4-8551-551 Japan Zoran Japan Office Te l : +81-03-5574-7081 Fax: +81-03-5574-7156 Korea Zoran Korea Office Tel: +82-2-761-7471 Fax: +82-2-761-7472 Taiwan Zoran Taiwan Office Te l : +886-2-2659-9797 Fax: +886-2-2659-9595 7/16/04-TS NRED-1-PB-1.0