HYM8563TS

HYM8563 HYM8563 2 I C Real Time Clock/Calendar Data Sheet Features General Description ■ Provides Year, Month, Day, Weekday, Hours, The HYM8563 is a CMOS real time clock/calendar, Minutes and Seconds Information which provides seconds, minutes, hours, day, date, ■ Century Flag month, and year information. The number of days in ■ Wide Operating Voltage: 1.8V to 5.5V each month and leap years are automatically ■ Low Power Consumption: 0.25μA at VDD = 3.0 V ■ I C-bus Interface adjusted. The clock can operate in two modes: one ■ Programmable Clock Output (32.768 kHz, 1024 is the 12-hour mode with an AM/PM indicator，the 2 Hz, 32 Hz and 1 Hz) other is the 24-hour mode. The clock/calendar is full ■ Alarm and Timer Functions binary-coded decimal (BCD). In addition, the ■ Built-in Power Voltage Detecting Circuit HYM8563 contains a programmable clock output, a 2 ■ I C -bus Slave Address: Read A3H and Write A2H timer, an alarm, a voltage-low detector. All address ■ Open-Drain Interrupt Pin 2 and data are transferred serially via I C bus and The Applications HYM8563 operates as a slave device on the serial ■ Cash Register bus. ■ Security Access Controller, Door Controller incremented automatically after each written or read ■ Time Recorder The built-in word address register is data byte. The HYM8563 is designed to operate on ■ Mobile Telephones very low power consumption. ■ Public Phone Bill Meter, Smart Card Payphone ■ MP3/MP4 Player ■ IC Water-Flow Meter, IC Gas Meter Block Diagram -1- HYM8563 Pin Assignment Absolute Maximum Rating Parameter Symbol Min Max Unit Supply Voltage VDD -0.5 +6.5 V Supply Current IDD -0.5 +50 mA Input Voltage on pins SCL and SDA VI -0.5 +6.5 V -0.5 VDD+0.5 V VO -0.5 +6.5 V DC input current at any input II -10 +10 mA DC output current at any output IO -10 +10 mA Total power dissipation P 300 mW Ambient temperature TA Input Voltage on pin OSCI Output Voltage on CLKOUT and INT Storage temperature -40 TS -65 +85 O C +150 O C Electricity characteristics Parameter Symbol Conditions Min 2 Supply voltage Typ [1] I C-bus inactive; 1.0 Max 5.5 TA = 25ºC Supply voltage for clock data VDD integrity V 2 [1] I C-bus active; 1.8 5.5 V Vlow 5.5 V 800 A 200 A fSCL = 400 kHz TA = 25ºC Supply current1(interface active) fSCL = 400 kHz IDD1 Supply current2(interface fSCL = 100 kHz fSCL = 0 Hz, TA = 25ºC inactive) CLKOUT disabled [2] VDD = 5.0 V 275 550 nA VDD = 3.0 V 250 500 nA 225 450 nA VDD = 5.0 V 500 750 nA VDD = 3.0 V 400 650 nA 400 600 nA VDD = 2.0 V IDD2 fSCL = 0 Hz, TA = -40 ～+85ºC [2] VDD = 2.0 V Supply Unit current3(interface fSCL = 0 Hz, TA = 25ºC [2] inactive) CLKOUT enabled at VDD = 5.0 V 825 1600 nA 32kHz VDD = 3.0 V 550 1000 nA 425 800 nA 950 1700 nA VDD = 2.0 V fSCL = 0 Hz, TA = -40 ～+85ºC IDD3 VDD = 5.0 V -2- [2] HYM8563 LOW-level input voltage VDD = 3.0 V 650 1100 nA VDD = 2.0 V 500 900 nA 0.3 V VIL VSS VDD HIGH-level input voltage VIH 0.7 VDD Input leakage current ILI Input capacitance CI [3] SDA LOW-level output current IOLS VOL = 0.4 V; VDD = 5 V -3 mA INT LOW-level output current IOLI VOL = 0.4 V; VDD = 5 V -1 mA CLKOUT VI= VDD or VSS -1 0 VDD V +1 A 7 pF LOW-level output IOLC VOL = 0.4 V; VDD = 5 V -1 mA HIGH-level output IOHC VOH = 4.6 V; VDD = 5 V -1 mA -1 current CLKOUT current Output leakage current ILO VO = VDD or VSS Low voltage detection Vlow TA = 25ºC 0 +1 A 0.9 1.0 V Note: [1] For reliable oscillator start-up at power-up: VDD(min, power-up) = VDD(min) + 0.3 V. [2] Timer source clock = 1/60 Hz, level of pins SCL and SDA is VDD [3] Tested on sample basis. Alternating Characteristics (VDD=1.8 to 5.5V, VSS=0V; TA=-40 to +85ºC; fosc=32.768kHz; quartz RS=40kΩ, CL=8pF; unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit 15 25 35 pF 40 kΩ oscillator integrated load capacitance C INT oscillator stability 2*10 -7 Dfosc/fosc Quartz crystal parameters(f=32.768 kHz) series resistance Rs parallel load capacitance CL trimmer capacitance CT 10 5 pF 25 pF CLKOUT output CLKOUT duty cycle 2 I C-bus timing characteristics SCL clock frequency δCLKOUT [1] fSCL [3] 50 % [2] 400 kHz START condition hold time tHD;STA 0.6 µs set-up time for a repeated tSU;STA 0.6 µs START condition -3- HYM8563 SCL LOW time tLOW 1.3 SCL HIGH time tHIGH 0.6 µs SCL and SDA rise time tr 0.3 µs SCL and SDA fall time tf 0.3 µs capacitive bus line load Cb 400 pF data set-up time tSU;DAT 100 ns data hold time tHD;DAT 0 ns set-up time for STOP tSU;STO 4.0 µs condition tolerable spike width on bus tSW 50 ns Note: [1] Unspecified for fCLKOUT = 32.768 kHz. [2] All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD. 2 [3] I C-bus access time between two STARTS or between a START and a STOP condition to this device must be less than one second. 2 Figure1: I C-bus timing waveform Figure 2: IDD as a function of VDD; Figure 3: IDD as a function of VDD; CLKOUT disabled CLKOUT = 32KHz -4- HYM8563 Figure 4: IDD as a function of T; Figure 5: Frequency deviation as a CLKOUT = 32KHz function of VDD Application Information Register Organization The HYM8563 contains 16 registers with an auto-incrementing address register as shown on Table1. Table 1.Registers Overview Address Register name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00H Control/status1 TEST 0 STOP 0 TESTC 0 0 0 01H Control/status2 0 0 0 TI/TP AF TF AIE TIE 02H Seconds VL Seconds 00 to 59 coded in BCD 03H Minutes - Minutes 00to 59 coded in BCD 04H Hours - - 05H Days - - 06H Weekdays - - - 07H Months/century C - - Hours 00 to 23 coded in BCD Days 01 to 31 coded in BCD - - Weekdays 0 to 6 Months 01 to 12 coded in BCD 08H Years Years 00 to 99 coded in BCD 09H Minute alarm AE 0AH Hour alarm AE - Hour alarm 00 to 23 coded in BCD 0BH Date alarm AE - Day alarm 01 to 31 coded in BCD 0CH Weekday alarm AE - - - - Weekday alarm 0 to 6 0DH CLKOUT control FE - - - - - FD1 FD0 0EH Timer control TE - - - - - TD1 TD0 0FH Timer countdown Minute alarm 00 to 59 coded in BCD Timer countdown value Note: Bit positions labeled as”-”are not implemented. Bit positions labeled with 0 should always be written with logic 0. All 16 registers are designed as addressable 8-bit parallel registers although not all bits are implemented. The first two registers (00H and 01H) are used as control and status registers. Registers 02H to 08H are used as counters for clock function (seconds up to year’ s counters). Registers 09H through 0CH contain alarm -5- HYM8563 registers which define the conditions for an alarm. Register 0DH controls the CLKOUT output frequency. Registers 0EH and 0FH are the timer control and timer register, respectively. The seconds, minutes, hours, days, months, year as well as the minute alarm, hour alarm and day alarm registers are all coded in BCD format. Weekday and weekday alarm are not coded in BCD format. Control/ Status 1 Register The TEST and TESTC bits of Control/Status 1 register must be set to logic 0. When these bits are set to logic 1, the device enters test mode for manufacturer (see Table2). Table 2. Control/Status 1 (address 00H) Register Bit Symbol Description 7 TEST TEST=0:normal mode; TEST=1: test mode for manufacturer 5 STOP STOP=0:RTC clock runs; STOP=1:All RTC divider chain flip-flops are asynchronously set to logic 0,the RTC clock is stopped(CLKOUT at 32.768 kHz is still available) 3 TESTC TESTC=0: normal operation; TESTC=1: test mode for manufacturer 6,4,2 to 0 Default value is logic 0 Control/ Status 2 Register Bit TF and AF: When an alarm occurs, AF is set to logic 1.Similary, at the end of a timer countdown, TF is set to 1.These bits maintain their value until overwritten by software. If both timer and alarm interrupts are required in the application, the source of the interrupts can be determined by reading these bits. To prevent one flag being overwritten while clearing, another logic AND is performed during a write access. Bit TIE and AIE: These bits activate the generation of an interrupt, when TF or AF is asserted. The interrupt is the logical OR. Table 3 . Control/ Status 2 Register (address 01H) Register Bit Symbol Description 7 to 5 Default value is logic 0 TI/TP=0: INT is active when TF is active (subject to the status of TIE) 4 TI/TP TI/TP=1: INT pulses active according to Table 5 (subject to the status of TIE); Note that if AF and AIE are active then INT will be permanently active AF=0: Reading, alarm flag inactive; Writing, alarm flag is cleared 3 AF 2 TF 1 AIE AIE=0: alarm interrupt disabled; AIE=1: alarm interrupt enabled 0 TIE TIE=0: timer interrupt disabled; TIE=0: timer interrupt enabled AF=1: Reading, alarm flag active; Writing, alarm flag remains unchanged TF=0: Reading, timer flag inactive; Writing, timer flag is cleared TF=1: Reading, timer flag active; Writing, timer flag remains unchanged Table 4. Source clock(Hz) Operation (Bit TI/TP=1) INT [2] [1] period n =1 n>1 4096 1/8192 1/4096 64 1/128 1/64 1 1/64 1/64 -6- HYM8563 1/60 Note: [1]. TF and 1/64 1/64 become simultaneously active. [2]. n=loaded countdown value. Timer stopped when n=0. Alarm Function By clearing the MSB of one or more of the alarm registers (bit AE=alarm enable), the corresponding alarm condition will be active. When one or more of these alarm registers are loaded with a valid minute, hour, day or weekday, then that information will be compared with the current minute, hour, day and weekday. When all enabled comparisons first match, the Alarm Flag (AF) is set. The asserted AF can be used to generate an interrupt ( INT ). The AF can only be cleared by software. Once AF has been cleared it will only be set again when the time increments to match the alarm condition once more. In this way, an alarm can be generated from once per minute up to once per week (see Table1). Timer Function The 8-bit countdown timer is controlled by timer control register (see Table1). The timer control register determiners one of 4 source clock frequencies for the timer (4096 Hz, 64 Hz, 1 Hz, or 1/64 Hz), and enables or disables end of every countdown. When bit7 (TE bit) of The timer control register is set to logic 0, timer is disabled; when TE=1, timer is enabled. The TD1 and TD0 bits determine the source clock for the countdown timer(see Table 5), when not in use, TD1 and TD0 should be set to 1/60 Hz for power saving. The timer counts down from a software-loaded 8-bit binary value. At the end of countdown, the timer sets the Timer Flag (TF). The asserted TF can be used to generate an interrupt ( INT ). The interrupt may be generated as a pulsed signal every countdown period, the TF may only be cleared by software. Bit TI/TP is used to control generated conditions of interrupt. When reading the timer, the current countdown value is returned. Table 5. Timer Frequency Selection TD1 TD0 Timer Source clock frequency(Hz) 0 0 4096 0 1 64 1 0 1 1 1 1/60 Clock Output A programmable square wave is available at pin CLKOUT. The CLKOUT control register is used to control the operation of the CLKOUT pin. Bit7 (FE bit) of the CLKOUT control register is square wave enable bit, when set to logic 0, the square wave output is enable, when set to logic 1, the CLKOUT output is inhibited. CLKOUT is an open-drain output and enabled at power-on. If disabled it becomes high-impedance. The frequency of the square wave output depends upon the value of the FD0 and FD1 bits. The FD bits control the frequency of the square wave output when the square wave output has been enabled. Table 6 lists the square wave frequencies that can be selected with the FD bits. -7- HYM8563 Table 6. CLKOUT frequency selection FD1 FD0 fCLKOUT 0 0 32.768 kHz 0 1 1024Hz 1 0 32Hz 1 1 1Hz Reset The HYM8563 includes an internal reset circuit which is active whenever the oscillator is stopped. In the reset 2 state the I C-bus logic is initialized and all registers, including the address pointer, are cleared with the exception of bits FE, VL, TD1, TD0, TESTC and AE which are set to logic 1. Voltage-Low Detector and Clock Surveillance The HYM8563 has an on-chip voltage-low detector. When VDD drops below VLOW, bit VL in the seconds register is set to indicate that the integrity of the clock/calendar information is no longer guaranteed. The VL flag can only be cleared by software. When VDD decreased slowly up to VLOW , bit VL will be set. This will indicate that the time may be corrupted. Figure 6. Voltage-low detection I2C-Bus Description I2C-Bus Interface 2 The HYM8563 supports I C-bus transmission protocol. The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. The master device generates the serial clock (SCL), controls the bus access, and generates the START and 2 STOP conditions. The HYM8563 operates as a slave on the I C-bus. A typical bus configuration using this 2-wire protocol is show in Figure 7. -8- HYM8563 2 Figure 7. Typical I C-Bus Configuration Data transfer may be initiated only when the bus is not busy. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Start and Stop Conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition(S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P), see Figure 8. Figure 8. Definition of Start and Stop Condition Bit Transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 9). Figure 9. Bit Transfer Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit -9- HYM8563 (see Figure 10). The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. Figure 10. Acknowledgement on the I2C bus Device Addressing 2 Before any data is transmitted on the I C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The HYM8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line. The HYM8563 slave address is shown in Table 7. Table 7. Slave address 1 0 1 0 0 0 1 R/W The address byte contains the 7-bit HYM8563 address, which is 1010001, followed by the direction bit (R/W). The R/W bit is a 1 for a read, and a 0 for a write. After receiving and decoding the address byte the device inputs an acknowledge on the SDA line. The HYM8563 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. Read/Write Cycles 2 The I C-bus configuration for the different HYM8563 read and write cycles is shown in Figure 11, Figure 12 and Figure 13. The word address is a 4-bit value that defines which register is to be accessed next. The upper four bits of the word address are not use. Figure 11. Master transmit to slave receiver(write mode) - 10 - HYM8563 Figure 12. Master reads after setting word address(write word address; read data) Figure 13.Master reads slave immediately after first byte(read mode) Typical Application Circuit Diagram - 11 - HYM8563 Ordering Information Type Temperature range HYM8563 HYM8563Z Package DIP8 -40 to +85ºC HYM8563TS SOP8 TSSOP8 Package - 12 -