DDR4 Datasheet
DDR4 Datasheet
D-00383
MD4C1001G-N43R
Version 0.1
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DDR4 Datasheet
MD4C1001G-N43R
Contents
Contents .............................................................................................................................................................. 2
Figures ................................................................................................................................................................. 3
Tables................................................................................................................................................................... 3
Key Features ........................................................................................................................................................ 4
1. Introduction ..................................................................................................................................................... 5
1.1 General Description .......................................................................................................................................................5
1.2 Part Number Decoder ....................................................................................................................................................5
1.3 Ordering Information .....................................................................................................................................................5
2. Product Specifications ................................................................................................................................... 6
2.1 Temperature Specifications ..........................................................................................................................................6
2.2 SDRAM Addressing .......................................................................................................................................................6
2.3 Ball Pin Configuration ....................................................................................................................................................6
2.4 Package Dimension .......................................................................................................................................................9
3. Basic IDD, IPP and IDDQ Measurement Conditions ................................................................................... 10
4. Input / Output Capacitance .......................................................................................................................... 14
5. Absolute Maximum DC Ratings ................................................................................................................... 15
6. Recommended DC Operating Conditions ................................................................................................... 16
7. Electrical Characteristics and AC Timing .................................................................................................... 17
7.1 Core Timing Parameters ............................................................................................................................................ 17
7.2 tREFI and tRFC Parameters ....................................................................................................................................... 18
Revision History ................................................................................................................................................ 19
Everything for Memory
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DDR4 Datasheet
MD4C1001G-N43R
Figures
Figure 1 Part Number Decoder .......................................................................................................................... 5
Figure 2 Ball Assignment.................................................................................................................................... 6
Figure 3 Package Dimension ............................................................................................................................. 9
Tables
Table 1 Key Timing Parameters ......................................................................................................................... 4
Table 2 Ordering Information ............................................................................................................................. 5
Table 3 Temperature Specifications .................................................................................................................. 6
Table 4 SDRAM Addressing ............................................................................................................................... 6
Table 5 Pin Description ....................................................................................................................................... 7
Table 6 Basic IDD, IPP and IDDQ Measurement Conditions .......................................................................... 10
Table 7 IDD, IPP, and IDDQ Current Limits ....................................................................................................... 12
Table 8 Input/Output Capacitance ................................................................................................................... 14
Table 9 Absolute Maximum DC Ratings .......................................................................................................... 15
Table 10 Recommended DC Operating Conditions ........................................................................................ 16
Table 11 DDR4-3200 Speed Bins and Operating Conditions ......................................................................... 17
Table 12 tREFI and tRFC Parameters .............................................................................................................. 18
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DDR4 Datasheet
MD4C1001G-N43R
Key Features
Specification Compatibility
JEDEC Standard No. JESD79-4
Features
VDD=VDDQ=1.14V~1.26V, 1.20V nominal
VPP = 2.375V~2.75V, 2.50V norminal
Fully differential clock inputs (CK, CK_n)
operation
Differential Data Strobe (DQS, DQS)
DM masks write data-in at the both rising and
falling edges of the data strobe
All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
Programmable CAS latency
Programmable CAS Write latency
Programmable burst length 4/8 with both
nibble sequential and interleave mode
Average Refresh Cycle
64ms at TC ≤ 85°C
–
32ms at 85°C ≤ TC ≤ 95°C
Temperature Controlled refresh(TCR)
LP ASR(Low Power Auto Self Refresh) mode
is supported
Fine Granularity Refresh is supported
Per DRAM Addressability is supported
This product in compliance with the RoHS
Directive
Options
Power Supply
8n-bit prefetch architecture
Internal Vref DQ level generation is available
512M x 16
Package
96-ball FBGA (7.5mm x 13mm x1.2mm
max)
Timing - Cycle time
–
VDD/VDDQ/VPP: 1.20V/1.20V/2.50V
Organization
–
Write Levelization supported
Everything for Memory
Maximum Power Saving Mode is supported
0.625
–
–
DDR4-3200
Write CRC is supported at all speed grades
–
Table 1 Key Timing Parameters
Date Rate per pin
tCK
（Mbps）
0.625ns@CL=22(DDR4-3200)
Operating temperature range
–
0°C to +85°C
CAS Latency (tCK）
tRCD (ns)
tRP (ns)
tRAS(ns)
tRC(ns)
tRCD-tRP-CL
22
13.75
13.75
32
45.75
22-22-22
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DDR4 Datasheet
MD4C1001G-N43R
1. Introduction
1.1 General Description
It is a 8Gb CMOS Double Data Rate IV(DDR4) Synchronous DRAM, ideally suited for the main memory
applications which requires large memory density and high bandwidth. The 8Gb DDR4 DRAMs offer fully
synchronous operations referenced to both rising and falling edges of the clock. While all addresses and
control inputs are latched on the rising edges of the /CK (falling edges of the /CK), Data, Data strobes
and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are
internally pipelined and 8-bit prefetched to achieve very high bandwidth.
1.2 Part Number Decoder
M
D4
C
1
001G
–
N43R
ISOCOM
Reserved
Product Name:
DDR4
DDR4 Capacity
Package:
96ball
7.5*13（mm2）
Reserved
Figure 1 Part Number Decoder
1.3 Ordering Information
Table 2 Ordering Information
Part Number
Package
Size(mm)
Memory
Combination
Operation Voltage
Density
Speed
Package
MD4C1001G-N43R
7.5*13*1.2(max)
DDR4
1.20V/1.20V/2.50V
8Gb
3200Mbps
96ball FBGA
Everything for Memory
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DDR4 Datasheet
MD4C1001G-N43R
2. Product Specifications
2.1 Temperature Specifications
Table 3 Temperature Specifications
The Case Surface Temperature（Tc）
Operation
0°C ~ +85°C
Storage
-55°C ~ +150°C
2.2 SDRAM Addressing
Table 4 SDRAM Addressing
512Meg x 16
Configuration (8Gb/Package)
Number of Bank Groups
2
BG Address
BG0
Bank Address in a BG
BA0 ~ BA1
Bank Address
Row address
A0 ~ A15
Column address
A0 ~ A9
Page size (bytes)
2 KB
2.3 Ball Pin Configuration
96-Ball FBGA Package
Figure 2 Ball Assignment
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DDR4 Datasheet
MD4C1001G-N43R
Notes:
1. See Ball Descriptions.
2. Address bits (including bank groups) are density- and configuration-dependent (see Addressing).
Table 5 Pin Description
Symbol
Type
A[17:0]
Input
A10/AP
Input
A12/BC_n
Input
ACT_n
Input
BA[1:0]
Input
BG[1:0]
Input
C0/CKE1,
C1/CS1_n,
C2/ODT1
Input
CK_t, CK_c
Input
CKE
Reference
CS_n
Supply
DM_n,
UDM_n
LDM_n
Supply
ODT
Input
Everything for Memory
Description
Address inputs: Provide the row address for ACTIVATE commands and the column address
for READ/WRITE commands to select one location out of the memory array in the
respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/A16 have additional
functions, see individual entries in this table.) The address inputs also provide the op-code
during theMODE REGISTER SET command. A16 is used on some 8Gb and 16Gb parts, and
A17 is only used on some 16Gb parts
Auto precharge: A10 is sampled during READ and WRITE commands to determine whether
auto precharge should be performed to the accessed bank after a READ or WRITE
operation. (HIGH = auto precharge; LOW = no auto precharge.) A10 is sampled during a
PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10
LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by
the bank group and bank addresses.
Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if burst
chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW = burst chopped). See the
Command Truth Table.
Command input: ACT_n indicates an ACTIVATE command. When ACT_n (along with CS_n)
is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are treated as row address
inputs for the ACTIVATE command. When ACT_n is HIGH (along with CS_n LOW), the input
pins RAS_n/ A16, CAS_n/A15, and WE_n/A14 are treated as normal commands that use the
RAS_n, CAS_n, and WE_n signals. See the Command Truth Table.
Bank address inputs: Define the bank (within a bank group) to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. Also determines which mode register is
to be accessed during a MODE REGISTER SET command.
Bank group address inputs: Define the bank group to which a REFRESH, ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. Also determines which mode register is
to be accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8
configurations. BG1 is not used in the x16 configuration.
Stack address inputs: These inputs are used only when devices are stacked; that is, they are
used in 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins are not used in the
x16 configuration). DDR4 will support a traditional DDP package, which uses these three
signals for control of the second die (CS1_n, CKE1, ODT1). DDR4 is not expected to support
a traditional QDP package. For all other stack configurations, such as a 4H or 8H, it is
assumed to be a single-load (master/slave) type of configuration where C0, C1, and C2 are
used as chip ID selects in conjunction with a single CS_n, CKE, and ODT signal.
Clock: Differential clock inputs. All address, command, and control input signals are
sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c.
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals,
device input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in
any bank). CKE is asynchronous for self refresh exit. After VREFCA has become stable
during the power-on and initialization sequence, it must be maintained during all operations
(including SELF REFRESH). CKE must be maintained HIGH throughout read and write
accesses. Input buffers (excluding CK_t, CK_c, ODT, RESET_n, and CKE) are disabled during
power-down. Input buffers (excluding CKE and RESET_n) are disabled during self refresh.
Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides for
external rank selection on systems with multiple ranks. CS_n is considered part of the
command code.
Input data mask: DM_n is an input mask signal for write data. Input data is masked when
DM is sampled LOW coincident with that input data during a write access. DM is sampled
on both edges of DQS. DM is not supported on x4 configurations. The UDM_n and LDM_n
pins are used in the x16 configuration: UDM_n is associated with DQ[15:8]; LDM_n is
associated with DQ[7:0]. The DM, DBI, and TDQS functions are enabled by mode register
settings. See the Data Mask section.
On-die termination: ODT (registered HIGH) enables termination resistance internal to the
DDR4 SDRAM. When enabled, ODT (RTT) is applied only to each DQ, DQS_t, DQS_c, DM_n/
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DDR4 Datasheet
MD4C1001G-N43R
Symbol
Type
PAR
Input
RAS_n/A16
CAS_n/A15
WE_n/A14
Input
RESET_n
Input
TEN
Input
DQ
IO
DBI_n,
UDBI_n,
LDBI_n
Input
DQS_t
DQS_cDQSU_tD
QSU_c,DQSL_t
DQSL_c
Input/
Output
ALERT_n
Output
TDQS_t,
TDQS_c
Output
Description
DBI_n/TDQS_t, and TDQS_c signal for the x4 and x8 configurations (when the TDQS function
is enabled via mode register). For the x16 configuration, RTT is applied to each DQ, DQSU_t,
DQSU_c, DQSL_t, DQSL_c, UDM_n, and LDM_n signal. The ODT pin will be ignored if the
mode registers are programmed to disable RTT.
Parity for command and address: This function can be enabled or disabled via the mode
register. When enabled, the parity signal covers all command and address inputs, including
ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, A[17:0], A10/AP, A12/BC_n, BA[1:0], and BG[1:0]
with C0, C1, and C2 on 3DS only devices. Control pins NOT covered by the parity signal are
CS_n, CKE, and ODT. Unused address pins that are density- and configuration specific
should be treated internally as 0s by the DRAM parity logic. Command and address inputs
will have parity check performed when commands are latched via the rising edge of CK_t
and when CS_n is LOW.
Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n and ACT_n)
define the command and/or address being entered. See the ACT_n description in this table.
Active LOW asynchronous reset: Reset is active when RESET_n is LOW, and inactive when
RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is a CMOS railto-rail signal with DC HIGH and LOW at 80% and 20% of VDD (960 mV for DC HIGH and 240
mV for DC LOW).
Connectivity test mode: TEN is active when HIGH and inactive when LOW. TEN must be
LOW during normal operation. TEN is a CMOS rail-to-rail signal with DC HIGH and LOW at
80% and 20% of VDD (960mV for DC HIGH and 240mV for DC LOW).
Data input/output: Bidirectional data bus. DQ represents DQ[3:0], DQ[7:0], and DQ[15:0] for
the x4, x8, and x16 configurations, respectively. If write CRC is enabled via mode register,
the write CRC code is added at the end of data burst. Any one or all of DQ0, DQ1, DQ2, and
DQ3 may be used to monitor the internal V REF level during test via mode register setting
MR[4] A[4] = HIGH, training times change when enabled. During this mode, the RTT value
should be set to High-Z. This measurement is for verification purposes and is NOT an
external voltage supply pin.
DBI input/output: Data bus inversion. DBI_n is an input/output signal used for data bus
inversion in the x8 configuration. UDBI_n and LDBI_n are used in the x16 configuration;
UDBI_n is associated with DQ[15:8], and LDBI_n is associated with DQ[7:0]. The DBI feature
is not supported on the x4 configuration. DBI can be configured for both READ (output) and
WRITE (input) operations depending on the mode register settings. The DM, DBI, and TDQS
functions are enabled by mode register settings. See the Data Bus Inversion section.
Data strobe: Output with READ data, input with WRITE data. Edge-aligned with READ data,
centered-aligned with WRITE data. For the x16, DQSL corresponds to the data on DQ[7:0];
DQSU corresponds to the data on DQ[15:8]. For the x4 and x8 configurations, DQS
corresponds to the data on DQ[3:0] and DQ[7:0], respectively. DDR4 SDRAM supports a
differential data strobe only and does not support a single-ended data strobe.
Alert output: This signal allows the DRAM to indicate to the system's memory controller that
a specific alert or event has occurred. Alerts will include the command/address parity error
and the CRC data error when either of these functions is enabled in the mode register.
Termination data strobe: TDQS_t and TDQS_c are used by x8 DRAMs only. When enabled via
the mode register, the DRAM will enable the same RTT termination resistance on TDQS_t
and TDQS_c that is applied to DQS_t and DQS_c. When the TDQS function is disabled via the
mode register, the DM/TDQS_t pin will provide the DATA MASK (DM) function, and the
TDQS_c pin is not used. The TDQS function must be disabled in the mode register for both
the x4 and x16 configurations. The DM function is supported only in x8 and x16
configurations.
VDD
Supply
Power supply: 1.2V ±0.060V.
VDDQ
Supply
DQ power supply: 1.2V ±0.060V.
VPP
Supply
DRAM activating power supply: 2.5V –0.125V/+0.250V.
VREFCA
Supply
Reference voltage for control, command, and address pins.
VSS
Supply
Ground.
VSSQ
Supply
DQ ground.
Reference
Reference ball for ZQ calibration:
which is tied to VSSQ.
ZQ
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DDR4 Datasheet
MD4C1001G-N43R
Symbol
Type
Description
RFU
-
Reserved for future use.
NC
-
No connect: No internal electrical connection is present.
NF
-
No function: May have internal connection present but has no function.
2.4 Package Dimension
Figure 3 Package Dimension
Everything for Memory
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DDR4 Datasheet
MD4C1001G-N43R
3. Basic IDD, IPP and IDDQ Measurement Conditions
Table 6 Basic IDD, IPP and IDDQ Measurement Conditions
Symbol
IDD0
IPP0
IDD1
IDD2N
IDD2NT
IDD2P
IDD2Q
IDD3N
IPP3N
IDD3P
IDD4R
IDD4W
Description
Operating One Bank Active-Precharge Current(AL=0)
CKE: High; External clock:On; tCK, nRC, nRAS, CL: see Table1; BL81·AL:0; CS_n: High between ACT and PRE;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 3: Data IO:
VDDQ; DM_n: stable at 1; Bank Activity: Cycling with one bank active at a time: 0, 0, 1, 1, 2, 2,……(see the I DD0
Measurement-Loop Pattern table); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0;
Pattern Details: see the I DD0 Measurement-Loop Pattern table
Operating One Bank Active-Precharge IPP Current (AL = 0)
Same conditions as I DD0 above
Operating One Bank Active-Read-Precharge Current (AL = 0)
CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, CL: see the previous table; BL: 8; 1, 5 AL: 0; CS_n: HIGH
between ACT, RD, and PRE; Command, address, bank group address, bank address inputs, Data I/O: partially
toggling according to the I DD1 Measurement-Loop Pattern table; DM_n: stable at 0; Bank activity: cycling with
one bank active at a time: 0, 0, 1, 1, 2, 2, ... (see the following table); Output buffer and RTT : enabled in mode
registers; 2 ODT Signal: stable at 0; Pattern details: see the IDD1 Measurement-Loop Pattern table
Precharge Standby Current (AL = 0)
CKE: HIGH; External clock: On; tCK, CL: see the previous table; BL: 8; 1 AL: 0; CS_n: stable at 1; Command,
address, bank group address, bank address Inputs: partially toggling according to the IDD2N and IDD3N
Measurement-Loop Pattern table; Data I/O: V DDQ ; DM_n: stable at 1; Bank activity: all banks closed; Output
buffer and RTT : enabled in mode registers; 2 ODT signal: stable at 0; Pattern details: see the I DD2N and I DD3N
Measurement-Loop Pattern table
Precharge Standby ODT Current
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8; 1 AL: 0; CS_n: stable at 1; Command, address,
bank group address, bank address inputs: partially toggling according to the IDD2NT Measurement-Loop Pattern
table; Data I/O: VSSQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and R TT: enabled in mode
registers; 2 ODT signal: toggling according to the IDD2NT Measurement-Loop Pattern table; Pattern details: see
the IDD2NT Measurement-Loop Pattern table
Precharge Power-Down Current
CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8; 1 AL: 0; CS_n: stable at 1; Command, address,
bank group address, bank address inputs: stable at 0; Data I/O: VDDQ ; DM_n: stable at 1; Bank activity: all banks
closed; Output buffer and R TT: Enabled in mode registers; 2 ODT signal: stable at 0
Precharge Quiet Standby Current
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8; 1 AL: 0; CS_n: stable at 1; Command,
address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity:
all banks closed; Output buffer and RTT: Enabled in mode registers; 2 ODT signal: stable at 0
Active Standby Current (AL = 0)
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8; 1 AL: 0; CS_n: stable at 1; Command,
address, bank group address, bank address inputs: partially toggling according to the IDD2N and IDD3N
Measurement-Loop Pattern table; Data I/O: V DDQ; DM_n: stable at 1; Bank activity: all banks open; Output buffer
and RTT: Enabled in mode registers; 2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N
Measurement-Loop Pattern table
Active Standby I PP3N Current (AL = 0)
Same conditions as I DD3N above
Active Power-Down Current (AL = 0)
CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8; 1 AL: 0; CS_n: stable at 1; Command, address,
bank group address, bank address inputs: stable at 1; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks
open; Output buffer and RTT: Enabled in mode registers; 2 ODT signal: stable at 0
Operating Burst Read Current (AL = 0)
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8; 15 AL: 0; CS_n: HIGH between RD; Command,
address, bank group address, bank address inputs: partially toggling according to the IDD4R Measurement-Loop
Pattern table; Data I/O: seamless read data burst with different data between one burst and the next one
according to the IDD4R Measurement-Loop Pattern table; DM_n: stable at 1; Bank activity: all banks open, RD
commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see the I DD4R Measurement-Loop Pattern table); Output
buffer and RTT: Enabled in mode registers; 2 ODT signal: stable at 0; Pattern details: see the IDD4R MeasurementLoop Pattern table
Operating Burst Write Current (AL = 0)
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8; 1 AL: 0; CS_n: HIGH between WR; Command,
address, bank group address, bank address inputs: partially toggling according to the IDD4W Measurement-Loop
Pattern table; Data I/O: seamless write data burst with different data between one burst and the next one
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DDR4 Datasheet
MD4C1001G-N43R
Symbol
IDD5R
IPP5R
IDD6N
IDD6E
IPP6x
IDD6R
IDD7
IPP7
IDD8
IDD9
IPP9
Description
according to the IDD4W Measurement-Loop Pattern table; DM: stable at 0; Bank activity: all banks open, WR
commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see IDD4W Measurement-Loop Pattern table); Output buffer
and RTT: enabled in mode registers (see note2); ODT signal: stable at HIGH; Pattern details: see the IDD4W
Measurement-Loop Pattern table
Distributed Refresh Current (1X REF)
CKE: HIGH; External clock: on; tCK, CL, nREFI: see the previous table; BL: 8; 1 AL: 0; CS_n: HIGH between REF;
Command, address, bank group address, bank address inputs: partially toggling according to the IDD5R
Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: REF command every nREFI
(see the IDD5R Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers 2 ; ODT
signal: stable at 0; Pattern details: see the IDD5R Measurement-Loop Pattern table
Distributed Refresh Current (1X REF)
Same conditions as IDD5R above
Self Refresh Current: Normal Temperature Range
TC: 0–85°C; Auto self refresh (ASR): disabled; 3 Self refresh temperature range (SRT): normal; 4 CKE: LOW;
External clock: off; CK_t and CK_c: LOW; CL: see the table above; BL: 8; 1 AL: 0; CS_n, command, address, bank
group address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: SELF REFRESH operation; Output
buffer and RTT: enabled in mode registers; 2 ODT signal: midlevel
Self Refresh Current: Extended Temperature Range 4
TC: 0–95°C; Auto self refresh (ASR): disabled 4 ; Self refresh temperature range (SRT): extended; 4 CKE: LOW;
External clock: off; CK_t and CK_c: LOW; CL: see the previous table; BL: 8; 1 AL: 0; CS_n, command, address, group
bank address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: EXTENDED TEMPERATURE SELF
REFRESH operation; Output buffer and RTT : enabled in mode registers; 2 ODT signal: midlevel
Self Refresh IPP Current
Same conditions as IDD6E above
Self Refresh Current: Reduced Temperature Range
TC: 0–45°C; Auto self refresh (ASR): disabled; Self refresh temperature range (SRT): reduced; 4 CKE: LOW;
External clock: off; CK_t and CK_c: LOW; CL: see the previous table; BL: 8; 1 AL: 0; CS_n, command, address, bank
group address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: EXTENDED TEMPERATURE SELF
REFRESH operation; Output buffer and RTT: enabled in mode registers; 2 ODT signal: midlevel
Operating Bank Interleave Read Current
CKE: HIGH; External clock: on; t CK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see the previous table; BL: 8; 15 AL: CL -1;
CS_n: HIGH between ACT and RDA; Command, address, group bank adress, bank address inputs: partially
toggling according to the IDD7 Measurement-Loop Pattern table; Data I/O: read data bursts with different data
between one burst and the next one according to the IDD7 Measurement-Loop Pattern table; DM: stable at 1;
Bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see the IDD7
Measurement-Loop Pattern table; Output buffer and RTT : enabled in mode registers; 2 ODT signal: stable at 0;
Pattern details: see the IDD7 Measurement-Loop Pattern table
Operating Bank Interleave Read IPP Current
Same conditions as IDD7 above
Maximum Power Down Current
Place DRAM in MPSM then CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8; 1 AL: 0; CS_n:
stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ ; DM_n:
stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers; 2 ODT signal: stable
at 0
MBIST-PPR Current 7
Device in MBIST-PPR mode; External clock: on; CS_n: stable at 1 after MBIST-PPR entry; Command, address,
bank group address, bank address inputs: stable at 1; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all
banks closed; Output buffer and RTT: Enabled in mode registers; 2 ODT signal: stable at 0
MBIST-PPR IPP Current
Same condition with IDD9 above
Notes:
1. Burst length: BL8 fixed by MRS: set MR0[1:0] 00.
2. Output buffer enable: set MR1[12] 0 (output buffer enabled); set MR1[2:1] 00 (RON =RZQ/7); RTT(NOM) enable: set MR1[10:8]
011 (RZQ /6); RTT(WR) enable: set MR2[11:9] 001 (RZQ/2), and RTT(Park) enable: set MR5[8:6] 000 (disabled).
3. Auto self refresh (ASR): set MR2[6] 0 to disable or MR2[6] 1 to enable feature.
4. Self refresh temperature range (SRT): set MR2[7] 0 for normal or MR2[7] 1 for extended temperature range.
5. READ burst type: Nibble sequential, set MR0[3] 0.
6. In the dual-rank DDP case, note the following I DD measurement considerations:
For all IDD measurements except IDD6 , the unselected rank should be in an IDD2P condition.
For all IPP measurements except IPP6 , the unselected rank should be in an IDD3N condition.
For all IDD6 /IPP6 measurements, both ranks should be in the same I DD6 condition.
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MD4C1001G-N43R
7. When measuring IDD9 /IPP9 after entering MBIST-PPR mode and ALERT_N driving LOW, there is a chance that the DRAM may
perform an internal hPPR if fails are found after internal self-test is completed and before ALERT_N fires HIGH.
Table 7 IDD, IPP, and IDDQ Current Limits
TC = 0°C to +95°C
Symbol
DDR4
Unit
IDD0: One bank ACTIVATE-to-PRE-CHARGE current
56
mA
IPP0: One bank ACTIVATE-to-PRE-CHARGE IPP current
4
mA
IDD1: One bank ACTIVATE-to-READ-to-PRECHARGE current
83
mA
IDD2N: Precharge standby current
34
mA
IDD2NT: Precharge standby ODT current
57
mA
IDD2P: Precharge power-down current
25
mA
IDD2Q: Precharge quiet standby current
27
mA
IDD3N: Active standby current
46
mA
IPP3N: Active standby IPP current
3
mA
IDD3P: Active power-down current
35
mA
IDD4R: Burst read current
322
mA
IDD4W: Burst write current
258
mA
IDD5R: Distributed refresh current (1XREF)
70
mA
IPP5R: Distributed refresh IPP current(1XREF)
5
mA
IDD6N: Self refresh current 1
34
mA
current 2
58
mA
21
mA
IDD6A: Auto self refresh current, 25°C 4
8.6
mA
IDD6A: Auto self refresh current, 45°C
4
21
mA
IDD6A: Auto self refresh current, 75°C 4
31
mA
I DD6A: Auto self refresh current, 95°C 4
58
mA
IPP6x: Auto self refresh current 23
5
mA
IDD7: Bank interleave read current
270
mA
IPP7: Bank interleave read IPP current
18
mA
IDD8: Maximum power-down current
18
mA
IDD6E: Self refresh
IDD6R: Self refresh current 3, 4
Notes:
1. Applicable for MR2 settings A7 = 0 and A6 = 0; Manual mode with normal temperature range of operation (–40–85°C).
2. Applicable for MR2 settings A7 = 1 and A6 = 0; Manual mode with extended temperature range of operation (–40–95°C).
3. Applicable for MR2 settings A7 = 0 and A6 = 1; Manual mode with reduced temperature range of operation (–40–45°C).
4. IDD6E, IDD6R, and IDD6A values are verified by design and characterization, and may not be subject to production test.
5. When additive latency is enabled for IDD0, current changes by approximately 1%.
6. When additive latency is enabled for IDD1 , current changes by approximately +8% (x8), +7% (x16).
7. When additive latency is enabled for IDD2N , current changes by approximately +1%.
8. When DLL is disabled for IDD2N , current changes by approximately –6%.
9. When CAL is enabled for IDD2N , current changes by approximately –30%.
10. When gear-down is enabled for IDD2N , current changes by approximately 0%.
11. When CA parity is enabled for IDD2N , current changes by approximately +10%.
12. When additive latency is enabled for IDD3N, current changes by approximately +1%.
13. When additive latency is enabled for IDD4R, current changes by approximately +4%.
14. When read DBI is enabled for IDD4R, current changes by approximately –14%.
15. When additive latency is enabled for IDD4W, current changes by approximately +3% (x8), +4% (x16).
16. When write DBI is enabled for IDD4W, current changes by approximately –20%.
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17. When write CRC is enabled for IDD4W, current changes by approximately –5% (x8), –5%(x16).
18. When CA parity is enabled for IDD4W, current changes by approximately +12% (x8), +12% (x16).
19. When 2X REF is enabled for IDD5R, current changes by approximately 0%.
20. When 4X REF is enabled for IDD5R, current changes by approximately 0%.
21. When 2X REF is enabled for IPP5R, current changes by approximately 0%.
22. When 4X REF is enabled for IPP5R , current changes by approximately 0%.
23. IPP0 test and limit is applicable for IDD0 and IDD1 conditions.
24. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x, and IDD8 conditions; That is, testing IPP3N should satisfy the
IPPs for the noted IDD tests.
25. IPP6x is applicable to IDD6N, IDD6E, IDD6R, and IDD6A conditions.
26. When TC < 0°C: IDD2P and IDD3P must be derated by 6%; IDD4R and IDD4W must be derated by 4%; IDD6, IDD6E, and IDD7
must be derated by 11%.
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MD4C1001G-N43R
4. Input / Output Capacitance
Table 8 Input/Output Capacitance
Symbol
Min.
Max.
Input/output capacitance: DQ, DM, DQS_t, DQS_c, TDQS_t, TDQS_c
CIO
0.55
1.15
1, 2, 3
Input capacitance: CK_t and CK_c
CCK
0.2
0.7
1, 2, 3, 4
CDCK
0
0.05
1, 2, 3, 5
Input/output capacitance delta: DQS_t and DQS_c
CDDQS
0
0.05
1, 3
Input capacitance: CTRL, ADD, CMD input-only pins
CI
0.2
0.7
Parameter
Input capacitance delta: CK_t and CK_c
Input capacitance delta: All CTRL input-only pins
Input capacitance delta: All ADD/CMD input-only pins
Input/output capacitance delta: DQ, DM, DQS_t, DQS_c, TDQS_t, TDQS_c
Input/output capacitance: ALERT pin
Input/output capacitance: ZQ pin
Unit
Notes
1, 3, 6
pF
CDI_CTRL
-0.1
0.1
1, 3, 7
CDI_ADD_C
MD
-0.1
0.1
1, 3, 8, 9
CDIO
-0.1
0.1
1, 2, 10, 11
CALERT
0.5
1.5
1, 3
CZQ
0.5
2.3
1, 3, 12
Notes:
1. Although the DM, TDQS_t, and TDQS_c pins have different functions, the loading matches DQ and DQS.
2. This parameter is not subject to a production test; It is verified by design and characterization. The capacitance is measured
according to the JEP147 specification, “Procedure for Measuring Input Capacitance Using a Vector Network Analyzer (VNA),”
with VDD, VDDQ, VSS, and VSSQ applied and all other pins floating (except the pin under test, CKE, RESET_n and ODT,
asnecessary). VDD = VDDQ = 1.5V, VBIAS = VDD/2 and on-die termination off.
3. This parameter applies to monolithic die, obtained by de-embedding the package L and C parasitics.
4. CDIO = CIO(DQ, DM) - 0.5 × (CIO(DQS_t) + CIO(DQS_c)).
5. Absolute value of CIO (DQS_t), CIO (DQS_c)
6. Absolute value of CCK_t, CCK_c
7. CI applies to ODT, CS_n, CKE, A[15:0], BA[1:0], RAS_n, CAS_n, and WE_n.
8. CDI_CTRL applies to ODT, CS_n, and CKE.
9. CDI_CTRL = CI(CTRL) - 0.5 × (CI (CLK_t) + CI(CLK_c)).
10. CDI_ADD_CMD applies to A[15:0], BA1:0], RAS_n, CAS_n and WE_n.
11. CDI_ADD_CMD = CI (ADD_CMD) - 0.5 × (CI (CLK_t) + CI (CLK_c)).
12. Maximum external load capacitance on ZQ pin: 5pF.
13. Only applicable if TEN pin does not have an internal pull-up
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5. Absolute Maximum DC Ratings
Stresses greater than those listed may cause permanent damage to the device. This is astress rating
only, and functional operation of the device at these or any other conditions outside those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may adversely affect reliability. Although "unlimited" row accesses to the
same row is allowed within the refresh period; excessive row accesses to the same row over a long term
can result in degraded operation.
Table 9 Absolute Maximum DC Ratings
Symbol
Parameter
Min.
Max.
Unit
Notes
VDD
Voltage on VDD pin relative to VSS
-0.4
1.5
V
1
VDDQ
Voltage on VDDQ pin relative to VSS
-0.4
1.5
V
1
VPP
Voltage on VPP pin relative to VSS
-0.4
3.0
V
3
VIN, VOUT
Voltage on any pin relative to VSS
-0.4
1.5
V
TSTG
Storage temperature
-55
150
°C
2
Notes:
1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be greater than 0.6 × V DDQ . When VDD
and VDDQ are
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