Tentative Product Specification
- MIE3XXXCH7AQ –
- MWE3XXXCH7AQ –
(eMMC 5.1)
-Support HS400-
Document Number: E22016 (Version 1.1)
Metorage Semiconductor Technology Co.,Ltd.
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CH7AQ Series
History of Specification Change
Revision
History
Date
Author
Preliminary version
2022/08/05
Fang
1.1
Update Chapter 5
2022/10/24
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1.0
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Requirement and Notice
This product is provided "as is", and Metorage does not make any other guarantees (whether express,
implied, statutory or otherwise) with respect to this product or any part of it. Metorage expressly denies any
implied warranties of marketability, suitability for specific uses, and non-infringement.
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1) The products described in this specification refer to the electronic equipment used in vehicles
(navigation, driving recorders, AV equipment, etc.)
If you have special quality and reliability requirements, product failure or misuse may directly endanger
life safety and human health for special uses (aviation, aerospace, transportation equipment,
combustion equipment, life support devices, safety devices, etc.) requirements, or consider to use other
than our standard use, please contact us to discuss in detail.
2) Please use within the product guarantee range (especially the working voltage range and temperature
range). Metorage will not be responsible for all failures of the machine if it exceeds these specifications.
In addition, even if it is used within these specifications, please pay attention to avoid infringement of
various laws and regulations due to the operation of our products.
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3) Please avoid tearing off the label attached to the product of this specification and / or changing the
label, as doing so may damage the characteristics and / or quality of the product.
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4) It is forbidden to copy, photocopy, translate or restore all or part of this document to anyone without
Metorage written permission by using electronic media or machine-readable form.
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Product Overview
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Support JEDEC eMMC 5.1 compliant
Compliant with eMMC Specification Ver. 4.3, 4.4, 4.41, 4.5, 4.51, 5.0,5.1
Bus mode
Clock frequency ：0-200MHz
12 wire bus (clock, command, 8-bit data bus, data strobe and hardware reset)
Support three different data bus widths ： 1-bit, 4-bit, 8-bit
Data transfer rate： up to 52Mbyte/s (using 8 parallel data lines at 52MHz)
Single data rate ： up to 200Mbyte/s @200MHz
Dual data rate ： up to 400Mbyte/s @200MHz
Operating voltage range：
VCCQ = 1.8V/3.3V
VCC = 3.3V
Error free memory access
Internal error correction code (ECC) to protect data communication
Security
Support secure erase/trim commands
Support Replay Protected Memory Block (RPMB)
Support Field Firmware Update(FFU)
Support Lock/Unlock
Support Data Protection for Power Failure
Support Power Saving Sleep Mode
Support High Priority Interrupt(HPI)
Support Packed Commands
Support Sampling Tuning Sequence
Support Enhanced Strobe Mode
Support Production State Awareness(PSA)
Multiple Densities and Packages
153-ball standard BGA packages
RoHS Compliant
NAND Density
MI:16/32/64/128GB
MW:16/32/64/128GB
Temperature range (Ta)
Operation：
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-25℃~85℃ (MI)
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-40℃~85℃ (MW)
Storage：
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-40℃~85℃
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Table of Contents
1 Introduction ...................................................................................................................................................... 7
2 eMMC Device and System ............................................................................................................................... 8
2.1 eMMC System Overview ......................................................................................................................... 8
2.2 eMMC Device Overview ......................................................................................................................... 8
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2.2.1 Clock (CLK) ..................................................................................................................................................... 8
2.2.2 Data Strobe (DS)............................................................................................................................................ 8
2.2.3 Command (CMD) ........................................................................................................................................... 9
2.2.4 Input/Outputs (DAT0-DAT7) ......................................................................................................................... 9
2.3 Bus Protocol .......................................................................................................................................... 10
2.4 Bus Speed Modes.................................................................................................................................. 10
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2.4.1 HS200 Bus Speed Mode ................................................................................................................................ 10
2.4.2 HS200 System Block Diagram...................................................................................................................... 11
2.4.3 HS400 Bus Speed mode ............................................................................................................................... 11
2.4.4 HS400 System Block Diagram ..................................................................................................................... 11
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3 eMMC Functional Description........................................................................................................................12
3.1 eMMC Overview .....................................................................................................................................12
3.2 Boot Operation Mode............................................................................................................................12
3.3 Device Identification Mode ...................................................................................................................12
3.4 Interrupt Mode ......................................................................................................................................12
3.5 Data Transfer Mode...............................................................................................................................12
3.6 Inactive Mode.........................................................................................................................................12
3.7 H/W Reset Operation .............................................................................................................................13
3.8 Noise Filtering Timing for H/W Reset ..................................................................................................13
3.9 Field Firmware Update(FFU) ............................................................................................................... 14
3.10 Power off Notification for sleep ........................................................................................................ 14
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4 Register Settings ............................................................................................................................................ 16
4.1 OCR Register.......................................................................................................................................... 16
4.2 CID Register ........................................................................................................................................... 16
4.3 CSD Register.......................................................................................................................................... 16
4.4 Extended CSD Register .........................................................................................................................17
4.5 RCA Register.......................................................................................................................................... 23
4.6 DSR Register .........................................................................................................................................24
5 The eMMC bus ................................................................................................................................................ 25
5.1 Power-up ................................................................................................................................................ 25
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5.1.1 eMMC power-up ............................................................................................................................................25
5.1.2 eMMC Power Cycling ................................................................................................................................... 26
5.2 Bus Operating Condition ...................................................................................................................... 27
5.2.1 Power supply： eMMC ................................................................................................................................. 27
5.2.2 eMMC Power Supply Voltage...................................................................................................................... 28
5.2.3 Bus Signal Line Load .................................................................................................................................... 28
5.2.4 HS400 reference load.................................................................................................................................. 29
5.3 Bus Signal Levels ................................................................................................................................... 30
5.3.1 Open-drain Mode Bus Signal Level .............................................................................................................. 30
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5.3.2 Push-pull mode bus signal level — eMMC .................................................................................................. 30
5.3.3 Bus Operating Conditions for HS200 & HS400............................................................................................ 31
5.3.4 Device Output Driver Requirements for HS200 & HS400 ........................................................................... 31
5.4 Bus Timing ..............................................................................................................................................31
5.4.1 Device Interface Timings .............................................................................................................................. 31
5.5 Bus Timing for DAT Signals During Dual Data Rate Operation ......................................................... 33
5.5.1 Dual Data Rate Interface Timings ................................................................................................................33
5.6 Bus Timing Specification in HS200 Mode ...........................................................................................34
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5.6.1 HS200 Clock Timing..................................................................................................................................... 34
5.6.2 HS200 Device Input Timing..........................................................................................................................35
5.6.3 HS200 Device Output Timing .......................................................................................................................35
5.7 Bus Timing Specification in HS400 mode ........................................................................................... 37
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5.7.1 HS400 Device Input Timing ..........................................................................................................................37
5.7.2 HS400 Device Output Timing ...................................................................................................................... 38
6 Package connections ..................................................................................................................................... 39
7 Ball Assignment (153 ball).............................................................................................................................. 41
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8 Marking...........................................................................................................................................................42
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9 Appendix.........................................................................................................................................................42
9.1 Endurance characteristic ...................................................................................................................... 42
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1 Introduction
Metorage eMMC products is a highly integrated solution which combines a feature-wise flash controller and standard
NAND flash memory. Its high performance and low power make the Metorage eMMC products a fabulous solution
for embedded and portable applications.
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The Metorage eMMC products leverages industry leading technology and experience in NAND management. In
addition, the Metorage eMMC products supports the standard eMMC interface as well as the newly introduced
eMMC features such as HS400 mode and FFU. By integrating all the advanced techniques, the Metorage eMMC
products is able to further enhance the data transferring efficiency and optimizes the overall performance for
embedded systems.
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Available in various densities, the Metorage eMMC products offers the features, performance, and flexibility exactly
for mobile handset, navigation, automotive infotainment, multi-function printer, and next-generation consumer
applications. With extended temperature support and high data reliability, offering easy and rapid design integration,
the Metorage eMMC products also ideally fits the requirements of point-of-sale terminals, networking and
telecommunications equipment, and a variety of leading-edge industrial applications.
Table 1-1 Product Part Number
NAND Density
Package
Operating voltage
MIE3016CH7
16GB
BGA153
VCC=3.3V VCCQ=1.8V/3.3V
MIE3032CH7
32GB
BGA153
VCC=3.3V VCCQ=1.8V/3.3V
MIE3064CH7
64GB
BGA153
VCC=3.3V VCCQ=1.8V/3.3V
MIE3128CH7
128GB
BGA153
VCC=3.3V VCCQ=1.8V/3.3V
16GB
BGA153
VCC=3.3V VCCQ=1.8V/3.3V
32GB
BGA153
VCC=3.3V VCCQ=1.8V/3.3V
64GB
BGA153
VCC=3.3V VCCQ=1.8V/3.3V
128GB
BGA153
VCC=3.3V VCCQ=1.8V/3.3V
MWE3064CH7
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Product Part Number
Table 1-2 Read/Write Performance
Products
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MIE3016CH7
MIE3032CH7
MIE3064CH7
MIE3128CH7
MWE3016CH7
MWE3032CH7
MWE3064CH7
MWE3128CH7
Typical value
Read Sequential (MB/s)
Write Sequential (MB/s)
220
178
178
178
220
178
178
178
48
26
45
63
48
26
45
63
Note 1： Values given for an 8-bit bus width, running HS400 mode from tool, VCC=3.3V,VCCQ=1.8V.
Note 2： Performance numbers might be subject to changes without notice.
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Table 1-3 User Density Size
Device
User Density
16GB
32GB
64GB
128GB
15099904 KBytes
30535680 KBytes
61071360 KBytes
122142720 KBytes
Table 1-4 Capacity according to partition
Boot partition 2
16GB
32GB
64GB
128GB
4096 KB
4096 KB
4096 KB
4096 KB
4096 KB
4096 KB
4096 KB
4096 KB
RPMB
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Boot partition 1
4096 KB
4096 KB
4096 KB
4096 KB
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Capacity
2 eMMC Device and System
2.1 eMMC System Overview
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System Performance The eMMC specification covers the behavior of the interface and the Device controller. As part
of this specification the existence of a host controller and a memory storage array are implied but the operation of
these pieces is not fully specified.
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Metorage NAND Device consists of a single chip MMC controller and NAND flash memory module. The microcontroller interfaces with a host system allowing data to be written to and read from the NAND flash memory
module. The controller allows the host to be independent from details of erasing and programming the flash memory.
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Figure 2-1 eMMC System Overview
2.2 eMMC Device Overview
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The eMMC device transfers data via a configurable number of data bus signals. The communication signals are:
2.2.1 Clock (CLK)
Each cycle of this signal directs a one bit transfer on the command and either a one bit (1x) or a two bits transfer (2x)
on all the data lines. The frequency may vary between zero and the maximum clock frequency.
2.2.2 Data Strobe (DS)
This signal is generated by the device and used for output in HS400 mode. The frequency of this signal follows the
frequency of CLK. For data output each cycle of this signal directs two bits transfer(2x) on the data - one bit for
positive edge and the other bit for negative edge. For CRC status response output and CMD response output
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(enabled only HS400 enhanced strobe mode), the CRC status is latched on the positive edge only, and don't care on
the negative edge.
2.2.3 Command (CMD)
This signal is a bidirectional command channel used for Device initialization and transfer of commands. The CMD signal
has two operation modes: open-drain for initialization mode, and push-pull for fast command transfer. Commands
are sent from the eMMC host controller to the eMMC Device and responses are sent from the Device to the host.
2.2.4 Input/Outputs (DAT0-DAT7)
CLK
I
DAT0-DAT7
I/O
CMD
I/O
RST_n
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Description
Clock
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Table 2-1 Communication Interface
VCC
VCCQ
VSSQ
RCLK
CMD
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RFU
Data
Command/Response
Hardware reset
S
Supply voltage for Core
S
Supply voltage for I/O
S
Supply voltage ground for Core
S
Supply voltage ground for I/O
O
eMMC interface Data strobe
I/O
Command/Response
--
Internal voltage node
O
UART Tx output for debug use
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No connect
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Reserved for future use.
Leave it floating
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These are bidirectional data channels. The DAT signals operate in push-pull mode. Only the Device or the host is driving
these signals at a time. By default, after power up or reset, only DAT0 is used for data transfer. A wider data bus can
be configured for data transfer, using either DAT0-DAT3 or DAT0- DAT7, by the eMMC host controller. The eMMC
Device includes internal pull-ups for data lines DAT1- DAT7. Immediately after entering the 4-bit mode, the Device
disconnects the internal pull-ups of lines DAT1, DAT2, and DAT3. Correspondingly, immediately after entering to the
8-bit mode the Device disconnects the internal pull-ups of lines DAT1–DAT7.
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Note 1：I: input; O: output; S: power supply.
Note 2： VDDi: A 1.0uF capacitor is required for VDDi for core power stabilization. Do not tie to supply voltage or ground.
Name
Description
RCA
2
DSR
2
Device Identification number, an individual number for identification.
Relative Device Address is the Device system address, dynamically
assigned by the host during initialization.
Driver Stage Register, to configure the Device’s output drivers.
CSD
16
Device Specific Data, information about the Device operation conditions.
OCR
4
EXT_CSD
512
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CID
Width
(Bytes)
16
Table 2-2 eMMC Registers
Operation Conditions Register. Used by a special broadcast command to
identify the voltage type of the Device.
Extended Device Specific Data. Contains information about the Device
capabilities and selected modes. Introduced in standard v4.0
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Implementation
Mandatory
Mandatory
Mandatory
Optional
Mandatory
Mandatory
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The host may reset the device by：
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Switching the power supply off and back on. The device shall have its own power-on
detection circuitry which puts the device into a defined state after the power-on Device.
A reset signal
By sending a special command
2.3 Bus Protocol
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After a power-on reset, the host must initialize the device by a special message-based eMMC bus protocol. For
more details, refer to section 5.3.1 of the JEDEC Standard Specification No.JESD84-B51.
2.4 Bus Speed Modes
eMMC defines several bus speed modes as shown in Table 2-3.
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Table 2-3 Bus Speed Mode
Data Rate
IO
Voltage
Bus Width
Frequency
Max Data Transfer
(implies x8 bus width)
Backwards Compatibility
with legacy MMC card
Single
3.3/1.8V
1, 4, 8
0-26MHz
26MB/s
High Speed SDR
Single
3.3/1.8V
4, 8
0-52MHz
52MB/s
High Speed DDR
Dual
3.3/1.8V
4, 8
0-52MHz
104MB/s
HS200
Single
1.8V
4, 8
0-200MHz
200MB/s
HS400
Dual
1.8V
8
0-200MHz
400MB/s
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2.4.1 HS200 Bus Speed Mode
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Mode Name
The HS200 mode offers the following features：
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SDR Data sampling method
CLK frequency up to 200MHz Data rate – up to 200MB/s
4 or 8-bits bus width supported
Single ended signaling with 4 selectable Drive Strength
Signaling levels of 1.8V
Tuning concept for Read Operations
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2.4.2 HS200 System Block Diagram
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Figure 2-2 shows a typical HS200 Host and Device system. The host has a clock generator, which supplies CLK to the
Device. For write operations, clock and data direction are the same, write data can be transferred synchronous
with CLK, regardless of transmission line delay. For read operations, clock and data direction are opposite; the read
data received by Host is delayed by round-trip delay, output delay and latency of Host and Device. For reads, the
Host needs to have an adjustable sampling point to reliably receive the incoming data.
2.4.3 HS400 Bus Speed mode
The HS400 mode has the following features：
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DDR Data sampling method
CLK frequency up to 200MHz, Data rate is – up to 400MB/s
Only 8-bit bus width supported
Signaling levels of 1.8V
Support up to 5 selective Drive Strength
Data strobe signal is toggled only for Data out and CRC response
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Figure 2-2 System Block Diagram
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2.4.4 HS400 System Block Diagram
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Figure 2-3 shows a typical HS400 Host and Device system. The host has a clock generator, which supplies CLK to the
Device. For read operations, Data Strobe is generated by device output circuit. Host receives the data which is aligned to
the edge of Data Strobe.
Figure 2-3 HS400 Host and Device block diagram
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3 eMMC Functional Description
CH7AQ Series
3.1 eMMC Overview
All communication between host and device are controlled by the host (main chip). The host sends a command,
which results in a device response. For more details, refer to section 6.1 of the JEDEC Standard Specification
No.JESD84-B51.
Five operation modes are defined for the eMMC system：
Boot operation mode
Device identification mode
Interrupt mode
Data transfer mode
Inactive mode
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3.2 Boot Operation Mode
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In boot operation mode, the master (eMMC host) can read boot data from the slave (eMMC device) by keeping
CMD line low or sending CMD0 with argument + 0xFFFFFFFA, before issuing CMD1. The data can be read from
either boot area or user area depending on register setting. For more details, refer to section 6.3 of the JEDEC
Standard Specification No.JESD84-B51.
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3.3 Device Identification Mode
3.4 Interrupt Mode
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While in device identification mode the host resets the device, validates operation voltage range and access mode,
identifies the device and assigns a Relative Device Address (RCA) to the device on the bus. All data communication
in the Device Identification Mode uses the command line (CMD) only. For more details, refer to section 6.4 of the
JEDEC Standard Specification No.JESD84-B51.
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The interrupt mode on the eMMC system enables the master (eMMC host) to grant the transmission allowance to
the slaves (Device) simultaneously. This mode reduces the polling load for the host and hence, the power
consumption of the system, while maintaining adequate responsiveness of the host to a Device request for service.
Supporting eMMC interrupt mode is an option, both for the host and the Device. For more details, refer to section
6.5 of the JEDEC Standard Specification No.JESD84-B51.
3.5 Data Transfer Mode
When the Device is in Stand-by State, communication over the CMD and DAT lines will be performed in push-pull
mode. For more details, refer to section 6.6 of the JEDEC Standard Specification No.JESD84-B51.
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3.6 Inactive Mode
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The device will enter inactive mode if either the device operating voltage range or access mode is not valid. The
device can also enter inactive mode with GO_INACTIVE_STATE command (CMD15). The device will reset to Pre-idle
state with power cycle. For more details, refer to section 6.1 of the JEDEC Standard Specification No.JESD84-B51.
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3.7 H/W Reset Operation
Figure 3-1 H/W Reset Waveform
Note 1： Device will detect the rising edge of RST_n signal to trigger internal reset sequence.
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Table 3-1 H/W Reset Timing Parameters
Comment
tRSTW
RST_n pulse width
tRSCA
RST_n to Command time
tRSTH
RST_n high period (interval time)
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Symbol
Min
Max
Unit
1
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[us]
2001
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[us]
1
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[us]
Note: 74 cycles of clock signal required before issuing CMD1 or CMD0 with argument 0xFFFFFFFA.
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3.8 Noise Filtering Timing for H/W Reset
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Device must filter out 5ns or less pulse width for noise immunity
Figure 3-2 Noise Filtering Timing for H/W Reset
Device must not detect these rising edge.
Device must not detect 5ns or less of positive or negative RST_n pulse.
Device must detect more than or equal to 1us of positive or negative RST_n pulse width.
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3.9 Field Firmware Update(FFU)
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Field Firmware Updates (FFU) enables features enhancement in the field. Using this mechanism the host
downloads a new version of the firmware to the eMMC device and, following a successful download, instructs the
eMMC device to install the new downloaded firmware into the device.
In order to start the FFU process the host first checks if the eMMC device supports FFU capabilities by reading
SUPPPORTED_MODES and FW_CONFIG fields in the EXT_CSD. If the eMMC device supports the FFU feature the
host may start the FFU process. The FFU process starts by switching to FFU Mode in MODE_CONFIG field in the
EXT_CSD. In FFU Mode host should use closed-ended or open ended commands for downloading the new
firmware and reading vendor proprietary data. In this mode, the host should set the argument of these commands
to be as defined in FFU_ARG field. In case these commands have a different argument the device behavior is not
defined and the FFU process may fail. The host should set Block Length to be DATA_SECTOR_SIZE. Downloaded
firmware bundle must be DATA_SECTOR_SIZE size aligned (internal padding of the bundle might be
required).Once in FFU Mode the host may send the new firmware bundle to the device using one or more write
commands.
The host could regain regular functionality of write and read commands by setting MODE_CONFIG field in the
EXT_CSD back to Normal state. Switching out of FFU Mode may abort the firmware download operation. When
host switched back to FFU Mode, the host should check the FFU Status to get indication about the number of
sectors which were downloaded successfully by reading the
NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED in the extended CSD. In case the number of sectors
which were downloaded successfully is zero the host should re-start downloading the new firmware bundle from
its first sector. In case the number of sectors which were downloaded successfully is positive the host should
continue the download from the next sector, which would resume the firmware download operation.
In case MODE_OPERATION_CODES field is not supported by the device the host sets to NORMAL state and
initiates a CMD0/HW_Reset/Power cycle to install the new firmware. In such case the device doesn’t need to use
NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED.
In both cases occurrence of a CMD0/HW_Reset/Power occurred before the host successfully downloaded the new
firmware bundle to the device may cause the firmware download process to be aborted.
3.10 Power off Notification for sleep
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The host should notify the device before it powers the device off. This allows the device to better prepare itself for
being powered off. Power the device off means to turn off all its power supplies. In particular, the host should
issue a power off notification (POWER_OFF_LONG, POWER_OFF_SHORT ) if it intends to turn off both VCC and
VCCQ power supplies or it may use to a power off notification (SLEEP_NOTIFICATION ) if it intends to turn-off VCC
after moving the device to Sleep state.
To indicate to the device that power off notification is supported by the host, a supporting host shall first set the
POWER_OFF_NOTIFICATION byte in EXT_CSD [34] to POWERED_ON (0x01). To execute a power off, before
powering the device down the host will changes the value to either POWER_OFF_SHORT (0x02) or
POWER_OFF_LONG (0x03). Host should waits for the busy line to be de-asserted. Once the setting has changed to
either 0x02 or 0x03, host may safely power off the device.
The host may issue SLEEP_AWAKE (CMD5) to enter or to exit from Sleep state if POWER_OFF_NOTIFICATION byte
is set to POWERED_ON. Before moving to Standby state and then to Sleep state, the host sets
POWER_OFF_NOTIFICATION to SLEEP_NOTIFICATION and waits for the DAT0 line de-assertion. While in Sleep (slp)
state VCC (Memory supply) may be turned off as defined in 4.1.6. Removing power supplies other than VCC while
the device is in the Sleep (slp) state may result in undefined device behavior. Before removing all power supplies,
the host should transition the device out of Sleep (slp) state back to Transfer state using CMD5 and CMD7 and then
execute a power off notification setting POWER_OFF_NOTIFICATION byte to either POWER_OFF_SHORT or
POWER_OFF_LONG.
If host continues to send commands to the device after switching to the power off setting (POWER_OFF_LONG,
POWER_OFF_SHORT or SLEEP_NOTIFICATION) or performs HPI during its busy condition, the device shall restore
the POWER_OFF_NOTIFICATION byte to POWERED_ON.
If host tries to change POWER_OFF_NOTIFICATION to 0x00 after writing another value there, a SWITCH_ERROR is
generated.
The difference between the two power-off modes is how urgent the host wants to turn power off. The device
should respond to POWER_OFF_SHORT quickly under the generic CMD6 timeout. If more time is acceptable,
POWER_OFF_LONG may be used and the device shall respond to it within the POWER_OFF_LONG_TIME timeout.
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While POWER_OFF_NOTIFICATION is set to POWERED_ON, the device expects the host to host shall：
•
Keep the device power supplies alive (both VCC and VCCQ) and in their active mode
• Not power off the device intentionally before changing POWER_OFF_NOTIFICATION to either
POWER_OFF_LONG or POWER_OFF_SHORT
• Not power off VCC intentionally before changing POWER_OFF_NOTIFICATION to SLEEP_NOTIFICATION and
before moving the device to Sleep state
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Before moving to Sleep state hosts may set the POWER_OFF_NOTIFICATION byte to SLEEP_NOTIFICATION (0x04)
if aware that the device is capable of autonomously initiating background operations for possible performance
improvements. Host should wait for the busy line to be de-asserted. Busy line may be asserted up the period
defined in SLEEP_NOTIFICATION_TIME byte in EXT_CSD [216]. Once the setting has changed to 0x04 host may set
the device into Sleep mode (CMD7+CMD5). After getting out from Sleep the POWER_OFF_NOTIFICATION byte will
restore its value to POWERED_ON. HPI may interrupt the SLEEP_NOTIFICATION operation. In that case
POWER_OFF_NOTIFICATION byte will restore to POWERED_ON.
15
Confidential Tentative
4 Register Settings
CH7AQ Series
Within the Device interface six registers are defined: OCR, CID, CSD, EXT_CSD, RCA and DSR. These can be accessed
only by corresponding commands (see Section 6.10 of JESD84-B51).
4.1 OCR Register
The 32-bit operation conditions register (OCR) stores the VDD voltage profile of the Device and the access mode
indication. In addition, this register includes a status information bit. This status bit is set if the Device power up
procedure has been finished. The OCR register shall be implemented by all Devices.
Table 4-1 OCR Register fields
tia
l
OCR Register
Definitions OCR bit
[31]
nf
id
en
VDD voltage window
Value
(Device power up status bit(busy) (Note1)
00b(byte mode)
[30:29]
Access Mode
10b(sector mode)
[28:24]
Reserved
[23:15]
2.7-3.6V
111111111b
[14:8]
2.0-2.6V
0000000b
[7]
1.7-1.95V
1b
[6:0]
Reserved
Note: This bit is set to LOW if the Device has not finished the power up routine.
4.2 CID Register
The Card Identification (CID) register is 128 bits wide. It contains the Device identification information used during
the Device identification phase (eMMC protocol). For details, refer to JEDEC Standard Specification No.JESD84-B51
Co
Table 4-2 CID Register fields
or
ag
e
CID Fields Name
Field
Width
Manufacturer ID
MID
8
Reserved
6
Device/BGA
CBX
2
OEM/Application ID
OID
8
Product name
PNM
48
Product revision
PRV
8
Product serial number
PSN
32
MDT
8
Manufacturing data
CRC7 checksum
CRC
7
Not used, always “1”
1
Note: The description are same as eMMC™ JEDEC standard.
CID slice
[127:120]
[119:114]
[113:112]
[111:104]
[103:56]
[55:48]
[47:16]
[15:8]
[7:1]
[0]
Value
C4h
1h
FFh
4D45544F5241h
Random by Production
month, year
- (Note 1)
1h
et
4.3 CSD Register
M
The Card-Specific Data (CSD) register provides information on how to access the contents stored in eMMC. The CSD
registers are used to define the error correction type, maximum data access time, data transfer speed, data
format…etc. For details, refer to section 7.3 of the JEDEC Standard Specification No.JESD84- B51.
Name
CSD structure
System specification version
Reserved
Data read access-time 1
Table 4-3 CSD Register fields
Field
CSD_STRUCTURE
SPEC_VERS
TAAC
16
Width
2
4
2
8
CSD-slice
[127:126]
[125:122]
[121:120]
[119:112]
Value
3h
4h
2Fh
Confidential Tentative
CH7AQ Series
8
[111:104]
1h
TRAN_SPEED
CCC
READ_BL_LEN
READ_BL_PARTIAL
WRITE_BLK_MISALIGN
READ_BLK_MISALIGN
DSR_IMP
C_SIZE
VDD_R_CURR_MIN
VDD_R_CURR_MAX
VDD_W_CURR_MIN
VDD_W_CURR_MAX
C_SIZE_MULT
ERASE_GRP_SIZE
ERASE_GRP_MULT
WP_GRP_SIZE
WP_GRP_ENABLE
DEFAULT_ECC
R2W_FACTOR
WRITE_BL_LEN
WRITE_BL_PARTIAL
CONTENT_PROT_APP
FILE_FORMAT_GRP
COPY
PERM_WRITE_PROTECT
TMP_WRITE_PROTECT
FILE_FORMAT
ECC
CRC
-
8
12
4
1
1
1
1
2
12
3
3
3
3
3
5
5
5
1
2
3
4
1
4
1
1
1
1
1
2
2
7
1
[103:96]
[95:84]
[83:80]
[79]
[78]
[77]
[76]
[75:74]
[73:62]
[61:59]
[58:56]
[55:53]
[52:50]
[49:47]
[46:42]
[41:37]
[36:32]
[31]
[30:29]
[28:26]
[25:22]
[21]
[20:17]
[16]
[15]
[14]
[13]
[12]
[11:10]
[9:8]
[7:1]
[0:0]
2Ah
DF5h
9h
0h
0h
0h
0h
FFFh
6h
6h
6h
6h
7h
1Fh
1Fh
1Fh
1h
0h
1h
9h
0h
0h
0h
0h
0h
0h
0h
0h
1h
Co
nf
id
en
tia
l
NSAC
or
ag
e
Data read access-time2 in CLK
cycle(NSAC*100)
Max. bus clock frequency
Device command classes
Max. read data block length
Partial blocks for read allowed
Write block misalignment
Read block misalignment
DSR implemented
Reserved
Device size
Max. read current @ VDD min
Max. read current @ VDD max
Max. write current @ VDD min
Max. write current @ VDD max
Device size multiplier
Erase group size
Erase group size multiplier
Write protect group size
Write protect group enable
Manufacturer default ECC
Write speed factor
Max. write data block length
Partial blocks for write allowed
Reserved
Content protection application
File format group
Copy flag (OTP)
Permanent write protection
Temporary write protection
File format
ECC code
CRC
Not used, always ’1’
4.4 Extended CSD Register
M
et
The Extended CSD register defines the Device properties and selected modes. It is 512 bytes long. The most
significant 320 bytes are the Properties segment, which defines the Device capabilities and cannot be modified by
the host. The lower 192 bytes are the Modes segment, which defines the configuration the Device is working in.
These modes can be changed by the host by means of the SWITCH command. For details, refer to section 7.4 of the
JEDEC Standard Specification No.JESD84-B51.
Name
Table 4-4 Extended CSD Register fields
Field
Size (Bytes)
CSD-slice
Value
Properties Segment
Reserved
-
6
[511:506]
-
Extended Security
Commands Error
EXT_SECURITY_ERR
1
[505]
0h
Supported Command Sets
S_CMD_SET
1
[504]
01h
17
Confidential Tentative
HPI features
CH7AQ Series
HPI_FEATURES
1
[503]
03h
BKOPS_SUPPORT
1
[502]
01h
MAX_PACKED_READS
1
[501]
3Fh
MAX_PACKED_WRITES
1
[500]
3Fh
Data Tag Support
DATA_TAG_SUPPORT
1
[499]
01h
Tag Unit Size
TAG_UNIT_SIZE
1
[498]
01h
[497]
0h
[496]
05h
[495]
0h
[494]
03h
1
[493]
01h
1
[492]
01h
1
[491]
17h
4
[490:487]
0h
1
[486]
0h
177
[485:309]
-
1
[308]
0h
Background operations
support
Max packed read
commands
Max packed write
Commands
TAG_RES_SIZE
1
CONTEXT_CAPABILITIES
1
Large Unit size
LARGE_UNIT_SIZE_M1
1
Extended partitions
attribute support
EXT_SUPPORT
1
Supported modes
SUPPORTED_MODES
FFU features
FFU_FEATURES
Operation codes timeout
OPERATION_CODE_TIME_OUT
FFU Argument
FFU_ARG
Barrier support
BARRIER_SUPPORT
Reserved
–
CMDQ support
CMDQ_SUPPORT
CMDQ depth
CMDQ_DEPTH
1
[307]
0h
Reserved
–
1
[306]
-
4
[305:302]
0h
32
[301:270]
0h
1
[269]
01h
1
[268]
01h
en
id
nf
Co
e
Number of FW sectors
NUMBER_OF_FW_SECTORS_
correctly programmed
CORRECTLY_PROGRAMMED
Vendor proprietary
VENDOR_PROPRIETARY _HEALTH_REPORT
health Report
Device life time
DEVICE_LIFE_TIME_EST_TYP_B
estimation type B
Device life time estimation
DEVICE_LIFE_TIME_EST_TYP_A
type A
or
ag
tia
l
Tag Resources Size
Context management
Capabilities
PRE_EOL_INFO
1
[267]
01h
Optimal read size
OPTIMAL_READ_SIZE
1
[266]
08h
Optimal write size
OPTIMAL_WRITE_SIZE
1
[265]
08h
Optimal trim unit size
OPTIMAL_TRIM_UNIT_SIZE
1
[264]
08h
Device version
DEVICE_VERSION
2
[263:262]
0h
M
et
Pre EOL information
Firmware version
FIRMWARE_VERSION
8
[261:254]
B0506h
Power class for 200MHz,
DDR at VCC=3.6V
PWR_CL_DDR_200_360
1
[253]
0h
Cache size
CACHE_SIZE
4
[252:249]
100h
Generic CMD6 timeout
GENERIC_CMD6_TIME
1
[248]
32h
Power off notification(long)
Timeout
POWER_OFF_LONG_TIME
1
[247]
3Ch
18
Confidential Tentative
CH7AQ Series
BKOPS_STATUS
1
[246]
0h
Number of correctly
programmed sectors
CORRECTLY_PRG_SECTORS_NUM
4
[245:242]
0h
1st initialization time after
Partitioning
INI_TIMEOUT_AP
1
[241]
1Eh
Cache Flushing Policy
CACHE_FLUSH_POLICY
1
[240]
0h
PWR_CL_DDR_52_360
1
[239]
0h
PWR_CL_DDR_52_195
1
PWR_CL_200_195
1
PWR_CL_200_130
1
[237]
0h
[236]
0h
1
[235]
0h
1
[234]
0h
1
[233]
–
1
[232]
02h
nf
MIN_PERF_DDR_R_8_52
0h
id
en
MIN_PERF_DDR_W_8_52
[238]
–
TRIM Multiplier
TRIM_MULT
Secure Feature support
SEC_FEATURE_SUPPORT
1
[231]
55h
Secure Erase Multiplier
SEC_ERASE_MULT
1
[230]
1Bh
Secure TRIM Multiplier
SEC_TRIM_MULT
1
[229]
11h
BOOT_INFO
1
[228]
07h
Reserved
–
1
[227]
–
Boot partition size
BOOT_SIZE_MULTI
1
[226]
20h
Access size
ACC_SIZE
1
[225]
06h
High-capacity erase unit size
HC_ERASE_GRP_SIZE
1
[224]
01h
High-capacity erase timeout
ERASE_TIMEOUT_MULT
1
[223]
01h
Reliable write sector count
REL_WR_SEC_C
1
[222]
01h
High-capacity write protect
group size
HC_WP_GRP_SIZE
1
[221]
20h
Sleep current (VCC)
S_C_VCC
1
[220]
07h
Sleep current (VCCQ)
S_C_VCCQ
1
[219]
07h
Production state
awareness Timeout
PRODUCTION_STATE_AWARE
NESS_TIMEOUT
1
[218]
17h
M
e
or
ag
Boot information
Co
Reserved
et
Power class for 52MHz,
DDR at 3.6V
Power class for 52MHz,
DDR at 1.95V
Power class for 200MHz
at 3.6V
Power class for 200MHz,
at 1.95V
Minimum Write
Performance for 8bit,
at 52MHz in DDR mode
Minimum Read
Performance for 8bit,
at 52MHz in DDR mode
tia
l
Background operations
Status
19
Confidential Tentative
CH7AQ Series
S_A_TIMEOUT
1
[217]
17h
Sleep Notification timeout
SLEEP_NOTIFICATION_TIME
1
[216]
11h
4
[215:212]
SECURE_WP_INFO
1
[211]
0h
MIN_PERF_W_8_52
1
[210]
0h
MIN_PERF_R_8_52
1
[209]
0h
MIN_PERF_W_8_26_4_52
1
[208]
0h
1
[207]
0h
1
[206]
0h
MIN_PERF_R_4_26
1
[205]
0h
–
1
[204]
–
PWR_CL_26_360
1
[203]
0h
PWR_CL_52_360
1
[202]
0h
PWR_CL_26_195
1
[201]
0h
PWR_CL_52_195
1
[200]
0h
PARTITION_SWITCH_TIME
1
[199]
05h
Out-of-interrupt busy timing
OUT_OF_INTERRUPT_TIME
1
[198]
19h
I/O Driver Strength
DRIVER_STRENGTH
1
[197]
0Fh
Device type
DEVICE_TYPE
1
[196]
57h
Reserved
–
1
[195]
–
CSD structure version
CSD_STRUCTURE
1
[194]
02h
Reserved
–
1
[193]
–
Extended CSD revision
EXT_CSD_REV
1
[192]
08h
Command set
CMD_SET
1
[191]
0h
Reserved
–
1
[190]
–
MIN_PERF_R_8_26_4_52
MIN_PERF_W_4_26
M
et
e
or
ag
Partition switching timing
Co
Reserved
Power class for 26MHz at
3.6V 1 R
Power class for 52MHz at
3.6V 1 R
Power class for 26MHz at
1.95V 1 R
Power class for 52MHz at
1.95V 1 R
en
Security write protect
information
Minimum Write Performance
for 8bit at 52MHz
Minimum Read Performance
for 8bit at 52MHz
Minimum Write Performance
for 8bit at 26MHz, for 4bit at
52MHz
Minimum Read Performance
for 8bit at 26MHz, for 4bit at
52MHz
Minimum Write Performance
for 4bit at 26MHz
Minimum Read Performance
for 4bit at 26MHz
nf
Sector Count
20
tia
l
SEC_COUNT
1CCD000h-16GB
3A3E000h 32GB
747C000h-64GB
E8F8000h-128GB
id
Sleep/awake timeout
Confidential Tentative
CH7AQ Series
CMD_SET_REV
1
[189]
0h
Reserved
–
1
[188]
–
Power class
POWER_CLASS
1
[187]
0h
Reserved
–
1
[186]
–
High-speed interface timing
HS_TIMING
1
[185]
0h
Strobe support
STROBE_SUPPORT
1
[184]
01h
Bus width mode
BUS_WIDTH
1
[183]
0h
Reserved
–
1
[182]
–
Erased memory content
ERASED_MEM_CONT
Reserved
–
Partition configuration
PARTITION_CONFIG
Boot config protection
[181]
0h
1
[180]
–
1
[179]
0h
BOOT_CONFIG_PROT
1
[178]
0h
Boot bus Conditions
BOOT_BUS_CONDITIONS
1
[177]
0h
Reserved
–
1
[176]
–
ERASE_GROUP_DEF
1
[175]
0h
BOOT_WP_STATUS
1
[174]
0h
BOOT_WP
1
[173]
0h
–
1
[172]
–
User area write protection
Register
USER_WP
1
[171]
0h
Reserved
–
1
[170]
–
FW configuration
FW_CONFIG
1
[169]
0h
RPMB Size
RPMB_SIZE_MULT
1
[168]
20h
WR_REL_SET
1
[167]
0h
WR_REL_PARAM
1
[166]
14h
SANITIZE_START
1
[165]
0h
BKOPS_START
1
[164]
0h
BKOPS_EN
1
[163]
0h
et
Co
or
ag
Reserved
e
High-density erase group
Definition
Boot write protection status
Registers
Boot area write protection
Register
M
Write reliability setting
Register
Write reliability parameter
Register
Start Sanitize operation
Manually start background
Operations
Enable background
operations handshake
nf
1
id
en
tia
l
Command set revision
21
Confidential Tentative
CH7AQ Series
H/W reset function
RST_n_FUNCTION
1
[162]
0h
HPI management
HPI_MGMT
1
[161]
0h
Partitioning Support
PARTITIONING_SUPPORT
1
[160]
07h
MAX_ENH_SIZE_MULT
3
[159:157]
Partitions attribute
PARTITIONS_ATTRIBUTE
1
[156]
0h
Partitioning Setting
PARTITION_SETTING_COMPLETED
1
[155]
0h
GP_SIZE_MULT4
3
[154:152]
0h
id
en
3
[151:149]
0h
3
[148:146]
0h
3
[145:143]
0h
3
[142:140]
0h
ENH_START_ADDR
4
[139:136]
0h
–
1
[135]
–
GP_SIZE_MULT2
GP_SIZE_MULT1
nf
ENH_SIZE_MULT
SEC_BAD_BLK_MGMNT
1
[134]
0h
Production state awareness
PRODUCTION_STATE_AWARENESS
1
[133]
0h
TCASE_SUPPORT
1
[132]
0h
PERIODIC_WAKEUP
1
[131]
0h
Program CID/CSD in DDR
mode support
PROGRAM_CID_CSD_DDR_SUPPORT
1
[130]
01h
Reserved
–
2
[129:128]
–
Vendor Specific Fields
VENDOR_SPECIFIC_FIELD
61
[127:67]
–
Error code
ERROR_CODE
2
[66:65]
0h
Error type
ERROR_TYPE
1
[64]
0h
Native sector size
NATIVE_SECTOR_SIZE
1
[63]
0h
Sector size emulation
USE_NATIVE_SECTOR
1
[62]
0h
Sector size
DATA_SECTOR_SIZE
1
[61]
0h
1st initialization after
disabling sector size
emulation
INI_TIMEOUT_EMU
1
[60]
0h
Package Case Temperature is
controlled
M
or
ag
Periodic Wake-up
e
Bad Block Management
Mode
et
Reserved
GP_SIZE_MULT3
Co
General Purpose Partition
Size
General Purpose Partition
Size
General Purpose Partition
Size
General Purpose Partition
Size
Enhanced User Data Area
Size
Enhanced User Data Start
Address
tia
l
Max Enhanced Area Size
13Bh-16GB
26Bh-32GB
4D7h-64GB
9AEh-128GB
22
Confidential Tentative
CH7AQ Series
CLASS_6_CTRL
1
[59]
0h
Number of addressed group
to be Released
DYNCAP_NEEDED
1
[58]
0h
Exception events control
EXCEPTION_EVENTS_CTRL
2
[57:56]
0h
Exception events status
EXCEPTION_EVENTS_STATUS
2
[55:54]
0h
Extended Partitions Attribute
EXT_PARTITIONS_ATTRIBUTE
2
[53:52]
0h
Context configuration
CONTEXT_CONF
15
[51:37]
-
Packed command status
PACKED_COMMAND_STATUS
1
[36]
0h
Packed command failure
PACKED_FAILURE_INDEX
1
[35]
0h
Power Off Notification
POWER_OFF_NOTIFICATION
Control to turn the Cache
ON/OFF
CACHE_CTRL
Flushing of the cache
FLUSH_CACHE
Barrier control
BARRIER CTRL
Mode config
[34]
0h
1
[33]
0h
1
[32]
0h
1
[31]
0h
MODE_CONFIG
1
[30:30]
0h
Mode operation codes
MODE_OPERATION_CODES
1
[29:29]
0h
Reserved
–
2
[28:27]
–
FFU_STATUS
1
[26:26]
0h
[25:22]
0h
Co
e
FFU status
nf
1
id
en
tia
l
Class 6 commands control
4
Max pre loading data size
MAX_PRE_LOADING_DATA_SIZE
4
[21:18]
Product state awareness
Enablement
PRODUCT_STATE_AWARENESS_ENABLEM
ENT
9D8000h-16GB
1358000h-32GB
26B8000h-64GB
4D70000h-128GB
1
[17:17]
03h
Secure removal type
SECURE_REMOVAL_TYPE
1
[16:16]
09h
Command Queue Mode
enable
CMQ _MODE_EN
1
[15:15]
0h
Reserved
–
16
[14:0]
–
PRE_LOADING_DATA_SIZE
M
et
or
ag
Per loading data size
4.5 RCA Register
The writable 16-bit Relative Device Address (RCA) register carries the Device address assigned by the host during
the Device identification. This address is used for the addressed host-Device communication after the Device
identification procedure. The default value of the RCA register is 0x0001. The value 0x0000 is reserved to set all
Devices into the Stand-by State with CMD7.
23
Confidential Tentative
CH7AQ Series
4.6 DSR Register
M
et
or
ag
e
Co
nf
id
en
tia
l
The 16-bit driver stage register (DSR) is described in detail in Section 7.6 of the JEDEC Standard Specification
No.JESD84-B51.It can be optionally used to improve the bus performance for extended operating conditions
(depending on parameters like bus length, transfer rate or number of Devices). The CSD register carries the
information about the DSR register usage.
24
Confidential Tentative
5 The eMMC bus
CH7AQ Series
The eMMC bus has ten communication lines and three supply lines：
Co
nf
id
en
•
•
•
CMD：Command is a bidirectional signal. The host and Device drivers are operating in two modes, open drain
and push/pull.
DAT0-7：Data lines are bidirectional signals. Host and Device drivers are operating in push-pull mode
CLK：Clock is a host to Device signal. CLK operates in push-pull mode
Data Strobe： Data Strobe is a Device to host signal. Data Strobe operates in push-pull mode.
tia
l
•
e
Figure 5-1 Bus Circuitry Diagram
or
ag
The ROD is switched on and off by the host synchronously to the open-drain and push-pull mode transitions. The
host does not have to have open drain drivers, but must recognize this mode to switch on the ROD. RDAT and
RCMD are pull- up resistors protecting the CMD and the DAT lines against bus floating device when all device drivers
are in a high- impedance mode.
A constant current source can replace the ROD by achieving a better performance (constant slopes for the signal
rising and falling edges). If the host does not allow the switchable ROD implementation, a fixed RCMD can be
used).Consequently the maximum operating frequency in the open drain mode has to be reduced if the used RCMD
value is higher than the minimal one given in.
et
RDatastrobe is pull-down resistor used in HS400 device.
M
5.1 Power-up
5.1.1 eMMC power-up
An eMMC bus power-up is handled locally in each device and in the bus master. Figure 5-2 shows the power-up
sequence and is followed by specific instructions regarding the power-up sequence. Refer to section 10.1 of the
JEDEC Standard Specification No.JESD84-B51 for specific instructions regarding the power-up sequence.
25
CH7AQ Series
id
en
tia
l
Confidential Tentative
nf
Figure 5-2 eMMC Power-up Diagram
5.1.2 eMMC Power Cycling
M
et
or
ag
e
Co
The master can execute any sequence of VCC and VCCQ power-up/power-down. However, the master must not
issue any commands until VCC and VCCQ are stable within each operating voltage range. After the slave enters
sleep mode, the master can power-down VCC to reduce power consumption. It is necessary for the slave to be
ramped up to VCC before the host issues CMD5 (SLEEP_AWAKE) to wake the slave unit. For more information
about power cycling see Section 10.1.3 of the JEDEC Standard Specification No. JESD84-B51.
Figure 5-3 The eMMC Power Cycle
26
Confidential Tentative
CH7AQ Series
5.2 Bus Operating Condition
Table 5-1 General Operating Conditions
Symbol
Min
Max
Unit
Peak voltage on all lines
-
-0.5
VCCQ
+0.5
V
-
-100
100
μA
-
-2
2
μA
All Inputs
Input Leakage Current (before initialization sequence 1 and/or the internal pull
up resistors connected)
Input Leakage Current (after initialization sequence and the internal pull up
resistors disconnected)
All Outputs
Output Leakage Current (before initialization sequence)
Output Leakage Current (after initialization sequence) 2
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Parameter
-100
100
-2
2
Note1:Initialization sequence is defined in section 10.1 of the JEDEC Standard Specification No. JESD84-B51.
Note2:DS (Data strobe) pin is excluded.
μA
μA
en
-
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5.2.1 Power supply： eMMC
Figure 5-4 eMMC Internal Power Diagram
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et
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nf
In the eMMC, VCC is used for the NAND flash device and its interface voltage; VCCQ is for the controller and the
MMC interface voltage as shown in Figure 5-4. The core regulator is optional and only required when internal core
logic voltage is regulated from VCCQ. A CReg capacitor must be connected to the VDDi terminal to stabilize
regulator output on the system.
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CH7AQ Series
5.2.2 eMMC Power Supply Voltage
The eMMC supports one or more combinations of VCC and VCCQ as shown in Table 5-2. The VCCQ must be defined
at equal to or less than VCC.
Table 5-2 eMMC Operating Voltage
Symbol
VCC
Supply voltage (I/O)
VCCQ
Supply power-up for 3.3V
Supply power-up for 1.8V
tPRUH
tPRUL
Min
2.7
1.7
2.7
-
Max
3.6
1.95
3.6
35
25
Unit
V
V
V
ms
ms
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Parameter
Supply voltage (NAND)
The eMMC must support at least one of the valid voltage configurations, and can optionally support all valid voltage
configurations (see Table ).
en
Table 5-3 eMMC Voltage Combinations
VCCQ
2.7V–3.6V 1
1.7V–1.95V
Valid
id
2.7V-3.6V
Vcc
Valid
Note: VCCQ (I/O) 3.3 volt range is not supported in HS200 /HS400 devices.
nf
5.2.3 Bus Signal Line Load
CL = CHOST + CBUS + CDEVICE
Co
The total capacitance CL of each line of the eMMC bus is the sum of the bus master capacitance CHOST, the bus
capacitance CBUS itself and the capacitance CDEVICE of eMMC connected to this line：
The sum of the host and bus capacitances must be under 20pF.
Table 5-4 Signal Line Load
Symbol
Min
Max
Typ
Unit
𝑅𝑅𝐶𝐶MD
4.7
50
10
Kohm
10
50
10
Kohm
𝑅𝑅RST_n _n
4.7
50
10
Kohm
CL
-
30
30
pF
𝐶𝐶BGA
-
6
6
pF
-
-
16
16
nH
-
45
55
50
ohm
𝑆𝑆𝑆𝑆𝐶𝐶𝐶𝐶𝐶𝐶
0
47
0
ohm
0
47
0
ohm
-
2.2+0.1
10+0.22
2.2+0.1
e
Parameter
Pull-up resistance for CMD
or
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Pull-up resistance for DAT0–7
Pull-up resistance for RST_n
Bus signal line capacitance
Single Device capacitance
et
Maximum signal line inductance
Impedance on CLK /
CMD / DAT0 ~ 7
Serial’s resistance
on CLK line
Serial’s resistance on
CMD / DAT0 ~ 7 line
𝑅𝑅DAT
CH1
1
2.2
1
VCC capacitor value
-
2.2+0.1
10+0.22
4.7+0.1
μF
VDDi capacitor value
-
1+0.1
2.2+0.1
1+0.1
μF
M
VCCQ decoupling capacitor
𝑆𝑆𝑆𝑆𝐶𝐶𝐶𝐶𝐶𝐶
𝑆𝑆R 𝐷𝐷AT0~7
28
μF
Confidential Tentative
CH7AQ Series
5.2.4 HS400 reference load
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The circuit in Figure 5-5 shows the reference load used to define the HS400 Device Output Timings and overshoot /
undershoot parameters.
The reference load is made up by the transmission line and the CREFERENCE capacitance.
The reference load is not intended to be a precise representation of the typical system environment nor a depiction
of the actual load presented by a production tester.
System designers should use IBIS or other simulation tools to correlate the reference load to system environment.
Manufacturers should correlate to their production test conditions.
Delay time (td) of the transmission line has been introduced to make the reference load independent from the PCB
technology and trace length.
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Figure 5-5 HS400 reference load
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CH7AQ Series
5.3 Bus Signal Levels
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As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage.
nf
Figure 5-6 Bus Signal Levels
5.3.1 Open-drain Mode Bus Signal Level
Table 5-5 Open-drain Bus Signal Level
Symbol
VOH
VOL
Min
VDD – 0.2
Max
-
0.3
Co
Parameter
Output HIGH voltage
Output LOW voltage
-
Unit
V
V
Conditions
IOH = -100 μA
IOL = 2 mA
The input levels are identical with the push-pull mode bus signal levels.
e
5.3.2 Push-pull mode bus signal level — eMMC
or
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The device input and output voltages shall be within the following specified ranges for any VDD of the allowed
voltage range.
For 1.70V – 1.95V VCCQ range (Compatible with EIA/JEDEC Standard “EIA/JESD8-7 Normal Range” as defined in the
following table.)
Parameter
Symbol
Min
Max
Unit
Conditions
et
Table 5-6 Push-pull Signal Level—1.70 -1.95 VCCQ Voltage Range
Output HIGH voltage
VOH
VCCQ – 0.45V
-
V
IOH = -2mA
Output LOW voltage
VOL
-
0.45V
V
IOL = 2mA
1
0.65 * VCCQ
VCCQ + 0.3
V
-
VSS – 0.3
2
0.35 * VDD
V
-
M
Input HIGH voltage
Input LOW voltage
VIH
VIL
Note 1： 0.7 * VDD for MMC™4.3 and older revisions.
Note 2： 0.3 * VDD for MMC™4.3 and older revisions.
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For 2.7V-3.6V VCCQ range (compatible with JESD8C.01)
Table 5-7 Push-pull Signal Level—High-voltage eMMC
Symbol
Min
Max
Unit
Conditions
Output HIGH voltage
VOH
-
V
IOH = -100 μA @ VCCQ min
Output LOW voltage
VOL
0.75 * VCCQ
V
IOL = 100 μA @ VCCQ min
Input HIGH voltage
VIH
0.125 * VCCQ
V
-
Input LOW voltage
VIL
V
-
-
VCCQ + 0.3
0.625 * VCCQ
VSS – 0.3
0.25 * VCCQ
5.3.3 Bus Operating Conditions for HS200 & HS400
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Parameter
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The bus operating conditions for HS200 devices is the same as specified in sections 10.5.1 of JESD84- B51 through
10.5.2 of JESD84-B51.
5.3.4 Device Output Driver Requirements for HS200 & HS400
id
Refer to section 10.5.4 of the JEDEC Standard Specification No.JESD84-B51.
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5.4 Bus Timing
Figure 5-7 Timing Diagram
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5.4.1 Device Interface Timings
Table 5-8 High-speed Device Interface Timing
Parameter
Symbol
Clock CLK1
Min
Max
Unit
Clock frequency Data Transfer Mode(PP)2
fPP
0
523
MHz
Clock frequency Identification Mode(OD)
Clock high time
fOD
tWH
0
6.5
400
kHz
ns
31
-
Confidential Tentative
-
3
3
-
13.7
-
3
ns
ns
ns
ns
ns
ns
ns
ns
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tWL
6.5
tTLH
tTHL
Inputs CMD, DAT (referenced to CLK)
Input set-up time
tISU
3
Input hold time
tIH
3
Outputs CMD, DAT (referenced to CLK)
Output delay time during data transfer
tODLY
Output hold time
tOH
2.5
Signal rise time5
tRISE
-
CH7AQ Series
Clock low time
Clock rise time4
Clock fall time
en
Note1:CLK timing is measured at 50% of VDD.
Note2:eMMC shall support the full frequency range from 0-26Mhz or 0-52MHz.
Note3:Device can operate as high-speed Device interface timing at 26 MHz clock frequency.
Note4:CLK rise and fall times are measured by min (VIH) and max (VIL).
Note5:Inputs CMD DAT rise and fall times are measured by min (VIH) and max (VIL) and outputs CMD DAT rise and fall
times are measured by min (VOH) and max (VOL).
Table 5-9 Backward-compatible Device Interface Timing
Symbol
Min
Max
Unit
2
Clock CLK
Clock frequency Data Transfer Mode (PP)3
fPP
0
26
MHz
Clock frequency Identification Mode (OD)
fOD
0
400
kHz
Clock high time
tWH
10
Clock low time
tWL
10
ns
Clock rise time4
tTLH
10
ns
Clock fall time
tTHL
10
ns
Inputs CMD, DAT (referenced to CLK)
Input set-up time
tISU
3
ns
Input hold time
tIH
3
ns
Outputs CMD, DAT (referenced to CLK)
Output set-up time5
tOSU
11.7
ns
Output hold time5
tOH
8.3
ns
Note1:The Device must always start with the backward-compatible interface timing. The timing mode can be switched to
high-speed interface timing by the host sending the SWITCH command (CMD6) with the argument for high-speed
interface select.
Note2:CLK timing is measured at 50% of VDD.
Note3:For compatibility with Devices that support the v4.2 standard or earlier, host should not use > 26 MHz before
switching to high-speed interface timing.
Note4:CLK rise and fall times are measured by min (VIH) and max (VIL).
Note5:tOSU and tOH are defined as values from clock rising edge. However, there may be Devices or devices which utilize
clock falling edge to output data in backward compatibility mode. Therefore, it is recommended for hosts either to
settWL value as long as possible within the range which will not go over tCK-tOH(min) in the system or to use slow
clock frequency, so that host could have data set up margin for those devices. In this case, each device which
utilizes clock falling edge might show the correlation either between tWL and tOSU or between tCK and tOSU for
the device in its own datasheet as a note or its application notes.
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Parameter
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CH7AQ Series
5.5 Bus Timing for DAT Signals During Dual Data Rate Operation
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These timings apply to the DAT[7：0] signals only when the device is configured for dual data mode operation. In this
dual data mode, the DAT signals operate synchronously of both the rising and the falling edges of CLK. The CMD signal
still operates synchronously of the rising edge of CLK and therefore complies with the bus timing specified in section
10.5 of the JEDEC Standard Specification No.JESD84-B51, therefore there is no timing change for the CMD signal.
Figure 5-8 Timing Diagram： Data Input/Output in Dual Data Rate Mode
5.5.1 Dual Data Rate Interface Timings
Symbol
or
ag
Parameter
e
Table 5-10 High-speed Dual Data Rate Interface Timing
Clock duty cycle
Input set-up time
Input hold time
Min
Max
Unit
45
55
%
-
ns
ns
Input CLK1
-
Input DAT (referenced to CLK-DDR mode)
tISUddr
2.5
tIHddr
2.5
Output DAT (referenced to CLK-DDR mode)
-
M
et
Output delay time during data
tODLYd dr
1.5
7
ns
transfer
Signal rise time (all signals)2
tRISE
2
ns
Signal fall time (all signals)
tFALL
2
ns
Note1:CLK timing is measured at 50% of VDD.
Note2:Inputs CMD, DAT rise and fall times are measured by min (VIH) and max (VIL), and outputs CMD, DAT rise
and fall times are measured by min (VOH) and max (VOL).
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CH7AQ Series
5.6 Bus Timing Specification in HS200 Mode
5.6.1 HS200 Clock Timing
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Host CLK Timing in HS200 mode shall conform to the timing specified in Figure 5-9 and Table 5-11. CLK input shall
satisfy the clock timing over all possible operation and environment conditions. CLK input parameters should be
measured while CMD and DAT lines are stable high or low, as close as possible to the Device.
The maximum frequency of HS200 is 200MHz. Hosts can use any frequency up to the maximum that HS200 mode
allows.
Figure 5-9 HS200 Clock Signal Timing
nf
Note 1：VIH denote VIH(min.) and VIL denotes VIL(max.).
Note 2：VT = 50% of VCCQ, indicates clock reference point for timing measurements.
Table 5-11 HS200 Clock Signal Timing
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et
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tTLH, tTHL
Duty Cycle
Min
5
30
Co
Symbol
tPERIOD
34
Max
t
0.2* PERIOD
70
Unit
ns
ns
%
Confidential Tentative
CH7AQ Series
en
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5.6.2 HS200 Device Input Timing
id
Figure 5-10 HS200 Device Input Timing
Note 1： tISU and tIH are measured at VIL(max.) and VIH(min.).
Note 2： VIH denote VIH(min.) and VIL denotes VIL(max.).
nf
Table 5-12 HS200 Device Input Timing
Min
1.4
0.8
5.6.3 HS200 Device Output Timing
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Symbol
tISU
tIH
Max
-
Unit
ns
ns
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et
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tPH parameter is defined to allow device output delay to be longer than tPERIOD. After initialization, the tPH may have
random phase relation to the clock. The Host is responsible to find the optimal sampling point for the Device outputs,
while switching to the HS200 mode.
Figure 5-11 and Table 5-13 define Device output timing.
While setting the sampling point of data, a long term drift, which mainly depends on temperature drift, should be
considered. The temperature drift is expressed by ΔTPH. Output valid data window (tVW) is available regardless of the
drift (ΔTPH) but position of data window varies by the drift, as described in Figure 5-12.
Figure 5-11 HS200 Device Output Timing
Note： VOH denotes VOH(min.) and VOL denotes VOL(max.).
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Confidential Tentative
CH7AQ Series
Table 5-13 Output Timing
Unit
UI
ps
UI
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Symbol
Min
Max
tPH
0
2
-350 (ΔT=-20°C)
+1550 (ΔT=90°C)
ΔTPH
TVW
0.575
Note:Unit Interval (UI) is one bit nominal time. For example, UI=5ns at 200MHz.
Co
Figure 5-12 ΔTPH consideration
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et
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Implementation Guide： Host should design to avoid sampling errors that may be caused by the ΔTPH drift. It is
recommended to perform tuning procedure while Device wakes up, after sleep. One simple way to overcome
the ΔTPH drift is by reduction of operating frequency.
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Confidential Tentative
CH7AQ Series
5.7 Bus Timing Specification in HS400 mode
5.7.1 HS400 Device Input Timing
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The CMD input timing for HS400 mode is the same as CMD input timing for HS200 mode. Figure 5-13 and Table 5-14
show Device input timing.
nf
Figure 5-13 HS400 Device Data input timing
Note 1： tISU and tIH are measured at VIL(max.) and VIH(min.).
Note 2： VIH denote VIH(min.) and VIL denotes VIL(max.).
Parameter
Co
Table 5-14 HS400 Device input timing
Symbol
Min
Max
Unit
Input CLK
tPERIOD
5
-
-
Slew rate
SR
1.125
-
V/ns
tCKDCD
0
0.3
ns
tCKMPW
2.2
-
ns
or
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Duty cycle distortion
e
Cycle time data transfer mode
Minimum pulse width
Input DAT (referenced to CLK)
tISUddr
0.4
-
ns
Input hold time
tIHddr
0.4
-
ns
Slew rate
SR
1.125
-
V/ns
M
et
Input set-up time
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Confidential Tentative
CH7AQ Series
5.7.2 HS400 Device Output Timing
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The Data Strobe is used to read data in HS400 mode. The Data Strobe is toggled only during data read or CRC status
response.
id
Figure 5-14 HS400 Device output timing
Note: VOH denotes VOH(min.) and VOL denotes VOL(max.).
Note: VT = 50% of VCCQ, indicates clock reference point for timing measurements.
Symbol
Cycle time data transfer mode
Slew rate
Duty cycle distortion
Minimum pulse width
Read pre-amble
tPERIOD
SR
tDSDCD
tDSMPW
tRPRE
e
Read post- amble
Min
Data Strobe
5
1.125
0
2
0.4
Co
Parameter
nf
Table 5-15 HS400 Device Output timing
tRPST
0.4
or
ag
Output DAT (referenced to Data Strobe)
Slew rate
SR
1.125
Note: Measured with HS400 reference load(6.2.4).
Max
Unit
0.2
-
V/ns
ns
ns
tPERIOD
-
tPERIOD
-
V/ns
Table 5-16 HS400 Capacitance
Symbol
RCMD
RDAT
RDS
Rint
CDevice
M
et
Parameter
Pull-up resistance for CMD
Pull-up resistance for DAT0-7
Pull-down resistance for Data Strobe
Internal pull up resistance DAT1-DAT7
Single Device capacitance
38
Min
4.7
10
10
10
Type
-
-
-
Max
50
50
50
150
6
Unit
Kohm
Kohm
Kohm
Kohm
pF
Confidential Tentative
6 Package connections
CH7AQ Series
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Package Mechanical (11.5mm x 13.0mm)
39
CH7AQ Series
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Confidential Tentative
M
et
Note： The size data is tentative.
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Confidential Tentative
CH7AQ Series
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7 Ball Assignment (153 ball)
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Figure 7-1 153 ball assignment (Top View, Ball Side Down)
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Confidential Tentative
CH7AQ Series
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8 Marking
YYYYYYYYYYYY
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XXXXXXXX
eMMC logo
nf
CHINA
Co
ZZZZZZZZ： Part Number
XXXXXXXX： Control Code1
9 Appendix
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YYYYYYYYYYYY： Control Code2
9.1 Endurance characteristic
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et
3,000 cycles/block (nominal value: under specified conditions)
*This value is not guaranteed
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