178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Features
Mobile LPDDR3 SDRAM
RS256M32LD3D1LMZ,RS512M32LD3D2LMZ,RS1G32LD3D4LMM
Features
Options
Marking
• VDD1/VDD2/VDDCA/VDDQ:
1.8V/1.2V/1.2V/1.2V
• Array configuration
– 256 Meg x 32 (SDP)
– 512 Meg x 32 (DDP)
– 1 Gig x 32 (QDP)
• Device configuration
– 1 die in package
– 2 die in package
– 4 die in package
• 178-ball FBGA “green” package
– 11mm x 11.5mm x 0.85mm MAX,
1 die, 2 die
– 12mm x 11.5mm x 1.0mm MAX, 4 die
• Speed grade, cycle time
– 938ps @ RL = 16
– 1.071ns @ RL = 14
– 1.25ns @ RL = 12
• Operating temperature range
– From -25°C to +85°C
• Revision
• Ultra-low-voltage core and I/O power supplies
• Frequency range
– 1066–10 MHz (data rate range: 2133–20 Mb/s/
pin)
• 8n prefetch DDR architecture
• 8 internal banks for concurrent operation
• Multiplexed, double data rate, command/address
inputs; commands entered on each CK_t/CK_c
edge
• Bidirectional/differential data strobe per byte of
data (DQS_t/DQS_c)
• Programmable READ and WRITE latencies (RL/WL)
• Burst length: 8
• Per-bank refresh for concurrent operation
• Temperature-compensated self refresh (TCSR)
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock-stop capability
• On-die termination (ODT)
• RoHS-compliant, “green” packaging
L
256M32
512M32
1G32
D1
D2
D4
MZ
MM
–093
–107
–125
Table 1: Key Timing Parameters
Speed
Grade
Clock
Rate
(MHz)
Data Rate
(Mb/s/pin)
Write
Latency
(set A/set B)
Read
Latency
–093
1066
2133
8/13
16
–107
933
1866
8/11
14
–125
800
1600
6/9
12
Table 2: Configuration Addressing
Architecture
1 Gig x 32
512 Meg x 32
256 Meg x 32
32Gb
16Gb
8Gb
4
2
1
Ranks (CS_n) per channel
2
2
1
Die per rank
CS0_n
2
1
1
CS1_n
2
1
–
Density per package
Die per package
1
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Part Number Ordering Information
Table 2: Configuration Addressing (Continued)
Architecture
1 Gig x 32
512 Meg x 32
256 Meg x 32
CS0_n
64 Meg x 16 x 8 banks
x 2 rank
32 Meg x 32 x 8 banks
32 Meg x 32 x 8 banks
CS1_n
64 Meg x 16 x 8 banks
x 2 rank
32 Meg x 32 x 8 banks
–
Row addressing
32K A[14:0]
32K A[14:0]
32K A[14:0]
Column addressing/CS_n
2K A[10:0]
1K A[9:0]
1K A[9:0]
Configuration per
rank (CS_n)
Part Number Ordering Information
Figure 1: Part Number Chart
2
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Part Number Ordering Information
Contents
Ball Assignments ............................................................................................................................................
Ball Descriptions ............................................................................................................................................
Package Block Diagrams .................................................................................................................................
Package Dimensions .......................................................................................................................................
MR0, MR5, MR6, MR8 Readout .......................................................................................................................
IDD Specifications – Single Die .........................................................................................................................
Pin Capacitance .............................................................................................................................................
LPDDR3 Array Configuration ..........................................................................................................................
General Notes ............................................................................................................................................
Functional Description ...................................................................................................................................
Simplified Bus Interface State Diagram ............................................................................................................
Power-Up and Initialization ............................................................................................................................
Voltage Ramp and Device Initialization .......................................................................................................
Initialization After Reset (Without Voltage Ramp) ........................................................................................
Power-Off Sequence .......................................................................................................................................
Uncontrolled Power-Off Sequence ..............................................................................................................
Standard Mode Register Definition ..................................................................................................................
Mode Register Assignments and Definitions ................................................................................................
Commands and Timing ..................................................................................................................................
ACTIVATE Command .....................................................................................................................................
8-Bank Device Operation ............................................................................................................................
Read and Write Access Modes .........................................................................................................................
Burst READ Command ...................................................................................................................................
tDQSCK Delta Timing .................................................................................................................................
Burst WRITE Command ..................................................................................................................................
Write Data Mask .............................................................................................................................................
PRECHARGE Command .................................................................................................................................
Burst READ Operation Followed by PRECHARGE .........................................................................................
Burst WRITE Followed by PRECHARGE .......................................................................................................
Auto Precharge ...........................................................................................................................................
Burst READ with Auto Precharge .................................................................................................................
Burst WRITE with Auto Precharge ...............................................................................................................
REFRESH Command ......................................................................................................................................
REFRESH Requirements .............................................................................................................................
SELF REFRESH Operation ...............................................................................................................................
Partial-Array Self Refresh (PASR) – Bank Masking .........................................................................................
Partial-Array Self Refresh – Segment Masking ..............................................................................................
MODE REGISTER READ .................................................................................................................................
MRR Following Idle Power-Down State ........................................................................................................
Temperature Sensor ...................................................................................................................................
DQ Calibration ...........................................................................................................................................
MODE REGISTER WRITE ................................................................................................................................
MRW RESET Command ..............................................................................................................................
MRW ZQ Calibration Commands ................................................................................................................
ZQ External Resistor Value, Tolerance, and Capacitive Loading .....................................................................
MRW – CA Training Mode ...........................................................................................................................
MRW - Write Leveling Mode ........................................................................................................................
On-Die Termination (ODT) .............................................................................................................................
ODT Mode Register ....................................................................................................................................
Asychronous ODT ......................................................................................................................................
3
10
12
14
17
19
20
24
25
25
26
28
30
30
32
33
33
34
34
44
45
45
46
47
49
53
57
58
59
60
61
61
62
64
67
69
70
70
72
73
74
75
77
77
78
81
81
83
85
85
85
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Part Number Ordering Information
ODT During READ Operations (READ or MRR) ............................................................................................ 86
ODT During Power-Down ........................................................................................................................... 86
ODT During Self Refresh ............................................................................................................................. 86
ODT During Deep Power-Down .................................................................................................................. 86
ODT During CA Training and Write Leveling ................................................................................................ 86
Power-Down .................................................................................................................................................. 89
Deep Power-Down ......................................................................................................................................... 95
Input Clock Frequency Changes and Stop Events ............................................................................................. 96
Input Clock Frequency Changes and Clock Stop with CKE LOW ................................................................... 96
Input Clock Frequency Changes and Clock Stop with CKE HIGH .................................................................. 97
NO OPERATION Command ............................................................................................................................ 97
Truth Tables ................................................................................................................................................... 98
Absolute Maximum Ratings ........................................................................................................................... 105
Electrical Specifications – IDD Measurements and Conditions ......................................................................... 106
IDD Specifications ...................................................................................................................................... 108
AC and DC Operating Conditions ................................................................................................................... 110
AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 111
VREF Tolerances ......................................................................................................................................... 112
Input Signal .............................................................................................................................................. 113
AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 115
Single-Ended Requirements for Differential Signals .................................................................................... 116
Differential Input Crosspoint Voltage ......................................................................................................... 117
Input Slew Rate ......................................................................................................................................... 118
Output Characteristics and Operating Conditions ........................................................................................... 120
Single-Ended Output Slew Rate .................................................................................................................. 120
Differential Output Slew Rate ..................................................................................................................... 122
HSUL_12 Driver Output Timing Reference Load ......................................................................................... 124
Output Driver Impedance .............................................................................................................................. 125
Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 126
Output Driver Temperature and Voltage Sensitivity ..................................................................................... 126
Output Impedance Characteristics Without ZQ Calibration ......................................................................... 127
ODT Levels and I-V Characteristics ............................................................................................................ 131
Clock Specification ........................................................................................................................................ 132
tCK(abs), tCH(abs), and tCL(abs) ................................................................................................................ 133
Clock Period Jitter .......................................................................................................................................... 133
Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 133
Cycle Time Derating for Core Timing Parameters ........................................................................................ 134
Clock Cycle Derating for Core Timing Parameters ....................................................................................... 134
Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 134
Clock Jitter Effects on Read Timing Parameters ........................................................................................... 134
Clock Jitter Effects on Write Timing Parameters .......................................................................................... 135
Refresh Requirements .................................................................................................................................... 136
AC Timing ..................................................................................................................................................... 137
CA and CS_n Setup, Hold, and Derating .......................................................................................................... 144
Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 151
Revision History ............................................................................................................................................ 158
Rev. D – 4/16 ............................................................................................................................................. 158
Rev. C – 3/16 .............................................................................................................................................. 158
Rev. B – 9/15 .............................................................................................................................................. 158
Rev. A – 11/14 ............................................................................................................................................ 158
4
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Part Number Ordering Information
List of Figures
Figure 1: Part Number Chart ............................................................................................................................ 2
Figure 2: 178-Ball Single-Channel FBGA – 1 x 8Gb Die ..................................................................................... 10
Figure 3: 178-Ball Single-Channel FBGA – 2 x 8Gb Die ..................................................................................... 11
Figure 4: 178-Ball Single-Channel FBGA – 4 x 8Gb Die ..................................................................................... 12
Figure 5: Single-Die, Single-Channel Package Block Diagram .......................................................................... 14
Figure 6: Dual-Rank, Dual-Die, Single-Channel Package Block Diagram .......................................................... 15
Figure 7: Quad-Die, Single-Channel Package Block Diagram ........................................................................... 16
Figure 8: 178-Ball FBGA (11mm x 11.5mm), RS256M32LD3D1LMZ,RS512M32LD3D2LMZ............................... 17
Figure 9: 178-Ball FBGA (12.0mm x 11.5mm), RS1G32LD3D4LMM................................................................... 18
Figure 10: Functional Block Diagram ............................................................................................................. 27
Figure 11: Simplified State Diagram ............................................................................................................... 29
Figure 12: Voltage Ramp and Initialization Sequence ...................................................................................... 32
Figure 13: Command and Input Setup and Hold ............................................................................................. 44
Figure 14: CKE Input Setup and Hold ............................................................................................................. 44
Figure 15: ACTIVATE Command .................................................................................................................... 45
Figure 16: tFAW Timing .................................................................................................................................. 46
Figure 17: READ Output Timing ..................................................................................................................... 47
Figure 18: Burst READ – RL = 12, BL = 8, tDQSCK > tCK ................................................................................... 47
Figure 19: Burst READ – RL = 12, BL = 8, tDQSCK < tCK ................................................................................... 48
Figure 20: Burst READ Followed by Burst WRITE – RL = 12, WL = 6, BL = 8 ....................................................... 48
Figure 21: Seamless Burst READ – RL = 6, BL = 8, tCCD = 4 .............................................................................. 49
Figure 22: tDQSCKDL Timing ........................................................................................................................ 50
Figure 23: tDQSCKDM Timing ....................................................................................................................... 51
Figure 24: tDQSCKDS Timing ......................................................................................................................... 52
Figure 25: Data Input (WRITE) Timing ........................................................................................................... 53
Figure 26: Burst WRITE ................................................................................................................................. 54
Figure 27: Method for Calculating tWPRE Transitions and Endpoints ............................................................... 54
Figure 28: Method for Calculating tWPST Transitions and Endpoints ............................................................... 55
Figure 29: Burst WRITE Followed by Burst READ ............................................................................................ 55
Figure 30: Seamless Burst WRITE – WL = 4, BL = 8, tCCD = 4 ............................................................................ 56
Figure 31: Data Mask Timing ......................................................................................................................... 57
Figure 32: Write Data Mask – Second Data Bit Masked .................................................................................... 57
Figure 33: Burst READ Followed by PRECHARGE – BL = 8, RU(tRTP(MIN)/tCK) = 2 ........................................... 59
Figure 34: Burst WRITE Followed by PRECHARGE – BL = 8 .............................................................................. 60
Figure 35: LPDDR3 – Burst READ with Auto Precharge .................................................................................... 61
Figure 36: Burst WRITE with Auto Precharge – BL = 8 ...................................................................................... 62
Figure 37: REFRESH Command Timing .......................................................................................................... 66
Figure 38: Postponing REFRESH Commands .................................................................................................. 66
Figure 39: Pulling In REFRESH Commands .................................................................................................... 66
Figure 40: All-Bank REFRESH Operation ........................................................................................................ 68
Figure 41: Per-Bank REFRESH Operation ....................................................................................................... 68
Figure 42: SELF REFRESH Operation .............................................................................................................. 70
Figure 43: MRR Timing .................................................................................................................................. 72
Figure 44: READ to MRR Timing .................................................................................................................... 73
Figure 45: Burst WRITE Followed by MRR ...................................................................................................... 73
Figure 46: MRR After Idle Power-Down Exit .................................................................................................... 74
Figure 47: Temperature Sensor Timing ........................................................................................................... 75
Figure 48: MR32 and MR40 DQ Calibration Timing ......................................................................................... 76
Figure 49: MODE REGISTER WRITE Timing ................................................................................................... 77
Figure 50: MODE REGISTER WRITE Timing for MRW RESET .......................................................................... 78
5
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Part Number Ordering Information
Figure 51:
Figure 52:
Figure 53:
Figure 54:
Figure 55:
Figure 56:
Figure 57:
Figure 58:
Figure 59:
Figure 60:
Figure 61:
Figure 62:
Figure 63:
Figure 64:
Figure 65:
Figure 66:
Figure 67:
Figure 68:
Figure 69:
Figure 70:
Figure 71:
Figure 72:
Figure 73:
Figure 74:
Figure 75:
Figure 76:
Figure 77:
Figure 78:
Figure 79:
Figure 80:
Figure 81:
Figure 82:
Figure 83:
Figure 84:
Figure 85:
Figure 86:
Figure 87:
Figure 88:
Figure 89:
Figure 90:
Figure 91:
Figure 92:
Figure 93:
ZQ Timings ................................................................................................................................... 80
CA Training Timing ....................................................................................................................... 81
Write-Leveling Timing ................................................................................................................... 84
Functional Representation of On-Die Termination .......................................................................... 85
Asynchronous ODT Timing – RL = 12 ............................................................................................. 87
Automatic ODT Timing During READ Operation – RL = m ............................................................... 88
ODT Timing During Power-Down, Self Refresh, Deep Power-Down Entry/Exit ................................. 88
Power-Down Entry and Exit Timing ................................................................................................ 90
CKE Intensive Environment ........................................................................................................... 90
REFRESH to REFRESH Timing in CKE Intensive Environments ....................................................... 91
READ to Power-Down Entry ........................................................................................................... 91
READ with Auto Precharge to Power-Down Entry ............................................................................ 92
WRITE to Power-Down Entry ......................................................................................................... 92
WRITE with Auto Precharge to Power-Down Entry .......................................................................... 93
REFRESH Command to Power-Down Entry .................................................................................... 93
ACTIVATE Command to Power-Down Entry ................................................................................... 94
PRECHARGE Command to Power-Down Entry ............................................................................... 94
MRR Power-Down Entry ................................................................................................................ 95
MRW Command to Power-Down Entry .......................................................................................... 95
Deep Power-Down Entry and Exit Timing ....................................................................................... 96
V REF DC Tolerance and V REF AC Noise Limits ................................................................................. 112
LPDDR3-1600 to LPDDR3-1333 Input Signal ................................................................................. 113
LPDDR3-2133 to LPDDR3-1866 Input Signal ................................................................................. 114
Differential AC Swing Time and tDVAC .......................................................................................... 115
Single-Ended Requirements for Differential Signals ....................................................................... 116
V IX Definition ............................................................................................................................... 118
Differential Input Slew Rate Definition for CK and DQS .................................................................. 119
Single-Ended Output Slew Rate Definition ..................................................................................... 121
Differential Output Slew Rate Definition ........................................................................................ 122
Overshoot and Undershoot Definition ........................................................................................... 123
HSUL_12 Driver Output Reference Load for Timing and Slew Rate ................................................. 124
Output Driver ............................................................................................................................... 125
Output Impedance = 240Ω, I-V Curves After ZQRESET ................................................................... 129
Output Impedance = 240Ω, I-V Curves After Calibration ................................................................. 130
ODT Functional Block Diagram .................................................................................................... 131
Typical Slew Rate and tVAC – tIS for CA and CS_n Relative to Clock ................................................. 147
Typical Slew Rate – tIH for CA and CS_n Relative to Clock ............................................................... 148
Tangent Line – tIS for CA and CS_n Relative to Clock ...................................................................... 149
Tangent Line – tIH for CA and CS_n Relative to Clock ..................................................................... 150
Typical Slew Rate and tVAC – tDS for DQ Relative to Strobe ............................................................. 154
Typical Slew Rate – tDH for DQ Relative to Strobe ........................................................................... 155
Tangent Line – tDS for DQ with Respect to Strobe .......................................................................... 156
Tangent Line – tDH for DQ with Respect to Strobe .......................................................................... 157
6
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Part Number Ordering Information
List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Configuration Addressing ................................................................................................................... 1
Table 3: Ball/Pad Descriptions ....................................................................................................................... 13
Table 4: IDD Specifications ............................................................................................................................. 20
Table 5: IDD6 Partial-Array Self Refresh Current at 25°C .................................................................................... 23
Table 6: IDD6 Partial-Array Self Refresh Current at 85°C .................................................................................... 23
Table 7: Input/Output Capacitance ................................................................................................................ 24
Table 8: Voltage Ramp Conditions .................................................................................................................. 30
Table 9: Initialization Timing Parameters ....................................................................................................... 32
Table 10: Power Supply Conditions ................................................................................................................ 33
Table 11: Power-Off Timing ............................................................................................................................ 33
Table 12: Mode Register Assignments ............................................................................................................. 34
Table 13: MR0 Device Feature 0 (MA[7:0] = 00h) .............................................................................................. 35
Table 14: MR0 Op-Code BIt Definitions .......................................................................................................... 35
Table 15: MR1 Device Feature 1 (MA[7:0] = 01h) .............................................................................................. 36
Table 16: MR1 Op-Code Bit Definitions .......................................................................................................... 36
Table 17: Burst Sequence ............................................................................................................................... 36
Table 18: MR2 Device Feature 2 (MA[7:0] = 02h) .............................................................................................. 36
Table 19: MR2 Op-Code Bit Definitions .......................................................................................................... 37
Table 20: LPDDR3 READ and WRITE Latency ................................................................................................. 37
Table 21: MR3 I/O Configuration 1 (MA[7:0] = 03h) ......................................................................................... 38
Table 22: MR3 Op-Code Bit Definitions .......................................................................................................... 38
Table 23: MR4 Device Temperature (MA[7:0] = 04h) ........................................................................................ 38
Table 24: MR4 Op-Code Bit Definitions .......................................................................................................... 38
Table 25: MR5 Basic Configuration 1 (MA[7:0] = 05h) ...................................................................................... 39
Table 26: MR5 Op-Code Bit Definitions .......................................................................................................... 39
Table 27: MR6 Basic Configuration 2 (MA[7:0] = 06h) ...................................................................................... 39
Table 28: MR6 Op-Code Bit Definitions .......................................................................................................... 39
Table 29: MR7 Basic Configuration 3 (MA[7:0] = 07h) ...................................................................................... 39
Table 30: MR7 Op-Code Bit Definitions .......................................................................................................... 40
Table 31: MR8 Basic Configuration 4 (MA[7:0] = 08h) ...................................................................................... 40
Table 32: MR8 Op-Code Bit Definitions .......................................................................................................... 40
Table 33: MR9 Test Mode (MA[7:0] = 09h) ....................................................................................................... 40
Table 34: MR10 Calibration (MA[7:0] = 0Ah) ................................................................................................... 40
Table 35: MR10 Op-Code Bit Definitions ........................................................................................................ 41
Table 36: MR11 ODT Control (MA[7:0] = 0Bh) ................................................................................................. 41
Table 37: MR11 Op-Code Bit Definitions ........................................................................................................ 41
Table 38: MR16 PASR Bank Mask (MA[7:0] = 010h) .......................................................................................... 41
Table 39: MR16 Op-Code Bit Definitions ........................................................................................................ 42
Table 40: MR17 PASR Segment Mask (MA[7:0] = 011h) .................................................................................... 42
Table 41: MR17 PASR Segment Mask Definitions ............................................................................................ 42
Table 42: MR17 PASR Row Address Ranges in Masked Segments ...................................................................... 42
Table 43: MR63 RESET (MA[7:0] = 3Fh) – MRW Only ....................................................................................... 42
Table 44: Reserved Mode Registers ................................................................................................................. 43
Table 45: Bank Selection for PRECHARGE by Address Bits ............................................................................... 58
Table 46: PRECHARGE and Auto Precharge Clarification ................................................................................. 63
Table 47: REFRESH Command Scheduling Separation Requirements .............................................................. 65
Table 48: Bank- and Segment-Masking Example ............................................................................................. 71
Table 49: Temperature Sensor Definitions and Operating Conditions .............................................................. 74
Table 50: Data Calibration Pattern Description ............................................................................................... 76
7
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Part Number Ordering Information
Table 51: Truth Table for MRR and MRW ........................................................................................................ 78
Table 52: CA Training Mode Enable (MR41 (29H, 0010 1001b), OP = A4H (1010 0100b)) .................................... 82
Table 53: CA Training Mode Disable (MR42 (2AH, 0010 1010b), OP = A8H(1010 1000b)) .................................... 82
Table 54: CA to DQ Mapping (CA Training Mode Enabled with MR41) ............................................................. 82
Table 55: CA Training Mode Enable (MR48 (30H, 0011 0000b), OP = C0H (1100 0000b)) .................................... 83
Table 56: CA to DQ Mapping (CA Training Mode Enabled with MR48) ............................................................. 83
Table 57: DRAM Termination Function in Write-Leveling Mode ...................................................................... 87
Table 58: ODT States Truth Table ................................................................................................................... 87
Table 59: Command Truth Table .................................................................................................................... 98
Table 60: CKE Truth Table .............................................................................................................................. 99
Table 61: Current State Bank n to Command to Bank n Truth Table ................................................................ 100
Table 62: Current State Bank n to Command to Bank m Truth Table ............................................................... 102
Table 63: DM Truth Table .............................................................................................................................. 105
Table 64: Absolute Maximum DC Ratings ...................................................................................................... 105
Table 65: Switching for CA Input Signals ........................................................................................................ 106
Table 66: Switching for IDD4R ......................................................................................................................... 106
Table 67: Switching for IDD4W ........................................................................................................................ 107
Table 68: IDD Specification Parameters and Operating Conditions .................................................................. 108
Table 69: Recommended DC Operating Conditions ....................................................................................... 110
Table 70: Input Leakage Current ................................................................................................................... 110
Table 71: Operating Temperature Range ........................................................................................................ 110
Table 72: Single-Ended AC and DC Input Levels for CA and CS_n Inputs ......................................................... 111
Table 73: Single-Ended AC and DC Input Levels for CKE ................................................................................ 111
Table 74: Single-Ended AC and DC Input Levels for DQ and DM ..................................................................... 111
Table 75: Differential AC and DC Input Levels ................................................................................................ 115
Table 76: CK and DQS Time Requirements Before Ringback ( tDVAC) .............................................................. 116
Table 77: Single-Ended Levels for CK and DQS .............................................................................................. 117
Table 78: Crosspoint Voltage for Differential Input Signals (CK, CK_c, DQS_t, DQS_c) ..................................... 118
Table 79: Differential Input Slew Rate Definition ............................................................................................ 118
Table 80: Single-Ended AC and DC Output Levels .......................................................................................... 120
Table 81: Differential AC and DC Output Levels ............................................................................................. 120
Table 82: Single-Ended Output Slew Rate Definition ...................................................................................... 120
Table 83: Single-Ended Output Slew Rate ...................................................................................................... 121
Table 84: Differential Output Slew Rate Definition ......................................................................................... 122
Table 85: Differential Output Slew Rate ......................................................................................................... 122
Table 86: AC Overshoot/Undershoot Specification ......................................................................................... 123
Table 87: Output Driver DC Electrical Characteristics with ZQ Calibration ...................................................... 126
Table 88: Output Driver Sensitivity Definition ................................................................................................ 126
Table 89: Output Driver Temperature and Voltage Sensitivity ......................................................................... 127
Table 90: Output Driver DC Electrical Characteristics Without ZQ Calibration ................................................ 127
Table 91: I-V Curves ..................................................................................................................................... 127
Table 92: ODT DC Electrical Characteristics (RZQ = 240Ω After Proper ZQ Calibration) .................................... 131
Table 93: Definitions and Calculations .......................................................................................................... 132
Table 94: tCK(abs), tCH(abs), and tCL(abs) Definitions ................................................................................... 133
Table 95: Refresh Requirement Parameters (Per Density) ............................................................................... 136
Table 96: AC Timing ..................................................................................................................................... 137
Table 97: CA Setup and Hold Base Values ...................................................................................................... 144
Table 98: CS_n Setup and Hold Base Values ................................................................................................... 145
Table 99: Derating Values for AC/DC-Based tIS/tIH (AC150) ........................................................................... 145
Table 100: Derating Values for AC/DC-Based tIS/tIH (AC135) ......................................................................... 145
Table 101: Required Time for Valid Transition – tVAC > V IH(AC) and < V IL(AC) ..................................................... 146
Table 102: Data Setup and Hold Base Values .................................................................................................. 152
8
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Part Number Ordering Information
Table 103: Derating Values for AC/DC-Based tDS/tDH (AC150) ....................................................................... 152
Table 104: Derating Values for AC/DC-Based tDS/tDH (AC135) ....................................................................... 152
Table 105: Required Time for Valid Transition – tVAC > V IH(AC) or < V IL(AC) ....................................................... 153
9
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Ball Assignments
Ball Assignments
Figure 2: 178-Ball Single-Channel FBGA – 1 x 8Gb Die
1
2
3
4
5
6
NU
NU
VDD1
VDD1
VDD1
NU
VSS
ZQ
NC
CA9
VSSCA
CA8
7
8
9
10
11
12
13
VDD1
VDD2
VDD2
VDD1
VDDQ
NU
NU
VSS
VSSQ
DQ31
DQ30
DQ29
DQ28
VSSQ
NU
NC
VSS
VSSQ
DQ27
DQ26
DQ25
DQ24
VDDQ
VSSCA
VDD2
VDD2
VDD2
DM3
DQ15 DQS3_t DQS3_c
VSSQ
CA7
CA6
VSS
VSS
VSSQ
VDDQ
DQ14
DQ13
DQ12
VDDQ
VDDCA
CA5
VSSCA
VSS
VSSQ
DQ11
DQ10
DQ9
DQ8
VSSQ
VDDCA
VSSCA
VSSCA
VDD2
VSSQ
DM1
VSSQ
VDDCA VREFCA
VDD2
VDD2
VDDQ
VDDQ
VSSQ
VDDQ
VDD2
A
B
C
D
E
F
G
DQS1_t DQS1_c VDDQ
H
VSS
J
CK_c
CK_t
VSSCA
VDD2
VDD2
ODT
VDDQ
VDDQ
VREFDQ
VSS
VSS
CKE
NC
VDD2
VDD2
VDDQ
NC
VSSQ
VDDQ
VDD2
VDDCA
CS_n
NC
VDD2
VSS
DM0
VSSQ
VDDCA
CA4
VSSCA
VSS
VSSQ
DQ4
DQ5
DQ6
DQ7
VSSQ
CA2
CA3
VSS
VSS
VSSQ
VDDQ
DQ1
DQ2
DQ3
VDDQ
CA1
VSSCA
VDD2
VDD2
VDD2
DM2
DQ0
CA0
NC
VSS
VSS
VSSQ
DQ20
DQ21
DQ22
DQ23
VDDQ
NU
VSS
VSS
VSS
VSS
VSSQ
DQ16
DQ17
DQ18
DQ19
VSSQ
NU
NU
NU
VDD1
VDD1
VDD1
VDD1
VDD2
VDD2
VDD1
VDDQ
NU
NU
K
L
DQS0_t DQS0_c VDDQ
M
N
P
DQS2_t DQS2_c
VSSQ
R
T
U
(Top view)
10
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Ball Assignments
Figure 3: 178-Ball Single-Channel FBGA – 2 x 8Gb Die
1
2
3
4
5
6
NU
NU
VDD1
VDD1
VDD1
NU
VSS
ZQ
NC
CA9
VSSCA
CA8
7
8
9
10
11
12
13
VDD1
VDD2
VDD2
VDD1
VDDQ
NU
NU
VSS
VSSQ
DQ31
DQ30
DQ29
DQ28
VSSQ
NU
NC
VSS
VSSQ
DQ27
DQ26
DQ25
DQ24
VDDQ
VSSCA
VDD2
VDD2
VDD2
DM3
DQ15 DQS3_t DQS3_c
VSSQ
CA7
CA6
VSS
VSS
VSSQ
VDDQ
DQ14
DQ13
DQ12
VDDQ
VDDCA
CA5
VSSCA
VSS
VSSQ
DQ11
DQ10
DQ9
DQ8
VSSQ
VDDCA
VSSCA
VSSCA
VDD2
VSSQ
DM1
VSSQ
VDDCA VREFCA
VDD2
VDD2
VDDQ
VDDQ
VSSQ
VDDQ
VDD2
A
B
C
D
E
F
G
DQS1_t DQS1_c VDDQ
H
VSS
J
CK_c
CK_t
VSSCA
VDD2
VDD2
ODT
VDDQ
VDDQ
VREFDQ
VSS
VSS
CKE0
CKE1
VDD2
VDD2
VDDQ
NC
VSSQ
VDDQ
VDD2
VDDCA
CS0_n
CS1_n
VDD2
VSS
DM0
VSSQ
VDDCA
CA4
VSSCA
VSS
VSSQ
DQ4
DQ5
DQ6
DQ7
VSSQ
CA2
CA3
VSS
VSS
VSSQ
VDDQ
DQ1
DQ2
DQ3
VDDQ
CA1
VSSCA
VDD2
VDD2
VDD2
DM2
DQ0
CA0
NC
VSS
VSS
VSSQ
DQ20
DQ21
DQ22
DQ23
VDDQ
NU
VSS
VSS
VSS
VSS
VSSQ
DQ16
DQ17
DQ18
DQ19
VSSQ
NU
NU
NU
VDD1
VDD1
VDD1
VDD1
VDD2
VDD2
VDD1
VDDQ
NU
NU
K
L
DQS0_t DQS0_c VDDQ
M
N
P
DQS2_t DQS2_c
VSSQ
R
T
U
(Top view)
11
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Ball Descriptions
Figure 4: 178-Ball Single-Channel FBGA – 4 x 8Gb Die
1
2
3
4
5
6
NU
NU
VDD1
VDD1
VDD1
NU
VSS
ZQ0
ZQ1
CA9
VSSCA
CA8
7
8
9
10
11
12
13
VDD1
VDD2
VDD2
VDD1
VDDQ
NU
NU
VSS
VSSQ
DQ31
DQ30
DQ29
DQ28
VSSQ
NU
NC
VSS
VSSQ
DQ27
DQ26
DQ25
DQ24
VDDQ
VSSCA
VDD2
VDD2
VDD2
DM3
DQ15 DQS3_t DQS3_c
VSSQ
CA7
CA6
VSS
VSS
VSSQ
VDDQ
DQ14
DQ13
DQ12
VDDQ
VDDCA
CA5
VSSCA
VSS
VSSQ
DQ11
DQ10
DQ9
DQ8
VSSQ
VDDCA
VSSCA
VSSCA
VDD2
VSSQ
DM1
VSSQ
VDDCA VREFCA
VDD2
VDD2
VDDQ
VDDQ
VSSQ
VDDQ
VDD2
A
B
C
D
E
F
G
DQS1_t DQS1_c VDDQ
H
VSS
J
CK_c
CK_t
VSSCA
VDD2
VDD2
ODT
VDDQ
VDDQ
VREFDQ
VSS
VSS
CKE0
CKE1
VDD2
VDD2
VDDQ
NC
VSSQ
VDDQ
VDD2
VDDCA
CS0_n
CS1_n
VDD2
VSS
DM0
VSSQ
VDDCA
CA4
VSSCA
VSS
VSSQ
DQ4
DQ5
DQ6
DQ7
VSSQ
CA2
CA3
VSS
VSS
VSSQ
VDDQ
DQ1
DQ2
DQ3
VDDQ
CA1
VSSCA
VDD2
VDD2
VDD2
DM2
DQ0
CA0
NC
VSS
VSS
VSSQ
DQ20
DQ21
DQ22
DQ23
VDDQ
NU
VSS
VSS
VSS
VSS
VSSQ
DQ16
DQ17
DQ18
DQ19
VSSQ
NU
NU
NU
VDD1
VDD1
VDD1
VDD1
VDD2
VDD2
VDD1
VDDQ
NU
NU
K
L
DQS0_t DQS0_c VDDQ
M
N
P
DQS2_t DQS2_c
VSSQ
R
T
U
(Top view)
Ball Descriptions
The ball/pad description table below is a comprehensive list of signals for the device
family. All signals listed may not be supported on this device. See Ball Assignments for
information specific to this device.
PDF: 09005aef85f8105e
178b_8-32gb_v01m_mobile-lpddr3.pdf – Rev. D 4/16 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Ball Descriptions
Table 3: Ball/Pad Descriptions
Symbol
Type
Description
CA[9:0]
Input
Command/address inputs: Provide the command and address inputs according to the
command truth table.
CK_t, CK_c
Input
Clock: Differential clock inputs. All CA inputs are sampled on both rising and falling
edges of CK. CS and CKE inputs are sampled at the rising edge of CK. AC timings are referenced to clock.
CKE[1:0]
Input
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, input buffers, and output drivers. Power-saving modes are entered and exited via CKE transitions. CKE is considered part of the command code. CKE is sampled on the rising edge of
CK.
CS[1:0]_n
Input
Chip select: Considered part of the command code and is sampled on the rising edge of
CK.
DM[3:0]
Input
Input data mask: Input mask signal for write data. Although DM balls are input-only,
the DM loading is designed to match that of DQ and DQS balls. DM[3:0] is DM for each of
the four data bytes, respectively.
ODT
Input
On-die termination: Enables and disables termination on the DRAM DQ bus according
to the specified mode register settings. For packages that do not support ODT, the ODT
signal may be grounded internally.
DQ[31:0]
I/O
Data input/output: Bidirectional data bus.
DQS[3:0]_t,
DQS[3:0]_c
I/O
Data strobe: Bidirectional (used for read and write data) and complementary (DQS_t
and DQS_c). It is edge-aligned output with read data and centered input with write data.
DQS[3:0]_t/DQS[3:0]_c is DQS for each of the four data bytes, respectively.
VDDQ
Supply
DQ power supply: Isolated on the die for improved noise immunity.
VSSQ
Supply
DQ ground: Isolated on the die for improved noise immunity.
VDDCA
Supply
Command/address power supply: Command/address power supply.
VSSCA
Supply
Command/address ground: Isolated on the die for improved noise immunity.
VDD1
Supply
Core power: Supply 1.
VDD2
Supply
Core power: Supply 2.
VSS
Supply
Common ground.
VREFCA, VREFDQ
Supply
Reference voltage: VREFCA is reference for command/address input buffers, VREFDQ is reference for DQ input buffers.
ZQ[1:0]
Reference
NU
–
Not usable: Do not connect.
NC
–
No connect: Not internally connected.
(NC)
–
No connect: Balls indicated as (NC) are no connects; however, they could be connected
together internally.
External reference ball for output drive calibration: This ball is tied to an external
240Ω resistor (RZQ), which is tied to VSSQ.
13
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Package Block Diagrams
Package Block Diagrams
Figure 5: Single-Die, Single-Channel Package Block Diagram
VDD1 VDD2 VDDQ VDDCA VSS
VREFCA
VSSCA VSSQ
VREFDQ
ZQ
CS_N
RZQ
CKE
CK_t
CK_c
DM[3:0]
LPDDR3
Die 0
CA[9:0]
DQ[31:0],
DQS[3:0]_t,
DQS[3:0]_c
ODT
14
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Package Block Diagrams
Figure 6: Dual-Rank, Dual-Die, Single-Channel Package Block Diagram
VDD1 VDD2 VDDQVDDCA VSS VSSCA VSSQ
VREFCA
VREFDQ
CS1_n
CKE1
ZQ
CS0_n
RZQ
CKE0
CK_t
CK_c
DM[3:0]
LPDDR3
LPDDR3
Die 0
Die 1
CA[9:0]
ODT
ODT
15
DQ[31:0], DQS[3:0]_t,
DQS[3:0]_c
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Package Block Diagrams
Figure 7: Quad-Die, Single-Channel Package Block Diagram
VDD1 VDD2 VDDQ VDDCA VSS VSSCA VSSQ
VREFCA
VREFDQ
ODT
ODT
LPDDR3
Die 0
CS1_n
CKE1
DM[1:0]
LPDDR3
Die 1
DM[3:2]
x16
DQ[15:0]
CK_t
x16
DQ[31:16]
CK_c
DM[3:0]
CA[9:0]
x16
DQ[15:0]
DM[1:0]
CKE0
CS0_n
ODT
x16
DQ[31:16]
DM[3:2]
LPDDR3
Die 3
LPDDR3
Die 2
ODT
ODT
16
RZQ1
ZQ1
DQ[31:16],
DQS[3:2]_t, DQS[3:2]_c
DQ[15:0],
DQS[1:0]_t, DQS[1:0]_c
ZQ0
RZQ0
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Package Dimensions
Package Dimensions
Figure 8: 178-Ball FBGA (11mm x 11.5mm)-MZ
Seating plane
A
178X Ø0.3
Dimensions apply
to solder balls postreflow on Ø0.28
SMD ball pads.
0.08 A
Ball A1 ID
13 12 11 10 9 8
Ball A1 ID
6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
11.5 ±0.1
10.4 CTR
0.65 TYP
0.8 TYP
0.92 ±0.08
9.6 CTR
0.17 MIN
11 ±0.1
Note:
1. All dimensions are in millimeters.
17
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Package Dimensions
Figure 9: 178-Ball FBGA (12.0mm x 11.5mm)-MM
Seating plane
A
178X Ø0.3
Dimensions apply
to solder balls postreflow on Ø0.28
SMD ball pads.
0.08 A
Ball A1 ID
13 12 11 10 9 8
Ball A1 ID
6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
11.5 ±0.1
10.4 CTR
0.65 TYP
0.8 TYP
0.9 ±0.1
9.6 CTR
0.17 MIN
12 ±0.1
Note:
1. All dimensions are in millimeters.
18
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MR0, MR5, MR6, MR8 Readout
MR0, MR5, MR6, MR8 Readout
Part Number
Total
Density
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
MR0
RS256M32LD3D1LMZ
8Gb
RS512M32LD3D2LMZ
16Gb
RS1G32LD3D4LMM
32Gb
OP6 = 1b indicates support for WL set B
OP7 = 1b indicates that the option for RL3 is supported
OP6 and OP7 =1b for this package
MR5
RS256M32LD3D1LMZ
8Gb
Manufacturer ID = 1111 1111b
RS512M32LD3D2LMZ
16Gb
Manufacturer ID = 0000 0110B
RS1G32LD3D4LMM
32Gb
MR6
RS256M32LD3D1LMZ
8Gb
RS512M32LD3D2LMZ
16Gb
RS1G32LD3D4LMM
32Gb
MR8
RS256M32LD3D1LMZ
Revision ID1 = 0000 0011b: Revision B
I/O Width/CS_n
8Gb
CS0_n
CS1_n
00b: x32
–
RS512M32LD3D2LMZ
16Gb
00b: x32 00b: x32
RS1G32LD3D4LMM
32Gb
01b: x16 01b: x16
19
Density
Type
0111b: 8Gb
11b: S8
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
IDD Specifications – Single Die
IDD Specifications – Single Die
Table 4: IDD Specifications
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –25°C to +85°C
Speed
Symbol
IDD01
Supply
2133
1866
1600
1333
VDD1
8
8
8
8
IDD02
VDD2
43
41.5
40
40
IDD0,in
VDDCA +
VDDQ
6
6
6
6
IDD2P1
VDD1
0.6
0.6
0.6
0.6
IDD2P2
VDD2
1.3
1.3
1.3
1.3
IDD2P,in
VDDCA +
VDDQ
0.1
0.1
0.1
0.1
IDD2PS1
VDD1
0.6
0.6
0.6
0.6
IDD2PS2
VDD2
1.3
1.3
1.3
1.3
IDD2PS,in
VDDCA +
VDDQ
0.1
0.1
0.1
0.1
IDD2N1
VDD1
0.6
0.6
0.6
0.6
IDD2N2
VDD2
22.5
21.5
20.5
20
IDD2N,in
VDDCA +
VDDQ
6
6
6
6
IDD2NS1
VDD1
0.6
0.6
0.6
0.6
IDD2NS2
VDD2
18.5
18.5
18.5
18.5
IDD2NS,in
VDDCA +
VDDQ
6
6
6
6
VDD1
1
1
1
1
IDD3P1
IDD3P2
VDD2
7
7
7
7
IDD3P,in
VDDCA +
VDDQ
0.1
0.1
0.1
0.1
20
Unit Parameter/Condition
mA
Operating one bank active-precharge current
= tCK(avg) MIN; tRC = tRC (MIN); CKE is
HIGH;
CS_n is HIGH between valid commands;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT disabled
tCK
mA
Idle power-down standby current
tCK = tCK(avg) MIN; CKE is LOW; CS_n is HIGH;
All banks idle; CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT disabled
mA
Idle power-down standby current with clock
stop
CK_t = LOW, CK_c = HIGH; CKE is LOW;
CS_n is HIGH; All banks idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT disabled
mA
Idle non power-down standby current
= tCK(avg) MIN; CKE is HIGH;
CS_n is HIGH; All banks idle;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT disabled
tCK
mA
Idle non power-down standby current with
clock stop
CK_t = LOW, CK_c = HIGH; CKE is HIGH;
CS_n is HIGH; All banks idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT disabled
mA
Active power-down standby current
= tCK(avg) MIN; CKE is LOW;
CS_n is HIGH; One bank active;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT disabled
tCK
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
IDD Specifications – Single Die
Table 4: IDD Specifications (Continued)
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –25°C to +85°C
Speed
Symbol
IDD3PS1
Supply
2133
1866
1600
1333
VDD1
1
1
1
1
IDD3PS2
VDD2
7
7
7
7
IDD3PS,in
VDDCA +
VDDQ
0.1
0.1
0.1
0.1
IDD3N1
VDD1
1.3
1.3
1.3
1.3
IDD3N2
VDD2
23
22
21
20.5
IDD3N,in
VDDCA +
VDDQ
6
6
6
6
IDD3NS1
VDD1
1.3
1.3
1.3
1.3
IDD3NS2
VDD2
19
19
19
19
IDD3NS,in
VDDCA +
VDDQ
6
6
6
6
IDD4R1
VDD1
2
2
2
2
IDD4R2
VDD2
330
(280)
290
(240)
250
(200)
220
(170)
IDD4R,in
VDDCA
6
6
6
6
IDD4W1
VDD1
2
2
2
2
IDD4W2
VDD2
325
(275)
285
(235)
245
(195)
215
(165)
IDD4W,in
VDDCA +
VDDQ
6
6
6
6
IDD51
VDD1
30
30
30
30
IDD52
VDD2
150
150
150
150
IDD5,in
VDDCA +
VDDQ
6
6
6
6
21
Unit Parameter/Condition
mA
mA
Active power-down standby current with clock
stop
CK_t = LOW, CK_c = HIGH; CKE is LOW;
CS_n is HIGH; One bank active;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT disabled
Active non power-down standby current
= tCK(avg) MIN; CKE is HIGH;
CS_n is HIGH; One bank active;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT disabled
tCK
mA
Active non power-down standby current with
clock stop
CK_t = LOW, CK_c = HIGH; CKE is HIGH;
CS_n is HIGH; One bank active;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT disabled
mA
Operating burst read current
tCK = tCK(avg) MIN;
CS_n is HIGH between valid commands;
One bank active; BL = 8; RL = RL (MIN);
CA bus inputs are SWITCHING;
50% data change each burst transfer;
ODT disabled;
Values in parenthesis are for x16 bits
mA
Operating burst write current
= tCK(avg) MIN;
CS_n is HIGH between valid commands;
One bank active; BL = 8; WL = WL (MIN);
CA bus inputs are SWITCHING;
50% data change each burst transfer;
ODT disabled;
Values in parenthesis are for x16 bits
tCK
mA
All bank auto-refresh burst current
tCK = tCK(avg) MIN;
CKE is HIGH between valid commands;
tRC = tRFCab (MIN); Burst refresh;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT disabled
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
IDD Specifications – Single Die
Table 4: IDD Specifications (Continued)
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –25°C to +85°C
Speed
Symbol
Supply
2133
1866
1600
1333
VDD1
3
3
3
3
IDD5AB2
VDD2
23
22
21
20.5
IDD5AB,in
VDDCA +
VDDQ
6
6
6
6
IDD5PB1
VDD1
3
3
3
3
IDD5PB2
VDD2
23
22
21
20.5
IDD5PB,in
VDDCA +
VDDQ
6
6
6
6
IDD81
VDD1
24
24
24
24
IDD82
VDD2
9
9
9
9
IDD8,in
VDDCA +
VDDQ
12
12
12
12
IDD5AB1
Notes:
Unit Parameter/Condition
mA
All bank auto-refresh average current
tCK = tCK(avg) MIN;
CKE is HIGH between valid commands;
tRC = tREFI;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT disabled
mA
Per bank auto-refresh average current
= tCK(avg) MIN;
CKE is HIGH between valid commands;
tRC = tREFIpb;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT disabled
tCK
μA
Deep power-down current
CK_t = LOW, CK _c = HIGH; CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT disabled
1. Published IDD values are the maximum of the distribution of the arithmetic mean.
2. IDD current specifications are tested after the device is properly initialized.
22
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
IDD Specifications – Single Die
Table 5: IDD6 Partial-Array Self Refresh Current at 25°C
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
PASR
Supply
Value
Unit
Full array
1/2 array
1/4 array
1/8 array
VDD1
200
(550)
VDD2
1100
(1700)
VDDCA + VDDQ
10
VDD1
140
(450)
VDD2
600
(1000)
VDDCA + VDDQ
10
VDD1
110
(400)
VDD2
400
(750)
VDDCA + VDDQ
10
VDD1
90
(370)
VDD2
300
(450)
VDDCA + VDDQ
10
Note:
μA
Parameter/Condition
Self refresh current
CK_t = LOW, CK_c = HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
Values in parentheses are the maximum of the distribution
of the arithmetic mean
1. IDD6 25°C is the typical of the distribution of the arithmetic mean.
Table 6: IDD6 Partial-Array Self Refresh Current at 85°C
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
PASR
Supply
Value
Unit
Full array
1/2 array
1/4 array
1/8 array
VDD1
1000
VDD2
7000
VDDCA + VDDQ
12
VDD1
600
VDD2
4100
VDDCA + VDDQ
12
VDD1
400
VDD2
2700
VDDCA + VDDQ
12
VDD1
300
VDD2
2000
VDDCA + VDDQ
12
Note:
μA
Parameter/Condition
Self refresh current
CK_t = LOW, CK_c = HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
1. IDD6 85°C is the typical of the distribution of the arithmetic mean.
23
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Pin Capacitance
Pin Capacitance
Table 7: Input/Output Capacitance
Part Number
Density Parameter
RS256M32LD3D1LMZ
8Gb
Part Number
Symbol
Min
Max
Unit
Notes
Input capacitance,
CK_t and CK_c
CCK
0.5
1.5
pF
1, 2
Input capacitance, all other input-only pins except
CS_n, CKE, and ODT
CI1
0.5
2.0
pF
1, 2
Input capacitance, CS_n,
CKE, and ODT
CI2
0.5
2.0
pF
1, 2
Input/output capacitance,
DQ, DM, DQS_t, DQS_c
CIO
1.0
3.0
pF
1, 2, 3
Input/output capacitance,
ZQ
CZQ
1.0
2.0
pF
1, 2, 3
Density Parameter
RS512M32LD3D2LMZ
16Gb
Part Number
Symbol
Min
Max
Unit
Notes
Input capacitance,
CK_t and CK_c
CCK
1.0
2.5
pF
1, 2
Input capacitance, all other input-only pins except
CS_n, CKE, and ODT
CI1
1.0
2.5
pF
1, 2
Input capacitance, CS_n,
CKE, and ODT
CI2
0.5
2.0
pF
1, 2
Input/output capacitance,
DQ, DM, DQS_t, DQS_c
CIO
1.5
4.5
pF
1, 2, 3
Input/output capacitance,
ZQ
CZQ
1.5
3.5
pF
1, 2, 3
Symbol
Min
Max
Unit
Notes
Input capacitance,
CK_t and CK_c
CCK
2.0
4.0
pF
1, 2
Input capacitance, all other input-only pins except
CS_n, CKE, and ODT
CI1
2.0
4.5
pF
1, 2
Input capacitance, CS_n,
CKE, and ODT
CI2
1.0
3.0
pF
1, 2
Input/output capacitance,
DQ, DM, DQS_t, DQS_c
CIO
1.5
4.5
pF
1, 2, 3
Input/output capacitance,
ZQ
CZQ
1.5
3.5
pF
1, 2, 3
Density Parameter
RS1G32LD3D4LMM
32Gb
Notes:
1. This parameter is not subject to production testing. It is verified by design and characterization.
2. These parameters are measured on f = 100 MHz, VOUT = VDDQ/2, TA = +25 °C.
3. DOUT circuits are disabled.
24
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
LPDDR3 Array Configuration
LPDDR3 Array Configuration
The 8Gb Mobile Low-Power DDR3 SDRAM (LPDDR3) is a high-speed CMOS, dynamic
random-access memory containing 8,589,934,592-bits. The device is internally configured as an eight-bank DRAM. Each of the x16’s 1,073,741,824-bit banks is organized as
32,768 rows by 2,048 columns by 16 bits. Each of the x32’s 1,073,741,824-bit banks is organized as 32,768 rows by 1024 columns by 32 bits.
General Notes
Throughout the data sheet, figures and text refer to DQs as “DQ.” DQ should be interpreted as any or all DQ collectively, unless specifically stated otherwise.
“DQS” and “CK” should be interpreted as DQS_t, DQS_c and CK_t, CK_c, respectively,
unless specifically stated otherwise. “BA” and "CA" include all BA and CA pins, respectively, used for a given density.
Complete functionality may be described throughout the entire document. Any page or
diagram may have been simplified to convey a topic and may not be inclusive of all requirements.
Timing diagrams reflect a single-channel device.
In timing diagrams, “CMD” is used as an indicator only. Actual signals occur on CA[9:0].
VREF indicates V REFCA and V REFDQ.
Any specific requirement takes precedence over a general statement.
Any functionality not specifically stated herein is considered undefined, illegal, is not
supported, and will result in unknown operation.
25
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Functional Description
Functional Description
Mobile LPDDR3 is a high-speed SDRAM internally configured as an 8-bank memory device. LPDDR3 uses a double data rate architecture on the command/address (CA) bus
to reduce the number of input pins in the system. The 10-bit CA bus is used to transmit
command, address, and bank information. Each command uses one clock cycle, during
which command information is transferred on both the rising and falling edges of the
clock.
LPDDR3 uses a double data rate architecture on the DQ pins to achieve high-speed operation. The double data rate architecture is essentially an 8n prefetch architecture with
an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins.
A single read or write access for LPDDR3 effectively consists of a single 8n-bit-wide,
one-clock-cycle data transfer at the internal SDRAM core and eight corresponding nbit-wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the device are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVATE command followed by a READ or
WRITE command. The address and BA bits registered coincident with the ACTIVATE
command are used to select the row and bank to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the
starting column location for the burst access.
26
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Functional Description
CK_t
CK_c
CKE
Clock
generator
Figure 10: Functional Block Diagram
CA[9:0]
Row
address
buffer
and
refresh
counter
Row decoder
Mode
register
Memory cell array
Bank 0
Sense amp.
Control logic
CS_n
Address/command decoder
Bank n
Column decoder
Column
address
buffer
and
burst
counter
Data control circuit
Latch circuit
Input and Output buffer
DQ
27
DQS_t, DQS_c
DM
ODT
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Simplified Bus Interface State Diagram
Simplified Bus Interface State Diagram
The state diagram provides a simplified illustration of the bus interface, supported state
transitions, and the commands that control them. For a complete description of device
behavior, use the information provided in the state diagram with the truth tables and
timing specifications. The truth tables describe device behavior and applicable restrictions when considering the actual state of all banks. For command descriptions, see the
Commands and Timing section.
28
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Simplified Bus Interface State Diagram
Figure 11: Simplified State Diagram
Power
applied
Deep
power-down
DPDX
Power-on
RE
Automatic sequence
SE
T
MRR
R
X
PD
ET
ES
Resetting
power-down
EF
X
DPD
PD
MRR
REF
Idle1
Refreshing
M
X
PD D
P
RW
Idle
MR reading
SR
EF
Resetting
SR
Resetting
MR reading
Command sequence
Self
refreshing
Idle
power-down
MR writing 2
ACT
Active
power-down
Active
MR reading
PD
X
PD
PR, PRA
R
MR
Active
RD
WR
WR3
RD 3
WR(A) = WRITE (with auto precharge)
Writing
PR, PRA
RD(A) = READ (with auto precharge)
RESET = RESET is achieved through
MRW command
WRA3
A
RD
ACT = ACTIVATE
W
RA
PRA = PRECHARGE ALL
Reading
RDA3
MRW = MODE REGISTER WRITE
MRR = MODE REGISTER READ
PD = Enter power-down
PDX = Exit power-down
Writing
with
auto precharge
Reading
with
auto precharge
SREF = Enter self refresh
SREFX = Exit self refresh
Precharging
DPD = Enter deep power-down
DPDX = Exit deep power-down
REF = REFRESH
Notes:
1. All banks are precharged in the idle state.
2. In the case of using MRW to enter CA training mode or write leveling mode, the state
machine will not automatically return to the idle state. In these cases, an additional
MRW command is required to exit either operating mode and return to the idle state.
See the CA Training Mode or Write Leveling Mode sections.
3. Terminated bursts are not allowed. For these state transitions, the burst operation must
be completed before a transition can occur.
29
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Up and Initialization
4. The state diagram is intended to provide a floorplan of the possible state transitions
and commands used to control them, but it is not comprehensive. In particular, situations involving more than one bank are not captured in full detail.
Power-Up and Initialization
The device must be powered up and initialized in a predefined manner. Power-up and
initialization by means other than those specified will result in undefined operation.
Voltage Ramp and Device Initialization
The following sequence must be used to power up the device. Unless specified otherwise, this procedure is mandatory.
1. Voltage Ramp: While applying power (after Ta), CKE must be held LOW, and all other
inputs must be between V ILmin and V IHmax. The device outputs remain at High-Z while
CKE is held LOW.
Following completion of the voltage ramp (Tb), CKE must be held LOW. DQ, DM and
DQS voltage levels must be between V SSQ and V DDQ during voltage ramp to avoid latchup. CK, CS_n, and CA input levels must be between V SSCA and V DDCA during voltage
ramp to avoid latch-up. Voltage ramp power supply requirements are provided in the
table below.
Table 8: Voltage Ramp Conditions
After
Applicable Conditions
Ta is reached
VDD1 must be greater than VDD2 - 200mV
VDD1 and VDD2 must be greater than VDDCA - 200mV
VDD1 and VDD2 must be greater than VDDQ - 200mV
VREF must always be less than all other supply voltages
Notes:
1. Ta is the point when any power supply first reaches 300mV.
2. Noted conditions apply between Ta and power-down (controlled or uncontrolled).
3. Tb is the point at which all supply and reference voltages are within their defined operating ranges.
4. For supply and reference voltage operating conditions, see the Recommended DC Operating Conditions table.
5. The voltage difference between any VSS, VSSQ, and VSSCA pins must not exceed 100mV.
Beginning at Tb, CKE must remain LOW for at least tINIT1, after which CKE can be asserted HIGH. The clock must be stable at least tINIT2 prior to the first CKE LOW-toHIGH transition (Tc). CKE, CS_n, and CA inputs must observe setup and hold requirements (tIS, tIH) with respect to the first rising clock edge and to subsequent falling and
rising edges.
If any MRRs are issued, the clock period must be within the range defined for tCKb.
MRWs can be issued at normal clock frequencies as long as all AC timings are met.
Some AC parameters (for example, tDQSCK) could have relaxed timings (such as
tDQSCKb) before the system is appropriately configured. While keeping CKE HIGH,
NOP commands must be issued for at least tINIT3 (Td). The ODT input signal may be in
an undefined state until tIS before CKE is registered HIGH. When CKE is registered
30
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Up and Initialization
HIGH, the ODT input signal must be statically held either LOW or HIGH. The ODT input signal remains static until the power-up initialization sequence is finished, including the expiration of tZQINIT.
2. RESET Command: After tINIT3 is satisfied, the MRW RESET command must be issued (Td). An optional PRECHARGE ALL command can be issued prior to the MRW RESET command. Wait at least tINIT4 while keeping CKE asserted and issuing NOP commands. Only NOP commands are allowed during tINIT4.
3. MRRs and Device Auto Initialization (DAI) Polling: After tINIT4 is satisfied (Te), only
MRR commands and POWER-DOWN ENTRY/EXIT commands are supported, and CKE
can go LOW in alignment with power-down entry and exit specifications (see PowerDown). MRR commands are valid at this time only when the CA bus does not need to be
trained. CA training can begin only after time Tf.
The MRR command can be initiated to poll the DAI bit, which indicates whether device
auto initialization is complete. When the bit indicates completion, the device is in an
idle state. The device is also in an idle state after tINIT5 (MAX) has expired, regardless
whether the DAI bit has been read by the MRR command. Because the memory output
buffers are not properly configured by Te, some AC parameters must use relaxed timing
specifications before the system is appropriately configured.
After the DAI bit (MR0, DAI) is set to zero by the memory device (DAI complete), the
device is in the idle state (Tf). DAI status can be determined by issuing the MRR command to MR0. The device sets the DAI bit no later than tINIT5 after the RESET command. The controller must wait at least tINIT5 (MAX) or until the DAI bit is set before
proceeding.
4. ZQ Calibration: If CA training is not required, the MRW INITIALIZATION CALIBRATION (ZQ_CAL) command can be issued to the memory (MR10) after Tf. No other CA
commands (other than RESET or NOP) may be issued prior to the completion of CA
training. After the completion of CA training (Tf'), the MRW INITIALIZATION CALIBRATION (ZQ_CAL) command can be issued to the memory.
This command is used to calibrate output impedance over process, voltage, and temperature. In systems where more than one LPDDR3 device exists on the same bus, the
controller must not overlap MRW ZQ_CAL commands. The device is ready for normal
operation after tZQINIT.
5. Normal Operation: AftertZQINIT (Tg), MRW commands must be used to properly
configure the memory (for example, output buffer drive strength, latencies, and so on).
Specifically, MR1, MR2, and MR3 must be set to configure the memory for the target frequency and memory configuration.
After the initialization sequence is complete, the device is ready for any valid command.
After Tg, the clock frequency can be changed using the procedure described in the Input Clock Frequency Changes and Clock Stop Events section.
31
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Up and Initialization
Figure 12: Voltage Ramp and Initialization Sequence
Ta
Tb
tINIT2
Tc
Td
Te
Tf
Tf’
Tg
CK_t/CK_c
tINIT0
Supplies
tINIT1
tINIT3
CKE
tINIT4
tISCKE
CA
RESET
tZQINIT
tINIT5
MRR
CA
Training
MRW
ZQ_CAL
Valid
DQ
Static HIGH or LOW
ODT
Notes:
Valid
1. High-Z on the CA bus indicates a valid NOP.
2. For tINIT values, see the Initialization Timing Parameters table.
3. After RESET command time (Tf), RTT is disabled until ODT function is enabled by MRW to
MR11 following Tg.
4. CA training is optional.
Table 9: Initialization Timing Parameters
Parameter
Min
Max
Unit
tINIT0
–
20
ms
Maximum voltage ramp time (Note 1)
tINIT1
100
–
ns
Minimum CKE LOW time after completion of voltage ramp
tINIT2
5
–
tCK
Minimum stable clock before first CKE HIGH
tINIT3
200
–
μs
Minimum idle time after first CKE assertion
tINIT4
1
–
μs
Minimum idle time after RESET command
tINIT5
–
10
μs
Maximum duration of device auto initialization (Note 2)
tZQINIT
1
–
μs
ZQ initial calibration
tCKb
18
100
ns
Clock cycle time during boot
Notes:
Comment
1. The tINIT0 maximum specification is not a tested limit and should be used as a general
guideline. For voltage ramp times exceeding tINIT0 MAX, please contact the factory.
2. If the DAI bit is not read via MRR, the device will be in the idle state after tINIT5 (MAX)
has expired.
Initialization After Reset (Without Voltage Ramp)
If the RESET command is issued before or after the power-up initialization sequence,
the reinitialization procedure must begin at Td.
32
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Off Sequence
Power-Off Sequence
The following procedure is required to power-off the device.
While powering off, CKE must be held LOW; all other inputs must be between V ILmin
and V IHmax. The device outputs remain at High-Z while CKE is held LOW.
DQ, DM, and DQS voltage levels must be between V SSQ and V DDQ during the power-off
sequence to avoid latch-up. CK, CS_n, and CA input levels must be between V SSCA and
VDDCA during the power-off sequence to avoid latch-up.
Tx is the point where any power supply drops below the minimum value specified in
the Recommended DC Operating Conditions table.
Tz is the point where all power supplies are below 300mV. After Tz, the device is powered off.
Table 10: Power Supply Conditions
Between...
Applicable Conditions
Tx and Tz
VDD1 must be greater than VDD2 - 200mV
VDD1 must be greater than VDDCA - 200mV
VDD1 must be greater than VDDQ - 200mV
VREF must always be less than all other supply voltages
Notes:
1. The voltage difference between any VSS, VSSQ, and VSSCA pins must not exceed 100mV.
2. For supply and reference voltage operating conditions, see Recommended DC Operating
Conditions table.
Uncontrolled Power-Off Sequence
When an uncontrolled power-off occurs, the following conditions must be met.
• At Tx, when the power supply drops below the minimum values specified in the Recommended DC Operating Conditions table, all power supplies must be turned off and
all power supply current capacity must be at zero, except for any static charge remaining in the system.
• After Tz (the point at which all power supplies first reach 300mV), the device must
power-off. During this period, the relative voltage between power supplies is uncontrolled. V DD1 and V DD2 must decrease with a slope lower than 0.5 V/μs between Tx
and Tz.
An uncontrolled power-off sequence can occur a maximum of 400 times over the life of
the device.
Table 11: Power-Off Timing
Parameter
Maximum power-off ramp time
33
Symbol
Min
Max
Unit
tPOFF
–
2
sec
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Standard Mode Register Definition
For LPDDR3, a set of mode registers is used for programming device operating parameters, reading device information and status, and for initiating special operations such as
DQ calibration, ZQ calibration, and device reset.
Mode Register Assignments and Definitions
Mode register definitions are provided in the Mode Register Assignments table. An "R"
in the access column of the table indicates read-only; "W" indicates write-only; "R/W"
indicates read- or write-capable or enabled. The MRR command is used to read from a
register. The MRW command is used to write to a register.
Table 12: Mode Register Assignments
Notes 1–5 apply to entire table
MR#
MA[7:0]
Function
Access
OP7
OP6
OP5
RL3
WL-B
RFU
0
00h
Device info
R
1
01h
Device feature 1
W
2
02h
Device feature 2
W
3
03h
I/O config-1
W
4
04h
SDRAM refresh
rate
R
5
05h
Basic config-1
R
OP4
WL
Select
OP2
RZQI
RFU
RFU
nWRE
OP0
DAI
Link
Go to MR0
BL
Go to MR1
RL and WL
Go to MR2
DS
Go to MR3
RFU
RFU
TUF
OP1
RFU
nWR (for AP)
WR
Lev
OP3
Refresh rate
Manufacturer ID
Go to MR4
Go to MR5
6
06h
Basic config-2
R
Revision ID1
Go to MR6
7
07h
Basic config-3
R
Revision ID2
Go to MR7
8
08h
Basic config-4
R
9
09h
Test mode
W
I/O width
Density
Type
Vendor-specific test mode
Go to MR8
Go to MR9
10
0Ah
I/O calibration
W
11
0Bh
ODT
W
Calibration code
12–15
0Ch–0Fh
Reserved
–
RFU
Go to MR12
16
10h
PASR_Bank
W
PASR bank mask
Go to MR16
RFU
PD ctl
Go to MR10
DQ ODT
Go to MR11
17
11h
PASR_Seg
W
PASR segment mask
Go to MR17
18–31
12h–1Fh
Reserved
–
RFU
Go to
MR18–MR31
32
20h
DQ calibration
pattern A
R
See Data Calibration Pattern Description
33–39
21h–27h
Do not use
–
40
28h
DQ calibration
pattern B
R
See Data Calibration Pattern Description
41
29h
CA training 1
W
See MRW - CA Training Mode
42
2Ah
CA training 2
W
See MRW - CA Training Mode
43–47
2Bh–2Fh
Do not use
–
CA training 3
W
See MRW - CA Training Mode
Reserved
–
RFU
48
30h
49–62
31h–3Eh
Go to MR33
Go to MR43
34
Go to MR49
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Table 12: Mode Register Assignments (Continued)
Notes 1–5 apply to entire table
MR#
MA[7:0]
Function
63
3Fh
64–255
40h–FFh
Access
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Link
RESET
W
X
Go to MR63
Reserved
–
RFU
Go to MR64
Notes:
1. RFU bits must be set to 0 during MRW.
2. RFU bits must be read as 0 during MRR.
3. For Reads to a write-only or RFU register, DQS is toggled and undefined data is returned.
4. RFU mode registers must not be written.
5. Writes to read-only registers must have no impact on the functionality of the device.
Table 13: MR0 Device Feature 0 (MA[7:0] = 00h)
OP7
OP6
OP5
RL3
WL-B
RFU
OP4
OP3
OP2
RZQI
OP1
RFU
OP0
DAI
Table 14: MR0 Op-Code BIt Definitions
Register
Information
Tag
Type
OP
Definition
DAI
Read-only
OP0
0b: DAI complete
1b: DAI in progress
Built-in self-test for
RZQ information
RZQI1
Read-only
OP[4:3]
WL Set B support
WL-B
Read-only
OP[6]
0b: Device does not support WL Set B
1b: Device supports WL Set B
RL3
Read-only
OP[7]
0b: Device does not support RL = 3, nWR = 3, WL = 1
1b: Device supports RL= 3, nWR = 3, WL = 1 for frequencies ≤166 MHz
Device auto initialization status
RL3 support
Notes:
00b: RZQ self-test not supported
01b: ZQ pin can connect to VDDCA or float
10b: ZQ pin can short to GND
11b: ZQ pin self-test completed, no error condition
detected (ZQ pin must not float; connect to VDD or
short to GND
1. RZQI will be set upon completion of the MRW ZQ INITIALIZATION CALIBRATION command.
2. If ZQ is connected to VDDCA to set default calibration, OP[4:3] must be set to 01. If ZQ is
not connected to VDDCA, either OP[4:3] = 01 or OP[4:3] = 10 may indicate a ZQ pin assembly error.
3. In the case of a possible assembly error, the device will default to factory trim settings
for RON and will ignore ZQ CALIBRATION commands. In either case, the system may not
function as intended.
4. If the ZQ self-test returns a value of 11b, it indicates that the device has detected a resistor connection to the ZQ pin. However, that result cannot be used to validate the ZQ
resistor value or that the ZQ resistor tolerance meets the specified limit of 240Ω
35
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Table 15: MR1 Device Feature 1 (MA[7:0] = 01h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
RFU
nWR (for AP)
OP0
BL
Table 16: MR1 Op-Code Bit Definitions
Feature
Type
OP
BL
Write-only
OP[2:0]
011b: BL8 (default)
All others: Reserved
nWR
Write-only
OP[7:5]
If nWR (MR2 OP[4]) = 0
001b: nWR = 3
100b: nWR = 6
110b: nWR = 8
111b: nWR = 9
If nWR (MR2 OP[4]) = 1
000b: nWR = 10 (default)
001b: nWR = 11
010b: nWR = 12
100b: nWR = 14
110b: nWR = 16
All others: Reserved
Notes:
Definition
Notes
1, 2
1. The programmed value in the nWR register is the number of clock cycles that determine
when to start the internal precharge operation for a WRITE burst with AP enabled. It is
determined by RU (tWR/tCK).
2. The range of nWR is extended (MR2 OP[4] = 1) by using an extra bit (nWRE) in MR2.
Table 17: Burst Sequence
Burst Cycle Number and Burst Address Sequence
C2
C1
C0
0b
0b
0b
0b
1b
0b
1b
0b
0b
1b
1b
0b
Note:
BL
8
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
2
3
4
5
6
7
0
1
4
5
6
7
0
1
2
3
6
7
0
1
2
3
4
5
1. C0 input is not present on CA bus; it is implied zero.
Table 18: MR2 Device Feature 2 (MA[7:0] = 02h)
OP7
OP6
OP5
OP4
WR Lev
WL Sel
RFU
nWRE
OP3
OP2
OP1
RL and WL
36
OP0
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Table 19: MR2 Op-Code Bit Definitions
Feature
RL and WL
Type
OP
Write-only
OP[3:0]
Definition
If OP[6] = 0 (default, WL Set A)
0001b: RL3/WL1 (≤166 MHz)1
0100b: RL6/WL3 (≤400 MHz)
0110b: RL8/WL4 (≤533 MHz)
0111b: RL9/WL5 (≤600 MHz)
1000b: RL10/WL6 (≤667 MHz, default)
1001b: RL11/WL6 (≤733 MHz)
1010b: RL12/WL6 (≤800 MHz)
1100b: RL14/WL8 (≤933 MHz)
1110b: RL16/WL8 (≤1066 MHz)
All others: Reserved
If OP[6] = 1 (WL Set B)
0001b: RL3/WL1 (≤166 MHz)1
0100b: RL6/WL3 (≤400 MHz)
0110b: RL8/WL4 (≤533 MHz)
0111b: RL9/WL5 (≤600 MHz)
1000b: RL10/WL8 (≤667 MHz, default)
1001b: RL11/WL9 (≤733 MHz)
1010b: RL12/WL9 (≤800 MHz)
1100b: RL14/WL11 (≤933 MHz)
1110b: RL16/WL13 (≤1066 MHz)
All others: Reserved
nWRE
Write-only
OP[4]
0b: Enable nWRE programming ≤9
1b: Enable nWRE programming >9 (default)
WL select
Write-only
OP[6]
0b: Use WL Set A (default)
1b: Use WL Set B2
WR Lev
Write-only
OP[7]
0b: Disable write leveling (default)
1b: Enable write leveling
Notes:
1. See MR0 OP7.
2. See MR0 OP6.
Table 20: LPDDR3 READ and WRITE Latency
Data Rate
(Mb/p/s)
tCK(ns)
333
800
1066
1200
1333
1466
1600
1866
2133
6
2.5
1.875
1.67
1.5
1.36
1.25
1.071
0.938
RL
3
6
8
9
10
11
12
14
16
WL (Set A)
1
3
4
5
6
6
6
8
8
WL (Set B)
1
3
4
5
8
9
9
11
13
37
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Table 21: MR3 I/O Configuration 1 (MA[7:0] = 03h)
OP7
OP6
OP5
OP4
OP3
OP2
RFU
OP1
OP0
OP1
OP0
DS
Table 22: MR3 Op-Code Bit Definitions
Feature
DS
Type
OP
Definition
Write-only
OP[3:0]
0001b: 34.3Ω typical
0010b: 40Ω typical (default)
0011b: 48Ω typical
0100b: Reserved
0110b: Reserved
1001b: 34.3Ω pull-down, 40Ω pull-up
1010b: 40Ω pull-down, 48Ω pull-up
1011b: 34.3Ω pull-down, 48Ω pull-up
All others: Reserved
Table 23: MR4 Device Temperature (MA[7:0] = 04h)
OP7
OP6
OP5
OP4
OP3
RFU
TUF
OP2
SDRAM refresh rate
Table 24: MR4 Op-Code Bit Definitions
Notes 1–8 apply to entire table
Feature
Type
OP
SDRAM refresh
rate
Read-only
OP[2:0]
Temperature update flag (TUF)
Read-only
OP7
Notes:
1.
2.
3.
4.
5.
6.
Definition
000b: SDRAM low-temperature operating limit exceeded
001b: 4 × tREFI, 4 × tREFIpb, 4 × tREFW
010b: 2 × tREFI, 2 × tREFIpb, 2 × tREFW
011b: 1 × tREFI, 1 × tREFIpb, 1 × tREFW (≤85˚C)
100b: 0.5 × tREFI, 0.5 × tREFIpb, 0.5 × tREFW, no AC timing derating
101b: 0.25 × tREFI, 0.25 × tREFIpb, 0.25 × tREFW, no AC timing derating
110b: 0.25 × tREFI, 0.25 × tREFIpb, 0.25 × tREFW, timing derating required
111b: SDRAM high-temperature operating limit exceeded
0b: OP[2:0] value has not changed since last read of MR4
1b: OP[2:0] value has changed since last read of MR4
A mode register read from MR4 will reset OP7 to 0.
OP7 is reset to 0 at power-up.
If OP2 = 1, the device temperature is greater than 85˚C.
OP7 is set to 1 if OP[2:0] has changed at any time since the last MR4 read.
The device might not operate properly when OP[2:0] = 000b or 111b.
For the specified operating temperature range and maximum operating temperature,
refer to the Operating Temperature Range table.
38
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
7. LPDDR3 devices must be derated by adding 1.875ns to the following core timing parameters: tRCD, tRC, tRAS, tRP, and tRRD. The tDQSCK parameter must be derated as specified in the AC Timing table. Prevailing clock frequency specifications and related setup
and hold timings remain unchanged.
8. The recommended frequency for reading MR4 is provided in the Temperature Sensor
section.
Table 25: MR5 Basic Configuration 1 (MA[7:0] = 05h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Manufacturer ID
Table 26: MR5 Op-Code Bit Definitions
Feature
Manufacturer ID
Type
OP
Definition
Read-only
OP[7:0]
0000 0011b: Micron 0000 0110B: Hynix Semiconductor
1111 1111b: Micron
All others: Reserved
Table 27: MR6 Basic Configuration 2 (MA[7:0] = 06h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
OP1
OP0
Revision ID1
Note:
1. MR6 is vendor-specific.
Table 28: MR6 Op-Code Bit Definitions
Feature
Revision ID1
Type
OP
Definition
Read-only
OP[7:0]
0000 0000b: Revision A
0000 0001b: Revision B
0000 0010b: Revision C
Table 29: MR7 Basic Configuration 3 (MA[7:0] = 07h)
OP7
OP6
OP5
OP4
OP3
Revision ID2
39
OP2
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Table 30: MR7 Op-Code Bit Definitions
Feature
Revision ID2
Note:
Type
OP
Read-only
OP[7:0]
Definition
RFU
1. MR7 is vendor-specific.
Table 31: MR8 Basic Configuration 4 (MA[7:0] = 08h)
OP7
OP6
OP5
OP4
I/O width
OP3
OP2
OP1
Density
OP0
Type
Table 32: MR8 Op-Code Bit Definitions
Type
OP
Type
Feature
Read-only
OP[1:0]
Definition
11b: LPDDR3
All other states reserved
Density
Read-only
OP[5:2]
0110b: 4Gb
1110b: 6Gb
0111b: 8Gb
1101b: 12Gb
1000b: 16Gb
1001b: 32Gb
All others: Reserved
I/O width
Read-only
OP[7:6]
00b: x32
01b: x16
All others: Reserved
Table 33: MR9 Test Mode (MA[7:0] = 09h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
OP2
OP1
OP0
Vendor-specific test mode
Table 34: MR10 Calibration (MA[7:0] = 0Ah)
OP7
OP6
OP5
OP4
OP3
Calibration code
40
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Table 35: MR10 Op-Code Bit Definitions
Notes 1–4 apply to entire table
Feature
Type
Calibration code
Write-only
Notes:
OP
Definition
OP[7:0]
0xFF: CALIBRATION command after initialization
0xAB: Long calibration
0x56: Short calibration
0xC3: ZQ reset
All others: Reserved
1. The device ignores calibration commands when a reserved value is written into MR10.
2. See AC Timing table for the calibration latency.
3. If ZQ is connected to VSSCA through RZQ, either the ZQ calibration function (see MRW ZQ
CALIBRATION Command) or default calibration (through the ZQ RESET command) is supported. If ZQ is connected to VDDCA, the device operates with default calibration and ZQ
CALIBRATION commands are ignored. In both cases, the ZQ connection must not change
after power is supplied to the device.
4. Devices that do not support calibration ignore the ZQ CALIBRATION command.
Table 36: MR11 ODT Control (MA[7:0] = 0Bh)
OP7
OP6
OP5
OP4
OP3
Reserved
OP2
OP1
PD CTL
OP0
DQ ODT
Table 37: MR11 Op-Code Bit Definitions
Feature
Type
OP
DQ ODT
Write-only
OP[1:0]
PD control
Write-only
OP[2]
Note:
Definition
00b: Disable (default)
01b: RZQ/4 (Note1)
10b: RZQ/2
11b: RZQ/1
00b: ODT disabled by DRAM during power-down (default)
01b: ODT enabled by DRAM during power-down
1. RZQ/4 is supported for LPDDR3-1866 and LPDDR3-2133 devices. RZQ/4 support is optional for LPDDR3-1333 and LPDDR3-1600 devices. Consult Micron specifications for RZQ/4
support for LPDDR3-1333 and LPDDR3-1600.
Table 38: MR16 PASR Bank Mask (MA[7:0] = 010h)
OP7
OP6
OP5
OP4
OP3
PASR bank mask
41
OP2
OP1
OP0
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Table 39: MR16 Op-Code Bit Definitions
Feature
Bank[7:0] mask
Type
OP
Write-only
OP[7:0]
Definition
0b: Refresh enable to the bank = unmasked (default)
1b: Refresh blocked = masked
Table 40: MR17 PASR Segment Mask (MA[7:0] = 011h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
PASR segment mask
Table 41: MR17 PASR Segment Mask Definitions
Feature
Segment[7:0] mask
Type
OP
Write-only
OP[7:0]
Definition
0b: Refresh enable to the segment = unmasked (default)
1b: Refresh blocked = masked
Table 42: MR17 PASR Row Address Ranges in Masked Segments
4Gb
6Gb2, 8Gb,
12Gb2 & 16Gb
32Gb
R[13:11]
R[14:12]
TBD
Segment
OP
Segment Mask
0
0
XXXXXXX1
000b
1
1
XXXXXX1X
001b
2
2
XXXXX1XX
010b
3
3
XXXX1XXX
011b
4
4
XXX1XXXX
100b
5
5
XX1XXXXX
101b
6
6
X1XXXXXX
110b
7
7
1XXXXXXX
111b
Notes:
1. X = “Don’t Care” for the designated segment.
2. No memory present at addresses with R13 = R14 = HIGH. Segment masks 6 and 7 are ignored.
Table 43: MR63 RESET (MA[7:0] = 3Fh) – MRW Only
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
X or 0xFCh
Note:
1. For additional information on MRW RESET, see the Mode Register Write (MRW) section.
42
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Table 44: Reserved Mode Registers
Mode
Register
MA
Address
Restriction
MR[12:15]
MA[7:0]
0Ch-0Fh
Reserved
Reserved
MR[18:31]
12h–1Fh
Reserved
Reserved
MR[33:39]
21h–27h
DNU
DNU
OP7
OP6
OP5
OP4
OP3
MR[43:47]
2Bh–2Fh
DNU
DNU
MR[49:62]
31h–3Eh
Reserved
Reserved
MR[64:255]
40h–FFh
Reserved
Reserved
Note:
1. DNU = Do not use; RVU = Reserved for vendor use.
43
OP2
OP1
OP0
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Commands and Timing
Commands and Timing
The setup and hold timings shown in the figures below apply for all commands.
Figure 13: Command and Input Setup and Hold
T0
T1
T2
T3
tIS tIH
tIS tIH
CK_c
CK_t
CS_n
VIL(DC)
VIL(AC)
VIH(AC)
tIS tIH
CA[9:0]
CA
rise
CA
fall
CA
rise
NOP
CMD
VIH(DC)
tIS tIH
CA
fall
Command
CA
rise
CA
fall
NOP
Don’t Care
Note:
CA
rise
CA
fall
Command
Transitioning data
1. Setup and hold conditions also apply to the CKE pin. For timing diagrams related to the
CKE pin, see the Power-Down section.
Figure 14: CKE Input Setup and Hold
T0
T1
Tx
Tx + 1
CK_c
CK_t
tIHCKE
CKE
VIHCKE
tISCKE
tIHCKE
VILCKE
VILCKE
tISCKE
VIHCKE
HIGH or LOW, but defined
Notes:
1. After CKE is registered LOW, the CKE signal level is maintained below VILCKE for tCKE
specification (LOW pulse width).
2. After CKE is registered HIGH, the CKE signal level is maintained above VIHCKE for tCKE
(HIGH pulse width).
44
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
ACTIVATE Command
ACTIVATE Command
The ACTIVATE command is issued by holding CS_n LOW, CA0 LOW, and CA1 HIGH at
the rising edge of the clock. The bank addresses BA[2:0] are used to select the desired
bank. Row addresses are used to determine which row to activate in the selected bank.
The ACTIVATE command must be applied before any READ or WRITE operation can be
executed. The device can accept a READ or WRITE command at tRCD after the ACTIVATE command is issued. After a bank has been activated, it must be precharged before
another ACTIVATE command can be applied to the same bank. The bank active and
precharge times are defined as tRAS and tRP, respectively. The minimum time interval
between successive ACTIVATE commands to the same bank is determined by the RAS
cycle time of the device (tRC). The minimum time interval between ACTIVATE commands to different banks is tRRD.
Figure 15: ACTIVATE Command
CK_c
CK_t
CA[9:0]
Bank n
row addr Row addr
Bank m
Bank n
row addr Row addr col addr
Col addr
Bank n
row addr Row addr
Bank n
tRRD
tRCD
tRP
tRAS
tRC
CMD
ACTIVATE
ACTIVATE
NOP
Note:
READ
PRECHARGE
NOP
NOP
ACTIVATE
1. A PRECHARGE ALL command uses tRPab timing, and a single-bank PRECHARGE command uses tRPpb timing. In this figure, tRP denotes either an all-bank PRECHARGE or a
single-bank PRECHARGE.
8-Bank Device Operation
Certain restrictions must be taken into consideration when operating 8-bank devices;
one restricts the number of sequential ACTIVATE commands that can be issued and
one provides additional RAS precharge time for a PRECHARGE ALL command.
The 8-Bank Device Sequential Bank Activation Restriction: No more than four banks
can be activated (or refreshed, in the case of REFpb) in a rolling tFAW window. The
number of clocks in a tFAW period depends on the clock frequency, which may vary. If
the clock frequency is not changed over this period, convert to clocks by dividing
tFAW[ns] by tCK[ns] and then rounding up to the next integer value. As an example of
the rolling window, if RU(tFAW/tCK) is 10 clocks, and an ACTIVATE command is issued
in clock n, no more than three further ACTIVATE commands can be issued at or between clock n + 1 and n + 9. REFpb also counts as bank activation for purposes of tFAW.
If the clock is changed during the tFAW period, the rolling tFAW window may be calculated in clock cycles by adding together the time spent in each clock period. The tFAW requirement is met when the previous n clock cycles exceeds the tFAW time.
The 8-Bank Device PRECHARGE ALL Provision: tRP for a PRECHARGE ALL command
must equal tRPab, which is greater than tRPpb.
45
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Read and Write Access Modes
Figure 16: tFAW Timing
Tn
Tn+
Tm
Tm+
Tx
Tx+
Ty
Ty + 1
Ty + 2
Tz
Tz + 1
Tz + 2
CK_c
CK_t
CA[9:0]
Bank Bank
A
A
Bank Bank
B
B
tRRD
CMD ACTIVATE
NOP
Bank Bank
C
C
tRRD
ACTIVATE
NOP
Bank Bank
D
D
Bank Bank
E
E
tRRD
ACTIVATE
NOP
ACTIVATE
NOP
NOP
NOP
ACTIVATE
NOP
tFAW
Read and Write Access Modes
After a bank is activated, a READ or WRITE command can be issued with CS_n LOW,
CA0 HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at
this time to determine whether the access cycle is a READ operation (CA2 HIGH) or a
WRITE operation (CA2 LOW). A single READ or WRITE command initiates a burst
READ or burst WRITE operation on successive clock cycles. Burst interrupts are not allowed.
46
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst READ Command
Burst READ Command
The burst READ command is initiated with CS_n LOW, CA0 HIGH, CA1 LOW, and CA2
HIGH at the rising edge of the clock. The command address bus inputs, CA5r–CA6r and
CA1f–CA9f, determine the starting column address for the burst. The read latency (RL)
is defined from the rising edge of the clock on which the READ command is issued to
the rising edge of the clock from which the tDQSCK delay is measured. The first valid
data is available RL × tCK + tDQSCK + tDQSQ after the rising edge of the clock when the
READ command is issued. The data strobe output is driven LOW tRPRE before the first
valid rising strobe edge. The first bit of the burst is synchronized with the first rising
edge of the data strobe. Each subsequent data-out appears on each DQ pin, edgealigned with the data strobe. The RL is programmed in the mode registers. Pin input
timings for the data strobe are measured relative to the crosspoint of DQS_t and its
complement, DQS_c.
Figure 17: READ Output Timing
RL-1
tCH
tCL
RL
RL + BL/ 2
CK_c
CK_t
tHZ(DQS)
tDQSCK
tLZ(DQS)
tRPST
tRPRE
DQS_c
DQS_t
tQH
tQH
tDQSQmax
tDQSQmax
DOUT
DQ
DOUT
DOUT
DOUT
tLZ(DQ)
DOUT
DOUT
DOUT
DOUT
tHZ(DQ)
Transitioning data
Note:
1. tDQSCK can span multiple clock periods.
Figure 18: Burst READ – RL = 12, BL = 8, tDQSCK > tCK
T0
T1
T2
T12
Ta-1
Ta
Ta+1
Ta+2
Ta+3
Ta+4
CK_c
CK_t
RL = 12
CA[9:0]
CMD
Bank n
col addr
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCK
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
Transitioning data
47
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst READ Command
Figure 19: Burst READ – RL = 12, BL = 8, tDQSCK < tCK
T0
T1
T2
T12
T13
T14
T15
T16
T17
CK_c
CK_t
RL = 12
CA[9:0]
Bank n
col addr
CMD
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCK
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3 DOUTA4
DOUTA5
DOUTA6
DOUTA7
Transitioning data
Figure 20: Burst READ Followed by Burst WRITE – RL = 12, WL = 6, BL = 8
T0
T1
T2
T12
Ta - 1
Ta
Ta + 1
Ta + 2
Ta + 3
Ta + 4
Ta + 9
Ta + 10
CK_c
CK_t
RL = 12
CA[9:0]
CMD
Bank n
col addr
BL/2
WL = 6
Bank n
col addr
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Col addr
WRITE
tDQSCK
NOP
NOP
NOP
tDQSSmin
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
DIN A0
DIN A1
DIN
Transitioning Data
The minimum time from the burst READ command to the burst WRITE command is
defined by the read latency (RL) and the burst length (BL). Minimum READ-to-WRITE
latency is RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1 - WL clock cycles.
48
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst READ Command
Figure 21: Seamless Burst READ – RL = 6, BL = 8, tCCD = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK_c
CK_t
RL = 6
CA[9:0]
tCCD
CMD
Bank n
Col addr b
col addr b
Bank n
Col addr a
col addr a
READ
tCCD
=4
NOP
NOP
NOP
READ
Bank n
Col addr c
col addr c
Bank n
Col addr d
col addr d
=4
NOP
NOP
NOP
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
DOUTB0
DOUTB1
DOUTB2
DOUTB3
DOUTB4
DOUTB5
DOUTB6
DOUTB7
DOUTC0
DOUTC1
Transitioning data
The seamless burst READ operation is supported by enabling a READ command at every fourth clock cycle for BL = 8 operation. This operation is supported as long as the
banks are activated, whether the accesses read the same or different banks.
tDQSCK
Delta Timing
To allow the system to track variations in tDQSCK output across multiple clock cycles,
three parameters are provided: tDQSCKDL (delta long), tDQSCKDM (delta medium),
and tDQSCKDS (delta short). Each of these parameters defines the change in tDQSCK
over a short, medium, or long rolling window, respectively. The definition for each
tDQSCK-delta parameter is shown in the figures below.
49
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst READ Command
Figure 22: tDQSCKDL Timing
Tn
Tn + 1
Tn + 2
Tn + 9
Tn + 10
Ta
Ta + 1
Ta + 12
CK_c
CK_t
RL = 10
CA
[9:0]
Bankn
Col addr
col addr
CMD
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKn
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2 DOUTA3 DOUTA4
32ms maximum…
1
Tm
Tm + 1
Tm + 2
Tm + 9
Tm + 10
Tb
Tb + 1
Tb + 2
CK_c
CK_t
RL = 10
CA
[9:0]
Bankn
Col addr
col addr
CMD
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKm
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2 DOUTA3 DOUTA4
…32ms maximum
Transitioning data
1
Notes:
1. tDQSCKDL = (tDQSCKn - tDQSCKm).
2. tDQSCKDL (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any
(tDQSCKn, tDQSCKm) pair within any 32ms rolling window.
50
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst READ Command
Figure 23: tDQSCKDM Timing
Tn
Tn + 1
Tn + 2
Tn + 9
Tn + 10
Ta
Ta + 1
Ta + 2
CK_c
CK_t
RL = 10
CA
[9:0]
Bank n
col addr
CMD
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKn
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
1.6μs maximum…
1
Tm
Tm + 1
Tm + 2
Tm + 9
Tm + 10
Tb
Tb + 1
Tb + 2
CK_c
CK_t
RL = 10
CA
[9:0]
Bank n
col addr
CMD
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKm
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
…1.6μs maximum
Transitioning data
1
Notes:
1. tDQSCKDM = (tDQSCKn - tDQSCKm).
2. tDQSCKDM (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any
(tDQSCKn, tDQSCKm) pair within any 1.6μs rolling window.
51
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst READ Command
Figure 24: tDQSCKDS Timing
Tn
Tn + 1
Tn + 2
Tn + 9
Tn + 10
Ta
Ta + 1
Ta + 2
CK_c
CK_t
RL = 10
CA
[9:0]
Bank n
col addr
CMD
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKn
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3 DOUTA4
160ns maximum…
1
Tm
Tm + 1
Tm + 2
Tm + 9
Tm + 10
Tb
Tb + 1
Tb + 2
CK_c
CK_t
RL = 10
CA
[9:0]
Bank n
col addr
CMD
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKm
DQS_c
DQS_t
DQ
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
DOUTA0
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
…160ns maximum
Transitioning data
1
Notes:
1. tDQSCKDS = (tDQSCKn - tDQSCKm).
2. tDQSCKDS (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any
(tDQSCKn, tDQSCKm) pair for READs within a consecutive burst, within any 160ns rolling
window.
52
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst WRITE Command
Burst WRITE Command
The burst WRITE command is initiated with CS_n LOW, CA0 HIGH, CA1 LOW, and CA2
LOW at the rising edge of the clock. The command address bus inputs, CA5r–CA6r and
CA1f–CA9f, determine the starting column address for the burst. Write latency (WL) is
defined from the rising edge of the clock on which the WRITE command is issued to the
rising edge of the clock from which the tDQSS delay is measured. The first valid data
must be driven WL × tCK + tDQSS from the rising edge of the clock from which the
WRITE command is issued. The data strobe signals (DQS) must be driven as shown in
Figure 27 (page 54). The burst cycle data bits must be applied to the DQ pins tDS prior
to the associated edge of the DQS and held valid until tDH after that edge. Burst data is
sampled on successive edges of the DQS_t until the burst length is completed. After a
burst WRITE operation, tWR must be satisfied before a PRECHARGE command to the
same bank can be issued. Pin input timings are measured relative to the crosspoint of
DQS_t and its complement, DQS_c.
Figure 25: Data Input (WRITE) Timing
tDQSL
tDQSH
tDQSL
tWPST
DQS_c
DQS_t
tWPRE
VIH(AC)
DQ
VIH(AC)
VIH(DC)
DIN
VIL(AC) tDS
tDH
DIN
VIL(DC)
tDH
tDS
DIN
tDS
tDH
VIH(DC)
DIN
VIL(AC) tDS
VIH(AC)
VIH(DC)
VIH(AC)
VIH(DC)
VIL(AC)
VIL(DC)
VIL(AC)
VIL(DC)
tDH
VIL(DC)
DM
53
Don’t Care
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst WRITE Command
Figure 26: Burst WRITE
T0
Ta
Ta + 1
...
Ta + 5
Tx
Tx + 1
Ty
Ty + 1
CK_c
CK_t
WL
CA[9:0]
CMD
Bank n
col addr
Col addr
WRITE
NOP
Case 1: tDQSS (MAX)
DQS_c
DQS_t
NOP
tDQSS
DIN A0
tDQSS
DQ
(MIN)
NOP
tDSS
(MAX)
DQ
Case 2: tDQSS (MIN)
DQS_c
DQS_t
Bank n Row addr
row addr
Bank n
tDSH
DIN A0
NOP
tDSS
DIN A1
DIN A6
PRECHARGE
NOP
ACTIVATE
NOP
Completion of burst WRITE
tWR
tRP
tWR
tRP
DIN A7
tDSH
DIN A1
DIN A2
DIN A7
Don’t Care
Figure 27: Method for Calculating tWPRE Transitions and Endpoints
CK_t
VTT
CK_c
T1
begins
tWPRE
DQS_t - DQS_c
0V
tWPRE
T2
Resulting differential
signal relevant for
tWPRE specification
tWPRE
54
ends
Transitioning Data
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst WRITE Command
Figure 28: Method for Calculating tWPST Transitions and Endpoints
CK_t
VTT
CK_c
tWPST
DQS_t - DQS_c
0V
Resulting differential
signal relevant for
tWPST specification
T1
begins
tWPST
T2
ends
tWPST
Figure 29: Burst WRITE Followed by Burst READ
T0
Tx
Tx + 1
Tx + 2
Tx + 5
Tx + 9
Tx + 10
Tx + 11
CK_c
CK_t
RL
WL
CA[9:0]
Bank m
Col addr a
col addr a
Bank n
Col addr b
col addr b
tWTR
CMD
WRITE
NOP
NOP
NOP
NOP
NOP
READ
NOP
NOP
DQS_c
DQS_t
DQ
DIN A0
DIN A1
DIN A7
Don’t Care
Notes:
Transitioning Data
1. The minimum number of clock cycles from the burst WRITE command to the burst READ
command for any bank is [WL + 1 + BL/2 + RU(tWTR/tCK)].
2. tWTR starts at the rising edge of the clock after the last valid input data.
55
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst WRITE Command
Figure 30: Seamless Burst WRITE – WL = 4, BL = 8, tCCD = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
CK_c
CK_t
WL = 4
CA[9:0]
Bankm Col addr a
col addr a
tCCD
CMD
WRITE
Bankn Col addr b
col addr b
Bankn Col addr c
col addr c
Bankn Col addr d
col addr d
=4
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
WRITE
NOP
DQS_c
DQS_t
DQ
DIN A0
DIN A1
DIN A2
DIN A3
DIN A4
DIN A5
DIN A6
DIN A7
DIN B0
DIN B1
DIN B2
DIN B3
DIN B4
DIN B5
Don’t Care
Note:
DIN B6
DIN B7
DIN C0
DIN C1
Transitioning Data
1. The seamless burst WRITE operation is supported by enabling a WRITE command every
four clocks for BL = 8 operation. This operation is supported for any activated bank.
56
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Write Data Mask
Write Data Mask
LPDDR3 devices support one write data mask (DM) pin for each data byte (DQ), which
is consistent with LPDDR2 devices. Each DM can mask its respective DQ for any given
cycle of the burst. Data mask timings match data bit timing, but are inputs only. Internal data mask loading is identical to data bit loading to ensure matched system timing.
Figure 31: Data Mask Timing
DQS_c
DQS_t
DQ
tDS
VIH(AC)
tDH
VIH(DC) VIH(AC)
tDS
tDH
VIH(DC)
DM
VIL(AC)
VIL(DC) VIL(AC)
VIL(DC)
Don’t Care
Figure 32: Write Data Mask – Second Data Bit Masked
CK_c
CK_t
tWR
tWTR
WL
CMD
WRITE
Case 1: t DQSS (MIN)
tDQSS
(MIN)
DQS_t
DQS_c
DOUT 1
DQ
DOUT 0
DOUT 2 DOUT 3
DOUT 4 DOUT 5 DOUT 6
DOUT 7
DM
Case 2: t DQSS (MAX)
tDQSS
(MAX)
DQS_t
DQS_c
DOUT 1
DQ
DOUT 0
DOUT 2 DOUT 3 DOUT 4
DOUT 5 DOUT 6 DOUT 7
DM
Don’t Care
57
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
PRECHARGE Command
PRECHARGE Command
The PRECHARGE command is used to precharge or close a bank that has been activated. The PRECHARGE command is initiated with CS_n LOW, CA0 HIGH, CA1 HIGH,
CA2 LOW, and CA3 HIGH at the rising edge of the clock. The PRECHARGE command
can be used to precharge each bank independently or all banks simultaneously. The AB
flag and the bank address bits BA0, BA1, and BA2 are used to determine which bank(s)
to precharge. The precharged bank(s) will be available for subsequent row access tRPab
after an all-bank PRECHARGE command is issued, or tRPpb after a single-bank PRECHARGE command is issued.
To ensure that LPDDR3 devices can meet the instantaneous current demand required
to operate, the row precharge time (tRP) for an all bank PRECHARGE (tRPab) will be longer than the row precharge time for a single-bank PRECHARGE (tRPpb). ACTIVATE to
PRECHARGE timing is shown in the ACTIVATE Command figure.
Table 45: Bank Selection for PRECHARGE by Address Bits
AB (CA4r)
BA2 (CA9r)
BA1 (CA8r)
BA0 (CA7r)
Precharged Bank(s)
8-Bank Device
0
0
0
0
Bank 0 only
0
0
0
1
Bank 1 only
0
0
1
0
Bank 2 only
0
0
1
1
Bank 3 only
0
1
0
0
Bank 4 only
0
1
0
1
Bank 5 only
0
1
1
0
Bank 6 only
0
1
1
1
Bank 7 only
1
Don’t Care
Don’t Care
Don’t Care
All banks
58
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
PRECHARGE Command
Burst READ Operation Followed by PRECHARGE
For the earliest possible precharge, the PRECHARGE command can be issued BL/2
clock cycles after a READ command. A new bank ACTIVATE command can be issued to
the same bank after the row precharge time (tRP) has elapsed. A PRECHARGE command cannot be issued until after tRAS is satisfied.
For LPDDR3 devices, the minimum READ-to-PRECHARGE time (tRTP) must also satisfy
a minimum analog time from the rising clock edge that initiates the last 8-bit prefetch
of a READ command. tRTP begins BL/2 - 4 clock cycles after the READ command. For
LPDDR3 READ-to-PRECHARGE timings, see the PRECHARGE and Auto Precharge Clarification table.
Figure 33: Burst READ Followed by PRECHARGE – BL = 8, RU(tRTP(MIN)/tCK) = 2
T0
T1
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
CK_c
CK_t
RL
CA[9:0]
Bank m
col addr a Col addr a
Bank m
Row addr
row addr
Bank m
tRP
tRTP
CMD
READ
NOP
NOP
PRECHARGE
NOP
NOP
NOP
ACTIVATE
NOP
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
Transitioning Data
59
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
PRECHARGE Command
Burst WRITE Followed by PRECHARGE
For WRITE cycles, a WRITE recovery time ( tWR) must be provided before a PRECHARGE
command can be issued. This delay is referenced from the last valid burst input data to
the completion of the burst WRITE. The PRECHARGE command must not be issued
prior to the tWR delay. For LPDDR3 WRITE-to-PRECHARGE timings, see the PRECHARGE and Auto Precharge Clarification table.
LPDDR3 devices write data to the array in prefetch multiples (prefetch = 8). An internal
WRITE operation can begin only after a prefetch group has been completely latched, so
tWR starts at prefetch bondaries.
The minimum WRITE-to-PRECHARGE time for commands to the same bank is WL +
BL/2 + 1 + RU(tWR/tCK) clock cycles.
Figure 34: Burst WRITE Followed by PRECHARGE – BL = 8
T0
Tx
Tx + 1
Tx + 4
Tx + 5
Ty
Ty + 1
Tz
Tz + 1
CK_c
CK_t
WL
CA[9:0]
Bankn
col addr
Col addr
≥ tRP
tWR
CMD
WRITE
Case 1: t DQSS (MAX)
Bankn Row addr
row addr
Bankn
NOP
NOP
tDQSS
NOP
NOP
(MAX)
PRECHARGE
NOP
ACTIVATE
NOP
Completion of burst WRITE
DQS_c
DQS_t
DQ
Case 2: t DQSS (MIN)
tDQSS
DIN A0
DIN A5
DIN A6
DIN A1
DIN A6
DIN A7
DIN A7
(MIN)
DQS_c
DQS_t
DQ
DIN A0
Don’t Care
60
Transitioning Data
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
PRECHARGE Command
Auto Precharge
Before a new row can be opened in an active bank, the active bank must be precharged
using either the PRECHARGE command or the auto precharge function. When a READ
or WRITE command is issued to the device, the AP bit (CA0f) can be set to enable the
active bank to automatically begin precharge at the earliest possible moment during the
burst READ or WRITE cycle.
If AP is LOW when the READ or WRITE command is issued, a normal READ or WRITE
burst operation is executed and the bank remains active at the completion of the burst.
If AP is HIGH when the READ or WRITE command is issued, the auto precharge function is engaged. This feature enables the PRECHARGE operation to be partially or completely hidden during burst READ cycles (dependent upon READ or WRITE latency),
thus improving system performance for random data access.
Burst READ with Auto Precharge
If AP (CA0f) is HIGH when a READ command is issued, the READ with auto precharge
function is engaged. The device starts an auto precharge on the rising edge of the clock,
BL/2 or BL/2 - 4 + RU(tRTP/tCK) clock cycles later than the READ with auto precharge
command, whichever is greater. For LPDDR3 auto precharge calculations, see the PRECHARGE and Auto Precharge Clarification table.
Following an auto precharge operation, an ACTIVATE command can be issued to the
same bank if the following two conditions are satisfied simultaneously:
• The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.
• The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Figure 35: LPDDR3 – Burst READ with Auto Precharge
T0
T1
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
CK_c
CK_t
RL
CA[9:0]
Bankm
Col addr a
col addr a
Bankm
Row addr
row addr
≥ tRPpb
tRTP
CMD
READ w/AP
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVATE
NOP
DQS_c
DQS_t
DQ
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A4
DOUT A5
DOUT A6
DOUT A7
Transitioning Data
61
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
PRECHARGE Command
Burst WRITE with Auto Precharge
If AP (CA0f) is HIGH when a WRITE command is issued, the WRITE with auto precharge
function is engaged. The device starts an auto precharge at the clock rising edge tWR
cycles after the completion of the burst WRITE.
Following a WRITE with auto precharge, an ACTIVATE command can be issued to the
same bank if the following two conditions are met:
• The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.
• The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Figure 36: Burst WRITE with Auto Precharge – BL = 8
T0
Tx
Tx + 1
...
Tx + 5
Ty
Ty + 1
Tz
Tz + 1
CK_c
CK_t
WL
CA[9:0]
Bankn
col addr
Bankn Row addr
row addr
Col addr
tWR
CMD
WRITE
NOP
NOP
NOP
NOP
≥ tRPpb
NOP
NOP
ACTIVATE
NOP
DQS_t
DQS_c
DQ
DIN A0
DIN A1
DIN A6
DIN A7
Don’t Care
62
Transitioning Data
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
PRECHARGE Command
Table 46: PRECHARGE and Auto Precharge Clarification
From
Command
READ
READ w/AP
WRITE
WRITE w/AP
To Command
BL/2 + MAX (4,
RU(tRTP/tCK))
-4
PRECHARGE ALL
BL/2 + MAX (4,
RU(tRTP/tCK))
-4
PRECHARGE to same bank as READ w/AP
BL/2 + MAX (4, RU(tRTP/tCK)) - 4
PRECHARGE ALL
BL/2 + MAX(4, RU(tRTP/tCK)) - 4
PRECHARGE to same bank as READ
-4+
Notes
CLK
1
CLK
1, 2
1
1
RU(tRPpb/
1
BL/2 + MAX(4,
tCK)
WRITE or WRITE w/AP (same bank)
Illegal
3
WRITE or WRITE w/AP (different bank)
RL + BL/2 + RU(tDQSCKmax/tCK) - WL + 1
3
READ or READ w/AP (same bank)
Illegal
3
READ or READ w/AP (different bank)
BL/2
3
RU(tWR/tCK)
+1
PRECHARGE to same bank as WRITE
WL + BL/2 +
PRECHARGE ALL
WL + BL/2 + RU(tWR/tCK) + 1
CLK
WL + BL/2 +
RU(tWR/tCK)
RU(tWR/tCK)
CLK
+1
+1+
1
1
PRECHARGE to same bank as WRITE w/AP WL + BL/2 + RU(tWR/tCK) + 1
1
1
RU(tRPpb/tCK)
1
ACTIVATE to same bank as WRITE w/AP
WL + BL/2 +
WRITE or WRITE w/AP (same bank)
Illegal
3
WRITE or WRITE w/AP (different bank)
BL/2
3
READ or READ w/AP (same bank)
Illegal
READ or READ w/AP (different bank)
PRECHARGE
ALL
RU(tRTP/tCK))
Unit
ACTIVATE to same bank as READ w/AP
PRECHARGE ALL
PRECHARGE
Minimum Delay Between Commands
WL + BL/2 +
PRECHARGE to same bank as PRECHARGE 1
PRECHARGE ALL
1
PRECHARGE
1
PRECHARGE ALL
1
Notes:
3
RU(tWTR/tCK)
+1
3
CLK
1
1
CLK
1
1
1. For a given bank, the PRECHARGE period should be counted from the latest PRECHARGE
command, which will be either a one-bank PRECHARGE command or a PRECHARGE ALL
command, issued to that bank. The PRECHARGE period is satisfied after tRP, depending
on the latest PRECHARGE command issued to that bank.
2. Any command issued during the specified minimum delay time is illegal.
3. After a READ with auto precharge command, seamless READ operations to different
banks are supported. After a WRITE with auto precharge command, seamless WRITE operations to different banks are supported. READ with auto precharge and WRITE with
auto precharge commands must not be interrupted or truncated.
63
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
REFRESH Command
REFRESH Command
The REFRESH command is initiated with CS_n LOW, CA0 LOW, CA1 LOW, and CA2
HIGH at the rising edge of the clock. Per-bank REFRESH is initiated with CA3 LOW at
the rising edge of the clock. All-bank REFRESH is initiated with CA3 HIGH at the rising
edge of the clock.
A per-bank REFRESH command (REFpb) performs a per-bank REFRESH operation to
the bank scheduled by the bank counter in the memory device. The bank sequence for
per-bank REFRESH is fixed to be a sequential round-robin: 0-1-2-3-4-5-6-7-0-1-.... The
bank count is synchronized between the controller and the SDRAM by resetting the
bank count to zero. Synchronization can occur upon issuing a RESET command or at
every exit from self refresh.
A bank must be idle before it can be refreshed. The controller must track the bank being
refreshed by the per-bank REFRESH command.
The REFpb command must not be issued to the device until the following conditions
have been met (see the REFRESH Command Scheduling Separation Requirements table):
•
•
•
•
tRFCab
has been satisfied after the prior REFab command
has been satisfied after the prior REFpb command
tRP has been satisfied after the prior PRECHARGE command to that bank
tRRD has been satisfied after the prior ACTIVATE command (if applicable, for example after activating a row in a different bank than the one affected by the REFpb command)
tRFCpb
The target bank is inaccessible during per-bank REFRESH cycle time (tRFCpb); however, other banks within the device are accessible and can be addressed during the cycle.
During the REFpb operation, any of the banks other than the one being refreshed can
be maintained in an active state or accessed by a READ or WRITE command. When the
per-bank REFRESH cycle has completed, the affected bank will be in the idle state.
After issuing REFpb, the following conditions must be met (see the REFRESH Command Scheduling Separation Requirements table):
•
•
•
•
tRFCpb
must be satisfied before issuing a REFab command
must be satisfied before issuing an ACTIVATE command to the same bank
tRRD must be satisfied before issuing an ACTIVATE command to a different bank
tRFCpb must be satisfied before issuing another REFpb command
tRFCpb
An all-bank REFRESH command (REFab) issues a REFRESH command to all banks. All
banks must be idle when REFab is issued (for instance, by issuing a PRECHARGE ALL
command prior to issuing an all-bank REFRESH command). REFab also synchronizes
the bank count between the controller and the SDRAM to zero. The REFab command
must not be issued to the device until the following conditions have been met (see the
REFRESH Command Scheduling Separation Requirements table):
• tRFCab has been satisfied following the prior REFab command
• tRFCpb has been satisfied following the prior REFpb command
• tRP has been satisfied following the prior PRECHARGE commands
When an all-bank REFRESH cycle has completed, all banks will be idle. After issuing REFab:
64
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
REFRESH Command
• tRFCab latency must be satisfied before issuing an ACTIVATE command
• tRFCab latency must be satisfied before issuing a REFab or REFpb command
Table 47: REFRESH Command Scheduling Separation Requirements
Symbol
Minimum
Delay From
tRFCab
REFab
To
Notes
REFab
ACTIVATE command to any bank
REFpb
tRFCpb
REFpb
REFab
ACTIVATE command to same bank as REFpb
REFpb
tRRD
REFpb
ACTIVATE
ACTIVATE command to a different bank than REFpb
REFpb
1
ACTIVATE command to a different bank than the prior ACTIVATE command
Note:
1. A bank must be in the idle state before it is refreshed, so following an ACTIVATE command REFab is prohibited. REFpb is supported only if it affects a bank that is in the idle
state.
In general, an all bank REFRESH command needs to be issued to the device regularly
every tREFI interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided for postponing
and pulling in the refresh command. A maximum of eight REFRESH commands can be
postponed during operation of the device, but at no point in time are more than a total
of eight REFRESH commands allowed to be postponed. In the case where eight REFRESH commands are postponed in a row, the resulting maximum interval between the
surrounding REFRESH commands is limited to 9 × tREFI. A maximum of eight additional REFRESH commands can be issued in advance (pulled in), with each one reducing
the number of regular REFRESH commands required later by one. Note that pulling in
more than eight REFRESH commands in advance does not reduce the number of regular REFRESH commands required later; therefore, the resulting maximum interval between two surrounding REFRESH commands is limited to 9 x tREFI. At any given time, a
maximum of 16 REFRESH commands can be issued within 2 x tREFI.
For per bank refresh, a maximum of 8 × 8 per bank REFRESH commands can be postponed or pulled in for scheduling efficiency. At any given time, a maximum of 2 × 8 × 8
per bank REFRESH commands may be issued within 2 × tREFI.
65
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
REFRESH Command
Figure 37: REFRESH Command Timing
T0
T1
REF
NOP
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
Vaild
Vaild
Vaild
Vaild
Tc0
Tc1
Tc2
Tc3
REF
Vaild
Vaild
Vaild
CK_c
CK_t
CMD
NOP
REF
tRFC
NOP
tRFC
NOP
Vaild
(MIN)
tREFI
(MAX 9 tREF)
DRAM must be idle
DRAM must be idle
1. Only NOP commands are allowed after the REFRESH command is registered until tRFC
(MIN) expires.
2. The time interval between two REFRESH commands may be extended to a maximum of
9 ×tREFI.
Notes:
Figure 38: Postponing REFRESH Commands
tREFI
9
tREFI
t
8 REFRESH commands postponed
Figure 39: Pulling In REFRESH Commands
tREFI
9
tREFI
t
8 REFRESH commands pulled-in
66
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
REFRESH Command
REFRESH Requirements
Minimum REFRESH Commands
LPDDR3 requires a minimum number, R, of REFRESH (REFab) commands within any
rolling refresh window (tREFW = 32ms @ MR4[2:0] = 011 or T C ≤ 85˚C). For actual values
per density and the resulting average refresh interval (tREFI), see the Refresh Requirement Parameters (Per Density) table.
For tREFW and tREFI refresh multipliers at different MR4 settings, see the MR4 Device
Temperature (MA[7:0] = 04h) and the MR4 Op-Code Bit Definitions tables.
When using per-bank REFRESH, a REFab command can be replaced by a full cycle of
eight REFpb commands.
REFRESH Requirements and Self Refresh
Self refresh mode may be entered with a maximum of eight REFRESH commands being
postponed. After exiting self refresh mode with one or more REFRESH commands postponed, additional REFRESH commands may be postponed, but the total number of
postponed refresh commands (before and after the self refresh) must never exceed
eight. During self refresh mode, the number of postponed or pulled-in REFRESH commands does not change.
An internally timed refresh event can be missed when CKE is raised for exit from self
refresh mode. After exiting self refresh, the device requires a minimum of one extra REFRESH command before it is put back into self refresh mode.
67
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
REFRESH Command
Figure 40: All-Bank REFRESH Operation
T0
T1
T2
T3
T4
Tx
Tx + 1
Ty
Ty + 1
CK_c
CK_t
CA[9:0]
CMD
AB
PRECHARGE
NOP
NOP
REFab
NOP
≥ tRFCab
≥ tRPab
NOP
REFab
Any
≥ tRFCab
Figure 41: Per-Bank REFRESH Operation
T0
T1
Tx
Tx + 1
Tx + 2
Ty
Ty + 1
Tz
Tz + 1
CK_c
CK_t
CA[9:0]
CMD
Bank 1
Row A
AB
PRECHARGE
NOP
NOP
≥tRPab
REFpb
REFRESH to bank 0
Notes:
ACTIVATE
REFpb
≥tRFCpb
Row A
≥tRFCpb
REFRESH to bank 1
ACTIVATE command
to bank 1
1. In the beginning of this example, the REFpb bank counter points to bank 0.
2. Operations to banks other than the bank being refreshed are supported during the
tRFCpb period.
68
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
SELF REFRESH Operation
SELF REFRESH Operation
The SELF REFRESH command can be used to retain data in the array, even if the rest of
the system is powered-down. When in the self refresh mode, the device retains data
without external clocking. The device has a built-in timer to accommodate SELF REFRESH operation. The SELF REFRESH command is executed by taking CKE LOW, CS_n
LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock. CKE must be
HIGH during the clock cycle preceding a SELF REFRESH command. CKE must not go
LOW while MRR, MRW, READ, or WRITE operations are in progress.
To ensure that there is enough time to account for internal delay on the CKE signal
path, two NOP commands are required after CKE is driven LOW; this timing period is
defined as tCPDED. CKE LOW will result in deactivation of input receivers after tCPDED
has expired. After the power-down command is registered, CKE must be held LOW to
keep the device in self refresh mode.
Mobile LPDDR3 devices can operate in self refresh mode in both the standard and extended temperature ranges. These devices also manage self refresh power consumption
when the operating temperature changes, resulting in the lowest possible power consumption across the operating temperature range. See the IDD Specification Parameters
and Operating Conditions table for details.
After the device has entered self refresh mode, all external signals other than CKE are
“Don’t Care.” For proper SELF REFRESH operation, power supply pins (VDD1, V DD2,
VDDQ, and V DDCA) must be at valid levels. V DDQ can be turned off during self refresh. If
VDDQ is turned off, V REFDQ must also be turned off. Prior to exiting self refresh, both
VDDQ and V REFDQ must be within their respective minimum/maximum operating ranges (see AC and DC Operating Conditions). V REFDQ can be at any level between 0 and
VDDQ; V REFCA can be at any level between 0 and V DDCA during self refresh.
Before exiting self refresh, V REFDQ and V REFCA must be within specified limits (see the AC
and DC Logic Input Measurement Levels for Single-Ended Signals section). After entering self refresh mode, the device initiates at least one all-bank REFRESH command internally during tCKESR. The clock is internally disabled during SELF REFRESH operation to save power. The device must remain in self refresh mode for at least tCKESR. The
user can change the external clock frequency or halt the external clock one clock after
self refresh entry is registered; however, the clock must be restarted and stable before
the device can exit SELF REFRESH operation.
Exiting self refresh requires a series of commands. First, the clock must be stable prior
to CKE returning HIGH. After the self refresh exit is registered, a minimum delay, at least
equal to the self refresh exit interval (tXSR), must be satisfied before a valid command
can be issued to the device. This provides completion time for any internal refresh in
progress. For proper operation, CKE must remain HIGH throughout tXSR. NOP commands must be registered on each rising clock edge during tXSR. For the description of
ODT operation and specifications during self-refresh entry and exit, see "On Die Termination" section.
Using self refresh mode introduces the possibility that an internally timed refresh event
could be missed when CKE is driven HIGH for exit from self refresh mode. Upon exiting
self refresh, at least one REFRESH command (one all-bank command or eight per-bank
commands) must be issued before issuing a subsequent SELF REFRESH command.
69
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
SELF REFRESH Operation
Figure 42: SELF REFRESH Operation
2 tCK (MIN)
CK
tCPDED
tIHCKE
Input clock frequency can be changed
or clock can be stopped during self refresh.
tIHCKE
CKE
tISCKE
tISCKE
CS_n
tCKESR (MIN)
CMD
Valid Enter
SR
tXSR (MIN)
Exit
SR
NOP NOP
Enter self refresh mode
NOP NOP Valid
Exit self refresh mode
Don’t Care
Notes:
1. Input clock frequency can be changed or stopped during self refresh, provided that
upon exiting self-refresh, a minimum of two cycles of stable clocks are provided, and the
clock frequency is between the minimum and maximum frequencies for the particular
speed grade.
2. The device must be in the all-banks-idle state prior to entering self refresh mode.
3. tXSR begins at the rising edge of the clock after CKE is driven HIGH.
4. A valid command can be issued only after tXSR is satisfied. NOPs must be issued during
tXSR.
Partial-Array Self Refresh (PASR) – Bank Masking
LPDDR3 SDRAMs comprise eight banks. Each bank can be configured independently
whether or not a SELF REFRESH operation will occur in that bank. One 8-bit mode register (accessible via the MRW command) is assigned to program the bank-masking status of each bank up to eight banks. For bank-masking bit assignments, see the MR16
PASR Bank Mask (MA[7:0] = 010h) and MR16 Op-Code Bit Definitions tables.
The mask bit to the bank enables or disables a refresh operation of the entire memory
space within the bank. If a bank is masked using the bank-mask register, a REFRESH
operation to the entire bank is blocked, and bank data retention is not guaranteed in
self refresh mode. To enable a REFRESH operation to a bank, the corresponding bank
mask bit must be programmed as “unmasked.” When a bank mask bit is unmasked, the
array space being refreshed within that bank is determined by the programmed status
of the segment mask bits.
Partial-Array Self Refresh – Segment Masking
Programming segment-mask bits is similar to programming bank-mask bits. Eight segments are used for masking (see the MR17 PASR Segment Mask (MA[7:0] = 011h) and
MR17 PASR Segment Mask Definitions tables). A mode register is used for programming
segment-mask bits up to eight bits.
70
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
SELF REFRESH Operation
When the mask bit to an address range (represented as a segment) is programmed as
“masked,” a REFRESH operation to that segment is blocked. Conversely, when a segment mask bit to an address range is unmasked, refresh to that segment is enabled.
A segment-masking scheme can be used in place of or in combination with a bankmasking scheme. Each segment mask bit setting is applied across all banks. For segment-masking bit assignments, see the MR17 PASR Segment Mask (MA[7:0] = 011h) and
MR17 PASR Segment Mask Definitions tables.
Table 48: Bank- and Segment-Masking Example
Segment Mask (MR17) Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7
Bank Mask (MR16)
0
1
0
0
0
0
0
1
Segment 0
0
–
M
–
–
–
–
–
M
Segment 1
0
–
M
–
–
–
–
–
M
Segment 2
1
M
M
M
M
M
M
M
M
Segment 3
0
–
M
–
–
–
–
–
M
Segment 4
0
–
M
–
–
–
–
–
M
Segment 5
0
–
M
–
–
–
–
–
M
Segment 6
0
–
M
–
–
–
–
–
M
Segment 7
1
M
M
M
M
M
M
M
M
Note:
1. This table provides values for an eight-bank device with REFRESH operations masked to
banks 1 and 7 and to segments 2 and 7.
71
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER READ
MODE REGISTER READ
The MODE REGISTER READ (MRR) command is used to read configuration and status
data from SDRAM mode registers. The MRR command is initiated with CS_n LOW, CA0
LOW, CA1 LOW, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The mode register is selected by CA1f–CA0f and CA9r–CA4r. The mode register contents are available
on the first data beat of DQ[7:0] after RL × tCK + tDQSCK + tDQSQ and following the rising edge of the clock where MRR is issued. Subsequent data beats contain valid but undefined content, except in the case of the DQ calibration function, where subsequent
data beats contain valid content as described in the Data Calibration Pattern Description table. All DQS are toggled for the duration of the mode register READ burst.
The MRR command has a burst length of eight. MRR operation (consisting of the MRR
command and the corresponding data traffic) must not be interrupted. The MRR command period is tMRR.
Figure 43: MRR Timing
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
CK_c
CK_t
RL = 8
CA[9:0]
Register
A
Register
A
Register
B
Register
B
tMRR
CMD
MRR1
NOP2
tMRR
NOP2
NOP2
MRR1
NOP2
NOP2
NOP2
Valid
Valid
Valid
Valid
Valid
Valid
Valid
DQS_c
DQS_t
DQ[7:0]3
DOUTA
DOUTB
DQ[MAX:8]
Transitioning data
Notes:
Undefined
1. MRRs to DQ calibration registers MR32 and MR40 are described in the DQ Calibration
section.
2. Only the NOP command is supported during tMRR.
3. Mode register data is valid only on DQ[7:0] on the first beat. Subsequent beats contain
valid but undefined data. DQ[MAX:8] contain valid but undefined data for the duration
of the MRR burst.
4. Minimum MRR to write latency is RL + RU(tDQSCK (MAX)/tCK) + 8/2 + 1 - WL clock cycles.
5. Minimum MRR to MRW latency is RL + RU(tDQSCK (MAX)/tCK) + 8/2 + 1 clock cycles.
6. In this example, RL = 8 for illustration purposes only.
After a prior READ command, the MRR command must not be issued before BL/2 clock
cycles have completed. Following a WRITE command, the MRR command must not be
issued before WL + 1 + BL/2 + RU( tWTR/tCK) clock cycles have completed, as READ
bursts and WRITE bursts must not be truncated my MRR.
72
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER READ
Figure 44: READ to MRR Timing
T0
T1
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
CK_c
CK_t
RL
CA[9:0]
Bankm Col addr
col addr a
a
Register
B
Register
B
tMRR
CMD
READ
NOP1
NOP1
NOP1
NOP1
MRR
NOP1
NOP1
Valid
DQS_c
DQS_t
DQ[7:0]
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DQ[MAX:8]
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT B
Transitioning data
Notes:
Undefined
1. The minimum number of clock cycles from the burst READ command to the MRR command is BL/2.
2. Only the NOP command is supported during tMRR.
Figure 45: Burst WRITE Followed by MRR
T0
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Ty
Ty+1
Ty+2
CK_c
CK_t
WL
CA[9:0]
Bankn
col addr a
RL
Col
addr a
Register
B
Register
B
t WTR
CMD
Valid
WRITE
tMRR
MRR1
NOP2
NOP2
DQS_c
DQS_t
DQ
DIN A0
DIN A1
DIN A2
DIN A3
DIN A4
DIN A5
DIN A6
DIN A7
Transitioning data
Notes:
1. The minimum number of clock cycles from the burst WRITE command to the MRR command is [WL + 1 + BL/2 + RU(tWTR/tCK)].
2. Only the NOP command is supported during tMRR.
MRR Following Idle Power-Down State
Following the idle power-down state, an additional time, tMRRI, is required prior to issuing the MODE REGISTER READ (MRR) command. This additional time (equivalent to
tRCD) is required in order to maximize power-down current savings by allowing more
power-up time for the MRR data path after exit from the idle power-down state.
73
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER READ
Figure 46: MRR After Idle Power-Down Exit
CK
tIHCKE
tCKE (MIN)
CKE
tISCKE
CS_n
tXP(MIN)
CMD
Exit
PD
tMRRI
NOP
NOP
Valid1
Valid1 Valid1
tMRR
MRR
Valid
Valid
Don’t Care
Exit power-down mode
1. Any valid command except MRR.
Note:
Temperature Sensor
LPDDR3 devices feature a temperature sensor whose status can be read from MR4. This
sensor can be used to determine an appropriate refresh rate, determine whether AC
timing derating is required in the extended temperature range, and/or monitor the operating temperature. Either the temperature sensor or the device operating temperature
can be used to determine whether operating temperature requirements are being met
(see the Operating Temperature Range table).
Temperature sensor data can be read from MR4 using the mode register read protocol.
Upon exiting self-refresh or power-down, the device temperature status bits will be no
older than tTSI.
When using the temperature sensor, the actual device case temperature may be higher
than the operating temperature specification that applies for the standard or extended
temperature ranges (see the Operating Temperature Range table). For example, T CASE
could be above 85°C when MR4[2:0] equals 011b.
To ensure proper operation using the temperature sensor, applications must accommodate the following table.
Table 49: Temperature Sensor Definitions and Operating Conditions
Parameter
Description
Symbol
Min/Max
Value
Unit
System temperature
gradient
Maximum temperature gradient experienced by the memory device at the temperature of interest over a range of 2°C
TempGradient
MAX
System-dependent
°C/s
MR4 READ interval
Time period between MR4 READs from the
system
ReadInterval
MAX
System-dependent
ms
Temperature sensor
interval
Maximum delay between internal updates
of MR4
tTSI
MAX
32
ms
System response
delay
Maximum response time from an MR4 READ
to the system response
SysRespDelay
MAX
System-dependent
ms
74
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER READ
Table 49: Temperature Sensor Definitions and Operating Conditions (Continued)
Parameter
Description
Device temperature
margin
Margin above maximum temperature to
support controller response
Symbol
Min/Max
Value
Unit
TempMargin
MAX
2
°C
These devices accommodate the temperature margin between the point at which the
device temperature enters the extended temperature range and the point at which the
controller reconfigures the system accordingly. To determine the required MR4 polling
frequency, the system must use the maximum TempGradient and the maximum response time of the system according to the following equation:
TempGradient × (ReadInterval + tTSI + SysRespDelay) ≤ 2°C
For example, if TempGradient is 10˚C/s, and the SysRespDelay is 1ms:
10°C × (ReadInterval + 32ms + 1ms) ≤ 2°C
s
In this case, ReadInterval must not exceed 167ms.
Figure 47: Temperature Sensor Timing
Temp
< (tTSI + ReadInterval + SysRespDelay)
Device
Temp
Margin
ient
Grad
Temp
2°C
MR4
Trip Level
tTSI
MR4 = 0x03
MR4 = 0x86
MR4 = 0x86
MR4 = 0x86
MR4 = 0x06
Time
Temperature sensor update
ReadInterval
Host MR4 READ
MRR MR4 = 0x03
SysRespDelay
MRR MR4 = 0x86
DQ Calibration
LPDDR3 devices feature a DQ calibration function that outputs one of two predefined
system timing calibration patterns. An MRR operation to MR32 (pattern A) or and MRR
75
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER READ
operation to MR40 (pattern B) will return the specified pattern on DQ0 and DQ8—for
x32 devices, on DQ0, DQ8, DQ16 and DQ24.
For x16 devices, DQ[7:1] and DQ[15:9] drive the same information as DQ0 during the
MRR burst. For x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] drive the
same information as DQ0 during the MRR burst. MRR DQ calibration commands can
occur only in the idle state.
Figure 48: MR32 and MR40 DQ Calibration Timing
T0
T1
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK_c
CK_t
RL = 6
CA[9:0] Reg 32 Reg 32
Reg 40 Reg 40
tMRR
CMD
MRR
tMRR
=4
NOP1
NOP1
NOP1
=4
NOP1
NOP
MRR
NOP1
NOP1
DQS_c
DQS_t
Pattern A
Pattern B
DQ0
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
DQ[7:1]
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
x16
DQ8
1
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
DQ[15:9]
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
DQ16
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
DQ[23:17]
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
DQ24
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
DQ[31:25]
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
x32
Transitioning data
Optionally driven the same as DQ0 or 0b
Table 50: Data Calibration Pattern Description
Pattern
MR#
Bit
Time
0
Bit
Time
1
Bit
Time
2
Bit
Time
3
Bit
Time
4
Bit
Time
5
Bit
Time
6
Bit
Time
7
Pattern
A
MR32
1
0
1
0
1
0
1
0
Reads to MR32 return DQ calibration pattern A
Pattern
B
MR40
0
0
1
1
0
0
1
1
Reads to MR40 return DQ calibration pattern B
76
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
MODE REGISTER WRITE
The MRW command is used to write configuration data to the mode registers. The
MRW command is initiated with CS_n LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3
LOW at the rising edge of the clock. The mode register is selected by CA1f–CA0f, CA9r–
CA4r. The data to be written to the mode register is contained in CA9f–CA2f. The MRW
command period is defined by tMRW. Mode register writes to read-only registers have
no impact on the functionality of the device.
Figure 49: MODE REGISTER WRITE Timing
T0
T1
T2
Tx
Tx + 1
Tx + 2
Ty 1
Ty + 1
Ty + 2
CK_c
CK_t
tMRW
CA[9:0]
CMD
tMRW
MR addr MR data
MRW
MR addr MR data
NOP2
Notes:
NOP2
NOP2
MRW
NOP2
Valid
1. At time Ty, the device is in the idle state.
2. Only the NOP command is supported during tMRW.
MRW can be issued only when all banks are in the idle precharge state. One method of
ensuring that the banks are in this state is to issue a PRECHARGE ALL command.
MRW RESET Command
The MRW RESET command brings the device to the device auto initialization (resetting) state in the power-on initialization sequence (see the Voltage Ramp and Device Initialization section). The MRW RESET command can be issued from the idle state. This
command resets all mode registers to their default values. After MRW RESET, boot timings must be observed until the device initialization sequence is complete, and the device is in the idle state. Array data is undefined after the MRW RESET command.
If the initialization is to be performed at-speed (greater than the recommended boot
clock frequency), then CA training may be necessary to ensure setup and hold timings.
As the MRW RESET command is required prior to CA Training, an alternate MRW RESET command with an op-code of 0xFCh should be used. This encoding ensures that
no transitions occur on the CA bus. Prior to CA training, it is recommended to hold the
CA bus stable for one cycle prior to, and one cycle after, the issuance of the MRW RESET
command to ensure setup and hold timings on the CA bus.
For MRW RESET timing, see the figure below and see the Voltage Ramp and Initialization Sequence figure.
77
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
Table 51: Truth Table for MRR and MRW
Current State
Command
Intermediate State
Next State
MRR
Reading mode register, all banks idle
All banks idle
MRW
Writing mode register, all banks idle
All banks idle
MRW (RESET)
Resetting, device auto initialization
All banks idle
All banks idle
Bank(s) active
MRR
Reading mode register, bank(s) active
Bank(s) active
MRW
Not allowed
Not allowed
MRW (RESET)
Not allowed
Not allowed
Figure 50: MODE REGISTER WRITE Timing for MRW RESET
Td
Td’
Te
CK_t
CK_c
CKE
CA[9:0]
FCh
CMD
FCh
FCh
Reg
B
FCh
MRW
(Optional)
MRW
Reg
B
MRR
tINIT3
tINIT4
CS_n
Optional CA/CMD
CMD not allowed
Note:
Optional CS_n
1. Optional MRW RESET command and optional CS_n assertion are allowed. When the optional MRW RESET command is used, tINIT4 starts at Td'.
MRW ZQ Calibration Commands
The MRW command is used to initiate a ZQ calibration command that calibrates output
driver impedance across process, temperature, and voltage. LPDDR3 devices support
ZQ calibration.
There are four ZQ calibration commands and related timings: tZQINIT, tZQRESET,
tZQCL, and tZQCS. tZQINIT is used for initialization calibration; tZQRESET is used for
resetting ZQ to the default output impedance; tZQCL is used for long calibration(s); and
78
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
tZQCS
is used for short calibration(s). See the MR10 Calibration (MA[7:0] = 0Ah) table
for ZQ calibration command code definitions.
The initialization ZQ calibration (ZQINIT) must be performed for LPDDR3. ZQINIT provides an output impedance accuracy of ±15%. After initialization, the ZQ calibration
long (ZQCL) can be used to recalibrate the system to an output impedance accuracy of
±15%. A ZQ calibration short (ZQCS) can be used periodically to compensate for temperature and voltage drift in the system.
ZQRESET resets the output impedance calibration to a default accuracy of ±30% across
process, voltage, and temperature. This command is used to ensure output impedance
accuracy to ±30% when ZQCS and ZQCL commands are not used.
One ZQCS command can effectively correct at least 1.5% (ZQ correction) of output impedance errors within tZQCS for all speed bins, assuming the maximum sensitivities
specified in the Output Driver Sensitivity Definition and Output Driver Temperature
and Voltage Sensitivity tables are met. The appropriate interval between ZQCS commands can be determined using these tables and system-specific parameters.
LPDDR3 devices are subject to temperature drift rate (Tdriftrate) and voltage drift rate
(Vdriftrate) in various applications. To accommodate drift rates and calculate the necessary interval between ZQCS commands, apply the following formula:
ZQcorrection
(Tsens × Tdriftrate ) + (Vsens × Vdriftrate )
Where T sens = MAX (dRONdT) and V sens = MAX (dRONdV) define temperature and voltage sensitivities.
For example, if T sens = 0.75%/˚C, V sens = 0.20%/mV, T driftrate = 1˚C/sec, and V driftrate =
15 mV/sec, then the interval between ZQCS commands is calculated as:
1.5
= 0.4s
(0.75 × 1) + (0.20 × 15)
A ZQ calibration command can be issued only when the device is in the idle state with
all banks precharged.
No other activities can be performed on the data bus during calibration periods
(tZQINIT, tZQCL, or tZQCS). The quiet time on the data bus helps to accurately calibrate
output impedance. There is no required quiet time after the ZQRESET command. If
multiple devices share a single ZQ resistor, only one device can be calibrating at any given time. After calibration is complete, the ZQ ball circuitry is disabled to reduce power
consumption.
In systems sharing a ZQ resistor among devices, the controller must prevent tZQINIT,
and tZQCL overlap between the devices. ZQRESET overlap is acceptable. If the
ZQ resistor is absent from the system, ZQ must be connected to V DDCA. In this situation,
the device must ignore ZQ calibration commands, and the device will use the default
calibration settings.
tZQCS,
79
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
Figure 51: ZQ Timings
T0
T1
T2
T3
T4
T5
Tx
Tx + 1
Tx + 2
CK_c
CK_t
CA[9:0]
MR addr MR data
ZQINIT
tZQINIT
CMD
MRW
NOP
NOP
NOP
NOP
NOP
Valid
NOP
NOP
Valid
NOP
NOP
Valid
NOP
NOP
Valid
ZQCS
tZQCS
CMD
MRW
NOP
NOP
NOP
ZQCL
tZQCL
CMD
MRW
NOP
NOP
NOP
ZQRESET
tZQRESET
CMD
MRW
NOP
Notes:
NOP
NOP
1. Only the NOP command is supported during ZQ calibration.
2. CKE must be registered HIGH continuously during the calibration period.
3. All devices connected to the DQ bus should be High-Z during the calibration process.
80
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
ZQ External Resistor Value, Tolerance, and Capacitive Loading
To use the ZQ calibration function, a 240Ω (±1% tolerance) external resistor must be
connected between the ZQ pin and ground. A single resistor can be used for each device, or one resistor can be shared among multiple devices if the ZQ calibration timings
for each device do not overlap. The total capacitive loading on the ZQ pin must be limited (see the Input/Output Capacitance table).
MRW – CA Training Mode
Because CA inputs operate as double data rate, it may be difficult for the memory controller to satisfy CA input setup/hold timings at higher frequency. A CA training mechanism is provided.
CA Training Sequence
1. CA training mode entry: MODE REGISTER WRITE command to MR41
2. CA training session: Calibrate CA0, CA1, CA2, CA3, CA5, CA6, CA7 and CA8 (see
the CA Training Mode Enable [MR41] table)
3. CA to DQ mapping change: MODE REGISTER WRITE command to MR48
4. Additional CA training session: Calibrate remaining CA pins (CA4 and CA9) (see
the CA Training Mode Enable [MR48] table)
5. CA training mode exit: MODE REGISTER WRITE command to MR42
Figure 52: CA Training Timing
CK_t
CK_c
MRW#41, #48 MRW#41, #48 MRW#41, #48
(optional)4 (CA cal.Entry) (optional)4
MRW#42
(optional)4
CAx CAx CAx CAx
R
R#
R
R#
CA[9:0]
MRW#42
(CA cal.Exit)
MRW#42
(optional)4
CAy CAy CAx CAx
R
R#
R
R#
CS_n
CKE
tCACKEL
tCAMRD
tCAENT
tCACD
tADR
tADR
tCACKEH
tCAEXT
tMRZ
Even
DQ
CAx
R
CAy
R
Odd
DQ
CAx
R#
CAy
R#
Optional CA
Notes:
Optional CS_n
Don’t Care
1. Unused DQ must be valid HIGH or LOW during data output period. Unused DQ may
transition at the same time as the active DQ. DQS must remain static and not transition.
2. CA to DQ mapping change via MR 48 omitted here for clarity of the timing diagram.
Both MR41 and MR48 training sequences must be completed before exiting the training
mode (MR42). To enable a CA to DQ mapping change, CKE must be driven HIGH prior to
issuance of the MRW 48 command. (See the steps in the CA Training Sequence section
for details.)
3. Because data-out control is asynchronous and will be an analog delay from when all the
CA data is available, tADR and tMRZ are defined from the falling edge of CK.
81
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
4. It is recommended to hold the CA bus stable for one cycle prior to and one cycle after
the issuance of the MRW CA TRAINING ENTRY command to ensure setup and hold timings on the CA bus.
5. Optional MRW 41, 48, 42 commands and the CA CALIBRATION command are allowed.
To complement these optional commands, optional CS_n assertions are also allowed. All
timing must comprehend these optional CS_n assertions: a) tADR starts at the falling
clock edge after the last registered CS_n assertion; b) tCACD, tCACKEL, and tCAMRD start
with the rising clock edge of the last CS_n assertion; c) tCAENT and tCAEXT need to be
met by the first CS_n assertion; and d) tMRZ will be met after the falling clock edge following the first CS_n assertion with exit (MRW42) command.
6. Clock phase may be adjusted in CA training mode while CS_n is HIGH and CKE is LOW,
resulting in an irregular clock with shorter/longer periods and pulse widths.
The device may not properly recognize a MODE REGISTER WRITE command at normal
operation frequency before CA training is finished. Special encodings are provided for
CA training mode enable/disable.
MR41 and MR42 encodings are selected so that rising-edge and falling-edge values are
the same. The device will recognize MR41 and MR42 at normal operation frequency
even before CA timing adjustments have been made. Calibration data will be output
through DQ pins. CA to DQ mapping is described in the CA to DQ mapping (CA training
mode enabled with MR41) table.
After timing calibration with MR41 is finished, issue MRW to MR48 and calibrate the remaining CA pins (CA4 and CA9) using (DQ0/DQ1and DQ8/DQ9) as calibration data
output pins (see the CA to DQ mapping (CA training mode enabled with MR48) table).
Table 52: CA Training Mode Enable (MR41 (29H, 0010 1001b), OP = A4H (1010 0100b))
Clock Edge
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CK rising edge
L
L
L
L
H
L
L
H
L
H
CK falling edge
L
L
L
L
H
L
L
H
L
H
Table 53: CA Training Mode Disable (MR42 (2AH, 0010 1010b), OP = A8H(1010 1000b))
Clock Edge
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CK rising edge
L
L
L
L
L
H
L
H
L
H
CK falling edge
L
L
L
L
L
H
L
H
L
H
Table 54: CA to DQ Mapping (CA Training Mode Enabled with MR41)
Clock Edge
CA0
CA1
CA2
CA3
CA5
CA6
CA7
CA8
CK rising edge
DQ0
DQ2
DQ4
DQ6
DQ8
DQ10
DQ12
DQ14
CK falling edge
DQ1
DQ3
DQ5
DQ7
DQ9
DQ11
DQ13
DQ15
Note:
1. Other DQs must have valid output (either HIGH or LOW).
82
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
Table 55: CA Training Mode Enable (MR48 (30H, 0011 0000b), OP = C0H (1100 0000b))
Clock Edge
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CK rising edge
L
L
L
L
L
L
L
L
H
H
CK falling edge
L
L
L
L
L
L
L
L
H
H
Table 56: CA to DQ Mapping (CA Training Mode Enabled with MR48)
Clock Edge
CA4
CA9
CK rising edge
DQ0
DQ8
CK falling edge
DQ1
DQ9
Note:
1. Other DQs must have valid output (either HIGH or LOW).
MRW - Write Leveling Mode
To improve signal integrity performance, the device provides a write-leveling feature to
compensate for timing skew, which affects timing parameters such as tDQSS, tDSS, and
tDSH.
The memory controller uses the write-leveling feature to receive feedback from the device, enabling it to adjust the clock-to-data strobe signal relationship for each DQS signal pair. The memory controller performing the leveling must have an adjustable delay
setting on the DQS signal pair to align the rising edge of DQS_t signals with that of the
clock signal at the DRAM pin. The device asynchronously feeds back CLK, sampled with
the rising edge of DQS_t signals. The controller repeatedly delays DQS_t signals until a
transition from 0 to 1 is detected. The DQS_t signal delay established through this exercise ensures the tDQSS specification can be met.
All data bits carry the leveling feedback to the controller (DQ[15:0] for x16 configuration, DQ[31:0] for x32 configuration). All DQS_t signals must be leveled independently.
The device enters write-leveling mode when mode register MR2[7] is set HIGH. When
entering write-leveling mode, the state of the DQ pins is undefined. During write-leveling mode, only NOP commands are allowed, or a MRW command to exit the write-leveling operation. Upon completion of the write-leveling operation, the device exits from
write-leveling mode when MR2[7] is reset LOW.
The controller drives DQS_t LOW and DQS_c HIGH after a delay of tWLDQSEN. After
time tWLMRD, the controller provides DQS_t signal input, which is used by the DRAM
to sample the clock signal driven from the controller. The delay time tWLMRD (MAX) is
controller-dependent. The DRAM samples the clock input with the rising edge of DQS_t
and provides asynchronous feedback on all the DQ bits after time tWLO. The controller
samples this information and either increments or decrements the DQS_t and/or
DQS_c delay settings and launches the next DQS_t/DQS_c pulse. The sample time and
trigger time are controller-dependent. After the following DQS_t/DQS_c transition is
sampled, the controller locks the strobe delay settings, and write leveling is achieved for
the device.
83
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
Figure 53: Write-Leveling Timing
tWLS
tWLH
tWLS
tWLH
CK_t
CK_c
CAs
CMD
CA
CA
MRW
CA
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CA
MRW
NOP
NOP
tWLDQSEN
DQS_t
DQS_c
DQ
tWLMRD
tWLO
tDQSL
tWLO
tDQSH
84
tMRD
NOP
Valid
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
On-Die Termination (ODT)
On-Die Termination (ODT)
On-die termination (ODT) is a feature that enables the device to enable/disable and
turn on/off termination resistance for each DQ, DQS, and DM signal via the ODT control pin. ODT is designed to improve signal integrity of the memory channel by enabling
the DRAM controller to independently turn on/off the internal termination resistance
for any or all DRAM devices. The ODT pin directly controls ODT operation and is not
sampled by the clock.
ODT is turned off and not supported in self refresh and deep power-down modes. The
device will also disable termination during READ operations. ODT operation can be enabled optionally during power-down mode via a mode register. Note that if ODT is enabled during power-down mode, V DDQ may not be turned off during power down. The
DRAM will also disable termination during READ operations.
A simple functional representation of the ODT feature is shown below.
Figure 54: Functional Representation of On-Die Termination
ODT
To other
circuitry
such as
RCV,
...
VDDQ
RTT
Switch
DQ, DQS, DM
The switch is enabled by the internal ODT control logic, which uses the external ODT
pin and other control information. The value of R TT (ODT termination resistance value)
is determined by the settings of several mode register bits. The ODT pin will be ignored
if MR11 is programmed to disable ODT in self refresh, in deep power-down, in CKE
power-down (mode register option), and during READ operations.
ODT Mode Register
ODT mode is enabled if MR11[1:0] are non-zero. In this case, the value of RTT is determined by the settings of those bits. ODT mode is disabled if MR11[1:0] are zero.
MR11[2] determines whether ODT will operate during power-down mode if enabled
through MR11[1:0].
Asychronous ODT
When enabled, the ODT feature is controlled asynchronously based on the status of the
ODT pin. ODT is off under any of the following conditions:
•
•
•
•
•
ODT is disabled through MR11[1:0]
Device is performing a READ operation (READ or MRR)
Device is in power-down mode and MR11[2] is zero
Device is in self refresh or deep power-down mode
Device is in CA training mode
In asynchronous ODT mode, the following timing parameters apply when ODT operation is controlled by the ODT pin tODToff, tODTon.
85
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
On-Die Termination (ODT)
Minimum RTT turn-on time (tODTon [MIN]) is the point in time when the device termination circuit leaves High-Z state and ODT resistance begins to turn on. Maximum RTT
turn-on time (tODTon,max) is the point in time when ODT resistance is fully on. tODTon (MIN) and tODTon (MAX) are measured from ODT pin HIGH.
Minimum RTT turn-off time (tODToff [MIN]) is the point in time when the device termination circuit starts to turn off the ODT resistance. Maximum ODT turn off time (tODToff [MAX]) is the point in time when the on-die termination has reached High-Z. tODToff,min and tODToff (MAX) are measured from ODT pin LOW.
ODT During READ Operations (READ or MRR)
During READ operations, the device will disable termination and disable ODT control
through the ODT pin. After READ operations are completed, ODT control is resumed
through the ODT pin (if ODT mode is enabled).
ODT During Power-Down
When MR11[2] is zero, termination control through the ODT pin will be disabled when
the DRAM enters power-down. After a power-down entry is registered, termination will
be disabled within a time window specified by tODTd (MIN) (MAX). ODT pin control is
resumed when power-down is exited (if ODT mode is enabled). Between the POWERDOWN EXIT command and until tXP is satisfied, termination will transition from disabled to control by the ODT pin. When tXP is satisfied, the ODT pin is used to control
termination.
Minimum RTT disable time (tODTd [MIN]) is the point in time when the device termination circuit is no longer controlled by the ODT pin. Maximum ODT disable time (tODTd
[MAX]) is the point in time when ODT will be in High-Z.
When MR11[2] is enabled and MR11[1:0] are non-zero, ODT operation is supported
during CKE power-down with ODT control through the ODT pin.
ODT During Self Refresh
The device disables the ODT function during self refresh. After a SELF REFRESH command is registered, termination will be disabled within a time window specified by
tODTd (MIN) (MAX). During self refresh exit, ODT control through the ODT pin is resumed (if ODT mode is enabled). Between the SELF REFRESH EXIT command and until
tXSR is satisfied, termination will transition from disabled to control by the ODT pin.
When tXSR is satisfied, the ODT pin is used to control termination.
ODT During Deep Power-Down
The device disables the ODT function during deep power-down. After a DEEP POWERDOWN command is registered, termination will be disabled within a time window
specified by tODTd (MIN) (MAX).
ODT During CA Training and Write Leveling
During CA training mode, the device will disable ODT and ignore the state of the ODT
control pin. For ODT operation during write leveling mode, refer to the DRAM Termination Function in Write-Leveling Mode table for termination activation and deactivation
for DQ and DQS_t/DQS_c. If ODT is enabled, the ODT pin must be HIGH in write leveling mode.
86
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
On-Die Termination (ODT)
Table 57: DRAM Termination Function in Write-Leveling Mode
ODT Pin
DQS Termination
DQ Termination
De-asserted
OFF
OFF
Asserted
ON
OFF
Table 58: ODT States Truth Table
Write
Read/DQ
Calibration
ZQ
Calibration
CA
Training
Write
Leveling
DQ
termination
Enabled
Disabled
Disabled
Disabled
Disabled
DQS
termination
Enabled
Disabled
Disabled
Disabled
Enabled
Figure 55: Asynchronous ODT Timing – RL = 12
T0
T1
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CK_t,
CK_c
Col add
CA[9:0]
Bank n
Col add
CMD
READ
RL = 12
DQS_t,
DQS_c
DO
0
DQ
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
tDQSCK
ODT
DRAM_RTT
ODTon
ODToff
tODToff
tODTon
(MIN)
tODToff
(MIN)
tODTon
(MIN)
(MAX)
Don’t Care
87
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
On-Die Termination (ODT)
Figure 56: Automatic ODT Timing During READ Operation – RL = m
T0
T1
Tm-3
Tm-2
Tm-1
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
Tm+6
Tm+7
Tm+8
Tm+9
CK_t,
CK_c
Col add
CA[9:0]
Bank n
Col add
CMD
READ
RL = m
tHZ(DQS)
BL/2
DQS_t,
DQS_c
DO
0
DQ
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
tDQSCK
ODT
ODTon
DRAM_RTT
ODToff
tAODToff
ODTon
tAODTon
Don’t Care
Notes:
1. The automatic RTT turn-off delay, tAODToff, is referenced from the rising edge of RL - 2
clock at Tm-2.
2. The automatic RTT turn-on delay, tAODTon, is referenced from the rising edge of RL +
BL/2 clock at Tm+4.
Figure 57: ODT Timing During Power-Down, Self Refresh, Deep Power-Down Entry/Exit
T0
T1
T2
T3
Tm-1
Tm-2
Tm
Tm+1
Tm+2
Tn
CK_t,
CK_c
CKE
ODT
DRAM_RTT
ODTon
ODToff
tODTd
ODTon
tODTe
Don’t Care
Note:
1. Upon exiting of deep power-down mode, a complete power-up initialization sequence
is required.
88
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Down
Power-Down
Power-down is entered synchronously when CKE is registered LOW and CS_n is HIGH
at the rising edge of clock. A NOP command must be driven in the clock cycle following
the POWER-DOWN command. CKE must not go LOW while MRR, MRW, READ, or
WRITE operations are in progress. CKE can go LOW while any other operations, such as
ROW ACTIVATION, PRECHARGE, AUTO PRECHARGE, or REFRESH are in progress, but
the power-down IDD specification is not applied until such operations are complete.
Entering power-down deactivates the input and output buffers, excluding CKE. To ensure enough time to account for internal delay on the CKE signal path, two NOP commands are required after CKE is driven LOW. this timing period is defined as tCPDED.
CKE LOW results in deactivation of input receivers after tCPDED has expired. In powerdown mode, CKE must be held LOW; all other input signals are “Don’t Care.” CKE LOW
must be maintained until tCKE is satisfied, and V REFCA must be maintained at a valid
level during power-down.
VDDQ can be turned off during power-down. If V DDQ is turned off, V REFDQ must also be
turned off. Prior to exiting power-down, both V DDQ and V REFDQ must be within their respective minimum/maximum operating ranges (see the AC and DC Operating Conditions section).
No refresh operations are performed in power-down mode. The maximum duration in
power-down mode is only limited by the refresh requirements outlined in the REFRESH
Command section.
The power-down state is exited when CKE is registered HIGH. The controller must drive
CS_n HIGH in conjunction with CKE HIGH when exiting the power-down state. CKE
HIGH must be maintained until tCKE is satisfied. A valid, executable command can be
applied with power-down exit latency tXP after CKE goes HIGH. Power-down exit latency is defined in the AC Timing table.
If power-down occurs when all banks are idle, this mode is referred to as idle powerdown; if power-down occurs when a row is active in any bank, this mode is referred to
as active power-down. For the description of ODT operation and specifications during
power-down entry and exit, see the On-Die Termination section.
89
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Down
Figure 58: Power-Down Entry and Exit Timing
2 tCK (MIN)
CK
tCPDED
Input clock frequency can be changed
1
or the input clock can be stopped during power-down.
tIHCKE
tIHCKE
tCKE
(MIN)
CKE
tISCKE
tISCKE
CS_n
tCKE
tXP
(MIN)
Exit
PD
CMD Valid Enter
NOP NOP
PD
Enter power-down mode
(MIN)
NOP NOP Valid
Exit power-down mode
Don’t Care
Note:
1. Input clock frequency can be changed or the input clock stopped during power-down,
provided that the clock frequency is between the minimum and maximum specified frequencies for the speed grade in use and that prior to power-down exit, a minimum of
two stable clocks complete.
Figure 59: CKE Intensive Environment
CK_c
CK_t
tCKE
tCKE
CKE
90
tCKE
tCKE
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Down
Figure 60: REFRESH to REFRESH Timing in CKE Intensive Environments
CK_c
CK_t
tCKE
tCKE
tCKE
tCKE
CKE
tXP
tXP
tREFI
CMD
REFRESH
Note:
REFRESH
1. The pattern shown can repeat over an extended period of time. With this pattern, all
AC and DC timing and voltage specifications with temperature and voltage drift are ensured.
Figure 61: READ to Power-Down Entry
T0
T1
T2
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
Tx + 6
Tx + 7
Tx + 8
Tx + 9
CK_c
CK_t
RL
tISCKE
CKE1, 2
CMD
READ
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
DQ
DQS_c
DQS_t
Notes:
1. CKE must be held HIGH until the end of the burst operation.
2. CKE can be registered LOW at {RL + RU[tDQSCK(MAX)/tCK] + BL/2 + 1} clock cycles after
the clock on which the READ command is registered.
91
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Down
Figure 62: READ with Auto Precharge to Power-Down Entry
T0
T1
T2
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
Tx + 6
Tx + 7
Tx + 8
Tx + 9
CK_c
CK_t
tISCKE
BL/23
RL
CKE1, 2
CMD
PRE4
READ w/AP
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
DQ
DQS_c
DQS_t
Notes:
1. CKE must be held HIGH until the end of the burst operation.
2. CKE can be registered LOW at [RL + RU(tDQSCK/tCK) + BL/2 + 1] clock cycles after the
clock on which the READ command is registered.
3. BL/2 with tRTP = 7.5ns and tRAS (MIN) is satisfied.
4. Start internal PRECHARGE.
Figure 63: WRITE to Power-Down Entry
T0
T1
Tm
Tm + 1
Tm + 2
Tm + 3
Tm + 4
Tm + 5
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
CK_c
CK_t
WL
tISCKE
BL/2
CKE1
tWR
CMD
WRITE
DIN
DQ
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DQS_c
DQS_t
Note:
1. CKE can be registered LOW at [WL + 1 + BL/2 + RU(tWR/tCK)] clock cycles after the clock
on which the WRITE command is registered.
92
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Down
Figure 64: WRITE with Auto Precharge to Power-Down Entry
T0
T1
Tm
Tm + 1
Tm + 2
Tm + 3
Tm + 4
Tm + 5
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
CK_c
CK_t
WL
tISCKE
BL/2
CKE1
tWR
CMD
PRE2
WRITE w/AP
DQ
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DQS_c
DQS_t
Notes:
1. CKE can be registered LOW at [WL + 1 + BL/2 + RU(tWR/tCK) + 1] clock cycles after the
WRITE command is registered.
2. Start internal PRECHARGE.
Figure 65: REFRESH Command to Power-Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_c
CK_t
tISCKE
CKE1
tIHCKE
CMD
REFRESH
Note:
1. CKE can go LOW tIHCKE after the clock on which the REFRESH command is registered.
93
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Down
Figure 66: ACTIVATE Command to Power-Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_c
CK_t
tISCKE
CKE1
tIHCKE
CMD
ACTIVATE
Note:
1. CKE can go LOW at tIHCKE after the clock on which the ACTIVATE command is registered.
Figure 67: PRECHARGE Command to Power-Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_c
CK_t
tISCKE
CKE1
tIHCKE
CMD
PRE
Note:
1. CKE can go LOW tIHCKE after the clock on which the PRECHARGE command is registered.
94
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Deep Power-Down
Figure 68: MRR Power-Down Entry
CK_c
T0
T1
T2
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
CK_t
Tx + 6
Tx + 7
Tx + 8
Tx + 9
tISCKE
RL
CKE1
CMD
MRR
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
DQ
DQS_c
DQS_t
Note:
1. CKE can be registered LOW at [RL + RU(tDQSCK/tCK)+ BL/2 + 1] clock cycles after the
clock on which the MRR command is registered.
Figure 69: MRW Command to Power-Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_c
CK_t
tISCKE
CKE1
tMRW
CMD
MRW
Note:
1. CKE can be registered LOW tMRW after the clock on which the MRW command is registered.
Deep Power-Down
Deep power-down (DPD) is entered when CKE is registered LOW with CS_n LOW, CA0
HIGH, CA1 HIGH, and CA2 LOW at the rising edge of the clock. All banks must be in the
idle state with no activity on the data bus prior to entering DPD mode. During DPD,
CKE must be held LOW. The contents of the device will be lost upon entering DPD
mode.
In DPD mode, all input buffers except CKE, all output buffers, and the power supply to
internal circuitry are disabled within the device. To ensure that there is enough time to
account for internal delay on the CKE signal path, two NOP commands are required after CKE is driven LOW; this timing period is defined as tCPDED. CKE LOW will result in
deactivation of command and address receivers after tCPDED has expired. V REFDQ can
be at any level between 0 and V DDQ, and V REFCA can be at any level between 0 and V DDCA
during DPD. All power supplies, including V REF, must be within the specified limits prior to exiting DPD (see AC and DC Operating Conditions).
95
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Input Clock Frequency Changes and Stop Events
DPD mode is exited when CKE is registered HIGH while meeting tISCKE, and the clock
must be stable. The device must be fully reinitialized using the power-up initialization
sequence. For a description of ODT operation and specifications during DPD entry and
exit, see the ODT During Deep Power-Down section.
Figure 70: Deep Power-Down Entry and Exit Timing
CK
tIHCKE
tCPDED
Input clock frequency can be changed
or the input clock can be stopped during DPD.
2 tCK (MIN)
tINIT31, 2
CKE
tISCKE
tISCKE
CS_n
tRP
CMD
tDPD
NOP Enter
DPD NOP
Exit
DPD
NOP
Enter DPD mode
Notes:
Exit DPD mode
NOP
RESET
Don’t Care
1. The initialization sequence can start at any time after Tx + 1.
2. tINIT3 and Tx + 1 refer to timings in the initialization sequence. For details, see the
Mode Register Definition section.
Input Clock Frequency Changes and Stop Events
Input Clock Frequency Changes and Clock Stop with CKE LOW
During CKE LOW, the device supports input clock frequency changes and clock stop
under the following conditions:
• Refresh requirements are met
• Only REFab or REFpb commands can be in process
• Any ACTIVATE or PRECHARGE commands have completed prior to changing the frequency
• Related timing conditions, tRCD and tRP, have been met prior to changing the frequency
• The initial clock frequency must be maintained for a minimum of two clock cycles after CKE goes LOW
• The clock satisfies tCH(abs) and tCL(abs) for a minimum of two clock cycles prior to
CKE going HIGH
For input clock frequency changes, tCK (MIN) and tCK (MAX) must be met for each
clock cycle.
After the input clock frequency changes and CKE is held HIGH, additional MRW commands may be required to set the WR, RL, and so on. These settings may require adjustment to meet minimum timing requirements at the target clock frequency.
96
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
NO OPERATION Command
For clock stop, CK_t is held LOW and CK_c is held HIGH.
Input Clock Frequency Changes and Clock Stop with CKE HIGH
During CKE HIGH, the device supports input clock frequency changes and clock stop
under the following conditions:
• Refresh requirements are met
• Any ACTIVATE, READ, WRITE, PRECHARGE, MRW, or MRR commands have completed, including any associated data bursts, prior to changing the frequency
• Related timing conditions, tRCD, tWR, tWRA, tRP, tMRW, tMRR, and so on, are met
• CS_n must be held HIGH
• Only REFab or REFpb commands can be in process
The device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs)
for a minimum of 2 × tCK + tXP.
After the input clock frequency changes, tCK (MIN) and tCK (MAX) must be met for
each clock cycle.
After the input clock frequency changes, additional MRW commands may be required
to set the WR, RL, and so on. These settings may require adjustment to meet minimum
timing requirements at the target clock frequency.
For clock stop, CK_t is held LOW and CK_c is held HIGH.
NO OPERATION Command
The NO OPERATION (NOP) command prevents the device from registering any unwanted commands issued between operations. A NOP command can be issued only at
clock cycle n when the CKE level is constant for clock cycle n - 1 and clock cycle n. A
NOP command has two possible encodings:
1. CS_n HIGH at the clock rising edge n.
2. CS_n LOW with CA0, CA1, CA2 HIGH at the clock rising edge n.
The NOP command does not terminate a previous operation that is still in process,
such as a READ burst or WRITE burst cycle.
97
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Truth Tables
Truth Tables
Truth tables provide complementary information to the state diagram. They also clarify
device behavior and applicable restrictions when considering the actual state of the
banks.
Unspecified operations and timings are illegal. To ensure proper operation after an illegal event, the device must be powered down and then restarted using the specified initialization sequence before normal operation can continue.
Table 59: Command Truth Table
Notes 1–13 apply to entire table
Command Pins
CKE
Command
MRW
MRR
CK(n-1)
CK(n)
CS_
n
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
H
H
L
L
L
L
L
MA0
MA1
MA2
MA3
MA4
MA5
X
MA6
MA7
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
L
L
L
L
H
MA0
MA1
MA2
MA3
MA4
MA5
X
MA6
MA7
L
L
L
H
REFRESH
(per bank)
H
REFRESH
(all banks)
H
Enter self refresh
H
ACTIVATE
(bank)
H
WRITE (bank)
H
READ (bank)
H
H
X
H
L
X
X
H
L
X
L
L
H
H
X
X
L
X
H
PRECHARGE
(per bank, all
banks)
H
ENTER DPD
H
L
X
L
L
H
H
H
H
H
X
L
L
H
R8
R9
R10
R11
R12
BA0
BA1
BA2
X
R0
R1
R2
R3
R4
R5
R6
R7
R13
R14
L
H
L
L
RFU
RFU
C1
C2
BA0
BA1
BA2
X
AP
C3
C4
C5
C6
C7
C8
C9
C10
C11
L
H
L
H
RFU
RFU
C1
C2
BA0
BA1
BA2
X
AP
C3
C4
C5
C6
C7
C8
C9
C10
C11
L
H
H
L
H
AB
X
X
BA0
BA1
BA2
X
H
L
L
X
H
H
L
X
H
L
L
NOP
H
L
H
L
X
X
H
H
H
X
MAINTAIN PD,
SREF, DPD
(NOP)
X
X
X
NOP
CA Pins
X
X
H
H
H
X
X
X
H
X
X
X
98
CK
Edge
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Truth Tables
Table 59: Command Truth Table (Continued)
Notes 1–13 apply to entire table
Command Pins
CKE
CA Pins
CK(n-1)
CK(n)
CS_
n
MAINTAIN PD,
SREF, DPD
L
L
X
X
X
X
ENTER POWER-DOWN
H
H
X
X
X
Exit PD, SREF,
DPD
L
H
X
X
X
Command
L
X
H
X
Notes:
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CK
Edge
1. All commands are defined by the current state of CS_n, CA0, CA1, CA2, CA3, and CKE at
the rising edge of the clock.
2. Bank addresses (BA) determine which bank will be operated upon.
3. AP HIGH during a READ or WRITE command indicates that an auto precharge will occur
to the bank associated with the READ or WRITE command.
4. X indicates a “Don’t Care” state, with a defined logic level, either HIGH (H) or LOW (L).
For PD, SREF and DPD, CS_n, CK can be floated after tCPDED has been met and until the
required exit procedure is initiated as described in their respective entry/exit procedures.
5. Self refresh exit and DPD exit are asynchronous.
6. VREF must be between 0 and VDDQ during SREF and DPD operation.
7. CAxr refers to command/address bit “x” on the rising edge of clock.
8. CAxf refers to command/address bit “x” on the falling edge of clock.
9. CS_n and CKE are sampled on the rising edge of the clock.
10. The least significant column address C0 is not transmitted on the CA bus, and is inferred
to be zero.
11. AB HIGH during a PRECHARGE command indicates that an all-bank precharge will occur.
In this case, bank address is a "Don't Care."
12. RFU needs to input H or L (defined logic level).
13. When CS_n is HIGH, the CA bus can be floated.
Table 60: CKE Truth Table
Notes 1–5 apply to entire table; L = LOW; H = HIGH; X = “Don’t Care”
Command
n
Current State
CKEn-1
CKEn
CS_n
Active
power-down
Idle power-down
Resetting idle
power-down
L
L
X
X
L
H
H
NOP
L
L
X
X
L
H
H
NOP
L
L
X
X
L
H
H
NOP
Operation n
Maintain active power-down
Exit active power-down
Maintain idle power-down
Exit idle power-down
Maintain resetting power-down
Exit resetting power-down
99
Next State
Notes
Active
power-down
Active
6, 7
Idle
power-down
Idle
6, 7
Resetting
power-down
Idle or resetting 6, 7, 8
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Truth Tables
Table 60: CKE Truth Table (Continued)
Notes 1–5 apply to entire table; L = LOW; H = HIGH; X = “Don’t Care”
Command
n
Current State
CKEn-1
CKEn
CS_n
Deep powerdown
Self refresh
L
L
X
X
L
H
H
NOP
Operation n
Next State
Maintain deep power-down
Exit deep power-down
Deep
power-down
Power-on
9
L
L
X
X
L
H
H
NOP
Exit self refresh
Bank(s) active
H
L
H
NOP
Enter active power-down
Active
power-down
All banks idle
H
L
H
NOP
Enter idle power-down
Idle
power-down
12
H
L
L
Self refresh
12
H
L
L
DPD
Enter deep power-down
Deep
power-down
12
Resetting
H
L
H
NOP
Enter resetting power-down
Resetting
power-down
Other states
H
H
Notes:
Maintain self refresh
Notes
Self refresh
Idle
ENTER SELF Enter self refresh
REFRESH
10, 11
Refer to the command truth table
1. Current state is the state of the device immediately prior to clock edge n.
2. All states and sequences not shown are illegal or reserved unless explicitly described
elsewhere in this document.
3. CKEn is the logic state of CKE at clock rising edge n; CKEn-1 was the state of CKE at the
previous clock edge.
4. CS_n is the logic state of CS_n at the clock rising edge n.
5. Command n is the command registered at clock edge n, and operation n is a result of
command n.
6. Power-down exit time (tXP) must elapse before any command other than NOP is issued.
7. The clock must toggle at least twice prior to the tXP period.
8. Upon exiting the resetting power-down state, the device will return to the idle state if
tINIT5 has expired.
9. The DPD exit procedure must be followed as described in Deep Power-Down.
10. Self refresh exit time (tXSR) must elapse before any command other than NOP is issued.
11. The clock must toggle at least twice prior to the tXSR time.
12. In the case of ODT disabled, all DQ output must be High-Z. In the case of ODT enabled,
all DQ must be terminated to VDDQ.
Table 61: Current State Bank n to Command to Bank n Truth Table
Notes 1–5 apply to entire table
Current State
Command
Any
NOP
Operation
Continue previous operation
100
Next State
Current state
Notes
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Truth Tables
Table 61: Current State Bank n to Command to Bank n Truth Table (Continued)
Notes 1–5 apply to entire table
Current State
Command
Idle
ACTIVATE
REFRESH (all banks)
Active
Begin to refresh
Refreshing (per bank)
6
Begin to refresh
Refreshing (all banks)
7
MR writing
7
Load value to mode register
MRR
Read value from mode register
Idle, MR reading
RESET
Begin device auto initialization
Resetting
7, 8
9, 10
PRECHARGE
Deactivate row(s) in bank or banks
Precharging
READ
Select column and start read burst
Reading
WRITE
Select column and start write burst
Writing
Read value from mode register
PRECHARGE
Writing
Notes
MRW
MRR
Reading
Next State
Select and activate row
REFRESH (per bank)
Row active
Operation
Active MR reading
Precharging
9
READ
Deactivate row(s) in bank or banks
Select column and start new read burst
Reading
11, 12
WRITE
Select column and start write burst
Writing
11, 12, 13
WRITE
Select column and start new write burst
Writing
11, 12
READ
Select column and start read burst
Reading
11, 12, 14
Power-on
MRW RESET
Begin device auto initialization
Resetting
7, 9
Resetting
MRR
Read value from mode register
Resetting MR reading
Notes:
1. Values in this table apply when both CKEn -1 and CKEn are HIGH, and after tXSR or tXP
has been met, if the previous state was power-down.
2. All states and sequences not shown are illegal or reserved.
3. Current state definitions:
State
Definition
Idle
The bank or banks have been precharged, and tRP has been met.
Active
A row in the bank has been activated, and tRCD has been met. No data bursts or accesses, and no register accesses, are in progress.
Reading
A READ burst has been initiated with auto precharge disabled, and
has not yet terminated.
Writing
A WRITE burst has been initiated with auto precharge disabled, and
has not yet terminated.
4. The states listed below must not be interrupted by a command issued to the same bank.
NOP commands or supported commands to the other bank should be issued on any
clock edge occurring during these states. Supported commands to the other banks are
determined by that bank’s current state, and the definitions given in the table: Current
State Bank n to Command to Bank m.
State
Starts with...
Ends
when...
tRP
is met
Precharging
Registration of a PRECHARGE command
Row activating
Registration of an ACTIVATE tRCD is met
command
101
Notes
After tRP is met, the bank is
in the idle state.
After tRCD is met, the bank
is in the active state.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Truth Tables
State
Starts with...
Ends
when...
READ with
AP enabled
Registration of a READ command with auto precharge
enabled
tRP
WRITE with
AP enabled
Registration of a WRITE
command with auto precharge enabled
tRP
Notes
is met
After tRP is met, the bank is
in the idle state.
is met
After tRP is met, the bank is
in the idle state.
5. The states listed below must not be interrupted by any executable command. NOP commands must be applied to each positive clock edge during these states.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Ends
when...
State
Starts with...
Refreshing
(per bank)
Registration of a REFRESH
(per bank) command
tRFCpb
is met After tRFCpb is met, the
bank is in the idle state.
Notes
Refreshing
(all banks)
Registration of a REFRESH
(all banks) command
tRFCab
is met After tRFCab is met, the device is in the all banks idle
state.
Idle MR read- Registration of the MRR
ing
command
tMRR
is met
After tMRR is met, the device is in the all banks idle
state.
Resetting MR Registration of the MRR
reading
command
tMRR
is met
After tMRR is met, the device is in the all banks idle
state.
Active MR
reading
Registration of the MRR
command
tMRR
is met
After tMRR is met, the bank
is in the active state.
MR writing
Registration of the MRW
command
tMRW
Precharging
all
Registration of a PRECHARGE ALL command
tRP
is met After tMRW is met, the device is in the all banks idle
state.
is met
After tRP is met, the device
is in the all banks idle state.
Bank-specific; requires that the bank is idle and no bursts are in progress.
Not bank-specific; requires that all banks are idle and no bursts are in progress.
Not bank-specific.
This command may or may not be bank-specific. If all banks are being precharged, they
must be in a valid state for precharging.
If a PRECHARGE command is issued to a bank in the idle state, tRP still applies.
A command other than NOP should not be issued to the same bank while a READ or
WRITE with auto precharge is enabled.
The new READ or WRITE command could be auto precharge enabled or auto precharge
disabled.
A WRITE command can be issued only after the completion of the READ burst.
A READ command can be issued only after completion of the WRITE burst.
Table 62: Current State Bank n to Command to Bank m Truth Table
Notes 1–6 apply to entire table
Current State
of Bank n
Command to Bank m
Any
NOP
Operation
Continue previous operation
102
Next State for Bank m
Current state of bank m
Notes
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Truth Tables
Table 62: Current State Bank n to Command to Bank m Truth Table (Continued)
Notes 1–6 apply to entire table
Current State
of Bank n
Command to Bank m
Idle
Row activating,
active, or precharging
Any
Writing
(auto precharge
disabled)
Reading with
auto precharge
Writing with
auto precharge
Next State for Bank m
Any command supported to bank m
ACTIVATE
Notes
–
Select and activate row in bank m
Active
6
READ
Select column and start READ burst
from bank m
Reading
7
WRITE
Select column and start WRITE burst to
bank m
Writing
7
Precharging
8
Idle MR reading or active
MR reading
9, 10, 11
PRECHARGE
Reading
(auto precharge
disabled)
Operation
Deactivate row(s) in bank or banks
MRR
READ value from mode register
READ
Select column and start READ burst
from bank m
Reading
7
WRITE
Select column and start WRITE burst to
bank m
Writing
7, 12
ACTIVATE
Select and activate row in bank m
Active
PRECHARGE
Deactivate row(s) in bank or banks
Precharging
8
READ
Select column and start READ burst
from bank m
Reading
7, 13
WRITE
Select column and start WRITE burst to
bank m
Writing
7
ACTIVATE
Select and activate row in bank m
Active
PRECHARGE
Deactivate row(s) in bank or banks
Precharging
8
READ
Select column and start READ burst
from bank m
Reading
7, 14
WRITE
Select column and start WRITE burst to
bank m
Writing
7, 12, 14
ACTIVATE
Select and activate row in bank m
Active
PRECHARGE
Deactivate row(s) in bank or banks
Precharging
8
READ
Select column and start READ burst
from bank m
Reading
7, 13, 14
WRITE
Select column and start WRITE burst to
bank m
Writing
7, 14
ACTIVATE
Select and activate row in bank m
Active
PRECHARGE
Deactivate row(s) in bank or banks
Precharging
8
15, 16
Power-on
MRW RESET
Begin device auto initialization
Resetting
Resetting
MRR
Read value from mode register
Resetting MR reading
Notes:
1. This table applies when:
• The previous state was self refresh or power-down;
• After tXSR or tXP has been met; and
103
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Truth Tables
• When both CKEn -1 and CKEn are HIGH.
2. All states and sequences not shown are illegal or reserved.
3. Current state definitions:
State
Condition
And…
Idle
The bank has been precharged
tRP
And…
Active
A row in the bank has been
activated
tRCD
Reading
A READ burst has been initi- The READ
ated with auto precharge
has not yet
disabled
terminated
Writing
A WRITE burst has been ini- The WRITE
tiated with auto precharge has not yet
disabled
terminated
is met
is met
No data bursts/accesses and
no register accesses are in
progress.
4. Refresh, self refresh, and MRW commands can only be issued when all banks are idle.
5. The states listed below must not be interrupted by any executable command. NOP commands must be applied during each clock cycle while in these states:
State
Starts with...
Ends
when...
Notes
Idle MR read- Registration of the MRR
ing
command
tMRR
is met
After tMRR is met, the device is in the all banks idle
state.
Resetting MR Registration of the MRR
reading
command
tMRR
is met
After tMRR is met, the device is in the all banks reset
state.
Active MR
reading
Registration of the MRR
command
tMRR
is met
After tMRR is met, the bank
is in the active state.
MR writing
Registration of the MRW
command
tMRW
is met After tMRW is met, the device is in the all banks idle
state.
6. tRRD must be met between the ACTIVATE command to bank n and any subsequent
ACTIVATE command to bank m.
7. READs or WRITEs listed in the command column include READs and WRITEs with or
without auto precharge enabled.
8. This command may or may not be bank-specific. If all banks are being precharged, they
must be in a valid state for precharging.
9. MRR is supported in the row-activating state.
10. MRR is supported in the precharging state.
11. The next state for bank m depends on the current state of bank m (idle, row-activating,
precharging, or active).
12. A WRITE command can be issued only after the completion of the READ burst.
13. A READ command can be issued only after the completion of the WRITE burst.
14. A READ with auto precharge enabled or a WRITE with auto precharge enabled can be
followed by any valid command to other banks, provided that the timing restrictions in
the PRECHARGE and Auto Precharge Clarification table are met.
15. Not bank-specific; requires that all banks are idle and no bursts are in progress.
16. RESET command is achieved through the MODE REGISTER WRITE command.
104
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Absolute Maximum Ratings
Table 63: DM Truth Table
DM
DQ
Notes
Write enable
Functional Name
L
Valid
1
Write inhibit
H
X
1
Note:
1. Used to mask write data; provided simultaneously with the corresponding input data.
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these conditions, or any other conditions outside those indicated in the operational sections of this document, is
not implied. Exposure to absolute maximum rating conditions for extended periods
may adversely affect reliability.
Table 64: Absolute Maximum DC Ratings
Parameter
Symbol
Min
Max
Unit
Notes
VDD1 supply voltage relative to VSS
VDD1
–0.4
2.3
V
1
VDD2 supply voltage relative to VSS
VDD2
–0.4
1.6
V
1
VDDCA supply voltage relative to VSSCA
VDDCA
–0.4
1.6
V
1, 2
VDDQ supply voltage relative to VSSQ
VDDQ
–0.4
1.6
V
1, 3
VIN, VOUT
–0.4
1.6
V
TSTG
–55
125
˚C
Voltage on any ball relative to VSS
Storage temperature
Notes:
4
1. For information about relationships between power supplies, see the Power-Up and Initialization section.
2. VREFCA ≤ 0.6 × VDDCA; however, VREFCA may be ≥ VDDCA, provided that VREFCA ≤ 300mV.
3. VREFDQ ≤ 0.7 × VDDQ; however, VREFDQ may be ≥ VDDQ, provided that VREFDQ ≤ 300mV.
4. Storage temperature is the case surface temperature on the center/top side of the device. For measurement conditions, refer to the JESD51-2 standard.
105
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Electrical Specifications – IDD Measurements and Conditions
Electrical Specifications – IDD Measurements and Conditions
The following definitions and conditions are used in the IDD measurement tables unless
stated otherwise:
•
•
•
•
LOW: V IN ≤ V IL(DC)max
HIGH: V IN ≥ V IH(DC)min
STABLE: Inputs are stable at a HIGH or LOW level
SWITCHING: See the following three tables
Table 65: Switching for CA Input Signals
CK_t
(Rising)/
CK_c
(Falling)
CK_t
(Falling)/
CK_c
(Rising)
CK_t
(Rising)/
CK_c
(Falling)
CK_t
(Falling)/
CK_c
(Rising)
CK_t
(Rising)/
CK_c
(Falling)
CK_t
(Falling)/
CK_c
(Rising)
CK_t
(Rising)/
CK_c
(Falling)
CK_t
(Falling)/
CK_c
(Rising)
Cycle
N
N+1
N+2
N+3
CS_n
HIGH
HIGH
HIGH
HIGH
CA0
H
L
L
L
L
CA1
H
H
H
L
L
CA2
H
L
L
L
L
CA3
H
H
H
L
L
CA4
H
L
L
L
L
CA5
H
H
H
L
L
CA6
H
L
L
L
L
CA7
H
H
H
L
L
CA8
H
L
L
L
CA9
H
H
H
L
Notes:
H
H
H
L
L
H
H
H
H
L
L
H
H
H
H
L
L
H
H
H
H
L
L
H
L
H
H
H
L
L
L
H
1. CS_n must always be driven HIGH.
2. For each clock cycle, 50% of the CA bus is changing between HIGH and LOW.
3. The noted pattern (N, N + 1, N + 2, N + 3...) is used continuously during IDD measurement for IDD values that require switching on the CA bus.
Table 66: Switching for IDD4R
Clock
CKE
CS_n
Clock Cycle
Number
Command
CA[2:0]
CA[9:3]
All DQ
Rising
H
L
N
Read_Rising
HLH
LHLHLHL
L
Falling
H
L
N
Read_Falling
LLL
LLLLLLL
L
Rising
H
H
N+1
NOP
LLL
LLLLLLL
H
Falling
H
H
N+1
NOP
LLL
LLLLLLL
L
Rising
H
H
N+2
NOP
LLL
LLLLLLL
H
Falling
H
H
N+2
NOP
LLL
LLLLLLL
H
Rising
H
H
N+3
NOP
LLL
LLLLLLL
H
Falling
H
H
N+3
NOP
HLH
LHLLHLH
L
106
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Electrical Specifications – IDD Measurements and Conditions
Table 66: Switching for IDD4R (Continued)
Clock
CKE
CS_n
Clock Cycle
Number
Command
CA[2:0]
CA[9:3]
All DQ
Rising
H
L
N+4
Read_Rising
HLH
LHLLHLH
H
Falling
H
L
N+4
Read_Falling
HHL
HHHHHHH
H
Rising
H
H
N+5
NOP
HHH
HHHHHHH
H
Falling
H
H
N+5
NOP
HHH
HHHHHHH
L
Rising
H
H
N+6
NOP
HHH
HHHHHHH
L
Falling
H
H
N+6
NOP
HHH
HHHHHHH
L
Rising
H
H
N+7
NOP
HHH
HHHHHHH
H
Falling
H
H
N+7
NOP
HLH
LHLHLHL
L
Notes:
1. Data strobe (DQS_t) is changing between HIGH and LOW with every clock cycle.
2. The noted pattern (N, N + 1...) is used continuously during IDD measurement for IDD4R.
Table 67: Switching for IDD4W
Clock
CKE
CS_n
Clock Cycle
Number
Command
CA[2:0]
CA[9:3]
All DQ
Rising
H
L
N
Write_Rising
LLH
LHLHLHL
L
Falling
H
L
N
Write_Falling
LLL
LLLLLLL
L
Rising
H
H
N+1
NOP
LLL
LLLLLLL
H
Falling
H
H
N+1
NOP
LLL
LLLLLLL
L
Rising
H
H
N+2
NOP
LLL
LLLLLLL
H
Falling
H
H
N+2
NOP
LLL
LLLLLLL
H
Rising
H
H
N+3
NOP
LLL
LLLLLLL
H
Falling
H
H
N+3
NOP
LLH
LHLLHLH
L
Rising
H
L
N+4
Write_Rising
LLH
LHLLHLH
H
Falling
H
L
N+4
Write_Falling
HHL
HHHHHHH
H
Rising
H
H
N+5
NOP
HHH
HHHHHHH
H
Falling
H
H
N+5
NOP
HHH
HHHHHHH
L
Rising
H
H
N+6
NOP
HHH
HHHHHHH
L
Falling
H
H
N+6
NOP
HHH
HHHHHHH
L
Rising
H
H
N+7
NOP
HHH
HHHHHHH
H
Falling
H
H
N+7
NOP
LLH
LHLHLHL
L
Notes:
1. Data strobe (DQS_t) is changing between HIGH and LOW with every clock cycle.
2. Data masking (DM) must always be driven LOW.
3. The noted pattern (N, N + 1...) is used continuously during IDD measurement for IDD4W.
107
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Electrical Specifications – IDD Measurements and Conditions
IDD Specifications
IDD values are for the entire operating voltage range, and all of them are for the entire
standard range, with the exception of IDD6ET, which is for the entire extended temperature range.
Table 68: IDD Specification Parameters and Operating Conditions
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
Notes 1, 2, 3, and 5 apply to entire table; Note 4 applies to all "in" values
Parameter/Condition
Operating one bank active-precharge current: tCK = tCK
(MIN); tRC = tRC (MIN); CKE is HIGH; CS_n is HIGH between valid
commands; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Idle power-down standby current: tCK = tCK (MIN); CKE is
LOW; CS_n is HIGH; All banks are idle; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Idle power-down standby current with clock stop: CK_t =
LOW, CK_c = HIGH; CKE is LOW; CS_n is HIGH; All banks are idle;
CA bus inputs are stable; Data bus inputs are stable; ODT is disabled
Idle non-power-down standby current: tCK = tCK (MIN); CKE is
HIGH; CS_n is HIGH; All banks are idle; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Idle non-power-down standby current with clock stopped:
CK_t = LOW; CK_c = HIGH; CKE is HIGH; CS_n is HIGH; All banks
are idle; CA bus inputs are stable; Data bus inputs are stable; ODT
is disabled
Active power-down standby current: tCK = tCK (MIN); CKE is
LOW; CS_n is HIGH; One bank is active; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Active power-down standby current with clock stop: CK_t =
LOW, CK_c = HIGH; CKE is LOW; CS_n is HIGH; One bank is active;
CA bus inputs are stable; Data bus inputs are stable; ODT is disabled
Active non-power-down standby current: tCK = tCK (MIN);
CKE is HIGH; CS_n is HIGH; One bank is active; CA bus inputs are
switching; Data bus inputs are stable; ODT is disabled
Active non-power-down standby current with clock stopped: CK_t = LOW, CK_c = HIGH; CKE is HIGH; CS_n is HIGH; One
bank is active; CA bus inputs are stable; Data bus inputs are stable; ODT is disabled
108
Symbol
Power
Supply
IDD01
VDD1
IDD02
VDD2
IDD0,in
VDDCA, VDDQ
IDD2P1
VDD1
IDD2P2
VDD2
IDD2P,in
VDDCA, VDDQ
IDD2PS1
VDD1
IDD2PS2
VDD2
IDD2PS,in
VDDCA, VDDQ
IDD2N1
VDD1
IDD2N2
VDD2
IDD2N,in
VDDCA, VDDQ
IDD2NS1
VDD1
IDD2NS2
VDD2
IDD2NS,in
VDDCA, VDDQ
IDD3P1
VDD1
IDD3P2
VDD2
IDD3P,in
VDDCA, VDDQ
IDD3PS1
VDD1
IDD3PS22
VDD2
IDD3PS,in
VDDCA, VDDQ
IDD3N1
VDD1
IDD3N2
VDD2
IDD3N,in
VDDCA, VDDQ
IDD3NS1
VDD1
IDD3NS2
VDD2
IDD3NS,in
VDDCA, VDDQ
Notes
2
2
2
2
2
2
3
3
3
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Electrical Specifications – IDD Measurements and Conditions
Table 68: IDD Specification Parameters and Operating Conditions (Continued)
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
Notes 1, 2, 3, and 5 apply to entire table; Note 4 applies to all "in" values
Parameter/Condition
tCK
tCK
=
(MIN); CS_n is HIGH
Operating burst READ current:
between valid commands; One bank is active; BL = 8; RL = RL
(MIN); CA bus inputs are switching; 50% data change each burst
transfer; ODT is disabled
Operating burst WRITE current: tCK = tCK (MIN); CS_n is HIGH
between valid commands; One bank is active; BL = 8; WL = WL
(MIN); CA bus inputs are switching; 50% data change each burst
transfer; ODT is disabled
All-bank REFRESH burst current: tCK = tCK (MIN); CKE is HIGH
between valid commands; tRC = tRFCab (MIN); Burst refresh; CA
bus inputs are switching; Data bus inputs are stable; ODT is disabled
All-bank REFRESH average current: tCK = tCK (MIN); CKE is
HIGH between valid commands; tRC = tREFI; CA bus inputs are
switching; Data bus inputs are stable; ODT is disabled
Per-bank REFRESH average current: tCK = tCK (MIN); CKE is
HIGH between valid commands; tRC = tREFI/8; CA bus inputs are
switching; Data bus inputs are stable; ODT is disabled
Self refresh current (0˚C to +85˚C): CK_t = LOW, CK_c =
HIGH; CKE is LOW; CA bus inputs are stable; Data bus inputs are
stable; Maximum 1x self refresh rate; ODT is disabled
Self refresh current (+85˚C to +105˚C): CK_t = LOW, CK_c =
HIGH; CKE is LOW; CA bus inputs are stable; Data bus inputs are
stable; ODT is disabled
Deep power-down current: CK_t = LOW, CK_c = HIGH; CKE is
LOW; CA bus inputs are stable; Data bus inputs are stable; ODT is
disabled
Notes:
Symbol
Power
Supply
IDD4R1
VDD1
Notes
IDD4R2
VDD2
IDD4R,in
VDDCA
IDD4W1
VDD1
IDD4W2
VDD2
IDD4W,in
VDDCA, VDDQ
IDD51
VDD1
IDD52
VDD2
IDD5,in
VDDCA, VDDQ
IDD5AB1
VDD1
IDD5AB2
VDD2
IDD5AB,in
VDDCA, VDDQ
IDD5PB1
VDD1
IDD5PB2
VDD2
IDD5PB,in
VDDCA, VDDQ
3
3
3
3
IDD61
VDD1
4, 5
IDD62
VDD2
4, 5
IDD6,in
VDDCA, VDDQ
3, 4
IDD6ET1
VDD1
5, 6
IDD6ET2
VDD2
5, 6
IDD6ET,in
VDDCA, VDDQ
3, 5, 6
IDD81
VDD1
IDD82
VDD2
IDD8,in
VDDCA, VDDQ
3
ODT disabled: MR11[2:0] = 000b.
IDD current specifications are tested after the device is properly initialized.
Measured currents are the summation of VDDQ and VDDCA.
The 1x self refresh rate is the rate at which the device is refreshed internally during self
refresh before going into the elevated temperature range.
5. This is the general definition that applies to full-array self-refresh.
6. IDD6ET is a typical value, is sampled only, and is not tested.
7. For all IDD measurements, VIHCKE = 0.8 × VDDCA; VILCKE = 0.2 × VDDCA.
1.
2.
3.
4.
109
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Operating Conditions
AC and DC Operating Conditions
Operation or timing that is not specified is illegal. To ensure proper operation, the device must be initialized properly.
Table 69: Recommended DC Operating Conditions
Note 1 applies to entire table
Symbol
Min
Typ
Max
DRAM
Unit
Notes
2
VDD1
1.70
1.80
1.95
Core power 1
V
VDD2
1.14
1.20
1.30
Core power 2
V
VDDCA
1.14
1.20
1.30
Input buffer power
V
VDDQ
1.14
1.20
1.30
I/O buffer power
V
Notes:
1. The voltage range is for DC voltage only. DC is defined as the voltage supplied at the
DRAM and is inclusive of all noise up to 1 MHz at the DRAM package ball.
2. VDD1 uses significantly less power than VDD2.
Table 70: Input Leakage Current
Symbol
Min
Max
Unit
Notes
Input leakage current: For CA, CKE, CS_n, CK; Any input 0V ≤ VIN ≤ VDDCA; (All other pins not under test = 0V)
Parameter/Condition
II
–2
2
μA
1
VREF supply leakage current: VREFDQ = VDDQ/2, or VREFCA = VDDCA/2; (All other pins not under test = 0V)
IVREF
–1
1
μA
2
Notes:
1. Although DM is for input only, the DM leakage must match the DQ and DQS output
leakage specification.
2. The minimum limit requirement is for testing purposes. The leakage current on VREFCA
and VREFDQ pins should be minimal.
Table 71: Operating Temperature Range
Notes 1 and 2 apply to entire table
Parameter/Condition
Standard (WT) temperature range
Symbol
TCASE
1
Wide temperature range
Notes:
Min
Max
Unit
-25
85
˚C
0
105
˚C
1. Operating temperature is the case surface temperature at the center of the top side of
the device. For measurement conditions, refer to the JESD51-2 standard.
2. Either the device operating temperature or the temperature sensor can be used to set
an appropriate refresh rate, determine the need for AC timing derating, and/or monitor
the operating temperature (see Temperature Sensor). When using the temperature sensor, the actual device case temperature may be higher than the TCASE rating that applies
for the operating temperature range. For example, TCASE could be above +85˚C when
the temperature sensor indicates a temperature of less than +85˚C.
110
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
AC and DC Logic Input Measurement Levels for Single-Ended Signals
Table 72: Single-Ended AC and DC Input Levels for CA and CS_n Inputs
Parameter
Symbol
1333/1600
Min
1866/2133
Max
Min
Max
Unit
Notes
AC input logic HIGH
VIHCA(AC)
VREF + 0.150
Note 2
VREF + 0.135
Note 2
V
1, 2
AC input logic LOW
VILCA(AC)
Note 2
VREF - 0.150
Note 2
VREF - 0.135
V
1, 2
DC input logic HIGH
VIHCA(DC)
VREF + 0.100
VDDCA
VREF + 0.100
VDDCA
V
1
DC input logic LOW
VILCA(DC)
VSSCA
VREF - 0.100
VSSCA
VREF - 0.100
V
1
VREFCA(DC)
0.49 × VDDCA
0.51 × VDDCA
0.49 × VDDCA
0.51 × VDDCA
V
3, 4
Reference voltage for CA
and CS_n inputs
Notes:
1. For CA and CS_n input-only pins. VREF = VREFCA(DC).
2. See figure: Overshoot and Undershoot Definition.
3. The AC peak noise on VREFCA could prevent VREFCA from deviating more than ±1% VDDCA
from VREFCA(DC) (for reference, approximately ±12mV).
4. For reference, approximately VDDCA/2 ±12mV.
Table 73: Single-Ended AC and DC Input Levels for CKE
Parameter
Symbol
Min
Max
Unit
Notes
CKE input HIGH level
VIHCKE
0.65 × VDDCA
Note 1
V
1
CKE input LOW level
VILCKE
Note 1
0.35 × VDDCA
V
1
Note:
1. See figure: Overshoot and Undershoot Definition.
Table 74: Single-Ended AC and DC Input Levels for DQ and DM
Parameter
Symbol
AC input logic HIGH
VIHDQ(AC)
1333/1600
1866/2133
Min
Max
Min
Max
Unit Notes
VREF + 0.150
Note 2
VREF + 0.135
Note 2
V
1, 2, 5
AC input logic LOW
VILDQ(AC)
Note 2
VREF - 0.150
Note 2
VREF - 0.135
V
1, 2, 5
DC input logic HIGH
VIHDQ(DC)
VREF + 0.100
VDDQ
VREF + 0.100
VDDQ
V
1
DC input logic LOW
VILDQ(DC)
VSSQ
VREF - 0.100
VSSQ
VREF - 0.100
V
1
Reference voltage
for DQ and DM inputs
VREFDQ(DC)
0.49 × VDDQ
0.51 × VDDQ
0.49 × VDDQ
0.51 × VDDQ
V
3, 4
VODTR/2 - 0.01 ×
VDDQ
VODTR/2 + 0.01 ×
VDDQ
VODTR/2 - 0.01 ×
VDDQ
VODTR/2 + 0.01 ×
VDDQ
V
3, 5, 6
Reference voltage
for DQ and DM inputs (DQ ODT enabled)
VREFDQ(DC)
DQODT,enabled
Notes:
1. For DQ input-only pins. VREF = VREFDQ(DC).
2. See figure: Overshoot and Undershoot Definition.
3. The AC peak noise on VREFDQ could prevent VREFDQ from deviating more than ±1% VDDQ
from VREFDQ(DC) (for reference, approximately ±12mV).
111
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
4. For reference, approximately VDDQ/2 ±12mV.
5. For reference, approximately VODTR/2 ±12mV.
6. The nominal mode register programmed values for RODT and the nominal controller output impedance RON are used for the calculation of VODTR. For testing purposes, a controller RON value of 50Ω is used.
VODTR=
2RON + RTT
× VDDQ
RON + RTT
VREF Tolerances
The DC tolerance limits and AC noise limits for the reference voltages V REFCA and
VREFDQ are shown below. This figure shows a valid reference voltage V REF(t) as a function
of time. V DD is used in place of V DDCA for V REFCA, and V DDQ for V REFDQ. V REF(DC) is the
linear average of V REF(t) over a very long period of time (for example, 1 second), and is
specified as a fraction of the linear average of V DDQ or V DDCA, also over a very long period of time (for example, 1 second). This average must meet the MIN/MAX requirements
in the table: Single-Ended AC and DC Input Levels for CA and CS_n Inputs. Additionally,
VREF(t) can temporarily deviate from V REF(DC) by no more than ±1% V DD. V REF(t) cannot
track noise on V DDQ or V DDCA if doing so would force V REF outside these specifications.
Figure 71: VREF DC Tolerance and VREF AC Noise Limits
VDD
Voltage
VREF(AC) noise
VREF(t)
VREF(DC)max
VREF(DC)
VREF(DC)nom
VREF(DC)min
VSS
Time
The voltage levels for setup and hold time measurements V IH(AC), V IH(DC), V IL(AC), and
VIL(DC) are dependent on V REF. V REF shall be understood as V REF(DC), as defined in the
Single-Ended Requirements for Differential Signals figure.
VREF DC variations affect the absolute voltage a signal must reach to achieve a valid
HIGH or LOW, as well as the time from which setup and hold times are measured.
System timing and voltage budgets must account for V REF deviations outside this range.
The setup/hold specification and derating values must include time and voltage associated with V REF AC noise. Timing and voltage effects due to AC noise on V REF up to the
specified limit (±1% V DD) are included in device timings and associated deratings.
112
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
Input Signal
Figure 72: LPDDR3-1600 to LPDDR3-1333 Input Signal
VIL and VIH levels with ringback
1.550V
VDD + 0.35V
narrow pulse width
1.200V
VDD
0.750V
VIH(AC)
0.700V
VIH(DC)
0.624V
0.612V
0.600V
0.588V
0.576V
VREF + AC noise
VREF + DC error
VREF - DC error
VREF - AC noise
0.500V
VIL(DC)
0.450V
VIL(AC)
0.000V
VSS
Minimum VIL and VIH levels
0.750V
0.700V
VIH(AC)
VIH(DC)
0.624V
0.612V
0.600V
0.588V
0.576V
0.500V
VIL(DC)
0.450V
VIL(AC)
VSS - 0.35V
narrow pulse width
–0.350V
Notes:
1. Numbers reflect typical values.
2. For CA[9:0], CK, and CS_n, VDD stands for VDDCA. For DQ, DM, DQS, and ODT, VDD stands
for VDDQ.
3. For CA[9:0], CK, and CS_n, VSS stands for VSSCA. For DQ, DM, DQS, and ODT, VSS stands
for VSSQ.
113
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
Figure 73: LPDDR3-2133 to LPDDR3-1866 Input Signal
VIL and VIH levels with ringback
1.550V
VDD + 0.35V
narrow pulse width
1.200V
VDD
0.735V
VIH(AC)
0.700V
VIH(DC)
0.624V
0.612V
0.600V
0.588V
0.576V
VREF + AC noise
VREF + DC error
VREF - DC error
VREF - AC noise
0.500V
VIL(DC)
0.565V
VIL(AC)
0.000V
VSS
Minimum VIL and VIH levels
0.735V
0.700V
VIH(AC)
VIH(DC)
0.624V
0.612V
0.600V
0.588V
0.576V
0.500V
VIL(DC)
0.565V
VIL(AC)
VSS - 0.35V
narrow pulse width
–0.350V
Notes:
1. Numbers reflect typical values.
2. For CA[9:0], CK, and CS_n, VDD stands for VDDCA. For DQ, DM, DQS, and ODT, VDD stands
for VDDQ.
3. For CA[9:0], CK, and CS_n, VSS stands for VSSCA. For DQ, DM, DQS, and ODT, VSS stands
for VSSQ.
114
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Logic Input Measurement Levels for Differential
Signals
AC and DC Logic Input Measurement Levels for Differential Signals
Figure 74: Differential AC Swing Time and tDVAC
tDVAC
Differential Voltage
VIH,diff(AC)min
VIH,diff(DC)min
CK
DQS
0.0
VIL,diff(DC)max
tDVAC
1/2 cycle
VIL,diff(AC)max
Time
Table 75: Differential AC and DC Input Levels
For CK, VREF = VREFCA(DC); For DQS, VREF = VREFDQ(DC)
LPDDR3
Parameter
Symbol
Min
Max
Unit
Notes
Differential input HIGH AC
VIH,diff(AC)
2 × (VIH(AC) - VREF)
Note 1
V
2
Differential input LOW AC
VIL,diff(AC)
Note 1
2 × (VIL(AC) - VREF)
V
2
Differential input HIGH DC
VIH,diff(DC)
2 × (VIH(DC) - VREF)
Note 1
V
3
Differential input LOW DC
VIL,diff(DC)
Note 1
2 × (VIL(DC) - VREF)
V
3
Notes:
1. These values are not defined; however, the single-ended signals CK and DQS must be
within the respective limits (VIH(DC)max, VIL(DC)min) for single-ended signals, and must comply with the specified limitations for overshoot and undershoot (see figure: Overshoot
and Undershoot Definition).
2. For CK, use VIH/VIL(AC) of CA and VREFCA; for DQS, use VIH/VIL(AC) of DQ and VREFDQ. If a
reduced AC HIGH or AC LOW is used for a signal group, the reduced voltage level also
applies.
3. Used to define a differential signal slew rate.
115
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Logic Input Measurement Levels for Differential
Signals
Table 76: CK and DQS Time Requirements Before Ringback (tDVAC)
tDVAC
(ps) @ VIH/
VIL,diff(AC) =
300mV1333 Mb/s
Slew Rate
(V/ns)
tDVAC
(ps) @ VIH/
VIL,diff(AC) =
300mV1600 Mb/s
tDVAC
(ps) @ VIH/VIL,diff(AC)
= 270mV1866 Mb/s
tDVAC
(ps) @ VIH/VIL,diff(AC)
= 270mV2133 Mb/s
Min
Max
Min
Max
Min
Max
Min
Max
>8.0
58
–
48
–
40
–
34
–
8.0
58
–
48
–
40
–
34
–
7.0
56
–
46
–
39
–
33
–
6.0
53
–
43
–
36
–
30
–
5.0
50
–
40
–
33
–
27
–
4.0
45
–
35
–
29
–
23
–
3.0
37
–
27
–
21
–
15
–
VIH(ac) = VREF(dc)+135mV, VIL(ac) = VREF(dc) - 135mV
DC100 Threshold -> VIH(dc) = VREF(dc) + 100mV, VIL(dc) = VREF(dc) - 100mV
CK_t, CK_c Differential Slew Rate
8.0 V/ns
CA, CS_n slew rate
V/ns
4.0
3.0
7.0 V/ns
6.0 V/ns
4.0 V/ns
3.0 V/ns
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
34
25
34
25
34
25
34
25
34
25
23
17
23
17
23
17
23
17
34
29
0
0
0
0
0
0
11
13
–23
–17
–23
–17
–12
–4
2.0
1.5
Note:
5.0 V/ns
ΔtIS
1. Shaded cells are not supported.
145
ΔtIS
ΔtIH
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
CA and CS_n Setup, Hold, and Derating
Table 101: Required Time for Valid Transition – tVAC > VIH(AC) and < VIL(AC)
Slew
Rate
(V/ns)
tVAC
at 150mV (ps)
1333 Mb/s
tVAC
at 150mV (ps)
1600 Mb/s
tVAC
at 135mV (ps)
1866 Mb/s
tVAC
at 135mV (ps)
2133 Mb/s
Min
Max
Min
Max
Min
Max
Min
Max
>4.0
58
–
48
–
40
–
34
–
4.0
58
–
48
–
40
–
34
–
3.5
56
–
46
–
39
–
33
–
3.0
53
–
43
–
36
–
30
–
2.5
50
–
40
–
33
–
27
–
2.0
45
–
35
–
29
–
23
–
1.5
37
–
27
–
21
–
15
–
V IH(AC) or <
VIL(AC) table).
The total setup time for slow slew rates could be negative (that is, a valid input signal
may not have reached V IH/VIL(AC) at the time of the rising clock transition). A valid input
signal is still required to complete the transition and reach V IH/VIL(AC).
For slew rates between the values listed in the following table, the derating values can
be obtained using linear interpolation. Slew rate values are not typically subject to production testing. They are verified by design and characterization.
151
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Data Setup, Hold, and Slew Rate Derating
Table 102: Data Setup and Hold Base Values
Data Rate
Parameter
1333
1600
(base)
100
75
–
–
VIH/VIL(AC) = VREF(DC) ±150mV
(base)
–
–
62.5
47.5
VIH/VIL(AC) = VREF(DC) ±135mV
125
100
80
65
VIH/VIL(DC) = VREF(DC) ±100mV
tDS
tDS
tDH
(base)
Note:
1866
2133
Reference
1. AC/DC referenced for 2 V/ns DQ, DM slew rate, and 4 V/ns differential DQS slew rate and
nominal VIX .
Table 103: Derating Values for AC/DC-Based tDS/tDH (AC150)
ΔtDS, ΔtDH derating in ps
ΔtDS, ΔtDH Derating in [ps] AC/DC-based
AC150 Threshold -> VIH(ac) = VREF(dc) + 150mV, VIL(ac) = VREF(dc) - 150mV
DC100 Threshold -> VIH(dc) = VREF(dc) + 100mV, VIL(dc) = VREF(dc) - 100mV
DQS_t, DQS_c Differential Slew Rate
8.0 V/ns
DQ, DM slew rate
V/ns
4.0
7.0 V/ns
6.0 V/ns
4.0 V/ns
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
38
25
38
25
38
25
38
25
38
25
25
17
25
17
25
17
25
17
0
0
3.0
2.0
1.5
Note:
5.0 V/ns
ΔtIS
3.0 V/ns
ΔtIS
ΔtIH
38
29
0
0
0
0
13
13
–25
–17
–25
–17
–12
–4
1. Shaded cells are not supported.
Table 104: Derating Values for AC/DC-Based tDS/tDH (AC135)
ΔtDS, ΔtDH derating in ps
ΔtDS, ΔtDH Derating in [ps] AC/DC-based
AC135 Threshold -> VIH(ac) = VREF(dc) + 135mV, VIL(ac) = VREF(dc) - 135mV
DC100 Threshold -> VIH(dc) = VREF(dc) + 100mV, VIL(dc) = VREF(dc) - 100mV
DQS_t, DQS_c Differential Slew Rate
8.0 V/ns
DQ, DM slew rate
V/ns
4.0
3.0
7.0 V/ns
6.0 V/ns
4.0 V/ns
3.0 V/ns
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
34
25
34
25
34
25
34
25
34
25
23
17
23
17
23
17
23
17
34
29
0
0
0
0
0
0
11
13
–23
–17
–23
–17
–12
–4
2.0
1.5
Note:
5.0 V/ns
ΔtIS
1. Shaded cells are not supported.
152
ΔtIS
ΔtIH
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Data Setup, Hold, and Slew Rate Derating
Table 105: Required Time for Valid Transition – tVAC > VIH(AC) or < VIL(AC)
Slew
Rate
(V/ns)
tVAC
at 150mV (ps)
1333 Mb/s
tVAC
at 150mV (ps)
1600 Mb/s
tVAC
at 135mV (ps)
1866 Mb/s
tVAC
at 135mV (ps)
2133 Mb/s
Min
Max
Min
Max
Min
Max
Min
Max
>4.0
58
–
48
–
40
–
34
–
4.0
58
–
48
–
40
–
34
–
3.5
56
–
46
–
39
–
33
–
3.0
53
–
43
–
36
–
30
–
2.5
50
–
40
–
33
–
27
–
2.0
45
–
35
–
29
–
23
–
1.5
37
–
27
–
21
–
15
–
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