RS128M32LD3D1LMZ-125BT

LPDDR3 Mobile RAM RS128M32LD3D1LMZ-125BT Specifications Features • Density: 4Gb • Organization: — 16: 32M words 16 bits 8 banks — 32: 16M words 32 bits 8 banks • Package: Bare Chip • Power supply — VDD1 = 1.70V to 1.95V — VDD2, VDDCA, VDDQ = 1.14V to 1.30V • Data rate: 1600Mbps max (RL = 12) • 4KB page size — Row address: R0 to R13 — Column address: C0 to C10 ( 16 bits) C0 to C9 ( 32 bits) • Eight internal banks for concurrent operation • Interface: HSUL_12 • Burst lengths (BL): 8 • Burst type (BT) — Sequential • Read latency (RL): 3, 6, 8, 9, 10, 11, 12 • Precharge: auto precharge option for each burst access • Programmable driver strength • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/32ms — Average refresh period: 3.9 s • Operating junction temperature range — Tj = 25 C to +85 C • Low power consumption • JEDEC LPDDR3 compliant • Per Bank Refresh • Partial Array Self-Refresh (PASR) — Bank Masking — Segment Masking • Auto Temperature Compensated Self-Refresh (ATCSR) by built-in temperature sensor • Deep power-down mode • On Die Termination (ODT) for better signal integrity • Double-data-rate architecture; two data transfers per one clock cycle • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture • Differential clock inputs (CK_t and CK_c) • Bi-directional differential data strobe (DQS_t and DQS_c) • Commands entered on both rising and falling CK_t edge; data and data mask referenced to both edges of DQS_t • Data mask (DM) for write data • CA training for CA input timing adjustment • Write leveling for clock to DQ, DQS_t, DQS_c and DM timing adjustment 1 Part Numbering Information Low Power memory devices are available in different configurations and densities. Table 1: Ordering Information Part Number Memory Combination RS128M32LD3D1LMZ LPDDR3 4Gb Operation Voltage Density Speed 1.8V/1.2/1.2/1.2 4Gb (x32, 1CS) DDR3 1333 2 Package 178Ball FBGA (Lead & Halogen Free) CONTENTS Specifications ........................................................................................................................................ 1 Features ................................................................................................................................................ 1 Part Number Information . ..................................................................................................................... 2 Ordering Information ............................................................................................................................. 3 Part Number .......................................................................................................................................... 3 Pin Descriptions .................................................................................................................................... 5 Pin Capacitance .................................................................................................................................... 6 Pin Configurations ................................................................................................................................ 7 Package Drawing .................................................................................................................................. 8 Package Dlock Diagrams . ...................................................................................................................... 8 1. Electrical Conditions ..................................................................................................................... 9 1.1 1.2 2. Electrical Specifications ................................................................................................................ 10 2.1 2.2 2.3 3. Absolute Maximum Ratings .............................................................................................................9 Recommended DC Operating Conditions ......................................................................................... 9 DC Characteristics 1 ........................................................................................................................10 DC Characteristics 2 ......................................................................................................... ................. 12 AC Characteristics .......................................................................................................................... 13 Mode Register Definition .............................................................................................................. 20 3 Pin Descriptions Pin name Function CK_t, CK_c Clock CKE Clock enable CS_n Chip select CA0 to CA9 DDR command/address inputs Address configurations Row:R0 to R13, Column:C0 to C10 ( 16 bits), C0 to C9 ( 32 bits) Bank:BA0 to BA2 DM0 to DM3 Input data mask 16: DM0 to DM1 32: DM0 to DM3 DQ0 to DQ31 Data input/output 16: DQ0 to DQ15 32: DQ0 to DQ31 DQS0_t to DQS3_t, DQS0_c to DQS3_c Data strobe 16: DQS0_t to DQS1_t, DQS0_c to DQS1_c 32: DQS0_t to DQS3_t, DQS0_c to DQS3_c ODT On-die termination VDD1 Core power supply 1 VDD2 Core power supply 2 VDDCA Input receiver power supply VDDQ I/O power supply VREFCA Reference voltage for CA input receiver VREFDQ Reference voltage for DQ input receiver VSS Ground VSSCA Ground for input receivers VSSQ I/O ground ZQ Reference pin for output drive strength calibration NU*1 Not usable Note: 1. Don’t connect. 4 Pin Capacitance Parameter Input capacitance Data input/output capacitance Notes: 1. 2. 3. Symbol Pins min max Unit Note CCK CK_t, CK_c 0.5 1.2 pF 1, 2 CI1 All other DDR3 Mobile RAM input only pins 0.5 1.1 pF 1, 2 CIO DQ0 to DQ31, DM0 to DM3, DQS0_t to DQS3_t, DQS0_c to DQS3_c 1.0 1.8 pF 1, 2, 3 CZQ ZQ 0.0 2.0 pF 1, 2, 3 This parameter is not subject to production test. It is verified by design and characterization. These parameters are measured on f = 100MHz, VOUT = VDDQ/2, TA = +25 C. DOUT circuits are disabled. 5 Pin Configurations 1 2 NU NU VDD1 VDD1 VDD1 VDD1 VDD2 NU VSS ZQ NC VSS VSSQ CA9 VSSCA NC VSS CA8 VSSCA VDD2 CA7 CA6 VDDCA VDDCA 10 11 12 13 VDD2 VDD1 VDDQ NU NU DQ31 DQ30 DQ29 DQ28 VSSQ NU VSSQ DQ27 DQ26 DQ25 DQ24 VDDQ VDD2 VDD2 DM3 DQ15 DQS3_t DQS3_c VSSQ VSS VSS VSSQ VDDQ DQ14 DQ13 DQ12 VDDQ CA5 VSSCA VSS VSSQ DQ11 DQ10 DQ9 DQ8 VSSQ VSSCA VSSCA VDD2 VSSQ DM1 VSSQ VDDCA VREFCA VDD2 VDD2 VDDQ VDDQ VSSQ VDDQ VDD2 A B C D E F G DQS1_t DQS1_c VDDQ H VSS J CK_c CK_t VSSCA VDD2 VDD2 ODT VDDQ VDDQ VREFDQ VSS VSS CKE NC VDD2 VDD2 VDDQ NC VSSQ VDDQ VDD2 VDDCA CS_n NC VDD2 VSS DM0 VSSQ VDDCA CA4 VSSCA VSS VSSQ DQ4 DQ5 DQ6 DQ7 VSSQ CA2 CA3 VSS VSS VSSQ VDDQ DQ1 DQ2 DQ3 VDDQ CA1 VSSCA VDD2 VDD2 VDD2 DM2 DQ0 CA0 NC VSS VSS VSSQ DQ20 DQ21 DQ22 DQ23 VDDQ NU VSS VSS VSS VSS VSSQ DQ16 DQ17 DQ18 DQ19 VSSQ NU NU NU VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD1 VDDQ NU NU K L DQS0_t DQS0_c VDDQ M N P DQS2_t DQS2_c VSSQ R T U (Top view) 6 PACKAGE INFORMATION 178 Ball 0.65mm pitch 11.0mm x 11.5mm [t = 1.00mm max] FBGA Unit: mm 0.800 x 12 = 9.600 0.700 ? 0.100 A1 INDEX MARK 0.800 11 10 9 8 7 6 5 4 3 2 1 DNU DNU DQ6 a DNU DQ6 a DNU DQ6 a DNU DQ6 a DQ6 a DQ6 a A VSSQ a VSSQ a VDDQ a VDDQ a VDDQ a VSSQ a VDDQ a VDDQ a VDDQ a VDDQ a VDDQ a B VDD1 a VDD1 a VDD2 a/b VDD2 a/b VDD2 a/b VDD1 a VDD2 a/b VDD2 a/b VDD2 a/b VDD2 a/b C DQ1 a DQ1 a VDDQ a VDDQ a VDDQ a DQ1 a VDDQ a VDDQ a VDDQ a VDDQ a D VSSQ a VSSQ a DQ0 a DQ0 a DQ0 a VSSQ a DQ0 a DQ0 a DQ0 a DQ0 a E DM2 a DM2 a VDDQ a VDDQ a VDDQ a DM2 a VDDQ a VDDQ a VDDQ a VDDQ a F DQS2_t a DQS2_t a DQS2_c a DQS2_c a DQS2_c a DQS2_t a DQS2_c a DQS2_c a DQS2_c a DQS2_c a G VSSQ a VSSQ a DQ23 a DQ23 a DQ23 a VSSQ a DQ23 a DQ23 a DQ23 a DQ23 a H VDDQ a VDDQ a DQ22 a DQ22 a DQ22 a VDDQ a DQ22 a DQ22 a DQ22 a DQ22 a J DQ20 a DQ20 a DQ21 a DQ21 a DQ21 a DQ20 a DQ21 a DQ21 a DQ21 a DQ21 a K DQ19 a DQ19 a VSSQ a VSSQ a VSSQ a DQ19 a VSSQ a VSSQ a VSSQ a VSSQ a L VDDQ a VDDQ a DQ18 a DQ18 a DQ18 a VDDQ a DQ18 a DQ18 a DQ18 a DQ18 a M DQ16 a DQ16 a DQ17 a DQ17 a DQ17 a DQ16 a DQ17 a DQ17 a DQ17 a DQ17 a VDD2 b VDD2 b VDD1 b VDD1 b VDD1 b VDD2 b VDD1 b VDD1 b VDD1 b VDD1 b N VSS b VSS b CA0 b CA0 b CA0 b VSS b CA0 b CA0 b CA0 b CA0 b R VDDCA b VDDCA b VDDCA b CA1 b CA1 b CA1 b VDDCA b CA1 b CA1 b CA1 b CA1 b CA1 b T Vref (CA) b Vref (CA) b CA2 b CA2 b CA2 b CA2 b Vref (CA) b CA2 b CA2 b CA2 b CA2 b CA2 b U 11.500 ± 0.100 DNU VSSQ a 0.650 x 16 = 10.400 12 0.650 13 0.550 ± 0.100 P 11.000 ± 0.100 178 x Ø 0.300± 0.050 (Post Reflow Ø 0.320± 0.050) A Bottom View B 0.220 ± 0.050 C 0.930 ± 0.070 Ø 0.15 M Vref (CA) b Vref (CA) b CA2 b CA2 b CA2 b Vref (CA) b CA2 b CA2 b CA2 b CA2 b CA2 b CA2 b SEATING PLANE C 0.10 Front View 7 C Package Block Diagrams Single Rank, Single Channel Package Block Diagram VDD1 VDD2 VDDQ VDDCA VSS VSSM VREFCA VREFDQ ZQ CS0# RZQ CKE0 CK LPDDR3 CK# Die 0 DM CA[9:0] DQ[31:0], DQS ODT 8 1. Electrical Conditions • All voltages are referenced to VSS (GND) • Execute power-up and Initialization sequence before proper device operation is achieved. • Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the DDR3 Mobile RAM Device must be powered down and then restarted through the specialized initialization sequence before normal operation can continue. 1.1 Absolute Maximum Ratings Table 1: Absolute Maximum Ratings Parameter Symbol min max Unit Note VDD1 supply voltage relative to VSS VDD1 0.4 2.3 V 2 VDD2 supply voltage relative to VSS VDD2 0.4 1.6 V 2 VDDCA supply voltage relative to VSSCA VDDCA 0.4 1.6 V 2, 3 VDDQ supply voltage relative to VSSQ VDDQ 0.4 1.6 V 2, 4 Voltage on any ball relative to VSS VIN, VOUT 0.4 1.6 V Storage Temperature TSTG 55 125 Notes: 1. 2. 3. 4. 5. Caution: 1.2 C 5 Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. See Power-Ramp section “Power-up, initialization and Power-Off” in the ”DDR3 Mobile RAM General Functionality and Electrical Condition” specification for relationship between power supplies. VREFCA 0.6 VDDCA; however, VREFCA may be VDDCA provided that VREFCA 300mV. VREFDQ 0.7 VDDQ; however, VREFDQ may be VDDQ provided that VREFDQ 300mV. Storage Temperature is the case surface temperature on the center/top side of the DDR3 Mobile RAM Device. For the measurement conditions, please refer to JESD51-2 standard. Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions Table 2: Recommended DC Operating Conditions (Tj= 30 C to +85 C) Parameter Symbol min typ max Unit Core Power1 VDD1 1.70 1.80 1.95 V Core Power2 VDD2 1.14 1.20 1.30 V Input Buffer Power VDDCA 1.14 1.20 1.30 V I/O Buffer Power VDDQ 1.14 1.20 1.30 V 9 2. 2.1 Electrical Specifications DC Characteristics 1 Table 3: IDD Specification Parameters and Operating Conditions (Tj = 30 C to +85 C, VDD1 = 1.70V to 1.95V, VDD2, VDDCA, VDDQ = 1.14V to 1.30V) Power Supply 1600 1333 Symbol max max IDD0_1 VDD1 6.0 6.0 mA IDD0_2 VDD2 30 30 mA IDD0_IN VDDCA VDDQ 6.0 6.0 mA IDD2P_1 VDD1 0.4 0.4 mA IDD2P_2 VDD2 0.9 0.9 mA IDD2P_IN VDDCA VDDQ 0.1 0.1 mA IDD2PS_1 VDD1 0.4 0.4 mA IDD2PS_2 VDD2 0.9 0.9 mA IDD2PS_IN VDDCA VDDQ 0.1 0.1 mA IDD2N_1 VDD1 0.4 0.4 mA IDD2N_2 VDD2 11.5 11 mA IDD2N_IN VDDCA VDDQ 6.0 6.0 mA IDD2NS_1 VDD1 0.4 0.4 mA IDD2NS_2 VDD2 9.5 9.5 mA IDD2NS_IN VDDCA VDDQ 6.0 6.0 mA IDD3P_1 VDD1 0.7 0.7 mA IDD3P_2 VDD2 5.0 5.0 mA IDD3P_IN VDDCA VDDQ 0.1 0.1 mA IDD3PS_1 VDD1 0.7 0.7 mA IDD3PS_2 VDD2 5.0 5.0 mA IDD3PS_IN VDDCA VDDQ 0.1 0.1 mA IDD3N_1 VDD1 1.0 1.0 mA IDD3N_2 VDD2 12.5 12 mA IDD3N_IN VDDCA VDDQ 6.0 6.0 mA Unit Parameter/Condition Operating one bank active-precharge current Conditions for operating devices are tCK = tCK(avg)min; tRC = tRCmin; CKE is HIGH; CS_n is HIGH between valid commands; CA bus inputs are SWITCHING; Data bus inputs are STABLE; ODT disabled Idle power-down standby current tCK = tCK(avg)min; CKE is LOW; CS_n is HIGH; All banks idle; CA bus inputs are SWITCHING; Data bus inputs are STABLE; ODT disabled Idle power-down standby current with clock stop CK_t = LOW, CK_c = HIGH; CKE is LOW; CS_n is HIGH; All banks idle; CA bus inputs are STABLE; Data bus inputs are STABLE; ODT disabled Idle non power-down standby current tCK = tCK(avg)min; CKE is HIGH; CS_n is HIGH; All banks idle; CA bus inputs are SWITCHING; Data bus inputs are STABLE; ODT disabled Idle non power-down standby current with clock stop CK_t = LOW, CK_c = HIGH; CKE is HIGH; CS_n is HIGH; All banks idle; CA bus inputs are STABLE; Data bus inputs are STABLE; ODT disabled Active power-down standby current tCK = tCK(avg)min; CKE is LOW; CS_n is HIGH; One bank active; CA bus inputs are SWITCHING; Data bus inputs are STABLE; ODT disabled Active power-down standby current with clock stop CK_t = LOW, CK_c = HIGH; CKE is LOW; CS_n is HIGH; One bank active; CA bus inputs are STABLE; Data bus inputs are STABLE; ODT disabled Active non power-down standby current tCK = tCK(avg)min; CKE is HIGH; CS_n is HIGH; One bank active; CA bus inputs are SWITCHING; Data bus inputs are STABLE; ODT disabled 10 Table 3: IDD Specification Parameters and Operating Conditions (Tj = 30 C to +85 C, VDD1 = 1.70V to 1.95V, VDD2, VDDCA, VDDQ = 1.14V to 1.30V) (cont’d) Power Supply 1600 1333 Symbol max max Unit Parameter/Condition IDD3NS_1 VDD1 1.0 1.0 mA IDD3NS_2 VDD2 10.5 10.5 mA IDD3NS_IN VDDCA VDDQ 6.0 6.0 mA IDD4R_1 VDD1 2.0 2.0 mA IDD4R_2 VDD2 200 175 mA IDD4R_IN VDDCA 6.0 6.0 mA IDD4W_1 VDD1 2.0 2.0 mA IDD4W_2 VDD2 190 165 mA IDD4W_IN VDDCA VDDQ 6.0 6.0 mA IDD5_1 VDD1 20 20 mA IDD5_2 VDD2 100 100 mA IDD5_IN VDDCA VDDQ 6.0 6.0 mA IDD5AB_1 VDD1 2.0 2.0 mA IDD5AB_2 VDD2 12 11.5 mA IDD5AB_IN VDDCA VDDQ 6.0 6.0 mA IDD5PB_1 VDD1 2.0 2.0 mA IDD5PB_2 VDD2 12 11.5 mA IDD5PB_IN VDDCA VDDQ 6.0 6.0 mA IDD8_1 VDD1 16 16 A IDD8_2 VDD2 6.0 6.0 A IDD8_IN VDDCA VDDQ 12 12 A Notes: 1. 2. Active non power-down standby current with clock stop CK_t = LOW, CK_c = HIGH; CKE is HIGH; CS_n is HIGH; One bank active; CA bus inputs are STABLE; Data bus inputs are STABLE; ODT disabled Operating burst read current tCK = tCK(avg)min; CS_n is HIGH between valid commands; One bank active; BL = 8; RL = RLmin; CA bus inputs are SWITCHING; 50% data change each burst transfer; Values in parenthesis are for ×16 bits; ODT disabled Operating burst write current tCK = tCK(avg)min; CS_n is HIGH between valid commands; One bank active; BL = 8; WL = WLmin; CA bus inputs are SWITCHING; 50% data change each burst transfer; Values in parenthesis are for ×16 bits; ODT disabled All bank auto refresh burst current tCK = tCK(avg)min; CKE is HIGH between valid commands; tRC = tRFCabmin; Burst refresh; CA bus inputs are SWITCHING; Data bus inputs are STABLE; ODT disabled All bank auto refresh average current tCK = tCK(avg)min; CKE is HIGH between valid commands; tRC = tREFI; CA bus inputs are SWITCHING; Data bus inputs are STABLE; ODT disabled Per bank auto refresh average current tCK = tCK(avg)min; CKE is HIGH between valid commands; tRC = tREFIpb; CA bus inputs are SWITCHING; Data bus inputs are STABLE; ODT disabled Deep power-down current CK_t = LOW, CK _c = HIGH; CKE is LOW; CA bus inputs are STABLE; Data bus inputs are STABLE; ODT disabled IDD values published are the maximum of the distribution of the arithmetic mean. IDD current specifications are tested after the device is properly initialized. 11 Table 4: IDD6 Full and Partial Array Self-Refresh Current (Tj = 30 C to +85 C, VDD1 = 1.70V to 1.95V, VDD2, VDDCA, VDDQ = 1.14V to 1.30V) Parameter Full Array 1/2 Array Self-Refresh Current +45 C 1/4 Array 1/8 Array Full Array 1/2 Array Self-Refresh Current +85 C 1/4 Array 1/8 Array Note: 1. 2.2 Symbol Value Unit IDD6_1 200 A IDD6_2 800 A IDD6_IN 10 A IDD6_1 160 A IDD6_2 500 A IDD6_IN 10 A IDD6_1 130 A IDD6_2 300 A IDD6_IN 10 A IDD6_1 120 A IDD6_2 200 A IDD6_IN 10 A IDD6_1 900 A IDD6_2 3200 A IDD6_IN 12 A IDD6_1 650 A IDD6_2 2200 A IDD6_IN 12 A IDD6_1 550 A IDD6_2 1700 A IDD6_IN 12 A IDD6_1 500 A IDD6_2 1400 A IDD6_IN 12 A Condition CK_t = LOW, CK_c = HIGH; CKE is LOW; CA bus inputs are STABLE; Data bus inputs are STABLE; ODT disabled IDD6 85 C is the maximum and IDD6 45 C is typical of the distribution of the arithmetic mean. DC Characteristics 2 Table 5: Electrical Characteristics and Operating Conditions (Tj = 30 C to +85 C, VDD1 = 1.70V to 1.95V, VDD2, VDDCA, VDDQ = 1.14V to 1.30V) Symbol min max Unit Parameter/Condition Note 2 1 IL 2 +2 A Input leakage current: For CA, CKE, CS_n, CK_t, CK_c Any input 0V VIN VDDCA (All other pins not under test = 0V) IVREF 1 +1 A VREF supply leakage current: VREFDQ = VDDQ/2 or VREFCA = VDDCA/2 (All other pins not under test = 0V) Notes: 1. 2. The minimum limit requirement is for testing purposes. The leakage current on VREFCA and VREFDQ pins should be minimal. Although DM is for input only, the DM leakage shall match the DQ and DQS_t, DQS_c output leakage specification. Please refer to the DDR3 Mobile RAM General Functionality and Electrical Condition data sheet (E1853E) for details. 12 2.3 AC Characteristics Table 6: AC Characteristics Table*3 *5 *9 (Tj = 30 C to +85 C, VDD1 = 1.70V to 1.95V, VDD2, VDDCA, VDDQ = 1.14V to 1.30V) Parameter Symbol min max Max. frequency min tCK*8 1600 1333 Unit 800 667 MHz 1.50 ns Clock Timing Average clock period tCK(avg) min 1.25 max 100 min 0.45 max 0.55 min 0.45 max 0.55 ns Average high pulse width tCH(avg) tCK(avg) Average low pulse width tCL(avg) Absolute clock period tCK(abs) min tCK(avg)min + tJIT(per)min Absolute clock high pulse width (with allowed jitter) tCH(abs), allowed min 0.43 max 0.57 Absolute clock low pulse width (with allowed jitter) tCL(abs), allowed min 0.43 max 0.57 Clock period jitter (with allowed jitter) tJIT(per), allowed min 70 80 max 70 80 Maximum clock jitter between two consecutive clock cycles (with allowed jitter) tJIT(cc), allowed max 140 160 Duty cycle jitter (with allowed jitter) tJIT(duty), allowed tCK(avg) tCK(avg) tCK(avg) min min((tCH(abs)min tCH(avg)min), (tCL(abs)min tCL(avg)min)) tCK(avg) max max((tCH(abs)max tCH(avg)max), (tCL(abs)max tCL(avg)max)) tCK(avg) Cumulative error across 2 cycles tERR(2per), allowed min 103 118 max 103 118 Cumulative error across 3 cycles tERR(3per), allowed min 122 140 max 122 140 Cumulative error across 4 cycles tERR(4per), allowed min 136 155 max 136 155 Cumulative error across 5 cycles tERR(5per), allowed min 147 168 max 147 168 Cumulative error across 6 cycles tERR(6per), allowed min 155 177 max 155 177 Cumulative error across 7 cycles tERR(7per), allowed min 163 186 max 163 186 Cumulative error across 8 cycles tERR(8per), allowed min 169 193 max 169 193 Cumulative error across 9 cycles tERR(9per), allowed min 175 200 max 175 200 Cumulative error across 10 cycles tERR(10per), min allowed max 180 205 180 205 Cumulative error across 11 cycles tERR(11per), min allowed max 184 210 184 210 Cumulative error across 12 cycles tERR(12per), min allowed max 188 215 188 215 13 ns ps ps ps ps ps ps ps ps ps ps ps ps ps ps Table 6: AC Characteristics Table*3 *5 *9 (Tj = 30 C to +85 C, VDD1 = 1.70V to 1.95V, VDD2, VDDCA, VDDQ = 1.14V to 1.30V) (cont’d) Parameter min max Symbol Cumulative error across n = 13, 14 . . . 19, 20 cycles tERR(nper), allowed min tCK* 8 1600 1333 min tERR(nper),allowed,min = (1 + 0.68ln(n)) tJIT(per),allowed,min max tERR(nper),allowed,max = (1 + 0.68ln(n)) tJIT(per),allowed,max min 2500 max 5500 Unit ps Read Parameters DQS output access time from CK_t, CK_c tDQSCK ps DQSCK delta short*15 tDQSCKDS max 220 265 ps DQSCK delta medium*16 tDQSCKDM max 511 593 ps DQSCK delta long* tDQSCKDL max 614 733 ps DQS – DQ skew tDQSQ max 135 165 ps DQS output high pulse width tQSH min tCH(abs) 0.05 DQS output low pulse width tQSL min tCL(abs) 0.05 DQ output hold time from DQS tQH min min (tQSH, tQSL) Read preamble*11, *12 tRPRE min 0.9 17 11, 13 Read postamble* * tCK(avg) tCK(avg) ps tCK(avg) tRPST min DQS low-Z from clock*11 tLZ(DQS) min tDQSCK(min) 300 ps DQ low-Z from clock* 11 tLZ(DQ) min tDQSCK(min) 300 ps DQS high-Z from clock*11 tHZ(DQS) max tDQSCK(max) 100 ps max tDQSCK(max) + (1.4 tDQSQ(max)) ps DQ high-Z from clock*11 tHZ(DQ) 0.3 tCK(avg) 10 Write Parameters* DQ and DM input hold time (VREF based) tDH min 150 175 ps DQ and DM input setup time (VREF based) tDS min 150 175 ps DQ and DM input pulse width tDIPW min 0.35 min 0.75 max 1.25 Write command to 1st DQS latching transition tDQSS tCK(avg) tCK(avg) DQS input high-level width tDQSH min 0.4 tCK(avg) DQS input low-level width tDQSL min 0.4 tCK(avg) DQS falling edge to CK setup time tDSS min 0.2 tCK(avg) DQS falling edge hold time from CK tDSH min 0.2 tCK(avg) Write postamble tWPST min 0.4 tCK(avg) Write preamble tWPRE min 0.8 tCK(avg) CKE Input Parameters CKE min. pulse width (high and low pulse width) tCKE CKE input setup time min tISCKE*1 min 2 CKE input hold time tIHCKE* min Command path disable delay tCPDED min 3 2 7.5 ns 0.25 tCK(avg) 0.25 tCK(avg) 2 tCK(avg) Command Address Input Parameters*10 Address and control input setup time tISCA min 150 175 ps Address and control input hold time tIHCA min 150 175 ps CS_n input setup time tISCS min 270 290 ps CS_n input hold time tIHCS min 270 290 ps Address and control input pulse width tIPWCA min 0.35 tCK(avg) CS_n input pulse width tIPWCS min 0.7 tCK(avg) 14 Table 6: AC Characteristics Table*3 *5 *9 (Tj = 30 C to +85 C, VDD1 = 1.70V to 1.95V, VDD2, VDDCA, VDDQ = 1.14V to 1.30V) (cont’d) Parameter Symbol min max min tCK* 8 1600 1333 Unit Boot Parameters (10 MHz – 55 MHz)*4, *6, *7 Clock cycle time tCKb max 100 min 18 ns CKE input setup time tISCKEb min 2.5 ns CKE input hold time tIHCKEb min 2.5 ns Address & control input setup time tISb min 1150 ps Address & control input hold time tIHb min 1150 ps min 2.0 max 10 1.2 ns DQS output data access time from CK_t, CK_c tDQSCKb Data strobe edge to output data edge tDQSQb max Mode register write command period (MRW command to MRW command interval) tMRW min 10 10 tCK(avg) Mode register set command delay (MRW command to non-MRW command interval) tMRD min 10 14 ns Mode register read command period tMRR min 4 4 tCK(avg) Additional time after tXP has expired until MRR tMRRI command may be issued min ns Mode Register Parameters tRCD (min) ns DDR3 Mobile RAM Core Parameters Read latency RL min 3 12 10 tCK(avg) Write latency (Set A) WL min 1 6 6 tCK(avg) Write latency (Set B) WL min 1 9 8 tCK(avg) ACTIVATE to ACTIVATE command period tRC min CKE min. pulse width during self-refresh (low pulse width during self-refresh) tCKESR min tRAS + tRPab (with all-bank Precharge) tRAS + tRPpb (with per-bank Precharge) ns 3 15 ns Self-refresh exit to next valid command delay tXSR min 2 tRFCab + 10 ns Exit power-down to next valid command delay tXP min 2 7.5 ns CAS to CAS delay tCCD min 4 4 Internal read to precharge command delay tRTP min 4 7.5 ns RAS to CAS delay tRCD min 3 18 ns Row precharge time (single bank) tRPpb min 3 18 ns Row precharge time (all banks) tRPab min 3 21 ns min 3 42 ns Row active time tRAS Write recovery time tWR min Internal write to read command delay tWTR Active bank A to active bank B tRRD Four bank activate window Minimum deep power-down time tCK(avg) 70 s 3 15 ns min 4 7.5 ns min 2 10 ns tFAW min 8 50 ns tDPD min 500 s max 15 Table 6: AC Characteristics Table*3 *5 *9 (Tj = 30 C to +85 C, VDD1 = 1.70V to 1.95V, VDD2, VDDCA, VDDQ = 1.14V to 1.30V) (cont’d) Symbol min max DQS output access time from CK_t, CK_c (derated) tDQSCK max 5620 ps RAS to CAS delay (derated) tRCD min tRCD + 1.875 ns ACTIVATE to ACTIVATE command period (derated) tRC min tRC + 1.875 ns Row active time (derated) tRAS min tRAS + 1.875 ns Row precharge time (derated) tRP min tRP + 1.875 ns Active bank A to active bank B (derated) tRRD min tRRD + 1.875 ns ms Parameter min tCK* 8 1600 1333 Unit Temperature Derating DDR3 Mobile RAM Refresh Requirement Parameters Refresh window tREFW max 32 Required number of REFRESH commands R min 8192 Average time between REFRESH commands (for reference only) tREFI max 3.9 s tREFIpb max 0.4875 s Refresh cycle time tRFCab min 130 ns Per bank refresh cycle time tRFCpb min 60 ns Burst refresh window = 4 8 tRFCab tREFBW min 4.16 s Initialization calibration time tZQINIT min Long calibration time tZQCL min 6 360 ns Short calibration time tZQCS min 6 90 ns Calibration reset time tZQRESET min 3 50 ns First DQS_t, DQS_c edge after write leveling mode is programmed*14 tWLMRD min 40 ns DQS_t, DQS_c delay after write leveling mode is programmed*14 tWLDQSEN min 25 ns Write leveling output delay tWLO min 0 ns max 20 ns ZQ Calibration Parameters 1 s Write Leveling Timings Write leveling hold time tWLH min 175 205 ps Write leveling setup time tWLS min 175 205 ps First CA calibration command after CA calibration mode is programmed tCAMRD min 20 tCK(avg) First CA calibration command after CKE is low tCAENT min 10 tCK(avg) CA calibration exit command after CKE is high tCAEXT min 10 tCK(avg) CKE low after CA calibration mode is programmed tCACKEL min 10 tCK(avg) CKE high after the last CA calibration results are tCACKEH driven min 10 tCK(avg) Data out delay after CA training calibration command is programmed tADR max 20 ns MRW CA exit command to DQ tristate tMRZ min 3 ns CA calibration command to CA calibration command delay tCACD min RU (tADR/tCK) + 2 CA Training Timing parameters 16 tCK(avg) Table 6: AC Characteristics Table*3 *5 *9 (Tj = 30 C to +85 C, VDD1 = 1.70V to 1.95V, VDD2, VDDCA, VDDQ = 1.14V to 1.30V) (cont’d) Parameter Symbol min max min tCK* 8 1600 1333 Unit ODT Parameters Asynchronous RTT turn-on delay from ODT input tODTon Asynchronous RTT turn-off delay from ODT input tODToff min 1.75 ns max 3.5 ns min 1.75 ns max 3.5 ns tDQSCK(max) + 1.4 tDQSQ(max) + tCK(avg, min) ps Automatic RTT turn-on delay after READ data tAODTon max Automatic RTT turn-off delay prior to READ data tAODToff min RTT disable delay from power-down, self-refresh and deep power-down entry tODTd max 12 ns RTT enable delay from power-down and self-refresh exit tODTe max 12 ns 17 tDQSCK(min) 300 ps Notes: 1. 2. 3. 4. CKE input setup time is measured from CKE reaching high/low voltage level to CK_t, CK_c crossing. CKE input hold time is measured from CK_t, CK_c crossing to CKE reaching high/low voltage level. Frequency values are for reference only. Clock cycle time (tCK or tCKb) shall be used to determine device capabilities. To guarantee device operation before the DDR3 Mobile RAM Device is configured a number of AC boot timing parameters are defined in the Table 6 on page 10. Boot parameter symbols have the letter b appended, e.g. tCK during boot is tCKb. 5. Measured with 4V/ns differential CK_t/CK_c slew rate and nominal VIX (differential input cross point voltage). 6. The DDR3 Mobile RAM will set some Mode register default values upon receiving a RESET (MRW) command as specified in Section 3 Mode Register Definition on page 17. 7. The output skew parameters are measured with Ron default settings into the reference load. 8. These parameters should be satisfied with both specification, analog (ns) value and min. tCK. 9. All AC timings assume an input slew rate of 2V/ns. 10. Read, Write, and Input setup and hold values are referenced to VREF. 11. For low-to-high and high-to-low transitions the timing reference will be at the point when the signal crosses VTT. tHZ and tLZ transitions occur in the same access time (with respect to clock) as valid data transitions. These parameters are not referenced to a specific voltage level but to the time when the device output is no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ) ), or begins driving (for tRPRE, tLZ(DQS), tLZ(DQ) ). Figure 1 shows a method to calculate the point when device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. ÊÑØ ÊÌÌ õ î¨ Ç ³Ê î¨ È È ÊÑØ – È ³Ê ÊÑØ – î¨ È ³Ê ¬ÔÆøÜÏÍ÷ô ¬ÔÆøÜÏ÷ ÊÌÌ õ Ç ³Ê ÊÌÌ î¨ Ç ÊÌÌ – Ç ³Ê ÊÌÌ – î¨ Ç ³Ê Ìï Ìî ÊÌÌ ¬ØÆøÜÏÍ÷ô ¬ØÆøÜÏ÷ Ç ¿½¬«¿´ ©¿ª»º±®³ ÊÑÔ õ î¨ È ³Ê ÊÑÔ õ È ³Ê ÊÑÔ ¾»¹·² ¼®·ª·²¹ °±·²¬ ã î I Ìï – Ìî Ìï Ìî -¬±° ¼®·ª·²¹ °±·²¬ ã î I Ìï – Ìî Figure 1: tLZ and tHZ Method for Calculating Transition and Endpoints 12. 13. 14. 15. 16. 17. The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing parameters tRPRE and tRPST are determined from the differential signal DQS_t – DQS_c. Measured from the start driving of DQS_t – DQS_c to the start driving the first rising strobe edge. Measured from the start driving the last falling strobe edge to the stop driving DQS_t – DQS_c. The max values are system dependent. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a contiguous sequence of bursts in a 160ns rolling window. tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is < 10 C/s. Values do not include clock jitter. tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a 1.6 s rolling window. tDQSCKDM is not tested and is guaranteed by design. Temperature drift in the system is < 10 C/s. Values do not include clock jitter. tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a 32ms rolling window. tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is < 10 C/s. Values do not include clock jitter. 18 2.3.1 HSUL_12 Driver Output Timing Reference Load These ‘Timing Reference Loads’ are not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. ÊÎÛÚ ðòë ¨ ÊÜÜÏ ÜÜÎí Ó±¾·´» ÎßÓ ÎÌÌ ã ëð Ñ«¬°«¬ ÊÌÌ ã ðòë ¨ ÊÜÜÏ Ý´±¿¼ ã ë°Ú Figure 2: HSUL_12 Driver Output Reference Load for Timing and Slew Rate Note: 1. All output timing parameter values (like tDQSCK, tDQSQ, tHZ, tRPRE etc) are reported with respect to this reference load. This reference load is also used to report slew rate. 19 3. Mode Register Definition Table 7 shows the mode registers for DDR3 Mobile RAM. Each register is denoted as “R” if it can be read but not written and “W” if it can be written but not read. Mode Register Read command shall be used to read a register. Mode Register Write command shall be used to write a register. Table 7: Mode Register Assignment MR# MA Function Access OP7 OP6 OP5 0 00H Device Info. R RL3 WL (Set B) Support (RFU) 1 01H Device Feature 1 W OP4 OP2 RZQI nWR (for AP) Write Leveling OP3 OP1 (RFU) (RFU) (RFU) OP0 Link DAI MR#0 BL nWRE MR#1 RL & WL MR#2 DS MR#3 2 02H Device Feature 2 W 3 03H I/O Config-1 W 4 04H Refresh Rate R 5 05H Basic Config-1 R Manufacturer ID MR#5 6 06H Basic Config-2 R Revision ID1 (Die Revision) MR#6 7 07H Basic Config-3 R Revision ID2 (RFU) MR#7 8 08H Basic Config-4 R 9 09H Test Mode W Vendor-Specific Test Mode 10 0AH IO Calibration W Calibration Code ODT Feature WL Select (RFU) TUF (RFU) I/O width Refresh Rate Density Type MR#8 MR#10 PD control (RFU) DQ ODT MR#11 11 0BH 12:15 0CH~0FH (Reserved) 16 10H PASR_Bank W Bank Mask MR#16 17 11H PASR_Seg W Segment Mask MR#17 18:31 12H~1FH (Reserved) 32 20H 33:39 21H~27H (Do Not Use) 40 28H 41 DQ Calibration Pattern A W MR#4 (RFU) (RFU) R See “DQ Calibration”. MR#32 DQ Calibration Pattern B R See “DQ Calibration”. MR#40 29H CA Training mode 1 entry W 1 0 1 0 0 1 0 0 42 2AH CA Training mode exit W 1 0 1 0 1 0 0 0 43:47 2BH~2FH (Do Not Use) 0 0 0 0 CA Training mode 2 entry 48 30H 49:62 31H~3EH (Reserved) 63 3FH 64:126 40H~7EH (Reserved) 127 7FH Reset (RFU) W 1 1 BFH X (RFU) (Do Not Use) (RFU) (Do Not Use) 192:254 C0H~FEH (Reserved) 255 FFH 0 (RFU) W 128:190 80H~BEH (Reserved) 191 0 (RFU) (Do Not Use) 20 MR#63 Notes: 1. 2. 3. 4. 5. RFU bits shall be set to ‘0’ during Mode Register writes. RFU bits shall be read as ‘0’ during Mode Register reads. All Mode Registers that are specified as RFU or write-only shall return undefined data when read and DQS_t, DQS_c shall be toggled. All Mode Registers that are specified as RFU shall not be written. Writes to read-only registers shall have no impact on the functionality of the device. 21 MR#0_Device Information (MA = 00H): Read-only OP7 OP6 OP5 RL3 WL (Set B) Support (RFU) OP4 OP3 RZQI OP DAI (Device Auto-Initialization Status) 0B: DAI complete 1B: DAI still in progress OP RZQI (Built in Self Test for RZQ Information) 01B: ZQ-pin may connect to VDDCA or float 10B: ZQ-pin may short to GND 11B: ZQ-pin self test completed, no error condition detected (ZQ-pin may not connect to VDDCA or float nor short to GND) OP WL (Set B) Support 1B: DRAM supports WL (Set B) OP RL3 Support 1B: DRAM supports RL = 3, nWR = 3, WL = 1 for frequencies Notes: 1. 2. 3. 4. OP2 OP1 (RFU) OP0 DAI 166MHz RZQI will be set upon completion of the MRW ZQ Initialization Calibration command. If ZQ is connected to VDDCA to set default calibration, OP[4:3] shall be set to 01. If ZQ is not connected to VDDCA, either OP[4:3]=01 or OP[4:3]=10 might indicate a ZQ-pin assembly error. It is recommended that the assembly error is corrected. In the case of possible assembly error (either OP[4:3]=01 or OP[4:3]=10 per Note 2), the DDR3 Mobile RAM device will default to factory trim settings for RON, and will ignore ZQ calibration commands. In either case, the system may not function as intended. In the case of the ZQ self-test returning a value of 11b, this result indicates that the device has detected a resistor connection to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or that the ZQ resistor 1%). tolerance meets the specified limits (i.e. 240 22 MR#1_Device Feature 1 (MA = 01H): Write-only OP7 OP6 OP5 OP4 nWR (for AP) OP BL 011B: BL8 All others: Reserved OP If nWRE (in MR#2 OP) = 0 001B: nWR = 3 100B: nWR = 6 110B: nWR = 8 111B: nWR = 9 else (if nWRE (in MR#2 OP) = 1) 000B: nWR = 10 (default) 001B: nWR = 11 010B: nWR = 12 100B: nWR = 14 110B: nWR = 16 All others: Reserved Notes: 1. 2. OP3 OP2 OP1 (RFU) OP0 BL Programmed value in nWR register is the number of clock cycles which determines when to start internal precharge operation for a write burst with AP enabled. It is determined by RU(tWR/tCK). The range of nWR is extended using an extra bit (nWRE) in MR#2. Table 8: Burst Sequence by BL, BT and WC Burst Cycle Number and Burst Address Sequence C2 C1 C0 WC BT BL 1 2 3 4 5 6 7 8 0B 0B 0B Wrap Seq 8 0 1 2 3 4 5 6 7 0B 1B 0B 2 3 4 5 6 7 0 1 1B 0B 0B 4 5 6 7 0 1 2 3 6 7 0 1 2 3 4 5 1B 1B 0B 2. The burst address represents C2 C0. Others Any Any Notes: 1. Illegal (Not allowed) C0 input is not present on CA bus. It is implied zero. - 23 MR#2_Device Feature 2 (MA = 02H): Write-only OP7 OP6 OP5 OP4 Write Leveling WL Select (RFU) nWRE OP OP3 OP2 OP1 OP0 RL & WL RL & WL If OP = 0 (WL Set A, default) 0001B: RL = 3/ WL = 1 ( 166MHz) * 1 0100B: RL = 6 / WL = 3 ( 400MHz) 0110B: RL = 8 / WL = 4 ( 533MHz) 0111B: RL = 9 / WL = 5 ( 600MHz) 1000B: RL = 10 / WL = 6 ( 667MHz, default) 1001B: RL = 11 / WL = 6 ( 733MHz) 1010B: RL = 12 / WL = 6 ( 800MHz) 1100B: RL = 14 / WL = 8 ( 933MHz) 1110B: RL = 16 / WL = 8 ( 1066MHz) All others: Reserved If OP = 1(WL Set B *1) 0001B: RL = 3/ WL = 1 ( 166MHz) * 1 0100B: RL = 6 / WL = 3 ( 400MHz) 0110B: RL = 8 / WL = 4 ( 533MHz) 0111B: RL = 9 / WL = 5 ( 600MHz) 1000B: RL = 10 / WL = 8 ( 667MHz, default) 1001B: RL = 11 / WL = 9 ( 733MHz) 1010B: RL = 12 / WL = 9 ( 800MHz) 1100B: RL = 14 / WL = 11 ( 933MHz) 1110B: RL = 16 / WL = 13 ( 1066MHz) All others: Reserved OP nWRE 0B: Enable nWR programming 9 1B: Enable nWR programming > 9 (default) OP WL Select 0B: Select WL Set A (default) 1B: Select WL Set B *2 OP Write Leveling 0B: Write Leveling Mode disabled (default) 1B: Write Leveling Mode enabled Notes: 1. 2. See MR#0, OP See MR#0, OP Table 9: DDR3 Mobile RAM Read and Write Latency Data Rate [Mbps] 333 800 1066 1200 1333 1466 1600 tCK [ns] 6 2.5 1.875 1.67 1.5 1.36 1.25 RL 3 6 8 9 10 11 12 WL (Set A) 1 3 4 5 6 6 6 WL (Set B) 1 3 4 5 8 9 9 24 MR#3_I/O Configuration 1 (MA = 03H): Write-only OP7 OP6 OP5 OP4 OP3 OP2 (RFU) OP OP1 OP0 OP1 OP0 DS DS 0001B: 34.3 typical pull-down/pull-up 0010B: 40 typical pull-down/pull-up (default) 0011B: 48 typical pull-down/pull-up 0100B: Reserved 0110B: Reserved 1001B: 34.3 typical pull-down, 40 typical pull-up 1010B: 40 typical pull-down, 48 typical pull-up 1011B: 34.3 typical pull-down, 48 typical pull-up All others: Reserved MR#4_Device Temperature (MA = 04H): Read-only OP7 OP6 OP5 OP4 OP3 OP2 (RFU) TUF Refresh Rate OP Refresh Rate 000B: Low temperature operating limit exceeded 001B: 4 tREFI, 4 tREFIpb, 4 tREFW 010B: 2 tREFI, 2 tREFIpb, 2 tREFW 011B: 1 tREFI, 1 tREFIpb, 1 tREFW( +85 C) 100B: 0.5 tREFI, 0.5 tREFIpb, 0.5 tREFW 101B: 0.25 tREFI, 0.25 tREFIpb, 0.25 tREFW, do not de-rate AC timing 110B: 0.25 tREFI, 0.25 tREFIpb, 0.25 tREFW, de-rate AC timing 111B: High temperature operating limit exceeded OP TUF(Temperature Update Flag) 0B: OP value has not changed since last read of MR#4. 1B: OP value has changed since last read of MR#4. Notes: 1. 2. 3. 4. 5. 6. A Mode Register Read from MR#4 will reset OP7 to ‘0’. OP7 is reset to ‘0’ at power-up. OP bits are undefined after power-up. If OP2 equals ‘1’, the device temperature is greater than 85 C. OP7 is set to “1” if OP2:OP0 has changed at any time since the last read of MR#4. DDR3 Mobile RAM will drive OP to ‘0’. Specified operating temperature range and maximum operating temperature are refer to Section 1 Electrical Conditions on page 6. If maximum temperature is 85 C, functionality for over 85 C is not guaranteed. MR#5_Basic Configuration 1 (MA = 05H): Read-only OP7 OP6 OP5 OP4 OP3 Manufacturer ID OP Manufacturer ID 00000011B 00000101B 25 OP2 OP1 OP0 MR#6_Basic Configuration 2 (MA = 06H): Read-only OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 OP2 OP1 OP0 OP2 OP1 Revision ID1 (Die Revision) OP Revision ID1 (Die Revision) 00000010B: C-version Revision ID1 (Die Revision) 00000000B: A-version MR#7_Basic Configuration 3 (MA = 07H): Read-only OP7 OP6 OP5 OP4 OP3 Revision ID2 (RFU) OP Revision ID2 (RFU) MR#8_Basic Configuration 4 (MA = 08H): Read-only OP7 OP6 OP5 OP4 I/O width OP3 Density OP Type 11B: S8 OP Density 0110B: 4G OP I/O width 00B: 32 01B: 16 OP0 Type MR#10_Calibration (MA = 0AH): Write-only OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Calibration Code OP Notes: 1. 2. 3. Calibration Code FF: Calibration command after initialization AB: Long calibration 56: Short calibration C3: ZQ Reset others: Reserved Host processor shall not write MR#10 with “Reserved” values. DDR3 Mobile RAM Devices shall ignore calibration command when a “Reserved” value is written into MR#10. See AC timing table for the calibration latency. 26 MR#11_ODT Feature (MA = 0BH): Write-only OP7 OP6 OP5 OP4 OP3 OP2 OP1 PD Control (RFU) OP DQ ODT 00B : Disabled (default) 01B : RZQ/4 10B : RZQ/2 11B : RZQ/1 OP PD Control (Power-down Control) 0B: ODT disabled by DRAM during power-down (default) 1B: ODT enabled by DRAM during power-down OP0 DQ ODT MR#16_PASR_Bank Mask (MA = 10H): Write-only OP7 OP6 OP5 OP4 OP3 OP2 OP1 Bank Mask OP Bank Mask 0B: refresh enable to the bank (=unmasked, default) 1B: refresh blocked (=masked) Bank and OP corresponding table OP Note: 1. Bank Bank # Bank Address OP0 Bank 0 000B OP1 Bank 1 001B OP2 Bank 2 010B OP3 Bank 3 011B OP4 Bank 4 100B OP5 Bank 5 101B OP6 Bank 6 110B OP7 Bank 7 111B Each bank can be masked independently by setting each OP value. 27 OP0 MR#17_PASR_Segment Mask (MA = 11H): Write-only OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Segment Mask OP Segment Mask 0B: refresh enable to the segment (=unmasked, default) 1B: refresh blocked (=masked) Segment and OP corresponding table OP Note: 1. Segment Segment # Row Address (R13:11) OP0 Segment 0 000B OP1 Segment 1 001B OP2 Segment 2 010B OP3 Segment 3 011B OP4 Segment 4 100B OP5 Segment 5 101B OP6 Segment 6 110B OP7 Segment 7 111B Each segment can be masked independently by setting each OP value. MR#32_DQ Calibration Pattern A (MA = 20H): Reads to MR#32 return DQ Calibration Pattern “A”. MR#40_DQ Calibration Pattern B (MA = 28H): Reads to MR#40 return DQ Calibration Pattern “B”. MR#63_Reset (MA = 3FH): MRW only OP7 OP6 OP5 OP4 OP3 X Note: 1. For additional information on MRW RESET. 28 OP2 OP1 OP0