RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
178ball FBGASpecification
16Gb LPDDR3 (x32)
1
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Document Title
FBGA
16Gb (x32) LPDDR3
Revision History
Revision No.
0.1
History
- Initial Draft
2
Draft Date
Remark
May. 2019
Preliminary
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
FEATURES
[ FBGA ]
● OperationTemperature
- -25oC ~85oC
● Package
- 178-ballFBGA
- 11.0x11.5mm2, 1.00t, 0.65mm pitch
- Lead & HalogenFree
[ LPDDR3 ]
• VDD1 = 1.8V (1.7V to1.95V)
• VDD2, VDDCA and VDDQ = 1.2V (1.14V to1.30)
• HSUL_12 interface (High Speed Unterminated Logic1.2V)
• Doubledataratearchitectureforcommand,addressanddataBus;
- allcontrolandaddressexceptCS_n,CKElatchedatbothrisingandfallingedgeoftheclock
- CS_n,CKElatchedatrisingedgeoftheclock
- twodataaccessesperclockcycle
• Differential clock inputs (CK_t,CK_c)
• Bi-directional differential data strobe (DQS_t,DQS_c)
- Sourcesynchronousdatatransactionalignedtobi-directionaldifferentialdatastrobe(DQS_t,DQS_c)
- Dataoutputsalignedtotheedgeofthedatastrobe(DQS_t,DQS_c)whenREADoperation
- Datainputsalignedtothecenterofthedatastrobe(DQS_t,DQS_c)whenWRITEoperation
• DMmaskswritedataatthebothrisingandfallingedgeofthedatastrobe
• Programmable RL (Read Latency) and WL (WriteLatency)
• Programmable burst length:8
• Auto refresh and self refreshsupported
• All bankautorefreshandperbankautorefreshsupported
• AutoTCSR(TemperatureCompensatedSelfRefresh)
• PASR(PartialArraySelfRefresh)byBankMaskandSegmentMask
• DS (DriveStrength)
• ZQ(Calibration)
• ODT (On DieTermination)
3
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Functional Block Diagram
CA0 ~ CA9
DM0~DM3, DQS0_t~DQS3_t, DQS0_c~DQS3_c
CS1_n
CKE1
CS0_n
CKE0
DQ0~DQ31
8Gb x32 device
(256M x 32)
CK_t, CK_c
ZQ, ODT
8Gb x32 device
(256M x 32)
VDD1, VDD2, VDDCA, VDDQ, Vref(CA/DQ)
VSS, VSSCA, VSSQ
Note
1. Totalcurrentconsumptionisdependenttouseroperatingconditions.ACandDCCharacteristicsshownin
thisspecificationarebasedonasingledie.Seethesectionof“DCParametersandOperatingConditions”
4
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
ORDERING INFORMATION
Part Number
RS512M32LD3D2LMZ-125BT
Memory
Operation
Combination
Voltage
LPDDR3
1.8V/1.2/1.2/1.2
5
Density
16Gb(x 32)
Speed
DDR3 1600
Package
178Ball FBGA
(Lead & Halogen Free)
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Ball ASSIGNMENT
1
2
A
B
VSS
3
4
5
6
7
8
9
10 11 1213
VDD1 VDD1VDD1 VDD1
VDD2 VDD2 VDD1 VDDQ
A
ZQ
DQ31 DQ30 DQ29 DQ28VSSQ
B
NC VSS VSSQ
C
D
CA9 VSSCA NC
CA8 VSSCA VDD2 VDD2 VDD2
DQ27 DQ26 DQ25 DQ24 VDDQ
DM3 DQ15 D _t 3 D_c3VSSQ
QS
QS
C
D
E
CA7
VDDQ DQ14 DQ13DQ12VDDQ
E
DQ11 DQ10 DQ9 DQ8 VSSQ
F
G
CA6
VSS VSSQ
VSS VSS VSSQ
F
G
VDDCA CA5 VSSCA
H
VDDQ VDDQ VSSQ VDDQVDD2
H
J
VSS VDDCA Vref VDD2 VDD2
(CA
)
CK_c CK_t
AVDD2 VDD2
ODT VDDQ VDDQ(DQ) VSS
Vref
J
K
VSS
VDDQ
K
VSS VSSQ
VDDCA VSSCA VSSCA VDD2 VSSQ
DM1
VSSC
CKE
NC VDD2VDD2
L
VDDCA CS_n
NC VDD2 VSS
M
VDDCA CA4
VSSCA VSS VSSQ
VSSQ D 1 D
VDDQ
_t
_cS1
QS
Q
NC
VSSQVDDQVDD2
DM0 VSSQ D _t
_c VDDQ
0D
QS
QS0
L
DQ4
DQ5
DQ6 DQ7VSSQ
M
VDDQ DQ1
DQ2 DQ3VDDQ
N
P
N
P
CA2
CA1 VSSCA VDD2VDD2 VDD2
DM2
R
CA0
DQ20 DQ21 DQ22DQ23VDDQ
R
DQ16 DQ17 DQ18 DQ19 VSSQ
T
T
VSS
U
CA3
NC
VSS
VSS VSS VSSQ
VSS VSS VSSQ
VSS VSS VSSQ
VDD1VDD1 VDD1 VDD1
1
2
3
4
5
DQ0 D_t 2 D_c2VSSQ
QS
QS
VDD2 VDD2 VDD1 VDDQ
6
7
8
9
LPDDR3
Commend/Address
LPDDR3 DataIO
Power(VDD1,VDD2,V
DDCA, VDDQ,VREF)
Ground (VSS,VSSC
A,V SSQ)
U
10 11 12 13
TopView
178ball x
32 LPDDR3
Note
1.1. J8 will be used as “ODT”. Users who don’t use ODT Function can assign J8 as VSSQ.
2. Insidethechip,VDDCAandVDD2aretied.F2,G2,H3,L2andM2arenotconnectedtothechip.Itfully
guaranteesDRAMoperationeventhereisaVDDCAinputvoltage.
6
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Pin Description
SYMBOL
DESCRIPTION
Type
CS0
Chip Select
Input
CK_c, CK_t
Differential Clocks
Input
CKE0
Clock Enable
Input
CA0 ~ CA9
Command / Address
Input
DQ0 ~ DQ31
Data I/O
Input/Output
DM0 ~ DM3
Input Data Mask
Input/Output
DQS0_t ~ DQS3_t
Differential Data Strobe (rising edge)
Input/Output
DQS0_c ~ DQS3_c
Differential Data Strobe (falling edge)
Input/Output
ZQ
Drive Strength Calibration
Input/Output
VDD1
Core Power Supply
Power
VDD2
Core Power Supply
Power
VSS
Ground
Ground
Power
VDDQ
I/O Power Supply
VDDCA
CA Power Supply
Power
VSSCA
CA Ground
Ground
VSSQ
I/O Ground
Ground
VREF
Reference Voltage
Power
ODT
On Die Termination Enable
Input
Input/Output Capacitance
Parameter
Input capacitance, CK_t and CK_c
Symbol
CCK
Min
1.5
Max
3.0
Unit
pF
Input capacitance, all other input-only pins
CI
0.5
3.0
pF
Input/output capacitance, DQ, DM, DQS_t, DQS_c
Input/Output Capacitance ZQ
CIO
CZQ
2.0
1.5
3.5
3.0
pF
pF
(TOPER; VDDQ = 1.14-1.3V; VDDCA = 1.14-1.3V; VDD1 = 1.7-1.95V, VDD2 = 1.14-1.3V)
Note:
1. This parameter applies to both die andpackage.
2. Thisparameteris notsubjecttoproductiontest.It isverifiedbydesignandcharacterization.Thecapacitanceismeasured according
to JEP147 (Procedure for measuring input capacitance using a vector network analyzer (VNA) with VDD1, VDD2, VDDQ,
VSS, VSSCA, VSSQ applied and all other pinsfloating).
3. CI applies to CS_n, CKE,CA0-CA9.
4. DM loading matches DQ andDQS.
5. MR3 I/O configuration DS OP3-OP0 = 0001B (34.3Ohm typical)
6. MaximumexternalloadcapacitanceonZQ pin,includingpackaging,board,pin,resistor,andotherLPDDR3devices:5pF.
7
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
PACKAGE INFORMATION
178 Ball 0.65mm pitch 11.0mm x 11.5mm [t = 1.00mm max] FBGA
Unit: mm
0.800 x 12 = 9.600
0.700±0.100
A1 INDEXMARK
0.800
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
0
0
0
4
.
1
=
6
1
x
0
5
6
.
0
G
H
100
.
0
J
±
0
0
5
.
1
1
K
L
M0
5
6
.
N0
P
R
T
U
11.000±0.100
178xØ0.300±0.050
(PostReflowØ0.320±0.050)
Ø0.15 M
C
A B
0
070 .0
5
.0 0
±±
0 0
3 22
.9
0 0.
BottomView
0
0
1
0
.
0±
5
5
0.
SEATING PLANE
C
0.10 C
Front View
8
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
8Gb LPDDR3 SDRAM
9
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Input/Output Functional Description
SYMBOL
CK_t, CK_c
TYPE
DESCRIPTION
Clock: CK_t and CK_c are differential clock inputs. All Double Data Rate (DDR) CA inputs
are sampled on both positive and negative edge of CK_t. Single Data Rate (SDR) inputs,
Input CS_n and CKE, are sampled at the positive Clock edge.
Clock is defined as the differential pair, CK_t and CK_c. The positive Clock edge is defined
bythecrosspointofarisingCK_tandafallingCK_c.ThenegativeClockedgeisdefinedby
the
crosspoint of a falling CK_t and a risingCK_c.
CKE
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and
Input therefore device input buffers and output drivers. Power savings modes are entered and
exited through CKE transitions.
CKE is considered part of the command code. CKE is sampled at the positive Clock edge.
CS_n
Input
CA0 - CA9
DQ0 - DQ15(x16)
DQ0 - DQ31(x32)
DQS0_t,
DQS1_t,
DQS0_c,
DQS1_c
(x16)
DQS0_t - DQS3_t,
DQS0_c - DQS3_c
(x32)
DM0-DM1 (x16)
DM0-DM3 (x32)
Chip Select: CS_n is considered part of the command code.CS_n is sampled at the posi-
tive Clock edge.
DDR Command/Address Inputs: Uni-directional command/address bus inputs. CA is
Input
considered part of the command code.
I/O
Data Input/Output: Bi-directional data bus
Data Strobe (Bi-directional, Differential): The data strobe is bi-directional (used for
read and write data) and differential (DQS_t and DQS_c). It is output with read data and
input with write data. DQS_t is edge-aligned to read data and centered with write data.
For x16, DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7; DQS1_t and DQS1_c
to the data on DQ8 - DQ15.
I/O For x32 DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7, DQS1_t and DQS1_c
tothedataonDQ8-DQ15,DQS2_tandDQS2_ctothedataonDQ16-DQ23,DQS3_tand DQS3_c to
the data on DQ24 -DQ31.
InputDataMask:DMistheinputmasksignalforwritedata.Inputdataismaskedwhen
DMissampledHIGHcoincidentwiththatinputdataduringaWriteaccess.DMissampled
onbothedgesofDQS_t.AlthoughDMisforinputonly,theDMloadingshallmatchtheDQ
and
Input DQS_t (orDQS_c).
For x16 and x32 devices, DM0 is the input data mask signal for the data on DQ0-7. DM1 is
the input data mask signal for the data on DQ8-15.
Forx32devices,DM2istheinputdatamasksignalforthedataonDQ16-23andDM3isthe input data
mask signal for the data onDQ24-31.
On-Die Termination: This signal enables and disables termination on the DRAM DQ bus
ODT
Input
VDD1
Supply Core Power Supply 1
VDD2
Supply Core Power Supply 2
VDDCA
Supply
VDDQ
VREFCA
VREFDQ
VSS
VSSCA
VSSQ
ZQ
according to the specified mode register settings.
Input Receiver Power Supply: Power for CA0-9, CKE, CS_n, CK_t and CK_c input buf-
fers.
Supply I/O Power Supply: Power supply for data input/output buffers.
ReferenceVoltageforCACommandandControlInputReceiver:Referencevoltage
Supply
for all CA0-9, CKE, CS_n, CK_t and CK_c input buffers.
Supply ReferenceVoltageforDQInputReceiver:ReferencevoltageforallDatainputbuffers.
Supply Ground
Supply Ground for Input Receivers
Supply I/O Ground: Ground for data input/output buffers
I/O Reference Pin for Output Drive Strength Calibration
10
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Functional Description
LPDDR3-SDRAM is a high-speed synchronous DRAM device internally configured as an 8-bank memory.
These devices contain the following number of bits:
8 Gb has 8,589,934,592 bits
LPDDR3devicesuseadoubledataratearchitectureontheCommand/Address(CA)bustoreducethenumberofinput
pinsinthesystem.The10-bitCAbuscontainscommand,address,andbankinformation.Eachcommandusesoneclock
cycle,duringwhichcommandinformationistransferredonboththepositiveandnegativeedgeoftheclock.
ThesedevicesalsouseadoubledataratearchitectureontheDQpinstoachievehighspeedoperation.Thedoubledata
ratearchitectureisessentiallyan8nprefetcharchitecturewithaninterfacedesignedtotransfertwodatabitsperDQ
everyclockcycleattheI/Opins.AsinglereadorwriteaccessfortheLPDDR3SDRAMeffectivelyconsistsofasingle 8nbitwide,oneclockcycledatatransferattheinternalDRAMcoreandeightcorrespondingn-bitwide,one-half-clock- cycle data
transfers at the I/Opins.
ReadandwriteaccessestotheLPDDR3SDRAMsareburstoriented;accessesstartataselectedlocationandcontinue
foraprogrammednumberoflocationsinaprogrammedsequence.AccessesbeginwiththeregistrationofanActivate
command,whichisthenfollowedbyaReadorWritecommand.TheaddressandBAbitsregisteredcoincidentwiththe
Activatecommandareusedtoselecttherowandthebanktobeaccessed.Theaddressbitsregisteredcoincidentwith
theReadorWritecommandareusedtoselectthebankandthestartingcolumnlocationfortheburstaccess.
Priortonormaloperation,theLPDDR3SDRAMmustbeinitialized.Thefollowingsectionprovidesdetailedinformation
coveringdeviceinitialization,registerdefinition,commanddescriptionanddeviceoperation.
LPDDR3 SDRAM Addressing
Density
Number of Banks
Bank Addresses
tREFI(us)2
x16
x32
8Gb
8
BA0 - BA2
3.9
Row Addresses
Column Addresses1
Row Addresses
Column Addresses1
R0 - R14
C0 - C10
R0 - R14
C0 - C9
Note:
1. Theleast-significantcolumnaddressC0isnottransmittedontheCAbus,andisimpliedtobezero.
2. tREFI values for all bank refresh is Tc = 0 ~ 85 °
C, Tc means Operating CaseTemperature.
3. Row and Column Address values on the CA bus which are not used are “don’tcare”.
4. NomemorypresentataddresseswithR13=R14=HIGH.ACTcommandwithR13=R14=HIGHisignored(NOP).Writeto
R13=R14=HIGH is ignored(NOP).
11
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
STATE DIAGRAM
Power
Applied
Resetting
MR
Reading
Power
On
RESET
MRR
Self
Refreshing
Resetting
SREF
PD
PDX
Resetting
Power
Down
SREFX
RESET
REF
Idle1
MRW
MR
Writing
Refreshing
PD
MRR
Idle
MR
Reading
PR,PRA
Active
Power
Down
PDX
Idle
Power
Down
ACT
MRR
PDX
Automatic
Active
MR
Reading
SequenceCommand
Sequence
PD
Active*1
RD
WR
Write
RD
Reading
Writing
WRA
RDA
WRA
Writing
with
Autoprecharge
RDA
PR,PRA
Reading
with
Autoprecharge
Precharging
PR(A) = Precharge (All)
PD = Enter Power Down
ACT = Activate
PDX = Exit Power Down
WR(A) = Write (with Autoprecharge)
SREF = Enter Self Refresh
RD(A) = Read (with Autoprecharge)
SREFX = Exit Self Refresh
REF = Refresh
RESET=ResetisachievedthroughMRWcommand
MRW=ModeRegisterWrite
MRR = Mode Register Read
12
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Note:
1. In the Idle state, all banks areprecharged.
2. In the case of MRW to enter CA Training mode or Write Leveling Mode, the state machine will not automatically return to the Idle
state.InthesecasesanadditionalMRWcommandisrequiredtoexiteitheroperatingmodeandreturntotheIdlestate.Seesections
"CA
Training"or "WriteLeveling".
3. Terminated bursts are not allowed. For these state transitions, the burst operation must be completed before the transition can
occur.
4. Use caution with this diagram. It is intended to provide a floorplan of the possible state transitions and commands to control them,
not all details. In particular, situations involving more than one bank are not capturediSn full detail.
13
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Power-up, Initialization and Power-off
Voltage Ramp and Device Initialization
The following sequence must be used to power up the device. Unless specified otherwise, this procedure is mandatory.
1. Voltage Ramp
Whileapplyingpower(afterTa),CKEmustbeheldLOW(≤0.2×VDDCA),andallotherinputsmustbebetween
VILmin
andVIHmax.Thedevice outputsremainatHigh-ZwhileCKEisheldLOW.
Followingthecompletionofthevoltageramp(Tb),CKEmustbemaintainedLOW.DQ,DM,DQS_tandDQS_cvoltage
levelsmustbebetweenVSSQandVDDQduringvoltageramptoavoidlatchup.CK_t,CK_c,CS_n,andCAinputlevels
mustbebetweenVSSCAandVDDCAduringvoltageramptoavoidlatch-up.Voltageramppowersupplyrequirements
are
provided in the table “Voltage RampConditions”.
After...
Ta is reached
Table.VoltageRampConditions
Applicable Conditions
VDD1 must be greater than VDD2-200mV.
VDD1 and VDD2 must be greater than VDDCA-200mV.
VDD1 and VDD2 must be greater than VDDQ-200mV.
VREF must always be less than all other supply voltages.
Note:
1. Ta is the point when any power supply firstreaches 300mV.
2. Noted conditions apply between Ta and power-off (controlledor uncontrolled).
3. Tb is the point at which all supply and reference voltages are within their defined operatingranges.
4. Power ramp duration tINIT0 (Tb - Ta) must not exceed20ms.
5. The voltage difference between any of VSS, VSSQ, and VSSCA pins must not exceed100mV.
BeginningatTb,CKEmustremainLOWforatleasttINIT1,afterwhichCKEcanbeassertedHIGH.Theclockmustbe
stableatleasttINIT2priortothefirstCKELOW-to-HIGHtransition(Tc).CKE,CS_n,andCAinputsmustobservesetup
andholdrequirements(tIS,tIH)withrespecttothefirstrisingclockedge(aswellastosubsequentfallingandrising edges).
IfanyMRRcommandsareissued,theclockperiodmustbewithintherangedefinedfortCKb.MRWcommandscanbe
issuedatnormalclockfrequenciesaslongasallACtimingsaremet.SomeACparameters(forexample,tDQSCK)
c
ould have relaxed timings (such as t DQSCKb) before the system is appropriately configured. While keeping CKE
HIGH,NOPcommandsmustbeissuedforatleasttINIT3(Td).TheODTinputsignalmaybeinundefinedstateuntilt
ISbeforeCKEisregisteredHIGH.WhenCKEisregisteredHIGH,theODTinputsignalshallbestaticallyheldateither
LOWorHIGH.TheODTinputsignalremainsstaticuntilthepowerupinitializationsequenceisfinished,includingthe expiration
oftZQINIT.
2. ResetCommand
After tINIT3 is satisfied, the MRW RESET command must be issued (Td).
AnoptionalPRECHARGEALLcommandcanbeissuedpriortotheMRWRESETcommand.WaitatleasttINIT4while
keepingCKEassertedandissuingNOPcommands.OnlyNOPcommandsareallowedduringtimetINIT4.
14
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
3. MRRs and Device Auto Initialization (DAI)Polling
AftertINIT4issatisfied(Te),onlyMRRcommandsandpower-downentry/exitcommandsaresupported.AfterTe,CKE
cangoLOWinalignmentwithpower-downentryandexitspecifications.MRRcommandsareonlyvalidatthistimeif the CA bus
does not need to be trained. may only begin after time Tf. User may issue MRR command to poll the DAI
bitwhichwillindicateifdeviceautoinitializationiscomplete;onceDAIbitindicatescompletion,SDRAMisinidlestate.
DevicewillalsobeinidlestateaftertINIT5(max)hasexpired(whetherornotDAIbithasbeenreadbyMRRcommand).
AsthememoryoutputbuffersarenotproperlyconfiguredbyTe,someACparametersmusthaverelaxedtimingsbefore the
system is appropriatelyconfigured.
4. ZQCalibration
IfCATrainingisnotrequired,theMRWinitializationcalibration(ZQ_CAL)commandcanbeissuedtothememory
(
MR10) after time Tf. If CA Training is required, the CA Training may begin at time Tf. See the section of "Mode
Regis- ter Write - CA Training Mode" for the CA Training command. No other CA commands (other than RESET or
NOP) may beissuedpriortothecompletionofCATraining.AtthecompletionofCATraining(Tf'),theMRWinitializationcalibra-t
ion(ZQ_CAL)commandcanbe issuedtothememory(MR10).
Thiscommandisusedtocalibrateoutputimpedanceoverprocess,voltage,andtemperature.Insystemswheremore
thanoneLPDDR3deviceexistsonthesamebus,thecontrollermustnotoverlapMRWZQ_CALcommands.Thedevice
is
readyfornormaloperationaftertZQINIT.
5. NormalOperation
AftertZQINIT(Tg),MRWcommandsmustbeusedtoproperlyconfigurethememory(forexampletheoutputbuffer
drivestrength,latencies,etc.).Specifically,MR1,MR2,andMR3mustbesettoconfigurethememoryforthetargetf requency
and memoryconfiguration.
Aftertheinitializationsequenceiscomplete,thedeviceisreadyforanyvalidcommand.AfterTg,theclockfrequency
canbechangedusingtheproceduredescribedintheLPDDR3specification.
Table. Timing Parameters for initialization
Symbol
tINIT0
tINIT1
tINIT2
tINIT3
tINIT4
tINIT5
tZQINIT
tCKb
Parameter
Maximum Voltage Ramp Time
Minimum CKE low time after completion of voltage ramp
Minimum stable clock before first CKE high
Minimum idle time after first CKE assertion
Minimum idle time after Reset command
Maximum duration of Device Auto-Initialization
ZQ Initial Calibration for LPDDR3 devices
Clock cycle time during boot
15
min
100
5
200
1
1
18
Value
max
20
10
100
Unit
ms
ns
tCK
us
us
us
us
ns
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Ta
Tb
Tc
Td
Te
Tf’
Tf
Tg
tINIT2 = 5 tCK (min)
CK_t / CK_c
tINIT0 = 20 ms (max)
Supplies
tINIT3 = 200 us (min)
tINIT1 = 100 ns (min)
CKE
PD
tINIT5
tISCKE
tZQINIT
tINIT4 = 1 us (min)
CA
CA*
RESET
MRR
Training
ZQC
DQ
tIS
ODT
Static HIGH or LOW
Valid
* Midlevel on CA bus means: valid NOP
Figure. Power Ramp and Initialization Sequence
Notes
1. High-Z on the CA bus indicatesNOP.
2. For tINIT values, see the table "Timing Parameters forInitialization".
3. After RESET command (time Te), RTT is disabled until ODT function is enabled by MRW to MR11following Tg.
4. CA Training isoptional.
16
Valid
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Initialization After Reset (without Power ramp)
IftheRESETcommandisissuedbeforeorafterthepower-upinitializationsequence,there-initializationproceduremust begin atTd.
Power-off Sequence
The following procedure is required to power off the device.
Whilepoweringoff,CKEmustbeheldLOW(≤0.2×VDDCA);allotherinputsmustbebetweenVILminandVIHmax.The
deviceoutputsremainatHigh-ZwhileCKEisheldLOW.
DQ,DM,DQS_t,andDQS_cvoltagelevelsmustbebetweenVSSQandVDDQduringthepower-offsequencetoavoidlatchup.CK_t,CK_c,CS_n,andCAinputlevelsmustbebetweenVSSCAandVDDCAduringthepower-offsequence
to avoid latch-up.
Tx is the point where any power supply drops below the minimum value specified.
Tz is the point where all power supplies are below 300mV. After Tz, the device is powered off (see the table “Power Supply
Conditions”).
Table. Power Supply Conditions
Between...
Tx and Tz
Applicable Conditions
VDD1 must be greater than VDD2—200mV
VDD1 must be greater than VDDCA—200mV
VDD1 must be greater than VDDQ—200mV
VREF must always be less than all other supply voltages
The voltage difference between any of VSS, VSSQ, and VSSCA pins must not exceed 100mV.
Uncontrolled Power-Off Sequence
When an uncontrolled power-off occurs, the following conditions must be met:
AtTx,whenthepowersupplydropsbelowtheminimumvaluesspecified,allpowersuppliesmustbeturnedoffandall powersupplycurrentcapacitymustbeatzero,exceptforanystaticchargeremaininginthesystem.
AfterTz(thepointatwhichallpowersuppliesfirstreach300mV),thedevicemustpoweroff.ThetimebetweenTxa
ndTzmustnotexceed10ms.Duringthisperiod,therelativevoltagebetweenpowersuppliesisuncontrolled.VDD1a
ndVDD2mustdecreasewithaslopelowerthan0.5V/μsbetweenTxandTz.
An uncontrolled power-off sequence can occur a maximum of 400 times over the life of the device.
Table. Power-Off Timing
Symbol
tPOFF
Parameter
Maximum power-off ramp time
17
Value
min
max
2
Unit
sec
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Mode Register Definition
TablebelowshowsthemoderegistersforLPDDR3SDRAM.Eachregisterisdenotedas“R”ifitcanbereadbutnotw
ritten,“W”ifitcanbewrittenbutnotread,and“R/W”ifitcanbereadandwritten.AModeRegisterReadcommands
hallbeusedtoreadamoderegister.AModeRegisterWritecommandshallbeusedtowriteamoderegister.
Table. Mode Register Assignment
MR
#
MA
Function
0
00H
Device Info.
R
1
01H
Device Feature1
W
2
02H
Device Feature 2
W
3
03H
W
4
04H
R
TUF
5
6
7
8
9
05H
06H
07H
08H
09H
I/O Config-1
Device Temperature
Basic Config-1
Basic Config-2
Basic Config-3
Basic Config-4
Test Mode
WL
RZQI
(RFU)
setB
(Optional)
nWR (for AP)
(RFU) BT
WR
WL
(RFU) nWRE
Lev Select
(RFU)
10
0AH
Calibration
W
11
0BH
ODT
W
16
10H
PASR_Bank
W
17
11H
PASR_Segment
W
32
20H
40
28H
41
29H
42
2AH
48
63
DQ Calibration
Pattern A
DQ Calibration
Pattern B
CA TrainingEntry
for CA0-3,CA5-8
Access OP7
R
R
R
R
W
OP6
OP5
OP4
OP3
RL3
(RFU)
I/O width
OP2
OP1
(RFU)
OP0
Link
DAI
go to MR0
BL
go to MR1
RL & WL
go to MR2
DS
go to MR3
Refresh Rate
go to MR4
Manufacturer ID
Revision ID1
Revision ID2
Density
Vendor-Specific Test Mode
Type
go
go
go
go
go
Calibration Code
PD
CTL
(RFU)
DQ ODT
PASR Bank Mask
PASR Segment Mask
R
See the section “DQ Calibration”
R
See the section “DQ Calibration”
W
See the section “Mode Register Write - CA Training Mode”
CA Training Exit
W
See the section “Mode Register Write - CA Training Mode”
30H
CA Training Entry
for CA4, 9
W
See the section “Mode Register Write - CA Training Mode”
3FH
Reset
W
X
Note:
1. RFU bits shall be set to `0' during Mode Registerwrites.
2. RFU bits shall be read as `0' during ModeRegister reads.
3. AllModeRegistersthatarespecifiedas RFUor write-onlyshallreturnundefineddatawhen readandDQS_t,DQS_cshallbetog- gled.
4. All Mode Registers that are specified as RFU shall not bewritten.
5. Writestoread-onlyregistersshallhavenoimpactsonthefunctionalityofthedevice.
18
to MR5
to MR6
to MR7
to MR8
to MR9
go to
MR10
go to
MR11
go to
MR16
go to
MR17
go to
MR32
go to
MR40
go to
MR41
go to
MR42
go to
MR48
go to
MR63
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
MR0 Device Information (MA = 00H)
OP7
OP6
OP5
RL3
WL (Set B)
Support
(RFU)
OP4
RZQI (Optional)
DAI (Device Auto-Initialization Status)
Read-only
RZQI
(Built in Self Test for RZQ Information)
Read-only
WL (Set B) Support
OP3
Read-only
RL3 Option Support
Read-only
OP2
OP1
(RFU)
OP0
DAI
0B: DAI complete
1B: DAI still in progress
00B: RZQ self test not supported
01B: ZQ-pin may connect to VDDCA or
float 10B: ZQ-pin may short to GND
OP4:OP3
11B:ZQ-pinself testcompleted,noerrorcondition detected (ZQ-pin may not connect toVDD
or float nor short to GND)
0B: DRAM does not support WL (Set B)
OP
1B: DRAM supports WL (Set B)
0B : DRAM does not support
RL=3, nWR=3, WL=1
1B : DRAM supports
RL=3, nWR=3, WL=1
OP
for frequencies 9 (default)
0B : Select WL Set A (default)
1B : Select WL Set B (optional2)
0B : Disabled (default)
1B : Enabled
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
MR3 I/O Configuration 1 (MA = 03H)
OP7
OP6
OP5
OP4
OP3
OP2
(RFU)
OP1
OP0
DS
0000B: reserved
0001B: 34.3typical pull-down/pull-up
0010B: 40typical pull-down/pull-up (default)
0011B: 48typical pull-down/pull-up
DS
Write-only
OP
0100B: reserved for 60typical pull-down/pull-up
0110B: reserved for 80typical pull-down/pull-up
1001B: 34.3typical pull-down, 40Typical Pull-up (optional1)
1010B: 40typical pull-down, 48Typical Pull-up (optional1)
1011B: 34.3typical pull-down, 48Typical Pull-up (optional1)
All others: reserved
Note:
1. Please contact us, for the supportability of the optionalfeature.
22
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
MR4 Device Temperature (MA = 04H)
OP7
OP6
OP5
TUF
OP4
OP3
(RFU)
OP2
OP1
OP0
Refresh Rate
000B: Low temperature operating limit exceeded
001B: 4 x tREFI, 4 x tREFIpb, 4 x tREFW
010B: 2 x tREFI, 2 x tREFIpb, 2 x tREFW
Refresh Rate
Read-only
OP
Temperature
Update Flag
(TUF)
Read-only
OP
011B:
100B:
101B:
110B:
111B:
1 x tREFI, 1 x tREFIpb, 1 x tREFW (85C)
1/2 x tREFI, 1/2 x tREFIpb, 1/2 x tREFW, do not de-rate AC timing
1/4 x tREFI, 1/4 x tREFIpb, 1/4 x tREFW, do not de-rate AC timing
1/4 x tREFI, 1/4 x tREFIpb, 1/4 x tREFW, de-rate AC timing
High temperature operating limit exceeded
0B: OP value has not changed since last read of MR4
1B: OP value has changed since last read of MR4
Note:
1.A Mode Register Read from MR4 will reset OP7 to ‘0’.
2. OP7 is reset to ‘0’ atpower-up.
3. If OP2 equals ‘1', the device temperature is greaterthan 85oC.
4. OP7 is set to ‘1’ if OP2:OP0 has changed at any time since the last readof MR4.
5. LPDDR3mightnotoperateproperlywhenOP[2:0]=000Bor111B.
6. For specified operating temperature range and maximum operating temperature refer to the section of Operating Temperature
Range.
7. LPDDR3 devices shall be de-rated by adding derating values to the following core timing parameters: tRCD, tRC, tRAS, tRP and
tRRD.tDQSCKshallbede-ratedaccordingtothetDQSCKde-ratingin“ACtimingtable”.Prevailingclockfrequencyspecandrelated setup and
hold timings shall remainunchanged.
8. See the section of Temperature Sensor for information on the recommended frequencyof reading MR4.
23
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
MR5BasicConfiguration1(MA=05H)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
OP2
OP1
OP0
OP2
OP1
OP0
Manufacturer ID
Company ID
Read-only
OP 0000 0110B: Hynix Semiconductor
MR6BasicConfiguration2(MA=06H)
OP7
OP6
OP5
OP4
OP3
Revision ID 1
Revision ID1
Read-only
OP 00000011B
MR7BasicConfiguration3(MA=07H)
OP7
OP6
OP5
OP4
OP3
Revision ID 2
Revision ID2
Read-only
OP 00000000B: A-version
MR8BasicConfiguration4(MA=08H)
OP7
OP6
OP5
I/O width
OP4
OP3
OP2
Density
Type
Read-only
OP
Density
Read-only
OP
I/O width
Read-only
OP
24
OP1
OP0
Type
11B: S8
All Others : Reserved
0110B : 4Gb
0111B : 8Gb
1000B : 16Gb
All Others : Reserved
00B: x32
01B: x16
All Others : Reserved
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
MR9 Test Mode (MA = 09H)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
OP2
OP1
OP0
Vendor-specific Test Mode
MR10 Calibration (MA = 0AH)
OP7
OP6
OP5
OP4
OP3
Calibration Code
Calibration Code
Write Only
1111 1111B: Calibration command after initialization
1010 1011B: Long Calibration
OP 0101 0110B: Short Calibration
1100 0011B: ZQ Reset
others: reserved
Note:
1. Host processor shall not write MR10 with “Reserved”values
2. LPDDR3devicesshallignorecalibrationcommandwhena“Reserved”valueis writtenintoMR10.
3. See AC timing table for the calibrationlatency.
4. If ZQ is connected to VSSCA through RZQ, either the ZQ calibration function (see "Mode Register Write ZQ Calibration Command")
or default calibration (through the ZQRESET command) is supported. If ZQ is connected to VDDCA, the device operates with default
calibration, and ZQ calibration commands are ignored. In both cases, the ZQ connection shall not change after power is applied to
thedevice.
5. LPDDR3 devices that do not support calibration shall ignore theZQ Calibration command.
6. Optionally, the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pinconnection.
MR11 ODT (MA = 0BH)
OP7
OP6
OP5
OP4
OP3
OP2
PD
Control
(RFU)
DQ ODT
Write Only
OP
Power Down Control
Write Only
OP
OP1
OP0
DQ ODT
00B : Disable (Default)
01B : RZQ/4 (See the Note 1.)
10B : RZQ/2
11B : RZQ/1
0B : ODT disabled by DRAM during power down
1B : ODT enabled by DRAM during power down
Note:
1. RZQ/4 shall be supported for LPDDR3-1866 devices. RZQ/4 support is optional for LPDDR3-1333 and LPDDR3-1600 devices. Consult manufacturer specifications for RZQ/4 support for LPDDR3-1333 and LPDDR3-1600.
MR12:15 (Reserved) (MA = 0CH - 0FH)
25
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
MR16 PASR Bank Mask (MA = 10H)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Bank Mask
Bank Mask
Write-only
OP
0B : refresh enable to the bank (=unmasked, default)
1B : refresh blocked (=masked)
OP
0
1
2
3
4
5
6
7
Bank Mask
XXXXXXX1
XXXXXX1X
XXXXX1XX
XXXX1XXX
XXX1XXXX
XX1XXXXX
X1XXXXXX
1XXXXXXX
LPDDR3 SDRAM
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
MR17 PASR Segment Mask (MA = 11H)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Segment Mask
Segment
Mask
Write-only
OP
0B : refresh enable to the segment (=unmasked, default)
1B : refresh blocked (=masked)
Segment
OP
Segment Mask
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
XXXXXXX1
XXXXXX1X
XXXXX1XX
XXXX1XXX
XXX1XXXX
XX1XXXXX
X1XXXXXX
1XXXXXXX
4Gb
R13:11
6Gb2
R14:12
8Gb
R14:12
12Gb2
R14:12
16Gb
R14:12
000B
001B
010B
011B
100B
101B
110B
111B
Note:
1. This table indicates the range of row addresses in each masked segment. X is do not care for a particular segment.
26
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
MR18:31 (Reserved) (MA = 12H - 1FH)
MR32 DQ Calibration Pattern A (MA = 20H): MRR only
Reads to MR32 return DQ Calibration Pattern A. See the section of DQ Calibration.
MR33:39 (Reserved) (MA = 21H - 27H)
MR40 DQ Calibration Pattern B (MA = 28H): MRR only
Reads to MR40 return DQ Calibration Pattern B. See the section of DQ Calibration.
MR41 CA Calibration Mode Entry for CA0-3, CA5-8 (MA = 29H)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
OP3
OP2
OP1
OP0
A4
See the section of CA Calibration.
MR42 CA Calibration Mode Exit (MA = 2AH)
OP7
OP6
OP5
OP4
A8
See the section of CA Calibration.
MR43:47 (Reserved) (MA = 2BH - 2FH)
MR48 CA Calibration Mode Entry for CA4, 9 (MA = 30H)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
OP3
OP2
OP1
OP0
C0
See the section of CA Calibration.
MR49:62 (Reserved) (MA = 31H - 3EH)
MR63 Reset (MA = 3FH): MRW only
OP7
OP6
OP5
OP4
X or 0xFC
Note: For additional information on MRW RESET, see Mode Register Write Command section.
27
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
TRUTHTABLES
Operationortimingthatisnotspecifiedisillegalandaftersuchanevent,inordertoguaranteeproperoperation,the
LPDDR3devicemustbepowereddownandthenrestartedthroughthespecifiedinitializationsequencebeforenormal
operation cancontinue.
COMMAND TRUTH TABLE
SDR Command Pins (2)
CKE
Command
CK_t(n-1)
CK_t(n)
MRW
H
H
MRR
H
H
Refresh
(per bank)
H
H
Refresh
(all bank)
H
H
H
L
Active
(bank)
H
H
Write
(bank)
H
H
Read
(bank)
H
H
H
H
NOP
H
H
Maintain SREF, PD
(NOP)4
L
L
NOP
H
H
L
L
Enter Power
Down
H
L
Exit PD,
SREF
L
H
Enter Self
Refresh
Precharge
(perbank,
all bank)11
Maintain PD,
SREF
(NOP)4
CS_n
DDR CA Pins (10)
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CK_t
edg
e
L
L
L
L
L
MA0
MA1
MA2
MA3
MA4
MA5
rising
X
MA6
MA7
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
falling
L
H
MA0
MA1
MA2
MA3
MA4
MA5
L
L
L
X
MA6
MA7
L
L
L
X
H
L
X
X
L
L
rising
X
L
L
H
falling
H
X
X
rising
X
L
L
falling
H
X
X
rising
falling
rising
X
falling
L
L
H
R8
R9
R10
R11
R12
BA0
BA1
BA2
rising
X
R0
R1
R2
R3
R4
R5
R6
R7
R13
R14
falling
L
H
L
L
RFU
RFU
C1
C2
BA0
BA1
BA2
rising
X
AP3
C3
C4
C5
C6
C7
C8
C9
C10
C11
falling
L
H
L
H
RFU
RFU
C1
C2
BA0
BA1
BA2
rising
X
AP3
C3
C4
C5
C6
C7
C8
C9
C10
C11
falling
L
H
H
L
H
AB
X
X
BA0
BA1
BA2
rising
X
X
X
X
X
X
X
X
X
X
X
falling
L
H
H
H
X
X
X
X
H
H
H
rising
falling
X
rising
X
X
falling
H
X
rising
X
X
falling
X
X
rising
X
X
falling
H
X
rising
X
X
falling
H
X
rising
X
X
falling
Note:
1. All LPDDR3 commands are defined by states of CS_n, CA0, CA1, CA2, CA3, and CKE at the rising edge of theclock.
2. BankaddressesBA0,BA1,BA2(BA)determinewhichbankistobeoperatedupon.
3. AP"high"duringaREADor WRITEcommandindicatesthatanauto-prechargewill occurto thebankassociatedwiththeREADor
WRITEcommand.
4. "X" means "H or L (but a defined logic level)", except when the LPDDR3 SDRAM is in PD, or SREF, in which case CS_n, CK_t/CK_c,
and CA can be floated after the required tCPDED time is satisfied, and until the required exit procedure is initiated as described in
the respective entry/exitprocedure.
5. Self refresh exit isasynchronous.
6. VREF must be between 0 and VDDQ during Self Refreshoperation.
7. CAxr refers to command/address bit "x" on the rising edge ofclock.
8. CAxf refers to command/address bit "x" on the falling edge ofclock.
9. CS_n and CKE are sampled at the rising edge ofclock.
10. Theleast-significantcolumnaddressC0isnottransmittedon theCAbus,andis impliedtobezero.
11. AB"high"duringPrechargecommandindicatesthatallbankPrechargewill occur.Inthiscase,BankAddressisdo-not-care.
12. When CS_n is HIGH, LPDDR3 CA bus can befloated.
28
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
CKE TRUTH TABLE
Current State3
CKEn-1
4
CKEn
4
CS_n5
Active
Power Down
L
L
X
L
H
H
Idl
Power Down
L
L
X
L
H
H
Resetting
Power Down
L
L
X
L
L
L
H
L
H
H
X
H
H
L
H
H
L
H
H
L
L
H
L
H
H
H
Self Refresh
Bank(s) Active
All Banks Idle
Resetting
Command n6
Operationn6
Next State
Maintain
Active
X
Active Power Down
Powe Down
NOP
Exit Active Power Down
Active
Maintain
Idle
X
Idle Power Down
Power Down
NOP
Exit Idle Power Down
Idle
Maintain
Resetting
X
Resetting Power Down
Power Down
NOP
Exit Resetting Power Down Idle or Resetting
X
Maintain Self Refresh
Self Refresh
NOP
Exit Self Refresh
Idle
Enter
Active PowerNOP
Active Power Down
Down
Enter
Idle Power
NOP
Down
Idle Power Down
Enter
Enter
Self Refresh
Self Refresh
Self Refresh
Enter
Resetting
NOP
Resetting Power Down
Power Down
Refer to the Command Truth Table
Notes
7
7
7,9
8
11
Note:
1. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere inthis document.
2. 'X' means 'Don'tcare'.
3. "Currentstate"isthestateoftheLPDDR3deviceimmediatelypriortoclockedgen.
4. "CKEn" is the logic state of CKE at clock rising edge n; "CKEn-1" was the state of CKE at the previousclock edge.
5. "CS_n" is the logic state of CS_n at the clock rising edgen.
6. "Commandn"isthecommandregisteredatclockedgeN, and"Operationn"is aresultof"Commandn".
7. PowerDownexittime(tXP)shouldelapsebeforeacommandotherthanNOPis issued.Theclockmusttoggleatleast
twice during the tXP period.
8. Self-Refresh exit time (tXSR) should elapse before a command other than NOP is issued. The clock must toggle at least t
wice during the tXSRtime.
9. UponexitingResettingPowerDown,thedevicewillreturntotheIdlestateiftINIT5hasexpired.
10. Inthecaseof ODTdisabled,allDQoutputshallbeHi-Z.InthecaseofODTenabled,all DQshallbe terminatedto VDDQ.
30
29
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Current State Bank n - Command to Bank n
Current State
Command
Any
NOP
Activate
Refresh (Per Bank)
Refresh (All Bank)
MRW
MRR
Reset
Precharge
Read
Write
MRR
Precharge
Idle
Row Active
Reading
Read
Write
Writing
Write
Power On
Resetting
Read
Reset
MRR
Operation
Next State
Note
Continue previous operation
Current State
Select and activate row
Active
Begin to refresh
Refreshing (Per Bank)
6
Begin to refresh
Refreshing (All Bank)
7
Write value to Mode Register
MR Writing
7
Read value from Mode Register
Idle MR Reading
Begin Device Auto-Initialization
Resetting
8
Deactive row in bank or banks
Precharging
9, 12
Select Column, and start read burst
Reading
Select Column, and start write burst
Writing
Read value from Mode Register
Active MR Reading
Deactivate row in bank or banks
Precharging
9
Select column, and start new read
Reading
10,11
burst
Select column, and start write burst
Writing
10,11,13
Select Column, and start new write
Writing
10,11
burst
Select column, and start read burst
Reading
10,11,14
Begin Device Auto-Initialization
Resetting
7, 9
Read value from Mode Register
Resetting MR Reading
Note:
1. ThetableapplieswhenbothCKEn-1andCKEnareHIGH,andaftertXSRortXPhasbeenmetifthepreviousstatewasPowerDown.
2. All states and sequences not shown are illegal orreserved.
3. Current StateDefinitions:
Idle: The bank or banks have been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accesses
are in progress.
Reading: A READ burst has been initiated, with Auto Precharge disabled.
Writing: A WRITE burst has been initiated, with Auto Precharge disabled.
4. The following states must not be interrupted by a command issued to the same bank. NOP commands or allowable commands to
theotherbankshouldbeissuedonanyclock edgeoccurringduringthesestates.Allowablecommandstotheotherbanksaredeter- mined by its
current state and Table “Current State Bank n - Command to Bank n”, and according to Table “Current State Bank n - Command to
Bankm”.
Precharging:startswiththeregistrationofaPRECHARGEcommandandendswhentRPismet.OncetRPismet,thebankwill be in the
idlestate.
Row Activating: starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be
in the ‘Active’ state.
Read with AP Enabled: starts with the registration of the READ command with Auto Precharge enabled and ends when tRP has
been met. Once tRP has been met, the bank will be in the idle state.
Write with AP Enabled: starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank will be in the idle state.
5. Thefollowingstatesmustnotbeinterruptedbyanyexecutablecommand;NOPcommandsmustbe appliedto eachpositiveclock edge
during thesestates.
Refreshing(PerBank):startswithregistrationofaREFRESH(PerBank)commandandendswhentRFCpbismet.OncetRFCpbis met, the
bank will be in an ‘idle’state.
Refreshing (All Bank): starts with registration of a REFRESH(All Bank) command and ends when tRFCab is met. Once tRFCab is
met, the device will be in an ‘all banks idle’ state.
Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met,
the bank will be in the Idle state.
Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been
met, the bank will be in the Resetting state.
30
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met,
the bank will be in the Row Active state.
MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has been met, the
bank will be in the Idle state.
PrechargingAll:startswiththeregistrationofaPRECHARGEALLcommandandendswhentRPismet.OncetRPismet,thebank will be in the
idlestate.
6. Bank-specific; requires that the bank is idle and no bursts are inprogress.
7. Not bank-specific; requires that all banks are idle and no bursts are inprogress.
8. Not bank-specific reset command is achieved through MODE REGISTER WRITEcommand.
9. Thiscommandmayormaynotbebankspecific.Ifallbanks arebeingprecharged,theymustbein a validstateforprecharging.
10. AcommandotherthanNOPshouldnotbeissuedtothesamebankwhileaREADorWRITEburstwithAutoPrechargeisenabled.
11. The new Read or Write command could be Auto Precharge enabled or Auto Prechargedisabled.
12. If a Precharge command is issued to a bank in the Idle state, tRP shallstill apply.
13. A Write command may be applied after the completion of the Read burst, burst terminates arenot permitted.
14. A Read command may be applied after the completion of the Write burst, burst terminates arenot permitted.
31
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Current State Bank n - Command to Bank m
Current State of Commandfor
Bank n
Bank m
Any
Idle
NOP
Any
Activate
Row Activating,
Active,
or Precharging
Read
Write
Precharge
MRR
Reading
(Autoprecharge
disabled)
Writing
(Autoprecharge
disabled)
Read
Write
Activate
Precharge
Read
Write
Activate
Precharge
Read
Reading with
Autoprecharge
Write
Activate
Precharge
Read
Writing with
Autoprecharge
Power On
Resetting
Write
Activate
Precharge
Reset
MRR
Operation
Next State for Bank m
Note
Continue previous operation
Current State of Bank m
Any command allowed to Bank m
Select and activate row in Bank m
Active
6
Select column, and start read burst from Bank
Reading
7
m
Select column, and start write burst to Bank m
Writing
7
Deactivate row in bank or banks
Precharging
8
Idle MR Readingor
Read value from Mode Register
9,10,12
Active MRReading
Select column, and start read burst from Bank
Reading
7
m
Select column, and start write burst to Bank m
Writing
7,15
Select and activate row in Bank m
Active
Deactivate row in bank or banks
Precharging
8
Select column, and start read burst from Bank
Reading
7,16
m
Select column, and start write burst to Bank m
Writing
7
Select and activate row in Bank m
Active
Deactivate row in bank or banks
Precharging
8
Select column, and start read burst from Bank
Reading
7,13
m
Select column, and start write burst to Bank m
Writing
7,15,13
Select and activate row in Bank m
Active
Deactivate row in bank or banks
Precharging
8
Select column, and start read burst from Bank
Reading
7,13,16
m
Select column, and start write burst to Bank m
Writing
7,13
Select and activate row in Bank m
Active
Deactivate row in bank or banks
Precharging
8
Begin Device Auto-Initialization
Resetting
11, 14
Read value from Mode Register
Resetting MR Reading
Note:
1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh
or PowerDown.
2. All states and sequences not shown are illegal orreserved.
3. Current StateDefinitions:
Idle: the bank has been precharged, and tRP has been met.
Active: a row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in
progress.
Reading: a READ burst has been initiated, with Auto Precharge disabled.
Writing: a WRITE burst has been initiated, with Auto Precharge disabled.
4. REFRESH,SELFREFRESH,andMODEREGISTERWRITEcommandsmayonlybeissuedwhenall bankareidle.
5. Thefollowingstatesmustnotbeinterruptedbyanyexecutablecommand;NOPcommandsmustbeappliedduringeachclockcycle while in
thesestates:
Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met,
the bank will be in the Idle state.
Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been
met, the bank will be in the Resetting state.
Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met,
the bank will be in the Row Active state.
MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has been met, the
bank will be in the Idle state.
6. tRRDmustbemetbetweenActivatecommandtoBanknandasubsequentActivatecommandtoBankm.
32
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
7. READsorWRITEslistedintheCommandcolumnincludeREADsandWRITEswithAutoPrechargeenabledandREADsandWRITEs with Auto
Prechargedisabled.
8. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging.
9.MRRisallowedduringtheRowActivatingstateandMRWisprohibitedduringtheRowActivatingstate.(RowActivatingstartswith
registrationofanActivatecommandandendswhentRCDismet.)
10. MRRisallowedduringthePrechargingstate.(PrechargingstartswithregistrationofaPrechargecommandandendswhentRPis met.
11. Not bank-specific; requires that all banks are idle and no bursts are inprogress.
12. ThenextstateforBankmdependsonthecurrentstateofBankm(Idle,RowActivating,Precharging,orActive).Thereadershall note that the
state may be in transition when a MRR is issued. Therefore, if Bank m is in the Row Activating state and Precharging, the next
state may be Active and Precharge dependent upon tRCD andtRP respectively.
13. ReadwithautoprechargeenabledoraWritewithautoprechargeenabledmaybefollowedbyanyvalidcommandtootherbanks
provided
that the timing restrictions in the section of Precharge and Auto Precharge clarification arefollowed.
14. Reset command is achieved through MODE REGISTER WRITEcommand.
15. A Write command may be applied after the completion of the Read burst, burst terminates arenot permitted.
16. A Read command may be applied after the completionof the Write burst, burst terminates are not permitted.
33
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
DATA MASK TRUTH TABLE
Function
Write Enable
Write Inhibit
DM
L
H
Note:
1. Used to mask write data, provided coincident with the corresponding data.
34
DQ
Valid
X
Note
1
1
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Absolute Maximum DC Ratings
Stressesgreaterthanthoselistedmaycausepermanentdamagetothedevice.Thisisastressratingonly,andfunc-t
ionaloperationofthedeviceattheseoranyotherconditions
above
thoseindicatedintheoperationalsectionsofthis
specificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectreliability.
Parameter
VDD1 supply voltage relative to VSS
VDD2 supply voltage relative to VSS
VDDCA supply voltage relative to VSSCA
VDDQ supply voltage relative to VSSQ
Voltage on Any Pin relative to VSS
Storage Temperature
Symbol
VDD1
VDD2
VDDCA
VDDQ
VIN, VOUT
TSTG
Min
-0.4
-0.4
-0.4
-0.4
-0.4
-55
Max
2.3
1.6
1.6
1.6
1.6
125
Unit
V
V
V
V
V
Notes
1
1
1, 2
1, 3
oC
4
Note:
1. See the section “Power-up, Initialization, and Power-off” for relationships between powersupplies.
2. VREFCA0.6x VDDCA;however,VREFCAmaybeVDDCAprovidedthatVREFCA300mV.
3. VREFDQ0.7x VDDQ; however,VREFDQmaybe VDDQprovidedthatVREFDQ 300mV.
4. StorageTemperatureisthecase surfacetemperatureonthecenter/topsideof thedevice.Forthemeasurementconditions,please refer to
JESD51-2standard.
35
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
AC and DC Operating Conditions
Operationortimingthatisnotspecifiedisillegal,andaftersuchanevent,inordertoguaranteeproperoperation,the
LPDDR3Devicemustbepowereddownandthenrestartedthroughthespecializedinitializationsequencebeforenormal
operation cancontinue.
Recommended DC Operating Conditions
Parameter
Core Power 1
Core Power 2
Input Buffer Power
I/O Buffer Power
Symbol
VDD1
VDD2
VDDCA
VDDQ
Min
1.70
1.14
1.14
1.14
Typ
1.80
1.20
1.20
1.20
Max
1.95
1.30
1.30
1.30
Unit
V
V
V
V
Note :
1. VDD1 uses significantly less current thanVDD2.
2. ThevoltagerangeisforDCvoltageonly.DCisdefinedasthevoltagesuppliedattheDRAMandisinclusiveof allnoiseupto 1MHz
at the DRAM package ball.
Input Leakage Current
Parameter
Input Leakage current
VREF supply leakage current
Symbol
IL
IVREF
Min
-2
-1
Max
2
1
Unit
uA
uA
Note
2
1
Unit
Note
1
Note:
1. ForCA,CKE,CS_n,CK_t,CK_c.Anyinput0V VIN VDDCA(Allotherpinsnotundertest=0V)
2. Although DM is for input only, the DM leakage shall match the DQ and DQS_t/DQS_c outputleakage specification.
3. Theminimumlimitrequirementisfortestingpurposes.Theleakagecurrenton
VREFCAandVREFDQpinsshouldbeminimal.
4. VREFDQ = VDDQ/2 or VREFCA = VDDCA/2. (All other pins not under test= 0V)
Operating Temperature
Parameter
Operating Temperature
Standard
Symbol
TOPER
Min
-25
Max
85
oC
Note:
1.Operating Temperature is the case surface temperature on the center-top side of the LPDDR3 device. For the measurement conditions, please refer to JESD51-2 standard.
36
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
AC and DC Input Measurement Levels
AC and DC Logic Input Levels for Single-Ended CA and CS_n Signals
Parameter
LPDDR3 1600/1333
Min
Max
VREF + 0.150
Note 2
Note 2
VREF - 0.150
VREF + 0.100
VDDCA
VSSCA
VREF - 0.100
Symbol
AC Input Logic High
AC Input Logic Low
DC Input Logic High
DC Input Logic Low
VIHCA
VILCA
VIHCA
VILCA
Reference Voltage for
CA and CS_n Inputs
VREFCA(DC)
0.49 * VDDCA
0.51 * VDDCA
Unit
Note
V
V
V
V
1,2
1,2
1
1
V
3,4
Note:
1. For CA and CS_n input only pins. VREF =VREFCA(DC).
2. See the section “Overshoot and UndershootSpecifications”.
3. The ac peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than +/-1% VDDCA (for reference: ap
prox. +/- 12mV).
4. For reference: approx. VDDCA/2 +/- 12mV.
AC and DC Logic Input Levels for CKE
Parameter
CKE Input High Level
CKE Input Low Level
Symbol
VIHCKE
VILCKE
Min
0.65 * VDDCA
Note 1
Max
Note 1
0.35 * VDDCA
Unit Note
V
1
V
1
Note: 1. See the section “Overshoot and Undershoot Specifications”.
AC and DC Logic Input Levels for Single-Ended Data (DQ and DM) Signals
Parameter
AC Input High Voltage
AC Input Low Voltage
DC Input High Voltage
DC Input Low Voltage
Reference Voltage for DQ
and DM Inputs
Reference Voltage for DQ
and DM Inputs
Symbol
VIHDQ
VILDQ
VIHDQ
VILDQ
VREFDQ(DC)
(DQ ODT disabled)
VREFDQ(DC)
(DQODT
enabled)
LPDDR3 1600/1333
Min
Max
VREF + 0.150
Note 2
Note 2
VREF - 0.150
VREF + 0.100
VDDQ
VSSCA
VREF - 0.100
0.49 * VDDQ
0.5 * Vodtr
- 0.01 * VDDQ
Unit
Note
V
V
V
V
1,2
1,2
1
1
0.51*VDDQ
V
3,4
0.5 * Vodtr
+ 0.01 * VDDQ
V
3,5,6
Note:
1. For DQ input only pins. VREF =VREFDQ(DC).
2. See the section of Overshoot and UndershootSpecifications.
3. The ac peak noise on VREFDQ may not allow VREFDQ to deviate from VREFDQ(DC) by more than +/-1% VDDQ (for reference: ap
prox. +/- 12mV).
4. For reference: approx. VDDQ/2 +/- 12mV.
5. For reference: approx. VODTR/2 +/- 12mV.
6. ThenominalmoderegisterprogrammedvalueforRODTandthenominalcontrolleroutputimpedanceRONareusedforthecalcu- lation of
VODTR. For testing purposes a controller RON value of 50 Ω isused.
Vodtr = (2 * RON + RTT) / (RON + RTT) * VDDQ
37
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
VREF Tolerances
Thedc-tolerancelimitsandac-noiselimitsforthereferencevoltagesVREFCAandVREFDQareillustratedinFigurebelow.ItshowsavalidreferencevoltageVREF(t)asafunctionoftime.(VREFstandsforVREFCAandVREFDQlikewise).
VDDstandsforVDDCSforVREFCAandVDDQforVREFDQ.VREF(DC)isthelinearaverageofVREF(t)overaverylong
periodoftime(e.g.1sec)andisspecifiedasafractionofthelinearaverageofVDDCAorVDDQalsooveraverylong
periodoftime(e.g.1sec).Thisaveragehastomeetthemin/maxrequirementsinTable“ElectricalCharacteristicsand
OperatingConditions”.FurthermoreVREF(t)maytemporarilydeviatefromVREF(DC)bynomorethan+/-1%VDD.V
REF(t)cannottracknoiseonVDDQorVDDCAif thiswouldsendVREF outsidethesespecifications.
voltage
VDD
V
VREF(t)
REF ac-noise
VREF(DC)max
VREF(DC)
VDD/2
VREF(DC)min
VSS
time
Figure. Illustration of VREF(DC) tolerance and VREF ac-noise limits
ThevoltagelevelsforsetupandholdtimemeasurementsVIH(AC),VIH(DC),VIL(AC)andVIL(DC)aredependentonV
REF."VREF"shallbe understoodasVREF(DC),asdefinedinFigure above.
Thisclarifiesthatdc-variationsofVRefaffecttheabsolutevoltageasignalhastoreachtoachieveavalidhighorlowl
evelandthereforethetimetowhichsetupandholdismeasured.Systemtimingandvoltagebudgetsneedtoaccount
forVREF(DC)deviationsfromtheoptimumpositionwithinthedata-eyeoftheinputsignals.
ThisalsoclarifiesthattheLPDDR3setup/holdspecificationandderatingvaluesneedtoincludetimeandvoltageassociatedwithVREFac-noise.Timingandvoltageeffectsduetoac-noiseonVREFuptothespecifiedlimit(+/-1%ofVD
D) are included in LPDDR3 timings and their associated deratings.
38
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Input Signal
Figure. LPDDR3 Input signal
Note:
1. Numbers reflect nominalvalues.
2. For CA0-9, CK_t, CK_c and CS_n, VDD stands for VDDCA. For DQ, DM/DNV, DQS_t and DQS_c, VDD stands forVDDQ.
3. ForCA0-9,CK_t,CK_candCS_n,VSSstandsforVSSCA.ForDQ,DM/DNV,DQS_tandDQS_c,VSSstandsfor VSSQ.
40
39
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
AC and DC Logic Input Levels for Differential Signals
DifferentialSignalDefinition
differential
voltage
VIHDIFF(AC)MIN
tDVAC
VIHDIFF(DC)MIN
CK_t - CK_c
DQS_t -DQS_c
0.0
VILDIFF(DC)MAX
VILDIFF(AC)MAX
halfcycle
tDVAC
Figure. Definition of differential ac-swing and Time above ac-level tDVAC
40
time
RS512M32LD3D2LMZ-125BT
LPDDR3 16Gb(x32)
Differential swing requirements for clock and strobe
Parameter
Symbol
DC Differential Input High
DC Differential Input Low
AC Differential Input High
AC Differential Input Low
VIHDIFF(DC)
VILDIFF(DC)
VIHDIFF(AC)
VILDIFF(AC)
Min
2 x (VIH(DC) - VREF)
Note 3
2 x (VIH(AC) - VREF)
Note 3
Max
Unit
Note
Note 3
2 x (VIL(DC) - VREF)
Note 3
2 x (VIL(AC) - VREF)
V
V
V
V
1
1
2
2
Note:
1.Used to define a differential signal slew-rate. For CK_t - CK_c use VIH/VIL(dc) of CA and VREFCA; for DQS_t - DQS_c, use VIH/
VIL(dc) of DQs and VREFDQ; if a reduced dc-high or dc-low level is used for a signal group, then the reduced level applies also here.
2.For CK_t - CK_c use VIH/VIL(ac) of CA and VREFCA; for DQS_t - DQS_c, use VIH/VIL(ac) of DQs and VREFDQ; if a reduced ac-high
or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined, however the single-ended signals CK_t, CK_c, DQS_t, and DQS_c need to be within the respective
limits(VIH(dc)max,VIL(dc)min) forsingle-endedsignalsaswellasthelimitationsforovershootandundershoot.Referto thesection of
“Overshoot and UndershootSpecifications”.
4. For CK_t and CK_c, Vref = VrefCA(DC). For DQS_t and DQS_c, Vref= VrefDQ(DC).
Table. Allowed time before ringback (tDVAC) for DQS_t - DQS_c
Slew Rate
[V/ns]
tDVAC [ps]
tDVAC [ps]
@ |VIH/Ldiff(ac)|=
300mV
1600Mbps
@ |VIH/Ldiff(ac)| =
300mV
1333Mbps
MIN
MIN
> 8.0
48
58
8.0
48
58
7.0
46
56
6.0
43
53
5.0
40
50
4.0
35
45
3.0
27
37
8.0
48
58
8.0
48
58
7.0
46
56
6.0
43
53
5.0
40
50
4.0
35
45
3.0
27
37
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