RTL8196E-CG
5-PORT 10/100M ETHERNET ROUTER
NETWORK PROCESSOR
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.0
29 June 2012
Track ID: JATR-3375-16
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
RTL8196E
Datasheet
COPYRIGHT
©2012 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
1.0
Release Date
2012/06/29
Summary
First release.
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Datasheet
Table of Contents
1.
GENERAL DESCRIPTION ..............................................................................................................................................1
2.
FEATURES .........................................................................................................................................................................2
3.
SYSTEM APPLICATIONS...............................................................................................................................................3
4.
BLOCK DIAGRAM ...........................................................................................................................................................4
5.
PIN ASSIGNMENTS .........................................................................................................................................................5
5.1.
6.
PIN DESCRIPTIONS.........................................................................................................................................................6
6.1.
6.2.
7.
PACKAGE IDENTIFICATION ...........................................................................................................................................5
CONFIGURATION UPON POWER ON STRAPPING .........................................................................................................10
SHARED I/O PIN MAPPING .........................................................................................................................................11
MEMORY CONTROLLER ............................................................................................................................................12
7.1.
SDR DRAM CONTROL INTERFACE ...........................................................................................................................12
7.1.1. Features................................................................................................................................................................12
7.2.
DDR DRAM CONTROLLER .......................................................................................................................................13
7.2.1. Features................................................................................................................................................................13
7.3.
SPI FLASH CONTROLLER ...........................................................................................................................................13
7.3.1. Features................................................................................................................................................................13
7.3.2. Pin Mode and Definition of Serial and Dual I/O..................................................................................................13
7.4.
SOFTWARE REGISTER DEFINITIONS ...........................................................................................................................14
7.4.1. Memory Control Register (MCR) (0xB800_1000) ...............................................................................................14
7.4.2. DRAM Configuration Register (DCR) (0xB800_1004)........................................................................................15
7.4.3. DRAM Timing Register (DTR) (0xB800_1008)....................................................................................................16
7.4.4. DDR DRAM Calibration Register (DDCR) (0xB800_1050)................................................................................17
7.4.5. SPI Flash Configuration Register (SFCR) (0xB800_1200)..................................................................................18
7.4.6. SPI Flash Configuration Register 2 (SFCR2) (0xB800_1204).............................................................................18
7.4.7. SPI Flash Control & Status Register (SFCSR) (0xB800_1208) ...........................................................................19
7.4.8. SPI Flash Data Register (SFDR) (0xB800_120C) ...............................................................................................20
7.4.9. SPI Flash Data Register 2 (SFDR2) (0xB800_1210)...........................................................................................20
8.
PERIPHERAL AND MISC CONTROLS......................................................................................................................21
8.1.
INTERRUPT CONTROL REGISTERS ..............................................................................................................................21
8.1.1. Global Interrupt Mask Register (GIMR) (0x B800_3000) ...................................................................................21
8.1.2. Global Interrupt Status Register (GISR) (0x B800_3004)....................................................................................22
8.1.3. Interrupt Routing Register 1 (IRR1) (0xB800_300C)...........................................................................................22
8.1.4. Interrupt Routing Register 2 (IRR2) (0xB800_3010) ...........................................................................................23
8.1.5. Interrupt Routing Register 3 (IRR3) (0xB800_3014) ...........................................................................................23
8.2.
TIMER ........................................................................................................................................................................24
8.2.1. Timer Control Address Mapping (Base: 0xB800_3100) ......................................................................................24
8.2.2. Timer/Counter 0 Data Register (0xB800_3100) ..................................................................................................24
8.2.3. Timer/Counter 1 Data Register (0xB800_3104) ..................................................................................................24
8.2.4. Timer/Counter 0 Counter Register (0xB800_3108) .............................................................................................25
8.2.5. Timer/Counter 1 Counter Register (0xB800_310C).............................................................................................25
8.2.6. Timer/Counter Control Register (0xB800_3110) .................................................................................................25
8.2.7. Timer/Counter Interrupt Register (0xB800_3114) ...............................................................................................25
8.2.8. Clock Division Base Register (0xB800_3118)......................................................................................................26
8.2.9. Watchdog Timer Control Register (0xB800_311C) .............................................................................................26
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8.3.
GPIO CONTROL .........................................................................................................................................................27
8.3.1. GPIO Register Set (0xB800_3500).......................................................................................................................27
8.3.2. GPIO Port A, B, C, D Control Register (PABCD_CNR) (0xB800_3500)............................................................28
8.3.3. GPIO Port A, B, C, D Direction Register (PABCD_DIR) (0xB800_3508)..........................................................28
8.3.4. Port A, B, C, D Data Register (PABCD_DAT) (0xB800_350C) ..........................................................................28
8.3.5. Port A, B, C, D Interrupt Status Register (PABCD_ISR) (0xB800_3510) ...........................................................29
8.3.6. Port A, B Interrupt Mask Register (PAB_IMR) (0xB800_3514) ..........................................................................29
8.3.7. Port C, D Interrupt Mask Register (PCD_IMR) (0xB800_3518).........................................................................30
8.4.
GPIO SHARED PIN CONFIGURED MAPPING LIST........................................................................................................31
8.4.1. Shared Pin Register (PIN_MUX_SEL) (0xB800_0040) .......................................................................................31
8.4.2. Shared Pin Register (PIN_MUX_SEL_2) (0xB800_0044) ...................................................................................32
9.
UART.................................................................................................................................................................................33
9.1.
FEATURES ..................................................................................................................................................................33
9.2.
INTERFACE PINS .........................................................................................................................................................33
9.3.
UART CONTROL REGISTER .......................................................................................................................................33
9.3.1. UART Control Register Address Mapping (Base: 0xB800_2000)........................................................................33
9.3.2. UART Receiver Buffer Register (DLAB=0) (0xB800_2100, 0xB800_2000) ........................................................34
9.3.3. UART Transmitter Holding Register (DLAB=0) (0xB800_2100, 0xB800_2000) ................................................34
9.3.4. UART Divisor Latch LSB (DLAB=1) (0xB800_2100, 0xB800_2000) .................................................................34
9.3.5. UART Divisor Latch MSB (DLAB=1) (0xB800_2104, 0xB800_2004) ................................................................34
9.3.6. UART Interrupt Enable Register (DLAB=0) (0xB800_2104, 0xB800_2004) ......................................................35
9.3.7. UART Interrupt Identification Register (0xB800_2108, 0xB800_2008) ..............................................................35
9.3.8. UART FIFO Control Register (0xB800_2108, 0xB800_2008).............................................................................35
9.3.9. UART Line Control Register (0xB800_210C, 0xB800_200C) .............................................................................36
9.3.10.
UART Modem Control Register (0xB800_2110, 0xB800_2010) .....................................................................36
9.3.11.
UART Line Status Register (0xB800_2114, 0xB800_2014) ............................................................................36
9.3.12.
UART Modem Status Register (0xB800_2110, 0xB800_2018)........................................................................37
9.4.
BAUD RATE ...............................................................................................................................................................37
10.
PCI EXPRESS BUS INTERFACE.............................................................................................................................38
10.1.
PCI EXPRESS TRANSMITTER ......................................................................................................................................38
10.2.
PCI EXPRESS RECEIVER .............................................................................................................................................38
10.3.
PCI EXPRESS HOST MODE .........................................................................................................................................39
10.3.1.
PCIe Port 0 Host Mode Extended Register Address Mapping (Base: 0xB8B0_1000) ....................................39
10.3.2.
PCIe MDIO Register (0xB8B0_1000) .............................................................................................................39
10.3.3.
PCIe Interrupt Status Register (0xB8B0_1004)...............................................................................................39
10.3.4.
PCIe Power Control Register (0xB8B0_1008)................................................................................................40
10.3.5.
PCIe IP Configuration Register (0xB8B0_100C)............................................................................................40
10.3.6.
PCIe SRAM BIST Check Register (0xB8B0_1010)..........................................................................................40
11.
SWITCH CORE CONTROL......................................................................................................................................41
11.1.
GLOBAL PORT CONTROL REGISTER ...........................................................................................................................41
11.1.1.
Global Port Control Register Address Mapping (Base: 0xBB80_4000) .........................................................41
11.1.2.
Global MDC/MDIO Command Register (0xBB80_4004) ...............................................................................41
11.1.3.
Global MDC/MDIO Status Register (0xBB80_4008)......................................................................................42
11.1.4.
Global Frame Filtering Control Register Address Mapping (Base: 0xBB80_4000).......................................42
11.1.5.
Global Broadcast Storm Control Register (0xBB80_4044).............................................................................42
11.2.
PER-PORT CONFIGURATION REGISTER.......................................................................................................................43
11.2.1.
Port Interface Type Control Register (0xBB80_4100) ....................................................................................43
11.2.2.
Port Configuration Register of Port N (N=0~4) .............................................................................................44
11.2.3.
Port Status Register of Port N (N=0~4) ..........................................................................................................47
12.
12.1.
GREEN ETHERNET ..................................................................................................................................................48
CABLE LENGTH POWER SAVING ................................................................................................................................48
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12.2.
12.3.
13.
LINK-DOWN POWER SAVING .....................................................................................................................................48
ENERGY EFFICIENT ETHERNET (EEE)........................................................................................................................48
DC SPECIFICATIONS...............................................................................................................................................49
13.1.
13.2.
13.3.
13.4.
13.5.
13.6.
13.7.
13.8.
13.9.
13.10.
13.11.
13.12.
14.
OPERATING CONDITIONS ...........................................................................................................................................49
TOTAL POWER CONSUMPTION ...................................................................................................................................49
SDR DRAM BUS DC PARAMETERS ..........................................................................................................................50
DDR DRAM BUS DC PARAMETERS .........................................................................................................................50
FLASH BUS DC PARAMETERS ....................................................................................................................................50
USB V1.1 DC PARAMETERS ......................................................................................................................................51
USB V2.0 DC PARAMETERS ......................................................................................................................................51
UART DC PARAMETERS ...........................................................................................................................................51
GPIO DC PARAMETERS .............................................................................................................................................52
JTAG DC PARAMETERS........................................................................................................................................52
RESET DC PARAMETERS .......................................................................................................................................52
LED DC PARAMETERS..........................................................................................................................................52
AC SPECIFICATIONS...............................................................................................................................................53
14.1.
CLOCK SIGNAL TIMING ..............................................................................................................................................53
14.1.1.
25MHz System Clock Timing...........................................................................................................................53
14.1.2.
40MHz System Clock Timing...........................................................................................................................54
14.1.3.
SDR DRAM Clock Timing ...............................................................................................................................54
14.2.
BUS SIGNAL TIMING ..................................................................................................................................................55
14.2.1.
SDR DRAM Bus...............................................................................................................................................55
14.2.2.
DDR DRAM Bus ..............................................................................................................................................57
14.2.3.
Serial Flash Interface ......................................................................................................................................59
14.2.4.
JTAG Boundary Scan ......................................................................................................................................60
14.2.5.
Power Configuration Timing ...........................................................................................................................61
14.3.
PCI EXPRESS BUS PARAMETERS ................................................................................................................................62
14.3.1.
Differential Transmitter Parameters ...............................................................................................................62
14.3.2.
Differential Receiver Parameters ....................................................................................................................63
14.3.3.
REFCLK Parameters.......................................................................................................................................63
15.
15.1.
15.2.
THERMAL CHARACTERISTICS ...........................................................................................................................68
THERMAL OPERATING RANGE ...................................................................................................................................69
THERMAL PARAMETERS.............................................................................................................................................69
16.
MECHANICAL DIMENSIONS.................................................................................................................................70
17.
ORDERING INFORMATION ...................................................................................................................................71
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List of Tables
TABLE 1.
TABLE 2.
TABLE 3.
TABLE 4.
TABLE 5.
TABLE 6.
TABLE 7.
TABLE 8.
TABLE 9.
TABLE 10.
TABLE 11.
TABLE 12.
TABLE 13.
TABLE 14.
TABLE 15.
TABLE 16.
TABLE 17.
TABLE 18.
TABLE 19.
TABLE 20.
TABLE 21.
TABLE 22.
TABLE 23.
TABLE 24.
TABLE 25.
TABLE 26.
TABLE 27.
TABLE 28.
TABLE 29.
TABLE 30.
TABLE 31.
TABLE 32.
TABLE 33.
TABLE 34.
TABLE 35.
TABLE 36.
TABLE 37.
TABLE 38.
TABLE 39.
TABLE 40.
TABLE 41.
TABLE 42.
TABLE 43.
TABLE 44.
TABLE 45.
TABLE 46.
TABLE 47.
TABLE 48.
TABLE 49.
TABLE 50.
TABLE 51.
TABLE 52.
PIN DESCRIPTIONS .......................................................................................................................................................6
CONFIGURATION UPON POWER ON STRAPPING .........................................................................................................10
SHARED I/O PIN MAPPING .........................................................................................................................................11
MEMORY CONTROL REGISTER (MCR) (0XB800_1000) ............................................................................................14
DRAM CONFIGURATION REGISTER (DCR) (0XB800_1004).....................................................................................15
DRAM TIMING REGISTER (DTR) (0XB800_1008)....................................................................................................16
DDR DRAM CALIBRATION REGISTER (DDCR) (0XB800_1050) .............................................................................17
SPI FLASH CONFIGURATION REGISTER (SFCR) (0XB800_1200) ..............................................................................18
SPI FLASH CONFIGURATION REGISTER 2 (SPCR2) (0XB800_1204) .........................................................................18
SPI FLASH CONTROL & STATUS REGISTER (SFCSR) (0XB800_1208) .....................................................................19
SPI FLASH DATA REGISTER (SFDR) (0XB800_120C) ..............................................................................................20
SPI FLASH DATA REGISTER 2 (SFDR2) (0XB800_1210) ..........................................................................................20
INTERRUPT CONTROL REGISTER ADDRESS MAPPING (BASE: 0XB800_3000) ...........................................................21
GLOBAL INTERRUPT MASK REGISTER (GIMR) (0X B800_3000) ..............................................................................21
GLOBAL INTERRUPT STATUS REGISTER (GISR) (0X B800_3004).............................................................................22
INTERRUPT ROUTING REGISTER 1 (IRR1) (0XB800_300C) ......................................................................................22
INTERRUPT ROUTING REGISTER 2 (IRR2) (0XB800_3010) .......................................................................................23
INTERRUPT ROUTING REGISTER 3 (IRR3) (0XB800_3014) .......................................................................................23
TIMER CONTROL ADDRESS MAPPING (BASE: 0XB800_3100) ...................................................................................24
TIMER/COUNTER 0 DATA REGISTER (0XB800_3100) ...............................................................................................24
TIMER/COUNTER 1 DATA REGISTER (0XB800_3104) ...............................................................................................24
TIMER/COUNTER 0 COUNTER REGISTER (0XB800_3108) .........................................................................................25
TIMER/COUNTER 1 COUNTER REGISTER (0XB800_310C).........................................................................................25
TIMER/COUNTER CONTROL REGISTER (0XB800_3110) ............................................................................................25
TIMER/COUNTER INTERRUPT REGISTER (0XB800_3114)..........................................................................................25
CLOCK DIVISION BASE REGISTER (0XB800_3118) ...................................................................................................26
WATCHDOG TIMER CONTROL REGISTER (0XB800_311C)........................................................................................26
GPIO REGISTER SET (0XB800_3500) .......................................................................................................................27
GPIO PORT A, B, C, D CONTROL REGISTER (PABCD_CNR) (0XB800_3500) ........................................................28
GPIO PORT A, B, C, D DIRECTION REGISTER (PABCD_DIR) (0XB800_3508)........................................................28
PORT A, B, C, D DATA REGISTER (PABCD_DAT) (0XB800_350C)........................................................................28
PORT A, B, C, D INTERRUPT STATUS REGISTER (PABCD_ISR) (0XB800_3510) .....................................................29
PORT A, B INTERRUPT MASK REGISTER (PAB_IMR) (0XB800_3514).....................................................................29
PORT C, D INTERRUPT MASK REGISTER (PCD_IMR) (0XB800_3518).....................................................................30
SHARED PIN REGISTER (PIN_MUX_SEL) (0XB800_0040)......................................................................................31
SHARED PIN REGISTER (PIN_MUX_SEL_2) (0XB800_0044)..................................................................................32
UART CONTROL INTERFACE PINS ............................................................................................................................33
UART CONTROL REGISTER ADDRESS MAPPING (BASE: 0XB800_2000) ..................................................................33
UART RECEIVER BUFFER REGISTER (DLAB=0) (0XB800_2100, 0XB800_2000) ...................................................34
UART TRANSMITTER HOLDING REGISTER (DLAB=0) (0XB800_2100, 0XB800_2000) ..........................................34
UART DIVISOR LATCH LSB (DLAB=1) (0XB800_2100, 0XB800_2000)................................................................34
UART DIVISOR LATCH MSB (DLAB=1) (0XB800_2104, 0XB800_2004)...............................................................34
UART INTERRUPT ENABLE REGISTER (DLAB=0) (0XB800_2104, 0XB800_2004) .................................................35
UART INTERRUPT IDENTIFICATION REGISTER (0XB800_2108, 0XB800_2008) .......................................................35
UART FIFO CONTROL REGISTER (0XB800_2108, 0XB800_2008) ..........................................................................35
UART LINE CONTROL REGISTER (0XB800_210C, 0XB800_200C)..........................................................................36
UART MODEM CONTROL REGISTER (0XB800_2110, 0XB800_2010)......................................................................36
UART LINE STATUS REGISTER (0XB800_2114, 0XB800_2014) ..............................................................................36
UART MODEM STATUS REGISTER (0XB800_2110, 0XB800_2018) .........................................................................37
DIVISOR LATCH VALUE EXAMPLES...........................................................................................................................37
PCIE PORT 0 HOST MODE EXTENDED REGISTER ADDRESS MAPPING (BASE: 0XB8B0_1000)..................................39
PCIE MDIO REGISTER (0XB8B0_1000) ...................................................................................................................39
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TABLE 53.
TABLE 54.
TABLE 55.
TABLE 56.
TABLE 57.
TABLE 58.
TABLE 59.
TABLE 60.
TABLE 61.
TABLE 62.
TABLE 63.
TABLE 64.
TABLE 65.
TABLE 66.
TABLE 67.
TABLE 68.
TABLE 69.
TABLE 70.
TABLE 71.
TABLE 72.
TABLE 73.
TABLE 74.
TABLE 75.
TABLE 76.
TABLE 77.
TABLE 78.
TABLE 79.
TABLE 80.
TABLE 81.
TABLE 82.
TABLE 83.
TABLE 84.
TABLE 85.
TABLE 86.
TABLE 87.
TABLE 88.
TABLE 89.
TABLE 90.
TABLE 91.
TABLE 92.
TABLE 93.
TABLE 94.
TABLE 95.
PCIE INTERRUPT STATUS REGISTER (0XB8B0_1004)...............................................................................................39
PCIE POWER CONTROL REGISTER (0XB8B0_1008)..................................................................................................40
PCIE IP CONFIGURATION REGISTER (0XB8B0_100C) ..............................................................................................40
PCIE SRAM BIST CHECK REGISTER (0XB8B0_1010) .............................................................................................40
GLOBAL PORT CONTROL REGISTER ADDRESS MAPPING (BASE: 0XBB80_4000) .....................................................41
GLOBAL MDC/MDIO COMMAND REGISTER (0XBB80-4004) ..................................................................................41
GLOBAL MDC/MDIO STATUS REGISTER (0XBB80_4008) ......................................................................................42
GLOBAL FRAME FILTERING CONTROL REGISTER ADDRESS MAPPING (BASE: 0XBB80_4000).................................42
GLOBAL BROADCAST STORM CONTROL REGISTER (0XBB80_4044) ........................................................................42
PER-PORT CONFIGURATION REGISTER ADDRESS MAPPING (BASE: 0XBB80_4100).................................................43
PORT INTERFACE TYPE CONTROL REGISTER (0XBB80_4100) ..................................................................................43
PORT CONFIGURATION REGISTER OF PORT N (N=0~4) .............................................................................................44
PORT STATUS REGISTER OF PORT N (N=0~4) ...........................................................................................................47
OPERATING CONDITIONS ...........................................................................................................................................49
TOTAL POWER CONSUMPTION...................................................................................................................................49
SDR DRAM BUS DC PARAMETERS..........................................................................................................................50
DDR DRAM BUS DC PARAMETERS .........................................................................................................................50
FLASH BUS DC PARAMETERS ...................................................................................................................................50
USB V1.1 DC PARAMETERS ......................................................................................................................................51
USB V2.0 DC PARAMETERS ......................................................................................................................................51
UART DC PARAMETERS ...........................................................................................................................................51
GPIO DC PARAMETERS ............................................................................................................................................52
JTAG DC PARAMETERS ............................................................................................................................................52
RESET DC PARAMETERS ...........................................................................................................................................52
LED DC PARAMETERS ..............................................................................................................................................52
25MHZ SYSTEM CLOCK TIMING ...............................................................................................................................53
40MHZ SYSTEM CLOCK TIMING ...............................................................................................................................54
SDR DRAM CLOCK TIMING .....................................................................................................................................54
SDR DRAM INPUT TIMING ......................................................................................................................................55
SDR DRAM OUTPUT TIMING ...................................................................................................................................55
SDR DRAM ACCESS CONTROL TIMING ...................................................................................................................56
DDR DRAM INPUT TIMING ......................................................................................................................................57
DDR DRAM OUTPUT TIMING ..................................................................................................................................57
DDR DRAM ACCESS CONTROL TIMING...................................................................................................................58
SERIAL FLASH INTERFACE OUTPUT TIMING ..............................................................................................................59
SERIAL FLASH INTERFACE INPUT TIMING..................................................................................................................59
JTAG BOUNDARY SCAN INTERFACE TIMING VALUES ..............................................................................................60
DIFFERENTIAL TRANSMITTER PARAMETERS .............................................................................................................62
DIFFERENTIAL RECEIVER PARAMETERS ....................................................................................................................63
REFCLK PARAMETERS.............................................................................................................................................63
THERMAL OPERATING RANGE...................................................................................................................................69
THERMAL PARAMETERS ............................................................................................................................................69
ORDERING INFORMATION ..........................................................................................................................................71
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List of Figures
FIGURE 1.
FIGURE 2.
FIGURE 3.
FIGURE 4.
FIGURE 5.
FIGURE 6.
FIGURE 7.
FIGURE 8.
FIGURE 9.
FIGURE 10.
FIGURE 11.
FIGURE 12.
FIGURE 13.
FIGURE 14.
FIGURE 15.
FIGURE 16.
FIGURE 17.
FIGURE 18.
FIGURE 19.
FIGURE 20.
FIGURE 21.
FIGURE 22.
BLOCK DIAGRAM .......................................................................................................................................................4
PIN ASSIGNMENTS ......................................................................................................................................................5
TYPICAL CONNECTION TO A CRYSTAL .....................................................................................................................53
TYPICAL CONNECTION TO AN OSCILLATOR ..............................................................................................................53
SDR DRAM CLOCK SPECIFICATIONS-1 ...................................................................................................................54
SDR DRAM CLOCK SPECIFICATIONS-2 ...................................................................................................................54
SDR DRAM INPUT TIMING ......................................................................................................................................55
SDR DRAM OUTPUT TIMING ..................................................................................................................................55
SDR DRAM ACCESS CONTROL TIMING ..................................................................................................................56
DDR DRAM ACCESS CONTROL TIMING .................................................................................................................58
SERIAL FLASH INTERFACE OUTPUT TIMING .............................................................................................................59
SERIAL FLASH INTERFACE INPUT TIMING ................................................................................................................59
BOUNDARY-SCAN GENERAL TIMING .......................................................................................................................60
BOUNDARY-SCAN RESET TIMING ............................................................................................................................60
POWER UP CONFIGURATION TIMING ........................................................................................................................61
SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING ................................................65
SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT ..........................................................................65
SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME MATCHING .......................................................65
DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD...................................................................66
DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME ...........................................................................66
DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK ...........................................................................................67
REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING .........................................................................67
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1.
General Description
The RTL8196E-CG is an integrated System-on-a-Chip (SoC) Application Specific Integrated Circuit
(ASIC) L2 5-Port Ethernet switch. An RLX4181 CPU is embedded and the clock rate can be up to
400MHz. To improve computational performance, a 16Kbyte I-Cache, 8Kbyte D-Cache, 16Kbyte
I-MEM, and 8Kbyte D-MEM are provided. A standard 5-signal P1149.1 compliant EJTAG test interface
is supported for CPU testing and software development.
The RTL8196E provides five ports (ports 0~4), integrated with five physical layer transceivers for
10Base-T and 100Base-TX. Each port of the RTL8196E may be configured as a LAN or WAN port.
The RTL8196E supports flexible IEEE 802.3x full-duplex flow control and optional half-duplex
backpressure control. For full-duplex, standard IEEE 803.3x flow control will enable pause ability only
when both sides of UTP have auto-negotiation ability and have enabled pause ability. The RTL8196E
also provides optional forced mode IEEE 802.3x full-duplex flow control. Based on optimized packet
memory management, the RTL8196E is capable of Head-Of-Line blocking prevention.
L2 Switch Features: The RTL8196E contains a 1024-entry address look-up table with a 10-bit 4-way
XOR hashing algorithm for address searching and learning. Auto-aging of each entry is provided and the
aging time is around 300~450 seconds.
The RTL8196E supports IEEE 802.3az, also known as Energy Efficient Ethernet (EEE). IEEE 802.3az
operates with the IEEE 802.3 Media Access Control (MAC) Sublayer to support operation in Low Power
Idle mode. When the Ethernet network is in low link utilization, EEE allows systems on both sides of the
link to save power. Green Ethernet power saving provides: link-on and dynamic detection of cable length,
and dynamic adjustment of power required for the detected cable length. This feature provides high
performance with minimum power consumption. The RTL8196E also implements link-down power
saving on a per-port basis, greatly cutting power consumption when the network cable is disconnected.
For peripheral interfaces, two 16550-compatible UARTs are supported, and a 16-byte FIFO buffer is
provided. USB OTG (On-The-Go) controllers are embedded in the RTL8196E to provide OTG
functionality. In addition, one USB PHY is embedded in the RTL8196E.
An MDI/MDIX auto crossover function is supported. For accessing high-speed devices, the RTL8196E
provides one PCI Express host to access a PCI Express interface.
The RTL8196E requires only a single 25MHz crystal or 40MHz clock input for the system PLL. The
RTL8196E also has two hardware timers and one watchdog timer to provide accurate timing and
watchdog functionality. For extension and flexibility, the RTL8196E supports up to 16 GPIO pins.
The RTL8196E is provided in a Low Profile Plastic Quad Flat Package, 128-Lead (LQFP128) package
and requires only a 3.3V external power supply. The built-in SWR or LDO 3.3V to 1.0V can be used for
the RTL8196E system core power.
5-Port 10/100M Ethernet Router Network Processor
1
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
2.
Features
SOC
Supports MIPS-1 ISA, MIPS16 ISA
Clock Rate: 400MHz
Provides a standard P1149.1 EJTAG test
port
Supports RLX4181 CPU suspend mode
Five Ethernet MAC switch with five
IEEE 802.3 10/100M physical layer
transceivers
Non-blocking wire-speed reception and
transmission and non-head-of-lineblocking/forwarding
Internal 256Kbit SRAM for packet
buffering
Internal 1024 entry 4-way hash L2 lookup table
Supports source and destination MAC
address filtering
One USB PHY embedded
Supports two 16550 UARTs
Supports up to 16 GPIO pins
Memory Interfaces
Serial Flash (SPI Type)
Supports one bank and dual I/O
channels for SPI Flash application
Each Flash bank could be configured
as 256K/512K/1M/2M/4M/8M/16M
Bytes
Boot up from SPI flash is supported
SDR DRAM
Supports one SDR DRAM bank; each
can be configured as
2M/4M/8M/16M/32M/64Mbyte
16-bit SDR DRAM data bus
supported
DDR1 DRAM
Supports one DDR1 DRAM bank
that can be configured as
16M/32M/64M/128Mbytes
16-bit DDR1 DRAM data bus
supported. System totally supports up
to 128Mbyte DDR1 DRAM memory
space
DDR2 DRAM
Supports one DDR2 DRAM bank
that can be configured as
32M/64M/128Mbyte
16-bit DDR2 DRAM data bus
supported. System totally supports up
to 128Mbyte DDR2 DRAM memory
space
CPU Interface (NIC)
Supports one-port USB
USB 2.0 Host or Device
L2 Capabilities
Embedded RISC CPU, RLX4181 with
16Kbyte I-Cache, 8Kbyte D-Cache,
16Kbyte I-MEM, 8Kbyte D-MEM
Supports BSD mbuf-like packet structure
with adjustable cluster size (128-byte to
2Kbyte) to provide optimum memory
utilization
The NIC DMA supports multipledescriptor-ring architecture for QoS
applications
Peripheral Interfaces
Supports PCI Express Host with
integrated PHY
One PCI Express PHY embedded
5-Port 10/100M Ethernet Router Network Processor
2
Supports Green Ethernet
Cable length power saving
Link down power saving
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
3.
Supports IEEE 802.3az Energy Efficient
Ethernet ability for 100Base-TX in full
duplex operation and 10Base-T in full/half
duplex mode
Other Added-Value Features
Supports Link Down Power Saving in
Ethernet PHYceivers
Supports two hardware timers and one
watchdog timer
Per-port configurable auto-crossover
function
Built-in internal ROM booting
Single 25MHz crystal or 40MHz clock
input
Built-in SWR/LDO
LDO for DDR1/DDR2
DDR1 DRAM: 3.3V to 2.5V
DDR2 DRAM: 3.3V to 1.8V
SWR or LDO for Core Power
SWR or LDO 3.3V to 1.0V
LQFP128 package
System Applications
IEEE 802.11b/g/n AP/Router
IEEE 802.11a/b/g/n Dualband Concurrent Router
Wired Router
5-Port 10/100M Ethernet Router Network Processor
3
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
Block Diagram
USB *1
UTP *5port
LED
PCIE *1
Arbiters
UART *2
GPIO A~C
EJTAG pins
4.
Figure 1.
5-Port 10/100M Ethernet Router Network Processor
Block Diagram
4
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
5.
Pin Assignments
Figure 2.
5.1.
Pin Assignments
Package Identification
Green package is indicated by the ‘G’ in GXXXX (Figure 2).
5-Port 10/100M Ethernet Router Network Processor
5
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
6.
Pin Descriptions
In this section the following abbreviations are used:
Upon Reset: Defined as a short time after the end of a hardware reset.
After Reset: Defined as the time after the specified ‘Upon Reset’ time.
I: Input
AI: Analog Input
O: Output
AO: Analog Output
I/O: Bi-Directional Input/Output
AI/O: Analog Bi-Directional Input/Output
P: Digital Power
AP: Analog Power
G: Digital Ground
AG: Analog Ground
IPD: Input Pin With Pull-Down Resistor
Pin Name
XI
XO
RESET#
TXOP_P[4:0]
TXON_P[4:0]
RXIP_P[4:0]
RXIN_P[4:0]
MD[15:0]
MA[13:0]
MCLK
MCLKE
MCS0#
BS[1:0]
RAS#
CAS#
IPU: Input Pin With Pull-Up Resistor;
(Typical Value = 75K Ohm)
Table 1. Pin Descriptions
Type Description
Clock & Reset
111
I
25MHz Crystal Clock, 25MHz External clock Input, or
40MHz External Clock Input.
110
O
25MHz Crystal Clock Output.
118
I
System External Reset.
10/100M Ethernet Physical Layer
26, 24, 15, 13, 5
AO
10/100M Ethernet Physical Layer Transmit Pair.
27, 23, 16, 12, 6
For differential data transmission.
28, 22, 18, 11, 7
AI
10/100M Ethernet Physical Layer Receive Pair.
29, 21, 19, 10, 8
For differential data reception.
Memory Interface
I/O
Data for DDR DRAM and SDR DRAM.
78, 77, 76, 75, 74, 73,
72, 71, 55, 56, 57, 58,
59, 60, 61, 62
O
Address for DDR DRAM and SDR DRAM
47, 37, 38, 39, 42, 43,
44, 45, 46, 48, 49, 50,
51, 52
SDR DRAM Control
65
O
SDR DRAM Clock.
85
O
SDR DRAM Clock Enable.
83
O
SDR DRAM Chip Select 0.
35, 36
O
SDR DRAM Chip Bank Select [1:0].
80
O
Raw Address Strobe (RAS#) for SDR DRAM.
81
O
Column Address Strobe for SDR DRAM.
Pin No.
5-Port 10/100M Ethernet Router Network Processor
6
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
Pin Name
WE#
LDQM
Pin No.
82
54
UDQM
69
MCLK
MCLK#
MCLKE
MCS0#
BS[2:0]
RAS#
CAS#
WE#
LDQM
65
66
85
83
84, 35, 36
80
81
82
54
UDQM
69
DDR_LDQS
63
DDR_UDQS
70
VREF
34
DDR_ODT
86
SF_CS0#
SF_SDIO[1:0]
SF_SCK
123
122, 121
120
U0_TX
U0_RX
U1_TX
U1_RX
U1_RTS#
U1_CTS#
125
126
1
127
128
2
JTAG_TCK
JTAG_TMS
JTAG_TDO
JTAG_TDI
127
2
1
128
Description
Write Enable for SDR DRAM.
Lower Data Mask Output to SDR DRAM.
Corresponds to D[7:0]
O
Upper Data Mask Output to SDR DRAM.
Corresponds to D[15:8]
DDR DRAM Control
O
DDR DRAM Differential Clock.
O
DDR DRAM Differential Clock.
O
DDR DRAM Clock Enable.
O
DDR DRAM Chip Select 0.
O
DDR DRAM Chip Bank Select [2:0].
O
Raw Address Strobe (RAS#) for DDR DRAM.
O
Column Address Strobe for DDR DRAM.
O
Write Enable for DDR DRAM.
O
Lower Data Mask Output to DDR DRAM.
Corresponds to D[7:0]
O
Upper Data mask output to DDR DRAM.
Corresponds to D[15:8]
O
Lower Data Strobe to DDR DRAM.
Corresponds to D[7:0]
O
Upper Data strobe to DDR DRAM.
Corresponds to D[15:8]
AI
Voltage Reference 1.25V for DDR1.
Voltage Reference 0.9V for DDR2.
O
DDR2 On-Die Termination.
ODT (registered HIGH) enables termination resistance
internal to the DDR2 DRAM.
Serial SPI Flash Control
O
SPI Serial Flash Chip Select 0.
I/O
SPI Serial Flash Serial Data Input/Output.
O
SPI Serial Flash Serial Clock Output.
SF_SDI will be driven on the falling edge.
SF_SDO will be latched on the rising edge.
UART
O
Data Transmit Serial Output of UART0.
IPU
Data Receive Serial Input of UART0.
O
Data Transmit Serial Output of UART1.
IPU
Data Receive Serial Input of UART1.
O
Request to Send of UART1.
I
Clear to Send of UART1.
JTAG
IPU
JTAG Test Clock.
IPU
JTAG Test Mode Select.
O
JTAG Test Data Output.
IPU
JTAG Test Data In.
5-Port 10/100M Ethernet Router Network Processor
Type
O
O
7
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
Pin Name
Pin No.
LED_PORT[4:0]
116, 118, 115, 114, 117
GPIOA[7:4]
GPIOA2
GPIOB[6:0]
126, 1, 128, 2
127
116, 118, 115, 114, 117,
124, 125
123
122, 121, 120
GPIOC6
GPIOC[3:1]
USB_DP
USB_DN
98
99
HSON0
HSOP0
HSIN0
HSIP0
REFCLKN0
REFCLKP0
PCIE_RST#
101
102
106
107
104
105
124
IBREF
31
R12K
113
VDD33
VDD33_25_18
119
79, 67, 53, 41
AVDD33
AVDD33_PHYPLL
VDD10
AVDD10
AVDD33X
AVDD33_BG
AVDD10_PCIE
AVDD10_PHYPLL
AVDD33_USB
AVDD10_USB
GND
GND_SWR
AGND_PCIE
20, 9
30
95, 64, 33, 3
25, 14, 4
109
112
103
32
96
97
93, 68, 40, 17
89
108
Type
Description
LED
O
Ethernet LED.
Link/Activity Status of 5 ports (Low Active).
GPIO
I/O
GPIO Port A.
I/O
GPIO Port B.
I/O
GPIO Port C.
USB Host 2.0
AI/O USB Host/OTG Device Data Plus Pin.
AI/O USB Host/OTG Device Data Minus Pin.
PCI Express Interface
AO
Transmitter Differential Pair.
5-Port 10/100M Ethernet Router Network Processor
AI
Receiver Differential Pair.
AO
Reference Clock Differential Pair.
O
PCI Express Reset.
Reference Voltage
AI
Reference Voltage for Ethernet PHY.
2.5K 1% pull down
AI
Reference Voltage for System.
12K 1% pull down
Power & GND
P
Digital I/O Power Supply 3.3V.
P
Memory I/O Power Supply 3.3V, 2.5V, or 1.8V.
SDR DRAM: 3.3V
DDR1 DRAM: 2.5V
DDR2 DRAM: 1.8V
AP
Ethernet Analog Power Supply 3.3V.
AP
Ethernet PHY PLL Power 3.3V.
P
Digital Core Power Supply 1.0V.
AP
Ethernet Analog Power Supply 1.0V.
AP
25M Crystal Power 3.3V.
AP
System Bandgap Power Supply 3.3V.
AP
PCI Express Analog Power Supply 1.0V.
AP
Ethernet PHY PLL Power 1.0V.
AP
USB 2.0 Analog Power 3.3V.
AP
USB 2.0 Analog Power 1.0V.
G
System GND.
AG
Switching Regulator GND.
AG
PCI Express GND.
8
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
Pin Name
AGND_USB
Pin No.
100
VDD33_LDO
LDO_OUT
87
88
AVDD33_SWR
SWR_LX
SWR_MODE
92
91, 90
93
VDD33_LDO_IN
94
VDD10_LDO_OUT
95
NC
31
Type Description
AG
USB GND.
SWR & LDO
AP
LDO Power Supply 3.3V Input for DDR.
AP
LDO Output Power for DDR.
DDR1 DRAM: 2.5V
DDR2 DRAM: 1.8V
AP
SWR Power Supply 3.3V.Input
AP
SWR Power Supply Output
I
Power Supply Output Voltage Select
0: SWR Output Voltage 1.0V Mode Select
1: LDO Output Voltage 1.0V Mode Select
AP
LDO Power Supply 3.3V Input for Core Power
LDO Mode:
LDO Power Supply 3.3V Input
SWR Mode:
This pin should be NC on the SWR Mode.
AP
LDO Power Supply 1.0V Output for Core Power
LDO Mode:
LDO Power Supply 1.0V Output
SWR Mode:
Power Supply 1.0V Input
Not Connected Pins
Not Connected.
5-Port 10/100M Ethernet Router Network Processor
9
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
6.1.
Configuration Upon Power On Strapping
All mode configuration pins are internal pull low. The 1.0V digital core power input pin voltage is up to
0.7V on system power-on. The strap data will be latched after a delay of 300ms.
H/W Pin Name
BS1, BS0, U0_TX
MA11, MA10,
MA9
MA2, MA1, MA0
MA6, MA5
MA3
MA4
MA8
MA12
MCLKE
Table 2. Configuration Upon Power On Strapping
Configuration Name
Pin No Description
ck_cpu_freq_sel[2:0]
74, 75, 2 CPU Clock Configuration.
000: 400MHz
001: 380MHz
010: 360MHz
011: 340MHz
100: 320MHz
101: 300MHz
110: 280MHz
111: 260MHz
ck_freq_sel[2:0]
77, 78, 80 DRAM Clock Rate Configuration.
000: 156.25MHz
001: 193.75MHz
010: 181.25MHz
011: Reserved
100: Reserved
101: 125MHz
110: Reserved
111: 168.75MHz
Bootpinsel[2:0]
88, 89, 90 Boot Pin Selection for the RTL8196E Boot Method.
000: SPI
001: Reserved
010: Reserved
011: Reserved
100: ROM booting Mode for SDR/DDR 16MB
101: ROM booting Mode for SDR/DDR 32MB
110: ROM booting Mode for SDR 8MB or DDR 64MB
111: ROM booting Mode for SDR 2MB or DDR 128MB
83, 84
Enable OLT (Auto Test Mode).
EnOLTautoTestMode[1:
0]
00: Normal Mode
10: Internal MP Test Mode
x1: Internal Debug Mode
DDR_TYPE
87
DDR DRAM Type.
0: DDR2
1: DDR1
External_Reset
86
Enable External Reset Pin.
0: Disable
1: Enable
DRAM_TYPE
81
DRAM Type.
0: SDR
1: DDR
Sel_40M
76
System Clock Source Select.
0: 25MHz
1: 40MHz
Strap_Testmode
126
Chip Test Mode Select.
0: Normal mode
1: Test mode
5-Port 10/100M Ethernet Router Network Processor
10
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
6.2.
Pin
127
2
128
1
126
125
124
117
114
115
118
116
120
121
122
123
Shared I/O Pin Mapping
GPIO
GPIOA[2]
GPIOA[4]
GPIOA[5]
GPIOA[6]
GPIOA[7]
GPIOB[0]
GPIOB[1]
GPIOB[2]
GPIOB[3]
GPIOB[4]
GPIOB[5]
GPIOB[6]
GPIOC[1]
GPIOC[2]
GPIOC[3]
GPIOC[6]
Table 3. Shared I/O Pin Mapping
Memory
EJTAG
LED
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
LED_PORT0
LED_PORT1
LED_PORT2
LED_PORT3
LED_PORT4
SF_SCK
SF_SDIO0
SF_SDIO1
SF_CS0#
-
5-Port 10/100M Ethernet Router Network Processor
11
UART
U1_RX
U1_CTS#
U1_RTS#
U1_TX
U0_RX
U0_TX
-
Reset
PCIE_RST#
RESET#
-
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
7.
Memory Controller
The RTL8196E integrates a memory control module to access external DDR DRAM , SDR DRAM, and
Flash memory.
The interface is designed for DDR-compliant DDR DRAM, and designed for PC133 or PC166-compliant
SDR DRAM, and supports auto-refresh mode, which requires a 4096 refresh cycle within 64ms. The
DRAM interface supports one chip (MCS0#), and the DRAM size and timing is configurable in registers.
The RTL8196E supports one flash memory chip (SF_CS0#). The interface supports SPI flash memory.
When Flash is used, the system will boot from KSEG1 at virtual address 0xBFC0_0000 (physical
address: 0x1FC0_0000).
7.1.
SDR DRAM Control Interface
PC100~PC166-compliant SDR DRAM is supported. The SDR DRAM controller supports Auto Refresh
mode, which requires a 4096-cycle refresh each 64ms. The RTL8196E provides a maximum of 512Mbit
address space (8Mx16x4Banks) and the SDR DRAM size is configurable.
7.1.1.
Features
•
Interface (Bus Width): 16-bit
•
Targeted SDR Frequency: Up to 168MHz
•
Supports one Chip Select (MCS0#)
•
Supported SDR DRAM Chip Specification:
Bank Counts: 2, 4
Row Counts: 2K (A0~A10), 4K (A0~A11), 8K (A0~A12)
Column Counts: 256 (A0~A7), 512 (A0~A8), 1K (A0~A9), 2K (A0~A9, A11)
Programmable Timing Parameters: tRAS, tRP, tRCD, tCL, tREFI…
•
5-Port 10/100M Ethernet Router Network Processor
12
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
7.2.
7.2.1.
DDR DRAM Controller
Features
•
Interface (Bus Width): 16-bit
•
Targeted DDR Frequency: Up to 193.75MHz
•
Supports one Chip Select (MCS0#)
•
Supports both DDR1 and DDR2
•
Supported DDR DRAM Chip Specification
Bank Counts: 8
Row Counts: 4K (A0~A11), 8K (A0~A12), 16K (A0~A13)
Column Counts: 512 (A0~A8), 1K (A0~A9), 2K (A0~A9, A11), 4K (A0~A9, A11, A12)
Programmable Timing Parameters: tRAS, tRP, tRCD, tCL, tREFI…
•
7.3.
SPI Flash Controller
The SPI flash controller is a new design and incorporates new features.
7.3.1.
Features
•
Targeted SPI flash frequency: Up to 96.875MHz (when DRAM clock is 193.75MHz)
•
Supports one chip
•
In addition to a programmed I/O interface, also supports a memory-mapped I/O interface for read
operation
•
Supports Read and Fast Read in memory-mapped I/O mode
7.3.2.
Pin Mode and Definition of Serial and Dual I/O
Modes supported on the SPI flash interface:
Serial I/O Mode
• SDI: Flash chip data input pin
•
SDO: Flash chip data output pin
Dual I/O Mode
• SDIO0 (SDI): Flash chip data bi-directional pin
•
SDIO1 (SDO): Flash chip data bi-directional pin
5-Port 10/100M Ethernet Router Network Processor
13
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
7.4.
7.4.1.
Software Register Definitions
Memory Control Register (MCR) (0xB800_1000)
This register does not provide byte access.
Bit
31
30
29
28
27
26
25:0
Table 4. Memory Control Register (MCR) (0xB800_1000)
Name
Description
DRAMTYPE
Report the Hardware Strapping Initial Value for DRAM Type.
0: SDR DRAM
1: DDR DRAM
BOOTSEL
Report the Hardware Strapping Initial Value for Boot Flash Type.
0: Reserved
1: Serial SPI flash
IPREF
Enable Instruction Prefetch Function.
0: Disable prefetch (also reset buffer status)
1: Enable prefetch (4 words)
DPREF
Enable Data Prefetch Function.
0: Disable prefetch (also reset buffer status)
1: Enable prefetch (4 words)
IPREF_MODE Choose Instruction Prefetch Mode.
0: Old prefetch mechanism
1: New prefetch mechanism
DPREF_MODE Choose Data Prefetch Mode.
0: Old prefetch mechanism
1: New prefetch mechanism
Reserved.
5-Port 10/100M Ethernet Router Network Processor
14
Mode
R
Default
0B
R
0B
RW
0B
RW
0B
RW
0B
RW
0B
-
-
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
7.4.2.
DRAM Configuration Register (DCR) (0xB800_1004)
This register does not provide byte access.
Bit
31:30
29:28
27
26:25
24:22
21
20
19
18
17
16
15:0
Table 5. DRAM Configuration Register (DCR) (0xB800_1004)
Name
Description
T_CAS
CAS Latency.
00: Latency=2
01: Latency=3
10: Latency=2.5 (only used for DDR)
11: Latency=4 (only used for DDR)
DBUSWID
DRAM Bus Width.
00: Reserved
01: 16 bit (used for DDR, SDR)
10: Reserved
11: Reserved
DCHIPSEL
DRAM Chip Select.
0: CS0#
1: CS0# and CS1#
ROWCNT
Row Counts.
00: 2K (A0~A10)
01: 4K (A0~A11)
10: 8K (A0~A12)
11: 16K (A0~A13)
COLCNT
Column Counts.
000: 256 (A0~A7)
001: 512 (A0~A8)
010: 1K (A0~A9)
011: 2K (A0~A9, A11)
100: 4K (A0~A9, A11, A12)
101: Reserved
110: Reserved
111: Reserved
BSTREF
Bursted 8 Auto-Refresh Commands (Used for DDR).
0: Disable
1: Enable
ARBIT
Enforce Interface Arbitration Take Effect.
0: Reserved
1: Take effect
BANKCNT
Bank Counts.
0: 2 banks (used for SDR)
1: 4 banks (used for SDR, DDR)
FAST_RX
If RX path turnaround delay is small enough, the memory controller
can return read data with reduced latency within 1DRAM clock
cycle (used for DDR).
0: Normal path
1: Fast path
MR_MODE
Select the Memory Command that Memory Controller Issues (Used
for DDR).
0: Mode Register
1: Extended Mode Register
DRV_STR
Drive Strength Setting of DRAM Chip (Used for DDR).
For this option to be effective, MR_MODE must be first set to 1.
0: Normal
1: Reduced
Reserved.
5-Port 10/100M Ethernet Router Network Processor
15
Mode
RW
Default
01B
RW
01B
RW
1B
RW
00B
RW
000B
RW
0B
RW
0B
RW
1B
RW
0B
RW
0B
RW
0B
-
-
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
7.4.3.
DRAM Timing Register (DTR) (0xB800_1008)
This register does not provide byte access.
Table 6. DRAM Timing Register (DTR) (0xB800_1008)
Description
tRP Timing Parameter of DRAM.
Basic Unit = 1*DRAM_CLK
000: 1 Unit
tRCD Timing Parameter of DRAM.
Basic Unit = 1*DRAM_CLK
000: 1 Unit
Minimum T_RAS Timing Parameter of DRAM.
Basic Unit = 1*DRAM_CLK
00000: 1 Unit
tRFC Timing Parameter of DRAM. Refresh row cycle time.
Basic Unit = 1*DRAM_CLK
0000000: 1 Unit
Bit
31:29
Name
T_RP
28:26
T_RCD
25:21
T_RAS
20:14
T_RFC
13:10
T_REFI
9:7
T_REFI_UNIT
6:4
T_WR
3:0
-
tREF Timing Parameter of DRAM. Refresh row interval time.
Basic unit = T_REFI_UNIT
0000: 1 Unit
0001: 2 Units
…
1111: 16 Units
Basic Unit of T_REFI.
000: 32 DRAM_CLK
001: 64 DRAM_CLK
010: 128 DRAM_CLK
011: 256 DRAM_CLK
100: 512 DRAM_CLK
101: 1024 DRAM_CLK
110: 2048 DRAM_CLK
111: 4096 DRAM_CLK
tWR Timing Parameter of DRAM. Write recovery time.
Basic Unit = 1*DRAM_CLK
000: 1 Unit
Reserved.
5-Port 10/100M Ethernet Router Network Processor
16
Mode
RW
Default
111B
RW
111B
RW
11111B
RW
1111100B
RW
0000B
RW
111B
RW
111B
-
-
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
7.4.4.
DDR DRAM Calibration Register (DDCR) (0xB800_1050)
This register does not provide byte access.
Bit
31
30
29:25
24:20
19:15
14:10
9:0
Table 7.
Name
CAL_MODE
DDR DRAM Calibration Register (DDCR) (0xB800_1050)
Description
Run-Time Calibration Mode.
0: Use analog DLL calibration
1: Use digital delay line calibration
SW_CAL_RDY
Ready for Digital Delay Line Calibration.
0: Not ready
1: Ready
DQS0_TAP[4:0]
Selects 32-Tap Delay Line for LDQS, which is Data Strobe for
DQ[7:0] Reception.
00000: 1st tap
00001: 2nd tap
…
11111: 32nd tap
Note: 32-tap delay is around 2.5 ns, which is chosen as it is
around 1/2 the DDR cycle (1 tap is around 78.125ps).
DQS1_TAP[4:0]
Selection of 32-Tap Delay Line for UDQS, which is Data strobe
for DQ[15:8] Reception.
00000: 1st tap
00001: 2nd tap
…
11111: 32nd tap
Note: 32-tap delay is around 2.5 ns, which is chosen as it is
around 1/2 the DDR cycle (1 tap is around 78.125ps).
DQS0_EN_TAP[4:0] Selection of 32-Tap Delay Line for the Internal LDQS_EN
Window.
00000: 1st tap
00001: 2nd tap
…
11111: 32nd tap
Note: 32-tap delay is around 2.5 ns, which is chosen as it is
around 1/2 the DDR cycle (1 tap is around 78.125ps).
DQS1_EN_TAP[4:0] Selection of 32-Tap Delay Line for the Internal UDQS_EN
Window.
00000: 1st tap
00001: 2nd tap
…
11111: 32nd tap
Note: 32-tap delay is around 2.5 ns, which is chosen as it is
around 1/2 the DDR cycle (1 tap is around 78.125ps).
Reserved.
5-Port 10/100M Ethernet Router Network Processor
17
Mode
RW
Default
0B
R
0B
RW
00000B
RW
00000B
RW
00000B
RW
00000B
-
-
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
7.4.5.
SPI Flash Configuration Register (SFCR) (0xB800_1200)
This register does not provide byte access.
Bit
31:29
Table 8.
Name
SPI_CLK_DIV
28
RBO
27
WBO
26:22
SPI_TCS
21:0
-
7.4.6.
SPI Flash Configuration Register (SFCR) (0xB800_1200)
Description
SPI Operating Clock Rate Selection.
The value defines the divisor to generate the SPI clock.
SPI Clock = (DRAM Clock)/(SPI_CLK_DIV).
000: DIV=2
001: DIV=4
010: DIV=6
011: DIV=8
100: DIV=10
101: DIV=12
110: DIV=14
111: DIV=16
Serial Flash Read Byte Ordering.
0: The byte order is from low to high
1: The byte order is from high to low
Serial Flash Write Byte Ordering.
0: The byte order is from low to high
1: The byte order is from high to low
SPI Chip Deselect Time.
Basic unit=1*DRAM clock cycle.
00000: 1 Unit
00001: 2 Units, etc.
Reserved.
Mode
RW
Default
111B
RW
1B
RW
1B
RW
11111B
-
-
SPI Flash Configuration Register 2 (SFCR2) (0xB800_1204)
This register does not provide byte access.
Bit
31:24
Table 9.
Name
SFCMD
23:21
SFSIZE
20
RD_OPT
19:18
CMD_IO
SPI Flash Configuration Register 2 (SPCR2) (0xB800_1204)
Description
Mode
RW
SPI Flash 8-Bit Command Code of a Read Transaction.
Example:
‘Read Data’ is 0x03.
‘Fast Read’ is 0x0B.
RW
SPI Flash Size.
000: 128Kbyte
001: 256Kbyte
010: 512Kbyte
011: 1Mbyte
100: 2Mbyte
101: 4Mbyte
110: 8Mbyte
111: 16Mbyte
RW
SPI Flash Sequential Access Optimization.
0: No optimization
1: Optimization for sequential access
RW
SPI Flash I/O Mode Selection for the Command Phase of a
Read Transaction.
00: Serial I/O (8 cycles)
01: Dual I/O (4 cycles)
10: Reserved
11: Reserved
5-Port 10/100M Ethernet Router Network Processor
18
Track ID: JATR-3375-16
Default
03H
111B
0B
00B
Rev. 1.0
RTL8196E
Datasheet
Bit
17:16
Name
ADDR_IO
15:13
DUMMY_CYCLES
12:11
DATA_IO
10
HOLD_TILL_SFDR2
9:0
-
7.4.7.
Description
SPI Flash I/O Mode Selection for the Address Phase of a Read
Transaction.
00: Serial I/O (24 cycles)
01: Dual I/O (12 cycles)
10: Reserved
11: Reserved
SPI Flash Inserted Dummy Cycles for the Dummy Cycle Phase
of a Read Transaction.
000: 0 Cycle
001: 2 Cycles
010: 4 Cycles
011: 6 Cycles
100: 8 Cycles
101: 10 Cycles
110: 12 Cycles
111: 14 Cycles
SPI Flash I/O Mode Selection for the Data Phase of a Read
Transaction (Assume 8*N Cycles).
00: Serial I/O (8*N cycles)
01: Dual I/O (4*N cycles)
10: Reserved
11: Reserved
If this bit is ‘1’, it indicates the write operation to this register
(SFCR2) will not take effect immediately but will be delayed
until another write operation to SFDR2.
Reserved.
Mode
RW
Default
00B
RW
000B
RW
00B
RW
0B
-
-
SPI Flash Control & Status Register (SFCSR) (0xB800_1208)
This register does not provide byte access.
Bit
31
30
29:28
27
26:25
24
23:16
15:0
Table 10. SPI Flash Control & Status Register (SFCSR) (0xB800_1208)
Name
Description
Mode
SPI_CSB0
SPI Flash Chip Select 0.
RW
0: Active
1: Not active
SPI_CSB1
SPI Flash Chip Select 1.
RW
0: Active
1: Not active
RW
LEN
SPI Read/Write Data Length (Unit=Byte).
00: 1 Byte
01: 2 Bytes
10: 3 Bytes
11: 4 Bytes
R
SPI_RDY
SPI Flash Operation Busy Indication Flag.
0: Busy (operation in progress)
1: Ready (idle or SPI access command is ready)
RW
IO_WIDTH
SPI Flash I/O Mode Selection of a Transaction.
00: Serial I/O
01: Dual I/O
10: Reserved
11: Reserved
CHIP_SEL
Chip Selection.
RW
0: CS0#
1: Reserved
CMD_BYTE
RW
SPI Flash 8-Bit Command Code of a Transaction (This field is
only used in MMIO mode). Example:
‘Read Data’ is 0x03.
‘Read ID’ is 0x9F.
Reserved.
-
5-Port 10/100M Ethernet Router Network Processor
19
Track ID: JATR-3375-16
Default
1B
1B
11B
1B
00B
0B
0B
Rev. 1.0
RTL8196E
Datasheet
7.4.8.
SPI Flash Data Register (SFDR) (0xB800_120C)
This register does not provide byte access.
This configuration register is used for the PIO (Programmed I/O) access mode.
Bit
31:24
23:16
15:8
7:0
7.4.9.
Name
Data3
Data2
Data1
Data0
Table 11. SPI Flash Data Register (SFDR) (0xB800_120C)
Description
Read/Write Data Byte 3.
Read/Write Data Byte 2.
Read/Write Data Byte 1.
Read/Write Data Byte 0.
Mode
RW
RW
RW
RW
Default
0B
0B
0B
0B
Mode
RW
RW
RW
RW
Default
0B
0B
0B
0B
SPI Flash Data Register 2 (SFDR2) (0xB800_1210)
This register does not provide byte access.
This configuration register is intended to be used under MMIO access mode.
Bit
31:24
23:16
15:8
7:0
Table 12. SPI Flash Data Register 2 (SFDR2) (0xB800_1210)
Name
Description
Data3
Read/Write Data Byte 3.
Data2
Read/Write Data Byte 2.
Data1
Read/Write Data Byte 1.
Data0
Read/Write Data Byte 0.
5-Port 10/100M Ethernet Router Network Processor
20
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
8.
Peripheral and MISC Controls
8.1.
Interrupt Control Registers
The RTL8196E provides fourteen hardware-interrupt inputs, IRQ2 to IRQ15. The Global Interrupt Mask
Register (GIMR) enables/disables an interrupt feature from the Timer, USB, UART, PCIe, Switch Core,
or GPIO modules. The Global Interrupt Status Register (GISR) shows the pending interrupt status. The
Interrupt Routing Register (IRR) controls the mappings of the IRQ2 to IRQ15 interrupt sources.
Offset
00
04
0C
10
14
8.1.1.
Bit
31:28
27
26
25
24:22
21
20:17
16
15
14
13
12
11
10
9
8
7:0
Table 13. Interrupt Control Register Address Mapping (Base: 0xB800_3000)
Size (byte)
Name
Description
4
GIMR
Global Interrupt Mask Register.
4
GISR
Global Interrupt Status Register.
4
IRR1
Interrupt Routing Register 1.
4
IRR2
Interrupt Routing Register 2.
4
IRR3
Interrupt Routing Register 3.
Global Interrupt Mask Register (GIMR) (0x B800_3000)
Table 14. Global Interrupt Mask Register (GIMR) (0x B800_3000)
Bit Name
Description
Reserved.
CPU_WAKE_IE
CPU Wake-Up Interrupt Enable.
Reserved.
USB1_WAKE_IE
USB Port 1 OTG (On-The-Go) Wake-Up Interrupt Enable.
Reserved.
PCIE0_IE
PCIe Port 0 Host Interface Interrupt Enable.
Reserved.
GPIO_ABCD_IE
GPIO Port A, B, C, D Interrupt Enable.
SW_IE
Switch Core Interrupt Enable.
Reserved.
UART1_IE
UART 1 Interrupt Enable.
UART0_IE
UART 0 Interrupt Enable.
USB_O_IE
USB 2.0 OTG Interrupt Enable.
Reserved.
TC1_IE
Timers/Counters #1 Interrupt Enable.
TC0_IE
Timers/Counters #0 Interrupt Enable.
Reserved.
5-Port 10/100M Ethernet Router Network Processor
21
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
8.1.2.
Bit
31:28
27
26
25
24:22
21
20:17
16
15
14
13
12
11
10
9
8
7:0
8.1.3.
Bit
31:28
27:24
23:20
19:16
15:12
11:8
7:4
3:0
Global Interrupt Status Register (GISR) (0x B800_3004)
Table 15. Global Interrupt Status Register (GISR) (0x B800_3004)
Bit Name
Description
RW
Reserved.
R
CPU_WAKE_IP
CPU Wake-Up Interrupt Pending Flag.
R
Reserved
R
USB1_WAKE_IP
R
USB Port 1 OTG (On-The-Go) Wake-Up Interrupt
Pending Flag.
Reserved.
R
PCIE0_IP
PCIE Port 0 Host Interface Interrupt Pending Flag.
R
Reserved.
R
GPIO_ABCD_IP
GPIO Port A, B, C, D Interrupt Pending Flag.
R
SW_IP
Switch Core Interrupt Pending Flag.
R
Reserved.
R
UART1_IP
UART 1 Interrupt Pending Flag.
R
UART0_IP
UART 0 Interrupt Pending Flag.
R
USB_O_IP
USB 2.0 OTG Interrupt Pending Flag.
R
Reserved.
R
TC1_IP
Timers/Counters #1 Interrupt Pending Flag.
R
TC0_IP
Timers/Counters #0 Interrupt Pending Flag.
R
Reserved.
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Interrupt Routing Register 1 (IRR1) (0xB800_300C)
Table 16. Interrupt Routing Register 1 (IRR1) (0xB800_300C)
Bit Name
Description
SW_RS[3:0]
Switch Core Interrupt Route Select.
Reserved.
UART1_RS[3:0]
UART 1 Interrupt Route Select.
UART0_RS[3:0]
UART 0 Interrupt Route Select.
USB_O_RS[3:0]
USB 2.0 OTG Interrupt Route Select.
Reserved.
TC1_RS[3:0]
Timers/Counters #1 Interrupt Route Select.
TC0_RS[3:0]
Timers/Counters #0 Interrupt Route Select.
5-Port 10/100M Ethernet Router Network Processor
22
RW
RW
RW
RW
RW
RW
RW
RW
RW
Track ID: JATR-3375-16
Default
0
0
0
0
0
0
0
0
Rev. 1.0
RTL8196E
Datasheet
8.1.4.
Bit
31:28
27:24
23:20
19:8
7:4
3:0
8.1.5.
Bit
31:20
19:16
15:12
11:8
7:4
3:0
Interrupt Routing Register 2 (IRR2) (0xB800_3010)
Table 17. Interrupt Routing Register 2 (IRR2) (0xB800_3010)
Bit Name
Description
Reserved.
Reserved.
PCIE0_RS[3:0]
PCIE Port 0 Interface Interrupt Route Select.
Reserved.
Reserved.
GPIO_ABCD_RS[3:0]
GPIO Port A, B, C, D Interrupt Route Select.
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
InitVal
0
0
0
0
0
RW
0
Interrupt Routing Register 3 (IRR3) (0xB800_3014)
Table 18. Interrupt Routing Register 3 (IRR3) (0xB800_3014)
Bit Name
Description
Reserved.
Reserved.
CPU_WAKE_RS[3:0]
CPU Wake-Up Interrupt Route Select.
Reserved.
USB1_WAKE_RS[3:0]
USB Port 1 OTG (On-The-Go) Wake-Up Interrupt
Route Select.
Reserved.
5-Port 10/100M Ethernet Router Network Processor
23
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
8.2.
Timer
The RTL8196E provides two sets of hardware timers and one watchdog timer. Each timer can be
configured to timer mode or counter mode. Counter mode means the timer only times-out once. The
initial time-out values are configured via TC0DATA and TC1DATA. The current count values are shown
in TC0CNT and TC1CNT. The Clock Division Base Register (CDBR) defines the base clock for
counting, and is based on a multiple of the system clock. The Timer/Counter Interrupt Register (TCIR)
controls the interrupt resulting from a timer time-out. The Watchdog timer is controlled by the Watchdog
Timer Control Register (WDTCNR).
8.2.1.
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
8.2.2.
Bit
31:4
3:0
8.2.3.
Bit
31:4
3:0
Timer Control Address Mapping (Base: 0xB800_3100)
Table 19. Timer Control Address Mapping (Base: 0xB800_3100)
Size (byte)
Name
Description
4
TC0DATA Timer/Counter 0 Data Register. It specifies the time-out duration.
4
TC1DATA Timer/Counter 1 Data Register. It specifies the time-out duration.
4
TC0CNT
Timer/Counter 0 Count Register.
4
TC1CNT
Timer/Counter 1 Count Register.
4
TCCNR
Timer/Counter Control Register.
4
TCIR
Timer/Counter Interrupt Register.
4
CDBR
Clock Division Base Register.
4
WDTCNR
Watchdog Timer Control Register.
Timer/Counter 0 Data Register (0xB800_3100)
Table 20. Timer/Counter 0 Data Register (0xB800_3100)
Name
Description
TC0Data[27:0]
The Timer or Counter Initial Value.
Counter values of 0 and 1 are not allowed.
Reserved.
RW
RW
Default
0H
-
-
RW
RW
Default
0H
-
-
Timer/Counter 1 Data Register (0xB800_3104)
Table 21. Timer/Counter 1 Data Register (0xB800_3104)
Name
Description
TC1Data[27:0]
The Timer or Counter Initial Value.
Counter values of 0 and 1 are not allowed.
Reserved.
5-Port 10/100M Ethernet Router Network Processor
24
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
8.2.4.
Bit
31:4
3:0
8.2.5.
Bit
31:4
3:0
8.2.6.
Bit
31
30
29
28
27: 0
8.2.7.
Bit
31
30
29
28
27:0
Timer/Counter 0 Counter Register (0xB800_3108)
Table 22. Timer/Counter 0 Counter Register (0xB800_3108)
Name
Description
TC0Value[27:0]
The Timer or Counter Value.
Count incremented by 1 from 0.
Reserved.
RW
R
Default
-
-
-
RW
R
Default
-
-
-
RW
RW
RW
Default
0
0
RW
RW
0
0
RW
0
RW
RW
RW
Default
0
0
RW
0
RW
0
RW
0
Timer/Counter 1 Counter Register (0xB800_310C)
Table 23. Timer/Counter 1 Counter Register (0xB800_310C)
Name
Description
TC1Value[27:0]
The Timer or Counter Value.
Count incremented by 1 from 0.
Reserved.
Timer/Counter Control Register (0xB800_3110)
Table 24. Timer/Counter Control Register (0xB800_3110)
Bit Name
Description
TC0En
Timer/Counter 0 Enable.
TC0Mode
Timer/Counter 0 Mode.
0: Counter mode
1: Timer mode
TC1En
Timer/Counter 1 Enable.
TC1Mode
Timer/Counter 1 Mode.
0: Counter mode
1: Timer mode
When Mitigation&Timer1 is asserted, this bit should be set to 1
to ensure normal processing.
Reserved.
Timer/Counter Interrupt Register (0xB800_3114)
Table 25. Timer/Counter Interrupt Register (0xB800_3114)
Bit Name
Description
TC0IE
Timer/Counter 0 Interrupt Enable.
TC1IE
Timer/Counter 1 Interrupt Enable.
When Mitigation&Timer1 is asserted, this bit should be set as
0 to assure normal processing.
TC0IP
Timer/Counter 0 Interrupt Pending.
Write ‘1’ to clear the interrupt.
TC1IP
Timer/Counter 1 Interrupt Pending.
Write ‘1’ to clear the interrupt.
Reserved.
5-Port 10/100M Ethernet Router Network Processor
25
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
8.2.8.
Bit
31:16
15:0
8.2.9.
Bit
31:24
23
22:21
20
19
Clock Division Base Register (0xB800_3118)
Table 26. Clock Division Base Register (0xB800_3118)
Name
Description
DivFactor[16:0] Clock Source Division Factor.
Assume DivFactor=N,
then Base clock=System_clock (Peripheral Lexra Bus)/N.
Both values 0x0000 and 0x0001 disable the clock.
Reserved.
RW
RW
Default
0x0000
-
-
RW
W
Default
0xA5
W
RW
0
00
RW
0
RW
0
Watchdog Timer Control Register (0xB800_311C)
Table 27. Watchdog Timer Control Register (0xB800_311C)
Name
Description
WDTE[7:0]
Watchdog Enable.
When these bits are set to 0xA5, the watchdog timer stops. Other
values will enable the watchdog timer and cause a system reset when
an overflow signal occurs.
WDTCLR
Watchdog Clear. Write a 1 to clear the up-count watchdog counter.
OVSEL[1:0] Lower Overflow Select Bits.
These bits specify the overflow condition when the watchdog timer
counts to the value. The watchdog timer is based on the base clock
defined by CDBR.
00: 215
01: 216
10: 217
11: 218
WatchDogIND Watchdog Event Indicator.
0: A Watchdog RESET did not occur (POWER-ON or PIN RESET)
1: A Watchdog RESET occurred
Write ‘1’ to clear.
NRFRstType NOR Flash Reset Command Type Selection.
When the watchdog event is active and WatchDogIND=1, It will
cause the memory controller to reboot and issue a Flash reset
command. The command type should be pre-defined by this control
bit.
0: AMD NOR Flash reset command Type
1: Intel NOR Flash reset command Type
Note: This bit should not be reset by watchdog reset.
This bit has been taken over by System_Register hw_strap
(Offset: 0xB800_0008h~B800_000bh, RW)
Initial value: 0xff00_1410
Reg.bit[19]
Strap register without PAD: Indicates NOR flash reset type
5-Port 10/100M Ethernet Router Network Processor
26
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
Bit
18:17
Name
OVSEL[3:2]
16:0
-
8.3.
Description
Higher Overflow Select Bits.
These bits specify the overflow condition when the watchdog timer
counts to the value. The watchdog timer is based on the base clock
defined by CDBR.
There are a total of 24 watchdog bits.
Condition values are the OVSEL[3:0]
0000: 215
0001: 216
0010: 217
0011: 218
0100: 219
0101: 220
0110: 221
0111: 222
1000: 223
1001: 224
Reserved.
RW
RW
Default
0
-
-
GPIO Control
The RTL8196E provides eight sets of General Purpose Input/Output (GPIO) pins (GPIO A, B, C, D).
Each GPIO pin may be configured as an input or output pin. The GPIO DATA register may be used to
control GPIO pin signals. The GPIO pins are shared with some peripheral pins, and the type of peripheral
can affect the attributes of the shared pins. All GPIO sets can be used to generate interrupts, and an
interrupt mask and status register are provided. The GPIO control registers are defined in the following
table.
8.3.1.
Offset
0x00
0x08
0x0C
0x10
0x14
0x18
GPIO Register Set (0xB800_3500)
Size (Byte)
4
4
4
4
4
4
Table 28.
Name
PABCD_CNR
PABCD_DIR
PABCD_DAT
PABCD_ISR
PAB_IMR
PCD_IMR
GPIO Register Set (0xB800_3500)
Description
Port A, B, C, D Control Register
Port A, B, C, D Direction Register
Port A, B, C, D Data Register
Port A, B, C, D Interrupt Status Register
Port A, B Interrupt Mask Register
Port C, D Interrupt Mask Register
5-Port 10/100M Ethernet Router Network Processor
27
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
8.3.2.
Bit
31:24
23:16
15:8
7:0
8.3.3.
Bit
31:24
23:16
15:8
7:0
8.3.4.
Bit
31:24
23:16
15:8
7:0
GPIO Port A, B, C, D Control Register (PABCD_CNR)
(0xB800_3500)
Table 29. GPIO Port A, B, C, D Control Register (PABCD_CNR) (0xB800_3500)
Name
Description
Mode
PFC_D[7:0] Pin Function Configuration of Port D
RW
PFC_C[7:0]
Pin Function Configuration of Port C
RW
PFC_B[7:0]
Pin Function Configuration of Port B
RW
RW
PFC_A[7:0] Pin Function Configuration of Port A
Bit Value:
0: Configured as GPIO pin
1: Configured as dedicated peripheral pin
Default
FFH
FFH
FFH
FFH
GPIO Port A, B, C, D Direction Register (PABCD_DIR)
(0xB800_3508)
Table 30. GPIO Port A, B, C, D Direction Register (PABCD_DIR) (0xB800_3508)
Name
Description
Mode
DRC_D[7:0] Pin Direction Configuration of Port D
RW
0: Configured as input pin
1: Configured as output pin
DRC_C[7:0] Pin Direction Configuration of Port C
RW
0: Configured as input pin
1: Configured as output pin
DRC_B[7:0] Pin Direction Configuration of Port B
RW
0: Configured as input pin
1: Configured as output pin
DRC_A[7:0] Pin Direction Configuration of Port A
RW
0: Configured as input pin
1: Configured as output pin
Default
00H
00H
00H
00H
Port A, B, C, D Data Register (PABCD_DAT) (0xB800_350C)
Table 31. Port A, B, C, D Data Register (PABCD_DAT) (0xB800_350C)
Name
Description
PD_D[7:0]
Pin Data of Port D
0: Data=0
1: Data=1
PD_C[7:0]
Pin Data of Port C
0: Data=0
1: Data=1
PD_B[7:0]
Pin Data of Port B
0: Data=0
1: Data=1
PD_A[7:0]
Pin Data of Port A
0: Data=0
1: Data=1
5-Port 10/100M Ethernet Router Network Processor
28
Mode
RW
Default
00H
RW
00H
RW
00H
RW
00H
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
8.3.5.
Bit
31:24
23:16
15:8
7:0
8.3.6.
Bit
31:30
29:28
27:26
25:24
23:22
21:20
19:18
17:16
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
Port A, B, C, D Interrupt Status Register (PABCD_ISR)
(0xB800_3510)
Table 32. Port A, B, C, D Interrupt Status Register (PABCD_ISR) (0xB800_3510)
Name
Description
Mode
IPS_D[7:0]
Interrupt Pending Status of Port D.
RW
Write ‘1’ to clear the interrupt
IPS_C[7:0]
Interrupt Pending Status of Port C.
RW
Write ‘1’ to clear the interrupt
IPS_B[7:0]
Interrupt Pending Status of Port B.
RW
Write ‘1’ to clear the interrupt
IPS_A[7:0]
Interrupt Pending Status of Port A.
RW
Write ‘1’ to clear the interrupt
Default
00H
00H
00H
00H
Port A, B Interrupt Mask Register (PAB_IMR) (0xB800_3514)
Table 33.
Name
PB7_IM[1:0]
PB6_IM[1:0]
PB5_IM[1:0]
PB4_IM[1:0]
PB3_IM[1:0]
PB2_IM[1:0]
PB1_IM[1:0]
PB0_IM[1:0]
PA7_IM[1:0]
PA6_IM[1:0]
PA5_IM[1:0]
PA4_IM[1:0]
PA3_IM[1:0]
PA2_IM[1:0]
PA1_IM[1:0]
PA0_IM[1:0]
Port A, B Interrupt Mask Register (PAB_IMR) (0xB800_3514)
Description
PortB.7 Interrupt Mode
PortB.6 Interrupt Mode
PortB.5 Interrupt Mode
PortB.4 Interrupt Mode
PortB.3 Interrupt Mode
PortB.2 Interrupt Mode
PortB.1 Interrupt Mode
PortB.0 Interrupt Mode
PortA.7 Interrupt Mode
PortA.6 Interrupt Mode
PortA.5 Interrupt Mode
PortA.4 Interrupt Mode
PortA.3 Interrupt Mode
PortA.2 Interrupt Mode
PortA.1 Interrupt Mode
PortA.0 Interrupt Mode
00: Disable interrupt
01: Enable falling edge interrupt
10: Enable rising edge interrupt
11: Enable both falling or rising edge interrupt
5-Port 10/100M Ethernet Router Network Processor
29
Mode
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Track ID: JATR-3375-16
Default
00B
00B
00B
00B
00B
00B
00B
00B
00B
00B
00B
00B
00B
00B
00B
00B
Rev. 1.0
RTL8196E
Datasheet
8.3.7.
Bit
31:30
29:28
27:26
25:24
23:22
21:20
19:18
17:16
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
Port C, D Interrupt Mask Register (PCD_IMR) (0xB800_3518)
Table 34.
Name
PD7_IM[1:0]
PD6_IM[1:0]
PD5_IM[1:0]
PD4_IM[1:0]
PD3_IM[1:0]
PD2_IM[1:0]
PD1_IM[1:0]
PD0_IM[1:0]
PC7_IM[1:0]
PC6_IM[1:0]
PC5_IM[1:0]
PC4_IM[1:0]
PC3_IM[1:0]
PC2_IM[1:0]
PC1_IM[1:0]
PC0_IM[1:0]
Port C, D Interrupt Mask Register (PCD_IMR) (0xB800_3518)
Description
Mode
PortD.7 Interrupt Mode
RW
PortD.6 Interrupt Mode
RW
PortD.5 Interrupt Mode
RW
PortD.4 Interrupt Mode
RW
PortD.3 Interrupt Mode
RW
PortD.2 Interrupt Mode
RW
PortD.1 Interrupt Mode
RW
PortC.0 Interrupt Mode
RW
PortC.7 Interrupt Mode
RW
PortC.6 Interrupt Mode
RW
PortC.5 Interrupt Mode
RW
PortC.4 Interrupt Mode
RW
PortC.3 Interrupt Mode
RW
PortC.2 Interrupt Mode
RW
PortC.1 Interrupt Mode
RW
RW
PortC.0 Interrupt Mode.
00: Disable interrupt
01: Enable falling edge interrupt
10: Enable rising edge interrupt
11: Enable both falling or rising edge interrupt
5-Port 10/100M Ethernet Router Network Processor
30
Track ID: JATR-3375-16
Default
00B
00B
00B
00B
00B
00B
00B
00B
00B
00B
00B
00B
00B
00B
00B
00B
Rev. 1.0
RTL8196E
Datasheet
8.4.
GPIO Shared Pin Configured Mapping List
The RTL8196E GPIO pins are shared with the other functions.
8.4.1.
Bit
31:26
25:24
23:22
21:20
19:18
17:7
6
5
4:3
2:0
Shared Pin Register (PIN_MUX_SEL) (0xB800_0040)
Table 35. Shared Pin Register (PIN_MUX_SEL) (0xB800_0040)
Bit Name
Description
Reserved
reg_iocfg_sdio1 Configure SF_SDIO1 Pin as SF_SDIO1 or GPIOC3
00: SF_SDIO1
01: Reserved
10: Reserved
11: GPIOC3
reg_iocfg_sdio0 Configure SF_SDIO0 Pin as SF_SDIO0 or GPIOC2
00: SF_SDIO0
01: Reserved
10: Reserved
11: GPIOC2
reg_iocfg_sck
Configure SF_SCK Pin as SF_SCK or GPIOC1
00: SF_SCK
01: Reserved
10: Reserved
11: GPIOC1
reg_iocfg_fcs0n Configure SF_CS0# Pin as SF_CS0# or GPIOC6
00: SF_CS0#
01: Reserved
10: Reserved
11: GPIOC6
Reserved
reg_iocfg_pcie
Configure PCIE_RST# Pin as PCIe or GPIO Mode
0: PCIE_RST#
11: GPIOB1
reg_iocfg_uart
Configure UART0_TX and UART0_RX Pins as UART or GPIO
Mode
0: UART
1: GPIO
Reserved
reg_iocfg_jtag
Configure JTAG Pins as JTAG, UART1, or GPIO Mode
000: Reserved
001: JTAG
010: UART1
011: Reserved
100: Reserved
101: Reserved
110: GPIO
111: Reserved
5-Port 10/100M Ethernet Router Network Processor
31
Mode
RW
Default
00B
RW
00B
RW
00B
RW
00B
RW
00B
RW
0B
RW
000B
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
8.4.2.
Shared Pin Register (PIN_MUX_SEL_2) (0xB800_0044)
Bit
31:14
13:12
Table 36.
Bit Name
reg_iocfg_led_port4
11
10:9
reg_iocfg_led_port3
8
7:6
reg_iocfg_led_port2
5
4:3
reg_iocfg_led_port1
2
1:0
reg_iocfg_led_port0
Shared Pin Register (PIN_MUX_SEL_2) (0xB800_0044)
Description
Reserved
Configure LED_PORT4 Pin as LED_PORT4 or GPIO Mode
00: LED_PORT4
01: Reserved
10: Reserved
11: GPIOB6
Reserved
Configure LED_PORT3 Pin as LED_PORT3 or GPIO Mode
00: LED_PORT3
01: Reserved
10: Reserved
11: GPIOB5
Reserved
Configure LED_PORT2 Pin as LED_PORT2 or GPIO Mode
00: LED_PORT2
01: Reserved
10: Reserved
11: GPIOB4
Reserved
Configure LED_PORT1 Pin as LED_PORT1 or GPIO Mode
00: LED_PORT1
01: Reserved
10: Reserved
11: GPIOB3
Reserved
Configure LED_PORT0 Pin as LED_PORT0 or GPIO Mode
00: LED_PORT0
01: Reserved
10: Reserved
11: GPIOB2
5-Port 10/100M Ethernet Router Network Processor
32
Mode
RW
Default
10B
RW
10B
RW
10B
RW
10B
RW
10B
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
9.
UART
9.1.
Features
The RTL8196E provides two 16550 compatible UARTs. These contain a 16-byte First In First Out
(FIFO) buffer and Auto Flow Control to control transmissions on port 1. The baud rate can be up to
1Mbps and a programmable baud rate generator allows division of any input reference clock by 1 to
(2^16-1) and generates an internal 16x clock.
9.2.
Interface Pins
The UART interface pins are shown in Table 37.
Signal Name
TXD#
RXD#
RTS#
CTS#
9.3.
Type
O
I
O
I
Table 37. UART Control Interface Pins
Function
Transmit Data for Port 0 and Port 1.
Receive Data for Port 0 and Port 1.
Request to Send for Port 1.
Clear to Send for Port 1.
UART Control Register
9.3.1.
Offset
000
000
000
004
004
008
008
00c
010
014
018
01c
100
100
100
104
UART Control Register Address Mapping (Base: 0xB800_2000)
Table 38. UART Control Register Address Mapping (Base: 0xB800_2000)
Size (byte)
Name
Description
1
UART0_RBR
Receiver Buffer Register (DLAB=0).
1
UART0_THR
Transmitter Holding Register (DLAB=0).
1
UART0_DLL
Divisor Latch LSB (DLAB=1).
1
UART0_IER
Interrupt Enable Register (DLAB=0).
1
UART0_DLM
Divisor Latch MSB (DLAB=1).
1
UART0_IIR
Interrupt Identification Register.
1
UART0_FCR
FIFO Control Register.
1
UART0_LCR
Line Control Register.
1
UART0_MCR
Modem Control Register.
1
UART0_LSR
Line Status Register.
1
UART0_MSR
Modem Status Register.
1
UART0_SCR
Scratch Register.
1
UART1_RBR
Receiver Buffer Register (DLAB=0).
1
UART1_THR
Transmitter Holding Register (DLAB=0).
1
UART1_DLL
Divisor Latch LSB (DLAB=1).
1
UART1_IER
Interrupt Enable Register (DLAB=0).
5-Port 10/100M Ethernet Router Network Processor
33
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
Offset
104
108
108
10c
110
114
118
11c
9.3.2.
Reg.bit
31:24
9.3.3.
Size (byte)
1
1
1
1
1
1
1
1
Name
UART1_DLM
UART1_IIR
UART1_FCR
UART1_LCR
UART1_MCR
UART1_LSR
UART1_MSR
UART1_SCR
Description
Divisor Latch MSB (DLAB=1).
Interrupt Identification Register.
FIFO Control Register.
Line Control Register.
Modem Control Register.
Line Status Register.
Modem Status Register.
Scratch Register.
UART Receiver Buffer Register (DLAB=0) (0xB800_2100,
0xB800_2000)
Table 39. UART Receiver Buffer Register (DLAB=0) (0xB800_2100, 0xB800_2000)
Name
Description
Mode
Default
RBR[7:0]
Receiver Buffer Data.
R
00H
UART Transmitter Holding Register (DLAB=0) (0xB800_2100,
0xB800_2000)
Table 40. UART Transmitter Holding Register (DLAB=0) (0xB800_2100, 0xB800_2000)
Reg.bit
Name
Description
Mode
Default
31:24
THR[7:0]
Transmitter Holding Data.
W
00H
9.3.4.
Reg.bit
31:24
9.3.5.
Reg.bit
31:24
UART Divisor Latch LSB (DLAB=1) (0xB800_2100,
0xB800_2000)
Table 41. UART Divisor Latch LSB (DLAB=1) (0xB800_2100, 0xB800_2000)
Name
Description
Mode
DLL[7:0]
Divisor Latch LSB.
RW
Default
00H
UART Divisor Latch MSB (DLAB=1) (0xB800_2104,
0xB800_2004)
Table 42. UART Divisor Latch MSB (DLAB=1) (0xB800_2104, 0xB800_2004)
Name
Description
Mode
DLM[7:0]
Divisor Latch MSB.
RW
5-Port 10/100M Ethernet Router Network Processor
34
Default
00H
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
9.3.6.
Reg.bit
24
25
26
27
28
29
31:30
9.3.7.
Reg.bit
24
27:25
29:28
31:30
9.3.8.
Reg.bit
24
25
26
29:27
31:30
UART Interrupt Enable Register (DLAB=0) (0xB800_2104,
0xB800_2004)
Table 43. UART Interrupt Enable Register (DLAB=0) (0xB800_2104, 0xB800_2004)
Name
Description
Mode
Default
ERBI
Enable Received Data Available Interrupt.
RW
0B
ETBEI
Enable Transmitter Holding Register Empty Interrupt.
RW
0B
ELSI
Enable Receiver Line Status Interrupt.
RW
0B
EDSSI
Enable Modem Status Register Interrupt.
RW
0B
ESLP
Sleep Mode Enable.
RW
0B
ELP
Low Power Mode Enable.
RW
0B
Reserved.
-
UART Interrupt Identification Register (0xB800_2108,
0xB800_2008)
Table 44. UART Interrupt Identification Register (0xB800_2108, 0xB800_2008)
Name
Description
Mode
IPND
Interrupt Pending.
R
0: Interrupt pending
IID[2:0]
Interrupt ID. IID[1:0] indicates the interrupt priority.
R
Reserved.
FIFO16[1:0] 00: No FIFO
R
11: 16-byte FIFO
Default
1B
000B
11B
UART FIFO Control Register (0xB800_2108, 0xB800_2008)
Table 45. UART FIFO Control Register (0xB800_2108, 0xB800_2008)
Name
Description
Mode
EFIFO
Enable FIFO.
W
When this bit is set, enables the transmitter and receiver FIFOs.
Changing this bit clears the FIFOs.
RFRST
Receiver FIFO Reset.
W
Writes 1 to clear the receiver FIFO.
TFRST
Transmitter FIFO Reset.
W
Writes 1 to clear the transmitter FIFO.
Reserved.
W
RTRG[1:0]
Receiver Trigger Level (Trigger Level: 16-byte).
00: 01
01: 04
10: 08
11: 14
5-Port 10/100M Ethernet Router Network Processor
35
Default
0B
Track ID: JATR-3375-16
0B
0B
11B
Rev. 1.0
RTL8196E
Datasheet
9.3.9.
Reg.bit
25:24
26
27
29:28
30
31
9.3.10.
Reg.bit
24
25
27:26
28
29
9.3.11.
Reg.bit
24
25
26
27
28
UART Line Control Register (0xB800_210C, 0xB800_200C)
Table 46. UART Line Control Register (0xB800_210C, 0xB800_200C)
Name
Description
Mode
RW
WLS[1:0]
Word Length Select.
00: Reserved (NA)
01: 6 bits (NA)
10: 7 bits
11: 8 bits
STB
Number of Stop Bits.
RW
0: 1 bit
1: 2 bits
PEN
Parity Enable.
RW
RW
EPS[1:0]
Even Parity Select.
00: Odd parity
01: Even parity
10: Mark parity
11: Space parity
RW
BRK
Break Control.
Set this bit force TXD to the spacing (low) state (break).
Clear this bit to disable break condition.
DLAB
Divisor Latch Access Bit.
RW
Default
11B
0B
0B
00B
0B
0B
UART Modem Control Register (0xB800_2110, 0xB800_2010)
Table 47. UART Modem Control Register (0xB800_2110, 0xB800_2010)
Bit Name
Description
Mode
DTR
Data Terminal Ready.
RW
0: Set DTR# high
1: Set DTR# low
RTS
Request to Send.
RW
0: Set RTS# high
1: Set RTS# low
Reserved.
LOOP
Loopback.
RW
AFE
Auto Flow Control Enable.
RW
Default
0B
0B
0B
0B
UART Line Status Register (0xB800_2114, 0xB800_2014)
Table 48. UART Line Status Register (0xB800_2114, 0xB800_2014)
Name
Description
Mode
R
DR
Data Ready.
Character Mode: Data ready in RBR
FIFO Mode: Receiver FIFO is not empty
OE
Overrun Error.
R
An overrun occurs when the receiver FIFO is full and the next
character is completely received in the receiver shift register. An
OE is indicated. The character in the shift register will be
overwritten.
PE
Parity Error.
R
FE
Framing Error.
R
BI
Break Interrupt Indicator.
R
5-Port 10/100M Ethernet Router Network Processor
36
Default
0B
Track ID: JATR-3375-16
0B
0B
0B
0B
Rev. 1.0
RTL8196E
Datasheet
Reg.bit
29
Name
THRE
30
TEMT
31
RFE
9.3.12.
Mode
R
Default
1B
R
1B
R
0B
UART Modem Status Register (0xB800_2110, 0xB800_2018)
Table 49. UART Modem Status Register (0xB800_2110, 0xB800_2018)
Name
Description
Mode
Delta Clear to Send (CTS# Signal Transmits).
R
∆CTS
Delta Data Set Ready (DSR# Signal Transmits; Returns 0).
R
∆DSR
TERI
Trailing Edge Ring Indicator.
R
RI# signal changes from low to high (Returns 0).
Delta Data Carrier Detect (DCD# Signal Transmits; Returns 0).
R
∆DCD
CTS
Clear to Send.
R
0: CTS# detected high
1: CTS# detected low
R
DSR
Data Set Ready.
0: DSR# detected high
1: DSR# detected low
Loopback mode: Returns bit 0 of MCR
Normal mode: Returns 1
R
RI
Ring Indicator.
0: RI# detected high
1: RI# detected low
Loopback mode: Returns bit 3 of MCR
Normal mode: Returns 0
R
DCD
Data Carrier Detect.
0: DCD# detected high
1: DCD# detected low
Loopback mode: Returns bit 2 of MCR
Normal mode: Returns 1
Reg.bit
31
30
29
28
27
26
25
24
9.4.
Description
Transmitter Holding Register Empty.
Character Mode: THR is empty
FIFO Mode: Transmitter FIFO is empty
Transmitter Empty.
Character Mode: Both THR and TSR are empty
FIFO Mode: Both transmitter FIFO and TSR are empty
Receiver FIFO Error.
Either a parity, framing, or break error in the FIFO.
Default
1B
0B
0B
0B
0B
1B
0B
1B
Baud Rate
Value of divisor latch=[base clock/(16×baud rate)]–1. The base clock is 200MHz.
System CLK
Base Clock
200MHz
300bps
41665
Table 50. Divisor Latch Value Examples
1200bps
2400bps
9600bps 19200bps 38400bps
10415
5207
5-Port 10/100M Ethernet Router Network Processor
1301
650
37
324
57600bps
115200bps
216
107
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
10. PCI Express Bus Interface
The RTL8196E complies with PCI Express Base Specification Revision 1.1, and runs at a 2.5GHz
signaling rate with X1 link width, i.e., one transmit and one receive differential pair. The RTL8196E
supports four types of PCI Express messages: interrupt messages, error messages, power management
messages, and hot-plug messages. To ease PCB layout constraints, PCI Express lane polarity reversal and
link reversal are also supported. The RTL8196E provides one port on the PCI Express Host interface.
10.1. PCI Express Transmitter
The RTL8196E PCI Express block receives digital data from the Ethernet interface and performs data
scrambling with Linear Feedback Shift Register (LFSR) and 8B/10B coding technology into 10-bit code
groups. Data scrambling is used to reduce the possibility of electrical resonance on the link, and 8B/10B
coding technology is used to benefit embedded clocking, error detection, and DC balance by adding an
overhead to the system through the addition of two extra bits. The data code groups are passed through its
serializer for packet framing. The generated 2.5Gbps serial data is transmitted onto the PCB trace to its
upstream device via a differential driver.
10.2. PCI Express Receiver
The RTL8196E PCI Express block receives 2.5Gbps serial data from its upstream device to generate
parallel data. The receiver’s PLL circuits are re-synchronized to maintain bit and symbol lock. Through
8B/10B decoding technology and data de-scrambling, the original digital data is recovered and passed to
the RTL8196E internal Ethernet MAC to be transmitted onto the Ethernet media.
5-Port 10/100M Ethernet Router Network Processor
38
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
10.3. PCI Express Host Mode
10.3.1.
PCIe Port 0 Host Mode Extended Register Address Mapping
(Base: 0xB8B0_1000)
Table 51. PCIe Port 0 Host Mode Extended Register Address Mapping (Base: 0xB8B0_1000)
Offset
Size (byte)
Name
Description
0x00
4
MDIO
PCIe Port 0 MDIO Control Register.
0x04
4
INTSTR
PCIe Port 0 Interrupt Status Register.
0x08
4
PWRCR
PCIe Port 0 Power Control Register.
0x0C
4
IPCFG
PCIe Port 0 IP Configuration Register.
0x10
4
BISTFAIL PCIe Port 0 BIST Fail Check Register.
10.3.2.
PCIe MDIO Register (0xB8B0_1000)
Reg.bit
31:16
15:13
12:8
7
6:5
4
3:2
Name
Mdio_data
Mdip_phyaddr
Mdio_regaddr
Mdio_st
Mdio rdy
Mdio_rate
1
Mdio_srst
0
Mdio_rdwr
10.3.3.
Reg.bit
3
2
1
0
Table 52. PCIe MDIO Register (0xB8B0_1000)
Description
MDIO Read Data or Write Data.
MDIO PHY Page Addr[2:0].
MDIO Register Address[4:0].
Reserved.
MDIO Status[1:0] for Debug Checking.
MDIO Ready for Debug Checking.
MDIO Clock Rate.
2’b00: lx clock/32
2’b01: lx clock/16
2’b10: lx clock/8
2’b11: lx clock/4
MDIO Soft Reset.
1: Active
0: Not active
MDIO Read/Write Command.
1: Write
0: Read
Mode
RW
RW
RW
R
R
RW
Default
0H
0H
00B
0
00B
RW
0B
RW
0B
Mode
R
R
R
R
Default
0B
0B
0B
0B
PCIe Interrupt Status Register (0xB8B0_1004)
Name
INTD
INTC
INTB
INTA
Table 53. PCIe Interrupt Status Register (0xB8B0_1004)
Description
Interrupt D Status Register (Level Active).
Interrupt C Status Register (Level Active).
Interrupt A Status Register (Level Active).
Interrupt A Status Register (Level Active).
5-Port 10/100M Ethernet Router Network Processor
39
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
10.3.4.
PCIe Power Control Register (0xB8B0_1008)
Table 54. PCIe Power Control Register (0xB8B0_1008)
Reg.bit
Name
Description
10
App_unlock_msg
Generate Unlock Message (One Pulse).
9
Apps_pm_xmt_turnoff Generate PME Turn Off Message.
8
App_init_rst
Application User Trigger Hot Reset (Must Keep Asserted for
2ms Minimum).
7
Phy_srst_n
PCIe PHY Software Reset.
0: Active
1: Not active
Note: This bit is for internal PCIe PHY reset and its default value
is ‘high’. Software must set this bit to ‘low’ for longer than
100ms to generate a REFCLK for the RTL8196E and any
external device.
6
P1_clk_req_en
Auxiliary State Enable.
1: Enable
0: Disable
5
Low_power enable
Enter Lower Power State Enable.
1: Enable
0: Disable
4
Sys_aux_pwr_det
System Detect Auxiliary Power Stable.
1: Stable
0: Unstable
3
App_ready_enter_l23 Application User Ready Enter L23 when Device in D3 Hot/Cold.
2
App_req_exit_l1
Application Request Exit L1 State.
1
App_req_enter_l1
Application Request Enter L1 State.
0
App_ltssm_en
Application User LTSSM Enable.
1: Enable LTSSM
0: Hold LTSSM in initial state
10.3.5.
PCIe IP Configuration Register (0xB8B0_100C)
Reg.bit
15:8
7:3
2:0
Table 55. PCIe IP Configuration Register (0xB8B0_100C)
Name
Description
Bus_num
Target Bus Number (265 Types).
Dev_num
Target Device Number (32 Types).
Fun_num
Target Function Number (8 Types).
10.3.6.
Reg.bit
31:0
Mode
RW
RW
RW
Default
0B
0B
0B
RW
1B
RW
0B
RW
0B
RW
0B
RW
RW
RW
RW
0B
0B
0B
1B
Mode
RW
RW
RW
Default
0H
0H
0H
Mode
R
Default
0H
PCIe SRAM BIST Check Register (0xB8B0_1010)
Table 56. PCIe SRAM BIST Check Register (0xB8B0_1010)
Name
Description
Bist_fail_chk
SRAM BIST Fail Check.
5-Port 10/100M Ethernet Router Network Processor
40
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
11. Switch Core Control
11.1. Global Port Control Register
11.1.1. Global Port Control Register Address Mapping
(Base: 0xBB80_4000)
The RTL8196E provides an MDC/MDIO (Management Data Clock/Management Data Input/Output)
interface to access embedded PHYs. As the MDC/MDIO interface is relatively slow, the access is divided
into command and status registers.
Offset
04
08
Table 57. Global Port Control Register Address Mapping (Base: 0xBB80_4000)
Size (byte)
Name
Description
4
MDCIOCR
MDC/MDIO Command Register.
4
MDCIOSR
MDC/MDIO Status Register.
11.1.2. Global MDC/MDIO Command Register (0xBB80_4004)
Reg.bit
31
30:29
28:24
23:21
20:16
15:0
Table 58. Global MDC/MDIO Command Register (0xBB80-4004)
Name
Description
COMMAND MDC/MDIO Command Type.
0: Read Access
1: Write Access
Note: The procedure to access the external PHY via the
MDC/MDIO interface is as follows:
1. Define the PHY address (PHYADD), register address (REGADD)
2. Define the write data content for write command (WRDATA)
3. Identify the command type (COMMAND)
4. Get the command execution status (STATUS) and read data
content (RDATA)
Reserved.
PHYADD[4:0] PHY Address of MDC/MDIO Command.
Reserved.
REGADD[4:0] Register Address of MDC/MDIO Command.
WRDATA[15:0] Write Data of MDC/MDIO Command.
5-Port 10/100M Ethernet Router Network Processor
41
Mode
RW
Default
0B
RW
RW
RW
00000B
00000B
0000H
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
11.1.3. Global MDC/MDIO Status Register (0xBB80_4008)
Reg.bit
31
30:16
15:0
Table 59. Global MDC/MDIO Status Register (0xBB80_4008)
Name
Description
STATUS
MDC/MDIO Command in Process Status.
0: Process done
1: In progress
Reserved.
RDATA
Read Data Result of MDC/MDIO Command.
Mode
R
Default
0000B
R
0B
11.1.4. Global Frame Filtering Control Register Address Mapping
(Base: 0xBB80_4000)
Table 60. Global Frame Filtering Control Register Address Mapping (Base: 0xBB80_4000)
Offset
Size (byte)
Name
Description
44
4
BSCR
Broadcast Storm Control Register.
11.1.5. Global Broadcast Storm Control Register (0xBB80_4044)
Per-port broadcast storm traffic utilization is a global parameter that is defined by BCSC_CNT[14:0] in
the Broadcast Storm Control Register (0xBB80_4044). Broadcast storm control can be enabled/disabled
on a per-port basis, and the broadcast traffic definition is user configurable.
Table 61. Global Broadcast Storm Control Register (0xBB80_4044)
Name
Description
Mode
Default
Reserved.
BCSC_CNT[14:0] Broadcast Storm Control Rate Configuration.
RW
0
Defines the per-port-based broadcast storm control valid
accumulated byte count in each default time interval
25ms/2.5ms/0.25ms for 10M/100M/1000M (the time interval
will auto update for different port link speeds).
For BCSC_BCNT[14:0] value=N.
The % max rate=N/30360*100%.
Note: When Broadcast Storm Control is enabled, every 25ms, each port will limit the max incoming byte counts of
broadcast, multicast, or unknown-unicast packets to 3 counts maximum. Other excessive packets within the duration time
will be dropped.
Reg.bit
31:15
14:0
5-Port 10/100M Ethernet Router Network Processor
42
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
11.2. Per-Port Configuration Register
The port ability properties, e.g., auto negotiation, port speed, duplex, flow control, can be configured via
the Per-Port Configuration Register.
Offset
00
04
08
0C
10
14
1C
20
24
28
2C
30
34
38
40
44
48
Table 62. Per-Port Configuration Register Address Mapping (Base: 0xBB80_4100)
Size (byte)
Name
Description
4
PITCR
Port Interface Type Control Register.
4
PCRP0
Port Configuration Register of Port 0.
4
PCRP1
Port Configuration Register of Port 1.
4
PCRP2
Port Configuration Register of Port 2.
4
PCRP3
Port Configuration Register of Port 3.
4
PCRP4
Port Configuration Register of Port 4.
4
PCRP6
Port Configuration Register of Port 6 (Ext. P0).
4
PCRP7
Port Configuration Register of Port 7 (Ext. P1).
4
PCRP8
Port Configuration Register of Port 8 (Ext. P2).
4
PSRP0
Port Status Register of Port 0.
4
PSRP1
Port Status Register of Port 1.
4
PSRP2
Port Status Register of Port 2.
4
PSRP3
Port Status Register of Port 3.
4
PSRP4
Port Status Register of Port 4.
4
PSRP6
Port Status Register of Port 6.
4
PSRP7
Port Status Register of Port 7.
4
PSRP8
Port Status Register of Port 8.
11.2.1. Port Interface Type Control Register (0xBB80_4100)
Reg.bit
31:10
9:8
7:6
5:4
3:2
1:0
Table 63. Port Interface Type Control Register (0xBB80_4100)
Name
Description
Reserved.
Port4_TypeCfg[1:0] Port 4 Interface Type Configuration.
00: UTP (10/100M embedded PHY)
01: Reserved
1x: Reserved
Port3_TypeCfg[1:0] Port 3 Interface Type Configuration.
00: UTP (10/100M embedded PHY)
01: Reserved
1x: Reserved
Port2_TypeCfg[1:0] Port 2 Interface Type Configuration.
00: UTP (10/100M embedded PHY)
01: Reserved
1x: Reserved
Port1_TypeCfg[1:0] Port 1 Interface Type Configuration.
00: UTP (10/100M embedded PHY)
01: Reserved
1x: Reserved
Port0_TypeCfg[1:0] Port 0 Interface Type Configuration.
00: UTP (10/100M embedded PHY)
01: Reserved
1x: Reserved
5-Port 10/100M Ethernet Router Network Processor
43
Mode
RW
Default
00B
RW
00B
RW
00B
RW
00B
RW
00B
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
11.2.2.
Reg.bit
31
30:26
25
24
23
22:18
Port Configuration Register of Port N (N=0~4)
Table 64. Port Configuration Register of Port N (N=0~4)
Name
Description
ByPassTCRC
1: Do not recalculate CRC for CRC error frame
0: Recalculate CRC for CRC error frame
ExtPHYID[4:0]
PHY ID Assign for PHY MII Register Polling Addressing.
Identifies the external PHY ID for MDC/MDIO polling
addressing. Only valid for ports 0~4.
EnForceMode
Enable Port Property (Link/Speed/Duplex/Flow Control) to be
Set by Force Mode.
0: Disable (enable Auto-Negotiation)
In this mode, the port link/speed/duplex /flow control setting
is based on the MDC/MDIO polling result.
1: Enable (Force Mode) (Disable Auto-Negotiation)
In this mode, the port speed/duplex /flow control setting is set
by the force mode control bits in this register. Note that the
method of determining the link status depends on the
PollinkStatus setting.
PollinkStatus
Polling PHY Link Status {EnForceMode, PollinkStatus}.
00, 01: Enable Auto-Negotiation
10: ForceMode. Disables Auto-Negotiation (this mode should
be set for MAC-to-MAC connection)
11: ForceMode with polling link status. Disables AutoNegotiation but polls the PHY’s link status.
ForceLink
Force Link-Up or Link-Down Setting. Available Only If
{EnForceMode, PollinkStatus}=10.
0: Force link down
1: Force link up
Note: If {EnForceMode, PollinkStatus}=11, the link status
information is derived from PHY register 1 via the ASIC’s
auto-polling mechanism.
FrcAbi_AnAbi_sel
If EnForceMode=1, FrcAbi_AnAbi_sel is used to indicate the
force mode operation for MAC or PHY mode operations.
FrcAbi_AnAbi_sel[0]: ForceDuplex
1: Force FULL duplex
0: Force HALF duplex
FrcAbi_AnAbi_sel[2:1]: ForceSpeed
00: Force 10Mbps
01: Force 100Mbps
10: Reserved
11: Reserved
FrcAbi_AnAbi_sel[4:3]: Reserved.
Mode
RW
Default
0B
RW
Port0~4
=0x0~4
RW
0
RW
0
RW
0
RW
5’b11111 for
port#0~4
If EnForceMode=0, FrcAbi_AnAbi_sel is used to indicate
Auto-Negotiation advertising ability.
FrcAbi_AnAbi_sel[0]: 10Mbps Half-duplex
FrcAbi_AnAbi_sel[1]: 10Mbps Full-duplex
FrcAbi_AnAbi_sel[2]: 100Mbps Half-duplex
FrcAbi_AnAbi_sel[3]: 100Mbps Full-duplex
FrcAbi_AnAbi_sel[4]: Reserved
5-Port 10/100M Ethernet Router Network Processor
44
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
Reg.bit
Name
Description
17:16 PauseFlowControl[1:0] If EnForceMode=1, this register controls PAUSE flow
control.
(ADVERTISE_
PAUSEABY)
0: Enable TX pause ability
1: Enable RX pause ability
15:12
11:9
BCSC_Types[2:0]
8
EnBCSC
7
EnLoopBack
6
DisBKP
5:4
STP_PortST[1:0]
If EnForceMode=0, the PHY advertises PAUSE flow control.
0: PAUSE operation for full duplex links
1: Asymmetric PAUSE operation for full duplex links
Reserved
Broadcast Storm Control Packet Types Selection.
When Broadcast storm control is enabled, the control packet
types can be selected.
Bit[0]: Enable control for broadcast packets
Bit[1]: Enable control for multicast packet
Bit[2]: Reserved
0: Disable
1: Enable
When Bit[3:0] are set as ‘000’, the port’s broadcast storm
function is disabled.
Enable Broadcast Storm Control.
0: Disable
1: Enable
When enabled, the broadcast storm control rate and control
packet type should be defined in the broadcast storm control
register.
Enable MAC – PHY Interface for MII Loopback.
Enable internal and external loopback. Sets the MAC as an
internal loopback, and sets the PHY side as an external
loopback.
0: Disable
1: Enable
Per-Port Disable Backpressure Function for Half Duplex
Mode.
1: Disable
0: Enable
Spanning Tree Protocol Port State Control.
00: Disable State
01: Blocking/Listen State
10: Learning State
11: Forwarding State
802.1d Port
State
Pass
Received
Non-BPDU
Frames
Disabled
Blocking
Listening
Learning
Forwarding
No
No
No
No
Yes
5-Port 10/100M Ethernet Router Network Processor
Mode
RW
Default
2’b11
RW
0B
RW
0B
RW
0B
RW
0B
RW
11
Learning
Pass
Station
Received
Location Into
BPDU
Address
Frames
Database
No
No
Yes
No
Yes
No
Yes
Yes
Yes
Yes
45
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
Reg.bit
3
Name
MAC S/W Reset
2:1
AcptMaxLen[1:0]
0
EnablePHYIf
Description
MAC S/W Reset supports a method to reset the MAC by
software. It can reset the circuit in the RXC and TXC domain
via an active-low signal. To reset the MAC, software should
write a 1 following the writing of a 0 .
0: Reset state
1: Normal state
Configures the Maximum Acceptable Packet Length
Supported.
This control is valid only when jumbo packet accept is
disabled on a port.
00: 1536 bytes
01: 1552 bytes
10: 9k bytes (jumbo packet: 9216 bytes)
11: 16k~14 bytes (jumbo packet: 16370 bytes)
Enable PHY Interface.
The bit controls the MAC vs. PHY interface, irrelevant as to
whether the port interface is UTP.
0: Disable
When disabled, the PHY interface will be isolated from the
MAC. Packets will not be transmitted or received to/from the
PHY to/from the MAC interface.
1: Enable
5-Port 10/100M Ethernet Router Network Processor
46
Mode
RW
Default
1
RW
00B
RW
0B
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
11.2.3.
Reg.bit
31:14
13:12
11:9
8
7:0
Port Status Register of Port N (N=0~4)
Table 65. Port Status Register of Port N (N=0~4)
Description
Reserved.
Port Link Status.
In NWay Mode, the status shown is that of PHY local and PHY
remote ability.
In Force mode, the status is the configuration result of the force
mode configuration registers.
Bit 1: Reserved
Bit 0: 100M EEE ability
Reserved.
LinkDownEventFlag Port Link Down Event Detection Monitor Flag
0: Idle
1: Link Down event detected
When the Port link status changes from link-up to link-down, the
flag bit will be latched as ‘1’ until read to clear and updated to the
new status.
PortStatus[7:0]
Port Link Status
In an NWay Mode port, the status shown is that of PHY local and
PHY remote ability.
In Force mode, the status is the configuration result of the force
mode configuration registers.
This report is valid for UTP Interface mode.
Bit 7: NWay Enable (link by auto-negotiation)
Bit 6: RX PAUSE ability
Bit 5: TX PAUSE ability
Bit 4: LinkUp
Bit 3: Duplex
Bit 2: Reserved
Bit [1:0] LinkSpeed[1:0]
LinkSpeed[1:0]:
00: 10M
01: 100M
10: Reserved
11: Reserved
Name
EEE Status[1:0]
5-Port 10/100M Ethernet Router Network Processor
47
Mode
R
Default
0
Latch,
RW
0
R
0
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
12. Green Ethernet
12.1. Cable Length Power Saving
The RTL8196E provides link-on and dynamic detection of cable length, and dynamic adjustment of
power required for the detected cable length. This feature provides high performance with minimum
power consumption.
12.2. Link-Down Power Saving
The RTL8196E implements link-down power saving on a per-port basis, greatly cutting power
consumption when the network cable is disconnected. A port automatically enters link-down power
saving mode ten seconds after the cable is disconnected from it. Once a port enters link-down power
saving mode, it transmits normal link pulses on its TXOP/TXON pins and continues to monitor the
RXIP/RXIN pins to detect incoming signals, which might be 100Base-TX MLT-3 idle pattern, 10Base-T
link pulses, or Auto-Negotiation’s FLP (Fast Link Pulse). After it detects an incoming signal, it wakes up
from link-down power saving mode and operates in normal mode according to the result of the
connection’s auto-negotiation.
12.3. Energy Efficient Ethernet (EEE)
The RTL8196E supports IEEE 802.3az, also known as Energy Efficient Ethernet (EEE) in 100Base-TX
in full duplex operation, and 10Base-T in full/half duplex mode. It provides a protocol to coordinate
transitions to/from a lower power consumption level (Low Power Idle mode) based on link utilization.
When no packets are being transmitted, the system goes to Low Power Idle mode to save power. Once
packets need to be transmitted, the system returns to normal mode, and does this without changing the
link status and without dropping/corrupting frames.
To save power, when the system is in Low Power Idle mode, most of the circuits are disabled, however,
the transition time to/from Low Power Idle mode is kept small enough to be transparent to upper layer
protocols and applications.
EEE also specifies a negotiation method to enable link partners to determine whether EEE is supported
and to select the best set of parameters common to both devices.
• For 100Base-TX PHY: Supports Energy Efficient Ethernet with the optional function of Low Power
Idle.
• For 10Base-T, EEE defines a 10Mbps PHY (10Base-Te) with reduced transmit amplitude
requirements. 10Base-Te is fully interoperable with 10Base-T PHYs over 100m of class-D (Cat-5)
cable.
The RTL8196E MAC uses Low Power Idle signaling to indicate to the PHY and to the link partner that a
break in the data stream is expected. Components may use this information to enter power saving modes
that require additional time to resume normal operation. Similarly, it informs the LPI Client that the link
partner has sent such an indication.
5-Port 10/100M Ethernet Router Network Processor
48
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
13. DC Specifications
13.1. Operating Conditions
Symbol
VDD33
AVDD33
VDD10
AVDD10
AVDD33X
AVDD33_BG
AVDD10_PCIE
AVDD10_PHYPLL
AVDD33_PHYPLL
AVDD33_USB
AVDD10_USB
AVDD33_SWR
VDD33_LDO_IN
VDD33_25
VREF
Table 66. Operating Conditions
Parameter
Min.
Digital I/O Power Supply 3.3V
3.135
Analog Power Supply 3.3V
3.135
Core Power Supply 1.0V
0.95
Analog Power Supply 1.0V
0.95
25/40MHz Crystal Power 3.3V
3.135
System Bandgap Power Supply 3.3V
3.135
PCI Express Analog Power 1.0V
0.95
Ethernet PHY PLL Power 1.0V
0.95
Ethernet PHY PLL Power 3.3V
3.135
USB2.0 Analog Power 3.3V
3.135
USB2.0 Analog Power 1.0V
0.95
SWR Power Input 3.3V
3.135
LDO Power Input 3.3V
3.135
3.135
SDR DRAM I/O Power Supply 3.3V
2.4
DDR1 DRAM I/O Power Supply 2.5V
1.7
DDR2 DRAM I/O Power Supply 1.8V
DDR1/DDR2 Reference Voltage
0.49*VDD
33_25
Typ.
3.3
3.3
1.00
1.00
3.3
3.3
1.00
1.00
3.3
3.3
1.00
3.3
3.3
3.3
2.5
1.8
0.5*VDD
33_25
Max.
3.465
3.465
1.05
1.05
3.465
3.465
1.05
1.05
3.465
3.465
1.05
3.465
3.465
3.465
2.7
1.9
0.51*VDD
33_25
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
13.2. Total Power Consumption
Table 67. Total Power Consumption
SYM
Conditions
Min
PS
All LAN Ports Idle
LAN Full Load Active for Link at 100Base-TX
Note: Power consumption is measured at full load of the chip system.
5-Port 10/100M Ethernet Router Network Processor
49
Typ.
0.31
0.87
Max
-
Track ID: JATR-3375-16
Units
Watt
Rev. 1.0
RTL8196E
Datasheet
13.3. SDR DRAM Bus DC Parameters
Table 68. SDR DRAM Bus DC Parameters
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
VIH
Input-High Voltage
LVTTL
2.0
V
1
VIL
Input-Low Voltage
LVTTL
0.8
V
2
VOH
Output-High Voltage
2.4
V
3
VOL
Output-Low Voltage
0.4
V
3
IIL
Input-Leakage Current
VIN=3.3V or 0
-10
10
±1
µA
IOZ
Tri-State Output-Leakage Current
-10
10
±1
µA
RPU
Input Pull-Up Resistance
75
KΩ
4
RPD
Input Pull-Down Resistance
75
KΩ
4
Note 1: VIH overshoot: VIH (MAX)=VDDH + 2V for a pulse width ≤ 3ns, and the pulse width not greater than one third of the
cycle rate.
Note 2: VIL undershoot: VIL (MIN)=-2V for a pulse width ≤ 3ns cannot be exceeded.
Note 3: The output current buffer is 16mA for SDR DRAM clock, address, and data bus.
Note 4: These values are typical values checked in the manufacturing process and are not tested.
13.4. DDR DRAM Bus DC Parameters
Symbol
VIH
VIL
VTT
IIL
IOZ
Table 69. DDR DRAM Bus DC Parameters
Parameter
Conditions
Min.
Input-High Voltage
SSTL_2
VREF+0.15
Input-Low Voltage
SSTL_2
-0.3
I/O Termination Voltage
VREF-0.04
Input-Leakage Current
VIN=VREF or 0
-10
Tri-State Output-Leakage Current
-10
Typ.
±1
±1
Max.
VREF+0.3
VREF-0.15
VREF+0.04
10
10
Units
V
V
V
µA
µA
13.5. Flash Bus DC Parameters
Table 70. Flash Bus DC Parameters
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
VIH
Input-High Voltage
LVTTL
2.0
V
1
VIL
Input-Low Voltage
LVTTL
0.8
V
2
VOH
Output-High Voltage
2.4
V
3
VOL
Output-Low Voltage
0.4
V
3
IIL
Input-Leakage Current
VIN=3.3V or 0
-10
10
±1
µA
IOZ
Tri-State Output-Leakage Current
-10
10
±1
µA
RPU
Input Pull-Up Resistance
75
KΩ
4
RPD
Input Pull-Down Resistance
75
KΩ
4
Note 1: VIH overshoot: VIH (MAX)=VDDH + 2V for a pulse width ≤ 3ns.
Note 2: VIL undershoot: VIL (MIN)=-2V for a pulse width ≤ 3ns.
Note 3: The output current buffer is 8mA for the flash address and data bus; and is 8mA for Flash control signals.
Note 4: These values are typical values checked in the manufacturing process and are not tested.
5-Port 10/100M Ethernet Router Network Processor
50
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
13.6. USB v1.1 DC Parameters
Table 71. USB v1.1 DC Parameters
Symbol Parameter
Conditions
Min.
Typ.
Max.
VIH
Input-High Voltage
2.0
VIL
Input-Low Voltage
0.8
VOH
Output-High Voltage
2.4
VOL
Output-Low Voltage
0.4
IIL
Input-Leakage Current
VIN=3.3V or 0
Note 1: These values are typical values checked in the manufacturing process and are not tested.
Note 2: For additional information, see the USB v1.1 Specification.
Units
V
V
V
V
µA
Notes
2
2
2
2
1
Units
mV
mV
mV
mV
µA
Notes
2
2
2
2
1
Units
V
V
V
V
µA
KΩ
KΩ
Notes
1
1
2
2
2
13.7. USB v2.0 DC Parameters
Table 72. USB v2.0 DC Parameters
Symbol Parameter
Conditions
Min.
Typ.
Max.
VIH
Input-High Voltage
200
VIL
Input-Low Voltage
10
VOH
Output-High Voltage
300
500
VOL
Output-Low Voltage
-10
10
IIL
Input-Leakage Current
Note 1: These values are typical values checked in the manufacturing process and are not tested.
Note 2: For additional information, see the USB v2.0 Specification.
13.8. UART DC Parameters
Table 73. UART DC Parameters
Symbol Parameter
Conditions
Min.
Typ.
Max.
VIH
Input-High Voltage
LVTTL
2.0
VIL
Input-Low Voltage
LVTTL
0.8
VOH
Output-High Voltage
2.4
VOL
Output-Low Voltage
0.4
IIL
Input-Leakage Current
VIN=3.3V or 0
-10
10
±1
RPU
Input Pull-Up Resistance
75
RPD
Input Pull-Down Resistance
75
Note 1: The output current buffer is 8mA for UART related signals.
Note 2: These values are typical values checked in the manufacturing process and are not tested.
5-Port 10/100M Ethernet Router Network Processor
51
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
13.9. GPIO DC Parameters
Table 74. GPIO DC Parameters
Symbol Parameter
Conditions
Min.
Typ.
Max.
VIH
Input-High Voltage
LVTTL
2.0
VIL
Input-Low Voltage
LVTTL
0.8
VOH
Output-High Voltage
2.4
VOL
Output-Low Voltage
0.4
IIL
Input-Leakage Current
-10
10
±1
RPD
Input Pull-Down Resistance
75
Note 1: The output current buffer is 8mA for GPIO related signals.
Note 2: These values are typical values checked in the manufacturing process and are not tested.
Units
V
V
V
V
µA
KΩ
Notes
1
1
2
2
Units
V
V
V
V
Notes
1
1
2
2
13.10. JTAG DC Parameters
Table 75. JTAG DC Parameters
Symbol Parameter
Conditions
Min.
Typ.
Max.
VIH
Input-High Voltage
LVTTL
2.0
VIL
Input-Low Voltage
LVTTL
0.8
2.4
VOH
Output-High Voltage
⎢IOH⎢=2~16mA
0.4
VOL
Output-Low Voltage
⎢IOL⎢=2~16mA
IIL
Input-Leakage Current
-10
10
±1
RPD
Input Pull-Down Resistance
75
Note 1: The output current buffer is 4mA for JTAG related signals.
Note 2: These values are typical values checked in the manufacturing process and are not tested.
µA
KΩ
13.11. Reset DC Parameters
Symbol
VIH
VIL
Parameter
Input-High Voltage
Input-Low Voltage
Table 76. Reset DC Parameters
Conditions
Min.
LVTTL
2.0
LVTTL
-
Typ.
-
Max.
0.8
Units
V
V
Typ.
-
Max.
0.4
Units
V
V
13.12. LED DC Parameters
Table 77. LED DC Parameters
Symbol Parameter
Conditions
Min.
VOHED Output-High Voltage
2.4
VOLLED Output-Low Voltage
Note: The output current buffer for LED signals is 8mA.
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Datasheet
14. AC Specifications
14.1. Clock Signal Timing
14.1.1.
25MHz System Clock Timing
Table 78. 25MHz System Clock Timing
Parameter
Min.
Typ.
Max.
Units
Notes
Input-High Voltage
2.0
V
Input-Low Voltage
0.8
V
TFREQUENCY Clock Frequency for RTL8196E Crystal or Oscillator
25
MHz
1
∆FREQUENCY Clock Tolerance Over 0ºC to 50ºC
-50
50
ppm
CSHUNT
7
pF
2
Crystal Parameter (Sometimes Referred to as the
Holder Capacitance)
C1
Load Capacitance
30
pF
3
C2
Load Capacitance
30
pF
3
TDC
Duty Cycle
50
%
Note 1: This value could be an oscillator input or a series resonant frequency from a crystal. If used as an oscillator
input, tie to the crystal input pin and leave the crystal output pin disconnected.
Note 2: The 25MHz Crystal CL=16pF is used on the RTL8196E.
Note 3: The RTL8196E PLL circuit requires an external 25MHz crystal with shunt capacitors. These shunt capacitors
cannot be over 30pF due to chip design requirements.
Symbol
VIH
VIL
Figure 3.
Figure 4.
Typical Connection to a Crystal
Typical Connection to an Oscillator
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14.1.2. 40MHz System Clock Timing
Symbol
VIH
VIL
TFREQUENCY
∆FREQUENCY
TDC
14.1.3.
Table 79. 40MHz System Clock Timing
Parameter
Min.
Typ.
Input-High Voltage
1.2
1.4
Input-Low Voltage
Clock Frequency
40
Clock Tolerance (between 0ºC~70ºC)
-50
Duty Cycle
50
Max.
2.0
0.2
50
-
Units
V
V
MHz
ppm
%
SDR DRAM Clock Timing
Table 80. SDR DRAM Clock Timing
Symbol
Parameter
Min.
Typ.
(156.25MHz)
TPERIOD_SDRAMCLK Clock Period for SDR DRAM Clock
6.4
TCLKHIGH
SDR DRAM Clock High Time
3.2
TCLKLOW
SDR DRAM Clock Low Time
3.2
TRISE/FALL
Rise and Fall Time Requirements for SDR
DRAM Clock
NA
TRISE/FALL_OUTPUT Propagation Delay for Output Rising and
Falling
Note: For detailed information, contact Realtek for the IBIS model.
Max.
Units
Notes
2
ns
ns
ns
ns
-
-
ns
1
0.5V DDH
TCLKHIGH
TCLKLOW
TPERIOD_SDRAMCLK
Figure 5.
SDR DRAM Clock Specifications-1
Figure 6.
SDR DRAM Clock Specifications-2
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14.2. Bus Signal Timing
14.2.1.
14.2.1.1
SDR DRAM Bus
SDR DRAM Input Timing
Table 81. SDR DRAM Input Timing
Symbol
TSETUP
Parameter
Min.
Typ.
Max.
Units
Input Setup Prior to Rising Edge of Clock.
1.13
ns
Inputs included in this timing are MD[15: 0] (during a read operation)
THOLD
Input Hold Time after the Rising Edge of Clock.
0
ns
Inputs included in this timing are MD[15:0] (during a read operation)
Note: The RTL8196E integrates some timing controls on the interface. Here the timing parameters listed in the table are
extracted in the default situation (without specific controls).
Figure 7.
14.2.1.2
SDR DRAM Input Timing
SDR DRAM Output Timing
Table 82. SDR DRAM Output Timing
Symbol Parameter
TCLK2OUT Rising Edge of Clock-to-Signal Output.
Outputs include this timing are MD[15: 0], MCS0#, MCS1#, RAS#, CAS#,
LDQM, UDQM, WE# (during a write operation)
THOLDOUT Signal Output Hold Time after the Rising Edge of the Clock.
Outputs included in this timing are MD[15: 0] (during a write operation)
Note: Timing was tested with 75-pF capacitor to ground.
Figure 8.
5-Port 10/100M Ethernet Router Network Processor
Min.
-
Typ.
-
Max.
2.3
Units
ns
0.8
-
-
ns
SDR DRAM Output Timing
55
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14.2.1.3
SDR DRAM Access Control Timing
Table 83. SDR DRAM Access Control Timing
Parameter
Auto-Refresh Timing.
Controlled by Reg. 0xB8001008 (DTR)
TRCD
The Time Interval between RAS# Active and CAS# Active.
Controlled by Reg. 0xB8001008 (DTR)
TRP
The Time Interval between Pre-Charge and the Next Active.
Controlled by Reg. 0xB8001008 (DTR)
TRAS
The Time Interval between Active and Pre-Charge.
Controlled by Reg. 0xB8001008 (DTR)
TRC
The Time Interval between Active and the Next Active.
Controlled by Reg. 0xB8001008 (DTR)
TRFC
The Time Interval between Auto-Refresh and Active.
Controlled by Reg. 0xB8001008 (DTR)
TCAS_LATENCY The Data Output Delay after CAS# Active.
Controlled by Reg. 0xB8001004 (DCR)
Note: TRC=TRAS+TRP.
Symbol
TREFRESH
Figure 9.
Units
µs
Notes
-
ns
-
ns
-
ns
-
ns
1
ns
-
ns
-
SDR DRAM Access Control Timing
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14.2.2.
14.2.2.1
DDR DRAM Bus
DDR DRAM Input Timing
Table 84. DDR DRAM Input Timing
Symbol
TSETUP
Parameter
Input Setup Prior to Rising Edge of Clock.
Inputs included in this timing are D[31: 0] (during a read operation)
THOLD
Input Hold Time after the Rising Edge of Clock.
Inputs included in this timing are D[31:0] (during a read operation)
Note: The RTL8196E integrates some timing control registers on the interface.
14.2.2.2
Units
ns
Notes
1
ns
1
Units
ns
Notes
1
ns
1
DDR DRAM Output Timing
Table 85. DDR DRAM Output Timing
Symbol
TCLK2OUT
Parameter
Rising Edge of Clock-to-Signal Output.
Outputs include this timing are D[31: 0], CS0#, CS1#, RAS#, CAS#, LDQM,
UDQM, WE#, LDQS, UDQS (during a write operation)
THOLDOUT
Signal Output Hold Time after the Rising Edge of the Clock.
Outputs included in this timing are D[31: 0] (during a write operation)
Note: The RTL8196E integrates some timing control registers on the interface.
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14.2.2.3
DDR DRAM Access Control Timing
Table 86. DDR DRAM Access Control Timing
Symbol
TREFRESH
Parameter
Auto-Refresh Timing.
Controlled by Reg. 0xB8001008 (DTR)
TRCD
The Time Interval between RAS# Active and CAS# Active.
Controlled by Reg. 0xB8001008 (DTR)
TRP
The Time Interval between Pre-Charge and the Next Active.
Controlled by Reg. 0xB8001008 (DTR)
TRAS
The Time Interval between Active and Pre-Charge.
Controlled by Reg. 0xB8001008 (DTR)
TRC
The Time Interval between Active and the Next Active.
Controlled by Reg. 0xB8001008 (DTR)
TRFC
The Time Interval between Auto-Refresh and Active.
Controlled by Reg. 0xB8001008 (DTR)
TCAS_LATENCY
The Data Output Delay after CAS# Active.
Controlled by Reg. 0xB8001004 (DCR)
Note: TRC=TRAS+TRP.
Units
µs
Notes
-
ns
-
ns
-
ns
-
ns
1
ns
-
ns
-
Figure 10. DDR DRAM Access Control Timing
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Datasheet
14.2.3.
14.2.3.1
Symbol
TSLCH
TCHSH
TCLQV
TCLQX
Serial Flash Interface
Serial Flash Interface Output Timing
Table 87. Serial Flash Interface Output Timing
Parameter
Min.
Typ.
2
The Timing Interval from Chip-Select Activated to the
First Clock Rising Edge
5
The Timing Interval from the Last Clock Rising Edge to
Chip-Select De-Activated
The Timing Interval from the Last Clock Falling Edge to
Data-Out Validated
0
The Timing Interval from the Next Clock Falling Edge to
Data-Out Invalidated
Max.
-
Units
ns
-
ns
10
ns
-
ns
Max.
-
Units
ns
-
ns
Figure 11. Serial Flash Interface Output Timing
14.2.3.2
Symbol
TDVCH
TCHDX
Serial Flash Interface Input Timing
Table 88. Serial Flash Interface Input Timing
Parameter
Min.
Typ.
2
The Timing Interval from Data-Input Ready to the Clock
Rising Edge
5
The Timing Interval from the Clock Rising Edge to DataInput Invalidated
Figure 12. Serial Flash Interface Input Timing
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Datasheet
14.2.4.
JTAG Boundary Scan
Table 89. JTAG Boundary Scan Interface Timing Values
Symbol Parameter
Min.
Typ.
Max.
Tbscl
JTAG Clock Low Time
50
Tbsch
JTAG Clock High Time
50
Tbsis
TDI, TMS Setup Time to Rising Edge of TCK
10
Tbsih
TDI, TMS Hold Time from Rising Edge of TCK
10
Tbsoh
TDO Hold Time after Falling Edge of TCK
1.5
Tbsod
TDO Output from Falling Edge of TCK
40
Tbsr
JTAG Reset Period
30
Tbsrs
TMS Setup Time to Rising Edge of JTAG Reset
10
Tbsrh
TMS Hold Time from Rising Edge of JTAG Reset
10
Note 1: JTAG clock TCK may be stopped indefinitely in either the low or high phase.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
-
TCK
TMS, TDI
TDO
Figure 13. Boundary-Scan General Timing
RESET#
TMS
Figure 14. Boundary-Scan Reset Timing
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Datasheet
14.2.5.
Power Configuration Timing
Power up configuration only relates to internal timing. The external hardware pin reset is unconcerned
with power up configuration. The Hardware reset pin is valid when an internal reset ends the active state.
Internal Reset
~
CLK
(25MHz Crystal)
~
The Latest
Stable Power
(1.0V)
300 ms
200 µs
Config Data
(Strapping Pin)
Latch Config Data
Figure 15. Power Up Configuration Timing
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Datasheet
14.3. PCI Express Bus Parameters
14.3.1.
Differential Transmitter Parameters
Table 90. Differential Transmitter Parameters
Symbol
Parameter
Min
Typical
Max
Units
UI
Unit Interval
399.88
400
400.12
ps
VTX-DIFFp-p
Differential Peak-to-Peak Output Voltage
0.800
1.2
V
-3.0
-3.5
-4.0
dB
VTX-DE-RATIO
De-Emphasized Differential Output Voltage
(Ratio)
TTX-EYE
Minimum TX Eye Width
0.75
UI
0.125
UI
TTX-EYE-MEDIAN- to-MAX-JITTER Maximum Time between the Jitter Median
and Maximum Deviation from the Median
TTX-RISE, TTX-FALL
D+/D- TX Output Rise/Fall Time
0.125
UI
20
mV
VTX-CM-ACp
RMS AC Peak Common Mode Output
Voltage
VTX-CM-DCACTIVE- IDLEDELTA
0
100
mV
Absolute Delta of DC Common Mode
Voltage During L0 and Electrical Idle
VTX-CM-DCLINE- DELTA
0
25
mV
Absolute Delta of DC Common Mode
Voltage between D+ and DVTX-IDLE-DIFFp
0
20
mV
Electrical Idle Differential Peak Output
Voltage
VTX-RCV-DETECT
600
mV
The Amount of Voltage Change Allowed
During Receiver Detection
VTX-DC-CM
TX DC Common Mode Voltage
0
3.6
V
ITX-SHORT
TX Short Circuit Current Limit
90
mA
TTX-IDLE-MIN
Minimum Time Spent in Electrical Idle
50
UI
TTX-IDLE- SETTO-IDLE
20
UI
Maximum Time to Transition to A Valid
Electrical Idle After Sending An Electrical
Idle Ordered Set
TTX-IDLE-TOTO- DIFF-DATA
20
UI
Maximum Time to Transition to Valid TX
Specifications After Leaving An Electrical
Idle Condition
RLTX-DIFF
Differential Return Loss
10
dB
RLTX-CM
Common Mode Return Loss
6
dB
ZTX-DIFF-DC
DC Differential TX Impedance
80
100
120
Ω
LTX-SKEW
Lane-to-Lane Output Skew
500+2*UI
ps
CTX
AC Coupling Capacitor
75
200
nF
Tcrosslink
Crosslink Random Timeout
0
1
ms
Note 1: Refer to PCI Express Base Specification, rev.1.1, for correct measurement environment setting of each parameter.
Note 2: The data rate can be modulated with an SSC (Spread Spectrum Clock) from +0 to -0.5% of the nominal data rate
frequency, at a modulation rate in the range not exceeding 30kHz – 33kHz. The ±300ppm requirement still holds, which
requires the two communicating ports be modulated such that they never exceed a total of 600ppm difference.
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Datasheet
14.3.2.
Differential Receiver Parameters
Table 91. Differential Receiver Parameters
Parameter
Min.
Typical
Max.
Units
Unit Interval
399.88
400
400.12
ps
Differential Input Peak-to-Peak Voltage
0.175
1.200
V
Minimum Receiver Eye Width
0.4
UI
0.3
UI
Maximum Time Between the Jitter Median
and Maximum Deviation from the Median
VRX-CM-ACp
AC Peak Common Mode Input Voltage
150
mV
RLRX-DIFF
Differential Return Loss
10
dB
RLRX-CM
Common Mode Return Loss
6
dB
ZRX-DIFF-DC
DC Differential Input Impedance
80
100
120
Ω
ZRX--DC
DC Input Impedance
40
50
60
Ω
ZRX-HIGH-IMP-DC
Powered Down DC Input Impedance
200k
Ω
VRX-IDLE-DET-DIFFp-p
Electrical Idle Detect Threshold
65
175
mV
TRX-IDLE-DET- DIFFENTERTIME
10
ms
Unexpected Electrical Idle Enter Detect
Threshold Integration Time
LRX-SKEW
Total Skew
20
ns
Note: Refer to PCI Express Base Specification, rev.1.1, for correct measurement environment setting of each parameter.
Symbol
UI
VRX-DIFFp-p
TRX-EYE
TRX-EYE-MEDIAN-to- MAX-JITTER
14.3.3.
REFCLK Parameters
Table 92. REFCLK Parameters
Symbol
Parameter
Rise Edge Rate
Fall Edge Rate
VIH
VIL
VCROSS
VCROSS DELTA
VRB
TSTABLE
TPERIOD AVG
TPERIOD ABS
Rising Edge Rate
Falling Edge Rate
Differential Input High Voltage
Differential Input Low Voltage
Absolute Crossing Point Voltage
Variation of VCROSS Over All Rising Clock Edges
Ring-Back Voltage Margin
Time before VRB is Allowed
Average Clock Period Accuracy
Absolute Period
(Including Jitter and Spread Spectrum)
Cycle to Cycle Jitter
Absolute Maximum Input Voltage
Absolute Minimum Input Voltage
Duty Cycle
TCCJITTER
VMAX
VMIN
Duty Cycle
5-Port 10/100M Ethernet Router Network Processor
63
100MHz Input
Min
Max
0.6
4.0
0.6
4.0
+150
-150
+250
+550
+140
-100
+100
500
-300
+2800
9.847
10.203
40
150
+1.15
-0.3
60
Units
Note
V/ns
V/ns
mV
mV
mV
mV
mV
ps
ppm
ns
2, 3
2, 3
2
2
1, 4, 5
1, 4, 9
2, 12
2, 12
2, 10, 13
2, 6
ps
V
V
%
2
1, 7
1, 8
2
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Symbol
Parameter
100MHz Input
Min
Max
20
Rise-Fall Matching
Units
Note
%
1, 14
Rising Edge Rate (REFCLK+) to
Falling Edge Rate (REFCLK-) Matching
ZC-DC
Clock Source DC Impedance
40
60
Ω
1, 11
Note 1: Measurement taken from single-ended waveform.
Note 2: Measurement taken from differential waveform.
Note 3: Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The
signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is
centered on the differential zero crossing. See Figure 19, page 66.
Note 4: Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the
falling edge of REFCLK-. See Figure 16, page 65.
Note 5: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
Refers to all crossing points for this measurement. See Figure 16, page 65.
Note 6: Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative
ppm tolerance, and spread spectrum modulation. See Figure 18, page 65.
Note 7: Defined as the maximum instantaneous voltage including overshoot. See Figure 16, page 65.
Note 8: Defined as the minimum instantaneous voltage including undershoot. See Figure 16, page 65.
Note 9: Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the
maximum allowed variance in VCROSS for any particular system. See Figure 16, page 65.
Note 10: Refer to Section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding ppm
considerations.
Note 11: System board compliance measurements must use the test load card described in Figure 22, page 67. REFCLK+
and REFCLK- are to be measured at the load capacitors CL. Single ended probes must be used for measurements
requiring single ended measurements. Either single ended probes with math or differential probe can be used for
differential measurements. Test load CL=2pF.
Note 12: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after
rising/falling edges before it is allowed to droop back into the VRB ±100mV differential range. See Figure 21, page 67.
Note 13: PPM refers to parts per million and is a DC absolute period accuracy specification. 1ppm is 1/1,000,000th of
100.000000MHz exactly, or 100Hz. For 300ppm then we have an error budget of 100Hz/ppm*300ppm=30kHz. The
period is to be measured with a frequency counter with measurement window set to 100ms or greater. The ±300ppm
applies to systems that do not employ Spread Spectrum or that use common clock source. For systems employing Spread
Spectrum there is an additional 2500ppm nominal shift in maximum period resulting from the 0.5% down spread resulting
in a maximum average period specification of +2800ppm.
Note 14: Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a
±75mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross
point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge
Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-; the maximum allowed difference should not
exceed 20% of the slowest edge rate. See Figure 17, page 65.
Note 15: Refer to PCI Express Card Electromechanical Specification, rev.1.1, for correct measurement environment
setting of each parameter.
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Figure 16. Single-Ended Measurement Points for Absolute Cross Point and Swing
Figure 17. Single-Ended Measurement Points for Delta Cross Point
Figure 18. Single-Ended Measurement Points for Rise and Fall Time Matching
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Datasheet
Figure 19. Differential Measurement Points for Duty Cycle and Period
Figure 20. Differential Measurement Points for Rise and Fall Time
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Datasheet
Figure 21. Differential Measurement Points for Ringback
Figure 22. Reference Clock System Measurement Point and Loading
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Datasheet
15. Thermal Characteristics
Heat generated by the chip causes a temperature rise of the package. If the temperature of the chip (Tj,
junction temperature) is beyond the design limits, there will be negative effects on operation and the life
of the IC package. Heat dissipation, either through a heat sink or electrical fan, is necessary to provide a
reasonable environment (Ta, ambient temperature) in a closed case. As power density increases, thermal
management becomes more critical. A method to estimate the possible Ta is outlined below.
Thermal parameters are defined as below according to JEDEC standard JESD 51-2, 51-6:
(1) θja (Thermal resistance from junction to ambient), represents resistance to heat flow from the chip to
ambient air. This is an index of heat dissipation capability. A lower θja means better thermal
performance.
θja=(Tj-Ta)/P
Where Tj is the die junction temperature, Ta is the ambient air temperature,
P is the power dissipation by device (Watts)
(2) θjc (Thermal Resistance Junction-to-Case, °C/W ), measures the heat flow resistance between the die
surface and the surface of the package (case). This data is relevant for packages used with external
heatsinks.
θjc=(Tj-Tc)/P
Where Tj is the die junction temperature, Tc is the package case temperature.
P is the power dissipation by device (Watts)
(3) Ψjt (Thermal Characterization Parameter: Junction to package top), represents the correlation between
the temperature of the chip and the package top.
Ψjt=(Tj-Tt)/P
Where Tj is the die junction temperature, Tt is the top of package temperature.
P is the power dissipation by the device (Watts)
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Datasheet
Thermal Terminology
The major thermal dissipation paths can be illustrated as following:
Tj: The maximum junction temperature
Ta: The ambient or environment temperature
Tc: The maximum compound surface temperature
Tb: The maximum surface temperature of PCB bottom
P: Total input power
P
PQFP Junction to ambient thermal resistance, θja,
defined as:
θja =
TJ - TA
P
Tc
•
Tj
•
•
Ta
Ta
Tb
Thermal Dissipation of PQFP Package
15.1. Thermal Operating Range
Table 93. Thermal Operating Range
Parameter
SYM Condition
Min
Junction Operating Temperature
Tj
0
Ambient Operating Temperature
Ta
4-layer FR4 PCB (without heat sink)
0
Note: PCB conditions (JEDEC JESD51-7). Dimensions: 120mm x 90mm. Thickness: 1.6mm.
Typ.
25
Max
125
65
Units
°C
°C
15.2. Thermal Parameters
Parameter
Table 94. Thermal Parameters
SYM
Condition
Thermal Resistance: Junction to Ambient
Thermal Resistance: Junction to Ambient
Thermal Characterization: Junction to Package Top
Thermal Characterization: Junction to Package Top
Thermal Resistance: Junction to Case
Thermal Resistance: Junction to Case
5-Port 10/100M Ethernet Router Network Processor
θja
θja
Ψjt
Ψjt
4-layer FR4 PCB
2-layer FR4 PCB
4-layer FR4 PCB
2-layer FR4 PCB
4-layer FR4 PCB
2-layer FR4 PCB
θjc
θjc
69
Air Flow
0 m/s
42.1
44.8
0.23
0.25
9.15
9.19
Track ID: JATR-3375-16
Units
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Rev. 1.0
RTL8196E
Datasheet
16. Mechanical Dimensions
Low Profile Plastic Quad Flat Package 128 Lead 14x14mm Outline
k
e
t
l
a
e
R
Symbol
Dimension in mm
Dimension in inch
Min
Nom
Max
Min
Nom
Max
A
—
—
1.60
—
—
0.063
A1
0.05
—
0.15
0.002
—
0.006
A2
1.35
1.40
1.45
0.053
0.055
0.057
b
0.13
0.18
0.23
0.005
0.007
0.090
D/E
16.00BSC
0.630BSC
D1/E1
14.00BSC
0.551BSC
e
0.40BSC
0.016BSC
L
0.45
0.60
0.75
0.018
L1
1.00REF
Note 1: CONTROLLING DIMENSION: MILLIMETER(mm).
Note 2: REFERENCE DOCUMENT: JEDEC MS-026.
5-Port 10/100M Ethernet Router Network Processor
0.024
0.030
0.039REF
70
Track ID: JATR-3375-16
Rev. 1.0
RTL8196E
Datasheet
17. Ordering Information
Table 95. Ordering Information
Part Number
Package
RTL8196E-CG
Low Profile Plastic Quad Flat Package 128 ‘Green’ Package
Note: See page 5 for package identification information.
Status
Mass Production
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu, 300, Taiwan, R.O.C.
Tel: +886-3-5780211 Fax: +886-3-5776047
www.realtek.com
5-Port 10/100M Ethernet Router Network Processor
71
Track ID: JATR-3375-16
Rev. 1.0