RTL8812BRH-VN-CG

RTL8812BRH-VN-CG Single-Chip 802.11ac/a/n 2T2R WLAN With PCI Express Interface DATASHEET (CONFIDENTIAL: Development Partners Only) Rev. 0.1 14, Sep. , 2017 Track ID: Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com RTL8812BRH-VN-CG Datasheet COPYRIGHT © 2017 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the software engineer’s reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. ELECTROSTATIC DISCHARGE (ESD) WARNING This product can be damaged by Electrostatic Discharge (ESD). When handling, care must be taken. Damage due to inappropriate handling is not covered by warranty. Do not open the protective conductive packaging until you have read the following, and are at an approved anti-static workstation.      Use an approved anti-static mat to cover your work surface. Use a conductive wrist strap attached to a good earth ground Always discharge yourself by touching a grounded bare metal surface or approved anti-static mat before picking up an ESD-sensitive electronic component If working on a prototyping board, use a soldering iron or station that is marked as ESD-safe Always disconnect the microcontroller from the prototyping board when it is being worked on REVISION HISTORY Revision 0.1 Release Date 2017/07/21 Summary Preliminary release. Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface ii Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet Table of Contents 1. GENERAL DESCRIPTION .............................................................................................................................................. 1 2. FEATURES ......................................................................................................................................................................... 2 3. APPLICATION DIAGRAMS ........................................................................................................................................... 4 3.1. 4. PIN ASSIGNMENTS ......................................................................................................................................................... 5 4.1. 5. PACKAGE IDENTIFICATION & MARK INFORMATION .................................................................................................... 6 PIN DESCRIPTIONS ........................................................................................................................................................ 6 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. 5.8. 6. 5GHZ-BAND 2X2 RF APPLICATION ............................................................................................................................. 4 POWER ON TRAP PIN ................................................................................................................................................... 6 PCI EXPRESS TRANSCEIVER INTERFACE ...................................................................................................................... 7 EEPROM INTERFACE .................................................................................................................................................. 7 RF INTERFACE ............................................................................................................................................................. 7 LED INTERFACE .......................................................................................................................................................... 8 POWER MANAGEMENT HANDSHAKE INTERFACE ......................................................................................................... 8 CLOCK AND OTHER PINS.............................................................................................................................................. 8 POWER PINS ................................................................................................................................................................. 9 ELECTRICAL AND THERMAL CHARACTERISTICS ........................................................................................... 11 6.1. TEMPERATURE LIMIT RATINGS .................................................................................................................................. 11 6.2. DC CHARACTERISTICS ............................................................................................................................................... 11 6.2.1. Power Supply Characteristics ............................................................................................................................. 11 6.2.2. Digital IO Pin DC Characteristics ....................................................................................................................... 11 7. INTERFACE TIMING SPECIFICATION .................................................................................................................... 12 7.1. 8. MECHANICAL DIMENSIONS...................................................................................................................................... 13 8.1. 9. PCIE BUS DURING POWER ON SEQUENCE .................................................................................................................. 12 MECHANICAL DIMENSIONS NOTES ............................................................................................................................ 14 ORDERING INFORMATION ........................................................................................................................................ 15 Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface iii Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet List of Tables TABLE 1. POWER-ON TRAP PINS ............................................................................................................................................ 6 TABLE 2. PCI EXPRESS TRANSCEIVER INTERFACE ................................................................................................................. 7 TABLE 4. EEPROM INTERFACE .................................................................................................................................................... 7 TABLE 5. RF INTERFACE ............................................................................................................................................................... 7 TABLE 6. LED INTERFACE...................................................................................................................................................... 8 TABLE 7. POWER MANAGEMENT HANDSHAKE INTERFACE ........................................................................................................... 8 TABLE 8. CLOCK AND OTHER PINS ......................................................................................................................................... 8 TABLE 9. POWER PINS ............................................................................................................................................................ 9 TABLE 10. TEMPERATURE LIMIT RATINGS ............................................................................................................................. 11 TABLE 11. DC CHARACTERISTICS .......................................................................................................................................... 11 TABLE 12. 3.3V GPIO DC CHARACTERISTICS ....................................................................................................................... 11 TABLE 15. THE TYPICAL TIMING RANGE ................................................................................................................................. 12 TABLE 17. DIMENSIONS INFORMATION .................................................................................................................................. 14 TABLE 18. ORDERING INFORMATION...................................................................................................................................... 15 List of Figures FIGURE 1. FIGURE 2. FIGURE 3. 5GHZ-BAND 2X2 SOLUTION(11AC 2X2 MAC/BB/RF + PA) SOLUTION --- RTL8812BRH-VN-CG ...................... 4 PIN ASSIGNMENTS ................................................................................................................................................... 5 RTL8812BRH-VN-CG PCIE BUS POWER ON SEQUENCE .................................................................................... 12 Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface iv Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet 1. General Description The Realtek RTL8812BRH-VN-CG is a highly integrated single-chip that support 2-stream 802.11ac solutions with Wireless LAN (WLAN) PCI Express network interface. It combines a WLAN MAC, a 2T2R capable WLAN baseband, and RF in a single chip. The RTL8812BRH-VN-CG baseband implements Orthogonal Frequency Division Multiplexing (OFDM) with two transmit and two receive paths (2T2R). Features include two spatial stream transmissions, short Guard Interval (GI) of 400ns, spatial spreading, and support for variant channel bandwidth. Moreover, RTL8812BRH-VN-CG provides one spatial stream space-time block code (STBC), Transmit Beamforming (TxBF) and Low Density Parity Check (LDPC) to extend the range of transmission. At the receiver, extended range and good minimum sensitivity is achieved by having receiver diversity up to 2 antennas. As the recipient, the RTL8812BRH-VN-CG also supports explicit sounding packet feedback that helps senders with beamforming capability. For legacy compatibility, OFDM baseband processing is included to support all IEEE 802.11a, 802.11n and 802.11ac data rates. The high speed FFT/IFFT paths, combined with BPSK, QPSK, 16QAM, 64QAM and 256QAM modulation of the individual subcarriers, and rate compatible coding rate of 1/2, 2/3, 3/4, and 5/6, provide up to 866.7Mbps for IEEE 802.11ac MIMO OFDM. The RTL8812BRH-VN-CG builds in an enhanced signal detector, an adaptive frequency domain equalizer, and a soft-decision Viterbi decoder to alleviate severe multi-path effects and mutual interference in the reception of multiple streams. For better detection quality, receive diversity with Maximal-Ratio-Combine (MRC) applying up to two receive paths, and Maximum-Likelihood Detection (MLD) are implemented. Receive vector diversity for multi-stream application is implemented for efficient utilization of the MIMO channel. Efficient IQ-imbalance, DC offset, phase noise, frequency offset, and timing offset compensations are provided for the radio frequency front-end. The RTL8812BRH-VN-CG supports fast receiver Automatic Gain Control (AGC) with synchronous and asynchronous control loops among antennas, antenna diversity functions, and adaptive transmit power control functions to obtain better performance in the analog portions of the transceiver. The RTL8812BRH-VN-CG MAC supports 802.11e for multimedia applications, 802.11i and WAPI (Wireless Authentication Privacy Infrastructure) for security, and 802.11n/802.11ac for enhanced MAC protocol efficiency. Using packet aggregation techniques such as A-MPDU with BA and A-MSDU, protocol efficiency is significantly improved. Power saving mechanisms such as Legacy Power Save, U-APSD, and MIMO power saving reduce the power wasted during idle time, and compensate for the extra power required to transmit MIMO OFDM. The RTL8812BRH-VN-CG provides simple legacy, 20MHz/40MHz/80MHz co-existence mechanisms to ensure backward and network compatibility. Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface 1 Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet 2. Features General 40MHz bandwidth, and 866.7Mbps using 80MHz bandwidth.  88-pin QFN  CMOS MAC, Baseband PHY and RF in a single chip for IEEE 802.11a/n/ac compatible WLAN  Complete 802.11n MIMO solution for 5GHz band  Maximum PHY data rate up to 173.3 Mbps using 20MHz bandwidth, 400Mbps using  Backward compatible with 802.11a devices while operating at 802.11n data rates  Backward compatible with 802.11a/n devices while operating at 802.11ac data rates.  PCIe LTR/L1.Off state supported Host Interface  Complies with PCI Express Specification Revision 1.1 Base Standards Supported  IEEE 802.11a/n/ac compatible WLAN  IEEE 802.11k Radio Resource Measurement  IEEE 802.11e QoS Enhancement (WMM)   WAPI (Wireless Authentication Privacy Infrastructure) certified. IEEE 802.11i (WPA, WPA2). Open, shared key, and pair-wise key authentication services  Cisco Compatible Extensions (CCX) for WLAN devices  Channel management and co-existence  Multiple BSSID feature allows the RTL8812BRH to assume multiple MAC identities when used as a wireless bridge  Transmit Opportunity (TXOP) Short Inter-Frame Space (SIFS) bursting for higher multimedia bandwidth  WiFi Direct supports wireless peer to peer applications.  IEEE 802.11h DFS, TPC, Spectrum Measurement MAC Features  Frame aggregation for increased MAC efficiency (A-MSDU, A-MPDU)  Low latency immediate Acknowledgement (BA)  Long NAV for media reservation with CF-End for NAV release  PHY-level spoofing to enhance legacy compatibility Block Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface 2 Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet Other Features  Supports Wake-On-WLAN Packet and Wake-up frame  Transmit Beamforming via Magic  CCA on secondary through RTS/CTS handshake.  Support TCP/UDP/IP checksum offload Peripheral Interfaces  Up to 15 General Purpose Input/Output pins  Generates 40MHz clock for peripheral chip.  Three configurable LED pins (mux with GPIO pins)  Single external power source 3.3V only  OFDM receive diversity with MRC using up to 2 receive paths. Switch diversity used for DSSS/CCK PHY Features  IEEE 802.11ac MIMO OFDM  IEEE 802.11n MIMO OFDM  Two Transmit and Two Receive paths  Support STBC  5MHz / 10MHz / 20MHz / 40MHz / 80MHz bandwidth transmission  Support LDPC   Hardware antenna diversity Support 5GHz band channels   Maximum-Likelihood Detection (MLD) Short Guard Interval (400ns)   Fast receiver Automatic Gain Control (AGC) Sounding packet.   On-chip ADC and DAC OFDM with BPSK, QPSK, 16QAM, 64QAM and 256QAM modulation. Convolutional Coding Rate: 1/2, 2/3, 3/4, and 5/6  Build-in both 5GHz PA  Build-in both 5GHz LNA  Flexible crystal frequency selection(52, 48, 40, 38.4, 27, 26, 25, 24, 20, 19.2, 17.664, 16, 14.318, 13 and 12MHz)  Support crystal or external clock input  Maximum data rate 300Mbps in 802.11n and 866.7bps in 802.11ac. Peripheral Interfaces  General Purpose Input/Output (8 pins)  4-wire EEPROM control interface (93C46)  Three configurable LED pins Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface 3 Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet 3. Application Diagrams 3.1. 5GHz-Band 2x2 RF Application Figure 1. 5GHz-Band 2x2 Solution(11ac 2x2 MAC/BB/RF + PA) Solution --- RTL8812BRH-VN-CG Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface 4 Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet 54 53 52 51 50 49 VD33_SYN VD1_SYN XI CAP_XTAL S0_TRSW 55 XO VDD_IO 56 VD33X GPIO4 58 57 VD1_WL_AFE GPIO5 59 RSVD GPIO0 60 S0_PAPE_5G GPIO1 62 61 S0_TRSWB GPIO2 66 65 64 63 GPIO3 EESK VD10D_1_WL VD33_IO Pin Assignments VDD33SPS 4. 48 47 46 45 LX_SPS2 67 44 LX_SPS1 68 43 S0_VD1_TRX RSVD S0_TSSI GND_SPS 69 42 VD10D_WL 70 41 RSVD GPIO14 71 40 S0_VD33_RFG WAKEn 72 39 S0_VD33_RFA CLKREQn 73 38 S0_WLA_RFO PERSTn 74 37 S0_VD1_RFA 36 S0_WLA_RFI VIO_HOST 75 RSVD 76 RSVD 77 RSVD 78 35 S1_TSSI 34 S1_VD1_TRX 33 RSVD HSON 79 HSOP 80 REFCLK_N 81 REFCLK_P 82 V10_VDDTX 83 28 S1_VD1_RFA V10_VDDRX 84 27 S1_WLA_RFI HSIN 85 26 VD33_PAD HSIP 86 25 ANTSWB V10_USB 87 24 RREF 88 23 RTL8812BRH LLLLLLL GXXXV 17 18 RSVD 31 S1_VD33_RFG 30 S1_VD33_RFA 29 S1_WLA_RFO ANTSW VD1_PAD_BT 19 20 21 22 Reserved 16 Reserved 15 Reserved GPIO11 13 14 Reserved GPIO9 12 VD33_BT_AFE GPIO6 11 VD1_AFE GPIO7 10 RSVD GPIO12 9 S1_PAPE_5G VDD_IO_1 8 S1_TRSWB 7 S1_TRSW 6 VD10D_BT 5 LED0 4 LED1 3 GPIO8 2 VD33_IO_1 1 EECS 89 GND ( Exposed Pad ) 32 Figure 2. Pin Assignments Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface 5 Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet 4.1. Package Identification & Mark Information Green package is indicated by a ‘G’ in the location marked ‘G’ in Figure 2. The version is shown in the location marked ‘V’ in Figure 2. 5. Pin Descriptions The following signal type codes are used in the tables: I: Input O: T/S: Tri-State bi-directional input/output pin O/D: Open Drain N/A: No Bonding pin S/T/S: P: Output Sustained Tri-State Power pin 5.1. Power On Trap Pin Symbol TEST_MODE_SEL SPS_LDO_SEL Type I I Table 1. Power-On Trap Pins Pin No Description 57 Shared with GPIO4 0: Normal operation mode 1: Test/debug mode 58 Shared with GPIO5 0: Internal switching regulator select 1: Internal LDO select Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface 6 Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet Symbol EEPROM_SEL Type I Pin No 63 Description Shared with EESK pin 0: Internal NV memory select 1: External EEPROM select 5.2. PCI Express Transceiver Interface Symbol HSIN/HSIP HSON/HSOP REFCLK_N/REFCLK_P CLKREQ# WAKE# PERST# Table 2. PCI Express Transceiver Interface Type Pin No Description I 85,86 PCI Express Receive Differential Pair O 79,80 PCI Express Transmit Differential Pair I 81,82 PCI Express Differential Reference Clock Source: 100MHz ± 300ppm I/O/D 73 Reference Clock Request Signal. Also used by L1 PM substates. This signal is used by the RTL8812BRH-VN-CG to request for the PCI Express reference clock. O/D 72 Power Management Event: Open drain, active low. Used to reactivate the PCI Express slot’s main power rails and reference clocks. I 74 PCI Express Reset Signal: active low. When the PERST# is asserted at power-on state, the RTL8812BRH-VN-CG returns to a pre-defined reset state and is ready for initialization and configuration after the de-assertion of the PERST#. 5.3. EEPROM Interface Symbol EECS EESK Type O O Table 3. EEPROM Interface Pin No Description 1 External EEPROM Chip Select 63 External EEPROM Clock 5.4. RF Interface Symbol S1_WLA_RFO Type I/O Pin No 29 S1_WLA_RFI S0_WLA_RFO I I/O 27 38 S0_WLA_RFI S1_TSSI S0_TSSI ANTSW I I I O 36 35 44 24 Table 4. RF Interface Description WLAN 5G RF I/O (w/o external FEM) and OUTPUT (w/i external FEM) WLAN 5G RF INPUT (w/i external FEM) WLAN 5G RF I/O (w/o external FEM) and OUTPUT (w/i external FEM) WLAN 5G RF INPUT (w/i external FEM) External PA TSSI INPUT External PA TSSI INPUT External ANTSW CONTROL Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface 7 Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet Symbol ANTSWB S1_PAPE_5G S1_TRSW S1_TRSWB S0_PAPE_5G S0_TRSW S0_TRSWB RSVD Type O O O O O O O Pin No 25 15 13 14 53 55 54 16,32,33, 41,42,52 Description External ANTSW CONTROL External 5G PAPE CONTROL External TRSW CONTROL External TRSW CONTROL External 5G PAPE CONTROL External TRSW CONTROL External TRSW CONTROL Reserved. 5.5. LED Interface Symbol LED0 LED1 LED2 Type O O O Pin No 11 10 9 Table 5. LED Interface Description LED Pin (Active Low) LED Pin (Active Low) LED Pin (Active Low), shared with GPIO8 5.6. Power Management Handshake Interface Symbol WL_DIS# Table 6. Power Management Handshake Interface Type Pin No Description I 6 This pin can be defined as the WLAN Radio-off function with host interface remaining connected. When this pin is pulled low, WLAN function will be Radio-off. When this function is not required, external pull high is required. Shared with GPIO9. 5.7. Clock and Other Pins Symbol XI XO SUS_CLK GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 Type I O I IO IO IO IO IO IO Table 7. Clock and Other Pins Pin No Description 48 40MHz OSC Input 40MHz Crystal reference clock input 49 40MHz Crystal reference clock output 1 Shared with EECS. External 32K or RTC clock input. 59 General Purpose Input/Output Pin 60 General Purpose Input/Output Pin 61 General Purpose Input/Output Pin 62 General Purpose Input/Output Pin 57 General Purpose Input/Output Pin 58 General Purpose Input/Output Pin Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface 8 Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet Symbol GPIO6 GPIO7 GPIO8 GPIO9 GPIO11 GPIO12 GPIO14 RSVD Type IO IO IO IO IO IO IO IO Pin No 5 4 9 6 7 3 71 76,77,78 Description General Purpose Input/Output Pin General Purpose Input/Output Pin General Purpose Input/Output Pin General Purpose Input/Output Pin General Purpose Input/Output Pin General Purpose Input/Output Pin General Purpose Input/Output Pin Reserved 5.8. Power Pins Symbol LX_SPS VD33_SPS VD33_IO VD33_IO_1 VDD_IO VDD_IO_1 VIO_HOST VD10D_WL VD10D_1_WL VD10D_BT GND_SPS RREF V10_VDDTX/ V10_VDDRX V10_USB VD1_PAD_BT VD33_BT_AFE VD1_ AFE VD33_PAD S1_VD1_RFA S1_VD33_RFA S1_VD33_RFG S1_VD1_TRX S0_VD1_RFA S0_VD33_RFA S0_VD33_RFG S0_VD1_TRX VD1_WL_SYN VD33_WL_SYN VD1_WL_AFE Type P P Pin No 67,68 66 P P P P P P P P P P P/I 65 8 56 2 75 70 64 12 69 88 83,84 P P P P P P P P P P P P P P P P 87 23 18 17 26 28 30 31 34 37 39 40 43 45 46 51 Table 8. Power Pins Description Switching Regulator Output Switching Regulator Input Or Linear Regulator input from 3.3V to 1.5V VDD3.3V for digital IO VDD3.3V for digital IO VDD for GPIO0 to GPIO5 and EESK VDD for GPIO6,GPIO7,GPIO9,GPIO11,GPIO12 and EECS. VIO_HOST 1.05V for WLAN digital power 1.05V for WLAN digital power 1.05V for BT/WLAN power Switching Regulator Ground Precision Resistor for Bandgap 1.05V for analog circuits in interface 1.05V for USB VDD 1.05V for BT/WLAN RF VDD 3.3V for BT/WLAN AFE VDD 1.05V for WLAN AFE VDD 3.3V for PAD VDD 1.05V for WLAN S1 5G RX VDD3.3V for WLAN S1 5G TX IPA VDD3.3V for WLAN S1 TX VDD 1.05V for WLAN S1 VDD 1.05V for WLAN S0 5G RX VDD3.3V for WLAN S0 5G TX IPA VDD3.3V for WLAN S0 TX VDD 1.05V for WLS0 VDD 1.05V for WLAN synthesizer VDD 3.3V for WLAN synthesizer VDD 1.05V for WLAN AFE Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface 9 Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet Symbol VD33X CAP_XTAL Reserved Type P P Pin No 50 47 19,20,21,22 Description VDD 3.3V for Crystal LDO output . External CAP 1uF is needed. Reserved Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface 10 Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet 6. Electrical and Thermal Characteristics 6.1. Temperature Limit Ratings Table 9. Parameter Storage Temperature Ambient Operating Temperature Junction Temperature Temperature Limit Ratings Minimum Maximum -55 +125 0 70 0 125 Units C C C 6.2. DC Characteristics 6.2.1. Symbol VD33 VD10 6.2.2. Symbol VIH VIL VOH VOL Power Supply Characteristics Table 10. DC Characteristics Parameter Minimum Typical 3.3V I/O Supply Voltage 3.0 3.3 1.05V Core Supply Voltage 1.04 1.09 Maximum 3.6 1.14 Units V V Maximum 3.6 0.9 3.3 0.33 Units V V V V Digital IO Pin DC Characteristics Table 11. 3.3V GPIO DC Characteristics Parameter Minimum Normal Input high voltage 2.0 3.3 Input low voltage -0 Output high voltage 2.97 -Output low voltage 0 -- PS. 3.3V and 1.05V ripple < 100mV Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface 11 Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet 7. Interface Timing Specification 7.1. PCIe Bus during Power On Sequence Tcore Ton 3.3V 1.09V CLKREQ# TPVPGL PERST# TPERST#-CLK REFCLK Figure 3. RTL8812BRH-VN-CG PCIe Bus Power On Sequence Ton: The main power ramp up duration TPVPGL: Power valid to PERST# input inactive TPERST#-CLK: Reference clock stable before PERST# inactive Table 12. The typical timing range Symbol Unit Min Typical Max Ton ms 0.5 1.5 5 Tcore ms 0.9 1 1.1 TPVPGL ms Implementation specific;recommended 50ms -- TPERST#-CLK us 100 -- Tattach ms 2 7 15 Tk-state ms 50 250 -- Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface 12 Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet 8. Mechanical Dimensions Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface 13 Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet 8.1. Mechanical Dimensions Notes Table 13. Dimensions Information Symbol A A1 A3 b D/E D2 E2 e L Min 0.80 0.00 0.13 4.9 5.7 0.30 Dimension in mm Nom 0.85 0.02 0.203 REF 0.18 10 BSC 5.0 5.8 0.40 BSC 0.40 Max 0.90 0.05 Min 0.031 0.000 0.23 0.005 5.1 5.9 0.193 0.224 0.50 0.012 Dimension in inch Nom 0.033 0.001 0.008 REF 0.007 0.394BSC 0.197 0.228 0.016 BSC 0.016 Max 0.035 0.002 0.009 0.201 0.232 0.020 Notes： 1. CONTROLLING DIMENSION：MILLIMETER(mm). 2. REFERENCE DOCUMENTL：JEDEC MO-220. Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface 14 Track ID: Rev. 0.1 RTL8812BRH-VN-CG Datasheet 9. Ordering Information Table 14. Ordering Information Part Number Package RTL8812BRH-VN-CG QFN-88, ‘Green’ Package Status Mass Production Realtek Semiconductor Corp. Headquarters No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan, R.O.C. Tel: 886-3-5780211 Fax: 886-3-5776047 www.realtek.com Single-Chip 802.11 ac/a/n 2T2R WLAN Controller with PCI-E Interface 15 Track ID: Rev. 0.1