MXD2656A1

Maxscend Confidential MXD2656A1 Datasheet MXD2656A1 Product Datasheet v1.2 Key Features          Applications  Interactive entertainment devices  TV/setup-box remote controls  Gaming controllers  Home automation, Building and Retail  E-lock  Smart Lighting  Electronic Shelf Label  Location Based Service  Personal area networks  Medical devices  Health  Fitness  Key finder  Beacons  Remote control toys Bluetooth Low Energy  Complies with Bluetooth 5.0 (1Mbps/2Mbps, extended ADV payload)  -94dBm sensitivity in 1Mbps mode  -20dBm to +5dBm output power  Single-pin antenna interface  13mA peak current in TX (0dBm)  12mA peak current in RX  RSSI (1dB resolution) ARM Cortex-M0+ 32-bit processor, 48MHz  65 uA/MHz running from SRAM  Single cycle multiplier  Serial Wire Debug Memory  80kB ROM  36kB SRAM, 4kB CACHE  512kB flash  32B eFuse Flexible power management  Supply voltage range 1.7V~3.6V  2uA at 3V in hibernate mode (GPIO state retention), wakeup by GPIO or RTC  5uA at 3V in sleep mode (BLE linked, all 40kB SRAM data retention), wakeup by GPIO, RTC or BLE Clock and timer  16MHz crystal oscillator  32KHz and 16MHz RC oscillator  5x 16bit timer  RTC  Watchdog DMA 2 channels Peripheral  19 general purpose I/Os with function anyroute  4-channel 9-bit general purpose ADC  2x UART with CTS/RTS  SPI with master/slave configurable  I2C with master/slave configurable  4x PWM  Infra-Red generator  Quadrature decoder (QDEC) interface  7816 T-0 master interface  12MHz clock output Audio Interface  Digital I2S mono or stereo data input  Digital PDM mono data input  16-bit mono ADC, single-ended or differential analog MIC input, 30dB PGA (3dB step), MICBIAS integrated Package QFN32 4 x 4 x 0.75 mm © 2018 Maxscend Microelectronics Company Limited. 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Maxscend Confidential 1 Maxscend Confidential MXD2656A1 Datasheet Contents 1 Revision History ........................................................................................................................................................... 6 2 Block Diagram ............................................................................................................................................................. 7 3 Pin Assignments .......................................................................................................................................................... 8 4 Specifications ............................................................................................................................................................ 11 4.1 Absolute Maximum Ratings ............................................................................................................................... 11 4.2 Recommended Operating Conditions ................................................................................................................ 11 4.3 DC Characteristics............................................................................................................................................... 11 4.4 Transceiver Characteristics ................................................................................................................................. 12 4.5 Audio Characteristics .......................................................................................................................................... 13 5 Function Blocks ......................................................................................................................................................... 14 5.1 Power Mode ....................................................................................................................................................... 14 5.2 ARM Cortex-M0+ CPU ........................................................................................................................................ 14 5.3 Bluetooth Low Energy ........................................................................................................................................ 15 5.4 Memories ........................................................................................................................................................... 16 5.5 QSPI Flash Controller .......................................................................................................................................... 16 5.5.1 Feature ........................................................................................................................................................ 17 5.5.2 Function Description ................................................................................................................................... 17 5.5.2.1 Cache Direct Read ................................................................................................................................ 17 5.5.2.2 MCU Indirect Access ............................................................................................................................. 17 5.5.2.3 Flash Clock Selection ............................................................................................................................ 18 5.6 CLOCK ................................................................................................................................................................. 18 5.6.1 Feature ........................................................................................................................................................ 18 5.6.2 Function Description ................................................................................................................................... 18 5.7 RESET .................................................................................................................................................................. 20 5.8 DMA ................................................................................................................................................................... 21 5.8.1 Feature ........................................................................................................................................................ 21 5.8.2 Function Description ................................................................................................................................... 21 5.8.2.1 DMA Peripherals................................................................................................................................... 21 5.8.2.2 DMA Channel Enable and Pause .......................................................................................................... 22 5.8.2.3 DMA Transfer Size ................................................................................................................................. 22 5.8.2.4 DMA Arbitration ................................................................................................................................... 22 5.8.2.5 Circular Mode ....................................................................................................................................... 23 5.8.2.6 TX Interval Mode .................................................................................................................................. 23 5.8.3 Software Procedure ..................................................................................................................................... 23 5.8.4 DMA Interrupt ............................................................................................................................................. 24 5.8.5 DMA Registers ............................................................................................................................................. 25 5.9 GPIO ................................................................................................................................................................... 33 5.9.1 Feature ........................................................................................................................................................ 33 5.9.2 Function Description ................................................................................................................................... 33 5.9.2.1 Pin Configuration .................................................................................................................................. 34 5.9.2.2 Pin Mapping ......................................................................................................................................... 35 © 2018 Maxscend Microelectronics Company Limited. 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Maxscend Confidential 2 Maxscend Confidential MXD2656A1 Datasheet 5.9.2.3 Pin Wakeup........................................................................................................................................... 36 5.9.2.4 Interrupt Generation ............................................................................................................................ 37 5.9.3 Software Procedure ..................................................................................................................................... 37 5.9.3.1 GPIO wakeup ........................................................................................................................................ 37 5.9.4 GPIO Interrupt ............................................................................................................................................. 38 5.9.5 GPIO Registers ............................................................................................................................................. 38 5.10 General Purpose ADC ....................................................................................................................................... 53 5.10.1 Feature ...................................................................................................................................................... 53 5.10.2 Function Description ................................................................................................................................. 53 5.10.3 Software Procedure ................................................................................................................................... 55 5.10.4 Registers .................................................................................................................................................... 55 5.11 UART ................................................................................................................................................................. 57 5.11.1 Feature ...................................................................................................................................................... 58 5.11.2 Function Description ................................................................................................................................. 58 5.11.2.1 Frame Format ..................................................................................................................................... 58 5.11.2.2 Transmission ....................................................................................................................................... 59 5.11.2.3 Reception ........................................................................................................................................... 60 5.11.2.4 Parity Error and Framing Error............................................................................................................ 60 5.11.3 Software Procedure ................................................................................................................................... 60 5.11.4 UART Interrupt .......................................................................................................................................... 61 5.11.4.1 Error Interrupt .................................................................................................................................... 61 5.11.4.2 Timeout Interrupt ............................................................................................................................... 62 5.11.4.3 Transmit Interrupt .............................................................................................................................. 62 5.11.4.4 Receive Interrupt ................................................................................................................................ 62 5.11.5 UART Registers .......................................................................................................................................... 63 5.12 SPI..................................................................................................................................................................... 68 5.12.1 Feature ...................................................................................................................................................... 68 5.12.2 Function Description ................................................................................................................................. 68 5.12.2.1 Clock Mode (Phase and Polarity) ........................................................................................................ 68 5.12.2.2 Clock Generation ................................................................................................................................ 69 5.12.2.3 TX Idle Data ........................................................................................................................................ 70 5.12.3 Software Procedure ................................................................................................................................... 70 5.12.3.1 Receive Procedure .............................................................................................................................. 70 5.12.3.2 Transmit Procedure ............................................................................................................................ 70 5.12.4 Interrupt .................................................................................................................................................... 70 5.12.5 Registers .................................................................................................................................................... 71 5.13 I2C .................................................................................................................................................................... 75 5.13.1 Feature ...................................................................................................................................................... 75 5.13.2 I2C Protocol ............................................................................................................................................... 76 5.13.2.1 Addressing Slave Protocol .................................................................................................................. 76 5.13.2.2 Transmitting and Receiving Protocol .................................................................................................. 76 5.13.2.3 Multiple Master Arbitration ............................................................................................................... 78 © 2018 Maxscend Microelectronics Company Limited. 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Maxscend Confidential 3 Maxscend Confidential MXD2656A1 Datasheet 5.13.3 Function Description ................................................................................................................................. 78 5.13.3.1 Transmission ....................................................................................................................................... 79 5.13.3.2 Reception ........................................................................................................................................... 80 5.13.3.3 RX FIFO Timeout ................................................................................................................................. 80 5.13.3.4 Master SCL Clock Generation ............................................................................................................. 80 5.13.4 Software Procedure ................................................................................................................................... 80 5.13.5 I2C interrupt .............................................................................................................................................. 82 5.13.6 I2C Registers .............................................................................................................................................. 82 5.14 7816 ................................................................................................................................................................. 90 5.14.1 Feature ...................................................................................................................................................... 90 5.14.2 Function Description ................................................................................................................................. 90 5.14.2.1 Frame Format ..................................................................................................................................... 91 5.14.2.2 Cold Reset........................................................................................................................................... 92 5.14.2.3 Warm Reset ........................................................................................................................................ 92 5.14.2.4 Transmission ....................................................................................................................................... 93 5.14.2.5 Reception ........................................................................................................................................... 93 5.14.2.6 Parity Error ......................................................................................................................................... 93 5.14.3 Software Procedure ................................................................................................................................... 94 5.14.3.1 CPU Operation Mode ......................................................................................................................... 94 5.14.3.2 DMA Operation Mode ........................................................................................................................ 94 5.14.4 7816 interrupt ........................................................................................................................................... 95 5.14.4.1 Timeout interrupt ............................................................................................................................... 96 5.14.4.2 Transmit Interrupt .............................................................................................................................. 96 5.14.4.3 Receive Interrupt ................................................................................................................................ 96 5.14.5 7816 Registers ........................................................................................................................................... 96 5.15 QDEC .............................................................................................................................................................. 101 5.15.1 Feature .................................................................................................................................................... 101 5.15.2 Function Description ............................................................................................................................... 101 5.15.2.1 Sampling and Decoding .................................................................................................................... 101 5.15.2.2 LED output........................................................................................................................................ 103 5.15.2.3 Inputs Digital Filters .......................................................................................................................... 103 5.15.2.4 Accumulators.................................................................................................................................... 104 5.15.3 Software Procedure ................................................................................................................................. 104 5.15.4 QDEC Interrupt ........................................................................................................................................ 105 5.15.5 QDEC Registers ........................................................................................................................................ 105 5.16 Audio .............................................................................................................................................................. 110 5.16.1 Feature .................................................................................................................................................... 110 5.16.2 Audio Interface Mode ............................................................................................................................. 111 5.16.3 PDM Interface ......................................................................................................................................... 111 5.16.4 Audio ADC ............................................................................................................................................... 111 5.16.5 I2S Interface ............................................................................................................................................ 112 5.16.5.1 Function Description ........................................................................................................................ 112 © 2018 Maxscend Microelectronics Company Limited. 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Maxscend Confidential 4 Maxscend Confidential MXD2656A1 Datasheet 5.16.5.2 Serial Interface Formats ................................................................................................................... 113 5.16.6 Audio Front Data Path ............................................................................................................................. 114 5.16.7 Typical Characteristics ............................................................................................................................. 115 5.16.8 Interrupts ................................................................................................................................................ 116 5.16.9 Software Procedure ................................................................................................................................. 117 5.16.9.1 PDM Mode ....................................................................................................................................... 117 5.16.9.2 ADC Mode ........................................................................................................................................ 117 5.16.9.3 I2S Mode .......................................................................................................................................... 117 5.16.10 Audio Register ....................................................................................................................................... 118 5.16.10.1 Audio Analog Register .................................................................................................................... 118 5.16.10.2 I2S Register ..................................................................................................................................... 118 5.16.10.3 CIC Register .................................................................................................................................... 121 5.17 Timer .............................................................................................................................................................. 124 5.17.1 Feature .................................................................................................................................................... 124 5.17.2 Function Description ............................................................................................................................... 125 5.17.3 PWM Function ......................................................................................................................................... 125 5.17.4 IR Function .............................................................................................................................................. 126 5.17.5 Software Procedure ................................................................................................................................. 126 5.17.6 Timer0~4 Interrupt .................................................................................................................................. 127 5.17.7 Timer0~4 Registers .................................................................................................................................. 128 5.18 Real Time Counter .......................................................................................................................................... 138 5.18.1 Feature .................................................................................................................................................... 138 5.18.2 Function Description ............................................................................................................................... 138 5.18.3 Signal Synchronous Time ......................................................................................................................... 139 5.18.4 RTC Counter Read .................................................................................................................................... 140 5.18.5 Software Procedure ................................................................................................................................. 140 5.18.6 RTC interrupt ........................................................................................................................................... 140 5.18.7 RTC Registers ........................................................................................................................................... 141 5.19 Watchdog Timer ............................................................................................................................................. 145 5.19.1 Feature .................................................................................................................................................... 145 5.19.2 Function Description ............................................................................................................................... 145 5.19.3 Software Procedure ................................................................................................................................. 145 5.19.4 Watchdog Interrupt ................................................................................................................................. 146 5.19.5 Watchdog timer Registers ....................................................................................................................... 146 6 Mechanical Information .......................................................................................................................................... 149 © 2018 Maxscend Microelectronics Company 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All Rights Reserved. Maxscend Confidential 5 Maxscend Confidential MXD2656A1 Datasheet 1 Revision History Version 1.0 Date Sep 5th, Description of Change 2019 the first release © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 6 Maxscend Confidential MXD2656A1 Datasheet 2 Block Diagram ARM M0+ POR LDO AON LDO RET LDO ACT PMU PLLx3 CLK Bus Matrix DMA (2 CH) 16MHz XOSC/RC 32KHz RC ROM 80KB CCM (AES) SRAM 36KB BLE 4.2 LL BLE RF AHB2APB SRAM 4KB QSPI FSHC ANALOG COMM TIMER ADC-9bit VBAT/IO UART*2 TIM SPI GTIM*4 Audio ADC I2C WDG 7816 RTC PDM/I2S ADC CIC SLEEP TIM CACHE Flash (512KB) TEMP Sensor GPIO (int, wakeup) IR Figure 1 Block Diagram © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 7 Maxscend Confidential MXD2656A1 Datasheet P1/MICN P0/MICP 29 P3 30 P2/MICVREF_CAP 31 P5 32 P4/MIC_BIAS P7/ADC P6 3 Pin Assignments 28 27 26 25 SWD 1 24 DVDD_RET SWCLK 2 23 DVDD_ACT DFT_EN 3 22 LDO_ACT_OUT 21 VDDR 20 16M_XI P8/ADC 4 P10/ADC 5 P11/ADC 6 19 16M_XO P14 7 18 VDDLO P15 8 17 VDDRF 14 15 16 RFIO P22 13 RSTN P20 12 P23 11 P21 10 P24 9 P19 VSS Figure 2 MXD2656A1 QFN32 4*4 Package Top View Note DIO (digital bidirectional), DI (digital input), AI (analog input), AIO (analog bidirectional). I-PD (input pull-down), I-PU (input pull-up). Table 1 Pin Description Pin Name Type Drive Reset (mA) State Description General Purpose I/Os INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. P5 DIO 5/10/15/20 I-PD State retention during sleep or hibernate power mode. Digital interface can be routed to any IO of Pn. INPUT/OUTPUT with selectable pull up/down resistor. Pull-up enabled during and after reset. Pn DIO 5/10/15/20 I-PU State retention during sleep or hibernate power mode. Digital interface can be routed to any IO of Pn. General Purpose I/Os with analog function INPUT/OUTPUT with selectable pull up/down P0/MICP DIO 5/10/15/20 I-PD resistor. Pull-down enabled during and after reset. State retention during sleep or hibernate power mode. Digital interface can be routed to any IO of © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 8 Maxscend Confidential MXD2656A1 Datasheet Pn. It can be used as MICP. In non-MICP mode, P0 always has a 30KΩ pull down resistor. Application design should take care of this, otherwise there may be 0.1mA leakage. INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. P4/MIC_BIAS DIO 5/10/15/20 I-PD State retention during sleep or hibernate power mode. Digital interface can be routed to any IO of Pn. It can be used as MICBIAS INPUT/OUTPUT with selectable pull up/down resistor. Pull-up enabled during and after reset. State retention during sleep or hibernate power mode. Digital interface can be routed to any IO of P1/MICN DIO 5/10/15/20 I-PU Pn. It can be used as MICN. In non-MICN mode, P1 always has a 30KΩ pull down resistor. Application design should take care of this, otherwise there may be 0.1mA leakage. INPUT/OUTPUT with selectable pull up/down resistor. Pull-up enabled during and after reset. P2/MICVREF_CAP DIO 5/10/15/20 I-PU State retention during sleep or hibernate power mode. Digital interface can be routed to any IO of Pn. It can be used as MIC VREF Decoupling Capacitance INPUT/OUTPUT with selectable pull up/down resistor. Pull-up enabled during and after reset. Pn/ADC DIO 5/10/15/20 I-PU Contains state retention mechanism during power down. Digital interface can be routed to any IO of Pn. It can be used as ADC input too. Debug Interface INPUT/OUTPUT with selectable pull up/down SWCLK DIO 5/10/15/20 I-PD resistor. Pull-down enabled during and after reset. Serial wire clock signal. Can also be used as a GPIO (digital interface any route is not supported). INPUT/OUTPUT with selectable pull up/down SWD DIO 5/10/15/20 I-PU resistor. Pull-up enabled during and after reset. Serial wire data signal. Can also be used as a GPIO (digital interface any route is not supported). © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 9 Maxscend Confidential MXD2656A1 Datasheet Clocks 16M_XI AI INPUT. Crystal input for the 16MHz XTAL. 16M_XO AO OUTPUT. Crystal output for the 16MHz XTAL. AIO RF input/output. Radio transceiver RFIO Miscellaneous INPUT. Reset signal (active low). Can be floating if RSTN DI DFT_EN DI INPUT. Connect to GND for application. DVDD_RET AIO Connect to external capacitor DVDD_ACT AIO Connect to external capacitor VDDRF AIO Connect to LDO_ACT_OUT VDDLO AIO Connect to LDO_ACT_OUT VDDR AIO Power supply 1.7V~3.6V VSS AIO Ground not used. Power supply © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 10 Maxscend Confidential MXD2656A1 Datasheet 4 Specifications 4.1 Absolute Maximum Ratings Table 2 Absolute Maximum Ratings Ratings Parameter Unit Min. Typ. Max. Power Supply Voltage (VDDR) -0.5 -- 3.9 V Maximum Junction Temperature -40 -- 125 ℃ Storage Temperature -40 -- 125 ℃ ESD HBM -3000 -- 3000 V ESD CDM -500 -- 500 V 4.2 Recommended Operating Conditions Table 3 Recommended Operating Conditions Ratings Parameter Unit Min. Typ. Max. Power Supply Voltage (VDDR) 1.7 3.0 3.6 V Operating Temperature -40 -- 85 ℃ Ta=25℃, VDDR=3.3V, unless otherwise specified. 4.3 DC Characteristics Table 4 DC Characteristics Ratings Parameter VIH (Logic-1 input voltage) Min. Typ. Unit VDDR = 3.3V 2.0 V VDDR = 2.5V 1.7 V VDDR = 1.8V 1.2 V IIH (Logic-1 input current) VIL (Logic-0 input voltage) Max. +10 uA VDDR = 3.3V 0.8 V VDDR = 2.5V 0.7 V VDDR = 1.8V 0.6 V IIL (Logic-0 input current) VOH (Logic-1 output voltage, IOL = -20/-15/-10/-5mA) -10 uA VDDR - 0.4 V VOL (Logic-0 output voltage, IOH = -20/-15/-10/-5mA) Rx Mode, 1Mbps mode 0.4 12 © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 11 V mA Maxscend Confidential MXD2656A1 Datasheet TX mode, 0 dBm output power 13 mA CPU running in SRAM 65 uA/MHz 2 uA 5 uA Hibernate mode (SRAM no retention, IO retention and IO wakeup or RTC wakeup) Sleep mode (SRAM 40kB retention, BLE linked, flash sleep included) Ta=25℃, VDDR=3.0V, unless otherwise specified. 4.4 Transceiver Characteristics Table 5 RX Characteristics Parameters Symbol Min Typ Max Unit Sensitivity PMIN -94 dBm Sensitivity(dirty on) PMIN -93 dBm Maximum input power PMAX 0 dBm In-band blocking Co-channel interference CI0 7 dB Interferer at foffs= +1MHz CI1 -1 dB Interferer at foffs= -1MHz CI1 -6 dB Interferer at foffs= +2MHz CI2 -38 dB Interferer at foffs= -2MHz CI2 -35 dB Interferer at foffs= +3MHz CI3 -42 dB Interferer at foffs= -3MHz CI3 -33 dB Interferer at image channel (Fimage) CI4 -29 dB Interferer at image channel (Fimage+1MHz) CI5 -33 dB Interferer at image channel (Fimage-1MHz) CI5 -32 dB Out-of-band f= 30–2000MHz >-25 dB blocking f= 2000–2399 MHz >-30 dB f= 2484–3000 MHz >-30 dB f= 3000–12750 MHz >-25 dB >-35 dB -20 dBm Intermodulation Performance for Wanted Signal at -64dBm and 1 Mbps BLE, 3rd, 4th and 5th offset channel Upper limit of input power range over which RSSI resolution is PRSSI_MAX maintained Ta=25℃, VDDR=3.0V, unless otherwise specified. Table 6 TX Characteristics Parameters Output power Symbol Min PTX -20 TX RF Output Steps Average Frequency deviation for 10101010 pattern ∆F2AVG Typ Max Unit +5 dBm 3 dB 238 KHz © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 12 Maxscend Confidential MXD2656A1 Datasheet Average Frequency deviation for 11110000 pattern ∆F1AVG Eye opening = ∆F2AVG/∆F1AVG EO 260 0.88 0.91 KHz 0.94 Frequency Accuracy -10 10 KHz Maximum Frequency Drift -6 5 KHz Initial Frequency drift -5 5 KHz -5.5 4.5 KHz/50μs Drift rate FDR Spurious Emissions In-band Emissions F < 1 GHz -68 dBm F > 1 GHz including harmonics -48 dBm -45 dBm -49 dBm < f ± 2MHz (f=2400~2483.5MHz,Ptx=5dBm) > f ± 3MHz (f=2400~2483.5MHz,Ptx=5dBm) Ta=25℃, VDDR=3.0V, unless otherwise specified. 4.5 Audio Characteristics Table 7 Audio Characteristics Parameters Min Typ Max Unit ADC Input Signal Level (0dB) - 0.8 - Vrms ADC ENOB - 12 - Bit ADC THD+N - 74 - dB ADC Conversion Rate - 16 - KHz ADC Signal Bandwidth 20 - 8K Hz PGA gain range 0 - 30 dB PGA step - 3 - dB MIC bias output voltage - 2.0, 2.5, or VDDR - V MIC bias loading current - - 5 mA Input Impedance (Resistance) - 30 - KΩ Input Impedance (Capacitance) - 1 - pF Current consumption - 1 - mA Total startup time - 10 - ms Ta=25℃, VDDR=3.0V, unless otherwise specified. © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 13 Maxscend Confidential MXD2656A1 Datasheet 5 Function Blocks 5.1 Power Mode Hibernate mode All IOs hold their status they had before entering hibernate mode. All power domains are off except PD_AON domain (IO, PMU). All clock sources are off except RC32K. IO or RTC can wake up the device from the hibernate mode. After wakeup, CPU will reset and restart the instructions from 0x0 address. CPU can differentiate whether it is wakeup or reset (pin reset, power-on-reset) through the reset status register. Sleep mode All IOs and 40KB SRAMs hold their status they had before entering sleep mode. All clock sources are off except RC32K. This mode can be waked up by any I/O pin, RTC, or Link layer timer. After wakeup, CPU will continue the instructions from where it went into Sleep. 5.2 ARM Cortex-M0+ CPU The Cortex-M0+ processor is a 32-bit Reduced Instruction Set Computing (RISC) processor with a von Neumann architecture (single bus interface). It implements the ARMv6-M architecture, which is based on the 16-bit Thumb (ARM7TDMI) instruction set and includes Thumb-2 technology. This provides the exceptional performance expected of a modern 32-bit architecture, with a higher code density than 8-bit and 16-bit microcontrollers. Table 8 CPU Interrupt Map CPU Interrupt Number # Module IRQ_CPU_NMI Watchdog Non-Maskable Interrupt IRQ_CPU_0 Power Management Unit Interrupt IRQ_CPU_1 Link Layer Controller Interrupt IRQ_CPU_2 UART0 Interrupt IRQ_CPU_3 UART1 Interrupt IRQ_CPU_4 SPI Interrupt IRQ_CPU_5 - IRQ_CPU_6 DMA Interrupt (DMA_INT0) IRQ_CPU_7 DMA Interrupt (DMA_INT1) IRQ_CPU_8 I2S Interrupt IRQ_CPU_9 I2C Interrupt IRQ_CPU_10 QDEC Interrupt IRQ_CPU_11 SCC/7816 Interrupt IRQ_CPU_12 Audio CIC Interrupt IRQ_CPU_13 RTC Interrupt IRQ_CPU_14 TIMER Interrupt (TIMER_INT0) © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 14 Maxscend Confidential MXD2656A1 Datasheet IRQ_CPU_15 TIMER Interrupt (TIMER_INT1) IRQ_CPU_16 TIMER Interrupt (TIMER_INT2) IRQ_CPU_17 GPIO Interrupt (GPIO_INT0) IRQ_CPU_18 GPIO Interrupt (GPIO_INT1) IRQ_CPU_19 GPIO Interrupt (GPIO_INT2) IRQ_CPU_20 - IRQ_CPU_21 CCM IRQ_CPU_22 - IRQ_CPU_23 - IRQ_CPU_24 RF Calibration IRQ_CPU_25 Software Defined Interrupt (SW0) IRQ_CPU_26 Software Defined Interrupt (SW2) IRQ_CPU_27 Software Defined Interrupt (SW3) IRQ_CPU_28 Software Defined Interrupt (SW3) IRQ_CPU_29~31 - 5.3 Bluetooth Low Energy The BLE radio transmits and receives GFSK packets at 2Mbps/1Mbps over a 2.4GHz ISM band, which is compliant with Bluetooth specification 5.0. The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50Ω antenna via a matching/filtering network. In the receive direction, it converts the RF signal from the antenna to a digital bit stream after performing GFSK demodulation. In the transit direction, it performs GFSK modulation and then converts a digital baseband signal to a radio frequency before transmitting it to air through the antenna. The BLE radio can estimate an accurate center frequency offset in case the opposite device crystal oscillator has a frequency PPM offset. In addition, the BLE radio can receive the packet with large carrier frequency offset (300KHz). The BLE core is a qualified Bluetooth baseband controller compatible with the Bluetooth Smart specification and it is in charge of packet encoding/decoding and frame scheduling. It performs Link Layer Control management supporting the main BLE states, including advertising and connection. Feature 1. All device classes support (Broadcaster, Central, Observer and Peripheral) 2. Simultaneous Master and Slave operation 3. Frequency Hopping 4. All packet types (Advertising / Data / Control) 5. Encryption (AES / CCM) 6. Bit stream processing (CRC, Whitening) 7. Operating clock 16MHz © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 15 Maxscend Confidential MXD2656A1 Datasheet 8. Low power mode with 32KHz timer counting 5.4 Memories FLASH 512kB) ROM (80kB) SRAM (40kB) Figure 3 Memories ROM 80kB ROM contains the Bluetooth Smart protocol stack as well as the boot code. Retention SRAM 40kB retention SRAM stores various data of the Bluetooth Smart protocol as well as the system’s global variables. The SRAM data is retained when the system goes into sleep mode. Storage of this data ensures secure and quick configuration of the BLE Core after the system wake up. Flash 512KB Flash memory stores the application code and user data for all the Bluetooth Smart devices. 5.5 QSPI Flash Controller The QSPI (Quad Serial Peripheral Interface) Flash Controller is used to read, write and erase FLASH memory. It supports the standard SPI, DSPI (Dual Serial Peripheral Interface) and QSPI (Quad Serial Peripheral Interface) interface formats. The QSPI flash controller has two AHB slave buses, one connecting with MCU to transfer data, and the other connecting with cache to fetch instructions. © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 16 Maxscend Confidential MXD2656A1 Datasheet Flash Controller Register MCU TX_FIFO RX_FIFO AHB1 AHB Arbiter FSM QSPI Interface QSPI Flash AHB2 Cache BUFF Figure 4 QSPI Flash Controller Block Diagram 5.5.1 Feature 1. SPI, DSPI, QSPI 2. Up to 48 MHz clock 3. Support CACHE direct instruction read from flash 4. Support MCU indirect data read from flash and data write to flash 5. Support MCU indirect status read from flash and status write to flash 6. Support chip/page/sector/block erase 7. 100,000 program/erase cycles 8. 20-year data retention 5.5.2 Function Description 5.5.2.1 Cache Direct Read Cache direct read mode is used to read CPU instruction code. Cache fetches 4 words (32bits per word) for one cache line if cache miss. 5.5.2.2 MCU Indirect Access There are four types of MCU indirect access types. - Erase - Program - MCU read/write flash status © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 17 Maxscend Confidential MXD2656A1 Datasheet - MCU read data When Erase or Program, the MCU must run from RAM and make sure all interrupts are disabled while in erasing or programming. CPU can read the flash status register (Read Status Register) to confirm that the erase or program is finished. Erase operations include block erase, sector erase and page erase. Page is the smallest erase unit. After erasing a flash page, all bits in the page are set to '1'. The typical erase time is 8ms. The flash can only be programmed from '1' to '0'. Before program, make sure that the address you want to program has been erased. The smallest program unit is 1 byte. Typical page program time is 2ms. MCU read/write flash status/data via register. Read or write flash status register only support SPI mode. The Flash can be read an unlimited number of times by the CPU via SPI, DSPI or QSPI mode, and burst length is unlimited. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. 5.5.2.3 Flash Clock Selection The Flash clock can select either 16M or PLL (48M) clock. 5.6 CLOCK 5.6.1 Feature 1. 16MHz crystal oscillator 2. 32KHz and 16MHz RC oscillator 3. 48MHz PLL 5.6.2 Function Description The system clock tree is described in detail in the following figure. It depicts the possible clock sources as well as all different divisions and multiplexing paths towards the generation of each block’s clock. © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 18 Maxscend Confidential MXD2656A1 Datasheet RC32K RC_32K_CLK 0 1 RC16M XI XO DCXO16M 0 RC16M_CLK clk_32k Div 2/4 LLC RTC PWT WDT 0 1 clk_xtal_cali DCXO_CLK_DIG DCXO_FIXED_16M_CLK 0 clk_high 1 2 Div PMU clk_pmu_div 16/32/ 48/96 Div 2/4/8/16/32 PLL_CLK_48M PLL_CLK_12M PLL 1 Div 256/512/1024 1 6/12/24/48/96 0 0 Efuse Table Register clk_apb 1 Div 2/4/8/16/32 1 ROM SRAM GPIO CPU DMA clk_ahb 0 CCM Div 2/6 0 clk_mdm_8m 1 Div3 0 0 1 MODEM I2C GPT TIM UART 7816 QDEC LLC RFDIG clk_16m 1 ext_spi0_s_clk 1 0 Div 2/4/8/16/32/64 6/12/24/48/96/192 clk_adc 0 1 SPI 1 0 ADC VCO-CALI AUDIO clk_ahb Div 8/16/32 ext_i2s_clk 0 1 FLASH i2s_bclk 0 1 I2S i2s_bclk_inv clk_pll_12m Div 2/4/8/16/32/64 clk_16m clk_out_div 0 iomux_out 1 PAD 2 Figure 5 Clock Tree Diagram Two main clocks:  clk_high: This is the system clock for CPU, AMBA bus (hclk/pclk), memories and some peripherals. This clock source can be 16MHz RC oscillator, PLL or 16MHz crystal oscillator.  clk_32KHz: This is the low power clock used for low power counter. The source can be either RC32KHz or RC16MHz. The 16MHz Crystal Oscillator (XO) must be used for the BLE operations or in the application where a very accurate clock is required for the ARM subsystem operations. © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 19 Maxscend Confidential MXD2656A1 Datasheet 5.7 RESET The device has several sources of reset. Resets may result in reset of the following: 1. The entire chip 2. A power domain 3. A voltage domain 4. Some digital modules Figure below shows the diagram of reset. RTC_RESET PIN RESET DAP_RESET POR !SYSRESETREQ SOC_RESET PMU_RESET PMU Watchdog WDOG_RESET ACT_RESET !SYSRESETREQ Figure 6 Reset Diagram The Power-on-Reset (POR) signal is generated by the analog circuitry contained in the device. POR resets the whole chip. Watchdog reset is used to recover from software crashes. The watchdog contains a 32-bit down counter with 32KHz internal RC clock which generates a Non-Maskable interrupt. If the interrupt is not serviced, the watchdog generates reset. The system reset request is generated by the debug circuitry of the Cortex-M0. The debugger writes to the SYSRESETREQ bit. The system reset request does not affect the debugger, thus allowing the debugger to remain connected during the reset sequence. The scope of all resets is listed in the following table. Table 9 Reset Functions Module POR Pin Watchdog System Hibernate Sleep Vector Reset Reset Reset Wakeup Wakeup Reset ARM_Debug X X X RTC X X X PMU X X X ARM_Core X X X X X Configuration for BLE X X X P X Data Path for BLE X X X X X Watchdog Timer X X X GPIO X X X X X X © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 20 Maxscend Confidential MXD2656A1 Datasheet Peripherals X X X X X RAM Retention X X X X X X Note:  X: Indicate that this module will be reset or RAM’s content will not be available.  P: Indicate that most registers are reset except some special registers. 5.8 DMA The DMA controller provides a way to offload data transfer tasks from the CPU. The DMA controller can perform transfers between memory and peripherals. The controller has dedicated channels for each supported on-chip module, and can be programmed to automatically perform transfers between peripherals and memories as the peripheral is ready to transfer more data. 5.8.1 Feature 1. Support memory to memory, memory to peripheral and peripheral to memory transmission 2. Support UART, SPI, I2C, 7816, I2S, CIC interface 3. 2 independent DMA channels 4. Configurable 2 level priority 5. Independent source and destination transfer size (8bit, 16bit, 32bit) 6. Support circular mode 7. Programmable number of data to be transferred: up to 65535 8. Source and destination address increment or no increment 5.8.2 Function Description The DMA controller performs direct memory transfer by sharing the system bus with the other masters of the device. The DMA request may stop the CPU access to the system bus for some bus cycles, when the CPU and DMA are accessing the same destination (memory or peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the CPU. 5.8.2.1 DMA Peripherals The DMA controller has two channels for fast data transfers between SPI, UART, I2C, 7816, CIC/I2S and on-chip RAM. Every peripheral is allocated with one dedicated ID, and each DMA channel can select any peripheral per ID. Table 10 DMA Peripherals Selection Register (DMAx_PERI_SEL) Value Name and Direction 0 UART0 TX 1 UART0 RX © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 21 Maxscend Confidential MXD2656A1 Datasheet 2 UART1 TX 3 UART1 RX 4 SPI0 TX 5 SPI0 RX 6 Reserved 7 Reserved 8 I2C0 TX 9 I2C0 RX 10 Reserved 11 Reserved 12 7816 TX 13 7816 RX 14 CIC RX 15 I2S RX 5.8.2.2 DMA Channel Enable and Pause A DMA channel is switched on with bit DMAx_EN. If DMA starts, data is transferred from address DMAx_SRC_ADDR to address DMAx_DST_ADDR for a length of DMAx_CFG_CNT, which can be 8, 16 or 32 bits wide. The address increment is implemented using a 16-bit index counter (DMAx_TCNT) which is initialized to ‘0’ when the transfer starts. This register is increased by 1 at the end of each DMA cycle and is then compared to DMAx_CFG_CNT (transfer completion or not). If completed, it is then automatically reset to ‘0’ again. Each channel of the DMA controller can be temporarily disabled by writing a ‘1’ at bit DMAx_PAUSE in the DMAx_CONFIG register. To enable the channel again, a ‘0’ to bit at DMAx_PAUSE must be written. 5.8.2.3 DMA Transfer Size A DMA transfer is the smallest unit of data that can be transferred by the DMA. The DMA supports byte, half-word and word sized transfers. The DMAx_SRC_SIZE/DMAx_DST_SIZE register specifies the data width of one DMA transfer for source/destination (0: 1byte, 1: 2bytes, 2/3: 4bytes). The transfer count DMAx_CFG_CNT defines how many DMA transfers to perform. The total transfer byte number is (DMAx_CFG_CNT * DMAx_SRC_SIZE). Before DMA completion, the number of bytes transferred is (DMAx_TCNT * DMAx_SRC_SIZE). 5.8.2.4 DMA Arbitration The arbiter manages the channel requests based on their priority and launches the peripheral/memory access © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 22 Maxscend Confidential MXD2656A1 Datasheet sequences. The priority level of a DMA channel can be set with bit DMAx_PRI. These bits determine which DMA channel will be activated in case more than one DMA channel requests DMA. If two channels have the same priority, DMA0 will win the arbitration. 5.8.2.5 Circular Mode Circular mode is available to handle circular buffers and continuous data flow. This feature can be enabled using the DMAx_CIRC bit in the DMAx_CONFIG register. When circular mode is activated, after the last transfer, the number of data to be transferred is automatically reloaded with the initial value programmed during the channel configuration phase. DMA will serve the configured request as before. 5.8.2.6 TX Interval Mode TX interval mode provides a quick DMA operation mode if the data is not all ready when triggering DMA. This mode is enabled by DMAx_INTER_TX_MODE bit. The DMA transfer length is calculated as below. - For the first time, it is DMAx_INTER_TX_OFFSET. - For the later times, there are two scenarios.  If the new DMAx_INTER_TX_OFFSET is larger than the old one, it is (new DMAx_INTER_TX_OFFSET - old DMAx_INTER_TX_OFFSET).  If the new DMAx_INTER_TX_OFFSET is smaller than the old one, it is (new DMAx_INTER_TX_OFFSET - old DMAx_INTER_TX_OFFSET + DMAx_CFG_CNT). 5.8.3 Software Procedure The following sequence should be followed to configure a DMA channel x (where x is the channel number).  Data from peripheral to memory 1. Set the peripheral register address in the DMAx_SRC_ADDR register. The data is moved from this address after the peripheral event. 2. Set the memory address in the DMAx_DST_ADDR register. The data will be written to this memory address after the peripheral event. 3. Configure the total number of data to be transferred in the bits DMAx_CFG_CNT in the DMAx_CONFIG register. After each peripheral event, this value is decremented. 4. Configure the channel priority using the DMAx_PRI bit in the DMAx_CONFIG register. 5. Configure data transfer direction, circular mode, peripheral and memory incremented mode, peripheral and memory data size, and interrupt after half and/or full transfer in the DMAx_CONFIG register. 6. Activate the channel by setting the DMAx_EN bit in the DMAx_CONFIG register. © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 23 Maxscend Confidential MXD2656A1 Datasheet  Data from memory to peripheral 1. Set the memory register address in the DMAx_SRC_ADDR register. The data is moved from this address before the peripheral event. 2. Set the peripheral address in the DMAx_DST_ADDR register. The data will written be to this address. 3. Configure the total number of data to be transferred in the bits DMAx_CFG_CNT in the DMAx_CONFIG register. After each peripheral event, this value is decremented. 4. Configure the channel priority using the DMAx_PRI bit in the DMAx_CONFIG register. 5. Configure data transfer direction, circular mode, peripheral and memory incremented mode, peripheral and memory data size, and interrupt after half and/or full transfer in the DMAx_CONFIG register. 6.  Activate the channel by setting the DMAx_EN bit in the DMAx_CONFIG register. Data from memory to memory 1. Set the memory register address in the DMAx_SRC_ADDR register. The data is moved from this address. 2. Set the memory address in the DMAx_DST_ADDR register. The data will be written to this address. 3. Configure the total number of data to be transferred in the bits DMAx_CFG_CNT in the DMAx_CONFIG register. After each peripheral event, this value is decremented. 4. Configure the channel priority using the DMAx_PRI bit in the DMAx_CONFIG register. 5. Configure data transfer direction, circular mode, peripheral and memory incremented mode, peripheral and memory data size, and interrupt after half and/or full transfer in the DMAx_CONFIG register. 6. Activate the channel by setting the DMAx_EN bit in the DMAx_CONFIG register. As soon as the channel is enabled, it can serve any DMA request from the peripheral connected on the channel or memory connected. At the end of the transfer, the transfer complete interrupt is generated if the transfer complete interrupt enable bit (DMAx_4/4_DONE in the DMA_INT_MASK register) is set. 5.8.4 DMA Interrupt DMA interrupt table is shown below. Table 11 DMA Interrupt Interrupt Number Interrupt Name Description 0 DMA0_TIMEOUT DMA0 timeout, no data is transferred 1 DMA0_4/4_DONE DMA0 has finished all data transfer length 2 DMA0_3/4_DONE DMA0 has finished 3/4 data transfer length 3 DMA0_2/4_DONE DMA0 has finished 2/4 data transfer length 4 DMA0_1/4_DONE DMA0 has finished 1/4 data transfer length 5 DMA1_TIMEOUT DMA1 timeout, no data is transferred 6 DMA1_4/4_DONE DMA1 has finished all data transfer length 7 DMA1_3/4_DONE DMA1 has finished 3/4 data transfer length 8 DMA1_2/4_DONE DMA1 has finished 2/4 data transfer length 9 DMA1_1/4_DONE DMA1 has finished 1/4 data transfer length © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 24 Maxscend Confidential MXD2656A1 Datasheet 5.8.5 DMA Registers Table 12 DMA Instance Base Address Peripheral Instance Description 0x40002000 DMA DMA Direct Memory Access Table 13 DMA Register Map Address Offset Name Description 0x00 DMA_INT_STATUS DMA Interrupt Status 0x04 DMA_INT_MASK DMA Interrupt Enable 0x08 DMA_INT_CLEAR DMA Interrupt Flag Clear Register 0x0C DMA0_CONFIG DMA0 Configuration Register 0x10 DMA0_SRC_ADDR DMA0 Source Start Address 0x14 DMA0_DST_ADDR DMA0 Destination Start Address 0x18 DMA0_TCNT DMA0 Transferred Data Number 0x1C DMA1_CONFIG DMA1 Configuration Register 0x20 DMA1_SRC_ADDR DMA1 Source Start Address 0x24 DMA1_DST_ADDR DMA1 Destination Start Address 0x28 DMA1_TCNT DMA1 Transferred Data Number 0x2C DMA_INT_SEL DMA Interrupt Selection 0x30 DMA_TO_THLD DMA Timeout Threshold 0x34 DMA0_INTER_TX_CFG DMA0 TX Interval Mode Configuration 0x38 DMA1_INTER_TX_CFG DMA1 TX Interval Mode Configuration Table 14 DMA_INT_STATUS (DMA_BASE_ADDR+0x00) Bit Field Name 9 DMA1_1/4_DONE Reset 0 RW R Description DMA1 has finished 1/4 data transfer length. 0: invalid 1: valid 8 DMA1_2/4_DONE 0 R DMA1 has finished 2/4 data transfer length. 0: invalid 1: valid 7 DMA1_3/4_DONE 0 R DMA1 has finished 3/4 data transfer length. 0: invalid 1: valid 6 DMA1_4/4_DONE 0 R DMA1 has finished all data transfer length. 0: invalid 1: valid 5 DMA1_TIMEOUT 0 R DMA1 timeout © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 25 Maxscend Confidential MXD2656A1 Datasheet 0: invalid 1: valid 4 DMA0_1/4_DONE 0 R DMA0 has finished 1/4 data transfer length. 0: invalid 1: valid 3 DMA0_2/4_DONE 0 R DMA0 has finished 2/4 data transfer length. 0: invalid 1: valid 2 DMA0_3/4_DONE 0 R DMA0 has finished 3/4 data transfer length. 0: invalid 1: valid 1 DMA0_4/4_DONE 0 R DMA0 has finished all data transfer length. 0: invalid 1: valid 0 DMA0_TIMEOUT 0 R DMA0 timeout 0: invalid 1: valid Table 15 DMA_INT_MASK (DMA_BASE_ADDR+0x04) Bit Field Name 9 DMA1_1/4_DONE_MASK Reset 0 RW RW Description DMA1_1/4_DONE interrupt enable 0: disable 1: enable 8 DMA1_2/4_DONE_MASK 0 RW DMA1_2/4_DONE interrupt enable 0: disable 1: enable 7 DMA1_3/4_DONE_MASK 0 RW DMA1_3/4_DONE interrupt enable 0: disable 1: enable 6 DMA1_4/4_DONE_MASK 0 RW DMA1_4/4_DONE interrupt enable 0: disable 1: enable 5 DMA1_TIMEOUT_MASK 0 RW DMA1 Timeout interrupt enable 0: disable 1: enable 4 DMA0_1/4_DONE_MASK 0 RW DMA0_1/4_DONE interrupt enable 0: disable 1: enable 3 DMA0_2/4_DONE_MASK 0 RW DMA0_2/4_DONE interrupt enable 0: disable 1: enable 2 DMA0_3/4_DONE_MASK 0 RW DMA0_3/4_DONE interrupt enable © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 26 Maxscend Confidential MXD2656A1 Datasheet 0: disable 1: enable 1 DMA0_4/4_DONE_MASK 0 RW DMA0_4/4_DONE interrupt enable 0: disable 1: enable 0 DMA0_TIMEOUT_MASK 0 RW DMA0 timeout interrupt enable 0: disable 1: enable Table 16 DMA_INT_CLEAR (DMA_BASE_ADDR+0x08) Bit Field Name 9 DMA1_1/4_DONE_CLEAR Reset 0 RW W Description DMA1_1/4_DONE interrupt clear 0: invalid 1: clear 8 DMA1_2/4_DONE_CLEAR 0 W DMA1_2/4_DONE interrupt clear 0: invalid 1: clear 7 DMA1_3/4_DONE_CLEAR 0 W DMA1_3/4_DONE interrupt clear 0: Invalid 1: Clear 6 DMA1_4/4_DONE_CLEAR 0 W DMA1_4/4_DONE interrupt clear 0: invalid 1: clear 5 DMA1_TIMEOUT_CLEAR 0 W DMA1 timeout interrupt clear 0: invalid 1: clear 4 DMA0_1/4_DONE_CLEAR 0 W DMA0_1/4_DONE interrupt clear 0: invalid 1: clear 3 DMA0_2/4_DONE_CLEAR 0 W DMA0_2/4_DONE interrupt clear 0: invalid 1: clear 2 DMA0_3/4_DONE_CLEAR 0 W DMA0_3/4_DONE interrupt clear 0: invalid 1: clear 1 DMA0_4/4_DONE_CLEAR 0 W DMA0_4/4_DONE interrupt clear 0: invalid 1: clear 0 DMA0_TIMEOUT_CLEAR 0 W DMA0 timeout interrupt clear 0: invalid 1: clear © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 27 Maxscend Confidential MXD2656A1 Datasheet Table 17 DMA0_CONFIG (DMA_BASE_ADDR+0x0C) Bit Field Name Reset 31 DMA0_EN 0 RW Description RW DMA0 enable control 0: disable 1: enable 30 DMA0_PAUSE 0 RW DMA0 pause control 0: invalid 1: pause transfer 29 DMA0_SRC_INC 0 RW DMA0 increment of source address 0: not increment, source address stays the same during the transfer 1: increment, according to the value DMA0_SRC_SIZE (by 1, when DMA0_SRC_SIZE is 0; by 2, when DMA0_SRC_SIZE is 1; by 4, when DMA0_SRC_SIZE is 2 or 3) 28:27 DMA0_SRC_SIZE 0x0 RW DMA0 source bus transfer width 0: 1 byte 1: 2 bytes 2~3: 4 bytes 26 DMA0_DST_INC 0 RW DMA0 increment of destination address 0: not increment, destination address stays the same during the transfer 1: increment, according to the value DMA0_DST_SIZE (by 1, when DMA0_DST_SIZE is 0; by 2, when DMA0_DST_SIZE is 1; by 4, when DMA0_DST_SIZE is 2 or 3) 25:24 DMA0_DST_SIZE 0x0 RW DMA0 destination bus transfer width 0: 1 byte 1: 2 bytes 2~3: 4 bytes 23 DMA0_MEM_TO_MEM 0 RW Data transfer from memory to memory 0: Data from memory to peripherals, or from peripherals to memory 1: Data from memory to memory 22 DMA0_MEM_TO_PERI 0 RW Data transmission from memory to peripherals 0: Peripherals to memory 1: Memory to peripherals Note: DMA0_MEM_TO_MEM must be 0, otherwise this bit is invalid 21:18 DMA0_PERI_SEL 0x0 RW DMA0 peripherals selection 0: uart 0 tx 1: uart 0 rx © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 28 Maxscend Confidential MXD2656A1 Datasheet 2: uart 1 tx 3: uart 1 rx 4: spi 0 tx 5: spi 0 rx 6: reserved 7: reserved 8: i2c 0 tx 9: i2c 0 rx 10: reserved 11: reserved 12: 7816 tx 13: 7816 rx 14: cic rx 15: i2s rx 17 DMA0_PRI 0 RW DMA0 priority level 0: lowest priority 1: highest priority Note: The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. If different channels with the equal priority level values request the bus at the same time, DMA0 will first be granted access to the bus. 16 DMA0_CIRC 0 RW DMA0 transfer data mode 0: normal mode. DMA0 stops after having completed the transfer of length determined by DMA0_CFG_CNT. 1: circular mode, DMA0 automatically starts a new transfer after having completed the transfer of length determined by DMA0_CFG_CNT register. 15:0 DMA0_CFG_CNT 0x0 RW DMA0 transfer length, unit is register (DMA0_SRC_SIZE) value Table 18 DMA0_SRC_ADDR (DMA_BASE_ADDR+0x10) Bit Field Name 31:0 DMA0_SRC_ADDR Reset 0x0 RW RW Description DMA0 source start address Table 19 DMA0_DST_ADDR (DMA_BASE_ADDR+0x14) Bit Field Name Reset RW Description © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 29 Maxscend Confidential MXD2656A1 Datasheet 31:0 DMA0_DST_ADDR 0x0 RW DMA0 destination start address Table 20 DMA0_TCNT (DMA_BASE_ADDR+0x18) Bit Field Name Reset RW 15:0 DMA0_TCNT 0x0 R Description DMA0, The data number has been transferred, unit is register (DMA0_SRC_SIZE) value Table 21 DMA1_CONFIG (DMA_BASE_ADDR+0x1C) Bit Field Name Reset 31 DMA1_EN 0 RW RW Description DMA1 enable control 0: disable 1: enable 30 DMA1_PAUSE 0 RW DMA1 pause control 0: invalid 1: pause transfer 29 DMA1_SRC_INC 0 RW DMA1 increment of source address 0: not increment, source address stays the same during the transfer 1: increment, according to the value DMA1_SRC_SIZE (by 1, when DMA1_SRC_SIZE is 0; by 2, when DMA1_SRC_SIZE is 1; by 4, when DMA1_SRC_SIZE is 2 or 3) 28:27 DMA1_SRC_SIZE 0x0 RW DMA1 source bus transfer width 0: 1 byte 1: 2 bytes 2~3: 4 bytes 26 DMA1_DST_INC 0 RW DMA1 increment of destination address 0: not increment, destination address stays the same during the transfer 1: increment, according to the value DMA1_DST_SIZE (by 1, when DMA1_DST_SIZE is 0; by 2, when DMA1_DST_SIZE is 1; by 4, when DMA1_DST_SIZE is 2 or 3) 25:24 DMA1_DST_SIZE 0x0 RW DMA1 destination bus transfer width 0: 1 byte 1: 2 bytes 2~3: 4 bytes 23 DMA1_MEM_TO_MEM 0 RW Data transfer from memory to memory 0: Data from memory to peripherals, or from peripherals to memory 1: Data from memory to memory 22 DMA1_MEM_TO_PERI 0 RW Data transmission from memory to peripherals © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 30 Maxscend Confidential MXD2656A1 Datasheet 0: Peripherals to memory 1: Memory to peripherals Note: DMA1_MEM_TO_MEM must be 0, otherwise this bit is invalid 21:18 DMA1_PERI_SEL 0x0 RW DMA1 peripherals selection 0: uart 0 tx 1: uart 0 rx 2: uart 1 tx 3: uart 1 rx 4: spi 0 tx 5: spi 0 rx 6: reserved 7: reserved 8: i2c 0 tx 9: i2c 0 rx 10: reserved 11: reserved 12: 7816 tx 13: 7816 rx 14: cic rx 15: i2s rx 17 DMA1_PRI 0 RW DMA1 priority level 0: lowest priority 1: highest priority Note: The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. If different channels with the equal priority level values request the bus at the same time, DMA1 will first be granted access to the bus. 16 DMA1_CIRC 0 RW DMA1 transfer data mode 0: normal mode. DMA1 stops after having completed the transfer of length determined by DMA1_CFG_CNT. 1: circular mode, DMA1 automatically starts a new transfer after having completed the transfer of length determined by DMA1_CFG_CNT register. 15:0 DMA1_CFG_CNT 0x0 RW DMA1 transfer length, unit is register (DMA1_SRC_SIZE) value © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 31 Maxscend Confidential MXD2656A1 Datasheet Table 22 DMA1_SRC_ADDR (DMA_BASE_ADDR+0x20) Bit Field Name Reset 31:0 DMA1_SRC_ADDR 0x0 RW RW Description DMA1 source start address Table 23 DMA1_DST_ADDR (DMA_BASE_ADDR+0x24) Bit Field Name Reset 31:0 DMA1_DST_ADDR 0x0 RW RW Description DMA1 destination start address Table 24 DMA1_TCNT (DMA_BASE_ADDR+0x28) Bit Field Name Reset RW 15:0 DMA1_TCNT 0x0 R Description DMA1, The data number has been transferred, unit is register (DMA1_SRC_SIZE) value Table 25 DMA_INT_SEL (DMA_BASE_ADDR+0x2C) Bit Field Name 1:0 DMA_INT_SEL Reset 0x0 RW RW Description Interrupt mapping to IRQ_CPU_6 or IRQ_CPU_7 bit[1], DMA1 interrupt mapping 0: IRQ_CPU_6 1: IRQ_CPU_7 bit[0], DMA0 interrupt mapping 0: IRQ_CPU_6 1: IRQ_CPU_7 Table 26 DMA_TO_THLD (DMA_BASE_ADDR+0x30) Bit Field Name 7:0 DMA_TO_THLD Reset 0x0 RW RW Description threshold of DMA0 and DMA1 timeout interrupt (N), time unit: 100us, so the time is N*100us Table 27 DMA0_INTER_TX_CFG (DMA_BASE_ADDR+0x34) Bit Field Name 16 DMA0_INTER_TX_MODE Reset 0 RW RW Description DMA0 interval tx mode enable control 0: disable 1: enable Note: When in interval tx mode, the data will be transferred an offset value number (DMA0_TX_OFFSET). When a new offset value is set, DMA0 continues to work until the total number arrives at DMA0_CFG_CNT. 15:0 DMA0_TX_OFFSET 0x0 RW DMA0 offset value of interval tx mode © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 32 Maxscend Confidential MXD2656A1 Datasheet Table 28 DMA1_INTER_TX_CFG (DMA_BASE_ADDR+0x38) Bit Field Name 16 DMA1_INTER_TX_MODE Reset 0 RW RW Description DMA1 interval tx mode enable control 0: disable 1: enable Note: When in interval tx mode, the data will be transferred an offset value number (DMA1_TX_OFFSET). When a new offset value is set, DMA1 continues to work until the total number arrives at DMA1_CFG_CNT. 15:0 DMA1_TX_OFFSET 0x0 RW DMA1 offset value of interval tx mode 5.9 GPIO 5.9.1 Feature 1. Software defined GPIO input or output with internal configurable pull-up and pull-down 2. Configurable Schmitt trigger or CMOS input 3. All pins can be individually mapped to peripheral interface blocks for PCB layout flexibility 4. Interrupt trigger by state change on any pin 5. Wake-up trigger by level (high or low) or edge (positive, negative or both edge) on any pin 5.9.2 Function Description The below figure shows a general overview. The design provides a flexible IO mux configuration, and most of the peripheral ports can be mapped to any of the physical I/O pads. GPIO Reg IO_MUX Peripherals © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 33 Maxscend Confidential MXD2656A1 Datasheet Figure 7 GPIO Overview 5.9.2.1 Pin Configuration GPIO pad architecture is shown below. Px_PID REG Peripheral output enable VDD Px_OE REG Px_PU REG Peripheral output GPIO_OUT_SET REG Px_IE REG GPIO_IN REG Peripheral input Px_PD REG VSS Figure 8 Pin Configuration Each of these pins can be individually configured in the GPIO_Pxx_CONFIG registers (xx=0..24). The following parameters can be configured through these registers.  Direction  Drive strength  Pull-up and pull-down When the port is configured as an input, the data in Register (GPIO_IN) can be used to read the level of each pin in the port (bit n in the register is connected to pin n on the port). When configured as an output, the value of the data out Register (GPIO_OUT_SET) is driving the pin. The output value can be changed in 2 different ways.  Writing the GPIO_OUT_SET register sets the output bit  Writing the GPIO_OUT_CLEAR register clears the output bit Reading the GPIO_OUT_STATUS register will return its content. The drive strength can be set to each pin individually. It’s configured through GPIO_Pxx_DSH and GPIO_Pxx_DSL. The below table describes the driving strength definition. Table 29 Driving Strength Degree table GPIO_Pxx_DSH GPIO_Pxx_DSL Driving Strength Degree (OE=1) 0 0 5mA 0 1 10mA 1 0 15mA 1 1 20mA © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 34 Maxscend Confidential MXD2656A1 Datasheet In peripheral function mode, the registers GPIO_Pxx_PID need to be set for a flexible IO mapping. 5.9.2.2 Pin Mapping The IO_MUX can map a number of peripheral modules such as GPIO, SPI, UART, I2C and I2S to any of the available I/Os. Each type of peripheral signal has a unique ID, and each IO can select one ID. To map a peripheral function to GPIOxx, where xx can range from 0 to a maximum of 24, the ID and pin configuration must be set in the corresponding bit GPIO_Pxx_PID in GPIO_Pxx_CONFIG register. The below table lists all the available peripheral IDs. Table 30 Peripheral ID ID Port Description 0 Default GPIO usage 1 UART 0 TX pin 2 UART 0 RX pin 3 UART 0 CTS pin 4 UART 0 RTS pin 5 SPI CLOCK pin 6 SPI CSN pin 7 SPI MOSI pin 8 SPI MISO pin 9 I2C SCL pin 10 I2C SDA pin 11 PWM 0 pin 12 PWM 1 pin 13 PWM 2 pin 14 PWM 3 pin 15 7816 CLOCK pin 16 7816 DATA pin 17 7816 RESET pin 18 IR pin 19 I2S MCLK pin 20 I2S BCLK pin 21 I2S WCLK pin 22 I2S DATA pin 23 UART 1 TX pin 24 UART 1 RX pin 25 UART 1 CTS pin 26 UART 1 RTS pin 27 FLASH CLOCK pin 28 FLASH CS pin © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 35 Maxscend Confidential MXD2656A1 Datasheet 29 FLASH SI pin 30 FLASH SO pin 31 FLASH WP pin 32 FLASH HOLD pin 33 PLL pin, output PLL clock 12M/16M/8M/4M/2M/1M. 34 QDEC PHASE A pin 35 QDEC PHASE B pin 36 QDEC LED pin 37~42 Reserved 43 TEST CLOCK pin, output clock RC32K/RC16M/XO16M. Only P21 can output test clock, other pins are reserved. 44~63 Reserved Please note that:  If a certain function (output pin like uart 0 txd) is selected on more than one port pin (like P00 and P01), and all ports (P00 and P01) will perform this function.  If a certain function (input pin like uart 0 rxd) is selected on more than one port pin, the internal signal uart_rxd connected to UART module will perform OR operation of all ports. 5.9.2.3 Pin Wakeup Any GPIO can wake up the chip from hibernate or sleep mode. As shown in the figure below, the wakeup request can be triggered through the pins by enabling the corresponding bit in the GPIO_PWT_EN register. When wakeup is enabled for the pin, the input filter (debounce function) can be optionally selected by GPIO_PWT_DEB register. The debouce circuit can avoid false wakeup caused by glitch. In addition, the polarity of the wakeup request can be selected using the GPIO_PWT_POL register. GPIO_PWT_POL 32k clock GPIO_PWT_EN Pxx PWT_DEB GPIO_PWT_WAKEUP_CLR Debounce set clear Figure 9 Pin Wakeup Logic © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 36 pin_wakeup Maxscend Confidential MXD2656A1 Datasheet 5.9.2.4 Interrupt Generation The GPIO can generate an interrupt by level or edge. See the below figure Pin xx Interrupt Generation. GPIO_INT_BOTH_EDGE 1 GPIO_INT_POL GPIO_INT_EDGE_NLEVEL edge_en GPIO_INT0_EN GPIO_INT_CLEAR IRQ_CPU_17 GPIO_INT_MASK Pxx GPIO_INT1_EN Sync set IRQ_CPU_18 clear GPIO_INT2_EN edge_en IRQ_CPU_19 Figure 10 Pin xx Interrupt Generation There are three GPIO interrupt groups (IRQ_CPU_17, IRQ_CPU_18, IRQ_CPU_19), and any pin can be grouped to any of the group for interrupt. The GPIO_INT0_EN, GPIO_INT1_EN and GPIO_INT2_EN registers select which ports in the group will trigger the interrupt. For example, if GPIO_INT0_EN = 0xFF, then P00~P07 will be selected for generating interrupt IRQ_CPU_17. While GPIO_INT1_EN = 0xFF00, P08~P15 use the second interrupt group (IRQ_CPU_18). In order to enable the level interrupt, set the GPIO_INT_EDGE_NLEVEL register to 0. Upon a level interrupt occurring, the corresponding interrupt polarity depends on the register GPIO_INT_POL. The GPIO_INT_BOTH_EDGE and GPIO_INT_POL registers determines interrupt generation by rising or falling edge. If setting the GPIO_INT_BOTH_EDGE register, both rising and falling edges can generate interrupt. If the register GPIO_INT_BOTH_EDGE is ‘0’, the register GPIO_INT_POL defines rising or falling edge. 5.9.3 Software Procedure 5.9.3.1 GPIO wakeup The following sequence should be followed in GPIO wakeup flow. Before hibernate/sleep. 1. Enable several GPIO as wakeup source 2. Set GPIO_PWT_DEB_CONFIG register bit GPIO_PWT_DEB. Select input filter (debounce) function. 3. Set GPIO_Pxx_CONFIG register. Configure wakeup source’s IO mode to GPIO mode and set it to input mode. 4. Set GPIO_PWT_POL register. Configure wakeup source’s polarity. 5. Set GPIO_PWT_EN register. Enable wakeup source IO. © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 37 Maxscend Confidential MXD2656A1 Datasheet 6. Set GPIO_PWT_32K_LOAD register. Load registers (GPIO_PWT_DEB_CONFIG, GPIO_PWT_POL and GPIO_PWT_EN) to take effect in 32KHz working domain. 7. Go hibernate process. Wakeup process. 1. One or more wakeup sources toggle for debounce time. Then internal signal io_pmu_wakeup toggles from ‘0’ to ‘1’. 2. PMU goes to wakeup process. 3. After CPU wakeup, software set GPIO_PWT_EN register to ‘0’. After debounce time, the internal wakeup state will be cleared, but io_pmu_wakeup is still at high. 4. set GPIO_PWT_WAKEUP_CLR register to clear io_pmu_wakeup. 5. set GPIO_Pxx_CONFIG reg. The wakeup source can be used for normal function. 5.9.4 GPIO Interrupt GPIO interrupts are described in register GPIO_INT_STATUS. 5.9.5 GPIO Registers Table 31 GPIO Instance Base Address Peripheral Instance Description 0x40001000 GPIO GPIO General Purpose Input/Output Table 32 GPIO Register Map Address Offset Name Description 0x00 GPIO_INT_STATUS GPIO Interrupt Status 0x04 GPIO_INT_MASK GPIO Interrupt Enable 0x08 GPIO_INT_CLEAR GPIO Interrupt Flag Clear Register 0x14 GPIO_OUT_STATUS GPIO Output Driver Value 0x18 GPIO_OUT_SET GPIO Output Driver Value Setting 0x1C GPIO_OUT_CLEAR GPIO Output Driver Value Clear 0x20 GPIO_INT_POL GPIO Interrupt Polarity 0x24 GPIO_INT_EDGE_NLEVEL GPIO Interrupt Mode 0x28 GPIO_INT_BOTH_EDGE GPIO Interrupt Edge Mode 0x2C GPIO_INT0_EN GPIO Interrupt Connected to IRQ_GPIO_17 0x30 GPIO_INT1_EN GPIO Interrupt Connected to IRQ_GPIO_18 0x34 GPIO_INT2_EN GPIO Interrupt Connected to IRQ_GPIO_19 0x38 GPIO_IN GPIO Input Value Register 0x3C GPIO_P00_CONFIG GPIO P00 Configuration Register 0x40 GPIO_P01_CONFIG GPIO P01 Configuration Register © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 38 Maxscend Confidential MXD2656A1 Datasheet 0x44 GPIO_P02_CONFIG GPIO P02 Configuration Register 0x48 GPIO_P03_CONFIG GPIO P03 Configuration Register 0x4C GPIO_P04_CONFIG GPIO P04 Configuration Register 0x50 GPIO_P05_CONFIG GPIO P05 Configuration Register 0x54 GPIO_P06_CONFIG GPIO P06 Configuration Register 0x58 GPIO_P07_CONFIG GPIO P07 Configuration Register 0x5C GPIO_P08_CONFIG GPIO P08 Configuration Register 0x60 GPIO_P09_CONFIG GPIO P09 Configuration Register 0x64 GPIO_P10_CONFIG GPIO P10 Configuration Register 0x68 GPIO_P11_CONFIG GPIO P11 Configuration Register 0x6C GPIO_P12_CONFIG GPIO P12 Configuration Register 0x70 GPIO_P13_CONFIG GPIO P13 Configuration Register 0x74 GPIO_P14_CONFIG GPIO P14 Configuration Register 0x78 GPIO_P15_CONFIG GPIO P15 Configuration Register 0x7C GPIO_P16_CONFIG GPIO P16 Configuration Register 0x80 GPIO_P17_CONFIG GPIO P17 Configuration Register 0x84 GPIO_P18_CONFIG GPIO P18 Configuration Register 0x88 GPIO_P19_CONFIG GPIO P19 Configuration Register 0x8C GPIO_P20_CONFIG GPIO P20 Configuration Register 0x90 GPIO_P21_CONFIG GPIO P21 Configuration Register 0x94 GPIO_P22_CONFIG GPIO P22 Configuration Register 0x98 GPIO_P23_CONFIG GPIO P23 Configuration Register 0x9C GPIO_P24_CONFIG GPIO P24 Configuration Register 0xA0 GPIO_PWT_32K_LOAD GPIO Load Enable 0xA4 GPIO_PWT_DEB_CONFIG GPIO Debounce Configuration Register 0xA8 GPIO_PWT_POL GPIO Wakeup Polarity 0xAC GPIO_PWT_EN GPIO Wakeup Enable 0xB0 GPIO_PWT_WAKEUP_CLR GPIO Wakeup Flag Clear Register 0xB4 GPIO_IOMUX_DEBUG_CTRL GPIO Debug Mode Configuration Register 0xDC GPIO_SW_SET Serial Wire Output Value Setting 0xE0 GPIO_SW_CLR Serial Wire Output Value Clear 0xB0 GPIO_SWCLK_CONFIG SWCLK Configuration Register 0xB4 GPIO_SWDIO_CONFIG SWDIO Configuration Register 0xEC GPIO_SW_IN Serial Wire Input Value Table 33 GPIO_INT_STATUS (GPIO_BASE_ADDR+0x00) Bit Field Name 24:0 GPIO_INT_STATUS Reset RW 0x0 R Description GPIO0-GPIO24 interrupt status 0: invalid 1: valid © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 39 Maxscend Confidential MXD2656A1 Datasheet Table 34 GPIO_INT_MASK (GPIO_BASE_ADDR+0x04) Bit Field Name Reset 24:0 GPIO_INT_MASK 0x0 RW RW Description GPIO0-GPIO24 interrupt enable 0: disable 1: enable Table 35 GPIO_INT_CLEAR (GPIO_BASE_ADDR+0x08) Bit Field Name 24:0 GPIO_INT_CLEAR Reset RW 0x0 W Description GPIO0-GPIO24 interrupt flag clear 0: invalid 1: clear Table 36 GPIO_OUT_STATUS (GPIO_BASE_ADDR+0x14) Bit Field Name 24:0 GPIO_OUT_STATUS Reset RW 0x0 R Description GPIO0-GPIO24 output driver value 0: low 1: high Table 37 GPIO_OUT_SET (GPIO_BASE_ADDR+0x18) Bit Field Name 24:0 GPIO_OUT_SET Reset RW 0x0 W Description GPIO0-GPIO24 output driver value setting 0: invalid 1: high Table 38 GPIO_OUT_CLEAR (GPIO_BASE_ADDR+0x1C) Bit Field Name 24:0 GPIO_OUT_CLEAR Reset RW 0x0 W Description GPIO0-GPIO24 output driver value clear 0: invalid 1: output driver value to low Table 39 GPIO_INT_POL (GPIO_BASE_ADDR+0x20) Bit Field Name 24:0 GPIO_INT_POL Reset 0x0 RW RW Description GPIO0-GPIO24 interrupt polarity when GPIO_INT_EDGE_NLEVEL is high and GPIO_INT_BOTH_EDGE is low 0: rising edge generates interrupt 1: falling edge generates interrupt when GPIO_INT_EDGE_NLEVEL is low 0: low level generates interrupt 1: high level generates interrupt Table 40 GPIO_INT_EDGE_NLEVEL (GPIO_BASE_ADDR+0x24) © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 40 Maxscend Confidential MXD2656A1 Datasheet Bit Field Name Reset 24:0 GPIO_INT_EDGE_NLEVEL 0x0 RW RW Description GPIO0-GPIO24 interrupt mode 0: level trigger mode 1: edge trigger mode Table 41 GPIO_INT_BOTH_EDGE (GPIO_BASE_ADDR+0x28) Bit Field Name Reset 24:0 GPIO_INT_BOTH_EDGE 0x0 RW RW Description single or both edge mode for GPIO0-GPIO24 interrupt edge trigger 0: single edge trigger. When GPIO_INT_POL is high, falling edge trigger generate interrupt. When GPIO_INT_POL is low, rising edge trigger generate interrupt. 1: both edge trigger Table 42 GPIO_INT0_EN (GPIO_BASE_ADDR+0x2C) Bit Field Name 24:0 GPIO_INT0_EN Reset 0x0 RW RW Description GPIO0-GPIO24 selection for IRQ_GPIO_17 0: not selected 1: selected Table 43 GPIO_INT1_EN (GPIO_BASE_ADDR+0x30) Bit Field Name 24:0 GPIO_INT1_EN Reset 0x0 RW RW Description GPIO0-GPIO24 selection for IRQ_GPIO_18 0: not selected 1: selected Table 44 GPIO_INT2_EN (GPIO_BASE_ADDR+0x34) Bit Field Name 24:0 GPIO_INT2_EN Reset 0x0 RW RW Description GPIO0-GPIO24 selection for IRQ_GPIO_19 0: not selected 1: selected Table 45 GPIO_IN (GPIO_BASE_ADDR+0x38) Bit Field Name 24:0 GPIO_IN Reset RW 0x0 R Description GPIO0-GPIO24 input value, GPIO_P(00-24)_IE should be set high before reading GPIO_IN 0: input value is low 1: input value is high Table 46 GPIO_P00_CONFIG (GPIO_BASE_ADDR+0x3C) Bit Field Name Reset RW Description © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 41 Maxscend Confidential MXD2656A1 Datasheet 12 GPIO_P00_CS 0 RW Schmitt trigger mode for GPIO input buffer 0: no Schmitt trigger 1: Schmitt trigger 11 GPIO_P00_DSH 0 RW driving strength high bit {dsh,dsl}: 00: lowest driving strength 01: lower driving strength 10: higher driving strength 11: highest driving strength 10 GPIO_P00_DSL 0 RW driving strength low bit {dsh,dsl}: 00: lowest driving strength 01: lower driving strength 10: higher driving strength 11: highest driving strength 9 GPIO_P00_PU 1 RW pull up enable control 0: disable 1: enable 8 GPIO_P00_PD 0 RW pull down enable control 0: disable 1: enable 7 GPIO_P00_IE 1 RW input enable control 0: disable 1: enable 6 GPIO_P00_OE 0 RW output enable control 0: disable 1: enable 5:0 GPIO_P00_PID 0x0 RW function of port 0: GPIO 1: uart 0 txd 2: uart 0 rxd 3: uart 0 cts 4: uart 0 rts 5: spi 0 clk 6: spi 0 csn 7: spi 0 mosi 8: spi 0 miso 9: i2c 0 scl 10: i2c 0 sda 11: pwm 0 12: pwm 1 13: pwm 2 © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 42 Maxscend Confidential MXD2656A1 Datasheet 14: pwm 3 15: 7816 clk 16: 7816 data 17: 7816 rst_n 18: ir 19: i2s mclk 20: i2s bclk 21: i2s wclk 22: i2s data 23: uart 1 txd 24: uart 1 rxd 25: uart 1 cts 26: uart 1 rts 27: flash clk 28: flash cs 29: flash si 30: flash so 31: flash wp 32: flash hold 33: PLL12M/16M/8M/4M/2M/1M 34: qdec phase_a in 35: qdec phase_b in 36: qdec led_out 37~63: reserved Table 47 GPIO_P01_CONFIG (GPIO_BASE_ADDR+0x40) Bit Field Name Reset RW Description 12 GPIO_P01_CS 0 RW see GPIO_P00 11 GPIO_P01_DSH 0 RW see GPIO_P00 10 GPIO_P01_DSL 0 RW see GPIO_P00 9 GPIO_P01_PU 1 RW see GPIO_P00 8 GPIO_P01_PD 0 RW see GPIO_P00 7 GPIO_P01_IE 1 RW see GPIO_P00 6 GPIO_P01_OE 0 RW see GPIO_P00 5:0 GPIO_P01_PID 0x0 RW see GPIO_P00 Table 48 GPIO_P02_CONFIG (GPIO_BASE_ADDR+0x44) Bit Field Name Reset RW Description 12 GPIO_P02_CS 0 RW see GPIO_P00 11 GPIO_P02_DSH 0 RW see GPIO_P00 10 GPIO_P02_DSL 0 RW see GPIO_P00 9 GPIO_P02_PU 1 RW see GPIO_P00 © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 43 Maxscend Confidential MXD2656A1 Datasheet 8 GPIO_P02_PD 0 RW see GPIO_P00 7 GPIO_P02_IE 1 RW see GPIO_P00 6 GPIO_P02_OE 0 RW see GPIO_P00 5:0 GPIO_P02_PID 0x0 RW see GPIO_P00 Table 49 GPIO_P03_CONFIG (GPIO_BASE_ADDR+0x48) Bit Field Name Reset RW Description 12 GPIO_P03_CS 0 RW see GPIO_P00 11 GPIO_P03_DSH 0 RW see GPIO_P00 10 GPIO_P03_DSL 0 RW see GPIO_P00 9 GPIO_P03_PU 1 RW see GPIO_P00 8 GPIO_P03_PD 0 RW see GPIO_P00 7 GPIO_P03_IE 1 RW see GPIO_P00 6 GPIO_P03_OE 0 RW see GPIO_P00 5:0 GPIO_P03_PID 0x0 RW see GPIO_P00 Table 50 GPIO_P04_CONFIG (GPIO_BASE_ADDR+0x4C) Bit Field Name Reset RW Description 12 GPIO_P04_CS 0 RW see GPIO_P00 11 GPIO_P04_DSH 0 RW see GPIO_P00 10 GPIO_P04_DSL 0 RW see GPIO_P00 9 GPIO_P04_PU 1 RW see GPIO_P00 8 GPIO_P04_PD 0 RW see GPIO_P00 7 GPIO_P04_IE 1 RW see GPIO_P00 6 GPIO_P04_OE 0 RW see GPIO_P00 5:0 GPIO_P04_PID 0x0 RW see GPIO_P00 Table 51 GPIO_P05_CONFIG (GPIO_BASE_ADDR+0x50) Bit Field Name Reset RW Description 12 GPIO_P05_CS 0 RW see GPIO_P00 11 GPIO_P05_DSH 0 RW see GPIO_P00 10 GPIO_P05_DSL 0 RW see GPIO_P00 9 GPIO_P05_PU 1 RW see GPIO_P00 8 GPIO_P05_PD 0 RW see GPIO_P00 7 GPIO_P05_IE 1 RW see GPIO_P00 6 GPIO_P05_OE 0 RW see GPIO_P00 5:0 GPIO_P05_PID 0x0 RW see GPIO_P00 Table 52 GPIO_P06_CONFIG (GPIO_BASE_ADDR+0x54) Bit Field Name 12 GPIO_P06_CS Reset 0 RW RW Description see GPIO_P00 © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 44 Maxscend Confidential MXD2656A1 Datasheet 11 GPIO_P06_DSH 0 RW see GPIO_P00 10 GPIO_P06_DSL 0 RW see GPIO_P00 9 GPIO_P06_PU 1 RW see GPIO_P00 8 GPIO_P06_PD 0 RW see GPIO_P00 7 GPIO_P06_IE 1 RW see GPIO_P00 6 GPIO_P06_OE 0 RW see GPIO_P00 5:0 GPIO_P06_PID 0x0 RW see GPIO_P00 Table 53 GPIO_P07_CONFIG (GPIO_BASE_ADDR+0x58) Bit Field Name Reset RW Description 12 GPIO_P07_CS 0 RW see GPIO_P00 11 GPIO_P07_DSH 0 RW see GPIO_P00 10 GPIO_P07_DSL 0 RW see GPIO_P00 9 GPIO_P07_PU 1 RW see GPIO_P00 8 GPIO_P07_PD 0 RW see GPIO_P00 7 GPIO_P07_IE 1 RW see GPIO_P00 6 GPIO_P07_OE 0 RW see GPIO_P00 5:0 GPIO_P07_PID 0x0 RW see GPIO_P00 Table 54 GPIO_P08_CONFIG (GPIO_BASE_ADDR+0x5C) Bit Field Name Reset RW Description 12 GPIO_P08_CS 0 RW see GPIO_P00 11 GPIO_P08_DSH 0 RW see GPIO_P00 10 GPIO_P08_DSL 0 RW see GPIO_P00 9 GPIO_P08_PU 1 RW see GPIO_P00 8 GPIO_P08_PD 0 RW see GPIO_P00 7 GPIO_P08_IE 1 RW see GPIO_P00 6 GPIO_P08_OE 0 RW see GPIO_P00 5:0 GPIO_P08_PID 0x0 RW see GPIO_P00 Table 55 GPIO_P09_CONFIG (GPIO_BASE_ADDR+0x60) Bit Field Name Reset RW Description 12 GPIO_P09_CS 0 RW see GPIO_P00 11 GPIO_P09_DSH 0 RW see GPIO_P00 10 GPIO_P09_DSL 0 RW see GPIO_P00 9 GPIO_P09_PU 1 RW see GPIO_P00 8 GPIO_P09_PD 0 RW see GPIO_P00 7 GPIO_P09_IE 1 RW see GPIO_P00 6 GPIO_P09_OE 0 RW see GPIO_P00 5:0 GPIO_P09_PID 0x0 RW see GPIO_P00 © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 45 Maxscend Confidential MXD2656A1 Datasheet Table 56 GPIO_P10_CONFIG (GPIO_BASE_ADDR+0x64) Bit Field Name Reset RW Description 12 GPIO_P10_CS 0 RW see GPIO_P00 11 GPIO_P10_DSH 0 RW see GPIO_P00 10 GPIO_P10_DSL 0 RW see GPIO_P00 9 GPIO_P10_PU 1 RW see GPIO_P00 8 GPIO_P10_PD 0 RW see GPIO_P00 7 GPIO_P10_IE 1 RW see GPIO_P00 6 GPIO_P10_OE 0 RW see GPIO_P00 5:0 GPIO_P10_PID 0x0 RW see GPIO_P00 Table 57 GPIO_P11_CONFIG (GPIO_BASE_ADDR+0x68) Bit Field Name Reset RW Description 12 GPIO_P11_CS 0 RW see GPIO_P00 11 GPIO_P11_DSH 0 RW see GPIO_P00 10 GPIO_P11_DSL 0 RW see GPIO_P00 9 GPIO_P11_PU 1 RW see GPIO_P00 8 GPIO_P11_PD 0 RW see GPIO_P00 7 GPIO_P11_IE 1 RW see GPIO_P00 6 GPIO_P11_OE 0 RW see GPIO_P00 5:0 GPIO_P11_PID 0x0 RW see GPIO_P00 Table 58 GPIO_P12_CONFIG (GPIO_BASE_ADDR+0x6C) Bit Field Name Reset RW Description 12 GPIO_P12_CS 0 RW see GPIO_P00 11 GPIO_P12_DSH 0 RW see GPIO_P00 10 GPIO_P12_DSL 0 RW see GPIO_P00 9 GPIO_P12_PU 1 RW see GPIO_P00 8 GPIO_P12_PD 0 RW see GPIO_P00 7 GPIO_P12_IE 1 RW see GPIO_P00 6 GPIO_P12_OE 0 RW see GPIO_P00 5:0 GPIO_P12_PID 0x0 RW see GPIO_P00 Table 59 GPIO_P13_CONFIG (GPIO_BASE_ADDR+0x70) Bit Field Name Reset RW Description 12 GPIO_P13_CS 0 RW see GPIO_P00 11 GPIO_P13_DSH 0 RW see GPIO_P00 10 GPIO_P13_DSL 0 RW see GPIO_P00 9 GPIO_P13_PU 1 RW see GPIO_P00 8 GPIO_P13_PD 0 RW see GPIO_P00 7 GPIO_P13_IE 1 RW see GPIO_P00 © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 46 Maxscend Confidential MXD2656A1 Datasheet 6 GPIO_P13_OE 0 RW see GPIO_P00 5:0 GPIO_P13_PID 0x0 RW see GPIO_P00 Table 60 GPIO_P14_CONFIG (GPIO_BASE_ADDR+0x74) Bit Field Name Reset RW Description 12 GPIO_P14_CS 0 RW see GPIO_P00 11 GPIO_P14_DSH 0 RW see GPIO_P00 10 GPIO_P14_DSL 0 RW see GPIO_P00 9 GPIO_P14_PU 1 RW see GPIO_P00 8 GPIO_P14_PD 0 RW see GPIO_P00 7 GPIO_P14_IE 1 RW see GPIO_P00 6 GPIO_P14_OE 0 RW see GPIO_P00 5:0 GPIO_P14_PID 0x0 RW see GPIO_P00 Table 61 GPIO_P15_CONFIG (GPIO_BASE_ADDR+0x78) Bit Field Name Reset RW Description 12 GPIO_P15_CS 0 RW see GPIO_P00 11 GPIO_P15_DSH 0 RW see GPIO_P00 10 GPIO_P15_DSL 0 RW see GPIO_P00 9 GPIO_P15_PU 1 RW see GPIO_P00 8 GPIO_P15_PD 0 RW see GPIO_P00 7 GPIO_P15_IE 1 RW see GPIO_P00 6 GPIO_P15_OE 0 RW see GPIO_P00 5:0 GPIO_P15_PID 0x0 RW see GPIO_P00 Table 62 GPIO_P16_CONFIG (GPIO_BASE_ADDR+0x7C) Bit Field Name Reset RW Description 12 GPIO_P16_CS 0 RW see GPIO_P00 11 GPIO_P16_DSH 0 RW see GPIO_P00 10 GPIO_P16_DSL 0 RW see GPIO_P00 9 GPIO_P16_PU 1 RW see GPIO_P00 8 GPIO_P16_PD 0 RW see GPIO_P00 7 GPIO_P16_IE 1 RW see GPIO_P00 6 GPIO_P16_OE 0 RW see GPIO_P00 5:0 GPIO_P16_PID 0x0 RW see GPIO_P00 Table 63 GPIO_P17_CONFIG (GPIO_BASE_ADDR+0x80) Bit Field Name Reset RW Description 12 GPIO_P17_CS 0 RW see GPIO_P00 11 GPIO_P17_DSH 0 RW see GPIO_P00 10 GPIO_P17_DSL 0 RW see GPIO_P00 © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 47 Maxscend Confidential MXD2656A1 Datasheet 9 GPIO_P17_PU 1 RW see GPIO_P00 8 GPIO_P17_PD 0 RW see GPIO_P00 7 GPIO_P17_IE 1 RW see GPIO_P00 6 GPIO_P17_OE 0 RW see GPIO_P00 5:0 GPIO_P17_PID 0x0 RW see GPIO_P00 Table 64 GPIO_P18_CONFIG (GPIO_BASE_ADDR+0x84) Bit Field Name Reset RW Description 12 GPIO_P18_CS 0 RW see GPIO_P00 11 GPIO_P18_DSH 0 RW see GPIO_P00 10 GPIO_P18_DSL 0 RW see GPIO_P00 9 GPIO_P18_PU 1 RW see GPIO_P00 8 GPIO_P18_PD 0 RW see GPIO_P00 7 GPIO_P18_IE 1 RW see GPIO_P00 6 GPIO_P18_OE 0 RW see GPIO_P00 5:0 GPIO_P18_PID 0x0 RW see GPIO_P00 Table 65 GPIO_P19_CONFIG (GPIO_BASE_ADDR+0x88) Bit Field Name Reset RW Description 12 GPIO_P19_CS 0 RW see GPIO_P00 11 GPIO_P19_DSH 0 RW see GPIO_P00 10 GPIO_P19_DSL 0 RW see GPIO_P00 9 GPIO_P19_PU 1 RW see GPIO_P00 8 GPIO_P19_PD 0 RW see GPIO_P00 7 GPIO_P19_IE 1 RW see GPIO_P00 6 GPIO_P19_OE 0 RW see GPIO_P00 5:0 GPIO_P19_PID 0x0 RW see GPIO_P00 Table 66 GPIO_P20_CONFIG (GPIO_BASE_ADDR+0x8C) Bit Field Name Reset RW Description 12 GPIO_P20_CS 0 RW see GPIO_P00 11 GPIO_P20_DSH 0 RW see GPIO_P00 10 GPIO_P20_DSL 0 RW see GPIO_P00 9 GPIO_P20_PU 1 RW see GPIO_P00 8 GPIO_P20_PD 0 RW see GPIO_P00 7 GPIO_P20_IE 1 RW see GPIO_P00 6 GPIO_P20_OE 0 RW see GPIO_P00 5:0 GPIO_P20_PID 0x0 RW see GPIO_P00 Table 67 GPIO_P21_CONFIG (GPIO_BASE_ADDR+0x90) Bit Field Name Reset RW Description © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 48 Maxscend Confidential MXD2656A1 Datasheet 12 GPIO_P21_CS 0 RW see GPIO_P00 11 GPIO_P21_DSH 0 RW see GPIO_P00 10 GPIO_P21_DSL 0 RW see GPIO_P00 9 GPIO_P21_PU 1 RW see GPIO_P00 8 GPIO_P21_PD 0 RW see GPIO_P00 7 GPIO_P21_IE 1 RW see GPIO_P00 6 GPIO_P21_OE 0 RW see GPIO_P00 5:0 GPIO_P21_PID 0x0 RW function of port 0: GPIO 1: uart 0 txd 2: uart 0 rxd 3: uart 0 cts 4: uart 0 rts 5: spi 0 clk 6: spi 0 csn 7: spi 0 mosi 8: spi 0 miso 9: i2c 0 scl 10: i2c 0 sda 11: pwm 0 12: pwm 1 13: pwm 2 14: pwm 3 15: 7816 clk 16: 7816 data 17: 7816 rst_n 18: ir 19: i2s mclk 20: i2s bclk 21: i2s wclk 22: i2s data 23: uart 1 txd 24: uart 1 rxd 25: uart 1 cts 26: uart 1 rts 27: flash clk 28: flash cs 29: flash si 30: flash so 31: flash wp 32: flash hold 33: PLL12M/16M/8M/4M/2M/1M © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 49 Maxscend Confidential MXD2656A1 Datasheet 34: qdec phase_a in 35: qdec phase_b in 36: qdec led_out 37~42: reserved 43: test clock 44~63: reserved Table 68 GPIO_P22_CONFIG (GPIO_BASE_ADDR+0x94) Bit Field Name Reset RW Description 12 GPIO_P22_CS 0 RW see GPIO_P00 11 GPIO_P22_DSH 0 RW see GPIO_P00 10 GPIO_P22_DSL 0 RW see GPIO_P00 9 GPIO_P22_PU 1 RW see GPIO_P00 8 GPIO_P22_PD 0 RW see GPIO_P00 7 GPIO_P22_IE 1 RW see GPIO_P00 6 GPIO_P22_OE 0 RW see GPIO_P00 5:0 GPIO_P22_PID 0x0 RW see GPIO_P00 Table 69 GPIO_P23_CONFIG (GPIO_BASE_ADDR+0x98) Bit Field Name Reset RW Description 12 GPIO_P23_CS 0 RW see GPIO_P00 11 GPIO_P23_DSH 0 RW see GPIO_P00 10 GPIO_P23_DSL 0 RW see GPIO_P00 9 GPIO_P23_PU 1 RW see GPIO_P00 8 GPIO_P23_PD 0 RW see GPIO_P00 7 GPIO_P23_IE 1 RW see GPIO_P00 6 GPIO_P23_OE 0 RW see GPIO_P00 5:0 GPIO_P23_PID 0x0 RW see GPIO_P00 Table 70 GPIO_P24_CONFIG (GPIO_BASE_ADDR+0x9C) Bit Field Name Reset RW Description 12 GPIO_P24_CS 0 RW see GPIO_P00 11 GPIO_P24_DSH 0 RW see GPIO_P00 10 GPIO_P24_DSL 0 RW see GPIO_P00 9 GPIO_P24_PU 1 RW see GPIO_P00 8 GPIO_P24_PD 0 RW see GPIO_P00 7 GPIO_P24_IE 1 RW see GPIO_P00 6 GPIO_P24_OE 0 RW see GPIO_P00 5:0 GPIO_P24_PID 0x0 RW see GPIO_P00 Table 71 GPIO_PWT_32K_LOAD (GPIO_BASE_ADDR+0xA0) © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 50 Maxscend Confidential MXD2656A1 Datasheet Bit Field Name Reset 0 GPIO_PWT_32K_LOAD 0 RW W Description Load event for registers (GPIO_PWT_DEB_CONFIG, GPIO_PWT_POL and GPIO_PWT_EN) to take effect in 32KHz clock working domain 0: invalid 1: load enable Table 72 GPIO_PWT_DEB_CONFIG (GPIO_BASE_ADDR+0xA4) Bit Field Name Reset 6 GPIO_PWT_MS_N32K 0 RW RW Description pin wakeup debounce time unit 0: 30us 1: 1ms 5:0 GPIO_PWT_DEB 0x0 RW pin wakeup debounce time counter (N) 0: no debounce 1~63: debounce time is N*PWT_MS_N32K Note: debounce function can improve pin wake up robustness Table 73 GPIO_PWT_POL (GPIO_BASE_ADDR+0xA8) Bit Field Name Reset 24:0 GPIO_PWT_POL 0x0 RW RW Description GPIO0-GPIO24 pin wakeup level polarity 0: low level wakeup 1: high level wakeup Table 74 GPIO_PWT_EN (GPIO_BASE_ADDR+0xAC) Bit Field Name Reset 24:0 GPIO_PWT_EN 0x0 RW RW Description GPIO0-GPIO24 pin wakeup enable control 0: disable 1: enable Table 75 GPIO_PWT_WAKEUP_CLR (GPIO_BASE_ADDR+0xB0) Bit Field Name 0 GPIO_PWT_WAKEUP_CLR Reset RW 0 W Description pin wakeup (debounce mode) source clear 0: invalid 1: clear Table 76 GPIO_IOMUX_DEBUG_CTRL (GPIO_BASE_ADDR+0xB4) Bit Field Name 2 GPIO_IOMUX_RX_EN Reset 0 RW RW Description rx or tx selection for Bluetooth debug mode 0: tx mode, GPIO inputs GFSK data 1: rx mode, GPIO outputs ADC data © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 51 Maxscend Confidential MXD2656A1 Datasheet 1 GPIO_IOMUX_MANUAL 0 RW rx mode enable selection in debug mode 0: rx mode enable selection from trxs modu le 1: rx mode enable selection from registers 0 GPIO_IOMUX_DEBUG 0 RW GPIO debug mode 0: GPIO for normal function mode 1: GPIO for Bluetooth debug mode Table 77 GPIO_SW_SET (GPIO_BASE_ADDR+0xDC) Bit Field Name Reset 1 GPIO_SWDIO_SET 0 RW W Description swdio output driver value setting 0: invalid 1: high 0 GPIO_SWCLK_SET 0 W swclk output driver value setting 0: invalid 1: high Table 78 GPIO_SW_CLR (GPIO_BASE_ADDR+0xE0) Bit Field Name Reset 1 GPIO_SWDIO_CLR 0 RW W Description swdio output driver value clear 0: invalid 1: output driver value to low 0 GPIO_SWCLK_CLR 0 W swclk output driver value clear 0: invalid 1: output driver value to low Table 79 GPIO_SWCLK_CONFIG (GPIO_BASE_ADDR+0xE4) Bit Field Name Reset RW Description 6 GPIO_SWCLK_CS 0 RW see GPIO_P00 5 GPIO_SWCLK_DSH 0 RW see GPIO_P00 4 GPIO_SWCLK_DSL 0 RW see GPIO_P00 3 GPIO_SWCLK_PU 0 RW see GPIO_P00 2 GPIO_SWCLK_PD 1 RW see GPIO_P00 1 GPIO_SWCLK_IE 1 RW see GPIO_P00 0 GPIO_SWCLK_OE 0 RW see GPIO_P00 Table 80 GPIO_SWDIO_CONFIG (GPIO_BASE_ADDR+0xE8) Bit Field Name Reset RW Description 6 GPIO_SWDIO_CS 0 RW see GPIO_P00 5 GPIO_SWDIO_DSH 0 RW see GPIO_P00 4 GPIO_SWDIO_DSL 0 RW see GPIO_P00 © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 52 Maxscend Confidential MXD2656A1 Datasheet 3 GPIO_SWDIO_PU 0 RW see GPIO_P00 2 GPIO_SWDIO_PD 1 RW see GPIO_P00 1 GPIO_SWDIO_IE 1 RW see GPIO_P00 0 GPIO_SWDIO_OE 0 RW see GPIO_P00 Table 81 GPIO_SW_IN (GPIO_BASE_ADDR+0xEC) Bit Field Name 1 GPIO_SWDIO_IN Reset 0 RW R Description swdio input value, GPIO_SWDIO_IE should be set high before reading 0: input value is low 1: input value is high 0 GPIO_SWCLK_IN 0 R swclk input value, GPIO_SWCLK_IE should be set high before reading 0: input value is low 1: input value is high 5.10 General Purpose ADC 5.10.1 Feature The GPADC (General Purpose Analog-to-Digital Converter) is a 9-bit successive approximation type ADC. The ADC has its voltage regulator (LDO) of 1.2V, which represents the full scale reference voltage. The main features are: 1. 9-bit dynamic ADC with configured clock frequency (up to 16MHz) 2. Four single-ended external GPIO input channels 3. Battery monitoring function 4. On-chip temperature sensor function 5. Digital down-sample with configurable ratio 5.10.2 Function Description The chip has a multiplexer between the ADC and four specific GPIO ports (GPIO7, GPIO8, GPIO10, GPIO11), and the GPIO input voltage range is 0~1.2 V. Furthermore, the ADC can be used to measure the battery voltage (VDDR) and the internal temperature. Only one function can be selected at the same time. Down-sample filtered data is stored in the register, which can be accessed through APB interface. © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 53 Maxscend Confidential MXD2656A1 Datasheet PAD VDDR R1 1.11M ANALOG GP_ADC_VBAT_EN R2 370K VSS GP_ADC_BUF_EN DIGITAL GP_ADC_EN SAR ADC Temp_sense TEMP_SENSE_EN [8:0] filter_en Dowm sample (1~4096) [8:0] APB BUS GP_ADC_BIAS_CTRL[1:0] GPIO7 GP_ADC_BUF_GAIN[1:0] GPIO8 MUX GPIO10 ADC clock generate (16MHz~250KHz) GP_ADC_CH_EN GPIO11 GP_ADC_CH_CHO[1:0] Figure 11 General Purpose ADC Block Diagram Enabling/disabling of the ADC is triggered by configuring bit GP_ADC_EN (it enables ADC LDO at the same time), and a settling time of 50 us is required before an AD-conversion can be started. The conversion itself is fast and takes approximately one clock cycle of 16 MHz (if ADC clock selected 16MHz), though the data handling will require several additional clock cycles, depending on the software code style. The fastest code can handle the data in four clock cycles of 16 MHz, resulting to a highest sampling rate of 16 MHz/5 = 3.2 MSamples/s. The ADC result also has some noises. The down-sample filter corrects ADC result (set bit FILTER_EN to 1). The filter takes more samples and the calculated average value reduces the noise and increases the resolution. The downsample ratio can be configured to 2~4096. The Temperature ADC data vs Temperature range is show in the figure below. Figure 12 ADC data vs Temperature © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 54 Maxscend Confidential MXD2656A1 Datasheet 5.10.3 Software Procedure The GPADC read procedure. 1. GPADC enable (set GP_ADC_EN) and wait 50us for ADC to stabilize 2. Restart GPADC module (set CLR_GPADC) 3. Select source to GPADC (GPIOs, Battery or Temperature) 4. GPADC buffer enable (set GP_ADC_BUF_EN) 5. If ADC_OK is 1 and GPADC_BREAK is 0, the data is valid. Read ADC data. 5.10.4 Registers Table 82 GPADC Instance Base Address Peripheral Instance Description 0x40017000 GPADC GPADC General Purpose ADC 0x4001e000 MISC MISC Miscellaneous Table 83 GPADC Register Map Address Offset Name Description 0x04 GPADC_CFG1 GPADC configure register 1 0x08 GPADC_SAD GPADC state and data 0x0c GPADC_DET_TH GPADC data overflow threshold 0x10 GPADC_CLR GPADC clears register 0x14 GPADC_CTRL GPADC control register Table 84 GPADC_CFG1 (GPADC_BASE_ADDR +0x4) Bit Field Name Reset RW Description 10 GP_ADC_VBAT_EN 0 RW VDDR measurement selection 0 : VDDR not selected 1 : VDDR selected 9:7 GP_ADC_CH_CHO 0 RW GPIOs channel selection 0 : select GPIO_7 1 : select GPIO_8 2 : select GPIO_10 3 : select GPIO_11 4~7 : reserved 6 GP_ADC_CH_EN 0 RW GPIOs measurement selection 0 : GPIOs not selected 1 : GPIOs selected 5:4 GP_ADC_BIAS_CTRL 0 RW Bias current selection , for debug 3:2 GP_ADC_BUF_GAIN 0 RW Buffer gain © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 55 Maxscend Confidential MXD2656A1 Datasheet 0 : 6dB 1 : 9dB 2 : 0dB 3 : 12dB 1 GP_ADC_BUF_EN 0 RW GPADC Buffer enable 0 : disable 1 : enable 0 GP_ADC_EN 0 RW GPADC enable 0 : disable 1 : enable Table 85 GPADC_SAD (GPADC_BASE_ADDR +0x8) Bit Field Name Reset RW Description 31 ADC_OK 0 R GPADC data valid flag 0 : invalid 1 : valid 30 ADC_OVERFLOW 0 R GPADC data overflow flag 0 : ADC_DATA less than register (ADC_DET_TH) 1 : ADC_DATA greater than register (ADC_DET_TH) 29 GPADC_BREAK 0 R GPADC break flag 0 : no break 1 : break 15:7 ADC_DATA 0 R 9 bits ADC data , if ADC_OK is 1 and GPADC_BREAK is 0, the data is valid Table 86 GPADC_DET_TH (GPADC_BASE_ADDR +0xC) Bit Field Name Reset RW Description 8:0 GPADC_DET_TH 0 RW ADC_DATA overflow threshold Table 87 GPADC_CLR (GPADC_BASE_ADDR +0x10) Bit Field Name Reset RW Description 1 CLR_GPADC 0 W restart GPADC module 0 : invalid 1 : restart 0 CLR_OVERFLOW 0 W clear ADC_OVERFLOW flag 0 : invalid 1 : clear Table 88 GPADC_CTRL (GPADC_BASE_ADDR +0x14) Bit Field Name Reset RW Description 13:6 EN_DIG_DLY 0x40 RW GPADC stable time from GP_ADC_EN setting to 1. Unit : 1 ADC clock cycle © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 56 Maxscend Confidential MXD2656A1 Datasheet 5 CAP_EDGE_SEL 0 RW clock edge selection to sample GPADC data 0 : negedge 1 : posedge 4:1 DOWNSAMPLE_SEL 0x6 RW GPADC down-sample frequency selection 1:2 2:4 3:8 4 : 16 5 : 32 6 : 64 7 : 128 8 : 256 9 : 512 10 : 1024 11 : 2048 12 : 4096 0,13~15 : reserved for future use 0 FILTER_EN 0x1 RW GPADC down-sample filter enable 0 : disable 1 : enable Table 89 MISC Register Map Address Offset Name Description 0xF0 GPADC_CFG2 GPADC configure register 2 Table 90 TEMP_SENSE_EN(MISC_BASE_ADDR +0xF0) Bit Field Name Reset RW Description 7 TEMP_SENSE_EN 0 RW TEMP_SENSE measurement selection 0 : TEMP_SENSE not selected 1 : TEMP_SENSE selected 5.11 UART The UART is compliant to the industry-standard 16550 and is used for serial communication with a peripheral data set. Data is written from a master (CPU/DMA) over the APB bus to the UART and it is converted to serial format and transmitted to the destination device. Serial data is also received by the UART and stored in internal FIFO, and the master (CPU/DMA) can read them back. Both UARTs support hardware flow control signals (RTS, CTS). © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 57 Maxscend Confidential MXD2656A1 Datasheet 5.11.1 Feature 1. 8 bytes transmit and receive FIFOs 2. Hardware flow control support (CTS/RTS) 3. Functionality based on the 16550 industry standard 4. Programmable serial data baud rate 5. Programmable character properties, such as number of data bits per character (5-8) 6. Programmable parity bit (with odd/even/stick/no parity) 7. Programmable stop bits (1, 1.5 or 2) 8. Line break generation and detection 9. RX timeout interrupt support 5.11.2 Function Description An overview of the UART module is shown in figure below. APB BUS CTS UART Control and status TX Buffer (8 bytes) RX Buffer (8 bytes) RTS IO MUX TX Shift Register TXD RXD RX Shift Register RXD TXD Figure 13 UART overview 5.11.2.1 Frame Format The frame format consists of start bit, data bits, optional parity bit and stop bit(s), as shown in the figure below. RXD/TXD START bit bit bit parity STOP 5~8 bits Figure 14 UART Frame Format A frame starts with one start bit, where the line is driven low for one bit-period. The start bit indicates the start of a frame, and it is used for synchronization. A parity bit may be added to the serial character. This bit appears after the last data bit and before the stop bit(s), and it provides the UART with the ability to perform simple error checking on the received data. © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 58 Maxscend Confidential MXD2656A1 Datasheet The number of data bits in a frame is set by UARTx_BYTE_SIZE in UARTx_CONFIG register, see the table below. Table 91 UART Data Bits BYTE_SIZE Number of Date Bits 0 5 1 6 2 7 3 8 (default) The number of stop-bits is set by UARTx_STOP_BIT in UARTx_CONFIG register, see the table below. Table 92 UART Stop Bits STOP_BIT Number of Stop Bits 0 1 (default) 1 1.5 2/3 2 The order in which the data bits are transmitted and received is defined by UARTx_MSB in UARTx_CONFIG register. When UARTx_MSB is low, data in a frame is sent and received with the least significant bit first. When it is high, the most significant bit comes first. 5.11.2.2 Transmission The first step of a transmission is storing bytes in the transmit buffer. When the transmission shift register is empty and ready for new data, a frame from the transmit buffer is loaded into the shift register, and transmission begins. When the frame has been transmitted, a new frame is loaded into the shift register if available, and transmission continues. If the transmit buffer is empty, the transmitter goes to an idle state, waiting for a new frame available. If flow control is enabled through the UARTx_FLOW_CTRL_EN field in the UARTx_CONFIG register, a transmission will be automatically suspended when CTS is deactivated and resumed when CTS is activated again. A frame can be loaded into the buffer by writing to UARTx_TFIFO_WR_DATA. When writing more frames to the transmit buffer than the free space there is, the TX FIFO overflow interrupt flag in UARTx_INT_STATUS will be set, indicating the overflow. The data already in the transmit buffer is preserved in this case, and no new data is written in. The transmit buffer and the transmit shift register can be cleared by setting UARTx_FIFO_CLR. This will prevent the UART from transmitting the old data in the buffer and shift register, and the space is ready for new data after clearing. © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 59 Maxscend Confidential MXD2656A1 Datasheet 5.11.2.3 Reception Data reception is enabled when UARTx clock is enabled. When the receiver is enabled, it actively samples the input looking for a transition from high to low indicating the start baud of a new frame. When a start baud is found, reception of the new frame begins if the receive shift register is empty and ready for new data. When the frame has been received, it is pushed into the receive buffer, making the shift register ready for new frame. If the receive buffer is full, the received frame remains in the shift register until more space in the receive buffer is available. If an incoming frame is detected while both the receive buffer and the receive shift register are full, the data in the shift register is overwritten. If flow control is enabled through the UARTx_FLOW_CTRL_EN field in the UARTx_CONFIG register, the RTS signal will be activated when the UART receives eight bytes in its internal RX FIFO. Data can be read from the receive buffer through UARTx_RFIFO_RD_DATA register. When the data is available in the receive buffer, the RX FIFO not empty flag in UARTx_INT_STATUS is set. When the buffer becomes full, RX FIFO overflow interrupt flag in UARTx_INT_STATUS is set. To know how many bytes have been received into the RX buffer, the CPU can read the UARTx_RFIFO_CNT field in UARTx_FIFO_CNT register. The receive buffer and the receive shift register can be cleared by setting UARTx_FIFO_CLR. Any frame currently being received will be discarded. 5.11.2.4 Parity Error and Framing Error When a parity error is detected in an incoming frame, the interrupt flag UARTx_RXD_PARITY_ERROR is set. Frames with parity errors are not loaded into the receive buffer. When a framing error (stop bit error) is detected in an incoming frame, the interrupt flag UARTx_RXD_STOP_ERROR is set. Frames with framing errors are not loaded into the receive buffer. 5.11.3 Software Procedure The transmit buffer and receive buffer can be accessed by CPU and DMA. CPU transmit flow: 1. CPU receives an under threshold interrupt when TX FIFO data counter under threshold. 2. CPU sends data to TX FIFO until TX FIFO data counter is full. 3. CPU clears interrupt. 4. Repeat 1~3 until transfer is done. CPU receive flow: © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 60 Maxscend Confidential MXD2656A1 Datasheet 1. CPU receives an over threshold interrupt when RX FIFO data counter over threshold. 2. CPU read RX FIFO data until RX FIFO data counter is empty. 3. CPU clears interrupt. 4. Repeat 1~3 until transfer is done. DMA transmit flow: 1. CPU configures DMA registers for selecting UART interface and TX FIFO address. 2. UART send TX request to DMA when TX FIFO data counter under threshold. 3. DMA writes data to TX FIFO. 4. Repeat 2~3 until reach DMA channel counter. DMA receive flow: 1. CPU configures DMA registers for selecting UART interface and RX FIFO address. 2. DMA receives RX request when RX FIFO data counter over threshold. 3. DMA read RX FIFO data until RX FIFO data counter is under threshold. 4. Repeat 2~3 until reach DMA channel counter. 5.11.4 UART Interrupt UART interrupt table as shown in below. Table 93 UART Interrupt Interrupt Number Interrupt name Description 0 STOP_ERROR UART receives an error stop bit. 1 PARITY_ERROR UART receives an error parity bit. 2 LINE_BREAK UART detects line break event. 3 TIMEOUT RX FIFO is not empty, and no further data is received. 4 TX_FIFO_UNDER_THLD TX FIFO data number is under threshold. 5 TX_FIFO_EMPTY TX FIFO is empty. 6 RX_FIFO_OVER_THLD RX FIFO data number is over threshold. 7 RX_FIFO_OVERFLOW RX FIFO data number is overflow. 8 RX_FIFO_NOT_EMPTY TX FIFO is not empty. 9 RX_FIFO_UNDERFLOW RX FIFO data number is under threshold. 10 TX_FIFO_OVERFLOW TX FIFO data number is overflow. 5.11.4.1 Error Interrupt The error interrupt is asserted when an error occurs in the reception of data by the UART. The interrupt can be caused by the following error conditions:  Framing (STOP_ERROR) © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 61 Maxscend Confidential MXD2656A1 Datasheet  Parity (PARITY_ERROR)  Break (LINE_BREAK) The cause of the interrupt is available by reading the UARTx_UART_INT_STATUS registers. The interrupt can be cleared by writing to the relevant bits of the UARTx_UART_INT_CLEAR register. 5.11.4.2 Timeout Interrupt The receive timeout interrupt is asserted when the RX FIFO is not empty, and no further data is received (or no correct start bit of a frame is detected in the RXD line) over a programmable timeout period (TO_THLD in UARTx_CONFIG register). This mechanism ensures that the user is aware that data is still present in the RX FIFO and requires servicing. The receive timeout interrupt is cleared when a ‘1’ is written to the corresponding bit of the UARTx_UART_INT_CLEAR register. 5.11.4.3 Transmit Interrupt The transmit interrupt is asserted HIGH when one of the following conditions occurs:  TX_FIFO_EMPTY The interrupt is set when no data in TX FIFO, or all written data popped out from the TX FIFO. TX FIFO EMPTY doesn’t mean the shift register is empty too. Software should wait more time for the shift register bits shifting out.  TX_FIFO_UNDER_THLD If the number of data in the TX FIFO is less than the register (TFIFO_THLD), this bit is asserted.  TX_FIFO_OVERFLOW If the written data in TX FIFO is full (the number is eight), a new write will trigger the bit to high state. 5.11.4.4 Receive Interrupt The receive interrupt is asserted HIGH when one of the following conditions occurs:  RX_FIFO_NOT_EMPTY The interrupt is set when RX FIFO is not empty.  RX_FIFO_UNDERFLOW If RX FIFO is empty, a new read command from CPU or DMA will trigger this bit to high state.  RX_FIFO_OVERFLOW If RX FIFO is full (the data number is eight), a new write will trigger this bit to high state.  RX_FIFO_OVERF_THLD If the data number in the RX FIFO is larger than the register (RFIFO_THLD), this bit is asserted. © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 62 Maxscend Confidential MXD2656A1 Datasheet 5.11.5 UART Registers Table 94 Instance Base Address Peripheral Instance Description 0x40011800 UART UART0 UART0 Registers 0x40011C00 UART UART1 UART1 Registers Table 95 Register Map Address Offset Name Description 0x00 UARTx_TFIFO_WR_DATA UARTx TX FIFO Write Register 0x04 UARTx_RFIFO_RD_DATA UARTx RX FIFO Read Register 0x08 UARTx_INT_STATUS UARTx Interrupt Status 0x0C UARTx_INT_EN UARTx Interrupt Enable 0x10 UARTx_INT_CLEAR UARTx Interrupt Flag Clear Register 0x14 UARTx_CONFIG UARTx Configuration Register 0x18 UARTx_DIVISOR UARTx Data Divisor 0x1C UARTx_FIFO_CNT UARTx FIFO Counter 0x20 UARTx_FIFO_CLR UARTx FIFO and Data Clear Table 96 UARTx_TFIFO_WR_DATA (UARTx_BASE_ADDR+0x00) Bit Field Name 7:0 UARTx _TFIFO_WR_DATA Reset RW 0x0 W Description DMA/CPU write UARTx transmit fifo data via this register Table 97 UARTx_RFIFO_RD_DATA (UARTx_BASE_ADDR+0x04) Bit Field Name 7:0 UARTx_RFIFO_RD_DATA Reset RW 0x0 R Description DMA/CPU read UARTx receive fifo data via this register Table 98 UARTx_INT_STATUS (UARTx_BASE_ADDR+0x08) Bit Field Name 10 UARTx_TX_FIFO_OVERFLOW Reset RW 0 R Description TX FIFO overflow 0: invalid 1: valid 9 UARTx_RX_FIFO_UNDERFLOW 0 R RX FIFO underflow 0: invalid 1: valid 8 UARTx_RX_FIFO_NOT_EMPTY 0 R RX FIFO not empty 0: invalid 1: valid 7 UARTx_RX_FIFO_OVERFLOW 0 R RX FIFO overflow © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 63 Maxscend Confidential MXD2656A1 Datasheet 0: invalid 1: valid 6 UARTx_RX_FIFO_OVER_THLD 0 R RX FIFO over threshold 0: invalid 1: valid 5 UARTx_TX_FIFO_EMPTY 0 R TX FIFO empty 0: invalid 1: valid 4 UARTx_TX_FIFO_UNDER_THLD 0 R TX FIFO under threshold 0: invalid 1: valid 3 UARTx_TIMEOUT 0 R RX timeout error. The time between two RX FIFO read/write exceeds timeout threshold (UARTx_TO_THLD) when RX FIFO is not empty. 0: invalid 1: valid 2 UARTx_RXD_LINE_BREAK 0 R RXD line break detected 0: invalid 1: valid 1 UARTx_RXD_PARITY_ERROR 0 R RXD parity error 0: invalid 1: valid 0 UARTx_RXD_STOP_ERROR 0 R RXD stop bit error 0: invalid 1: valid Table 99 UARTx_INT_MASK (UARTx_BASE_ADDR+0x0C) Bit Field Name 10 UARTx_TX_FIFO_OVERFLOW_MASK Reset RW Description 0 RW TX FIFO overflow interrupt enable 0: disable 1: enable 9 UARTx_RX_FIFO_UNDERFLOW_MASK 0 RW RX FIFO underflow interrupt enable 0: disable 1: enable 8 UARTx_RX_FIFO_NOT_EMPTY_MASK 0 RW RX FIFO not empty interrupt enable 0: disable 1: enable 7 UARTx_RX_FIFO_OVERFLOW_MASK 0 RW RX FIFO overflow interrupt enable 0: disable 1: enable 6 UARTx_RX_FIFO_OVER_THLD_MASK 0 RW RWX FIFO over threshold interrupt © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 64 Maxscend Confidential MXD2656A1 Datasheet enable 0: disable 1: enable 5 UARTx_TX_FIFO_EMPTY_MASK 0 RW TX FIFO empty interrupt enable 0: disable 1: enable 4 UARTx_TX_FIFO_UNDER_THLD_MASK 0 RW TX FIFO under threshold interrupt enable 0: disable 1: enable 3 UARTx_TIMEOUT_MASK 0 RW RX timeout error interrupt enable 0: disable 1: enable 2 UARTx_RXD_LINE_BREAK_MASK 0 RW RXD line break detected interrupt enable 0: disable 1: enable 1 UARTx_RXD_PARITY_ERROR_MASK 0 RW RXD parity error interrupt enable 0: disable 1: enable 0 UARTx_RXD_STOP_ERROR_MASK 0 RW RXD stop bit error interrupt enable 0: disable 1: enable Table 100 UARTx_INT_CLEAR (UARTx_BASE_ADDR+0x10) Bit Field Name 10 UARTx_TX_FIFO_OVERFLOW_CLEAR Reset RW 0 W Description TX FIFO overflow interrupt clear 0: invalid 1: valid 9 UARTx_RX_FIFO_UNDERFLOW_CLEAR 0 W RX FIFO underflow interrupt clear 0: invalid 1: valid 8 UARTx_RX_FIFO_NOT_EMPTY_CLEAR 0 W RX FIFO not empty interrupt clear 0: invalid 1: valid 7 UARTx_RX_FIFO_OVERFLOW_CLEAR 0 W RX FIFO overflow interrupt clear 0: invalid 1: valid 6 UARTx_RX_FIFO_OVER_THLD_CLEAR 0 W RX FIFO over threshold interrupt clear 0: invalid 1: valid 5 UARTx_TX_FIFO_EMPTY_CLEAR 0 W TX FIFO empty interrupt clear © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 65 Maxscend Confidential MXD2656A1 Datasheet 0: invalid 1: valid 4 UARTx_TX_FIFO_UNDER_THLD_CLEAR 0 W TX FIFO under threshold interrupt clear 0: invalid 1: valid 3 UARTx_TIMEOUT_CLEAR 0 W RX timeout error interrupt clear. 0: invalid 1: valid 2 UARTx_RXD_LINE_BREAK_CLEAR 0 W RXD line break detected interrupt clear 0: invalid 1: valid 1 UARTx_RXD_PARITY_ERROR_CLEAR 0 W RXD parity error interrupt clear 0: invalid 1: valid 0 UARTx_RXD_STOP_ERROR_CLEAR 0 W RXD stop bit error interrupt clear 0: invalid 1: valid Table 101 UARTx_CONFIG (UARTx_BASE_ADDR+0x14) Bit Field Name 30 UARTx_ERR_DISCARD Reset RW Description 0 RW discard event enable when error parity bit or error stop bit data received 0: disable 1: enable 29:26 UARTx_RTS_THLD 0x0 RW When the number of data in rx fifo is larger than RTS threshold then suspend 25 UARTx_FLOW_CTRL_EN 0 RW hardware flow control 0: disable 1: enable 24 UARTx_LB_SND 0 RW line break enable 0: disable 1: enable 23 UARTx_MSB 0 RW big-endian mode or little-endian mode selection 0: little-endian 1: big-endian 22:20 UARTx_PARITY_MODE 0x0 RW parity mode 0: parity odd 1: parity even 2: parity stick at 1 3: parity stick at 0 4~7: reserved © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 66 Maxscend Confidential MXD2656A1 Datasheet 19:18 UARTx_BYTE_SIZE 0x3 RW transmitted data size 0: 5 bit 1: 6 bit 2: 7 bit 3: 8 bit 17:16 UARTx_STOP_BIT 0x0 RW stop bit length 0: 1 bit 1: 1.5 bit 2~3: 2 bit 15:8 UARTx_TO_THLD 0xFF RW RX time out threshold unit is 1 symbol (byte) 7:4 UARTx_RFIFO_THLD 0x4 RW RX FIFO threshold When the data number in rx fifo arrived at RX threshold, interrupt is generated. 3:0 UARTx_TFIFO_THLD 0x4 RW TX FIFO threshold When the data number in tx fifo arrived at TX threshold, interrupt is generated. Table 102 UARTx_DIVISOR (UARTx_BASE_ADDR+0x18) Bit Field Name 25:16 UARTx_TRIG_INTV Reset RW Description 0x13 RW input RXD detected interval should be set (cap_intv+1)/7 15:0 UARTx_CAP_INTV 0x89 RW Baud rate setting Baud rate = 16MHz/(cap_intv+1) Table 103 UARTx_FIFO_CNT (UARTx_BASE_ADDR+0x1C) Bit Field Name Reset RW 7:4 3:0 Description UARTx_RFIFO_CNT 0x0 R rx fifo counter UARTx_TFIFO_CNT 0x0 R tx fifo counter Table 104 UARTx_FIFO_CLR (UARTx_BASE_ADDR+0x20) Bit Field Name 0 UARTx_FIFO_CLR Reset RW 0 W Description counter (rx and tx) and data (rx and tx) both cleared 0: invalid 1: clear © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 67 Maxscend Confidential MXD2656A1 Datasheet 5.12 SPI 5.12.1 Feature SPI is a serial parallel interface compatible with Motorola standard. The main features are: 1. Master and slave mode 2. Programmable TX only, RX only and TRX mode 3. Support CPU and DMA access 4. Programmable output frequency in master mode. Up to 8MHz clock for both master and slave mode 5. Programmable clock phase and polarity 6. Programmable data frame size from 8-bits, 16-bits, 32-bits and 64-bits. 7. 8 bytes transmit FIFOs, 8 bytes receive FIFOs 5.12.2 Function Description The SPI performs serial-to-parallel conversion on data received from a peripheral device on the MISO pin in master mode and on the MOSI pin in slave mode. The SPI performs parallel-to-serial conversion on data written by the CPU/DMA for transmission on the MOSI pin in master mode and on the MISO pin in slave mode. The SPI has a programmable bit-rate clock divider to generate the serial output clock signal on the SCLK pin. The transmission and reception paths have individual 8 bytes FIFO memories. FIFOs may be burst-loaded or emptied by the CPU/DMA. SCLK MOSI MISO CSN Master Slave Figure 15 SPI Interface Signals 5.12.2.1 Clock Mode (Phase and Polarity) The CPOL bit determines the polarity of the clock. - CPOL=0 means idle state is ‘0’, and each cycle consists of a pulse of 1. That is, the leading edge is a rising edge, and the trailing edge is a falling edge. - CPOL=1 means idle state is ‘1’, and each cycle consists of a pulse of 0. That is, the leading edge is a falling edge, and the trailing edge is a rising edge. The CPHA bit determines the timing of the data bit relative to the clock pulse. - For CPHA=0, the ‘out’ side changes the data on the trailing edge of the preceding clock cycle, while the ‘in’ side © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 68 Maxscend Confidential MXD2656A1 Datasheet captures the data on (or shortly after) the leading edge of the clock cycle. The outside holds the data valid until the trailing edge of the current clock cycle. For the first cycle, the first bit must be on the MOSI line before the leading clock edge. - For CPHA=1, the ‘out’ side changes the data on the leading edge of the current clock cycle, while the ‘in’ side captures the data on (or shortly after) the trailing edge of the clock cycle. The outside holds the data valid until the leading edge of the following clock cycle. For the last cycle, the slave holds the MISO line valid until slave select is deserted. CPHA = 0 CPOL = 0 CPOL = 1 send MISO MOSI capture CSN Figure 16 SPI Clock Mode Diagram (CPHA=0) CPHA = 1 CPOL = 0 CPOL = 1 send MISO MOSI capture CSN Figure 17 SPI Clock Mode Diagram (CPHA=1) 5.12.2.2 Clock Generation In master mode, the SCLK frequency is configurable. - SCLK = 8MHz / (1 + register: SPI_CLK_DIVISOR) In slave mode, the SCLK is from the external master, and the supported highest clock is 8MHz. © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 69 Maxscend Confidential MXD2656A1 Datasheet 5.12.2.3 TX Idle Data In master mode, when TX FIFO is empty and RX only mode, SPI transmits register value (TX_IDLE_DATA) to external slave. In slave mode, when TX FIFO is empty, SPI transmits register value (TX_IDLE_DATA) to external master. 5.12.3 Software Procedure 5.12.3.1 Receive Procedure 1. Empty the receive FIFO by set SPI_FIFO_CLR register. 2. Program GPIO to route SPI port signals on those GPIO (refer to GPIO registers). 3. Program the SPI_CONFIG register to RX/TRX mode. 4. Receive data a) If in the master and RX only mode, set SPI enable (RX_EN) and RX length (MRXO_LEN). b) If in the master and TRX mode, write the register (SPI_TX_FIFO). c) If in the slave mode, wait external master transmit data. 5.12.3.2 Transmit Procedure 1. Empty the transmit FIFO by set SPI_FIFO_CLR register. 2. Program GPIO to rout SPI port signals on those GPIO (refer to GPIO registers). 3. Program the SPI_CONFIG register to TX/TRX mode. 4. Transmit data a) If in the master mode, write the register (SPI_TX_FIFO). b) If in the slave mode, write the register (SPI_TX_FIFO) and wait for an external master’s SCLK. 5.12.4 Interrupt SPI interrupt table is shown below. Table 105 SPI Interrupt Interrupt Interrupt name Description 10 TX_FIFO_FULL Set during transmit if the register (TFIFO_CNT) is filled to 8 9 RX_FIFO_FULL Set during receive if the register (RFIFO_CNT) is filled to 8 8 TX_FIFO_OVERFLOW Set during transmit if the register (TFIFO_CNT) is filled to 8 and the Number DMA/CPU attempts to issue another data by writing to the register (TX_FIFO) © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 70 Maxscend Confidential MXD2656A1 Datasheet 7 6 TX_FIFO_UNDERFLOW Set during transmit if the register (TFIFO_CNT) is equal to 0 and the (only SPI slave mode) external SPI master send next frame completed RX_FIFO_UNDERFLOW Set if the DMA/CPU attempts to read the receive buffer when it is empty by reading from the register (RX_FIFO) 5 RX_FIFO_NOT_EMPTY Set during receive if the register (RFIFO_CNT) isn't equal to 0 4 RX_FIFO_OVERFLOW Set during receive if the register (RFIFO_CNT) is filled to 8 and the (only SPI slave mode) external SPI master send next frame completed Indicate when a DMA/CPU read register (RX_FIFO) operation is not completed in time 3 RX_FIFO_OVERF_THLD Set when the receive buffer reaches or goes above the register (RFIFO_THLD) 2 TX_FIFO_EMPTY Set during transmit if the register (TFIFO_CNT) is equal to 0 1 TX_FIFO_UNDER_THLD Set when the transmit buffer reaches or goes below the register (TFIFO_THLD) 0 RX_TIMEOUT In slave mode, set when the RX FIFO is not empty, and no further data is received over a programmable timeout period (TO_THLD in SPI_CONFIG register). 5.12.5 Registers Table 106 SPI Instance Base Address Peripheral Instance Description 0x40017000 SPI SPI Serial-Peripheral-Interface Table 107 SPI Register Map Address Offset Name Description 0x00 SPI_TX_FIFO DMA/CPU write SPI transmit FIFO data via this register 0x04 SPI_RX_FIFO DMA/CPU read SPI receive FIFO data via this register 0x08 SPI_INT_FLAG SPI interrupt flag 0x0C SPI_INT_EN SPI interrupt enable 0x10 SPI_INT_CLR SPI interrupt clear 0x14 SPI_CONFIG SPI configuration 0x18 SPI_DIVISOR SPI master mode clock divisor 0x1C SPI_FIFO_CNT SPO TX and RX FIFO counter 0x20 SPI_TX_IDLE SPI transmit idle data 0x24 SPI_EXTM_READ_LEN external master read FIFO counter 0x28 SPI_FIFO_CLR SPI 8x8 FIFO clear Table 108 SPI_TX_FIFO (SPI_BASE_ADDR +0x0) Bit Field Name Reset RW Description 7:0 SPI_TX_FIFO 0x0 W DMA/CPU write SPI transmit FIFO data via this register © 2018 Maxscend Microelectronics Company Limited. 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Maxscend Confidential 71 Maxscend Confidential MXD2656A1 Datasheet Table 109 SPI_RX_FIFO (SPI_BASE_ADDR +0x4) Bit Field Name Reset RW Description 7:0 SPI_RX_FIFO 0x0 R DMA/CPU read SPI receive FIFO data via this register Table 110 SPI_INT_FLAG (SPI_BASE_ADDR +0x8) Bit Field Name Reset RW Description 10 TX_FIFO_FULL 0 R See Interrupt 9 RX_FIFO_FULL 0 R See Interrupt 8 TX_FIFO_OVERFLOW 0 R See Interrupt 7 TX_FIFO_UNDERFLOW 0 R See Interrupt 6 RX_FIFO_UNDERFLOW 0 R See Interrupt 5 RX_FIFO_NOT_EMPTY 0 R See Interrupt 4 RX_FIFO_OVERFLOW 0 R See Interrupt 3 RX_FIFO_OVERF_THLD 0 R See Interrupt 2 TX_FIFO_EMPTY 0 R See Interrupt 1 TX_FIFO_UNDER_THLD 0 R See Interrupt 0 RX_TIMEOUT 0 R See Interrupt Table 111 SPI_INT_EN (SPI_BASE_ADDR +0xC) Bit Field Name Reset RW Description 10 TX_FIFO_FULL_EN 0 RW Interrupt enable register 0 : disable 1 : enable 9 RX_FIFO_FULL_EN 0 RW Interrupt enable register 0 : disable 1 : enable 8 TX_FIFO_OVERFLOW_EN 0 RW Interrupt enable register 0 : disable 1 : enable 7 TX_FIFO_UNDERFLOW_EN 0 RW Interrupt enable register 0 : disable 1 : enable 6 RX_FIFO_UNDERFLOW_EN 0 RW Interrupt enable register 0 : disable 1 : enable 5 RX_FIFO_NOT_EMPTY_EN 0 RW Interrupt enable register 0 : disable 1 : enable 4 RX_FIFO_OVERFLOW_EN 0 RW Interrupt enable register 0 : disable © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 72 Maxscend Confidential MXD2656A1 Datasheet 1 : enable 3 RX_FIFO_OVERF_THLD_EN 0 RW Interrupt enable register 0 : disable 1 : enable 2 TX_FIFO_EMPTY_EN 0 RW Interrupt enable register 0 : disable 1 : enable 1 TX_FIFO_UNDER_THLD_EN 0 RW Interrupt enable register 0 : disable 1 : enable 0 RX_TIMEOUT_EN 0 RW Interrupt enable register 0 : disable 1 : enable Table 112 SPI_INT_CLR (SPI_BASE_ADDR +0x10) Bit Field Name Reset RW Description 10 TX_FIFO_FULL_CLR 0 W Interrupt clear register 0 : invalid 1 : clear 9 RX_FIFO_FULL_CLR 0 W Interrupt clear register 0 : invalid 1 : clear 8 TX_FIFO_OVERFLOW_CLR 0 W Interrupt clear register 0 : invalid 1 : clear 7 TX_FIFO_UNDERFLOW_CLR 0 W Interrupt clear register 0 : invalid 1 : clear 6 RX_FIFO_UNDERFLOW_CLR 0 W Interrupt clear register 0 : invalid 1 : clear 5 RX_FIFO_NOT_EMPTY_CLR 0 W Interrupt clear register 0 : invalid 1 : clear 4 RX_FIFO_OVERFLOW_CLR 0 W Interrupt clear register 0 : invalid 1 : clear 3 RX_FIFO_OVERF_THLD_CLR 0 W Interrupt clear register 0 : invalid 1 : clear 2 TX_FIFO_EMPTY_CLR 0 W Interrupt clear register 0 : invalid © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 73 Maxscend Confidential MXD2656A1 Datasheet 1 : clear 1 TX_FIFO_UNDER_THLD_CLR 0 W Interrupt clear register 0 : invalid 1 : clear 0 RX_TIMEOUT_CLR 0 W Interrupt clear register 0 : invalid 1 : clear Table 113 SPI_CONFIG (SPI_BASE_ADDR +0x14) Bit Field Name Reset RW Description 31 RX_EN 0 RW SPI RX enable 0 : disable 1 : enable 30 MASTE_SLAVE 0 RW Master or slave mode selection 0 : slave mode 1 : master mode 29 CPOL 0 RW See Clock Mode 28 CPHA 0 RW See Clock Mode 27:20 MRXO_LEN 0 RW SPI receive data length when master mode (when master is set to '1') and RX only mode (when TRX_MODE[1:0] is set to '2') Unit : 1 CSN frame length 19:18 SIZE 0 RW SPI master mode CSN frame size 0 : 8bit 1 : 16bit 2 : 32bit 3 : 64bit 17:16 TRX_MODE 0x2 RW SPI TRX mode: 0 : transmit enable, receive enable (full duplex mode) 1 : transmit enable, receive disable (TX only mode) 2 : transmit disable, receive enable (TX only mode) 3 : transmit & receive disable 15:8 TO_THLD 0xFF RW SPI RX time out threshold Unit : 1 byte 7:4 RFIFO_THLD 0x4 RW receive FIFO threshold 3:0 TFIFO_THLD 0x4 RW transmit FIFO threshold Table 114 SPI_CONFIG (SPI_BASE_ADDR +0x18) Bit Field Name Reset RW Description 7:0 SPI_CLK_DIVISOR 0 RW See Clock Generation Table 115 SPI_FIFO_CNT (SPI_BASE_ADDR +0x1c) Bit Field Name Reset RW Description © 2018 Maxscend Microelectronics Company Limited. All Rights Reserved. Maxscend Confidential 74 Maxscend Confidential MXD2656A1 Datasheet 7:4 RFIFO_CNT 0 R receive FIFO counter 3:0 TFIFO_CNT 0 R transmit FIFO counter Table 116 SPI_TX_IDLE (SPI_BASE_ADDR +0x20) Bit Field Name Reset RW Description 7:0 TX_IDLE_DATA 0 RW See TX Idle Data Table 117 SPI_EXTM_READ_LEN (SPI_BASE_ADDR +0x24) Bit Field Name Reset RW Description 8 SPI_EXTM_READ_LEN_EN 0 RW SPI in slave mode. if received byte (in the current frame) matches SPI_EXTM_READ_LEN_CMD, SPI transmits one byte data (4bits TFIFO_CNT, 4bits RFIFO_CNT) for next frame to external master. 0 : disable 1 : enable 7:0 SPI_EXTM_READ_LEN_CMD 0 RW See SPI_EXTM_READ_LEN_EN Table 118 SPI_FIFO_CLR (SPI_BASE_ADDR +0x28) Bit Field Name Reset RW Description 0 SPI_FIFO_CLR 0 W SPI 8x8 TRX FIFO clear 0 : invalid 1 : clear 5.13 I2C The I2C is a programmable control bus that provides support for the communications link between Integrated Circuits in a system. 5.13.1 Feature 1. Two-wire I2C serial interface consists of a serial data line (SDA) and a serial clock (SCL) 2. Support both master and slave modes 3. Standard mode (0 to 100 KHz) and Fast mode (