TSD840MD

TSD840MD TSD840MD 500V N-Channel MOSFET General Description Features This Power MOSFET is produced using Truesemi‘s advanced planar stripe DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switched mode power supplies, active power factor correction based on half bridge topology. • 8.0A,500V,Max.RDS(on)=0.95 Ω @ VGS =10V • 100% avalanche tested • High ruggedness • Fast switching • Improved dv/dt capability D G S TO-252 Absolute Maximum Ratings Symbol TJ=25℃ unless otherwise specified Parameter Value Units VDSS Drain-Source Voltage 500 V VGS Gate-Source Voltage ±30 V TC = 25℃ 8.0* A TC = 100℃ 5.0* A ID Drain Current IDM Pulsed Drain Current (Note 1) 32 A EAS Single Pulsed Avalanche Energy (Note 2) 280 mJ EAR Repetitive Avalanche Energy (Note 1) 6.3 mJ dv/dt Peak Diode Recovery dv/dt (Note 3) PD TJ, TSTG TL Power Dissipation (TC = 25℃) -Derate above 25℃ Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8” from case for 5 seconds 4.5 V/ns 100 W 0.36 W/℃ -55 to +150 ℃ 300 ℃ * Drain current limited by maximum junction temperature. Thermal Resistance Characteristics Symbol Parameter Value Units RθJC Thermal Resistance,Junction-to-Case 0.9 ℃/W RθCS Thermal Resistance,Case-to-Sink Typ. -- ℃/W RθJA Thermal Resistance,Junction-to-Ambient 62.5 ℃/W © 2018 Truesemi Semiconductor Corporation Ver.B1 www.truesemi.com Symbol unless otherwise specified Parameter Test Conditions Min Typ Max Units Gate Threshold Voltage VDS = VGS, ID = 250 uA㎂ 2.0 -- 4.0 V Static Drain-Source On-Resistance VGS = 10 V, ID = 4.5 A -- 0.88 0.95 Ω 500 -- -- V ID = 250 uA, Referenced to 25℃ -- -- -- V/℃ VDS = 500 V, VGS = 0 V -- -- 1 uA VDS = 400 V, TJ = 125℃ -- -- 10 uA On Characteristics VGS(th) RDS(ON) Off Characteristics BVDSS Drain-Source Breakdown Voltage △BVDSS Breakdown Voltage Temperature / △TJ Coefficient VGS = 0 V, ID = 250 uA㎂ IDSS Zero Gate Voltage Drain Current IGSSF Gate-Body Leakage Current,Forward VGS = 30 V, VDS = 0 V -- -- 100 nA㎁ IGSSR Gate-Body Leakage Current,Reverse VGS =- 30 V, VDS = 0 V -- -- -100 nA㎁ Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz -- 1400 -- pF㎊ -- 210 -- pF㎊ -- 80 -- pF -- 15 -- ns -- 62 -- ns㎱ -- 93 -- ns㎱ -- 48 -- ns㎱ -- 26 -- nC -- 4 -- nC -- 13 -- nC Switching Characteristics td(on) Turn-On Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd VDS = 250 V, ID = 8.0A, RG = 25 Ω (Note 4,5) VDS = 400 V, ID = 8.0A, VGS = 10 V (Note 4,5) Gate-Drain Charge Source-Drain Diode Maximum Ratings and Characteristics IS Continuous Source-Drain Diode Forward Current -- -- 8.0 ISM Pulsed Source-Drain Diode Forward Current -- -- 24.0 VSD Source-Drain Diode Forward Voltage IS = 3.0 A, VGS = 0 V -- -- 1.4 trr Reverse Recovery Time IS =8.0A, VGS = 0 V -- 340 -- ns㎱ Qrr Reverse Recovery Charge diF/dt = 100 A/μs -- 3 -- uC (Note 4) A V NOTES: 1. Repetitive Rating: Pulse width limited by maximum junction temperature 2. L=5mH, IAS=10.6A, VDD=50V, VG=10V,Starting TJ=25 ℃ 3. ISD≤8.0A, di/dt ≤ 200A/us, VDD ≤ BVDSS, Starting TJ = 25 ℃ 4. Pulse Test: Pulse width ≤ 300us, Duty Cycle ≤ 2% 5. Essentially Independent of Operating Temperature Typical Characteristics © 2018 Truesemi Semiconductor Corporation Ver.B1 www.truesemi.com TSD840MD Electrical Characteristics TJ=25 ℃ Fig. 1 Typical Output Characteristics Fig. 2 Typical Output Characteristics Fig.3 On-Resistance Variation with Drain Current and Gate Voltage Fig. 4 Body Diode Forward Voltage Variation with Source Current and Temperature Fig. 5 Typical Capacitance Characteristics © 2018 Truesemi Semiconductor Corporation Fig. 6 Typical Total Gate Charge Characteristics Ver.B1 www.truesemi.com TSD840MD Electrical Characteristics Curves Fig. 8 On-Resistance Variation vs. Temperature Fig. 9 Maximum Drain Current vs. Case Temperature Fig. 10 Maximum Safe Operating Area Fig. 11 Transient Thermal Impedance © 2018 Truesemi Semiconductor Corporation Ver.B1 www.truesemi.com TSD840MD Fig. 7 Breakdown Voltage Variation vs. Temperature TSD840MD Fig. 12 Gate Charge Test Circuit & Waveform Fig. 13 Resistive Switching Test Circuit & Waveform Fig. 14 EAS Test Circuit & Waveform © 2018 Truesemi Semiconductor Corporation Ver.B1 www.truesemi.com TSD840MD Fig. 15 Diode Reverse Recovery Time Test Circuit & Waveform © 2018 Truesemi Semiconductor Corporation Ver.B1 www.truesemi.com