A81X05F5001AQ5A/Q

A8105 2.4GHz FSK/GFSK SoC Document Title A8105 Data Sheet, 2.4GHz FSK/GFSK SOC Revision History Issue Date Remark 0.0 Initial issue. June, 2012 Objective 0.1 Add RF register Sep, 2012 Objective 0.2 Modify RF register Sep, 2013 0.3 0.4 0.5 0.6 Remove RCADC Revise Order information Add 32Kbytes Flash version and related information. Add die form and QFN48L in order information. Add reset timing of stable power and RESETN pin Add P2 registers for extra 4 GPIO for 32KB flash version Oct,, 2013 Jan., 2014 Apr., 2014 Sep., 2014 L History EN TI A Preliminary Preliminary Preliminary Preliminary Preliminary A M IC C O M C O N FI D Rev. No. Important Notice: AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such applications is understood to be fully at the risk of the customer. Sep., 2014, Version 0.6 (Preliminary) 1 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Table of Contents A M IC C O M C O N FI D EN TI A L 1. General Description ................................................................................................................................................................ 1 2. Typical Applications ................................................................................................................................................................ 1 3. Feature ................................................................................................................................................................................... 1 4. Pin Configurations .................................................................................................................................................................. 3 5. Pin Description (I: input; O: output, I/O: input or output) ......................................................................................................... 5 6. Chip Block Diagram ................................................................................................................................................................ 7 7. Absolute Maximum Ratings .................................................................................................................................................... 8 8. Electrical Specification ............................................................................................................................................................ 9 9. SFR & RFR(Radio Frequency Register) ............................................................................................................................... 11 9.1 SFR Overview ..................................................................................................................................................................... 11 9.2 RFR Overview .................................................................................................................................................................... 13 9.2.1 Mode Register (Address: 0x800h) ..................................................................................................................... 17 9.2.2 Mode Control Register 1 (Address: 0x801h)...................................................................................................... 17 9.2.3 Mode Control Register 2 (Address: 0x802h)...................................................................................................... 18 9.2.4 Calibration Control Register (Address: 0x803h) ................................................................................................ 18 9.2.5 FIFO Register I (Address: 0x804h) .................................................................................................................... 19 9.2.6 FIFO Register II (Address: 0x805h) ................................................................................................................... 19 9.2.7 RC OSC Register I (Address: 0x806h) .............................................................................................................. 19 9.2.8 RC OSC Register II (Address: 0x807h) ............................................................................................................. 19 9.2.9 RC OSC Register III (Address: 0x808h) ............................................................................................................ 19 9.2.10 RC OSC Register IV (Address: 0x809h) .......................................................................................................... 20 9.2.11 RC OSC Register V (Address: 0x80Ah)........................................................................................................... 20 9.2.12 RC OSC Register VI (Address: 0x80Bh) ......................................................................................................... 20 9.2.13 RC OSC Register VII (Address: 0x80Ch)...................................................................................................... 21 9.2.14 RC OSC Register VIII (Address: 0x80Dh) ..................................................................................................... 21 9.2.15 CKO Pin Control Register (Address: 0x80Eh) ................................................................................................. 21 9.2.16 GIO1 Pin Control Register I (Address: 0x80Fh) ............................................................................................... 21 9.2.17 GIO2 Pin Control Register II (Address: 0x810h) .............................................................................................. 22 9.2.18 Clock Register (Address: 0x811h) ................................................................................................................... 23 9.2.19 Data Rate Register (Address: 0x812h) ............................................................................................................ 23 9.2.20 PLL Register I (Address: 0x813h) .................................................................................................................... 23 9.2.21 PLL Register II (Address: 0x814h) ................................................................................................................... 23 9.2.22 PLL Register III (Address: 0x815h) .................................................................................................................. 24 9.2.23 PLL Register IV (Address: 0x816h) ................................................................................................................. 24 9.2.24 PLL Register V (Address: 0x817h) .................................................................................................................. 24 9.2.25 TX Register I (Address: 0x818h)...................................................................................................................... 24 9.2.26 TX Register II (Address: 0x819h)..................................................................................................................... 25 9.2.27 Delay Register I (Address: 0x81Ah) ................................................................................................................ 25 9.2.28 Delay Register II (Address: 0x81Bh) ............................................................................................................... 25 9.2.29 RX Register (Address: 0x81Ch) ...................................................................................................................... 25 9.2.30 RX Gain Register I (Address: 0x81Dh) ............................................................................................................ 26 9.2.31 RX Gain Register II (Address: 0x81Eh) ........................................................................................................... 26 9.2.32 RX Gain Register III (Address: 0x81Fh) .......................................................................................................... 27 9.2.33 RX Gain Register IV (Address: 0x820h) .......................................................................................................... 27 9.2.34 RSSI Threshold Register (Address: 0x821h) ................................................................................................... 27 9.2.35 ADC Control Register (Address: 0x822h) ........................................................................................................ 28 9.2.36 Code Register I (Address: 0x823h) ................................................................................................................. 28 9.2.37 Code Register II (Address: 0x824h) ................................................................................................................ 28 9.2.38 Code Register III (Address: 0x825h)................................................................................................................ 29 9.2.39 IF Calibration Register I (Address: 0x826h) ..................................................................................................... 29 9.2.40 IF Calibration Register II (Address: 0x827h) .................................................................................................... 29 9.2.41 VCO current Calibration Register (Address: 0x828h) ...................................................................................... 30 9.2.42 VCO Single band Calibration Register I (Address: 0x829h) ............................................................................ 30 9.2.43 VCO Single band Calibration Register II (Address: 0x82Ah) ........................................................................... 30 9.2.44 Battery detect Register (Address: 0x82Bh)...................................................................................................... 31 9.2.45 TX test Register (Address: 0x82Ch) ................................................................................................................ 31 9.2.46 Rx DEM test Register I (Address: 0x82Dh) ..................................................................................................... 31 9.2.47 Rx DEM test Register II (Address: 0x82Eh) ..................................................................................................... 32 9.2.48 Charge Pump Current Register (Address: 0x82Fh) ......................................................................................... 32 9.2.49 Crystal test Register (Address: 0x830h) .......................................................................................................... 32 9.2.50 PLL test Register (Address: 0x831h) ............................................................................................................... 32 Sep., 2014, Version 0.6 (Preliminary) 2 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC A M IC C O M C O N FI D EN TI A L 9.2.51 VCO test Register I (Address: 0x832h)............................................................................................................ 33 9.2.52 VCO test Register II (Address: 0x833h)........................................................................................................... 33 9.2.53 IFAT Register (Address: 0x834h) ..................................................................................................................... 33 9.2.54 RFT Test Register I (Address: 0x835h)............................................................................................................ 33 9.2.55 RFT Test Register II (Address: 0x836h)........................................................................................................... 34 9.2.56 RFT Test Register III (Address: 0x837h).......................................................................................................... 34 9.2.57 RFT Test Register IV (Address: 0x838h) ......................................................................................................... 34 9.2.58 RFT Test Register V (Address: 0x839h) .......................................................................................................... 34 9.2.59 Channel Index Register (Address: 0x83Ah)..................................................................................................... 34 9.2.60 CRC Register 1 (Address: 0x83Bh) ................................................................................................................. 35 9.2.61 CRC Register 2 (Address: 0x83Ch) ................................................................................................................. 35 9.2.62 CRC Register 3 (Address: 0x83Dh) ................................................................................................................. 35 9.2.63 CRC Register 4 (Address: 0x83Eh) ................................................................................................................. 35 9.2.64 CRC Register 5 (Address: 0x83Fh) ................................................................................................................. 35 9.2.65 CRC Register 6 (Address: 0x840h) ................................................................................................................. 35 9.2.66 VCO Single band Calibration Register I (Address: 0x841h) ............................................................................ 35 9.2.67 VCO deviation Calibration Register I (Address: 0x842h) ................................................................................. 36 9.2.68 VCO deviation Calibration Register II (Address: 0x843h) ................................................................................ 36 9.2.69 VCO deviation Calibration Register III (Address: 0x844h) ............................................................................... 36 9.2.70 ADC Control Register (Address: 0x845h) ........................................................................................................ 36 9.2.71 WOT Register (Address: 0x846h) .................................................................................................................... 37 9.2.72 Channel Group Register I (Address: 0x847h) .................................................................................................. 37 9.2.73 Channel Group Register II (Address: 0x848h) ................................................................................................. 37 9.2.74 Charge Pump Current Register II (Address: 0x849h) ...................................................................................... 37 9.2.75 VCO Modulation Delay Register (Address: 0x84Ah) ....................................................................................... 38 9.2.76 Internal Capacitance Register (Address: 0x84Bh) ........................................................................................... 38 9.2.77 RX Detection Register (Address: 0x84Ch) ...................................................................................................... 38 9.2.78 BLE Header Register 0 (Address: 0x84Dh) ..................................................................................................... 38 9.2.79 BLE Header Register 1 (Address: 0x84Eh) ..................................................................................................... 38 9.2.80 ID Register 0 (Address: 0x84Fh) ..................................................................................................................... 39 9.2.81 ID Register 1 (Address: 0x850h) ..................................................................................................................... 39 9.2.82 ID Register 2 (Address: 0x851h) ..................................................................................................................... 39 9.2.83 ID Register 3 (Address: 0x852h) ..................................................................................................................... 39 9.2.84 DID Register 0 (Address: 0x853h) ................................................................................................................... 39 9.2.85 DID Register 1 (Address: 0x854h) ................................................................................................................... 39 9.2.86 DID Register 2 (Address: 0x855h) ................................................................................................................... 39 9.2.87 DID Register 3 (Address: 0x856h) ................................................................................................................... 40 9.2.88 EXT Register 1 (Address: 0x857h) .................................................................................................................. 40 9.2.89 EXT Register 2 (Address: 0x858h) .................................................................................................................. 40 9.2.90 EXT Register 3 (Address: 0x859h) .................................................................................................................. 40 9.2.91 ADC Control Register (Address: 0x85Ah) ........................................................................................................ 40 9.2.92 ADC Value Register 1 (Address: 0x85Bh) ....................................................................................................... 41 9.2.93 ADC Value Register 2 (Address: 0x85Ch) ....................................................................................................... 41 9.2.94 ADC Value Register 3 (Address: 0x85Dh) ....................................................................................................... 41 9.2.95 Timer Interval Register 1 (Address: 0x85Eh) ................................................................................................... 41 9.2.96 Timer Interval Register 2 (Address: 0x85Fh) ................................................................................................... 42 9.2.97 Timer Wake On Radio Register 0 (Address: 0x860h) ...................................................................................... 42 9.2.98 Timer Wake On Radio Register 1 (Address: 0x861h) ...................................................................................... 42 9.2.99 Timer Control Register (Address: 0x862h)....................................................................................................... 42 9.2.100 Power Control Register 0 (Address: 0x863h) ................................................................................................ 43 9.2.101 Power Control Register 1 (Address: 0x864h) ................................................................................................ 43 9.2.102 Power Control Register 2 (Address: 0x865h) ................................................................................................ 43 9.2.103 Power Control Register 3 (Address: 0x866h) ................................................................................................ 43 9.2.104 Power Control Register 4 (Address: 0x867h) ................................................................................................ 43 9.2.105 DC_SHIFT(Address: 0x868h) ........................................................................................................................ 43 9.2.106 TX_5DLY(Address: 0x869h) .......................................................................................................................... 44 9.2.107 ACKRT (Address: 0x87Ch) ............................................................................................................................ 44 10.SOC Architectural Overview ................................................................................................................................................ 45 10.1 Pipeline 8051 CPU............................................................................................................................................................ 45 10.2 Memory Organization........................................................................................................................................................ 45 10.2.1 Program memory ............................................................................................................................................. 45 10.2.2 Data memory ................................................................................................................................................... 45 10.2.3 General Purpose Registers ............................................................................................................................. 46 Sep., 2014, Version 0.6 (Preliminary) 3 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC A M IC C O M C O N FI D EN TI A L 10.2.4 Bit Addressable Locations ............................................................................................................................... 46 10.2.5 Special Function Registers .............................................................................................................................. 46 10.2.6 Stack ................................................................................................................................................................ 46 10.2.7 Data Pointer Register ...................................................................................................................................... 46 10.2.8 RF Registers and RF FIFO .............................................................................................................................. 47 10.3 Instruction set ................................................................................................................................................................... 48 10.4 Interrupt handler................................................................................................................................................................ 51 10.4.1 FUNCTIONALITY ............................................................................................................................................ 51 10.5 Reset source ..................................................................................................................................................................... 54 10.6 Clock source ..................................................................................................................................................................... 56 11. I/O Ports .............................................................................................................................................................................. 58 11.1 FUNCTIONALITY .............................................................................................................................................................. 58 11.2 Key interrupt ...................................................................................................................................................................... 61 12 Timer0,1 and Timer2 ............................................................................................................................................................ 63 12.1 Timer 0 & 1 PINS DESCRIPTION ..................................................................................................................................... 63 12.2 Timer 0 & 1 FUNCTIONALITY .......................................................................................................................................... 63 12.2.1 OVERVIEW ..................................................................................................................................................... 63 12.2.2 Timer 0 & 1 Registers ...................................................................................................................................... 63 12.2.3 Timer 0 – Mode 0 ............................................................................................................................................. 64 12.2.4 Timer 0 – Mode 1 ............................................................................................................................................. 65 12.2.5 Timer 0 – Mode 2 ............................................................................................................................................. 65 12.2.6 Timer 0 – Mode 3 ............................................................................................................................................. 66 12.2.7 Timer 1 – Mode 0 ............................................................................................................................................. 66 12.2.8 Timer 1 – Mode 1 ............................................................................................................................................. 66 12.2.9 Timer 1 – Mode 2 ............................................................................................................................................. 67 12.2.10 Timer 1 – Mode 3 ........................................................................................................................................... 67 12.3 Timer2 PINS DESCRIPTION ............................................................................................................................................ 67 12.4 Timer2 FUNCTIONALITY ................................................................................................................................................. 67 12.4.1 OVERVIEW ..................................................................................................................................................... 67 12.4.2 Timer 2 Registers ............................................................................................................................................ 68 13. UART .................................................................................................................................................................................. 71 13.1 UART PINS DESCRIPTION ............................................................................................................................................. 71 13.2 FUNCTIONALITY ............................................................................................................................................................. 71 13.3 OPERATING MODES ....................................................................................................................................................... 73 13.3.1 UART MODE 0, SYNCHRONOUS .................................................................................................................. 73 13.3.2 UART MODE 1, 8-BIT UART, VARIABLE BAUD RATE, TIMER CLOCK SOURCE ........................................ 73 13.3.3 UART MODE 2, 9‐BIT UART, FIXED BAUD RATE ......................................................................................... 73 13.3.4 UART MODE 3, 9‐BIT UART, VARIABLE BAUD RATE, TIMER CLOCK SOURCE ........................................ 73 14. IIC interface ........................................................................................................................................................................ 74 2 14.1 Master mode I C ............................................................................................................................................................... 74 2 14.1.1 I C REGISTERS .............................................................................................................................................. 74 14.2.4 I2C MASTER MODULE AVAILABLE SPEED MODES .................................................................................... 77 14.2.5 I2C MASTER MODULE AVAILABLE COMMAND SEQUENCES .................................................................... 78 14.3 I2C MASTER MODULE INTERRUPT GENERATION ...................................................................................................... 85 2 14.5 Slave mode I C ................................................................................................................................................................. 85 14.5.1 I2C MODULE INTERNAL REGISTERS .......................................................................................................... 85 14.7 AVAILABLE I2C MODULE TRANSMISSION MODES ...................................................................................................... 87 2 14.7.1 I C module SINGLE RECEIVE ........................................................................................................................ 87 2 14.7.2 I C module SINGLE SEND .............................................................................................................................. 87 2 14.7.3 I C module BURST RECEIVE ......................................................................................................................... 87 2 14.7.4 I C module BURST SEND ............................................................................................................................... 88 2 14.7.5 AVAILABLE I C module COMMAND SEQUENCES FLOWCHART................................................................. 88 14.8 I2C MODULE INTERRUPT GENERATION ...................................................................................................................... 89 15. SPI interface ....................................................................................................................................................................... 90 15.1 KEY FEATURES ............................................................................................................................................................... 90 15.2 SPI PINS DESCRIPTION ................................................................................................................................................. 91 15.3 SPI HARDWARE DESCRIPTION ..................................................................................................................................... 91 15.3.1 BLOCK DIAGRAM ........................................................................................................................................... 91 15.3.2 INTERNAL REGISTERS ................................................................................................................................. 92 15.4 MASTER OPERATIONS ................................................................................................................................................... 93 15.4.1 MASTER MODE ERRORS .............................................................................................................................. 94 15.5 SLAVE OPERATIONS ...................................................................................................................................................... 95 15.5.1 SLAVE MODE ERRORS ................................................................................................................................. 95 Sep., 2014, Version 0.6 (Preliminary) 4 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC A M IC C O M C O N FI D EN TI A L 15.6 CLOCK CONTROL LOGIC ............................................................................................................................................... 96 15.6.1 SPI CLOCK PHASE AND POLARITY CONTROLS......................................................................................... 96 15.6.2 SPI MODULE TRANSFER FORMATS ............................................................................................................ 96 15.6.3 CPHA EQUALS ZERO TRANSFER FORMAT ................................................................................................ 96 15.6.4 CPHA EQUALS ONE TRANSFER FORMAT................................................................................................... 96 15.7 SPI DATA TRANSFER ...................................................................................................................................................... 97 15.7.1 TRANSFER BEGINNING PERIOD ( INITIATION DELAY ) ............................................................................. 97 15.7.2 TRANSFER ENDING PERIOD ........................................................................................................................ 97 15.8 TIMING DIAGRAMS ......................................................................................................................................................... 97 15.8.1 MASTER TRANSMISSION ............................................................................................................................. 97 15.8.2 SLAVE TRANSMISSION ................................................................................................................................. 98 15.9 SPI MODULE INTERRUPT GENERATION ...................................................................................................................... 98 16. PWM ................................................................................................................................................................................. 100 16.1 PWM FUNCTIONALITY .................................................................................................................................................. 100 16.1.1 PWM Registers .............................................................................................................................................. 100 17. Watchdog Timer ................................................................................................................................................................ 102 17.1 Watchdog timer overview ................................................................................................................................. 102 17.2 Watchdog interrupt ........................................................................................................................................... 102 17.3 Watchdog Timer reset....................................................................................................................................... 103 17.4 SIMPLE TIMER ................................................................................................................................................ 103 17.5 SYSTEM MONITOR ......................................................................................................................................... 103 17.6 WATCHDOG RELATED REGISTERS .............................................................................................................. 103 17.7 TIMED ACCESS REGISTERS ......................................................................................................................... 104 18. ADC (Analog to Digital Converter) .................................................................................................................................... 106 18.1 8-bits ADC ....................................................................................................................................................................... 106 18.1.1 RSSI Measurement ....................................................................................................................................... 106 18.1.2 Carrier Detect ................................................................................................................................................ 108 18.2 12-bits SAR ADC .............................................................................................................................................. 108 19. Battery Detect ................................................................................................................................................................... 110 20 Power Management........................................................................................................................................................... 111 21 A8105 RF ........................................................................................................................................................................... 113 21.1 Mode Control Register 1 (Address: 0x801h)..................................................................................................... 113 21.1.1 Strobe Command - Sleep Mode .................................................................................................................... 113 21.1.2 Strobe Command - Idle Mode ........................................................................................................................ 113 21.1.3 Strobe Command - Standby Mode ................................................................................................................. 113 21.1.4 Strobe Command - PLL Mode ....................................................................................................................... 113 21.1.5 Strobe Command - RX Mode ......................................................................................................................... 114 21.1.6 Strobe Command - TX Mode ......................................................................................................................... 114 21.2 RF Reset Command ....................................................................................................................................................... 114 21.3 FIFO Accessing Command ............................................................................................................................................. 114 21.4 Packet Format of FIFO mode ......................................................................................................................................... 114 21.5 Transceiver Frequency ................................................................................................................................................... 115 21.5.1 RF Clock ...................................................................................................................................................................... 115 21.5.2 LO Frequency Setting .................................................................................................................................................. 116 21.5.2.1 How to set FLO_BASE..................................................................................................................................... 116 21.5.2.2 How to set FLO = FLO_BASE + FOFFSET............................................................................................................ 117 21.6 State machine ................................................................................................................................................................. 117 21.6.1 Key states ...................................................................................................................................................... 117 21.6.2 FIFO mode .................................................................................................................................................... 118 22. Encryption and Autherfication ........................................................................................................................................... 120 22.1 AES .................................................................................................................................................................. 120 22.1.1 AddRoundKey................................................................................................................................................ 120 22.1.2 SubBytes ....................................................................................................................................................... 120 22.1.3 ShiftRows ...................................................................................................................................................... 120 22.1.3 MixColumns ................................................................................................................................................... 120 22.2 CCM ................................................................................................................................................................. 120 23. Flash memory controller ................................................................................................................................................... 122 24 In Circuit Emulator (ICE) .................................................................................................................................................... 124 24.1 PIN define ....................................................................................................................................................................... 124 24.2 ICE Key feature............................................................................................................................................................... 125 25. Application circuit .............................................................................................................................................................. 126 26. Abbreviations .................................................................................................................................................................... 127 27. Ordering Information ......................................................................................................................................................... 128 Sep., 2014, Version 0.6 (Preliminary) 5 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC A M IC C O M C O N FI D EN TI A L 28. Package Information ......................................................................................................................................................... 129 29. Top Marking Information ................................................................................................................................................... 131 30. Reflow Profile.................................................................................................................................................................... 134 31. Tape Reel Information ....................................................................................................................................................... 135 32. Product Status .................................................................................................................................................................. 136 Sep., 2014, Version 0.6 (Preliminary) 6 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 1. General Description L A8105 is a high performance and low cost 2.4GHz FSK/GFSK system-on-chip (SOC) wireless transceiver. With on chip fraction-N synthesizer, it can support the application of data rate from 5Kbps to 2Mbps and frequency hopping system and it can support peripheral mode of Bluetooth Low Energy. It is a Bluetooth smart device. This device integrates high speed pipeline 8051 MCU, 32/16KBytes In-system programmable flash memory, 2KB SRAM, various powerful functions and excellent performance of a leading 2.4GHz FSK/GFSK RF transceiver. It can be operated with wide voltage from 2.0V ~ 3.6V. A8105 has various operating modes, making it highly suited for systems where ultra-low power consumption is required. Besides, A8105 has two flash memory sizes. One is 16KBytes (A8105F4) and the other is 32Kbytes (A8105F5) that supports AES128 engine and CCM. The device has two package sizes. A8105F4 and A8105F5 are QFN5X5 40 pin package and only A8105F5 has QFN5x5 48pin package.  Wireless toy and gaming  Helicopter and airplane radio controller  Bluetooth smart device 2400 ~ 2483.5 MHz ISM frequency hopping system Smart remote controller Home and building automation Wireless keyboard and mouse EN     TI A 2. Typical Applications 3. Feature FI D N C O M O C A M          Package size (QFN5 X5, 40 pins/ 48 pins). High performance pipeline complicated 8051 Operation clock: 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of crystal oscillator. 32/16KB Flash memory with copy protection, 2KB SARM 2 UART, I C, SPI serial communication Three 16/8-bit counter/timers Two Channel PWM Watchdog timer Sleep timer In-Circuit Debugger In-System programming/ In-Application programming 24/ 28 GPIO(28 I/O only in QFN48) RX current consumption with MCU in operation mode :18mA TX current consumption with MCU in operation mode (18.5mA @ 0dBm, 21mA @ 6 dBm output power). Deep sleep current (0.8 uA) Low sleep current (3 uA) Frequency band: 2400 – 2483MHz. FSK and GFSK modulation High sensitivity:  -96dBm at 500Kbps data rate  -92dBm at 1Mbps data rate  -90dBm at 2Mbps data rate Programmable data rate 4K ~ 2Mbps. Fast settling time synthesizer for frequency hopping system. Built-in thermal sensor for monitoring relative temperature. Built-in one channel 8-bits ADC for external analog voltage (0V ~ 1.2V). Built-in eight channels 12-bits ADC for general purpose analog input (0V ~ 1.8 V). Built-in Low Battery Detector. Support low cost crystal (8 /12 / 16 / 24MHz). Low cost BLE application Easy to use.  Change frequency channel by ONE register setting.  8-bits Digital RSSI for clear channel indication.  Auto RSSI measurement.  Auto WOR (wake up when receive RX packet).  Auto WOT (wake up to transmit TX packet).  Auto Calibrations.  Auto IF function.  Auto Frequency Compensation.  Auto CRC Check.  Auto FEC by (7, 4) Hamming code (1 bit error correction / code word).  Data Whitening for encryption and decryption. IC                    Sep., 2014, Version 0.6 (Preliminary) 1 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Separated 64 bytes RX and TX FIFO A M IC C O M C O N FI D EN TI A L  Sep., 2014, Version 0.6 (Preliminary) 2 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC VDD_S 5 VDD_D 6 BP_BG 7 VDD_R 8 VDD_A 9 P2.1 P3.2 P3.1 P3.0 P1.7 42 41 40 39 38 L P2.2 43 P1.6 34 P1.3 33 P1.2 32 P1.1 31 P1.0 30 P0.7 29 P0.6 28 P0.5 27 P0.4 26 P0.3 25 2.0 EN 4 P1.4 FI D RESETN 35 N 3 P1.5 C O GND 36 M 2 10 RFO 11 N.C. C O RFI IC P3.7 37 P2.3 44 P3.4 46 P3.3 P3.5 47 45 P3.6 1 TI A N.C. 48 4. Pin Configurations 18 19 20 21 22 23 24 XO VDD_PLL REGI P0.0 P0.1 P0.2 GND 17 16 CP XI 15 14 N.C. VDD_V 13 N.C. A M 12 Fig 4-1. A8105 QFN 5x5 48 pin Package Top View Sep., 2014, Version 0.6 (Preliminary) 3 AMICCOM Electronics Corporation A8105 P3.1 P3.0 P1.7 P1.6 P1.5 35 34 33 32 31 L P3.2 36 P3.4 38 P3.3 P3.5 39 37 P3.6 TI A EN 19 20 GND P1.4 29 P1.3 28 P1.2 27 P1.1 26 P1.0 25 P0.7 24 P0.6 23 P0.5 22 P0.4 21 P0.3 Sep., 2014, Version 0.6 (Preliminary) CP VDD_V A M IC C 11 P0.2 10 RFO 18 9 P0.1 RFI FI D 8 17 VDD_A P0.0 7 N VDD_R 16 6 REGI BP_BG 15 5 VDD_P VDD_D C O 4 14 VDD_S XO 3 M RESETN 13 2 XI GND 30 12 1 O P3.7 40 2.4GHz FSK/GFSK SoC Fig 4-2. A8105 QFN 5x5 40 pin Package Top View 4 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 5. Pin Description (I: input; O: output, I/O: input or output) Pin No. Symbol 1 NC 2 P3.7 3 NC 4 RESETN DI RESETN 5 VDD_S AO Voltage supply for SARM 6 VDD_D AO VDD_D 7 BP_BG AO BP_BG 8 VDD_R AO VDD_R 9 VDD_A AO VDD_A 10 RFI AI RFI 11 RFO AO RFO 12 NC 13 NC 14 NC 15 VDD_V AI VDD_VCO 16 CP AO 17 XI AI CP XI 18 XO AO XO 19 VDD_P AO VDD_PLL 20 REGI AI REGI 21 P0.0 DIO SPI_SCLK 22 P0.1 DIO SPI_MOSI 23 P0.2 DIO SPI_MISO 24 GND DIO GND 25 P2.0 DIO P2.0 26 P0.3 DIO SPI_SSEL 27 P0.4 DIO GPIO/ ICE mode P0.5 DIO I2C_SCL P0.6 DIO I2C_SDA Function Description TI A EN FI D N C O M O C 30 P0.7 DIO INT2 /GIO1 31 P1.0 DIO Timer2_T2 32 P1.1 DIO Timer2_T2EX 33 P1.2 DIO INT3 /GIO2 34 P1.3 DIO INT4/ CKO 35 P1.4 DIO TTAG_TTDIO 36 P1.5 DIO TTAG_TTCK 37 P1.6 DIO PWM0/ADC4 38 P1.7 DIO PWM1/ADC5 39 P3.0 DIO UART0_RX/ADC6 40 P3.1 DIO UART0_TX/ADC7 A L RTC_O No connection M 29 DIO/AI IC 28 I/O Sep., 2014, Version 0.6 (Preliminary) 5 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC DIO/AI P2.1 DIO INT0/ADC0 P2.1 43 P2.2 DIO P2.2 44 P2.3 DIO P2.3 45 P3.3 DIO/AI INT1/ADC1 46 P3.4 DIO/AI Timer0_T0/ADC2 47 P3.5 DIO/AI Timer1_T1/ADC3 48 P3.6 DIO/AI RTC_I L P3.2 42 TI A 41 Table 5-1 QFN5x5 48 Pin Symbol I/O 1 P3.7 DIO/AI Function Description EN Pin No. RTC_O No connection NC 3 RESETN DI RESETN 4 VDD_S AO Voltage supply for SARM 5 VDD_D AO VDD_D 6 BP_BG AO BP_BG 7 VDD_R AO VDD_R 8 VDD_A AO VDD_A 9 RFI AI RFI 10 RFO AO RFO 11 VDD_VCO AI VDD_VCO 12 CP AO 13 XI AI CP XI 14 XO AO XO 15 VDD_PLL 16 REGI 17 P0.0 DIO SPI_SCLK 18 P0.1 DIO SPI_MOSI P0.2 DIO SPI_MISO GND DIO GND 21 P0.3 DIO SPI_SSEL 22 P0.4 DIO GPIO/ ICE mode 23 P0.5 DIO I2C_SCL 24 P0.6 DIO I2C_SDA 25 P0.7 DIO INT2 /GIO1 26 P1.0 DIO Timer2_T2 27 P1.1 DIO Timer2_T2EX 28 P1.2 DIO INT3 /GIO2 29 P1.3 DIO INT4/ CKO 30 P1.4 DIO TTAG_TTDIO 31 P1.5 DIO TTAG_TTCK N C O M O AO VDD_PLL AI REGI C A M 20 IC 19 FI D 2 Sep., 2014, Version 0.6 (Preliminary) 6 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC P1.6 DIO PWM0/ADC4 33 P1.7 DIO PWM1/ADC5 34 P3.0 DIO UART0_RX/ADC6 35 P3.1 DIO UART0_TX/ADC7 36 P3.2 DIO/AI INT0/ADC0 37 P3.3 DIO/AI INT1/ADC1 38 P3.4 DIO/AI Timer0_T0/ADC2 39 P3.5 DIO/AI Timer1_T1/ADC3 40 P3.6 DIO/AI RTC_I TI A L 32 1 P3.7 Regulator UART 4 5 BP_BG 6 C ADC VDD_R 7 31 Battery Detect AES128 CCM* AFC I2C interface AGC P1.4 29 P1.3 28 P1.2 27 P1.1 26 P1.0 25 P0.7 24 P0.6 23 P0.5 22 P0.4 21 P0.3 P a c k e tT H aX n-F dI leF rO / R X - 17 18 19 20 GND 16 P0.2 15 P0.1 14 P0.0 13 REGI VDD_VCO 12 30 SPI interface XOSC CLK GEN Sigma-Delta Modulator Gaussian Filter 11 Radio Control VDD_PLL A FractionalN PLL XO 10 VCO XI RFO PA CP 9 M RFI LNA M O D E M 6 4 -b y te F s IF O CRC Filtering IC VDD_A 8 PWM 0/1 interface Timer 0/1/2 interface 2KB SRAM M VDD_D 32 32/16KB Flash Memory 8051 Core O VDD_S 33 N Debug ICE C O RESETN 3 RTC CLK GEN 34 12bit SAR ADC 2 NC 35 P1.5 36 P1.6 P3.2 37 P1.7 P3.3 38 P3.0 P3.4 39 FI D P3.5 40 P3.1 P3.6 6. Chip Block Diagram EN Table 5-1 QFN5x5 40 Pin Fig 6-1. A8105 QFN5x5 40 pin Block Diagram Note*: Only 32KByes version (A8105F5) support AES128/CCM*. Sep., 2014, Version 0.6 (Preliminary) 7 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 7. Absolute Maximum Ratings With respect to Rating Unit Supply voltage range (VDD) GND -0.3 ~ 3.6 V Digital IO pins range GND -0.3 ~ VDD+0.3 V Voltage on the analog pins range GND -0.3 ~ 2.1 Input RF level 14 ESD Rating dBm -55 ~ 125 C ± 2K V ± 100 V TI A Storage Temperature range V L Parameter HBM MM FI D EN *Stresses above those listed under “Absolute Maximum Rating” may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. A M IC C O M C O N *Device is ESD sensitive. Use appropriate ESD precautions. HBM (Human Body Mode) is tested under MIL-STD-883F Method 3015.7. MM (Machine Mode) is tested under JEDEC EIA/JESD22-A115-A. *Device is Moisture Sensitivity Level III (MSL 3). Sep., 2014, Version 0.6 (Preliminary) 8 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 8. Electrical Specification (Ta=25℃, REGI = 3.3V, internal regulator voltage = 1.8V, unless otherwise noted) Parameter Description Min. Type Max. Unit 85 0.8 3 5 2.5 3 C V uA uA uA mA mA 9.5 17.5 18 18.5 23.5 mA mA mA mA mA 0.6 ms 16 MHz ohm MHz dBc General Current Consumption (RF with MCU in normal mode) Standby Mode FI D PLL Mode RX Mode (AGC Off) RX Mode (AGC On) TX Mode (@0dBm output) TX Mode (@6dBm output) 2.0 3.6 TI A With internal regulator Deep Sleep Sleep(WOR/TWOR off) Sleep (WOR /TWOR wake) Normal L -40 Supply Voltage Current Consumption (MCU only, RF in sleep mode) EN Operating Temperature Synthesizer block (includes crystal oscillator, PLL and VCO.) Idle to standby (Xtal, 49US type, is stable at 40ppm) N Crystal start up time C O Crystal frequency Crystal ESR VCO Operation Frequency PLL phase noise 80 95 105 M Offset 100k Offset 500K Offset 1M PLL settling time O Output power range IC C Out Band Spurious Emission 1 A M Frequency deviation S 75 @Loop BW = 100Khz TX 80 2483.5 2400 -10 30MHz~1GHz 1GHz~12.75GHz -36 -30 dBm dBm dBm 1.8GHz~ 1.9GHz 5.15GHz~ 5.3GHz -47 -47 dBm dBm 500Kbps 1M 2M Data rate 0 10 186K 250K Hz Hz 500K Hz Bps 4K 2M 70 S dBm dBm dBm IF frequency bandwidth -90 -92 -96 1200/2400 IF center frequency 1000/2000 KHz Co-Channel (C/I0) 11 dB 1 Adjacent Channel (C/I1) 2 dB TX settling time Loop bandwidth 100K RX Receiver sensitivity @ BER = 0.1% Data rate 2M (FIF = 2MHz) Data rate 1M (FIF = 1MHz) Data rate 500K (FIF = 1MHz) Interference st Sep., 2014, Version 0.6 (Preliminary) 9 KHz AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 2 nd Adjacent Channel (C/I2) -18 dB 3 Adjacent Channel (C/I3) -28 dB Image (C/IIM) -12 dB rd @RF input (BER=0.1%) 30MHz~1GHz 1GHz~12.75GHz RSSI Range with AGC turn on @RF input -100 0 dBm dBm dBm -10 dBm TI A 12Bit SAR ADC Input voltage range External reference voltage Input capacitor Bandwidth EOB, effective number of bits INL DNL Conversion time Current consumption 0 -52 -47 L Maximum Operating Input Power Spurious Emission 1.8 EN 1.8 25 200 10 +/- 2 +/-1 FI D 128 Regulator Regulator settling time Pin 19 connected to 1nF N Band-gap reference voltage Regulator output voltage C O Digital IO DC characteristics High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Output Voltage (VOH) Low Level Output Voltage (VOL) 0.4 s V V 200 1.21 1.8 VDD 0.2*VDD VDD 0.4 V V V V A M IC C O M @IOH= -0.5mA @IOL= 0.5mA 0.8*VDD 0 VDD-0.4 0 8 V V pF KHz bit LSB LSB uS mA Sep., 2014, Version 0.6 (Preliminary) 10 AMICCOM Electronics Corporation 9. SFR & RFR(Radio Frequency Register) A8105 contains standard 8051 SFRs(special function registers) and RFR (RF control registers). A8051’s SFR location is almost the same as the standard 8052 SFR location. RFR is Radio Frequency Registers are located in XDATA spaces and located in 0x0800 ~ 0x08FF. For more detail information, please reference Section 9.2. 9.1 SFR Overview Table 9.1 A8105 Special Function Registers (SFRs) table 1/9 2/A 3/B 4/C 5/D OSCCON 0xF0 B I2CSADR 0xE8 EIE 0xE0 ACC P3OE P3PUN P3WUN 0xD8 WDCON P1OE P1PUN P1WUN 0xD0 PSW P0OE P0PUN P0WUN 0xC8 T2CON T2IF RLDL RLDH 0xB8 IP PCONE RSFLAG IOSEL 0xB0 P3 PWM1CON PWM1H PWM1L 0xA8 IE PWM0CON PWM0H PWM0L 0xA0 P2 P2OE P2PUN 0x98 SOCN0 SBUF0 0x90 P1 EIF 0x88 TCON TMOD 0x80 P0 SP I2CSCR I2CSBUF L EIP 7/F I2CMSA I2CMCR I2CMBUF SPCR SPSR SPDR SSCR SPCR1 SPSR1 SPDR1 SSCR1 TL2 TH2 DEVICR FI D 0xC0 I2CMTP TI A 0xF8 6/E EN 0/8 N ADCCH P2WUN C O FLASHCTRL FLASHMR USBADDR USBDATA TL1 TH0 TH1 CKCON DMAIR DPL0 DPH0 DPL1 DPH1 DPS PCON M TL0 O : It means bit-addressable : It means reserved. IC C Following are description of SFRs related to the operation of A8105 System Controller. Detailed descriptions of the remaining SFRs are including the sections of the datasheet associated with their corresponding system function. The arithmetic section of the processor performs extensive data manipulation and is comprised of the 8-bit arithmetic logic unit (ALU), an ACC(0xE0) register, B(0xF0) register and PSW(0xD0) register. A M PSW (Address: D0h) Address/Name D0h PSW Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W CY AC F0 RS1 RS2 0 0 0 0 0 Program Status Word register OV F1 P 0 0 0 The ALU performs typical arithmetic operations as: addition, subtraction, multiplication, division and additional operations such as: increment, decrement, BCD-decimal-add-adjust and compare. Within logic unit are performance: AND, OR, Exclusive OR, complement and rotation. The Boolean processor performance the bit operations as: set, clear, complement, jump-if-not-set, jump-if-set-and-clear and move to/from carry. CY - Carry flag AC - Auxiliary carry F0 - General purpose flag 0 RS[1:0] - Register bank select bits Aug., 2014, Version 0.6 (Preliminary) 11 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC TI A L OV - Overflow flag F1 - General purpose flag 1 P - Parity flag The PSW contains several bits that reflect the current state of the CPU. ACC (Address: E0h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address/Name F0h B Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EN Address/Name E0h ACC Reset R/W 0 0 0 B (Address: F0h) R/W 0 0 0 0 0 0 0 B Register The B register is used during multiply and divide operations. In other cases may be used as normal SFR. A M IC C O M C O 0 N FI D 0 0 0 0 0 Accumulator ACC Register Sep., 2014, Version 0.6 (Preliminary) 12 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 9.2 RFR Overview W R W R W R RESETN -STRB7 WTR Bit 6 Bit 5 Bit 4 FWPRN FRPRN ADC12RN FECF CRCF CER STRB6 STRB5 STRB4 P_CKO P_IRQ1O P_IRQ2O ARSSI AIF DFCD ARSSI AIF CD WWS_AC WWS_AC R/W FIFOREV RSSC 7 6 Bit 3 Bit 2 Bit 1 Bit 0 -XER STRB3 FPF WWSE WWSE BFCRN PLLER STRB2 -FMT FMT -- TRSR STRB1 -FMS FMS -TRER STRB0 -ADCM ADCM VDC VCC VBC FBC W FEP7 FEP6 FEP5 FEP4 FEP3 W FPM1 FPM0 PSA5 PSA4 PSA3 L Bit 7 TI A R/W FEP2 FEP1 FEP0 PSA2 PSA1 PSA0 WWS_SL7 WWS_SL6 WWS_SL5 WWS_SL4 WWS_SL3 WWS_SL2 WWS_SL1 WWS_SL0 W WWS_SL9 WWS_SL8 EN W WWS_AC WWS_AC WWS_AC WWS_AC WWS_AC WWS_AC 5 4 3 2 1 0 BBCKS0 -- CRCSW W R W R W R RCOT[2:0] NUMLH[11:8] MRCT9 MRCT8 -NUMLH7 NUMLH6 NUMLH5 MRCT7 MRCT6 MRCT5 RCOC7 RCOC6 RCOC5 BLE_ON FI D BBCKS1 WCKSEL[1:0] ---NUMLH4 NUMLH3 MRCT4 MRCT3 RCOC4 RCOC3 W W C O N W RCTS TSEL MVS[1:0] RCOC[9:8] TMRE MAN NUMLH2 NUMLH1 MRCT2 MRCT1 RCOC2 RCOC1 TWOR_E ENCAL ENCAL MCALS NUMLH0 MRCT0 RCOC0 TGNUM[11:8] TGNUM[7:0] CKOS2 CKOS1 CKOS0 CKOI WAKEBBI E INTT1IE VGC0 GIO1S3 GIO1S2 GIO1S1 GIO1S0 GIO1I -- HBW WWS_AC 8 GIO2S3 GIO2S2 GIO2S1 GIO2S0 GIO2I -- GRC3 GRC2 GRC1 GRC0 IDREV CSC0 CGS XS IC Address / Name 0x800h MODE 0x801h MODEC1 0x802h MODEC2 0x803h CALC 0x804h FIFO I 0x805h FIFO II 0x806h RC OSC 1 0x807h RC OSC 2 0x808h RC OSC 3 0x809h RC OSC 4 0x80Ah RC OSC 5 0x80Bh RC OSC 6 0x80Ch RC OSC 7 0x80Dh RC OSC 8 0x80Eh CKO Pin 0x80Fh GPIO1 Pin I 0x810h GPIO2 Pin II 0x811h Clock 0x812h Data rate 0x813h PLL I 0x814h PLL II 0x815h PLL III 0x816h PLL IV 0x817h PLL V 0x818h TX I 0x819h TX II 0x81Ah Delay I 0x81Bh Delay II R/W SDR7 SDR6 SDR5 SDR4 SDR3 SDR2 SDR1 SDR0 R/W CHN7 CHN6 CHN5 CHN4 CHN3 CHN2 CHN1 CHN0 R/W DBL RRC1 RRC0 CHR3 CHR2 CHR1 CHR0 IP8 R/W IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 W R W R FP15 -FP7 AC7 FP14 AC14 FP6 AC6 FP13 AC13 FP5 AC5 FP12 AC12 FP4 AC4 FP11 AC11 FP3 AC3 FP10 AC10 FP2 AC2 FP9 AC9 FP1 AC1 FP8 AC8 FP0 AC0 W GDR TMDE TXDI TME FS FDP2 FDP1 FDP0 W FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 W DPR2 DPR1 DPR0 TDL1 TDL0 PDL2 PDL1 PDL0 W WSEL2 WSEL1 WSEL0 AGC_D1 AGC_D0 DOCKOE W VGC1 A M C R/W O W CKOS3 M W Sep., 2014, Version 0.6 (Preliminary) 13 RS_DLY2 RS_DLY1 RS_DLY0 AMICCOM Electronics Corporation A8105 RXSM0 AFC RXDI DMG BWS ULS W R W R W R W R W R AGCE ADC8 PKIS1 -IFPK RH7 MXD RL7 RTH7 ADC7 MIC MICR PKIS0 -VRSEL RH6 CSS RL6 RTH6 ADC6 IGC1 IGCR1 PKT1 -MS RH5 HPLS RL5 RTH5 ADC5 IGC0 IGCR0 PKT0 -MSCL4 RH4 MHC1 RL4 RTH4 ADC4 MGC1 MGCR1 DCH1 -MSCL3 RH3 MHC0 RL3 RTH3 ADC3 MGC0 MGCR0 DCH0 -MSCL2 RH2 LHC1 RL2 RTH2 ADC2 LGC1 LGCR1 RSAGC1 VTB1 MSCL1 RH1 LHC0 RL1 RTH1 ADC1 LGC0 LGCR0 RSAGC0 VTB0 MSCL0 RH0 XADSP RL0 RTH0 ADC0 W RSM1 RSM0 ERSS FSARS SYNCS XADS RSS CDM W XDS MCS WHTS FECS CRCS PML2 PML1 PML0 W DCL2 DCL1 DCL0 ETH2 W IDL WS6 WS5 WS4 RNUM0_2 RNUM0_1 RNUM0_0 ---- TI A ETH0 PMD1 PMD0 WS3 WS2 WS1 WS0 MFBS FBCF MFB3 FB3 MFB2 FB2 TRT0 MRCKS FCD4 MVCS FCD3 VCOC3 FVCC VCB3 VCB2 VCB1 VCB0 MFB1 MFB0 FB1 FB0 RNUM1_ RNUM1_2 RNUM1_0 1 FCD2 FCD1 FCD0 VCOC2 VCOC1 VCOC0 PWORS TRT2 TRT1 R W --- -PKS -VCCS R TWORF -- -- W DCD1 DCD0 DAGS PDV MVBS MVB2 MVB1 MVB0 R -- -- -- -- VBCF VB2 VB1 VB0 W DAMV1 DAMV0 VTH2 VTH1 VTH0 VTL2 VTL1 VTL0 W R RGS -- RGV0 RGV0 PACTL BDF BVT2 BVT2 BVT1 BVT1 BVT0 BVT0 BDS BDS W M C O N W RGV1 RGV1 IFBC1 IFBC0 TXCS PAC1 PAC0 TBG2 TBG1 TBG0 DMT DCM1 DCM0 MLP1 MLP0 SLF2 SLF1 SLF0 W DCV7 DCV6 DCV5 DCV4 DCV3 DCV2 DCV1 DCV0 W CPM3 CPM2 CPM1 CPM0 CPT3 CPT2 CPT1 CPT0 W PRS QDS QCLIM DBD XCC1 XCC0 XCP1 XCP0 W MDEN PMPE PRIC1 PRIC0 PRRC1 PRRC0 SDPW NSDO W DEVGD2 DEVGD1 DEVGD0 TLB1 TLB0 RLB1 RLB0 MGS W CHD3 CHD2 CHD1 CHD0 RFT3 RFT2 RFT1 RFT0 W MPDT5 MPDT4 MPDT3 MPDT2 MPDT1 MPDT0 -- LIMC W ASMV2 ASMV1 ASMV0 SDMS OLM CPCS CPH CPS W R W ---- CRS3 CRSR3 STMP CRS2 CRSR2 STM5 CRS1 CRSR1 STM4 CRS0 CRSR0 STM3 SRS2 SRSR2 STM2 SRS1 SRSR1 STM1 SRS0 SRSR0 STM0 W M A ETH1 FI D W R L RXSM1 IC 0x828h VCO current Calibration 0x829h VCO band Calibration I 0x82Ah VCO band Calibration II 0x82Bh Battery detect 0x82Ch TX test 0x82Dh Rx DEM test I 0x82Eh Rx DEM test II 0x82Fh Charge Pump Current I 0x830h Crystal test 0x831h PLL test 0x832h VCO test I 0x833h VCO test II 0x834h IFAT 0x835h RF test I 0x836h RF test II 0x837h MSCRC O 0x827h IF Calibration II W C 0x81Ch RX 0x81Dh RX Gain I 0x81Eh RX Gain II 0x81Fh RX Gain III 0x820h RX Gain IV 0x821h RSSI Threshold 0x822h ADC 0x823h Code I 0x824h Code II 0x825h Code III 0x826h IF Calibration I EN 2.4GHz FSK/GFSK SoC Sep., 2014, Version 0.6 (Preliminary) 14 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC ---FGC1 FGCR1 -DVI1 -FGC0 FGCR0 -- -- STMR2 FBG2 FBGR2 CTR2 CTRR2 STMR1 FBG1 FBGR1 CTR1 CTRR1 STMR0 FBG0 FBGR0 CTR0 CTRR0 CHIDX[5:0] L TI A CRCINIT7 CRCINIT6 CRCINIT5 CRCINIT4 CRCINIT3 CRCINIT2 CRCINIT1 CRCINIT0 EN CRCINR2 CRCINR2 CRCINR2 CRCINR2 CRCINR1 CRCINR1 CRCINR1 CRCINR1 3 2 1 0 9 8 7 6 CRCINR1 CRCINR1 CRCINR1 CRCINR1 CRCINR1 CRCINR1 CRCINR9 CRCINR8 5 4 3 2 1 0 CRCINR7 CRCINIR6 CRCINIR5 CRCINIR4 CRCINIR3 CRCINIR2 CRCINIR1 CRCINIR0 MDAG6 MDAG5 MDAG4 MDAG3 MDAG2 MDAG1 MDAG0 ADAG7 ADAG6 ADAG5 ADAG4 ADAG3 ADAG2 ADAG1 ADAG0 DEVS3 DEVS2 DEVS1 VMS_M MSEL DEVA7 DEVA6 DEVA5 MVDS DEVM6 DEVM5 ADEV7 ADEV6 ADEV5 VMG7 VMG6 VMG5 AVSEL1 AVSEL0 -- FI D MDAG7 DEVS0 DAMR_M VMTE_M DEVA2 DEVA1 DEVA0 DEVM4 DEVM3 DEVM2 DEVM1 DEVM0 ADEV4 ADEV3 ADEV2 ADEV1 ADEV0 VMG4 VMG3 VMG2 VMG1 VMG0 MVSEL1 MVSEL0 RADC FPS2 FPS1 FPS0 SPSS WMODE WN1 WN0 CHGL6 CHGL5 CHGL4 CHGL3 CHGL2 CHGL1 CHGL0 CHGH6 CHGH5 CHGH4 CHGH3 CHGH2 CHGH1 CHGH0 CPTX3 CPTX2 CPTX1 CPTX0 CPRX3 CPRX2 CPRX1 CPRX0 -- INTPRC DEVFD2 DEVFD1 DEVFD0 DEVD2 DEVD1 DEVD0 VRPL1 VRPL0 VCOSC5 VCOSC4 VCOSC3 VCOSC2 VCOSC1 VCOSC0 DC_SEL RXDCS PREDN2 PREUP2 PREUP1 PREUP0 TX_HEAD ER15 RX_HEAD ER15 TX_HEAD ER7 RX_HEAD ER7 TX_HEAD ER14 RX_HEAD ER14 TX_HEAD ER6 RX_HEAD ER6 TX_HEAD ER13 RX_HEAD ER13 TX_HEAD ER5 RX_HEAD ER5 PREDN1 PREDN0 DCOUT[7:0] TX_HEAD TX_HEAD ER12 ER11 RX_HEAD RX_HEAD ER12 ER11 TX_HEAD TX_HEAD ER4 ER3 RX_HEAD RX_HEAD ER4 ER3 TX_HEAD ER10 RX_HEAD ER10 TX_HEAD ER2 RX_HEAD ER2 TX_HEAD ER9 RX_HEAD ER9 TX_HEAD ER1 RX_HEAD ER1 TX_HEAD ER8 RX_HEAD ER8 TX_HEAD ER0 RX_HEAD ER0 W/R ID31 ID30 ID29 ID28 ID27 ID26 ID25 ID24 W/R ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 W R W R M C O N DEVA3 CHGL7 CHGH7 C 0x84Fh ID0 0x850h ID1 STMR3 FBG3 FBGR3 CTR3 CTRR3 CRCINIT2 CRCINIT2 CRCINIT2 CRCINIT2 CRCINIT1 CRCINIT1 CRCINIT1 CRCINIT1 3 2 1 0 9 8 7 6 CRCINIT1 CRCINIT1 CRCINIT1 CRCINIT1 CRCINIT1 CRCINIT1 CRCINIT9 CRCINIT8 5 4 3 2 1 0 IC 0x84Eh BLE_HEADER1 STMR4 FBG4 FBGR4 CTR4 CTRR4 DEVA4 M A 0x84Dh BLE_HEADER0 STMR5 DVI0 -CTR5 CTRR5 O RF test III R W 0x838h RF test IV R W 0x839h RF test V R 0x83Ah W Channel Index 0x83Bh W CRC1 0x83Ch W CRC2 0x83Dh W CRC3 0x83Eh W CRC4 0x83Fh W CRC5 0x840h W CRC6 0x841h W VCO band R Calibration III 0x842h W VCO deviation R Calibration I 0x843h W VCO deviation R Calibration II 0x844h VCO deviation W/R Calibration III 0x845h W ADC Control 0x846h W WOT 0x847h R/W Channel Group I 0x848h R/W Channel Group II 0x849h Charge Pump W Current II 0x84Ah VCO modulation W Delay 0x84Bh W INTC W 0x84Ch DET R Sep., 2014, Version 0.6 (Preliminary) 15 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 W/R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 R DID31 DID30 DID29 DID28 DID27 DID26 DID25 DID24 R DID23 DID22 DID21 DID20 DID19 DID18 DID17 DID16 R DID15 DID14 DID13 DID12 DID11 DID10 DID9 DID8 R DID7 DID6 DID5 DID4 DID3 DID2 DID1 W/R -- XEC BREV BGS LIMB ADCCS BOD REGR W VTRB3 VTRB2 VTRB1 VTRB0 VMRB3 VMRB2 VMRB1 VMRB0 W -- IFAS CGC IWA IWC LBG VCS VCSW MVADC7 MVADC6 MVADC5 R ADC7 ADC6 ADC5 TI A MVS2 MVS2 ADIVL ADC11 MVS1 MVS1 ADCYC ADC10 MVS0 MVS0 ENADC ADC9 ADCE ADCE DTMP ADC8 MVADC4 MVADC3 MVADC2 MVADC1 MVADC0 ADC4 ADC3 ADC2 ADC1 ADC0 TMR_ITV[15:8] W W TMRWORS W R TMRON -- W W O W C O W W M -- TMRIE TMRIE - TMR_ITV[7:0] -- TMR_OFS4 TMR_OFS3 TMR_OFS2 TMR_OFS1 TMR_OFS0 TMRIF TMRIF TMRCOR -- TMRWOR -- TMRCKS1 TMRCKS1 TMRCKS0 TMRCKS0 TMR_CE TMR_CE CBG1 CBG0 PDNS STA ENDL2 ENDL1 ENDL0 EBOD ENAV QDSA ENDV QDSD CEL SVREF CELA P3PUNIE -- -- RCR1 RCR0 RGC1 RGC0 RCHC C CBG2 W MR[7:0] (analog) M A EN R MODE MODE -MVADC8 FI D BUFS CKS ----ADCIE --MVADC11 MVADC10 MVADC9 DID0 N W R W R L W/R IC 0x851h ID2 0x852h ID3 0x853h DID0 0x854h DID1 0x855h DID2 0x856h DID3 0x857h EXT1 0x858h EXT2 0x859h EXT3 0x85Ah ADCCTL 0x85Bh ADCAVG1 0x85Ch ADCAVG2 0x85Dh ADCAVG3 0x85Eh TMRITV1 0x85Fh TMRITV2 0x860h TMRWOR0 0x861h TMRWOR1 0x862h TMRCTL 0x863h PWRCTL0 0x864h PWRCTL1 0x865h PWRCTL2 0x866h PWRCTL3 0x867h PWRCTL4 0x868h DCSFT 0x869h TX5DY 0x87Ch ACKRT W MS[7:0] (analog) W dc_shift[7:0] W/R HDRSW EARTS W -- -- EACKS TX_5DLY[4:0] LL_TIME_OUT[5:0] Legend: - = unimplemented Sep., 2014, Version 0.6 (Preliminary) 16 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 9.2.1 Mode Register (Address: 0x800h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MODE W R RESETN --- FWPRN FECF -- FRPRN CRCF -- ADC12RN CER -- -XER -- BFCRN PLLER -- -TRSR -- -TRER -- Reset RESETN: Write to this register by 0x00 to issue reset command, then it is auto clear L FWPRN: FIFO Write Point Software Reset. TI A FRPRN: FIFO Read Point Software Reset. ADC12RN: 12-bits ADC Software Reset. EN BFCRN: IF Filter Bank Calibration Software Reset. FECF: FEC flag. [0]: FEC pass. [1]: FEC error. FI D CRCF: CRC flag. [0]: CRC pass. [1]: CRC error. CER: RF chip enable status. [0]: RF chip is disabled. [1]: RF chip is enabled. N XER: Internal crystal oscillator enabled status. [0]: Crystal oscillator is disabled. [1]: Crystal oscillator is enabled. C O PLLER: PLL enabled status. [0]: PLL is disabled. [1]: PLL is enabled. M TRSR: TRX Status Register. [0]: RX state. [1]: TX state. Serviceable if TRER=1 (TRX is enable). O TRER: TRX state enabled status. [0]: TRX is disabled. [1]: TRX is enabled. Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W R STRB7 STRB6 STRB5 STRB4 STRB2 STRB1 STRB0 ARCWTR P_CKO 1 0 STRB3 FSYNC 0 0 0 0 IC MODEC1 C 9.2.2 Mode Control Register 1 (Address: 0x801h) P_IRQ1O P_IRQ2O 1 0 M Reset A STRB[7:0]: Strobe command register. [80]: Sleep mode. [90]: Idle mode. [A0]: Standby mode. [B0]: PLL mode. [C0]: TX mode. [D0]: RX mode. Reverse for other settings. ARCWTR: Read ARCWTR output signal. P_CKO: Read P_CKO pin output signal. P_IRQ1O: Read P_IRQ1O pin output signal. P_IRQ2O: Read P_IRQ2O pin output signal. Sep., 2014, Version 0.6 (Preliminary) 17 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC FSYNC: Read Frame sync ok output signal. 9.2.3 Mode Control Register 2 (Address: 0x802h) R/W MODEC2 W R Bit 7 Reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ARSSI ARSSI 0 AIF AIF 0 DFCD CD 0 WWSE WWSE 0 FMT FMT 0 FMS FMS 0 ADCM ADCM 0 L Name TI A ARSSI: Auto RSSI measurement while entering RX mode. [0]: Disable. [1]: Enable. AIF (Auto IF Offset): RF LO frequency will auto offset one IF frequency while entering RX mode. [0]: Disable. [1]: Enable. EN CD / DFCD: DFCD (Data Filter by CD): The received package will be filtered out if Carrier Detector signal is inactive. [0]: Disable. [1]: Enable. FI D CD (Read): Carrier detector signal. [0]: Input power below threshold. [1]: Input power above threshold. WWSE: Reserved for internal usage only. Shall be set to [0]. N FMT: Reserved for internal usage only. Shall be set to [0]. FMS: Direct/FIFO mode select. [0]: Direct mode. [1]: FIFO mode. C O ADCM: ADC measurement enable (Auto clear when done). [0]: Disable measurement or measurement finished. [1]: Enable measurement. ADCM A8105 @ Standby mode A8105 @ RX mode [0] Disable ADC D i s a b l e Measure temperature, external Analog Digital [1] Measure RSSI, carrier detect Convert D C O M A 9.2.4 Calibration Control Register (Address: 0x803h) Bit 7 W Bit 6 Bit 5 WWS_AC WWS_AC FIFOREV 7 6 IC CALC R/W C Name Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RSSC VDC VCC VBC FBC 0 0 0 0 0 R -- -- -- M Reset A WWS_AC [7:6]: See 9.2.8 FIFOREV: FIFO reverse enable. [0]: Disable. [1]: Enable RSSC: RSSI calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. VCC: VCO Current calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. VBC: VCO Bank calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. VDC: VCO Deviation calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. Sep., 2014, Version 0.6 (Preliminary) 18 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC FBC: IF Filter Bank calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. 9.2.5 FIFO Register I (Address: 0x804h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFO I Reset W FEP7 0 FEP6 0 FEP5 1 FEP4 1 FEP3 1 FEP2 1 FEP1 1 FEP0 1 FEP [7:0]: FIFO End Pointer for TX FIFO and Rx FIFO. Refer to chapter chapter 21 for details. 9.2.6 FIFO Register II (Address: 0x805h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 FIFO II Reset W FPM1 0 FPM0 1 PSA5 0 PSA4 0 PSA3 0 PSA [5:0]: Used for Segment FIFO. Refer to chapter 21 for details. 9.2.7 RC OSC Register I (Address: 0x806h) W Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 PSA2 0 PSA1 0 PSA0 0 Bit 3 Bit 2 Bit 1 Bit 0 N R/W Bit 1 WWS_SL7 WWS_SL6 WWS_SL5 WWS_SL4 WWS_SL3 WWS_SL2 WWS_SL1 WWS_SL0 0 0 0 0 0 0 0 0 C O Name RC OSC I Reset FI D FPM [1:0]: FIFO Pointer Margin Bit 2 EN Name TI A L Name WWS_SL [9:0]: 10-bits WWS_SL Timer for TWWS Function (7.8ms ~ 7.99s). WWS_SL [9:0] are from address (0x806h) and (0x807h). 9.2.8 RC OSC Register II (Address: 0x807h) W Bit 7 Bit 6 M R/W Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WWS_SL9 WWS_SL8 WWS_AC5 WWS_AC4 WWS_AC3 WWS_AC2 WWS_AC1 WWS_AC0 0 0 0 0 0 0 0 0 O Name RC OSC II Reset C WWS_SL [9:0]: 10-bits WWS_SL Timer for TWWS Function (7.8ms ~ 7.99s). WWS_SL [9:0] are from address (0x806h) and (0x807h). IC WWS_AC [8:0]: 9-bits WWS_AC Timer for TWWS Function (244us ~ 15.6ms). M 9.2.9 RC OSC Register III (Address: 0x808h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W BBCKS1 0 BBCKS0 0 --- CRCSW -- BLE_ON -- RCTS 1 TSEL 0 TWWS_E 1 A Name RC OSC III Reset BBCKS [1:0]: Clock select for internal digital block [00]: FSYCK / 8. [01]: FSYCK / 16. [10]: FSYCK / 32. [11]: FSYCK / 64. FSYCK :System clock. Should be set to 8MHz. CRCSW: CRC select (BLE_ON=0). [0]: Select CRC-16, CCITT. [1]: Select CRC-24 (BLE). BLE_ON: Bluetooth Low-Energy Mode enable. [0]: Disable. [1]: Enable. RCTS: Internal / External 32.768k Hz oscillator selection. [0]: Internal. [1]: External. Sep., 2014, Version 0.6 (Preliminary) 19 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC TSEL: Timer select for TWWS function. [0]: Use WWS_AC. [1]: Use WWS_SL. TWWS_E: Enable TWWS function. [0]: Disable. [1]: Enable. 9.2.10 RC OSC Register IV (Address: 0x809h) Bit 7 Bit 6 Bit 5 RC OSC IV W R RCOT2 NUMLH11 -- RCOT1 NUMLH10 -- RCOT0 NUMLH9 -- Reset Bit 4 Bit 3 WCKSEL1 WCKSEL0 NUMLH8 -0 0 MVS1 RCOC9 0 MVS0 RCOC8 0 Bit 0 ENCAL ENCAL 0 FI D WSEL [1:0]: Clock select for internal RC oscillator Calibration [00]: 16 MHz [01]: 8 MHz [10]: 4 MHz [11]: 2MHz Bit 1 EN RCOT[2:0]: RCOSC current select for RC oscillator calibration. Bit 2 L R/W TI A Name ENCAL: WOR calibration enable. [0]: Disable [1]: Enable. N RCOC [9:0]: WOR Calibration value. C O NUMLH[11:0]: WOR calibration latch number. 9.2.11 RC OSC Register V (Address: 0x80Ah) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RC OSC V W R MRCT9 NUMLH7 0 MRCT8 NUMLH6 0 -NUMLH5 -- -NUMLH4 -- -NUMLH3 -- TMRE NUMLH2 -- MAN NUMLH1 0 MCALS NUMLH0 0 M Reset O MRCT[9:0]: Manual RC-OSC calibration value setting. C MAN: Enable Manual RC-OSC Calibration. [0]: Auto [1]: Manual. IC TMRE: RC-oscillator enable. [0]: Disable. [1]: Enable. M MCALS: Enable Continuous RC-OSC Calibration. [0]: Continuous mode. [1]: Single mode. A NUMLH[11:0]: RC-OSC calibration latch number. 9.2.12 RC OSC Register VI (Address: 0x80Bh) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RC OSC VI W R MRCT7 RCOC7 0 MRCT6 RCOC6 0 MRCT5 RCOC5 0 MRCT4 RCOC4 0 MRCT3 RCOC3 0 MRCT2 RCOC2 0 MRCT1 RCOC1 0 MRCT0 RCOC0 0 Reset MRCT [9:0]: Manual RC-OSC calibration value setting. RCOC [9:0]: RC-OSC calibration value. Sep., 2014, Version 0.6 (Preliminary) 20 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 9.2.13 RC OSC Register VII (Address: 0x80Ch) Name R/W RCOSC7 Reset W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -- -- -- -- TGNUM11 TGNUM10 TGNUM9 TGNUM8 -- -- -- -- 0 0 0 0 TGNUM[11:0]: Target Number for RC OSC Calibration. 9.2.14 RC OSC Register VIII (Address: 0x80Dh) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCOSC8 Reset W TGNUM7 TGNUM6 TGNUM5 TGNUM4 TGNUM3 TGNUM2 TGNUM1 TGNUM0 0 0 0 0 0 R/W CKO Pin Control W Bit 7 Bit 6 Bit 5 Bit 4 ECKOE CKOS3 CKOS2 CKOS1 1 0 1 1 Reset Bit 3 Bit 2 CKOS0 CKOI 1 0 FI D Name TI A 9.2.15 CKO Pin Control Register (Address: 0x80Eh) 0 EN TGNUM[11:0]: Target Number for RC OSC Calibration. L Name 0 0 Bit 1 Bit 0 WAKEBBI INTT1IE E -- -- ECKOE: External Clock Output Enable for CKOS [3:0]= [0100] ~ [0111]. [0]: Disable. [1]: Enable. C O M C O N CKOS[3:0]: CKO pin output select. [0000]: DCK (TX data clock). [0001]: RCK (RX recovery clock). [0010]: FPF (FIFO pointer flag). [0011]: EOP, EOVBC, EOFBC, EOADC, EOVCC, OKADC, RSSC_OK (Internal usage only). [0100]: External clock output= FSYCK. [0101]: External clock output / 2= FSYCK / 2. [0110]: External clock output / 4= FSYCK / 4. [0111]: External clock output / 8= FSYCK / 8. [1000]: WCK.(4Khz) [1001]: PF8M(8MHz) [1010]: TMRCK(32Khz) [1011]: SYCK(8Mhz) [1100]: TMRCK_OVF(Timer clock) IC CKOI: CKO pin output signal invert. [0]: Non-inverted output. [1]: Inverted output. M WAKEBBIE: Wake BB interrupt enable. [0]: Disable. [1]: Enable. A INTT1IE: ARCWTR interrupt enable. [0]: Disable. [1]: Enable. 9.2.16 GIO1 Pin Control Register I (Address: 0x80Fh) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GPIO1 Pin I Reset W VGC1 0 VGC0 0 GIO1S3 0 GIO1S2 0 GIO1S1 0 GIO1S0 0 GIO1I 0 --- GIO1S [3:0]: GIO1 pin function select. GIO1S [3:0] TX state RX state [0000] WTR (Wait until TX or RX finished) [0001] EOAC (end of access code) FSYNC (frame sync) TMEO or TMDEO (TX [0010] CD (carrier detect) modulation enable) Sep., 2014, Version 0.6 (Preliminary) 21 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC L Preamble Detect Output (PMDO) MCU wakeup signal (TWWS) In phase demodulator input (DMII) Reserved TRXD In/Out (Direct mode) RXD (Direct mode) TXD (Direct mode) In phase demodulator external input (EXDI0) External FSYNC input in RX direct mode INC PDN_RX INT5 Reserved TI A [0011] [0100] [0101] [0110] [0111] [1000] [1001] [1010] [1011] [1100] [1101] [1110] [1111] 9.2.17 GIO2 Pin Control Register II (Address: 0x810h) R/W GIO2 Pin Control II Bit 7 Bit 6 Bit 5 Bit 4 HBW WWS_AC 8 GIO2S3 GIO2S2 0 -- 0 W Reset WWS_AC8: See 9.2.8 IF(Hz) BW 1 1 2000 1200 1 0 2000 2400 0 1 1000 1200 0 0 1000 1200 Bit 0 GIO2S1 GIO2S0 GIO2I -- 1 0 0 0 -- C O HBW Bit 1 M BWS Bit 2 N HBW: IF bandwidth setting. Bit 3 FI D Name EN GIO1I: GIO1 pin output signal invert. [0]: Non-inverted output. [1]: Inverted output. A M IC C O GIO2S [3:0]: GIO2 pin function select. GIO2S TX state RX state [0000] ARCWTR (Wait until TX or RX finished) [0001] EOAC (end of access code) FSYNC (frame sync) TMEO or TMDEO(TX [0010] CD (carrier detect) modulation enable) [0011] Preamble Detect Output (PMDO) [0100] MCU wakeup signal (TWWS) [0101] Quadrature phase demodulator input (DMIQ) [0110] Reserved [0111] TRXD In/Out (Direct mode) [1000] RXD (Direct mode) [1001] TXD (Direct mode) [1010] Quadrature phase demodulator external input (EXDI1) [1011] External FSYNC input in RX direct mode [1100] DEC [1101] PDN_TX [1110] Reserved [1111] Reserved GIO2I: GIO2 pin output signal invert. [0]: Non-inverted output. [1]: Inverted output. Sep., 2014, Version 0.6 (Preliminary) 22 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 9.2.18 Clock Register (Address: 0x811h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Clock Reset R/W GRC3 1 GRC2 1 GRC1 1 GRC0 1 IDREV CSC 0 CGS 1 XS 1 0 TI A IDREV: ID reverse enable. [0]: Disable. [1]: Enable. EN CSC: system clock FSYCK divider select. [0]: FCSCK . [1]: FCSCK / 2. CGS: Clock generator enable. [0]: Disable. [1]: Enable. CGS shall be set to [1]. FI D XS: Crystal oscillator select. [0]: Use external clock. [1]: Use external crystal. CGS = 0 Crystal frequency crystal frequency C O 9.2.19 Data Rate Register (Address: 0x812h) CGS = 1 32 MHz 64 MHz N Master clock frequency BWS = 0 BWS = 1 L GRC [3:0]: Clock generation reference counter. GRC is used to get 2 MHz Clock Generator Reference (FCGR) for internal usage. Clock generation reference = FCSCK / (GRC+1). Maximum divide ratio is 16. FCSCK is A8105’s master clock. Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Rate Reset R/W SDR7 0 SDR6 0 SDR5 0 SDR4 0 SDR3 0 SDR2 0 SDR1 0 SDR0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CHN6 0 CHN5 0 CHN4 0 CHN3 0 CHN2 0 CHN1 0 CHN0 0 M SDR [7:0]: Data rate division selection. Data rate = FCSCK / [32*(SDR [7:0]+1)]. Bit 7 R/W CHN7 0 IC PLL I Reset R/W C Name O 9.2.20 PLL Register I (Address: 0x813h) CHN [7:0]: LO channel number select. M 9.2.21 PLL Register II (Address: 0x814h) A Name PLL II Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W DBL DBL 0 RRC1 RRC1 0 RRC0 RRC0 0 CHR3 CHR3 0 CHR2 CHR2 1 CHR1 CHR1 1 CHR0 CHR0 1 IP8 BIP8 0 DBL: Crystal frequency doubler selection. [0]: Disable. FXREF = FXTAL. [1]: Enable. FXREF =2 * FXTAL. RRC [1:0]: RF PLL reference counter setting. CHR [3:0]: PLL channel step setting. IP [8:0]: LO frequency integer part value. IP [8:0] are from address (0x812h) and (0x813h), Sep., 2014, Version 0.6 (Preliminary) 23 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 9.2.22 PLL Register III (Address: 0x815h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLL III W R BIP7 IP7 0 BIP6 IP6 1 BIP5 IP5 0 BIP4 IP4 0 BIP3 IP3 1 BIP2 IP2 0 BIP1 IP1 1 BIP0 IP0 1 Bit 5 Bit 4 Bit 3 Reset BIP [8:0]: LO base frequency integer part setting. BIP [8:0] are from address (0x812h) and (0x813h), R/W Bit 7 PLL IV W R FP15 --/FP15 0 Reset Bit 6 Bit 2 FP14 FP13 FP12 FP11 FP10 AC14/FP14 AC13/FP13 AC12/P12 AC11/ FP11 AC10/FP10 0 0 0 0 0 Bit 1 Bit 0 FP9 AC9/FP9 0 FP8 AC8/FP8 0 FI D Name EN 9.2.23 PLL Register IV (Address: 0x816h) TI A L IP [8:0]: LO frequency integer part value. IP [8:0] are from address (0x812h) and (0x813h), FP [15:0]: LO base frequency fractional part setting. FP [15:0] are from address (0x816h) and (0x817h), N AC [14:0] (Read): Auto Frequency compensation value (if AFC (0x81Ah) =1). C O FP [15:0] (Read): LO frequency fractional part setting. 9.2.24 PLL Register V (Address: 0x817h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLL V W R FP7 AC7/FP7 0 FP6 AC6/FP6 0 FP5 AC5/FP5 0 FP4 AC4/FP4 0 FP3 AC3/FP3 0 FP2 AC2/FP2 0 FP1 AC1/FP1 1 FP0 AC0/FP0 1 Reset M Name C O FP [15:0]: LO base frequency fractional part setting. FP [15:0] are from address (0x814h) and (0x815h), IC AC [14:0] (Read): Auto Frequency compensation value (if AFC (0x81Ah) =1). FP [15:0] (Read): LO frequency fractional part setting. M 9.2.25 TX Register I (Address: 0x818h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TX I Reset W GDR 0 TMDE 1 TXDI 0 TME 1 FS 0 FDP2 1 FDP1 1 FDP0 0 A Name GDR: Gaussian Filter Over Sampling Rate Select. [0]: BT= 1. [1]: BT= 0.5 TMDE: TX Modulation Enable for VCO Modulation. [0]: Disable. [1]: Enable. TXDI: TX data invert. Recommend TXDI = [0]. [0]: Non-invert. [1]: Invert. TME: TX modulation enable. [0]: Disable. [1]: Enable. Sep., 2014, Version 0.6 (Preliminary) 24 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC FS: Filter select. The filter shape is gaussian filter. [0]: disable. [1]: enable. FDP [2:0]: Frequency deviation power setting. Refer to control register (15h). 9.2.26 TX Register II (Address: 0x819h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 TX II Reset W FD7 0 FD6 0 FD5 1 FD4 0 FD3 1 FD2 1 FD1 1 Bit 7 Bit 6 Bit 5 Bit 4 W DPR2 0 DPR1 0 DPR0 0 TDL1 1 DPR [2:0]: Delay scaling setting. Recommend DPR = [000]. EN R/W Delay Reset Bit 3 Bit 2 Bit 1 Bit 0 TDL0 0 PDL2 0 PDL1 1 PDL0 0 FI D Name FD0 1 TI A FD [7:0]: Frequency deviation setting. = FPFD /2**16*FD* 2**(FDP-1). Where FPFD= FXTAL * (DBL+1) / (RRC [1:0]+1), PLL comparison frequency. FDEV 9.2.27 Delay Register I (Address: 0x81Ah) Bit 0 L Name C O N TDL [1:0]: Delay for TX data out after PDN_TX enable. Delay= 20 * (TDL [1:0]+1)*(DPR [2:0]+1) + (TX_5DLY [4:0]+1) us. PDL [2:0]: Delay for TX settling. Delay= 20 * (PDL [2:0]+1)*(DPR [2:0]+1) us. 9.2.28 Delay Register II (Address: 0x81Bh) R/W Bit 7 Delay Reset W WSEL2 0 Bit 6 M Name Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WSEL0 0 AGC_D1 0 AGC_D0 0 RS_DLY2 0 RS_DLY1 0 RS_DLY0 1 O WSEL1 1 C WSEL[2:0]: XTAL settling delay setting (200us ~ 2.5ms). Recommend WSEL = [010]. [000]: 200us. [001]: 400us. [010]: 600us. [011]: 800us. [100]: 1ms. [101]: 1.5ms. [110]: 2ms. [111]: 2.5ms. IC AGC_D [1:0]: RSSI calibration switching time (10us ~ 40us). Recommend AGC_D = [00]. [00]: 10us. [01]: 20us. [10]: 30us. [11]: 40us. A M RS_DLY [2:0]: RSSI measurement delay (10us ~ 80us). Recommend RS_DLY = [001]. [000]: 10us. [001]: 20us. [010]: 30us. [011]: 40us. [100]: 50us. [101]: 60us. [110]: 70us. [111]: 80us. 9.2.29 RX Register (Address: 0x81Ch) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RX Reset W MSCRC 0 RXSM1 1 RXSM0 0 AFC 0 RXDI 0 DMG 0 BWS 1 ULS 0 MSCRC: Mask CRC (CRC Data Filtering Enable). [0]: Disable. [1]: Enable. RXSM [1:0]: Reserved for internal usage only. Shall be set to [10]. AFC: Auto Frequency compensation select. [0]: Manual compensation. [1]: Auto compensation. Sep., 2014, Version 0.6 (Preliminary) 25 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC RXDI: RX data output invert. Recommend RXDI = [0]. [0]: Non-inverted output. [1]: Inverted output. DMG: Reserved for internal usage only. Shall be set to [0]. IF(Hz) BW 1 1 2000 1200 1 0 2000 2400 0 1 1000 1200 0 0 1000 1200 TI A HBW EN BWS L BWS: IF Bandwidth selection. HBW: IF bandwidth setting. ULS: RX Up/Low side band select. [0]: Up side band, [1]: Low side band. R/W Bit 7 Bit 6 Bit 5 RX Gain I W R AGCE ADC8 0 MIC MICR 1 IGC1 IGCR1 1 Reset Bit 3 Bit 2 Bit 1 Bit 0 IGC0 IGCR0 1 MGC1 MGCR1 1 MGC0 MGCR0 1 LGC1 LGCR1 1 LGC0 LGCR0 1 C O AGCE: Auto Front end Gain Control Select. [0]: Disable. [1]: Enable. Bit 4 N Name FI D 9.2.30 RX Gain Register I (Address: 0x81Dh) IGC [1:0]: IFA Attenuation Select. [00]: 0dB. [01]: 6dB. [10]: 12dB. [11]: 18dB. M MGC [1:0]: Mixer Gain Attenuation select. [00]: 0dB. [01]: 6dB. [10]: 12dB. [11]: 18dB. O LGC [1:0]: LNA Gain Attenuation select. [00]: 6dB. [01]: 12dB. [10]: 18dB. [11]: 24dB. Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W PKIS1 -0 PKIS0 -0 PKT1 -0 PKT0 -1 DCH1 -0 DCH0 -0 RSAGC1 VT1 0 RSAGC0 VT0 0 IC RX Gain II C 9.2.31 RX Gain Register II (Address: 0x81Eh) M Reset PKIS[1:0]: AGC Peak Detect Current Select. Recommend PKIS[1:0[ = [00]. A PKT[1:0]: VCO Peak Detect Current Select. Recommend PKT [1:0] = [01]. DCH [1:0]: AGC Hold setting. [00]: Hold by Preamble OK. [01]: Hold by SYNC. [10]: No Hold. [11]: No Hold. VT[1:0]: AGC comparator output. RH [7:0]: Reserved for internal usage only. RSAGC [1:0]: AGC clock select. [00]: IF/4 Sep., 2014, Version 0.6 (Preliminary) 26 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC [01]: IF/2 [10]: IF [11]: 2*IF Where IF is 1Mhz for BWS=0, and 2Mhz for BWS=1. 9.2.32 RX Gain Register III (Address: 0x81Fh) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RX Gain III W R IFPK RH7 0 VRSEL RH6 0 MS RH5 0 MSCL4 RH4 0 MSCL3 RH3 0 MSCL2 RH2 0 MSCL1 RH1 0 MSCL0 RH0 0 IFPK: AGC Amplifier Current Select. Recommend IFPK = [0]. EN VRSEL: ADC reading select. [0]: Normal ADC. [1]: RSSI ADC (with AGC turn on). MS: AGC Manual scale select. [0]: RL-RH(Auto). [1]: MSCL(Manual). FI D MSCL[4:0]: AGC Manual Scale setting. RH [7:0]: RSSI Calibration High Threshold. 9.2.33 RX Gain Register IV (Address: 0x820h) R/W Bit 7 Bit 6 Bit 5 RX Gain III W R MXD RL7 0 CSS RL6 0 HPLS RL5 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MHC1 RL4 0 MHC0 RL3 1 LHC1 RL2 1 LHC0 RL1 1 XADSP RL0 0 C O N Name Reset TI A Reset L Name MXD: Reserved for internal usage only. Shall be set to [0]. M CSS: RX demodulation carrier detect select. [0]: Deselect. [1]: select. C O HPLS: High Power LNA Gain Select. Recommend HPLS = [0]. [0]: LGC is set to 6dB when in TX Mode. [1]: LGC is set to LGM[1:0]. MHC [1:0]: Reserved for internal usage only. Shall be set to [10]. IC LHC [1:0]: Reserved for internal usage only. Shall be set to [10]. M XADS: ADC input signal select. [0]: Convert internal temperature or RSS signal. [1]: Convert external voltage, A RL [7:0]: RSSI Calibration Low Threshold value. 9.2.34 RSSI Threshold Register (Address: 0x821h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RSSI Threshold W R RTH7 ADC7 0 RTH6 ADC6 0 RTH5 ADC5 0 RTH4 ADC4 0 RTH3 ADC3 0 RTH2 ADC2 0 RTH1 ADC1 0 RTH0 ADC0 0 Reset RTH [7:0]: Carrier detect threshold. ADC [8:0]: ADC output value of temperature, RSSI or external voltage measurement (read only). ADC [8:0] are located at address 0x81D and 0x821h. For normal ADC measurement with VRSEL=0 (in 0x81Fh), which include external voltage, Temp and RSSI with AGC off measurement, ADC [8] is zero. ADC input voltage= 1.2 * ADC [8:0] / 256 V. Sep., 2014, Version 0.6 (Preliminary) 27 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 9.2.35 ADC Control Register (Address: 0x822h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADC Control Reset W RSM1 0 RSM0 1 ERSS 0 FSARS 1 SYNCS 0 XADS 0 RSS 1 CDM 1 EN FSARS: ADC clock select. Recommend FSARS = [0]. [0]: 2MHz. [1]: 4MHz. TI A ERSS: end enable for RSSI measurement [0]: RSSI measurement continues until leave off RX mode. [1]: RSSI measurement will end when carrier detected and ID code word received. L RSM [1:0]: RSSI margin = RTH – RTL. Recommend RSM = [11]. [00]: 5. [01]: 10. [10]: 15. [11]: 20. SYNCS: Sync word detect select. [1]: sync word. [0]: preamble FI D XADS: ADC input signal select. [0]: Convert internal temperature or RSS signal. [1]: Convert external voltage, N RSS: Temperature/RSSI measurement select. [0]: Temperature measurement. [1]: RSSI or carrier-detect measurement. C O CDM: RSSI measurement mode. [0]: Single mode. [1]: Continuous mode. 9.2.36 Code Register I (Address: 0x823h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Code I Reset W XDS 0 MCS 0 WHTS 0 FECS 0 CRCS 0 PML2 0 PML1 1 PML0 1 M Name O XDS: VCO Modulation Data Sampling Clock selection. [0]: 8x over-sampling Clock. [1]: XCPCK Clock. C MCS: Manchester Code Enable. [0]: Disable. [1]: Enable. M IC WHTS: Data whitening (Data Encryption) select. [0]: Disable. [1]: Enable. FECS: FEC select. [0]: Disable. [1]: Enable. A CRCS: CRC select. [0]: Disable. [1]: Enable. PML [2:0]: Preamble length select. Recommend PML= [11]. [000]: 1 byte. [001]: 2 bytes. [010]: 3 bytes. [011]: 4 bytes. [100]: 5byts. [101]: 6bytes. [110]: 7bytes. [111]: 8bytes 9.2.37 Code Register II (Address: 0x824h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Code II Reset W DCL2 1 DCL1 1 DCL0 1 ETH2 0 ETH1 0 ETH0 1 PMD1 1 PMD0 1 DCL [2:0]: Demodulator DC estimation average mode. Refer to DCM (0x82Bh) for details. Sep., 2014, Version 0.6 (Preliminary) 28 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC DCL [2]: payload average mode. [0]: 128 bits average. [1]: 256 bits average. DCL [1]: For average and hold mode. [0]: 32 bits average. [1]: 64 bits average. DCL [0]: Preamble detection delay. Count from preamble detected signal. Recommend DCL0 = [1]. [0]: 4 bits for DCL1=0, 8 bits for DCL1=1. [1]: 8 bits for DCL1=0, 16 bits for DCL1=1. PMD [1:0]: Preamble pattern detection length. Recommend PMD = [10]. [00]: 0bit. [01]: 4bits. [10]: 8bits. [11]: 16bits. 9.2.38 Code Register III (Address: 0x825h) R/W Bit 7 Bit 6 Bit 5 Bit 4 W IDL 1 WS6 0 WS5 1 WS4 0 WS3 1 Bit 2 Bit 1 Bit 0 WS2 0 WS1 1 WS0 0 FI D IDL: ID code length select. Recommend IDL= [1]. [0]: 2 bytes. [1]: 4 bytes. Bit 3 EN Name Code III Reset TI A L ETH [2:0]: ID code error tolerance. Recommend ETH = [01]. [000]~[111]: 0~7 bit. WS [6:0]: Data Whitening seed setting (data encryption key). N 9.2.39 IF Calibration Register I (Address: 0x826h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IF Calibration I W R RNUM0_2 -1 RNUM0_1 -0 RNUM0_0 -0 MFBS FBCF 0 MFB3 FB3 0 MFB2 FB2 1 MFB1 FB1 1 MFB0 FB0 0 Reset C O Name M RNUM0[2:0]: sync word clock recovery manual setting. O MFBS: IF filter calibration value select. Recommend MFBS = [0]. [0]: Auto calibration value. [1]: Manual calibration value. C MFB [3:0]: IF filter manual calibration value. IC FBCF: IF filter auto calibration flag. [0]: Pass. [1]: Fail. M FB [3:0]: IF filter calibration value. MFBS= 0: Auto calibration value (AFB), MFBS= 1: Manual calibration value (MFB). A 9.2.40 IF Calibration Register II (Address: 0x827h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IF Calibration II W R PWORS -0 TRT2 -0 TRT1 -1 TRT0 FCD4 1 MRCKS FCD3 0 RNUM1_2 FCD2 0 RNUM1_1 FCD1 0 RNUM1_0 FCD0 0 Reset PWORS: TX high power setting. [0]: Disable. [1]: Enable. TRT [2:0]: TX Ramp down discharge current select. Recommand value=[000] MRCKS: Preamble detect and sync detect manual setting. [1]: manual Sep., 2014, Version 0.6 (Preliminary) 29 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC RNUM1[2:0]: sync word clock recovery manual setting. FCD [4:0]: IF filter calibration deviation from goal. 9.2.41 VCO current Calibration Register (Address: 0x828h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VCO current Calibration W R -TWORF 0 PKS -0 VCCS -0 MVCS FVCC 0 VCOC3 VCB3 1 VCOC2 VCB2 0 VCOC1 VCB1 0 VCOC0 VCB0 0 TI A Reset PKS: VCO Current Calibration Mode Select. Recommend PKS = [0]. VCOC [3:0]: VCO current manual calibration value. FI D TWORF: TWOR interrupt flag. C O N FVCC: VCO current auto calibration flag. [0]: Pass. [1]: Fail. VCB [3:0]: VCO current calibration value. MVCS= 0: Auto calibration value (VCB). MVCS= 1: Manual calibration value (VCOC). EN VCCS: Reserved for internal usage only. Shall be set [0]. MVCS: VCO current calibration value select. Recommend MVCS = [0]. [0]: Auto calibration value. [1]: Manual calibration value. L Name 9.2.42 VCO Single band Calibration Register I (Address: 0x829h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VCO Single band Calibration I W R DCD1 -1 DCD0 -1 DAGS -0 PDV -1 MVBS VBCF 0 MVB2 VB2 1 MVB1 VB1 0 MVB0 VB0 0 Bit 2 Bit 1 Bit 0 M Name Reset C O DCD [1:0]: VCO Deviation Calibration Delay. Recommend DCD = [01]. Delay time = PDL (Delay Register I, 0x818h) × (DDC + 1 ). IC DAGS: DAG Calibration Value Select. Recommend DAGS = [0]. [0]: Auto calibration value. [1]: Manual calibration value. PDV: Reserved for internal usage only. Shall be set [0]. A M MVBS: VCO bank calibration value select. Recommend MVBS = [0]. [0]: Auto calibration value. [1]: Manual calibration value. MVB [2:0]: VCO band manual calibration value. VBCF: VCO band auto calibration flag. [0]: Pass. [1]: Fail. VB [2:0]: VCO bank calibration value. MVBS= 0: Auto calibration value (AVB). MVBS= 1: Manual calibration value (MVB). 9.2.43 VCO Single band Calibration Register II (Address: 0x82Ah) Name R/W Bit 7 Sep., 2014, Version 0.6 (Preliminary) Bit 6 Bit 5 Bit 4 30 Bit 3 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC VCO Single band Calibration II Reset W DAMV1 DAMV0 VTH2 VTH1 VTH0 VTL2 VTL1 VTL0 1 0 1 1 1 0 1 1 TI A VTH [2:0]: RF AGC upper threshold level setting [000]: VDD_A – 0.6V. [001]: VDD_A – 0.7V. [010]: VDD_A – 0.8V. [011]: VDD_A – 0.9V [100]: VDD_A – 1.0V. [101]: VDD_A – 1.1V. [110]: VDD_A – 1.2V. [111]: VDD_A – 1.3V VDD_A is on chip analog regulator output voltage 9.2.44 Battery detect Register (Address: 0x82Bh) R/W Bit 7 Bit 6 Bit 5 Bit 4 Battery detect W R RGS -0 RGV1 RGV1 0 RGV0 RGV0 0 PACTL BDF 0 RGS: VDD_D voltage setting in Sleep mode. [0]: 1.8V. [1]: 1.6V. Bit 3 Bit 2 Bit 1 Bit 0 BVT2 BVT2 0 BVT1 BVT1 1 BVT0 BVT0 1 BDS BDS 0 FI D Name EN VTL [2:0]: RX AGC lower threshold level setting [000]: 0.1V. [001]: 0.2V. [010]: 0.3V. [011]: 0.4V. [100]: 0.5V. [101]: 0.6V. [110]: 0.7V. [111]: 0.8V Reset L DMV [1:0]: Demodulator D/A Voltage Range Select. Recommend DMV = [10]. [00]: 1/32*1.2. [01]: 1/16*1.2. [10]: 1/8*1.2. [11]: 1/4*1.2. C O N RGV [1:0]: VDD_D and VDD_A voltage setting in non-Sleep mode. Recommend RGV = [11]. [00]: 1.9V. [01]: 1.8V. [10]: 1.7V. [11]: 1.6V. PACTL: Reserved for internal usage only. Shall be set to [0]. M BVT [2:0]: Battery voltage detect threshold. [000]: 1.8V. [001]: 1.9V. [010]: 2.0V. [011]: 2.1V. [100]: 2.2V. [101]: 2.3V. [110]: 2.4V. [111]: 2.5V. O BDS: Battery detect enable. [0]: Disable. [1]: Enable. It will be clear after battery detection done. C BDF: Battery detection flag. [0]: Battery voltage less than threshold. [1]: Battery voltage greater than threshold. IC Refer to chapter 19 for details. 9.2.45 TX test Register (Address: 0x82Ch) M Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W IFBC1 0 IFBC0 0 TXCS 0 PAC1 1 PAC0 0 TBG2 1 TBG1 1 TBG0 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A TX test Reset RMP [1:0]: PA ramp up timing scale. Delay scales 2^(RMP [1:0]) TXCS: TX Current Setting. PAC [1:0]: PA Current Setting. TBG [2:0]: TX Buffer Setting. 9.2.46 Rx DEM test Register I (Address: 0x82Dh) Name R/W Bit 7 Sep., 2014, Version 0.6 (Preliminary) Bit 6 Bit 5 31 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Rx DEM test I Reset W DMT 0 DCM1 1 DCM0 1 MLP1 0 MLP0 0 SLF2 1 SLF1 0 SLF0 0 DMT: Reserved for internal usage only. Shall be set to [0]. MLP [1:0]: Reserved for internal usage only. Shall be set to [000]. SLF [2:0]: Reserved for internal usage only. Shall be set to [111]. 9.2.47 Rx DEM test Register II (Address: 0x82Eh) R/W Bit 7 Bit 6 Bit 5 Bit 4 Rx DEM test II Reset W DCV7 1 DCV6 0 DCV5 0 DCV4 0 Bit 3 Bit 2 Bit 1 Bit 0 DCV2 0 DCV1 0 DCV0 0 EN Name TI A L DCM [1:0]: Demodulator DC estimation mode. [00]: Fix mode (For testing only). DC level is set by DCV [7:0]. [01]: Preamble hold mode. DC level is preamble average value. [10]: Average and hold mode. DC level is the average value hold about 8 bit data rate later after preamble is detected. [11]: Payload average mode (For internal usage). DC level is payload data average. DCV3 0 FI D DCV [7:0]: Demodulator fix mode DC value. Recommend DCV = [0x80]. 9.2.48 Charge Pump Current Register (Address: 0x82Fh) R/W Bit 7 Bit 6 Bit 5 Charge Pump Current Reset W CPM3 1 CPM2 1 CPM1 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPM0 1 CPT3 1 CPT2 1 CPT1 1 CPT0 1 C O N Name CPM [3:0]: Charge Pump Current Setting for VM loop. Recommend CPM = [1111]. Charge pump current = (CPM + 1) / 16 mA. M CPT [3:0]: Charge Pump Current Setting for VT loop. Recommend CPT = [1111]. Charge pump current = (CPT + 1) / 16 mA. R/W Crystal test Reset W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PRS 0 QDS 0 QLIM 0 DBD 0 XCC1 0 XCC0 1 XCP1 0 XCP0 1 IC C Name O 9.2.49 Crystal test Register (Address: 0x830h) PRS: Limiter amplifier discharge manual select. Recommend PRS =[0]. M QDS: VDD_A Quick Discharge Select. [0]: Disable. [1]: Enable. A QLIM: quick charge select for IF limiter amp. [0]: disable. [1]: enable (QLIM fall down delay 10us) DBD: Reserved for internal usage only. Shall be set to [0]. XCC[1:0]: Crystal current setting. Shall be set to [01]. XCP[1:0]: Crystal regulating couple setting. Shall be set to [01]. 9.2.50 PLL test Register (Address: 0x831h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLL test Reset W MDEN 0 PMPE 1 PRIC1 1 PRIC0 0 PRRC1 1 PRRC0 0 SDPW 0 NSDO 0 Sep., 2014, Version 0.6 (Preliminary) 32 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC MDEN : Use for Manual VCO Calibration. Shall be set to [0]. PMPE: Reserved for internal usage only. Shall be set to [1]. PRIC[1:0]: Reserved for internal usage only. Shall be set to [01]. PRRC[1:0]: Reserved for internal usage only. Shall be set to [01]. NSDO: Reserved for internal usage only. Shall be set to [1]. 9.2.51 VCO test Register I (Address: 0x832h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 W DEVGD2 0 DEVGD1 0 DEVGD0 0 TLB1 1 TLB0 1 Bit 2 Bit 1 Bit 0 RLB1 0 RLB0 1 MGS 0 EN Name VCO test I Reset TI A L SDPW: Reserved for internal usage only. Shall be set to [0]. DEVGD [2:0]: Sigma Delta Modulator Data Delay Setting. Recommend DEVGD = [000]. FI D TLB [1:0]: Reserved for internal usage only. Shall be set to [11]. MGS: IGC Manual setting select. [0]: Auto. [1]: Manual. C O 9.2.52 VCO test Register II (Address: 0x833h) N RLB [1:0]: Reserved for internal usage only. Shall be set to [00]. Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VCO test II Reset W CHD3 0 CHD2 1 CHD1 0 CHD0 1 RFT3 0 RFT2 0 RFT1 0 RFT0 0 M CHD [3:0]: Channel Frequency Offset for Deviation Calibration. Offset channel number = +/- (CHD + 1). O RFT [3:0]: RF analog pin configuration for testing. Recommend RFT= [0000]. Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W MPDT5 1 MPDT4 0 MPDT3 0 MPDT2 0 MPDT1 0 MPDT0 0 --- LIMC 1 IC VCO test II Reset C 9.2.53 IFAT Register (Address: 0x834h) M MPDT[5:0]: TX ramp up/down scale select. A LIMC: Reserved for internal usage only. Shall be set to [1]. 9.2.54 RFT Test Register I (Address: 0x835h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RFT1 Reset W ASMV2 0 ASMV1 0 ASMV0 0 SDMS 1 OLM 0 CPCS 1 CPH 1 CPS 1 AMSV [2:0]: TX Ramp up/Ramp down Timing Select. [000]: 4us, [001]: 8us. [010]: 12us. [011]: 16us. [100]: 20us, [101]: 24us. [110]: 28us. [111]: 32us. SDMS: Reserved for internal usage only. Shall be set to [1]. OLM : Open Loop Modulation Enable. Shall be set to [0]. [0]: Disable. [1]: Enable. Sep., 2014, Version 0.6 (Preliminary) 33 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC CPCS: Charge Pump Current Select. Shall be set to [0]. [0]: Use CPM for TX, CPT for RX. [1]: Use CPTX for TX, CPRX for RX. CPH: Charge Pump High Current. Shall be set to [0]. [0]: Normal. [1]: High. 9.2.55 RFT Test Register II (Address: 0x836h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 RFT2 W R ---- CRS3 CRSR3 0 CRS2 CRSR2 1 CRS1 CRSR1 0 CRS0 CRSR0 0 Reset SRS [2:0]: RSSI voltage curve slope fine time setting. 9.2.56 RFT Test Register III (Address: 0x837h) R/W Bit 7 Bit 6 Bit 5 RFT3 W R --0 STMP -0 STM5 STMR5 1 Bit 0 SRS0 SRSR0 0 Bit 3 Bit 2 Bit 1 Bit 0 STM3 STMR3 0 STM2 STMR2 0 STM1 STMR1 0 STM0 STMR0 0 C O Reset Bit 4 Bit 1 SRS1 SRSR1 0 STM4 STMR4 0 N Name FI D CRS [2:0]: RSSI voltage offset fine trim setting. Bit 2 SRS2 SRSR2 1 EN Name TI A L CPCS: Charge Pump Current Select. Shall be set to [0]. [0]: Use CPM for TX, CPT for RX. [1]: Use CPTX for TX, CPRX for RX. STMP: Temp voltage ADC reading select. [0]: 1 scale / degree C. [1]: 2 scale/degree C. M STM [5:0]: ADC voltage fine trim setting. R/W RFT4 W R Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ---- DVI1 -0 DVI0 -0 FBG4 FBGR4 1 FBG3 FBGR3 0 FBG2 FBGR2 0 FBG1 FBGR1 0 FBG0 FBGR0 0 IC Reset Bit 7 C Name O 9.2.57 RFT Test Register IV (Address: 0x838h) M DVI[1:0]: Reserved for internal usage FBG[4:0]: Bandgap voltage SPI fine trim setting. A 9.2.58 RFT Test Register V (Address: 0x839h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RFT5 W R FGC1 FGCR1 1 FGC0 FGCR0 1 CTR5 CTRR5 1 CTR4 CTRR4 0 CTR3 CTRR3 0 CTR2 CTRR2 0 CTR1 CTRR1 0 CTR0 CTRR0 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset FGC[1:0]: BPF fine gain control. CTR [5:0]: ADC voltage SPI fine trim setting. 9.2.59 Channel Index Register (Address: 0x83Ah) Name R/W Bit 7 Sep., 2014, Version 0.6 (Preliminary) Bit 6 Bit 5 34 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Channel Index Reset W --- -0 CHIDX5 1 CHIDX4 0 CHIDX3 0 CHIDX2 1 CHIDX1 0 CHIDX0 1 Bit 3 Bit 2 Bit 1 Bit 0 CHIDX[5:0]: Whitening seed setting for BLE mode(BLE_ON=1). 9.2.60 CRC Register 1 (Address: 0x83Bh) CRC1 Reset W Bit 7 Bit 6 Bit 5 Bit 4 CRCINIT23 CRCINIT22 CRCINIT21 CRCINIT20 CRCINIT19 CRCINIT18 CRCINIT17 CRCINIT16 0 1 0 1 0 1 0 1 L R/W CRCINIT[23:0]: CRC initial value for TX CRC-24bits encoder. 9.2.61 CRC Register 2 (Address: 0x83Ch) W Bit 7 Bit 6 Bit 5 Bit 4 9.2.62 CRC Register 3 (Address: 0x83Dh) R/W Bit 7 Bit 6 Bit 5 CRC3 Reset W CRCINIT7 0 CRCINIT6 1 CRCINIT5 0 R/W W Bit 1 Bit 7 Bit 6 Bit 0 CRCINIT8 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CRCINIT4 1 CRCINIT3 0 CRCINIT2 1 CRCINIT1 0 CRCINIT0 1 Bit 3 Bit 2 Bit 1 Bit 0 C O 9.2.63 CRC Register 4 (Address: 0x83Eh) CRC4 Reset Bit 2 N Name Name Bit 3 CRCINIT15 CRCINIT14 CRCINIT13 CRCINIT12 CRCINIT11 CRCINIT10 CRCINIT9 0 1 0 1 0 1 0 EN R/W CRC2 Reset FI D Name TI A Name Bit 5 Bit 4 CRCINR23 CRCINR22 CRCINR21 CRCINR20 CRCINR19 CRCINR18 CRCINR17 CRCINR16 0 1 0 1 0 1 0 1 M CRCINR[23:0]: CRC initial value for RX CRC-24bits decoder. 9.2.64 CRC Register 5 (Address: 0x83Fh) W Bit 7 Bit 6 O R/W CRC5 Reset Bit 5 Bit 4 Bit 3 Bit 2 CRCINR15 CRCINR14 CRCINR13 CRCINR12 CRCINR11 CRCINR10 0 1 0 1 0 1 IC C Name Bit 1 Bit 0 CRCINR9 0 CRCINR8 1 9.2.65 CRC Register 6 (Address: 0x840h) M Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W CRCINR7 0 CRCINIR6 1 CRCINIR5 0 CRCINIR4 1 CRCINIR3 0 CRCINIR2 1 CRCINIR1 0 CRCINIR0 1 A CRC6 Reset R/W 9.2.66 VCO Single band Calibration Register I (Address: 0x841h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VCO Single band Calibration III W R DAGM7 ADAG7 1 DAGM6 ADAG6 0 DAGM5 ADAG5 0 DAGM4 ADAG4 0 DAGM3 ADAG3 0 DAGM2 ADAG2 0 DAGM1 ADAG1 0 DAGM0 ADAG0 0 Reset DAGM [7:0]: DAG Manual Setting Value. Recommend DAGM = [0x80]. ADAG [7:0]: Auto DAG Calibration Value. Sep., 2014, Version 0.6 (Preliminary) 35 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 9.2.67 VCO deviation Calibration Register I (Address: 0x842h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VCO Deviation I W R DEVS3 DEVA7 DEVS2 DEVA6 DEVS1 DEVA5 DEVS0 DEVA4 DAMR_M DEVA3 VMTE_M DEVA2 VMS_M DEVA1 MSEL DEVA0 0 1 1 1 0 0 0 0 Reset DEVS [3:0]: Deviation Output Scaling. Recommend DEVS = [0011]. TI A L DAMR_M: DAMR Manual Enable. Recommend DAMR_M = [0]. [0]: Disable. [1]: Enable. VMS_M: VM Manual Enable. Recommend VMS_M = [0]. [0]: Disable. [1]: Enable. MSEL: VMS, VMTE and DAMR control select. Recommend MSEL = [0]. [0]: Auto control. [1]: Manual control. FI D DEVA [7:0]: Deviation Output Value. MVDS (0x841h)= 0: Auto calibration value ((DEVC / 8) × (DEVS + 1)), MVDS (0x841h)= 1: Manual calibration value (DEVM [6:0]). EN VMTE_M: VMT Manual Enable. Recommend VMTE_M = [0]. [0]: Disable. [1]: Enable. N 9.2.68 VCO deviation Calibration Register II (Address: 0x843h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VCO Deviation II W R MVDS ADEV7 0 DEVM6 ADEV6 0 DEVM5 ADEV5 1 DEVM4 ADEV4 0 DEVM3 ADEV3 1 DEVM2 ADEV2 0 DEVM1 ADEV1 0 DEVM0 ADEV0 0 Reset C O Name M MVDS: VCO Deviation Calibration Select. Recommend MVDS = [0]. [0]: Auto calibration value. [1]: Manual calibration value. O DEVM [6:0]: VCO Deviation Manual Calibration Value. ADEVC [7:0]: VCO Deviation Auto Calibration Value. R/W Bit 7 IC Name C 9.2.69 VCO deviation Calibration Register III (Address: 0x844h) W/R VMG7 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VMG6 0 VMG5 0 VMG4 0 VMG3 0 VMG2 0 VMG1 0 VMG0 0 M VCO Deviation III Reset VMG [7:0]: VM Center Value for Deviation Calibration. Recommend VMG [7:0] = [0x80]. A 9.2.70 ADC Control Register (Address: 0x845h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADC Reset W AVSEL1 1 AVSEL0 0 MVSEL1 1 MVSEL0 0 RADC 0 FPS2 0 FPS1 0 FPS0 0 AVSEL [1:0]: ADC average times (for Carrier / temeperature sensor / external ADC). Recommend AVSEL = [10]. [00]: No average. [01]: Average 2 times. [10]: Average 4 times. [11]: Average 8 times. MVSEL [1:0]: ADC average times (for VCO calibration and RSSI ). Recommend MVSEL = [01]. [00]: Average 8 times. [01]: Average 16 times. [10]: Average 32 times. [11]: Average 64 times. RADC: ADC read out average mode. [0]: 1, 2, 4, 8 average mode. The average number is according to the setting of AVSEL in RX Gain Register (IV). Sep., 2014, Version 0.6 (Preliminary) 36 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC [1]: 8, 16, 32, 64 average mode. The average number is according to the setting of MVSEL in RX Gain Register (IV) 7 1.4 6 1.3 5 1.2 4 1.1 3 0.75 2 0.7 1 0.65 0 0.6 GDR=1. FPS[2:0] BT 7 0.7 6 0.65 5 0.6 4 0.55 3 X 2 X 1 X 0 X 9.2.71 WOT Register (Address: 0x846h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 WOT Reset W -0 SPSS 0 WMODE 0 WN1 0 WN0 0 Bit 2 Bit 1 Bit 0 -- -- -- EN . SPSS: Mode back select in WOT mode. [0]:Standby mode. [1]: PLL mode. TI A GDR=0. FPS[2:0] BT L FPS[2:0]: Gaussian filter BT setting. FI D WMODE: Wakeup mode select. [0]:WOR [1]:WOT WN[1:0]: WOT Wake up times. N 9.2.72 Channel Group Register I (Address: 0x847h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CHGL Reset R/W CHGL7 0 CHGL6 0 CHGL5 1 CHGL4 0 CHGL3 1 CHGL2 0 CHGL1 0 CHGL0 0 C O Name CHGL [7:0]: PLL channel group low boundary setting. M 9.2.73 Channel Group Register II (Address: 0x848h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CHGH Reset R/W CHGH7 0 CHGH6 1 CHGH5 0 CHGH4 1 CHGH3 0 CHGH2 0 CHGH1 0 CHGH0 0 O Name C CHGH [7:0]: PLL channel group high boundary setting. A M IC PLL frequency is divided into 3 groups: Channel Group1 0 ~ CHGL-1 Group2 CHGL ~ CHGH-1 Group3 CHGH ~ 255 Note: Each group needs its own VCO current, bank and deviation calibration. Use the same calibration value for the frequency in the same group. 9.2.74 Charge Pump Current Register II (Address: 0x849h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPC II Reset W CPTX3 0 CPTX2 0 CPTX1 1 CPTX0 0 CPRX3 0 CPRX2 0 CPRX1 1 CPRX0 0 CPTX [3:0]: Charge Pump Current Setting for TX mode. Recommend CPTX = [0010]. Charge pump current = (CPTX + 1) / 16 mA. CPRX [3:0]: Charge Pump Current Setting for RX mode. Recommend CPRX = [0010]. Charge pump current = (CPRX + 1) / 16 mA. Sep., 2014, Version 0.6 (Preliminary) 37 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 9.2.75 VCO Modulation Delay Register (Address: 0x84Ah) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VCO Delay Reset W -0 INTPRC 0 DEVFD2 1 DEVFD1 0 DEVFD0 1 DEVD2 0 DEVD1 0 DEVD0 0 L INTPRC: Internal PLL loop filter resistor and capacitor select. [0]: disable. [1]: enable TI A DEVFD [2:0]: VCO Modulation Data Delay by 8x over-sampling Clock. Recommend DEVFD = [101]. DEVD [2:0]: VCO Modulation Data Delay by XCPCK Clock. Recommend DEVD = [000]. 9.2.76 Internal Capacitance Register (Address: 0x84Bh) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 INTC Reset W VRPL1 0 VRPL0 0 VCOSC5 0 VCOSC4 1 VCOSC3 0 Bit 1 Bit 0 VCOSC1 0 VCOSC0 0 FI D VRPL [1:0]: internal PLL loop filter resistor value select. [00]: 500 ohm. [01]: 666 ohm. [10]: 1 K ohm. [11]: 2K ohm. Bit 2 VCOSC2 1 EN Name VCOSC[5:0]: Reserved for internal usage N 9.2.77 RX Detection Register (Address: 0x84Ch) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DET W R DC_SEL RXDCS PREDN2 PREDN1 PREDN0 PREUP2 PREUP1 PREUP0 0 1 0 Reset 0 C O Name 0 1 DCOUT[7:0] 0 0 M DC_SEL: Initial DC value select when sync word ok.[0]: DC set by last pattern DC [1]: DC set by 0x82Eh DC value. RXDCS: RX dc average clock setting. Recommed RXDCS=[0] O PREDN[2:0]: Preamble detect low threshold setting. C PREUP[2:0]: Preamble detect high threshold setting. IC DCOUT [7:0]: Read demodulator DC value. 9.2.78 BLE Header Register 0 (Address: 0x84Dh) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HEADER0 W R TXHDR15 RXHDR15 0 TXHDR14 RXHDR14 0 TXHDR13 RXHDR13 0 TXHDR12 RXHDR12 0 TXHDR11 RXHDR11 0 TXHDR10 RXHDR10 0 TXHDR9 RXHDR9 0 TXHDR8 RXHDR8 0 A M Name Reset TXHDR[15:0]: TX header setting for BLE mode. RXHDR[15:0]: RX header setting for BLE mode. 9.2.79 BLE Header Register 1 (Address: 0x84Eh) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HEADER1 W R TXHDR7 RXHDR7 0 TXHDR6 RXHDR6 0 TXHDR5 RXHDR5 0 TXHER4 RXHDR4 0 TXHDR3 RXHDR3 0 TXHDR2 RXHDR2 0 TXHDR1 RXHDR1 0 TXHDR0 RXHDR0 0 Reset Sep., 2014, Version 0.6 (Preliminary) 38 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 9.2.80 ID Register 0 (Address: 0x84Fh) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID0 Reset W/R ID31 0 ID30 0 ID29 0 ID28 0 ID27 0 ID26 0 ID25 0 ID24 0 9.2.81 ID Register 1 (Address: 0x850h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ID1 Reset W/R ID23 0 ID22 0 ID21 0 ID20 0 ID19 0 Bit 2 Bit 1 Bit 0 ID18 0 ID17 0 ID16 0 TI A Name L ID[31:0]: ID Data. Once this address is accessed, ID Data is input/output in sequence corresponding to Write or Read. 9.2.82 ID Register 2 (Address: 0x851h) R/W Bit 7 Bit 6 Bit 5 ID2 Reset W/R ID15 0 ID14 0 ID13 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID11 0 ID10 0 ID9 0 ID8 0 FI D Name EN ID[31:0]: ID Data. Once this address is accessed, ID Data is input/output in sequence corresponding to Write or Read. ID12 0 C O 9.2.83 ID Register 3 (Address: 0x852h) N ID[31:0]: ID Data. Once this address is accessed, ID Data is input/output in sequence corresponding to Write or Read. Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID3 Reset W/R ID7 0 ID6 0 ID5 0 ID4 0 ID3 0 ID2 0 ID1 0 ID0 0 M ID[31:0]: ID Data. Once this address is accessed, ID Data is input/output in sequence corresponding to Write or Read. R/W R Bit 7 DID31 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DID30 0 DID29 1 DID28 0 DID27 1 DID26 0 DID25 1 DID24 0 IC DID0 Reset C Name O 9.2.84 DID Register 0 (Address: 0x853h) DID[31:0]: Device ID. M 9.2.85 DID Register 1 (Address: 0x854h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DID1 Reset R DID23 1 DID22 0 DID21 0 DID20 0 DID19 0 DID18 0 DID17 0 DID16 1 A Name DID[31:0]: Device ID. 9.2.86 DID Register 2 (Address: 0x855h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DID2 Reset R DID15 0 DID14 0 DID13 0 DID12 0 DID11 0 DID10 1 DID9 0 DID8 1 DID[31:0]: Device ID. Sep., 2014, Version 0.6 (Preliminary) 39 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 9.2.87 DID Register 3 (Address: 0x856h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DID3 Reset R DID7 1 DID6 0 DID5 1 DID4 0 DID3 0 DID2 0 DID1 0 DID0 1 DID[31:0]: Device ID. 9.2.88 EXT Register 1 (Address: 0x857h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXT1 Reset W/R --- XEC 1 BREV 0 BGS 0 LIMB 0 ADCCS 0 BOD 0 REGR 0 FI D 9.2.89 EXT Register 2 (Address: 0x858h) TI A EN XEC: Reserved. Should set to [1] BREV: data byte reversion for TX data in the air [0]: normal. [1]: reverted. BGS: Reverved should set to [0] LIMB: Reserved. Should set to [0] ADCCS: Reserved. Should set to [0] BOD: regulator input low voltage detect selection. [0]: disable. [1]: enable. REGR: pin7 “VDD_R” driver voltage output enable for 12bit ADC [0]: disable. [1]: enable. Output voltage is equal to pin8 “VDD_A” L Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXT2 Reset W VTRB3 0 VTRB2 0 VTRB1 0 VTRB0 0 VMRB3 0 VMRB2 0 VMRB1 0 VMRB0 0 C O N Name VTRB[3:0]: Reserved. Should set to [0000] VMRB[3:0]: Reserved. Should set to [0000] M 9.2.90 EXT Register 3 (Address: 0x859h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXT3 Reset W -0 IFAS CGC IWA IWC LBG 0 0 0 0 0 VCS 0 VCSW 0 C O Name [Fcsck = 64Mhz]: GRC=3, CGC=1. A M IC IFAS: Reserved for internal usage only. CGC: Clock generation setting. [Fcsck = 32Mhz]: GRC=7, CGC=0. IWA: RXFE new IFAMP path gain IWC: Reserved for internal usage only. Shall be set to [0]. LBG: Reserved for internal usage only. VCS: Reserved. VCSW: Reserved. 9.2.91 ADC Control Register (Address: 0x85Ah) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADCCTL W R BUFS -0 CKS -1 --0 MODE MODE 0 MVS2 MVS2 0 MVS1 MVS1 0 MVS0 MVS0 0 ADCE ADCE 0 Reset BUFS: input buffer select for 12 bit ADC. [0]: disable. [1]: enable. CKS: ADC clock selected. [0]: 1 MHz [1]: 4 MHz Sep., 2014, Version 0.6 (Preliminary) 40 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC MODE: ADC measurement mode. [0]: Single mode. [1]: Continuous mode. MVS [1:0]: ADC average times (for VCO calibration and RSSI ). [00]: Average 8 times. [01]: Average 16 times. [10]: Average 32 times. [11]: Average 64 times. 9.2.92 ADC Value Register 1 (Address: 0x85Bh) R/W ADCAVG1 W R Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TI A Name L ADCE: ADC measurement enable ADCIE -- -- -- ADIVL ADCYC ENADC DTMP MVADC11 0 MVADC10 -- MVADC9 -- MVADC8 -- ADC11 0 ADC10 0 ADC9 0 ADC8 0 EN ADCIE : 12-bits interrupt enable. [0]: disable. [1]: enable. FI D ADIVL: Reserved. Should set to [0] ADCYC: Reserved. Should set to [0] ENADC: Enable ADC. ADC [11:0]: ADC output value C O MVADC [11:0]: Moving average ADC output value N MVADC [11:0]: Moving average ADC output value 9.2.93 ADC Value Register 2 (Address: 0x85Ch) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADCAVG2 Reset R MVADC7 -- MVADC6 -- MVADC5 -- MVADC4 -- MVADC3 -- MVADC2 -- MVADC1 -- MVADC0 -- M Name O MVADC [11:0]: Moving average ADC output value 9.2.94 ADC Value Register 3 (Address: 0x85Dh) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADC7 -- ADC6 -- ADC5 -- ADC4 -- ADC3 -- ADC2 -- ADC1 -- ADC0 -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 C Name R IC ADCAVG3 Reset M ADC [11:0]: ADC output value 9.2.95 Timer Interval Register 1 (Address: 0x85Eh) R/W W/R A Name TMRITV1 Reset Bit 7 Bit 6 Bit 5 TMR_ITV[15:8] 0 0 0 0 0 TMR_ITV[15:0]: Timer interval setting. Timer interval can be set to be: TMRCKS[1:0] = 00: 0.15625 ms ~ 10.24 s TMRCKS[1:0] = 01: 0.3125 ms ~ 20.48 s TMRCKS[1:0] = 10: 0.625 ms ~ 40.96 s TMRCKS[1:0] = 11: 1.25 ms ~ 81.92 s Sep., 2014, Version 0.6 (Preliminary) 41 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 9.2.96 Timer Interval Register 2 (Address: 0x85Fh) Name R/W TMRITV2 Reset W/R Bit 7 Bit 6 Bit 5 Bit 4 0 0 0 0 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 TMR_ITV[7:0] 0 TMR_ITV[15:0]: Timer interval setting. Timer interval can be set to be: 9.2.97 Timer Wake On Radio Register 0 (Address: 0x860h) R/W TMRWOR0 Reset W/R Bit 7 Bit 6 Bit 5 Bit 4 0 0 0 0 -- R/W TMRWOR1 Reset Bit 7 Bit 6 Bit 5 -- -- 0 0 W/R TMRWORS Bit 1 Bit 0 0 0 0 Bit 3 Bit 2 Bit 1 Bit 0 TMR_OFS4 TMR_OFS3 TMR_OFS2 TMR_OFS1 TMR_OFS0 0 0 0 0 Bit 2 Bit 1 0 C O TMRWORS: Timer WOR / WOT selection. [0]: WOR [1]: WOT Bit 4 Bit 2 N 0 0 FI D 9.2.98 Timer Wake On Radio Register 1 (Address: 0x861h) Name Bit 3 EN Name TI A L TMRCKS[1:0] = 00: 0.15625 ms ~ 10.24 s TMRCKS[1:0] = 01: 0.3125 ms ~ 20.48 s TMRCKS[1:0] = 10: 0.625 ms ~ 40.96 s TMRCKS[1:0] = 11: 1.25 ms ~ 81.92 s TMR_OFS[4:0]: Interrupt offset for 16-bits Timer. 9.2.99 Timer Control Register (Address: 0x862h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TMRCTL W R TMRON -0 TMRIE TMRIE 0 TMRIF TMRIF TMRCOR -- TMRWOR -- 0 0 0 O TMRCKS[1:0] TMRCKS[1:0] 0 0 Bit 0 TMR_CE TMR_CE 0 C Reset M Name A M IC TMRON: Turn on TMR. TMRIE: Timer Interrupt Enable. [0]: Disable. [1]: Enable. TMRIF: Timer Interrupt Flag. (Write “1” to clear) TMRCOR : Timer CLK re-correct when sync. [0]: disable. [1]: enable TMRWOR: Timer WOR function enable. [0]: Disable. [1]: Enable. TMRCKS[1:0]: Select Timer Source Clock [00]: 6.4 kHz [01]: 3.2 kHz [10]: 1.6 kHz [11]: 0.8 kHz TMR_CE: Start Timer counting. [0]: Stop. [1]: Start. Sep., 2014, Version 0.6 (Preliminary) 42 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 9.2.100 Power Control Register 0 (Address: 0x863h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWRCTL0 Reset W CBG2 CBG1 CBG0 PDNS STS ENDL2 ENDL1 ENDL0 0 0 0 1 0 0 0 0 9.2.101 Power Control Register 1 (Address: 0x864h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PWRCTL1 Reset W EBOD ENAV QDSA ENDV QDSD 1 0 1 1 0 Bit 1 Bit 0 CEL SVREF CELA 0 0 0 C O N FI D EBOD: Reserved for internal usage. ENAV: REGOA and REGOS connection. QDSA: quick discharge select for REGOA. ENDV: REGOA is connected to REGOD. QDSD: quick discharge select for REGOD. CEL: Digital voltage select in standby mode. Recommend CEL = [0]. SVREF: Reserved for internal usage. Recommend SVREF = [0]. CELA: Reserved for internal usage. PM mode: Low power operation select. MCU STOP PM1(idle) ENAV=1, QDSA=0, ENDV=1, QDSD=0 PM2(sleep) ENAV=0, QDSA=1, ENDV=1, QDSD=0 PM3(deep sleep) ENAV=0, QDSA=1, ENDV=0, QDSD=1 Bit 2 EN Name TI A L CBG[2:0]: Reserved for internal usage. PDNS: Power manager to turn on REGOD Recommend PDNS = [0] STS: Reserved for internal usage only. Shall be set to [0]. ENDL[2:0]: Reserved for internal usage only 9.2.102 Power Control Register 2 (Address: 0x865h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W RTCPUNIE -- -- RCR1 RCR0 RGC1 RGC0 RCHC 0 -- -- 0 0 0 1 0 O M Name PWRCTL2 Reset IC C RTCPUNIE: Reserved for internal usage. Shall be set to [0]. RCR[1:0]: Reserved for internal usage. RGC[1:0]: Low power band-gap current select. Recommend RGC = [01] RCHC: Reserved for internal usage. 9.2.103 Power Control Register 3 (Address: 0x866h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWRCTL3 Reset W MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 0 0 0 0 0 0 0 0 A M Name MR[7:0]: Reserved for internal usage. 9.2.104 Power Control Register 4 (Address: 0x867h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWRCTL4 Reset W MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 0 0 0 0 0 0 0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MS[7:0]: Reserved for internal usage. 9.2.105 DC_SHIFT(Address: 0x868h) Name R/W Bit 7 Sep., 2014, Version 0.6 (Preliminary) 43 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC DCSFT Reset dc_shift[7:0] W/R 0 1 0 1 0 1 0 0 Bit 1 Bit 0 0 0 dc_shift [7:0]: DC average by ID initial dc value shift setting. (NOTE): DC_SHIFT[7] is signed bit. 9.2.106 TX_5DLY(Address: 0x869h) Bit 6 Bit 5 TX5DY Reset W HDRSW EARTS EACKS 0 0 0 Bit 4 Bit 3 0 0 TX_5DLY[4:0] HDRSW: switch header length [1]: 6 bits [0]: 5 bits EARTS: Auto resend ( EARTS=1  TX) EACKS: Auto ack ( EACKS=1  RX) TX_5DLY [4:0]: TX data output delay timing after PDN_TX enable. 9.2.107 ACKRT (Address: 0x87Ch) Name R/W Bit 7 Bit 6 Bit 5 ACKRT Reset W -0 -0 0 Bit 4 0 Bit 3 Bit 2 Bit 1 Bit 0 0 1 FI D LL_TIME_OUT[5:0] 1 0 0 Timeout = 20us x (1+LL_TIME_OUT) A M IC C O M C O N LL_TIME_OUT[5:0]: RX timeout register, Bit 2 L Bit 7 TI A R/W EN Name Sep., 2014, Version 0.6 (Preliminary) 44 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 10.SOC Architectural Overview L A8105 microcontroller is instruction set compatible with the industry standard 8051. Besides FSK/GFSK RF transceiver, A8105 2 integrates many features, three 8/16bit counters/timers, watchdog timer, RTC, UART, SPI interface, I C interface, 2 channels PWM, 8 channels ADC and battery detector, The interrupt controller is extended to support 6 interrupt sources; watchdog timer, 2 RTC, SPI, I C, ADC and RF. A8105 includes TTAG (2-wire) debug circuitry that provides full time, real-time, in-circuit debugging. 10.1 Pipeline 8051 CPU 1 2 3 Number of instructions 24 38 29 4 5 6 11 8 1 FI D Clock to Execute EN TI A A8105 microcontroller has pipelined RSIC architecture 10 times faster compared to standard 8051 architecture. The pipeline TM 8051 is fully compatible with the MCS-51 instruction set. User can use standard 8051 assemblers and compilers to develop software. The pipelined architecture 8051 has greatly increases its instruction throughput over the standard 8051 architecture. A8105 has a total of 110 instructions. The table below shows the total number of instructions that require each execution time. For more detail information of instruction, please refer Table 10.1. 10.2 Memory Organization The memory organization of A8105 is similar to the standard 8051. The memory organization is shown as figure 10.1 C O 0x3FFF 2KBytes Data Storage (In-System programmable in 512 bytes sector) M 0x3800 0x37FF External Data address space N Program /Data memory (FLASH) O C IC M A 0x0000 0xFF Special Function Registers Upper 128 RAM (Indirect Adressing Only) (Direct addressing only 0x0A7F 0x0900 0x0800 0x07FF Internal Data Space RF FIFO 0x80 0x7F RF Register Direct and Indirect Addressing XRAM 2KBytes (accessable using MOVX instruction) 0x0000 0x30 0x2F 0x20 0x1F 0x00 Low 128 Bytes RAM (Direct and Indirect Addressing ) Bit Addressable General Purpose Registers Figure 10.1 Memory Organization 10.2.1 Program memory The standard 8051 core has 64KB program memory space. A8105 implement 16KB flash. The last 2KB program memory space (0x 3800 ~ 0x3FFF) supports IAP (In-Application Programming) function. The each block size in this area is 128Bytes. User has 16 blocks in 2KB program memory space to storage data. Program memory is normally assumed to be read-only. However, A8105 can write to program memory by IAP function call. Please reference Application note to write program memory for more detail. 10.2.2 Data memory The A8105 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general Sep., 2014, Version 0.6 (Preliminary) 45 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the Special Function Registers (SFR) but is physically separate from the SFR space. The addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure 10.1 illustrates the data memory organization of the A8105. 10.2.3 General Purpose Registers TI A L The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in SFR Definition 9.1). This allows fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers. 10.2.4 Bit Addressable Locations FI D EN In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination). The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B is the bit position within the byte. For example, the instruction: MOV C, 22.3h ;moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag. 10.2.5 Special Function Registers M C O N The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 9.2 lists the SFRs implemented in the CIP-51 System Controller. The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. 10.2.6 Stack C O A8105 has 8-bit stack point called SP (0x81) located in the internal RAM space. It is incremented before data is stored during PUSH and CALL execution and decremented after data is popped during POP, RET and RETI execution. In the other words it always points to the last valid stack byte. The SP is accessed as any other SFRS. R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W 0 0 0 0 Stack pointer register 0 1 1 1 M IC Address/Name 81h SP Reset 10.2.7 Data Pointer Register A A8105 are implemented dual data pointer registers, auto increment and auto decrement to speed up data block copying. DPTR0 and DPTR1 are located at four SFR addresses. Active DPTR register is selected by SEL bit (0x86.0). If SEL = 0 the DPTR0 is selected otherwise DPTR1. Address/Name 82h DPL0 Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address/Name 83h DPH0 R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sep., 2014, Version 0.6 (Preliminary) R/W 0 0 0 0 0 0 0 0 R/W 46 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Reset 0 0 0 0 0 Data Pointer Register DPTR0 0 0 0 Address/Name 84h DPL1 Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address/Name 85h DPH1 Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address/Name 86h DPS Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W 0 0 0 0 0 0 0 R/W R/W ID1 ID0 TSL AU1 0 0 0 EN 0 0 0 0 0 Data Pointer 1 Register DPTR1 TI A L 0 AU0 - SEL 0 0 0 FI D 0 0 0 0 0 Data Pointers Select Register - C O N ID[1:0] ‐ Increment/decrement function select. See table below. TSL ‐ Toggle select enable. When set, this bit allows the following DPTR related instruction to toggle the SEL bit following execution of the instruction: MOVC A, @A+DPTR INC DPTR MOVX @DPTR, A MOVX A, @DPTR MOV DPTR, #data16 When TSL=0, DPTR related instructions do not affect state of SEL bit. M IC C O M AU ‐When set to '1' performs automatic increment(0)/ decrement(1) of selected DPTR according to IDx bits, after each MOVX @DPTR, MOVC @DPTR instructions SEL ‐ Select active data pointer – see table below ‐ ‐ Unimplemented bit. Read as 0 or 1. A Table DPTR0, DPTR1 operations Selected data pointer register in used in the following instructions: MOVX @DPTR,A MOVX A,@DPTR MOVC A,A+DPTR JMP @A+DPTR INC DPTR MOV DPTR,#data16 10.2.8 RF Registers and RF FIFO RF registers are RF radio control registers and located in 0x0800 ~ 0x08ff. Please refer the section 9.2 and the related function setting in the datasheet. A8105 has 384 Bytes FIFO located from 0x0900 to 0x0A7F. There are 128 bytes FIFO from 0x0900 ~ 0x097F for data transmitting. There are 128 bytes FIFO from 0x0980 ~ 0x09FF for data receiving. Sep., 2014, Version 0.6 (Preliminary) 47 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 10.3 Instruction set TM A8105 use a high performance, pipeline 8051 core and it is filly compatible with the standard MCS-51 instruction set. Standard 8051 development tools can used to develop software for A8105. All A8105 instruction sets are the binary and TM functional equivalent of the MCS-51 . However, instruct timing is different with the standard 8051. All instruction timings are specified in the terms of clock cycles as shown in the table 10.1 Absolute subroutine call ADD A,#data Add immediate data to accumulator ADD A,@Ri Add indirect RAM to accumulator ADD A,direct Add direct byte to accumulator ADD A,Rn Add register to accumulator ADDC A,#data Add immediate data to A with carry flag ADDC A,@Ri Add indirect RAM to A with carry flag ADDC A,direct Add direct byte to A with carry flag ADDC A,Rn Bytes Cycles 0x11‐0xF1 2 4 0x24 2 2 L ACALL addr11 Code TI A Description 1 2 0x25 2 2 0x28‐0x2F 1 1 0x34 2 2 0x36‐0x37 1 2 0x35 2 2 Add register to accumulator with carry flag 0x38‐0x3F 1 1 AJMP addr11 Absolute jump 0x01‐0xE1 2 3 ANL C,/bit AND complement of direct bit to carry 0xB0 2 2 ANL A,#data AND immediate data to accumulator 0x54 2 2 ANL A,@Ri AND indirect RAM to accumulator 0x56‐0x57 1 2 ANL A,direct AND direct byte to accumulator 0x55 2 2 ANL A,Rn AND register to accumulator 0x58‐0x5F 1 1 ANL C,bit AND direct bit to carry flag 0x82 2 2 AND immediate data to direct byte 0x53 3 3 AND accumulator to direct byte 0x52 2 3 0xB6‐0xB7 3 5 ANL direct,#data O ANL direct,A M C O FI D EN 0x26‐0x27 N Mnemonic Compare immediate to ind. and jump if not equal CJNE A,#datare Compare immediate to A and jump if not equal 0xB4 3 4 CJNE A,directre Compare direct byte to A and jump if not equal 0xB5 3 5 CJNE Rn,#datar Compare immediate to reg. and jump if not equal 0xB8‐0xBF 3 4 CLR A Clear accumulator 0xE4 1 1 CLR bit Clear direct bit 0xC2 2 3 CLR C Clear carry flag 0xC3 1 1 CPL A Complement accumulator 0xF4 1 1 CPL bit Complement direct bit 0xB2 2 3 CPL C Complement carry flag 0xB3 1 1 DA A Decimal adjust accumulator 0xD4 1 3 DEC @Ri Decrement indirect RAM 0x16‐0x17 2 3 DEC A Decrement accumulator 0x14 1 1 DEC direct Decrement direct byte 0x15 1 3 DEC Rn Decrement register 0x18‐0x1F 1 2 A M IC C CJNE @Ri,#data Sep., 2014, Version 0.6 (Preliminary) 48 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Divide A by B 0x84 1 6 DJNZ direct,rel Decrement direct byte and jump if not zero 0xD5 3 5 DJNZ Rn,rel Decrement register and jump if not zero 0xD8‐0xDF 2 4 INC @Ri Increment indirect RAM 0x06‐0x07 1 3 INC A Increment accumulator 0x04 1 1 INC direct Increment directbyte 0x05 2 3 INC Rn Increment register 0x08‐0x0F 1 2 INC DPTR Increment data pointer 0xA3 1 1 JB bit,rel Jump if direct bit is set 0x20 3 5 JBC bit,directre Jump if direct bit is set and clear bit 0x10 3 5 JC rel Jump if carry flag is set 0x40 2 3 JMP@A+DPTR Jump indirect relative to the DPTR 0x73 1 5 JNB bit,rel Jumpifdirectbitisnotset 0x30 3 5 JNC Jump if carry flag is not set 0x50 2 3 JNZ rel Jump if accumulator is not zero 0x70 2 4 JZ rel Jump if accumulator is zero 0x60 2 4 LCALL addr16 Long subroutine call 0x12 3 4 LJMP addr16 Long jump 0x02 3 4 MOV A,@Ri Move indirect RAM to accumulator 0xE6‐0xE7 1 2 MOV bit,C Move carry flag to direct bit 0x92 2 3 MOV @Ri,#data Move immediate data to indirect RAM 0x76‐0x77 2 2 MOV @Ri,A Move accumulator to indirect RAM 0xF6‐0xF7 1 2 Move direct byte to indirect RAM 0xA6‐0xA7 2 3 Move immediate data to accumulator 0x74 2 2 Move direct byte to accumulator 0xE5 2 2 Move register to accumulator 0xE8‐0xEF 1 1 MOV C,bit Move direct bit to carry flag 0xA2 2 2 MOV direct,#data Move immediate data to direct byte 0x75 3 3 MOV direct,@Ri Move indirect RAM to direct byte 0x86‐0x87 2 3 MOV direct,A Move accumulator to direct byte 0xF5 2 2 0x88‐0x8F 2 2 MOV A,#data TI A EN FI D N C O M C MOV A,direct O MOV @Ri,direct A M IC MOV A,Rn L DIV A,B MOV direct,Rn Move register to direct byte MOV direct1,direct2 Move direct byte to direct byte 0x85 3 3 MOV DPTR,#data16 Load 16‐bit constant in to active DPTR 0x90 3 3 MOV Rn,#data Move immediate data to register 0x78‐0x7F 2 2 MOV Rn,A Move accumulator to register 0xF8‐0xFF 1 1 MOV Rn,direct Move direct byte to register 0xA8‐0xAF 2 3 MOVC A,@A+DPTR Move code byte relative to DPTR to accumulator 0x93 1 5 MOVC A,@A+PC Move code byte relative to PC to accumulator 0x83 1 4 Sep., 2014, Version 0.6 (Preliminary) 49 AMICCOM Electronics Corporation A8105 1 1 Move A to external RAM (8‐bitaddress) 0xF2‐0xF3 1 2 MOVX A,@DPTR Move external RAM (16‐bitaddress) to A 0xE0 1 1 MOVX A,@Ri Move external RAM (8‐bitaddress) to A 0xE2‐0xE3 1 2 MUL A,B Multiply A and B 0xA4 1 2 NOP No operation 0x00 1 1 ORL direct,A OR accumulator to direct byte 0x42 2 3 ORL A,#data OR immediate data to accumulator 0x44 2 2 ORL A,@Ri OR indirect RAM to accumulator 0x46‐0x47 1 2 ORL A,direct OR direct byte to accumulator 0x45 2 2 ORL A,Rn OR register to accumulator 0x48‐0x4F 1 1 ORL C,/bit OR complement of direct bit to carry 0xA0 2 2 ORL C,bit OR direct bit to carry flag 0x72 2 2 ORL direct,#data OR immediate data to direct byte 0x43 3 3 POP direct Pop direct byte from internal ram stack 0xD0 2 2 PUSH direct Push direct byte on to internal ram stack 0xC0 2 3 RET Return from subroutine 0x22 1 4 RETI Return from interrupt 0x32 1 4 RL A Rotate accumulator left 0x23 1 1 RLC A Rotate accumulator left through carry 0x33 1 1 RR A Rotate accumulator right 0x03 1 1 RRC A Rotate accumulator right through carry 0x13 1 1 Set carry flag 0xD3 1 1 Set direct bit 0xD2 2 3 Short jump (relative address) 0x80 2 3 0x96‐0x97 1 2 TI A MOVX @Ri,A EN Move A to external SRAM (16‐bitaddress) C O N FI D MOVX @DPTR,A SETB bit C SJMP rel O SETB C IC SUBB A,@Ri L 0xF0 M 2.4GHz FSK/GFSK SoC Subtract indirect RAM from A with borrow Subtract direct byte from A with borrow 0x95 2 2 SUBB A,#data Subtract immediate data from A with borrow 0x94 2 2 M SUBB A,direct Subtract register from A with borrow 0x98‐0x9F 1 1 SWAP A Swap nibbles within the accumulator 0xC4 1 1 0xC6‐0xC7 1 3 0xC5 2 3 A SUBB A,Rn XCH A,@Ri Exchange indirect RAM with accumulator XCH A,direct Exchange direct byte with accumulator XCH A,Rn Exchange register with accumulator 0xC8‐0xCF 1 2 XCHD A,@Ri Exchange low‐order nibble indirect RAM with A 0xD6‐0xD7 1 3 XRL direct,#data ExclusiveOR immediate data to direct byte 0x63 3 3 XRL A,#data ExclusiveOR immediate data to accumulator 0x64 2 2 XRL A,@Ri ExclusiveOR indirect RAM to accumulator 0x66‐0x67 1 2 XRL A,direct ExclusiveOR direct byte to accumulator 0x65 2 2 Sep., 2014, Version 0.6 (Preliminary) 50 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC XRL A,Rn ExclusiveOR register to accumulator XRL direct,A ExclusiveOR accumulator to direct byte 0x68‐0x6F 1 1 0x62 2 3 Table 10.1 Instruction set sorted by alphabet 10.4 Interrupt handler TI A L This section describes 8051 external interrupts and their functionality. For peripheral related interrupts, please refer to an appropriate peripheral section. The external interrupts symbol is shown in figure above. And the pins functionality is described in the following table. All pins are one directional. There are no three-state output pins and internal signals. FI D EN Name ACTIVE TYPE DESCRIPTION int0(P3.2) low/falling Input External interrupt 0 line int1(P3.3) low/falling Input External interrupt 1 line int2(P0.7) low Input External interrupt 2 line int3*(P1.2) low Input External interrupt 3 line int4*(P1.3) low Input External interrupt 4 line RFINT failing KEYINT failing Table 10.2 External interrupts pins description Note1：Number of external interrupt sources depends on core configuration. It can be adjusted upon request. The int0 & int1 sources are always available. Please check your configuration. Note2：*pin functionality depends on compare / capture unit. 10.4.1 FUNCTIONALITY Active level/edge Low/falling Low/falling Low Low Low -Falling -Falling - O M Function Device pin INT0 Internal, Timer 0 Device pin INT1 Internal, Timer 1 Interrupt, UART Interrupt, Timer 2 Reserved Device pin INT2 Device pin INT3 Device pin INT4 Interrupt, RFINT Interrupt, KeyINT Internal, Watchdog Internal, I2C MASTER MODULE Internal, DI2CS/ Internal, SPI Reserved Reserved A M IC C Interrupt flag IE0 TF0 IE1 TF1 TI & RI TF2 Reserved INT2F INT3F INT4F RFINT KEYINT WDIF I2CMIF I2CSIF SPIIF Reserved Reserved C O N All 8051 IP cores have implemented two levels interrupt priority control. Each external interrupt can be in high or low level priority group by setting or clearing a bit in the IP(0xB8), EIP(0xF8), and DEVICR(0xCF) registers. External interrupt pins are activated at low level or by a falling edge. Interrupt requests are sampled each system clock at the rising edge of CLK. 1- - Table10.3 Flag resets Hardware Hardware Hardware Hardware Software Software Software Hardware Hardware Hardware Software Software Software Software Software Vector 0x03 0x0B 0x13 0x1B 0x23 0x2B 0x33 0x3B 0x43 0x4B 0x53 0x5B 0x63 0x6B 0x73 Hardware Hardware 0x7B 0x83 1 Natural priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 8051 interrupts summary This is a default location when IRQ_INTERVAL = 8, in other case is equal to (IRQ_INTERVAL* n ) + 3, when n = (natural Priority - 1) Each interrupt vector can be individually enabled or disabled by setting or clearing a corresponding bit in the IE(0xA8), EIE(0xE8), DEVICR(0xCF). The IE contains global interrupt system disable(0) / enable(1) bit called EA. IE register (0xA8) Address/Name A8h IE Sep., 2014, Version 0.6 (Preliminary) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W EA - ET2 51 ES0 ET1 EX1 ET0 EX0 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Reset 0 0 0 0 0 0 0 0 L EA：Enable global interrupts EX0：Enable INT0 interrupts ET0：Enable Timer 0 interrupts EX1：Enable INT1 interrupts ET1：Enable Timer 1 interrupts ES：Enable UART interrupts ET2：Enable Timer 2 interrupts (0xB8) Address/Name B8h IP Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W - - 0 0 PT2 PS PT1 PX1 PT0 PX0 0 0 0 0 0 0 TCON register M C O N PX0：INT0 priority level control (at 1-high-level) PT0：Timer 0 priority level control (at 1-high-level) PX1：INT1 priority level control (at 1-high-level) PT1：Timer 1 priority level control (at 1-high-level) PS：UART priority level control (at 1-high-level) PT2：Timer 2 priority level control (at 1-high-level) FI D IP register EN TI A All of bits that generate interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. The exceptions of this rule are the request flags IE0 and lE1. If the external interrupts 0 or 1 are programmed to be level activated, IE0 and lE1 are controlled by the external source via pin INT0 and INT1, respectively. Thus, writing a one to these bits will not set the request flag IE0 and/or lE1. The same exception is related to INT2F, INT3F, INT4F, RFINTF, and KEYINTF – external interrupts number 2, 3, 4, 5, 6. (0x88) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 O Address/Name 88h TCON Reset TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 0 0 0 0 0 0 0 0 IC C R/W A M IT0：INT0 level (at 0) / edge (at 1) sensitivity IT1：INT1 level (at 0) / edge (at 1) sensitivity IE0：INT0 interrupt flag Cleared by hardware when processor branches to interrupt routine IE1：INT1 interrupt flag Cleared by hardware when processor branches to interrupt routine TF0：Timer 0 interrupt (overflow) flag Cleared by hardware when processor branches to interrupt routine TF1：Timer 1 interrupt (overflow) flag Cleared by hardware when processor branches to interrupt routine SCON register (0x98) Address/Name 98h SCON Reset Sep., 2014, Version 0.6 (Preliminary) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W SM0 SM1 SM2 REN TB8 RB8 TI RI 0 0 0 0 0 0 0 0 52 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC RI：UART receiver interrupt flag TI：UART transmitter interrupt flag EIE register (0xE8) (0xF8) FI D EIP register EN TI A L Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 E8h EI2CS R/W EI2CM EWDI EKEYINT ERFINT EINT4 EINT3 EINT2 EIE ESPI Reset 0 0 0 0 0 0 0 0 EINT2：Enable INT2 interrupts EINT3：Enable INT3 EINT4：Enable INT4 ERFINT：Enable RF INT EKEYINT：Enable KEYINT EWDI：Enable Watchdog interrupts EI2CM：Enable I2C MASTER MODULE interrupts EI2CS：Enable DI2CS interrupts ESPI：Enable SPI MODULE interrupts O M C O N Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F8h PI2CS R/W PI2CM PWDI PKEYINT PRFINT PINT4 PINT3 PINT2 EIP PSPI Reset 0 0 0 0 0 0 0 0 PINT2：INT2 priority level control (at 1-high-level) PINT3：INT3/Compare 0 priority level control (at 1-high-level) PINT4：INT4/Compare 1 priority level control (at 1-high-level) PRFINT：RFINT priority level control (at 1-high-level) PKEYINT：KEYINT priority level control (at 1-high-level) PWDI：Watchdog priority level control (at 1-high-level) PI2CM：I2C MASTER MODULE priority level control (at 1-high-level) PI2CS：I2C MODULE priority level control (at 1-high-level) PSPI：SPI MODULE priority level control (at 1-high-level) EIF register (0x91) A M IC C Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 91h I2CSF R/W I2CMF - KEYINTF RFINTF INT4F INT3F INT2F EIF SPIF Reset 0 0 0 0 0 0 0 0 INT2F：INT2 interrupt flag Should be cleared by external hardware when processor branches to interrupt routine. This bit is a copy of INT2 pin updated every CLK period. It cannot be set by software. INT3F*：INT3/Compare 0 interrupt flag Should be cleared by external hardware when processor branches to interrupt routine. t cannot be set by software. INT4F*：INT4/Compare 1 interrupt flag Should be cleared by external hardware when processor branches to interrupt routine. It cannot be set by software. RFINTF：RFINT interrupt flag Must be cleared by software writing 0x08 when controlled by RFINT. KEYINTF：KEYINT interrupt flag Must be cleared by software writing 0x10 when controlled by KEYINT. I2CMIF：I2C MASTER MODULE interrupt flag. It must be cleared by software writing 0x40. It cannot be set by software I2CSIF：I2C MODULE interrupt flag SPIIF：SPI MODULE interrupt flag Software should determine the source of interrupt by checking both modules’ interrupt related bits. It must be cleared by software writing 0x80. It cannot be set by software. Sep., 2014, Version 0.6 (Preliminary) 53 AMICCOM Electronics Corporation A8105 FI D EN TI A L 2.4GHz FSK/GFSK SoC 10.5 Reset source C O N Reset circuitry allows A8105 to be easily placed in a predefined default condition. LVD, Reset, POR, and Watchdog signal will reset 8153 when they happen. Power on Reset REGI RESETN Internal Reset C Low voltage detecot Watchdog timer Figure 10.2 Reset source M IC REGI O M Reset circuit A RSFLAG: Reset Flag(0xBA): Address/Name BAh RSFLAG R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 R - - - - - 0 0 0 0 0 Reset Write any data to RSFLAG to clear all bits. PORF (power-on reset flag) = 1: Occurred Power-on Reset = 0: No Power-on Reset RESETNF (resetn flag) = 1: Occurred ResetN reset = 0: No ResetN resetno resetn reset LVD (Low voltage detect) flag = 1: Occurred Low Voltage Reset Sep., 2014, Version 0.6 (Preliminary) 54 Bit 2 Bit 1 Bit 0 LVDF RESETNF PORF 0 0 1 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC FI D EN TI A L = 0: No Low Voltage reset N Please refer the figure 10.3 and 10.4 for the timing diagram for stable power of reset signal and internal behavior of CPU. C O XOUT O M REGI IC C RESETN T RST1 VIH 2046 Crystal Clock Cycles Figure 10.3 Timing Diagram for stable power to the release of RESETN A M T RST1 : According to RESETN’s RC delay (standard module is about 50ms) Sep., 2014, Version 0.6 (Preliminary) 55 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC CPU clock VIH RESETN 2046 Crystal Clock Cycles EN Tstartup CPU OP Code Fetch : 2 Crystal Clock Cycles (min) FI D CPU Start Running CPU Stop Running T RST2 TI A L T RST2 N Tstartup : 2046 Crystal Clock Cycles + RESETN’s RC delay (standard module is about 50ms) C O Figure 10.4 Timing Diagram for RESETN control sequence 10.6 Clock source A M IC C O M A8105 has three clock source, crystal oscillator (pin 13,14/ Xi, XO), RTC crystal (pin 1,2/ P3.6, P3.7/ RTC_I, RTC_O) and internal RC oscillator. In the MCU part (digital peripherals ), user choices the suitable clock source by power consumptions and performance. In the RF part, the clock source only comes from XO.. Sep., 2014, Version 0.6 (Preliminary) 56 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC RF Clock Generator XO 0 CLKRUN 1 0 /1 L IRC 1 CLKCTRL /2 CLKSEL =7 RTCS /4 CLKSEL /16 /32 WOR/TWOR timer PMM STOP FI D /64 MCU Core CLKPMM EN /8 CLK TI A RTC C O N CLKSEL = 0 ~6 A M IC C O M Figure 10.3 Whole chip clock Sep., 2014, Version 0.6 (Preliminary) 57 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 11. I/O Ports TI A L A8105 has two type of digitla I/O Pins. One is 24 pins and the other is 28 pins. In 24pins, there are separated to 3 Ports (Port0, Port1 and Port3) and each of the Port pin can be defined as general-purpose I/O (GPIO) or peripheral I/O signals connected to the timers, UART, I2C and SPI functions. In 28pins, there are extra 4pins of Port2 and they are Port2.0 ~ Port2.3. Thus, each pin can also be used to wake A8105 up from sleep mode. User can select each pin function by setting register. Each port has itself port register like P0 (0x80), P1 (0x90), P2(0xA0) and P3 (0xB0) that are both byte addressable and bit addressable. When reading, the logic levels of the Port’s input pins are returned. Each port has three registers to setting Pull-up (PUN), Output-enable (OE) and Wake-up enable (WUN). As shown the bellow block diagram, Fig. 11.1. Unused I/O pins should have a defined level and not be left floating. One way to do this is to leave the pin unconnected and configure the pin as a general-purpose I/O input with pull-up resistor. DO EN PUN P DI WUN C O KEYINT N FI D OE Figure11.1 Ports I/O block diagram M PUN P DI 0 1 1 1 HZ INH X DO DO Table 11.1 OE and PUN setting and Output(P) and Input(DI) WUN KEYINT 0 Enable 1 Disable Table 11.2 WUN setting and KEYINT source M IC C O OE 0 0 1 11.1 FUNCTIONALITY A It has three 8-bit full bi-directional ports, P0, P1 and P3. Each port bit can be individually accessed by bit addressable instructions. Address/Name 80h P0 Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address/Name 90h P1 R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sep., 2014, Version 0.6 (Preliminary) R/W 0 0 0 0 Port 0 register 0 0 0 0 R/W 58 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Reset 0 0 0 0 Port 1 register 0 0 0 0 Address/Name A0h P2 Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address/Name B0h P3 Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W 0 0 0 Port 2 register 0 0 0 0 R/W 0 0 0 Port 3 register 0 0 0 0 EN 0 TI A L 0 N Function description Logic AND Logic OR Logic eXclusive OR Jump if bit is set and clear Complement bit Increment, decrement byte Decrement and jump if not zero Move carry bit to y of port x Clear bit y of port x Set bit y of port x Read-modify-write instructions M C O Instruction ANL ORL XRL JBC CPL INC, DEC DJNZ MOV Px.y, C CLR Px.y SETB Px.y Table11.3 FI D Read and write accesses to the I/O port are performed via their corresponding SFRs P0(0x80), P1(0x90), and P3(0xB0). Some port‐reading instructions read the data register and others read the port’s pin. The “Read‐Modify‐Write” instructions are directed to the data registers and are shown below. All the other instructions used to read a port exclusively read the port’s pin. C O According the Table 11.1, all Port pins can be configured as Output, Input with the pull-up resistor (around 100 Kohm) or Input. Please refer the following truth table to know every function setting. When OE=1, this pin is configured as Output. Otherwise OE =0, this pin is configured as Input. User can set PUN =1 or 0 depending on application. When OE =0, PUN=0 is recommended for saving power. A M IC All Port pins can wake A8105 up when WUEN=0 and configured GPIO. All Port pins’ WUN signals connect one OR gate to KEYINT. It means pin wake up function needs KEYINT ISR to take care this interrupt event. Address/Name D1h P0OE Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address/Name D2h P0PUN Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address/Name D3h P0WUN Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sep., 2014, Version 0.6 (Preliminary) R/W 0 0 0 0 0 Port 0 Output Enable Register 0 0 0 R/W 0 0 0 0 Port 0 Pull Up Register 0 0 0 0 R/W 1 1 1 1 1 Port 0 Wake Up Enable Register 59 1 1 1 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Address/Name D9h P1OE Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address/Name DAh P1PUN Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address/Name DBh P1WUN Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address/Name A1h P2OE Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address/Name A2h P2PUN Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W 0 0 0 R/W 0 0 0 EN R/W 1 FI D 1 1 1 1 1 Port 1 Wake Up Enable Register R/W 0 TI A 0 0 0 0 Port 1 Pull Up Register L 0 0 0 0 0 Port 1 Output Enable Register 0 0 1 0 C O N 0 0 0 0 0 Port 2 Output Enable Register 1 R/W 0 0 0 0 M 0 0 0 0 Port 2 Pull Up Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W A M IC C O Address/Name A3h P2WUN Reset 1 1 1 1 1 Port 2 Wake Up Enable Register 1 1 1 Address/Name E1h P3OE Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address/Name E2h P3PUN Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address/Name E3h P3WUN Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sep., 2014, Version 0.6 (Preliminary) R/W 0 0 0 0 0 Port 3 Output Enable Register 0 0 0 R/W 0 0 0 0 Port 3Pull Up Register 0 0 0 0 R/W 1 1 1 1 1 Port 3 Wake Up Enable Register 60 1 1 1 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC (0xBB) Bit 7 Bit 6 R/W - Bit 5 Bit 4 Bit 3 RADCIOS[1:0] RTCIOS BBIOS 0 0 0 0 0 - Bit 1 Bit 0 I2CIOS URT0IOS 0 0 0 ADCCH Register (0xBC) Bit 7 Bit 6 Bit 5 Bit 4 -- -- -- -- 0 0 0 0 M Address/Name R/W BCh R/W ADCCH Reset C O N FI D RADCIOS1 (RC-ADC1 I/O select) [0]: Disable RC-ADC1 analog input. [1]: P1.0, P1.1, P1.2, P1.3 are selected for RC-ADC0 analog input pin. RADCIOS0 (RC-ADC0 I/O select) [0]: Disable RC-ADC0 analog input. [1]: P0.0, P0.1, P0.2, P0.3 are selected for RC-ADC0 analog input pin. RTCIOS (Real-time clock I/O select) [1]: The pad is for RTC clock [0]: The pad is normal I/O BBIOS (Base band I/O select) [1]: P0.7, P1.2, P1.3 are selected for RF GPIO1,GPIO2,CKO function pin [0]: P0.7, P1.2, P1.3 are normal I/O I2CIOS (I2C I/O select) [1]: The pad is selected for I2C (open drain I/O) [0]: The pad is normal I/O UARTIOS (UART0 I/O select) [1]: Port 3.0 and Port3.1 are selected for UART0 mode0 (open drain I/O) [0]: Port 3.0 and Port3.1 are normal I/O Bit 2 L R/W TI A Address/Name BBh IOSEL Reset EN IOSEL Register Bit 3 Bit 2 Bit 1 Bit 0 ADCCH3 ADCCH2 ADCCH1 ADCCH0 0 0 0 0 A M IC C O ADCCH[3:1] (ADC I/O select) [000]: Select P3.2 as ADC analog input. [001]: Select P3.3 as ADC analog input. [010]: Select P3.4 as ADC analog input. [011]: Select P3.5 as ADC analog input. [100]: Select P1.6 as ADC analog input. [101]: Select P1.7 as ADC analog input. [110]: Select P3.0 as ADC analog input. [111]: Select P3.1 as ADC analog input. ADCCCH0 [1]: Enable ADC analog input [0]: Disable ADC analog input 11.2 Key interrupt User can use P0, P1 or P3 port as key input and meanwhile these key are clicked to event a key interrupt to wake up A8105 or enter key process flow. It is a helpful use to design a remote controller and low power consumption with power saving mode setting. The KEY INT vector is located on 0x5B. User can put an interrupt service routine in 0x5B. The KEY interrupts can wake up A8105 back to normal mode in PM1 and PM2. In PM3, Port 3.2~Port 3.5 and RESETN PIN will reset A8105 and A8105 need to initial all needed peripherals and take care key interrupt event. Sep., 2014, Version 0.6 (Preliminary) 61 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC p0wun[0] p0[0] p0wun[7] L p0[7] TI A p1wun[0] p1[0] KEYINT EN p1wun[7] FI D p1[7] p3wun[0] N p3[0] p3[7] C O p3wun[7] A M IC C O M Figure11.2 Key interrupt block diagram Sep., 2014, Version 0.6 (Preliminary) 62 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 12 Timer0,1 and Timer2 A8105 contains three 16-bit timer/counters, Timer 0, Timer 1 and Timer 2. Timer 0 and Timer 1 in the “timer mode“, timer registers are incremented every 4/12/CLK periods depends on CKCON (0x8E) setting, when appropriate timer is enabled. In the “counter mode” the timer registers are incremented every falling transition on theirs corresponding input pins: T0 or T1. The input pins are sampled every CLK period. L The Timer 2 is one of the most powerful peripheral units of the core. It can be used for all kinds of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse width measuring etc. 12.1 Timer 0 & 1 PINS DESCRIPTION ACTIVE Falling High Falling High TYPE Input Input Input Input DESCRIPTION Timer 0 clock line Timer 0 clock line gate control Timer 1 clock line Timer 1clock line gate control EN PIN T0(P3.4) GATE0(P3.2) T1(P3.5) GATE1(P3.3) TI A The pins functionality is described in the following table. All pins are one directional. Table12.1 Timer 0, 1 pins description FI D 12.2 Timer 0 & 1 FUNCTIONALITY 12.2.1 OVERVIEW M0 0 1 0 1 Mode 0 1 2 3 Function description THx operates as 8-bit timer/counter with a divide by 32 prescaler served by lower 5-bit of TLx. 16-bit timer/counter. THx and TLx are cascaded. TLx operates as 8-bit timer/counter with 8-bit auto-reload by THx. TL0 is configured as 8-bit timer/counter controlled by the standard Timer 0 bits. TH0 is an 8-bit timer controlled by the Timer 1 controls bits. Timer 1 holds its count. C O M1 0 0 1 1 N Timer 0 and Timer 1 are fully compatible with the standard 8051 timers. Each timer consists of two 8-bit registers TH0 (0x8C), TL0 (0x8A), TH1 (0x8D), TL1 (0x8B). Timers 0, 1 work in the same four modes. The modes are described below. TMOD register (0x89) O 12.2.2 Timer 0 & 1 Registers M Table12.2 Timer 0 and 1 modes R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W GATE1 CT M1 M0 GATE0 CT M1 M0 IC C Address/Name 89h TMOD Reset 0 Timer 1 control bits 0 0 0 0 Timer 0 control bits 0 0 0 A M GATE：Gating control =1, Timer x enabled while GATEx pin is high and TRx control bit is set. =0, Timer x enabled while TRx control bit is set. CT：Counter or timer select bit =1, Counter mode, Timer x clock from Tx pin. =0, Timer mode, internally clocked. M[1：0]：Mode select bits TCON register (0x88) Address/Name 88h TCON Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 0 0 0 0 0 0 0 0 TR0：Timer 0 run control bit =1, enabled. =0, disabled. TR1：Timer 1 run control bit Sep., 2014, Version 0.6 (Preliminary) 63 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC =1, enabled. =0, disabled. TF0：Timer 0 interrupt (overflow) flag. Cleared by hardware when processor branches to interrupt routine. TF1：Timer 1 interrupt (overflow) flag. Cleared by hardware when processor branches to interrupt routine. CKCON register (0x8E) TI A FI D T0M：This bit controls the division of the system clock that drives Timer 0. =1, Timer 0 uses a divided-by-4 of the system clock frequency. =0, Timer 0 uses a divided-by-12 of the system clock frequency. EN T1M：This bit controls the division of the system clock that drives Timer 1. =1, Timer 1 uses a divided-by-4 of the system clock frequency. =0, Timer 1 uses a divided-by-12 of the system clock frequency. L Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 8Eh R/W WD1 WD0 T2M T1M T0M MD2 MD1 MD0 CKCON Reset 0 0 0 0 0 0 0 0 T2M：This bit controls the division of the system clock that drives Timer 2. =1, Timer 2 uses a divided-by-4 of the system clock frequency. =0, Timer 2 uses a divided-by-12 of the system clock frequency. R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EA IP register (0xB8) - ET2 ES ET1 EX1 ET0 EX0 0 0 0 0 0 0 0 C O R/W 0 M Address/Name A8h IE Reset EA：Enable global interrupts. ET0：Enable Timer 0 interrupts. ET1：Enable Timer 1 interrupts. N IE register (0xA8) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - PT2 PS PT1 PX1 PT0 PX0 0 0 0 0 0 0 0 IC C O Address/Name R/W Bit 7 B8h R/W IP Reset 0 PT0：Timer 0 priority level control (at 1-high level) PT1：Timer 1 priority level control (at 1-high level) A M Timer 0, 1 related bits that generate interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. Interrupt flag TF0 TF1 Function Internal, Timer 0 Internal, Timer 1 Active level/edge - Table12.3 Flag resets Hardware Hardware Vector 0x0B 0x1B Natural priority 2 4 Timer 0, 1 interrupts 12.2.3 Timer 0 – Mode 0 In this mode, the Timer 0 register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s. Timer 0 interrupt flag TF0 is set. The counted input is enabled to the Timer 0 when TCON.4 = 1 and either TMOD.3 = 1 or GATE0 = 1. (Setting TMOD.3 = 1 allows the Timer 0 to be controlled by external input GATE0, to facilitate pulse width measurement). The 13-bit register consists of all 8-bit of TH0 and lower 5 bits of TL0.The upper 3 bits of TL0 are indeterminate and should be ignored. Sep., 2014, Version 0.6 (Preliminary) 64 AMICCOM Electronics Corporation A8105 Timer/Counter 0, Mode 0：13-Bit Timer/Counter EN Figure12.1 TI A L 2.4GHz FSK/GFSK SoC 12.2.4 Timer 0 – Mode 1 C O N FI D Mode 1 is the same as Mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in figure below. Timer/Counter 0, Mode 1：16-Bit Timer/Counter M Figure12.2 O 12.2.5 Timer 0 – Mode 2 A M IC C Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reloads, as shown in figure below. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is loaded by software. The reload leaves TH0 unchanged. Figure12.3 Sep., 2014, Version 0.6 (Preliminary) Timer/Counter 0, Mode 2：8-Bit Timer/Counter with Auto-Reload 65 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 12.2.6 Timer 0 – Mode 3 Figure12.4 12.2.7 Timer 1 – Mode 0 C O N FI D EN TI A L Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in figure below. TL0 uses the Timer 0 control bits：C/T, GATE, TR0, GATE0 and TF0. TH0 is locked into a timer function and use the TR1 and TF1 flag from Timer1 and controls Timer1 interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer/counter. When Timer 0 is in Mode 3, Timer 1 can be turned off by switching it into its own Mode 3, or can still be used by the serial channel as a baud rate generator, or in any application where interrupt from Timer 1 is not required. Timer/Counter 0, Mode 3：Two 8-Bit Timers/Counters A M IC C O M In this Mode, the Timer1 register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, Timer1 interrupt flag TF1 is set. The counted input is enabled to the Timer1 when TCON.6 = 1 and either TMOD.6 = 0 or GATE1 = 1. (Setting TMOD.7 = 1 allows the Timer1 to be controlled by external input GATE1, to facilitate pulse width measurements). The 13‐bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be ignored. Figure12.5 Timer/Counter 1, Mode 0：13-Bit Timers/Counters 12.2.8 Timer 1 – Mode 1 Mode 1 is the same as Mode 0, except that timer register is running with all 16 bits. Mode 1 is shown in figure below. Sep., 2014, Version 0.6 (Preliminary) 66 AMICCOM Electronics Corporation A8105 Figure12.6 TI A L 2.4GHz FSK/GFSK SoC Timer/Counter 1, Mode 0：16-Bit Timers/Counter EN 12.2.9 Timer 1 – Mode 2 M C O N FI D Mode 2 configures the timer register as an 8-bit counter (TL1) with automatic reloads, as shown in figure below. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is loaded by software. The reload leaves TH1 unchanged. Timer/Counter 1, Mode 2：8-Bit Timer/Counter with Auto-Reload O Figure12.7 12.2.10 Timer 1 – Mode 3 IC C Timer 1 in Mode 3 is held counting. The effect is the same as setting TR1=0. 12.3 Timer2 PINS DESCRIPTION M The Timer 2 pins functionality is described in the following table. All pins are one directional. A PIN t2(P1.0) t2ex(P1.1) ACTIVE falling high TYPE INPUT INPUT DESCRIPTION Timer 2 clock line Timer 2 control Table12.4 Compare/Capture pins description 12.4 Timer2 FUNCTIONALITY 12.4.1 OVERVIEW Timer 2 is fully compatible with the standard 8052 Timer 2. It is up counter. Totally five SFRs control the Timer 2 operation: TH2/TL2(0xCD/0xCC) counter registers, RCAP2H/RCAP2L (0xCB/0xCA) capture registers and T2CON(0xC8) control register. Timer 2 works in the three modes selected by T2CON bits as shown in table below. RCLK, CPRL2 TR2 Sep., 2014, Version 0.6 (Preliminary) Function description 67 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 0 1 0 1 1 1 X 1 X X 0 16-bit auto-reload mode. The Timer 2 overflow sets TF2 bit and the TH2,TL2 registers reloaded 16-bit value from RCAP2H, RCAP2L. 16-bit capture mode. The Timer 2 overflow sets TF2 bit. When the EXEN2 = 1, the TH2, TL2 register values are stored into RCAP2H, RCAP2Lwhile falling edge is detected on T2EX pin. Baud rate generator for the UART0 interface. It auto-reloads its counter with RCAP2H, RCAP2Lvalues each overflows. Timer 2 is off Table12.5 Timer 2 modes T2CON register TI A 12.4.2 Timer 2 Registers L TCLK 0 (0xC8) A M IC C O M C O N FI D EN Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C8h R/W TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2 APOL Reset 0 0 0 0 0 0 0 0 EXF2：Falling edge indicator on T2EX pin when EXEN = 1. Must be cleared by software. RCLK：Receiver clock enable =1, UART0 receiver is clocked by Timer 2 overflow pulses =0, UART0 receiver is clocked by Timer 2 overflow pulses TCLK：Transmit clock enable =1, UART0 transmitter is clocked by Timer 2 overflow pulses =0, UART0 transmitter is clocked by Timer 2 overflow pulses EXEN2：Enable T2EX pin functionality. =1, Allows capture or reload as a result of T2EX pin falling edge. =0, ignore T2EX events TR2：Start / Stop Timer 2 =1, start =0, stop CT2：Timer / counter select =1, external event counter. Clock source is T2 pin. =0, timer 2 internally clocked CPRL2：Capture / Reload select =1, T2EX pin falling edge causes capture to occur when EXEN2 = 1 =0, automatic reload occurs on Timer 2 overflow or falling edge T2EX pin when EXEN2 = 1. When RCLK or TCLK is set this bit is ignored and automatic reload on Timer 2 overflow is forced. Sep., 2014, Version 0.6 (Preliminary) 68 AMICCOM Electronics Corporation A8105 N FI D EN TI A L 2.4GHz FSK/GFSK SoC CKCON register (0x8E) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W WD1 WD0 T2M T1M T0M MD2 MD1 MD0 0 0 0 0 0 0 0 0 M Address/Name 8Eh CKCON Reset Timer 2 block diagram in timer mode C O Figure12.8 timer is in baud C O T2M：This bit controls the division of the system clock that drives Timer 2. This bit has no effect when the rate generator mode. =1, Timer 2 uses a divide-by-4 of the system clock frequency. =0, Timer 2 uses a divide-by-12 of the system clock frequency. IC Timer 2 interrupt related bits are shown below. An interrupt can be turned on/off by IE (0xA8) register, and set into high/low priority group by IP register. M IE register (0xA8) A Address/Name A8h IE Reset EA：Enable global interrupts. ET2：Enable Timer 2 interrupts. R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W EA - ET2 ES ET1 EX1 ET0 EX0 0 0 0 0 0 0 0 0 IP register (0xB8) Address/Name R/W B8h R/W IP Reset Sep., 2014, Version 0.6 (Preliminary) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - PT2 PS PT1 PX1 PT0 PX0 0 0 0 0 0 0 0 0 69 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC PT2：Timer 2 priority level control (at 1-high level) T2CON register (0xC8) Bit 7 Bit 6 TF2 EXF2 RCLK TCLK EXEN2 TR2 0 0 Bit 5 Bit 4 0 Bit 3 0 Bit 2 0 Bit 0 CT2 CPRL2 0 0 0 TI A TF2：Timer 2 interrupt (overflow) flag. It must be cleared by software. The flag will not be set when either RCLK or TCLK is set. Bit 1 L Address/Name R/W C8h R/W T2CON Reset Table12.6 EN All Timer 2 related bits generate interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. Interrupt flag Function Active level / edge Flag resets Vector Natural priority TF2 Internal, Timer2 Software 0x2B 6 Timer2 interrupt A M IC C O M C O N FI D Interrupt is also generated at falling edge of T2EX pin, while EXEN2 bit is set. This interrupt doesn’t set TF2 flag, but EXF2 only and also uses 0x2B vector. Please see picture below. Timer2 internal logic configured as baud‐rate generator is shwon below. Figure12.9 Timer 2 block diagram as UART0 baud rate generator Please note that SMODbit is ignored by UART when clocked by Timer2. The RLCK/TCLK frequency is equal to： Sep., 2014, Version 0.6 (Preliminary) 70 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 13. UART TI A L UART is full duplex, meaning it can transmit and receive concurrently. It is receive double‐buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. Writing to SBUF loads the transmit register, and reading SBUF reads a physically separate receive register. The serial port can operate in 4 modes: one synchronous and three asynchronous modes. Mode 2 and 3 has a special feature for multiprocessor communications. This feature is enabled by setting SM2 bit in SCON register. The master processor first sends out an address byte, which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte will interrupt all slaves. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that were not being addressed leave their SM2 set and ignoring the incoming data. 13.1 UART PINS DESCRIPTION EN The UART pins functionality is described in the following table. All pins are one directional. There are no three‐state output pins and internal signals. ACTIVE TYPE DESCRIPTION Input / Output Serial receiver I_0 / O_0 Output Serial transmitter line 0 Table13.1 UART pins description FI D PIN Rxd_0(P3.0) Txd_0(P3.1) N 13.2 FUNCTIONALITY SBUF register C O The UART has the same functionality as a standard 8051 UART. The UART related registers are: SBUF(0x99), SCON (0x98), PCON(0x87), IE(0xA8) and IP(0xB8). The UART data buffer (SBUF) consists of two separate registers: transmit and receive registers. A data writes into the SBUF sets this data in UART output register and starts a transmission. A data reads from SBUF, reads data from the UART receive register. (0x99) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Bit 6 O M Address/Name R/W 99h R/W SBUF Reset (0x98) IC SCON register C SBUF[7:0]：UART buffer R/W Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 98h SCON R/W SM00 SM01 SM02 REN TB8 RB8 TI RI 0 0 0 0 0 A M Address/Name Reset 0 0 0 SM2：Enable a multiprocessor communication feature SM [1:0]：Sets baud rate SM0 SM1 Mode Description Baud Rate 0 0 0 Shift register FCLK/12 0 1 1 8-bit UART Variable 1 0 2 9-bit UART FCLK/32 or FCLK/64 1 1 3 9-bit UART Variable Timer 2 cannot be used as baud rate generator when Compare Capture unit is present in the system. The UART baud rates are presented in the table below. Mode Baud Rate Mode 0 FCLK/12 Sep., 2014, Version 0.6 (Preliminary) 71 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Timer 1 overflow rate – T1ov SMOD= 0 T1ov/32 SMOD= 1 T1ov/16 Timer 2 overflow rate – T2ov SMOD= x T2ov/16 Mode 2 SMOD= 0 FCLK/64 SMOD= 1 FCLK/32 The SMOD bit is located in PCON register. Mode 1, 3 (0x87) Address/Name 87h PCON Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 R/W SMOD - - PWE - 0 0 0 0 0 Bit 2 Bit 1 Bit 0 SWB STOP CKSE 0 0 0 FI D SMOD：UART double baud rate bit when clocked by Timer 1 only. Bit 3 EN PCON register TI A L REN：If set, enable serial reception. Cleared by software to disable reception. th TB8：The 9 transmitted data bit in Modes 2 and 3. Set or cleared by the MCU, depending on the function it performs (parity check, multiprocessor communication etc.) th RB8：In Modes 2 and 3 it is the 9 data bit received. In Mode 1, if SM2 is 0, RB8 is the stop bit. In Mode 0 this bit is not used. UART interrupt related bits are shown below. An interrupt can be turned on / off by IE register, and set into high / low priority group by IP register. Address/Name A8h IE Reset N (0xA8) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C O IE register R/W - ET2 ES ET1 EX1 ET0 EX0 0 0 0 0 0 0 0 0 M ES：RI & TI interrupt enable flag EA (0xB8) Address/Name B8h IP Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - PT2 PS PT1 PX1 PT0 PX0 0 0 0 0 0 0 0 0 O IP register C R/W IC PS：RI & TI interrupt priority flag (0x98) Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 98h R/W SM0 SM1 SM2 REN TB8 RB8 TI RI SCON Reset 0 0 0 0 0 0 0 0 TI：Transmit interrupt flag, set by hardware after completion of a serial transfer. It must be cleared by software. RI：Receive interrupt flag, set by hardware after completion of a serial reception. It must be cleared by software. A M SCON register All of bits that generate interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. Interrupt flag TI & RI Function Internal, UART Active level / edge - Table13.3 Sep., 2014, Version 0.6 (Preliminary) Flag resets Software Vector 0x23 Natural priority 5 UART interrupt 72 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 13.3 OPERATING MODES 13.3.1 UART MODE 0, SYNCHRONOUS Figure13.3 TI A L Pin RXD0I serves as input and RXD0O as output. TXD0 output is a shift clock. The baud rate is fixed at 1/12 of the CLK clock frequency. Eight bits are transmitted with LSB first. Reception is initialized by setting the flags in SCON as follows: RI=0 and REN=1. UART transmission mode 0 timing diagram EN 13.3.2 UART MODE 1, 8-BIT UART, VARIABLE BAUD RATE, TIMER CLOCK SOURCE C O N FI D Pin RXD0I serves as input, and TXD0 serves as serial output. 10 bits are transmitted: a start bit (always 0), 8 data bits (LSB first), and a stop bit (always 1). On receive, a start bit synchronizes the transmission, 8 data bits are available by reading SBUF, and stop bit sets the flag RB8 in the SFR SCON. The baud rate is variable and depends from Timer 1 or Timer 2 mode. To enable Timer 2 clocking set the TCLK, RCLK bits located in T2CON (0xC8) register. SMOD bit is ignored when UART is clocked by Timer2. Figure13.4 UART transmission mode 1 timing diagram 13.3.3 UART MODE 2, 9‐BIT UART, FIXED BAUD RATE M IC C O M This mode is similar to Mode 1 with two differences. The baud rate is fixed at 1/32 or 1/64 of CLK clock frequency, and 11 th th bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a programmable 9 bit, and a stop bit (1). The 9 bit can be th th used to control the parity of the UART interface: at transmission, bit TB8 in SCON is output as the 9 bit, and at receive, the 9 bit affects RB8 in SCON. Figure13.5 UART transmission mode 2 timing diagram A 13.3.4 UART MODE 3, 9‐BIT UART, VARIABLE BAUD RATE, TIMER CLOCK SOURCE The only difference between Mode 2 and Mode 3 is that the baud rate is a variable in Mode 3. When REN=1 data receiving is enabled. The baud rate is variable and depends from Timer 1 or Timer 2 mode. To enable Timer 2 clocking set the TCLK, RCLK bits located in T2CON (0xC8) register. SMOD bit is ignored when UART is clocked by Timer2. Figure13.6 Sep., 2014, Version 0.6 (Preliminary) UART transmission mode 3 timing diagram 73 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 14. IIC interface 2 2 2 TI A L A8105’s I C peripheral provides two-wire interface between the device and I C -compatible device by the two-wire I C serial bus. 2 The I C peripheral supports the following functions. 2  Conforms to v2.1 of the I C specification (published by Philips Semiconductor)  Master transmitter / receiver  Slave transmitter / receiver  Flexible transmission speed modes: Standard (up to 100 Kb/s) and Fast (up to 400Kb/s)  Multi-master systems supported 2  Supports 7-bit addressing modes on the I C bus  Interrupt generation  Allows operation from a wide range of input clock frequencies (build-in 8-bit timer) PIN 23 and PIN 24 are I2C Interface in A8105. The alternate function is Port 0.5 and Port 0.6. User can set BBSEL (BBH) to set up the PIN function. Please refer the Chapter 11 for more detail information. TYPE INPUT /OUTPUT INPUT/ OUTPUT Table14.1 2 I2C interface pins description FI D 14.1 Master mode I C DESCRIPTION 2 I C clock input /output 2 I C data input /output EN PIN SCL(P0.5) SDA(P0.6) 2 2 N The I C master mode provides an interface between a microprocessor and an I C bus. It can be programmed to operate 2 with arbitration and clock synchronization to allow it to operate in multi‐master systems. Master mode I C supports transmission speeds up to 400Kb/s. 2 14.1.1 I C REGISTERS C O There are six registers used to interface to the host: the Control, Status, Slave Address, Transmitted Data, Received Data and Timer Period Register.  Table14.3 I2C Registers for writing Register Slave address – I2CMSA Status – I2CMSR Received data - I2CBUF Timer period - I2CMTP Table14.4 Address 0xF4 0xF5 0xF6 0xF7 Address 0xF4 0xF5 0xF6 0xF7 I2C Registers for reading M IC C O M Register Slave address – I2CMSA Control – I2CMCR Transmitted data I2CBUF Timer period - I2CMTP 2 A I C Master mode Timer Period Register To generate wide range of SCL frequencies the core have built‐in 8‐bit timer. Programming sequence must be done at least once after system reset. After reset, register have 0x01 value by default. SCL_PERIOD = 2 x (1+TIMER_PRD) x (SCL_LP + SCL_HP) x CLK_PRD For example： - CLK_PRD = 62.5ns (CLK_FRQ = 16MHz)； - TIMER_PRD =3； - SCL_LP = 6；(fixed) - SCL_HP = 4; (fixed) SCL_PERIOD = 2 x (1 + 3) x (6 + 4 ) x 62.5ns = 5000ns = 5us SCL_FREQUENCY = 1 / 5us = 200 KHz SCL_PRD - SCL line period (I2C clock line) TIMER PRD -Timer period register value (range 1 to 255) Sep., 2014, Version 0.6 (Preliminary) 74 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC CLK_PRD I2CMTP - System clock period (1/fclk) (0xE7) Address/Name R/W E7h R/W I2CMTP Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 P.6 P.5 P.4 P.3 P.2 P.1 P.0 0 0 0 0 0 0 0 1 2  I2CMCR (0xF5) ADDR 0 0 0 0 0 0 RSTB SLRST ADDR 0 ACK STOP START RUN 0 0 START 1 RUN 1 0 0 - 1 1 1 0 1 0 0 1 1 1 0 1 1 1 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 Table14.5 ADDR HS STOP 0 0 SLRST Bit 2 ACK - 0 RSTB Bit 3 0 0 0 Bit 4 R/S 0 IC M Bit 5 A 0 0 Bit 6 HS 0 O SLRST 0 R/W Bit 7 0 C RSTB 0 R/W M Address/Name F5h I2CMCR Reset C O N FI D EN TI A L I C CONTROL AND STATUS REGISTERS The Control Register consists of eight bits: the RUN, START, STOP, ACK, HS, ADDR, SLRST and RSTB bit. The RSTB bit 2 performs reset of whole I C controller and behaves identically as external reset provided by RST pin. Using this bit software 2 2 2 application can reinitialize I C mater module when some problem is encountered on I C bus. In case when I C Slave device 2 2 blocks I C bus, then SLRST bit should be set along with RUN bit (just after issuing the RSTB). SLRST bit causes that I C master module generates 9 SCK clocks (no START is generated) to recover Slave device to known state and issues at the end STOP. This bit is automatically cleared by I2C MASTER MODULE, thus, it is always read as ‘0’. The BUSY bit should be checked to know when this transmission is ended. The START bit will cause the generation of the START, or REPEATED START condition. The STOP bit determines if the cycle will stop at the end of the data cycle, or continue on to a burst. To generate a single send cycle, the Slave Address register is written with the desired address, the R/S bit is set to ‘0’, and Control Register is written with HS=0, ACK=x, STOP=1, START=1, RUN=1 (binary xxx0x111 x‐mean 0 or 1) to perform the operation and stop. When the operation is completed (or aborted due an error), the interrupt is generated. The data may be read from Received Data Register. When I2C MASTER MODULE core operates in Master receiver mode the ACK bit must be set normally to logic 1. This cause the I2C MASTER MODULE bus controller to send acknowledge automatically after each byte. This bit must be reset when the I2C MASTER MODULE bus controller requires no further data to be sent from slave transmitter. The ADDR bit along with RUN bit cause the generation of the START condition and transmission of Slave Address. Next STOP can end transmission, or REPEATED START generates the START and ADDRRESS sequence once again. In both 2 cases STOP can ends transmission. See I C MASTER MODULE ACK Polling chapter for details. HS R/S Sep., 2014, Version 0.6 (Preliminary) ACK Bit 1 0 0 Bit 0 0 OPERATION START condition followed by SEND (Master remains in Transmitter mode) START condition followed by SEND and STOP condition START condition followed by RECEIVE operation with negative Acknowledge (Master remains in Receiver mode) START condition followed by RECEIVE and STOP condition START condition followed by RECEIVE (Master remains in Receiver mode) forbidden sequence Master Code sending and switching to High‐speed mode I2CM module software reset Reset slaves connected to I2C bus by generating 9 SCK clocks followed by STOP START condition followed by Slave Address Control bits combinations permitted in IDLE state * STOP START 75 RUN OPERATION AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 0 - - 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 - 1 1 0 0 0 1 0 1 1 0 0 0 0 0 - 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 1 0 0 1 0 1 - 1 0 1 1 1 1 Control bits combinations permitted in Master Transmitter mode FI D Table14.6 SLRST 0 ADDR 0 HS 0 R/S - ACK 0 STOP 0 START 0 RUN 1 0 0 0 0 0 0 0 0 0 0 0 0 - 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 1 1 1 1 0 1 1 O C O 0 1 - 0 1 1 0 0 - 1 1 1 - - - - - M 1 0 C 0 IC 0 N RSTB 0 0 - SEND operation (Master remains in Transmitter mode) STOP condition SEND followed by STOP condition Repeated START condition followed by SEND (Master remains in Transmitter mode) Repeated START condition followed by SEND and STOP condition Repeated START condition followed by RECEIVE operation with negative Acknowledge (Master remains in Receiver mode) Repeated START condition followed by SEND and STOP condition Repeated START condition followed by RECEIVE (Master remains in Receiver mode) forbidden sequence I2CM module software reset Repeated START condition followed by Slave Address L 0 TI A 0 EN 0 Control bits combinations permitted in Master Receiver mode M Table14.7 OPERATION RECEIVE operation with negative Acknowledge (Master remains in Receiver mode) STOP condition** RECEIVE followed by STOP condition RECEIVE operation (Master remains in Receiver mode) forbidden sequence Repeated START condition followed by RECEIVE operation with negative Acknowledge (Master remains in Receiver mode) Repeated START condition followed by RECEIVE and STOP condition Repeated START condition followed by RECEIVE (Master remains in Receiver mode) Repeated START condition followed by SEND (Master remains in Transmitter mode) Repeated START condition followed by SEND and STOP condition I2CM module software reset A The status Register is consisted of six bits：the BUSY bit, the ERROR bit, the ADDR_ACK bit, the DATA_ACK bit, the ARB_LOST bit, and the IDLE bit. I2CMSR (0xF5) Address/Name R/W F5h R/W I2CMSR Reset 0x20 Bit 7 0 Bit 6 BUS_ BUSY 0 Bit 5 Bit 4 ARB_ LOST 0 IDLE 1 Bit 3 DATA_ ACK 0 Bit 2 ADDR_ ACK 0 Bit 1 Bit 0 ERROR BUSY 0 0 IDLE：This bit indicates that I2C BUS controller is in the IDLE state。 BUSY：This bit indicates that I2C BUS controller receiving, or transmitting data on the bus, and other bits of Status register are no valid; BUS_BUSY：This bit indicates that the Bus is Busy, and access is not possible. This bit is set / reset by START and STOP conditions; Sep., 2014, Version 0.6 (Preliminary) 76 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC ERROR：This bit indicates that due the last operation an error occurred: slave address wasn’t acknowledged, data wasn’t acknowledged, or I2C Bus controller lost the arbitration; ADDR_ACK：This bit indicates that due the last operation slave address wasn’t acknowledged; ARB_LOST：This bit indicates that due the last operation I2C Bus controller lost the arbitration; transmitted  (0xF4) Address/Name R/W F4h R/W I2CMCA Reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A.6 A.5 A.4 A.3 A.2 A.1 A.0 R/S 0 0 0 0 0 0 0 0 2 FI D I2CBUF EN I C Buffer – RECEIVER AND TRANSMITTER REGISTERS I2C module has two separated 1 byte buffer in receiver and transmitter and these are located in the same address (0xF6). The Transmitted Data Register consists of eight data bits which will be sent on the bus due the next Send, or Burst Send operation. The first send bit is D.7 (MSB). (0xF6) Address/Name R/W F6h R/W I2CBUF Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D.7 D.6 D.5 D.4 D.3 D.2 D.1 D.P 0 0 0 0 0 0 N  Bit 7 TI A I2CMSA L SLAVE ADDRESS REGISTER The Slave address Register consists of eight bits：Seven address bits (A6-A0), and Receive/ not send bit R/S. The R/S bit determines if the next operation will be a Receive (high), or Send (low). 0 0 I2CBUF (0xF6) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D.7 D.6 D.5 D.4 D.3 D.2 D.1 D.P 0 0 0 0 0 0 0 0 O M Address/Name R/W F6h R/W I2CBUF Reset C O The Receiver Data Register consists of eight data bits which have been received on the bus due the last receive, or Burst Receive operation. C 14.2.4 I2C MASTER MODULE AVAILABLE SPEED MODES I2C MASTER MODULE STANDARD MODE Typical configuration values for Standard speed mode： M  IC Default transmission parameter/constant values are shown in sections below. SCL clock frequency can be changed by modification of timer period values as show in the table below. A The following table gives an example parameters for standard I2C speed mode. System clock TIMER_PERIOD Transmission speed 4 MHz 1 (01h) 100kb/s 6 MHz 2 (02h) 100kb/s 10 MHz 4 (04h) 100kb/s 16 MHz 7 (07h) 100kb/s 20 MHz 9 (09h) 100kb/s Table14.8  I2C MASTER MODULE Timer period values for standard speed mode I2C MASTER MODULE FAST MODE Typical configuration values for Fast speed mode： The following table gives example parameters for Fast I2C speed mode. Sep., 2014, Version 0.6 (Preliminary) 77 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC System clock TIMER_PERIOD Transmission speed 10 MHz 1 (01h) 250 Kb/s 16 MHz 1 (01h) 400 Kb/s 20 MHz 2 (02h) 333 Kb/s Table14.8 I2C MASTER MODULE Timer period values for Fast speed mode 14.2.5 I2C MASTER MODULE AVAILABLE COMMAND SEQUENCES I2C MASTER MODULE SINGLE SEND L  TI A IDLE Write Slave Address to I2CSA register This sequence may be omitted in single-Master systems EN Write Data to I2CBUF register NO FI D Read I2CCR register Bus Busy=“0” C O Write ,,---0-111”to I2CCR register N YES Read I2CCR register M NO O Bus Busy=“0” Error =“0” IC C YES IDLE NO Error service IDLE Figure14.4 I2C MASTER MODULE Single SEND flowchart A M YES Sep., 2014, Version 0.6 (Preliminary) 78 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC  I2C MASTER MODULE SINGLE RECEIVE IDLE Write Slave Address to I2CSA register L This sequence may be omitted in single-Master systems NO TI A Read I2CCR register Bus Busy=“0” EN YES Read I2CCR register Bus Busy=“0” YES C O YES N NO FI D Write ,,---00111”to I2CCR register Error =“0” NO Error service IDLE IDLE Figure14.5 Single RECEIVE flowchart A M IC C O M Read Data from I2CBUF register Sep., 2014, Version 0.6 (Preliminary) 79 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC  I2C MASTER MODULE BURST SEND IDLE Write Slave Address to I2CSA register This sequence may be omitted in single-Master systems L Write Data to I2CBUF register NO TI A Read I2CCR register Bus Busy=“0” YES EN Write ,,---0-011”to I2CCR register Bus Busy=“0” NO NO C O Error =“0” N YES FI D Read I2CCR register YES Write Data to I2CBUF register Index = n M NO IC C O Write ,,---0-001”to I2CCR register NO Write ,,---0-100”to I2CCR register YES Error service Error service IDLE IDLE Write ,,---0-101”to I2CCR register Read I2CCR register NO Bus Busy=“0” M YES YES Error =“0” A IDLE NO Error service IDLE Figure14.6 Sep., 2014, Version 0.6 (Preliminary) YES Arb_Lost =‘1’ I2C MASTER MODULE Sending n bytes flowchart 80 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC  I2C MASTER MODULE BURST RECEIVE IDLE This sequence may be omitted in single-Master systems Write Slave Address to I2CSA register Bus Busy=“0” TI A NO L Read I2CCR register YES EN Write ,,---01011”to I2CCR register Bus Busy=“0” NO YES C O YES NO N Error =“0” FI D Read I2CCR register Read Data from I2CBUF register NO YES M Index = m-1 O Write ,,---01001”to I2CCR register Arb_Lost =‘1’ YES NO Write ,,---0-100”to I2CCR register Error service Error service IDLE IDLE Write ,,---00101”to I2CCR register C Read I2CCR register IC NO Bus Busy=“0” M YES YES Error =“0” A Read Data from I2CBUF register Error service IDLE IDLE Figure14.7 Sep., 2014, Version 0.6 (Preliminary) NO I2C MASTER MODULE Receiving m bytes flowchart 81 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC I2C MASTER MODULE BURST RECEIVE AFTER BURST SEND C O N FI D EN TI A L  M I2C MASTER MODULE Sending n bytes then Repeated Start and Receiving m bytes flowchart A M IC C O Figure14.8 Sep., 2014, Version 0.6 (Preliminary) 82 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC I2C MASTER MODULE BURST SEND AFTER BURST RECEIVE I2C MASTER MODULE Receiving m bytes then Repeated Start and Sending n bytes flowchart C O Figure14.9 M C O N FI D EN TI A L  A M IC Figure14.10 I2C MASTER MODULE Single RECEIVE with 10-bit addressing flowchart Sep., 2014, Version 0.6 (Preliminary) 83 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC  I2C MASTER MODULE ACK POLLING IDLE Write Slave Address to I2CSA register NO TI A L Read I2CCR register BUS BUSY= ‘0’ EN YES FI D Write ,,00100001" to I2CCR register Read I2CCR register N NO C O BUSY= ‘0’ YES NO M YES ADDR_ACK=‘0’ O Burst Send or Stop C Write ,,00100011" to I2CCR register NO A M IC Read I2CCR register BUSY= ‘0’ YES YES ADDR_ACK=‘0’ NO Burst Send or Stop Figure14.11 I2C MASTER MODULE ACK Polling flowchart Sep., 2014, Version 0.6 (Preliminary) 84 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 14.3 I2C MASTER MODULE INTERRUPT GENERATION I2C MASTER MODULE interrupt flag is automatically asserted when I2C transfer (send or receive a byte) is completed or transfer error has occurred. I2CMIF flag has to be cleared by software. Interrupt flag I2CMIF Function Internal, I2C MASTER MODULE Active level/edge - Flag resets Software Vector 0x6B Natural priority 14 Table14.11 I2C MASTER MODULE interrupt summary EIE TI A L I2C MASTER MODULE related interrupt bits have been summarized below. The IE (0xA8) contains global interrupt system disable (0) / enable (1) bit called EA. (0xE8) EN Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 E8h EI2CS R/W EI2CM EWDI EKEYINT ERFINT EINT4 EINT3 EINT2 EIE ESPI Reset 0 0 0 0 0 0 0 0 EIP FI D EI2CM：Enable I2C MASTER MODULE interrupts (0xF8) C O N Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F8h PI2CS R/W PI2CM PWDI PKEYINT PRFINT PINT4 PINT3 PINT2 EIP PSPI Reset 0 0 0 0 0 0 0 0 PI2CM：I2C MASTER MODULE priority level control (at 1-high-level) EIF (0x91) O M Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 91h I2CSF R/W I2CMF - KEYINTF RFINTF INT4F INT3F INT2F EIF SPIF Reset 0 0 0 0 0 0 0 0 IC C I2CMIF：I2C MASTER MODULE interrupt flag It must be cleared by software writing logic ‘1’. Writing ‘0’ does not change its content. 14.5 Slave mode I2C 2 2 A M The I C module provides an interface between a microprocessor and I C bus. It can works as a slave receiver or transmitter 2 depending on working mode determined by microprocessor/microcontroller. The core incorporates all features required by I C 2 specification. The I C module supports all the transmission modes: Standard and Fast. 14.5.1 I2C MODULE INTERNAL REGISTERS There are five registers used to interface to the target device：The Own Address, Control, Status, Transmitted Data and Received Data registers. Register Own address – I2CSOA Control – I2CSCR Transmitted data – I2CSBUF Address 0xF1 0xF2 0xF3 Table14.12 I2C MODULE Registers for writing Register Own address – I2CSOA Control – I2CSSR Sep., 2014, Version 0.6 (Preliminary) 85 Address 0xF1 0xF2 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Received data – I2CSBUF Table14.13 0xF3 I2C MODULE Registers for reading I2CSOA – OWN ADDRESS REGISTER 2 2 The Own Address Register consists of seven address bits which identify I C module core on I C Bus. This register can be read and written at the address 0xF1. I2CSOA (0xF1)  Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - A.6 A.5 A.4 A.3 A.2 A.1 A0 0 0 0 0 0 0 0 0 L Bit 7 TI A Address/Name R/W F1h R/W I2CSOA Reset I2CSCR – CONTROL AND STATUS REGISTERS 2 The Control Register consists of the bits：The RSTB and DA bit. The RSTB bit performs reset of whole I C controller and 2 behaves identically as external reset provided by RST pin. Using this bit software application can reinitialize I C module when 2 2 some problem is encountered on I C bus. The DA bit enables (‘1’) and disable (‘0’) the I C module device operation. DA is set immediately to ‘1’ when MCU write DA=1. This register can be only written at address 0xF2. Reading this address puts status register on data bus – see below. (0xF2) FI D I2CSCR EN  2 N Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F2h R/W RSTB DA - RECFINCLR SENDFINCLR I2CSCR Reset 0 0 0 0 0 0 0 0 C O DA：Device Active – enable or disable the I C module device operation; 2 RSTB：Reset of whole I C controller by writing ‘1’ to this bit. It behaves identically as RST pin RECFINCLR：Writing ‘1’ to this bit clears RECFIN bit from the I2C MODULE status register. SENDFINCLR：Writing ‘1’ to this bit clears SENDFIN bit from the I2C MODULE status register. M IC C O M The Status Register consists of five bits: the DA, BUSACTIVE, RECFIN, SENDFIN bit, RREQ bit, TREQ bit. The receive finished RECFIN bit indicates that Master I2C controller has finished transmitting of data during single or burst receive operations. It also causes generation of interrupt on IRQ pin. The send finished SENDFIN bit indicates that Master I2C controller has finished receiving of data during single or burst send operations. It also causes generation of interrupt on IRQ pin. 2 2 The Receive Request RREQ bit indicates that I C module device has received data byte from I2C master. I C module host device (usually MCU) should read one data byte from the Received Data register I2CSBUF. The Transmit Request TREQ bit 2 indicates that I2C MODULE device is addressed as Slave Transmitter and I C module host device (usually MCU) should write one data byte into the Transmitted Data register I2CSBUF. The BUSACTIVE ‘1’ signalizes that any transmission (send, receive 2 or own address detection) is in progress. BUSACTIVE is cleared (‘0’) automatically by I C module in case when there is no any transmission. This is read only bit. The DA bit should be polled (read) when MCU wrote DA=0. The DA bit is not immediately cleared when any I2C transmission (send, receive or own address detection) is in progress. When current transmission has completed then this bit is 2 cleared to ‘0’ and I C module become inactive. (0xF2) A I2CSSR Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F2h R/W DA - BUSACTIVE RECFIN SENDFIN TREQ RREQ I2CSSR Reset 0 0 0 0 0 0 0 0 DA：Device Active – enable (‘1’) or disable (‘0’) the I2C MODULE device operation; BUSACTIVE：Bus ACTIVE – ‘1’ signalizes that any transmission: send, receive or own address detection is in progress; 2 2 RREQ：Indicates that I C module device has received data byte from I C master; It is automatically cleared by read of I2CSBUF. 2 TREQ：Indicates that I C module device is addressed as transmitter and requires data byte from host device; It is automatically cleared by write data I2CSBUF. Sep., 2014, Version 0.6 (Preliminary) 86 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC RECFIN：Indicates that Master I2C controller has ended transmit operation. It means that no more RREQ will be set during 2 2 this single or burst I C module receive operation. It is cleared by writing ‘1’ to the RECFINCLR bit in the I C module control register. SENDFIN：Indicates that Master I2C controller has ended receive operation. It means that no more TREQ will be set during 2 this single or burst I C module send operation. It is cleared by writing ‘1’ to the SENDFINCLR bit in the I2C control register. NOTE：All bits are active at HIGH level (‘1’). I2CSBUF – RECEIVER AND TRANSMITTER REGISTERS The Transmitter Data Register consists of eight Data bits which will be sent on the bus due the next Send operation. The first send bit is the D.7(MSB). I2CSBUF (0xF3) TI A L  (0xF3) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W D.7 D.6 D.5 D.4 D.3 D.2 D.1 D.0 0 0 0 0 0 0 0 0 N Address/Name F3h I2CSBUF Reset FI D I2CSBUF EN Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F3h R/W D.7 D.6 D.5 D.4 D.3 D.2 D.1 D.0 I2CSBUF Reset 0 0 0 0 0 0 0 0 The Receiver Data Register consists of eight data bits which have been received on the bus due the last Receive operation. C O 14.7 AVAILABLE I2C MODULE TRANSMISSION MODES 2 This chapter describes all available transmission modes of the I C module core. Default I2C own address for all presented waveforms is 0x39 (“0111001”). 2 14.7.1 I C module SINGLE RECEIVE C O M The figure below shows a set of sequences during Single data Receive by I2C MODULE. Single receive sequences：  Start condition 2  I C module is addressed by I2C Master as receiver 2  Address is acknowledged by I C module 2  Data is received by I C module 2  Data is acknowledged by I C module  Stop condition 2 14.7.2 I C module SINGLE SEND A M IC The figure below shows a set of sequences during Single data Send by I2C MODULE. Single send sequences：  Start condition 2  I C module is addressed by I2C Master as transmitter 2  Address is acknowledged by I C module 2  Data is transmitted by I C module  Data is not acknowledged by I2C Master  Stop condition 2 14.7.3 I C module BURST RECEIVE 2 The figure below shows a set of sequences during Burst data Receive by I C module. Burst receive sequences：  Start condition 2  I C module is addressed by I2C Master as receiver 2  Address is acknowledged by I C module 2  (1)Data is received by I C module 2  (2)Data is acknowledged by I C module  STOP condition Sequences (1) and (2) are repeated until Stop condition occurs. Sep., 2014, Version 0.6 (Preliminary) 87 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 2 14.7.4 I C module BURST SEND 2 2 14.7.5 AVAILABLE I C module COMMAND SEQUENCES FLOWCHART IDLE TI A L The figure below shows a set of sequences during Burst Data Send by I C module. Burst send sequences：  Start condition 2  I C module is addressed by I2C Master as transmitter 2  Address is acknowledged by I C module 2  (1)Data is transmitted by I C module  (2)Data is acknowledged by I2C Master  (3)Last data is not acknowledged by I2C Master  Stop condition Sequences (1) and (2) are repeated until last transmitted data is not acknowledged (3) by I2C Master. software reset EN Write own Address to I2CSOA register Write ,,1-------“ to I2CSCR register FI D Write ,,01------“ to I2CSCR register C O N Read I2CSCR register RREQ = ‘1’ A M IC C O M NO (Burst) Send is done Clear SENDFIN bit TREQ = ‘1’ NO YES YES Read data from I2CSBUF register YES write data to I2CSBUF register SENDFIN = ‘1’ NO RECFIN = ‘1’ NO YES (Burst) Receive is done Clear RECFIN bit Figure14.20 Available I2C MODULE command sequences flowchart Sep., 2014, Version 0.6 (Preliminary) 88 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 14.8 I2C MODULE INTERRUPT GENERATION I2C MODULE interrupt flag is automatically asserted when I2C transfer (send or receive a byte) is completed or transfer error has occurred. I2CSIF flag has to be cleared by software. Interrupt flag I2CSIF Function Internal, DI2CS Active level/edge - Table14.16 Flag resets Software Vector 0x73 Natural priority 15 I2C MODULE interrupt summary (0xE8) Address/Name E8h EIE Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EI2CS R/W EI2CM EWDI EKEYINT ERFINT EINT4 EINT3 EINT2 ESPI 0 0 0 0 0 0 0 0 EN EIE TI A L I2C MODULE related interrupt bits have been summarized below. The IE (0xA8) contains global interrupt system disable (0) / enable (1) bit called EA. EI2CS：Enable I2C MODULE interrupts Address/Name F8h EIP FI D (0xF8) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PI2CS R/W PI2CM PWDI PKEYINT PRFINT PINT4 PINT3 PINT2 PSPI 0 0 0 0 0 0 0 0 C O Reset N EIP PI2CS：I2C MODULE priority level control (at 1-high-level) EIF (0x91) R/W O Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2CSF I2CMF KEYINTF RFINTF INT4F INT3F INT2F SPIF M Address/Name 91h EIF 0 0 0 0 0 0 0 0 A M IC C I2CSIF：I2C MODULE interrupt flag Software should determine the source of interrupt by check both modules’ interrupt related bits. It must be cleared by software writing 0x80. It cannot be set by software. Sep., 2014, Version 0.6 (Preliminary) 89 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 15. SPI interface C O M C O N FI D EN TI A L The SPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. The SPI allows the microcontroller to communicate with serial peripheral devices. It is also capable of inter-processor communications in a multi‐master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. The SPI is a technology independent design that can be implemented in a variety of process technologies. The SPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device. Data rates as high as System clock divided by four (CLK/4). Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. The SPI automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O), and address SPI slave device to exchange serially shifted data. Error‐detection logic is included to support inter-processor communications. A write‐collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple‐master mode‐fault detector automatically disables SPI output drivers if more than one SPI devices simultaneously attempts to be become bus master. IC 15.1 KEY FEATURES All features listed below are included in the current version of SPI core. SPI Master  Full duplex synchronous serial data transfer  Master operation  Multi-master system supported  Up to 8 SPI slaves can be addressed  System error detection  Interrupt generation  Supports speeds up to 1/4 up to system clock  Bit rates generated 1/4, 1/8, 1/32, 1/64, 1/128, 1/512 of system clock  Four transfer formats supported  Simple interface allows easy connection to microcontrollers SPI Slave  Full duplex synchronous serial data transfer  Slave operation  System error detection  Interrupt generation  Supports speeds up to 1/4 of system clock  Simple interface allows easy connection to microcontrollers A M   Sep., 2014, Version 0.6 (Preliminary) 90 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC   Four transfer formats supported Fully synthesizable, static synchronous design with no internal tri-states 15.2 SPI PINS DESCRIPTION ACTIVE low DESCRIPTION SPI clock input / output Master serial data input / Slave serial data output Slave serial data input / Master serial data output Slave select output L TYPE INPUT / OUTPUT INPUT / OUTPUT INPUT / OUTPUT OUTPUT Table15.1 SPI pins description 15.3 SPI HARDWARE DESCRIPTION 15.3.1 BLOCK DIAGRAM TI A PIN Scki_Scko(P0.0) MISO(P0.1) SIMO(P0.2) SSO(P0.3) A M IC C O M C O N FI D EN When an SPI transfer occurs, an 8‐bit character is shifted out on data pin while a different 8‐bit character is simultaneously shifted in a second data pin. Another way to view this transfer is that an 8‐bit shift register in the master and another 8‐bit shift register in the slave are connected as a circular 16‐bit shift register. When a transfer occurs, this distributed shift register is shifted eight bit positions; thus, the characters in the master and slave are effectively exchanged. The central element in the SPI system is the block containing the shift register and the read data buffer. The system is single buffered in the transmit direction and double buffered in the receive direction. This fact means new data for transmission cannot be written to the shifter until the previous transaction is complete; however, received data is transferred into a parallel read data buffer so the shifter is free to accept a second serial character. As long as the first character is read out of the read data buffer before the next serial character is ready to be transferred, no overrun condition will occur. Figure 15.2 SPI Block Diagram The eight pins are associated with the SPI: the SS, clock pins SCKI, SCKO and SCKEN, master pins MI and MO and slave pins SOEN, SI and SO. The SS input pin in a master mode is used to detect mode‐fault errors. A low on this pin indicates that some other device in a multi‐master system has become a master and trying to select the SPI MODULE as a slave. The SS input pin in a slave mode is used to enable transfer. The SCKI pin is used when the SPI is configured as a slave. The input clock from a master synchronizes data transfer between a master and the slave devices. The slave device ignore the SCKI signal unless the SS (slave select) pin is active low. The SCKO and SCKEN pins are used as the SPI clock signal reference in a master mode. When the master initiates a transfer eight clock cycles is automatically generated on the SCKO pin. Sep., 2014, Version 0.6 (Preliminary) 91 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC When the SPI is configured as a slave the SI pin is the slave input data line, and the SO is the slave output data line. When the SPI is configured as a master, the MI pin is the master input data line, and the MO is the master output data line. 15.3.2 INTERNAL REGISTERS  SPI Control Register The control register may be read or written at any time, is used to configure the SPI System. SPCR (0xEC) Bit 7 Bit 6 Bit 5 R/W SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0 0 0 Reset 0 Bit 4 0 Bit 3 Bit 2 0 1 Bit 1 0 Bit 0 L R/W 0 TI A Address/Name ECh EIE O M C O N FI D EN SPIE：SPI interrupt enable = 0, interrupts are disabled, polling mode is used = 1, interrupts are enabled SPE：SPI system enable = 0, system is off = 1, system is on MSTR：Master/Slave mode select = 0, slave = 1, master CPOL：Clock polarity select = 0, high level; SCK idle low = 1, low level; SCK idle high CPHA：Clock phase.. Select one of two different transfer formats SPR[2:0]：SPI clock rate select bits. See the table below SPR2 SPR1 SPR0 System clock divided by 0 0 0 4 0 0 1 8 0 1 0 16 0 1 1 32 1 0 0 64 1 0 1 128 1 1 0 256 1 1 1 512  IC C Slave Select Control Register The control register may be read or written at any time. It is used to configure which slave select output should be driven while SPI master transfer. Contents of SSCR register is automatically assigned on SS7O‐SS0O pins when SPI master transmission starts. SSCR (0xEF) M Address/Name EFh SSCR Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W SS7 SS6 SS5 SS4 SS3 SS2 SS1 SS0 1 1 1 1 1 1 1 A 1 SS7 – SS0 = 0, Pin SSxO assigned while Master Transfer = 1, Pin SSxO is forced to logic 1  SPI Status Register SPSR (0xED) Address/Name EDh Sep., 2014, Version 0.6 (Preliminary) R/W R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 SPIF WCOL MODF - 92 Bit 2 - Bit 1 Bit 0 SSCEN AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC EIE Reset 0 0 0 0 0 1 0 0 is in process. TI A L SPIF：SPI interrupt request. The flag is automatically set to one at the end of an SPI transfer. WCOL：Write collision error status flag. The flag is automatically set if the SPDR is written while a transfer MODF：SPI mode-fault error status flag This flag is set if SS pin goes to active low while the SPI is configured as a master (MSTR = 1) SSCEN： = 1, auto SS assertions enabled = 0, auto SS assertions disabled – SSO always shows contents of SSCR FI D EN SPI status register (SPSR) contains flags indicating the completion of transfer or occurrence of system errors. All flags are set automatically when the corresponding event occur and cleared by software sequence. SPIF and WCOL are automatically cleared by reading SPSR followed by an access of the SPDR. MODF flag is cleared by reading SPSR with MODF set followed by a write to SPCR. The SSCSEN bit is a enable bit of automatic Slave Select Outputs assertion. When SSCEN is set (‘1’) then during master transmission the SSXO lines are automatically loaded with contents of SSCR register before each byte transfer, and deasserted when byte is transferred. When SSCEN bit is cleared the SSXO lines always shows contents of the SSCR register, regardless of the transmission is in progress or SPI MODULE is in IDLE state.  Receiver and Transmitter Registers The Transmitted Data Register consists of eight data bits, which will be sending on the bus due the next Send operation. The first send bit is the D.7 (MSB). SPDR (0xEE) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EEh SPDR R/W D.7 D.6 D.5 D.4 D.3 D.2 D.1 D.0 0 0 0 0 0 1 0 0 C O Reset N Address/Name The Received Data Register consists of eight data bits, which were received on the bus due the last Receive operation. SPDR (0xEE) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EEh SPDR R/W D.7 D.6 D.5 D.4 D.3 D.2 D.1 D.0 0 0 0 0 0 1 0 0 O M Address/Name C Reset IC 15.4 MASTER OPERATIONS A M When the SPI MODULE core is configured as a SPI master, the transfer is initiated by write to the SPDR register. When the new byte is written to the SPDR register, SPI MODULE begins transfer on the nearest BAUD timer overflow. The serial clock SCK is generated by the SPI MODULE. In master mode the SPI MODULE activates the SCKEN to enable the SCK output driver. The SPI MODULE in master mode can select one of the eight SPI slave devices, through the SSxO lines. The SSxO lines – Slave Select output lines are loaded with contents of the SSCR register (0x03). The SSCEN bit from the SPSR register select between automatic SSxO lines control and software control. When set the automatic Slave Select outputs assertion is enabled. With SSCEN bit set in master mode the SSXO lines are automatically loaded with contents of SSCR register before each byte transfer, and deasserted when byte is transferred. When SSCEN bit is cleared the SSXO lines are controlled by the software, and always shows contents of the SSCR register, regardless of the transmission is in progress or the SPI MODULE is in IDLE state. Sep., 2014, Version 0.6 (Preliminary) 93 AMICCOM Electronics Corporation A8105 Automatic slave select lines assertion 15.4.1 MASTER MODE ERRORS Software controlled SSxO lines C O Figure15.4 N FI D EN Figure15.3 TI A L 2.4GHz FSK/GFSK SoC M In master mode two system errors can be detected by the SPI MODULE. The first type of error arises in multiple‐master system when more than one SPI device simultaneously tries to be a master. This error is called a Mode Fault. The second error type, a Write Collision, indicates that MCU tried to write the SPDR register while transfer was in progress.  IC C O MODE FAULT ERROR Mode fault error occurs when the SPI MODULE is configured as a master and some other SPI master device will select this device as if it were a slave. If a Mode Fault Error occur：  The MSTR bit is forced to zero to reconfigure the SPI MODULE as a slave.  The SPE bit is forced to zero to disable the SPI MODULE system  The MODF status flag is set and an interrupt request is generated A M The MODF flag is cleared by reading SPSR with MODF set followed by a write to SPCR Figure15.5 Sep., 2014, Version 0.6 (Preliminary) Mode Fault Error generation 94 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC  Figure15.6 15.5 SLAVE OPERATIONS FI D EN TI A L WRITE-COLLISION ERROR A write collision occurs if the SPI MODULE data register is written while a transfer is in progress. The transfer continues undisturbed, and the write data that caused the error is not written to the shifter. The Write Collision is indicated by the WCOL flag in SPSR (3) register. The WCOL flag is set automatically by hardware, when the WCOL error condition occurs. To clear the WCOL bit, user should execute the following sequence:  Read contents of the SPSR register  Perform access to the SPDR register ( read or write ) Write Collision Error in SPI Master mode 15.5.1 SLAVE MODE ERRORS C O N When configured as SPI Slave the SPI MODULE transfer is initiated by external SPI master module by assertion of the SPI MODULE Slave Select input, and generation of the SCK serial clock. Before transfer starts, the SPI master has to assert the Slave Select line to determine which SPI slave will be used to exchange data. The SS is asserted (cleared = 0), the clock signal connected to the SXCK line will cause the SPI MODULE slave to shift into receiver shift register contents of the MOSI line, and drives the MISO line with contents of the Transmitter Shift register. When all eight bits are shifted in/out the SPI MODULE generates the Interrupt request by setting the IRQ output. In SPI MODULE slave mode only one transfer error is possible – Write Collision Error. C O M In slave mode, only the Write Collision Error can be detected by the SPI MODULE. The Write Collision Error occurs when the SPDR register write is performed while the SPI MODULE transfer is in progress. In SLAVE mode when the CPHA is cleared, the write collision error may occur as long as the SS Slave Select line is driven low, even if all bits are already transferred. This is because there is not clearly specified the transfer beginning, and SS driven low after full byte transfer may indicate beginning of the next byte transfer.  A M IC WRITE-COLLISION ERROR A write collision occurs if the SPI MODULE data register is written while a transfer is in progress. The transfer continues undisturbed, and the write data that caused the error is not written to the shifter. The Write Collision is indicated by the W COL flag in SPSR (3) register. The WCOL flag is set automatically by hardware, when the WCOL error condition occurs. To clear the WCLO bit, user should execute the following sequence:  Read contents of the SPSR register  Perform access to the SPDR register ( read or write ) Figure15.7 Sep., 2014, Version 0.6 (Preliminary) Write Collision Error – SPI Slave mode – SPDR write during transfer 95 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Figure15.8 EN TI A L Figure below shows the WCOL generation, in case that the CPHA is cleared. As it is shown the WCOL generation is cause by any S{DR register write with SS line cleared. It is done even if the SPI master didn’t generate the serial clock SCK. This is because there is not clearly specified the transfer beginning, and SS driven low after full byte transfer may indicate beginning of the next byte transfer. WCOL Error-SPI Slave mode-SPDR write when CPHA = 0 and SS = 0 FI D 15.6 CLOCK CONTROL LOGIC 15.6.1 SPI CLOCK PHASE AND POLARITY CONTROLS C O N Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock and has no significant effect on the transfer format. The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers to allow a master device to communicate with peripheral slaves having different requirements. The flexibility of the SPI system on the SPI MODULE allows direct interface to almost any existing synchronous serial peripheral. 15.6.2 SPI MODULE TRANSFER FORMATS M During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. On a master SPI device, the slave select line can optionally be used to indicate a multiple‐master bus contention. 15.6.3 CPHA EQUALS ZERO TRANSFER FORMAT A M IC C O Figure below shows a timing diagram of an SPI transfer where CPHA is 0. Two waveforms are shown for SCK: one for CPOL equals 0 and another for CPOL equals 1. The diagram may be interpreted as a master or slave timing diagram since the SCK, master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave; the SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high. This timing diagram functionally depicts how a transfer takes place; it should not be used as a replacement for data‐sheet parametric information. Figure15.9 CPHA Equals Zero SPI Transfer Format When CPHA = 0, the SS line must be disserted and reasserted between each successive serial byte. Also, if the slave writes data to the SPI data register (SPDR) while SS is active low, a write‐collision error results. When CPHA = 1, the SS line may remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fixed master and a single slave driving the MISO data line. 15.6.4 CPHA EQUALS ONE TRANSFER FORMAT Figure below is a timing diagram of an SPI transfer where CPHA = 1. Two waveforms are shown for SCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the SCK, MISO, and Sep., 2014, Version 0.6 (Preliminary) 96 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 15.7 SPI DATA TRANSFER 15.7.1 TRANSFER BEGINNING PERIOD ( INITIATION DELAY ) EN Figure15.10 CPHA Equals One SPI Transfer Format TI A L MOSI pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave; the SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as a general‐purpose output not affecting the SPI. N FI D All SPI transfers are started and controlled by a master SPI device. As a slave, the SPI MODULE considers a transfer to begin with the first SCK edge or the falling edge of SS, depending on the CPHA format selected. When CPHA = 0, the falling edge of SS indicates the beginning of a transfer. When CPHA = 1, the first edge on the SCK indicates the start of the transfer. In either CPHA format, a transfer can be aborted by taking the SS line high, which causes the SPI slave logic and bit counters to be reset. The SCK rate selected has no effect on slave operations since the clock from the master is controlling transfers. When the SPI is configured as a master, transfers are started by a software write to the SPDR. C O 15.7.2 TRANSFER ENDING PERIOD IC C O M An SPI transfer is technically complete when the SPIF flag is set, but, depending on the configuration of the SPI system, there may be additional tasks. Because the SPI bit rate does not affect timing of the ending period, only the fastest rate is considered in discussions of the ending period. When the SPI is configured as a master, SPIF is set at the end of the eighth SCK cycle. When CPHA equals 1, SCK is inactive for the last half of the eighth SCK cycle. When the SPI is operating as a slave, the ending period is different because the SCK line can be asynchronous to the MCU clocks of the slave and because the slave does not have access to as much information about SCK cycles as the master. For example, when CPHA = 1, where the last SCK edge occurs in the middle of the eighth SCK cycle, the slave has no way of knowing when the end of the last SCK cycle is. For these reasons, the slave considers the transfer complete after the last bit of serial data has been sampled, which corresponds to the middle of the eighth SCK cycle. The SPIF flag is set at the end of a transfer, but the slave is not permitted to write new data to the SPDR while the SS line is still low. 15.8 TIMING DIAGRAMS A M 15.8.1 MASTER TRANSMISSION Figure15.11 Master mode timing diagram Sep., 2014, Version 0.6 (Preliminary) 97 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 15.8.2 SLAVE TRANSMISSION EN Figure15.12 Slave mode timing diagram TI A L At a beginning of transfer in Slave mode, the data on serial output (MISO) appears on first rising edge after falling edge on Slave Select (SS) line. Next bits of serial data are driving into MISO line on first rising edge of CLK after SKC active edge (in this case rising edge of SCK). FI D 15.9 SPI MODULE INTERRUPT GENERATION C O N When interrupt is enabled (SPIE bit in SPCR=1), SPI interrupt flag is automatically asserted when SPI transfer is completed or transfer error has occurred. SPIIF flag has to be cleared by software. M Figure15.13 Interrupt generation Function Internal, SPI Active level/edge - Table15.2 Flag resets Software Vector 0x73 Natural priority 15 SPI interrupt summary C O Interrupt flag SPIIF (0xE8) M EIE IC SPI related interrupt bits have been summarized below. The IE (0xA8) contains global interrupt system disable (0) / enable (1) bit called EA. A Address/Name E8h EIE R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EI2CS R/W EI2CM EWDI EKEYINT ERFINT EINT4 EINT3 EINT2 ESPI Reset 0 0 0 0 0 0 0 0 ESPI：Enable SPI Interrupts EIP (0xF8) Address/Name F8h EIP Reset Sep., 2014, Version 0.6 (Preliminary) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PI2CS R/W PI2CM PWDI PKEYINT PRFINT PINT4 PINT3 PINT2 PSPI 0 0 0 98 0 0 0 0 0 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC PSPI：SPI priority level control (at 1-high-level) EIF (0x91) Address/Name 91h EIF R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2CSF I2CMF KEYINTF RFINTF INT4F INT3F INT2F SPIF R/W 0 0 0 0 0 0 0 0 L Reset A M IC C O M C O N FI D EN TI A SPIIF：SPI interrupt flag It must be cleared by software Sep., 2014, Version 0.6 (Preliminary) 99 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 16. PWM A8105 has two channels Pulse width modulator (PWM) output. Every channel PWM has an 8-bit counter with comparator, a control register (PWMxCON) and two setting registers (PWMxH and PWMxL). User can select clock source by setting PWMxCON. Enable PWM output and function by setting PWMxEN = 1; otherwise disable PWM output and function by setting PWMxEN =0. When user set PWMxEN=0, it output LOW single and reload the PWMxL to itself. When the counter is enabled and matches the content of PWMxH, its output is asserted HIGH; when the counter is overflow, its output is asserted LOW and reload PWMxL to itself. The pulse frequency and the duty cycle for 8-bit PWM is given by the below equation pwxclk+1 EN 16.1 PWM FUNCTIONALITY TI A Noted: PWMxH must be larger then PWMxL. Otherwise, PWM output always is LOW. L Pulse frequency = System clock / 2 / (255-PWMxL) Duty cycle = (255-PWMxH) / 255-PWMxL) FI D PWMxL /2 PWM counter /8 M /16 PWxCLK C O CLK N /4 /32 PWM Output 8-bit comparator IC C O PWMxH PWMxCON M Figure16.1 PWM Block Digram A The PWM pins functionality is described in the following table. All pins are one directional. PIN PWM0(P1.6) PWM1(P1.7) ACTIVE Table16.1 TYPE OUTPUT OUTPUT DESCRIPTION PWM 0 output PWM 1 output PWM PIN define 16.1.1 PWM Registers PWM0/1 is new design from AMICCOM. They can output pulse width modulation. User adjusts to duty cycle by setting PWMxH. PWM counter is up counter. PWM counter is not access directly by MCU. User can set or reset PWM counter by setting PWMxCON. When PWMxEN =1, PWM counter start to count. When PWMxEN=0, PWM counter stop counting and reload PWMxL to itself. PWxCLK is clock divider. It divide system clock to 2,4,8,16 ,32 and 64 by setting PWxCLK. Address/Name R/W Sep., 2014, Version 0.6 (Preliminary) Bit 7 Bit Bit Bit Bit 6 5 4 3 100 Bit 2 Bit 1 Bit 0 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC A9h PWM0CON Reset R/W PWM0EN - - - - PW0CLK2 PW0CLK1 PW0CLK0 0 0 0 0 0 0 0 PWM0CON: PWM channel 0 control register 0 PWM0EN: PWM Channel 0 Enable, [0]: Disable. [1]: Enable. TI A L PWM0CLK[2:0]: PWM Channel 0 Clock select [000]: MCU Clock /2 [001]: MCU Clock / 4 [010]: MCU Clock / 8 [011]: MCU Clock / 16 [100]: MCU Clock / 32 [101]: MCU Clock / 64 FI D EN Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AAh R/W PWM0H Reset 0 0 0 0 0 0 0 0 PWM0H: PWM channel 0 output HIGH register C O N Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ABh R/W PWM0L Reset 0 0 0 0 0 0 0 0 PWM0L: PWM channel 0 frequency setting register O M Bit Bit Bit Bit Address/Name R/W Bit 7 6 5 4 3 Bit 2 Bit 1 Bit 0 B0h R/W PWM1EN - - - - PW1CLK2 PW1CLK1 PW1CLK0 PWM1CON Reset 0 0 0 0 0 0 0 0 PWM1CON: PWM channel 1 control register PWM1EN: PWM Channel 1 Enable, [0]: Disable. [1]: Enable. A M IC C PWM1CLK[2:0]: PWM Channel 1 Clock select [000]: MCU Clock / 2 [001]: MCU Clock / 4 [010]: MCU Clock / 8 [011]: MCU Clock / 16 [100]: MCU Clock / 32 [101]: MCU Clock / 64 Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 B1h R/W PWM1H Reset 0 0 0 0 0 0 0 0 PWM1H: PWM channel 1 output HIGH register Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 B2h R/W PWM1L Reset 0 0 0 0 0 0 0 0 PWM1L: PWM channel 1 frequency setting register Sep., 2014, Version 0.6 (Preliminary) 101 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 17. Watchdog Timer A8105 has a special timer, called Watchdog Timer. It is a useful programmable clock counter that serves as a time-base generator, an event timer or system supervisor. User can use be a very long timer with disabled reset function. 17.1 Watchdog timer overview N FI D EN TI A L As can be seen in the figure below, the watchdog timer is driven by the main system clock that is supplied to a series of dividers. The divider output is selectable and determines interval between timeouts. When the timeout is reached, an interrupt flag will cause an interrupt to occur if its individual enable bit is set and the global interrupt enable is set. The reset and interrupt are discrete functions that may be acknowledged or ignored, together or separately for various applications. C O Figure 17.1 Watchdog Timer architecture 17.2 Watchdog interrupt M WATCHDOG interrupt related bits are shown below. An interrupt can be turned on/off by EIE register, and set into high/low priority group by EIP register. The IE contains global interrupt system disable (0) / enable (1) bit called EA. IE register (0xA8) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W EIE EA - ET2 ES ET1 EX1 ET0 EX0 0 0 0 0 0 0 0 0 IC C O Address/Name A8h IE Reset EA：Enable global interrupts. (0xE8) A M Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 E8h EI2CS R/W EI2CM EWDI EKEYINT ERFINT EINT4 EINT3 EINT2 EIE ESPI Reset 0 0 0 0 0 0 0 0 EWDI：Enable Watchdog interrupts EIP (0xF8) Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F8h PI2CS R/W PI2CM PWDI PKEYINT PRFINT PINT4 PINT3 PINT2 EIP PSPI Reset 0 0 0 0 0 0 0 0 PWDI：Enable Watchdog priority level control (at 1-high-level) Address/Name Sep., 2014, Version 0.6 (Preliminary) R/W Bit 7 Bit 6 Bit 5 102 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC D8h R/W WDIF WTRF EWT RWT WDCON Reset 0 0 0 0 0 0 0 0 WDIF：Watchdog Interrupt Flag. WDIF in conjunction with the Enable Watchdog Interrupt bit (EXIE.5), and EWT, indicates if watchdog timer event has occurred and what action should be taken. This bit must be cleared by software before exiting the interrupt service routine, or another interrupt is generated. Setting WDIF in software will generate a watchdog interrupt if enabled. Timed access registers procedure can be used to modify this bit. TI A L All of bits that generate interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. The Watchdog interrupt vector is located in 0x63. User can put interrupt service routine to take care watchdog interrupt event. 17.3 Watchdog Timer reset EN The Watchdog Timer Reset function works as follows. After initializing the correct timeout interval, software first restarts the Watchdog using RWT and then enables the reset mode by setting the Enable Watchdog Timer Reset (WDCON.1) bit. At any time prior to reaching its user selected terminal value, software can set the Reset Watchdog Timer (WDCON.0) bit. If RWT is set before the timeout is reached, the timer will start over. If the timeout is reached without RWT being set, the Watchdog will reset the MCU. Hardware will automatically clear RWT after software sets it. When the reset occurs, the Watchdog Timer Reset Flag (WDCON.2) will automatically be set to indicate the cause of the reset, however software must clear this bit manually. FI D 17.4 SIMPLE TIMER C O N The Watchdog Timer is a free running timer. When used as a simple timer with both the reset (EWT=0) and interrupt functions disabled (EWDI=0), the timer will continue to set the Watchdog Interrupt flag each time the timer completes the selected timer interval as programmed by WD[1:0]. Restarting the timer using the RWT bit, allows software to use the timer in a polled timeout mode. The WDIF bit is cleared by software or any reset. The Watchdog Interrupt is also available for applications that do not need a true Watchdog Reset but simply a very long timer. The interrupt is enabled using the Enable Watchdog Timer Interrupt (EIE.4) bit. When the timeout occurs, the Watchdog Timer will set the WDIF bit (WDCON.3), and an interrupt will occur if the global interrupt enable (EA) is set. A potential Watchdog Reset is executed 512 clocks after setting of WDIF flag. The Watchdog Interrupt Flag indicates the source of the interrupt, and software must clear WDIF flag. Proper use of the Watchdog Interrupt with the Watchdog Reset allows interrupt software to survey the system for errant conditions. 17.5 SYSTEM MONITOR O M When using the Watchdog Timer as a system monitor, the Watchdog Reset function should be used. If the Interrupt function were used, the purpose of the watchdog would be defeated. For example, assume the system is executing errant code prior to the Watchdog Interrupt. The interrupt would temporarily force the system back into control by vectoring the MCU to the interrupt service routine. Restarting the Watchdog and exiting by an RETI or RET, would return the processor to the lost position prior to the interrupt. By using the Watchdog Reset function, the processor is restarted from the beginning of the program, and therefore placed into a known state. C 17.6 WATCHDOG RELATED REGISTERS M IC The watchdog timer has several SFR bits that contribute to its operation. It can be enabled to function as either a reset source, interrupt source, software polled timer or any combination of the three. Both the reset and interrupt have status flags. The watchdog also has a bit that restarts the timer. A summary table showing the bit locations is below. A description follows. A Bit name EWDI PWDI WD[1:0] RWT EWT WTRF WDIF Register EIE EIP CKCON WDCON Bit position EIE.5 EIP.5 CKCON.7-6 WDCON.0 WDCON.1 WDCON.2 WDCON.3 Description Enable Watchdog Timer Interrupt Priority of Watchdog Timer Interrupt Watchdog Interval Reset Watchdog Timer Enable Watchdog Timer Reset Watchdog Timer Reset flag Watchdog Interrupt flag A Watchdog timeout reset will not disable the Watchdog Timer, but restarts the timer. In general, software should set the Watchdog to whichever state is desired, just to be certain of its state. Control bits that support Watchdog operation are described in next subchapters. 17.6.1. WATCHDOG CONTROL Watchdog control bits are described below. Please note that access (write) to this register has to be performed using Timed access registers procedure. Sep., 2014, Version 0.6 (Preliminary) 103 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Address/Name D8h WDCON Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 R/W - - - - 0 0 0 0 Bit 3 Bit 2 Bit 1 Bit 0 WDIF WTRF EWT RWT 0 0 0 0 TI A L WDIF：Watchdog Interrupt Flag. WDIF in conjunction with the Enable Watchdog Interrupt bit (EXIE.5), and EWT, indicates if watchdog timer event has occurred and what action should be taken. This bit must be cleared by software before exiting the interrupt service routine, or another interrupt is generated. Setting WDIF in software will generate a watchdog interrupt if enabled. Timed access registers procedure can be used to modify this bit. EN WTRF：Watchdog Timer Reset Flag. When set by hardware, indicates that a watchdog timer reset has occurred. Set by software do not generate a watchdog timer reset. It is cleared by RESET pin, but otherwise must be cleared by software. The watchdog timer has no effect on this bit, when EWT bit is cleared. FI D EWT：Enable Watchdog Timer Reset. The reset of microcontroller by watchdog timer is controlled by this bit. This bit has no effect on the ability of the watchdog timer to generate a watchdog interrupt. Timed Access procedure must be used to modify this bit. 0: watchdog timer timeout doesn’t reset microcontroller 1: watchdog timer timeout resets microcontroller C O N RWT：Reset Watchdog Timer. Setting RWT resets the watchdog timer count. Timed Access procedure must be used to set this bit before the watchdog timer expires, or a watchdog timer reset and/or interrupt will be generated if enabled. 17.6.2 CLOCK CONTROL The Watchdog timeout selection is made using bits WD[1:0] as shown in the figure. CKCON register (0x8E) IC C O M Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 8Eh R/W WD1 WD0 T2M T1M T0M MD2 MD1 MD0 CKCON Reset 0 0 0 0 0 0 0 0 Clock control register CKCON(0x8E) contains WD[1:0] bits select Watchdog timer timeout period. The Watchdog is clocked directly from CLK pin, and CKSE directly affects its timeout period. It is increased 256 times slower when the core is enabled CKSE. This allows the watchdog period to remain synchronized with device operation. Number of clocks needed for timeout does not depend on CKSE, and is constant as shown in table below. The Watchdog has four timeout selections based on the input CLK clock frequency as shown in the figure. The selections are a pre-selected number of clocks. Therefore, the actual timeout interval is dependent on the CLK frequency. A M WD[1:0] Watchdog interval Number of clocks 17 00 2 131072 20 01 2 1048576 23 10 2 8388608 26 11 2 67108864 Note that the periods shown above are for the interrupt events. The Reset, when enabled, is generated 512 clocks later regardless of whether the interrupt is used. Therefore, the actual Watchdog timeout period is the number shown above plus 512 clocks (always CLK pin). 17.7 TIMED ACCESS REGISTERS Timed Access registers have built in mechanism preventing them from accidental writes. TA is located at 0xEB SFR address. To do a correct write to such register the following sequence has to be applied: CLR EA ;disable interrupt system MOV TA, #0xAA MOV TA, #0x55 Sep., 2014, Version 0.6 (Preliminary) 104 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC ; Any direct addressing instruction writing timed access register. SETB EA ;Enable interrupt system A M IC C O M C O N FI D EN TI A L The time elapsed between first, second, and third operation does not matter (any number of Program Wait Sates is allowed). The only correct sequence is required. Any third instruction causes protection mechanism to be turned on. This means that time protected register is opened for write only for single instruction. Reading from such register is never protected. WDCON (D8h) is Timed Access register. Sep., 2014, Version 0.6 (Preliminary) 105 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 18. ADC (Analog to Digital Converter) A8105 has two built-in ADCs. One is 8-bits ADC do RSSI measurement as well as carrier detection function. The 8-bit ADC converting time is 20 x ADC clock periods. The other is 8-channel 12-bits SAR ADC. Bit Mode RSS 1 Standby None RX RSSI / Carrier detect TI A XADS 0 L 18.1 8-bits ADC Relative Control Register Mode Control Register (Address: 0802h) R/W Name R W Bit 7 Reset Bit 6 Bit 5 Bit 4 ARSSI ARSSI 0 AIF AIF 0 CD DFCD 0 N ADC Register (Address: 0821h) Bit 3 Bit 2 Bit 1 Bit 0 WWSE WWSE 0 FMT FMT 0 FMS FMS 0 ADCM ADCM 0 FI D Bit EN Table 17.1 Setting of ADC function R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RSSI Threshold R W ADC7 RTH7 1 ADC6 RTH6 0 ADC5 RTH5 0 ADC4 RTH4 1 ADC3 RTH3 0 ADC2 RTH2 0 ADC1 RTH1 0 ADC0 RTH0 1 Reset ADC Control Register (Address: 0822h) C O Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W RSM1 0 RSM0 1 ERSS 0 FSARS 1 --- XADS 0 RSS 1 CDM 1 O M Name ADC Control Reset C 18.1.1 RSSI Measurement A M IC A8105 supports 8-bits digital RSSI to detect RF signal strength. RSSI value is stored in ADC [7:0] (1Dh). Fig 17.1 shows a typical plot of RSSI reading as a function of input power. This curve is base on the current gain setting of A8105 reference code. A8105 automatically averages 8-times ADC conversion a RSSI measurement until A8105 exits RX mode. Therefore, each RSSI measuring time is ( 8 x 20 x FADC). Be aware RSSI accuracy is about ± 6dBm. Sep., 2014, Version 0.6 (Preliminary) 106 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 25℃_U-8_RSSI with AGC (1M) L2H 350 RSSI AGC 300 250 L normal AGC RSSI Code 200 TI A AGC Fix 150 50 -100 -90 -80 -70 -60 -50 -40 -30 -20 FI D 0 -110 EN 100 -10 0 10 Input Power (dBm) Figure 18.1 Typical RSSI characteristic. C O N Auto RSSI measurement for TX Power: 1. Set wanted FRXLO 2. Set RSS= 1 (822h), FSARS= 1 (822h, 4MHz ADC clock). 3. Enable ARSSI= 1 (802h). 4. Send RX Strobe command. 5. In RX mode, 8-times average a RSSI measurement periodically. 6. Exit RX mode, user can read digital RSSI value from ADC [8:0] (1Dh) for TX power. O M In step 6, if A8105 is set in direct mode, MCU shall let A8105 exit RX mode within 40 us to prevent RSSI inaccuracy. Strobe CMD (SCS,SCK,SDIO) RX Mode C RX-Strobe MCU Read ADC[7:0] RX Ready Time Received Packet Read 8-bits RSSI value IC RF-IN GIO1 Pin - WTR (GPIO1S[3:0]=0000) A M GIO2 Pin - FSYNC (GPIO2S[3:0]=0001) T0 T0-T1: T2-T3: T3 : T3-T4: T1 T2 T3 T4 Settling Time Receiving Packet Exit RX mode automatically in FIFO mode MCU read RSSI value @ ADC [7:0] Figure 18.2 RSSI Measurement of TX Power. Auto RSSI measurement for Background Power: 1. Set wanted FRXLO 2. Set RSS= 1 (822h), FSARS= 0 (822h, 4MHz ADC clock). 3. Enable ARSSI= 1 (802h). 4. Send RX Strobe command. Sep., 2014, Version 0.6 (Preliminary) 107 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC MCU delays min. 140us. Read digital RSSI value from ADC [8:0] (in 0x81DH and 0x821h) to get background power. Send other Strobe command to let A8105 exit RX mode. Strobe CMD (SCS,SCK,SDIO) RX-Strobe MCU Read ADC[7:0] No Packet RFI Pin L 5. 6. 7. Min. 140 us TI A GIO1 Pin - WTR (GPIO1S[3:0]=0000) MCU reads 8-bits RSSI value that is refresh every 40 us T0 EN GIO2 Pin - FSYNC (GPIO2S[3:0]=0001) T1 FI D T0-T1: MCU Delay Loop from PLL to RX mode for RSSI measurment T1 : Auto RSSI Measurment is done by 8-times average. MCU can read RSSI value from ADC [7:0] Figure 18.3 RSSI Measurement of Background Power. N 18.1.2 Carrier Detect C O Base on RSSI measurement, user can extend its application to do carrier detect (CD). In Carrier Detect mode, RSSI is refresh every 5 us without 8-times average. If RSSI level is below threshold level (RTH), CD is output high to GIO1 or GIO2 pin to inform MCU that current channel is busy. Below is a reference procedure: M Set CDTH (0821h) for absolute RSSI threshold level (ex. RTH = 80d). Set GIO2S = [0010] (080Eh) for Carrier Detect to GIO2 pin. (2-1) Set wanted FRXLO (2-2) Set RSM= [11] (0822h, CDM =0 and hysteresis =6, or CDM =1 and hysteresis =12). (2-3) Enable ARSSI= 1 (802h). (2-4) Send RX Strobe command. (2-5) MCU enables a timer delay (min. 100 us). MCU checks GIO2 pin. (3-1) If ADC ≧ CDTH, GIO2 = 0. (3-2) If ADC ≦ CDTH-CDM, GIO2 = 1. (3-3) If ADC locates in hysteresis zone, GIO2 = previous state. Exit RX mode. A M 4. IC 3. C O 1. 2. 18.2 12-bits SAR ADC A8105 includes a 12-bit successive approximation A/D converter which enables channel selection from 8 channels. The A/D converter has two operating modes: single mode and continuous mode. The 12-bits A/D converter can be used to perform the analog input of the specified channel or temperature sensor. Fig 18.5 shows a typical plot of temperature reading for 12-bit ADC. Bit Mode DTMP BUFS 0 0 Analog Input 1 1 Temperature Sensor Table 18.2 Setting of 12-bit ADC function Sep., 2014, Version 0.6 (Preliminary) 108 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC The conversion time in single mode can be determined as follows: tconv  1 1   32 4MHz CKS[1: 0] tconv A/D converter operation A/D conversion Waiting for conversion TI A Waiting for conversion L SARE ADC output Conversion Result EN OKADB Figure 18.4 Single Mode for A/D Conversion. N FI D Measurement for Analog Input: 1. Set ADCCH (0xBCh) for selecting ADC channel. 2. Set ENADC (0x85Bh) to enable the SAR ADC. 3. Set MODE (0x85Ah) to select single mode or continuous mode. 4. Enable ADCE = 1 (0x85Ah) M C O Measurement for Temperature: 1. Set ENADC (0x85Bh) to enable the SAR ADC. 2. Set BUFS = 1 (0x85Ah) 3. Set DTMP = 1 (0x85B) to enable the temperature sensor for 12-bit ADC. 4. Set MODE (0x85Ah) to select single mode or continuous mode. 5. Enable ADCE = 1 (0x85Ah) O Temperature 12bit ADC value C 2100 2000 IC 1900 A M ADC value 1800 1700 1600 1500 1400 1300 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (℃) Figure 18.5 Typical 12-bit ADC temperature sensor characteristic curve. Sep., 2014, Version 0.6 (Preliminary) 109 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 19. Battery Detect A8105 has a built-in battery detector to check supply voltage (REGI pin). The detecting range is 1.8V ~ 2.5V in 8 levels. Relative Control Register Battery detect Register (Address: 082Bh) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Battery detect W R RGS -0 RGV1 RGV1 0 RGV0 RGV0 0 PACTL BDF 0 BVT2 BVT2 0 BVT1 BVT1 1 BVT0 BVT0 1 BDS BDS 0 N Set A8105 in standby or PLL mode. Set BVT[2:0] (082Bh) = [011] and enable BDS (082Bh) = 1. After 5 us, BDE is auto clear. MCU reads BDF (082Bh). If REGI pin > 2.1V, BDF = 1 (battery high). Else, BDF = 0 (battery low). A M IC C O M C O 1. 2. 3. 4. FI D Below is the procedure to detect low voltage input (ex. below 2.1V): TI A BVT[1:0]: Battery detection threshold. [000]: 1.8V. [001]: 1.9V. [010]: 2.0V. [011]: 2.1V. [100]: 2.2V. [101]: 2.3V. [110]: 2.4V. [111]: 2.5V. When REGI < Threshold, BDF= low. When REGI > Threshold, BDF= high. EN Reset L Name Sep., 2014, Version 0.6 (Preliminary) 110 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 20 Power Management L The power consumption of A8105 comes from two parts. One is RF part and the other is digital part (includes MCU core and peripherals). In the RF part, the idle mode use the minimum power and the TX or RX mode use the maximum power consumptions. Use changes RF status by setting the strobe control,register(0800h). For more detail information, please refer chapter 21.1. In this chapter only introduces digital parts. Low power operation is enabled through different power modes setting. A8105 has various operating mode are referred as normal mode, PM1, PM2, and PM3 (power manager mode 3). Table 20.1 shows the impact of different power modes on systems operation. There are two registers to setting power manager. One is power control register (PCON, 0x87h) and the other is power control extend register (PCONE, 0xB9h). Bit 7 R/W SMOD 0 Bit 5 Bit 4 Bit 3 - PWE - 0 0 0 Bit 2 Bit 1 Bit 0 SWB STOP CKSE 0 0 0 C O N 0 Bit 6 M Reset SWB (Switchback enable) [1]: Enable [0]: Disable STOP (Stop mode) [1]: Enable [0]: Disable CKSE (Clock select enable ) [1]: Enable clock select [0]: Disable clock select R/W FI D PCON (087h) Power control Address/Name 87h PCON EN TI A In normal mode, user selects different clock be MCU core clock.in CLKSEL[2:0] (PCONE, 0xB9h) then enable CKSE (PCON, 0x87h). User adjusts MCU clocks depends on the required power consumption. CLKSEL[2:0] = 001 ~ 110b, the MCU core clock is the clock sources divide 2 ~ 64. User could adjust the MCU speed to trade-off between the performance and the power consumption. BEWARE, please choice CLKSEL firstly then enable CKSE to avoid glitch. Please refer the reference code or contact AMICCOM’s FAE for more details. User can enable STOP to freeze MCU core clock and all digital peripherals also stop. MCU can be waked up by hardware reset, KEY wake up, KEYINT or sleep timer (WOR /TWOR). User set sleep timer, WOR or TWOR before enter STOP mode. In this condition, it is called PM1. In PM1, all digital circuitry is stop and RF circuitry is active by WOR Note: Please don’t enable STOP and CKSE at the same time. C O PCONE(0xB9h) Power control extend Address/Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 B9h R/W QD REGAE PM2F CLKSEL2 CLKSEL1 CLKSEL0 PCONE 0 0 0 0 0 0 0 0 IC Reset A M QD (Quick discharge ) : Reserved for internal usage REGAE(RegA Enable) : Reserved for internal usage PM2F (Power Mode 2 flag) : Reserved for internal usage CLKSEL[2:0] (Clock Select), Select clock source when enable clock select. [000]: Clock source div 64 as MCU clock [001]: Clock source div 2 as MCU clock [010]: Clock source div 4 as MCU clock [011]: Clock source div 8 as MCU clock [100]: Clock source div 16 as MCU clock [101]: Clock source div 32 as MCU clock [110]: Clock source div 64 as MCU clock [111]: Select RTC as CPU clock when CKSE=0; RTC div 2 as CPU clock when CKSE=1 Sep., 2014, Version 0.6 (Preliminary) 111 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 16MHz RAM Back to Normal LVR RF 16MHz ON ON X X X ON ON X X X OFF 8/4/2/1 MHz IRC/RTC OFF OFF OFF FI D RF Clock Generator XO X EN X H/W reset / KEYINT OFF OFF ON / Sleep timer H/W reset / wakeup key OFF OFF ON / Sleep timer 256K OFF H/W reset / wakeup key OFF OFF 2K ON / Sleep timer Table 20.1 Power manager X: don’t care, it can turn on or off by user setting Note: PM mode setting refer to chapter 9.2.101 L MCU speed TI A Normal CKSE=0 Normal CKSE=1 (Low speed) Idle (PM1) Sleep (PM2) Deep Sleep (PM3) 0 1 0 CLKSEL =7 RTCS /64 0 /2 1 C O IRC 1 M /4 M IC C O /8 A N CLKRUN RTC /16 /32 /64 /2 CLKCTRL CLK MCU Core 2 CLKPMM 3 4 CLKSEL 5 CKSE STOP 6 7 WOR/TWOR timer CLKSEL = 0 ~ 7 Figure 20.1 Whole chip clock sources Sep., 2014, Version 0.6 (Preliminary) 112 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 21 A8105 RF L A8105 integrate 2.4 Ghz GFSK transceiver and use Strobe control register (0800h) to control RF state. There are 6 Strobe commands to control internal state machine for RF operations. These modes include Sleep mode, Idle mode, Standby mode, PLL mode, RX mode and TX mode. There are 64Bytes FIFO for data transmitting, receiving. Sleep timer is used for WOR (Wake On Rx) and time-slotted mode operation. Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 MODEC1 Reset W STRB7 STRB6 STRB5 STRB4 STRB3 1 0 1 0 0 Bit 2 Bit 1 Bit 0 STRB2 STRB1 STRB0 0 0 0 FI D EN Use strobe command control RF state. STRB[7:0]: Strobe command register. 0x80: Sleep mode. 0x90: Idle mode. 0xA0: Standby mode. 0xB0: PLL mode. 0xC0: TX mode. 0xD0: RX mode. TI A 21.1 Mode Control Register 1 (Address: 0x801h) N Mode Register (Address: 0x800h) R/W Bit 7 Bit 6 Bit 3 Bit 2 Bit 1 Bit 0 Mode W R RESETN - FWPRN FECF FRPRN CRCF ADC12RN CER XER BFCRN PLLER TRSR TRER -- -- -- -- -- -- -- -- Reset Bit 5 Bit 4 C O Name M In A8105, user can read the RF state from mode register M IC C O CER: RF chip enable status. [0]: RF chip is disabled. [1]: RF chip is enabled. XER: Internal crystal oscillator enabled status. [0]: Crystal oscillator is disabled. [1]: Crystal oscillator is enabled. PLLE: PLL enabled status. [0]: PLL is disabled. [1]: PLL is enabled. TRER: TRX state enabled status. [0]: TRX is disabled. [1]: TRX is enabled. TRSR: TRX Status Register. [0]: RX state. [1]: TX state. A In A8105, user control RF mode as well as read/write ram. By DPTR access and MOVX instruction, user change RF mode and know RF status. 21.1.1 Strobe Command - Sleep Mode Refer to Strobe Control Register, user can write 0x80 to Strobe Control Register directly to set RF into Sleep mode. 21.1.2 Strobe Command - Idle Mode Refer to Strobe Control Register, user can write 0x90 to Strobe Control Register directly to set RF into Idle mode. 21.1.3 Strobe Command - Standby Mode Refer to Strobe Control Register, user can write 0xA0 to Strobe Control Register directly to set RF into Standby mode. 21.1.4 Strobe Command - PLL Mode Refer to Strobe Control Register, user can write 0xB0 to Strobe Control Register directly to set RF into PLL mode. Sep., 2014, Version 0.6 (Preliminary) 113 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 21.1.5 Strobe Command - RX Mode Refer to Strobe Control Register, user can write 0xC0 to Strobe Control Register directly to set RF into RX mode. 21.1.6 Strobe Command - TX Mode Refer to Strobe Control Register, user can write 0xD0 to Strobe Control Register directly to set RF into TX mode. 21.2 RF Reset Command TI A L In addition to power on reset (POR), A8105 could issue software reset (80h) to RF by setting Mode Register (0800h). A8105 generates an internal signal “RESETN” to initial RF circuit. After reset command, RF state is in standby mode and re-calibration is necessary. 21.3 FIFO Accessing Command FI D There are similar steps to read RX FIFO. Step1: Send RX Strobe command for receiving data. Step2: Read RX data from RX FIFO in sequence by Data Byte 0, 1, 2 to n. EN Before TX delivery, user only needs to write wanted data into TX FIFO (0x900 ~ 0x93F) in advance. Similarly, user can read RX FIFO (0x900 ~ 0x93F) once payload data is received. It is easy to delivery data to air. Below is the procedure of writing TX FIFO. Step1: Send (n+1) bytes TX data in sequence by Data Byte 0, 1, 2 to n. Step2: Send TX Strobe command for transmitting. C O N A8105 supports separated 64-bytes TX and RX FIFO. To use A8105’s FIFO mode, user just needs to enable FMS =1 (01h). For FIFO accessing, TX FIFO (write-only) and RX FIFO (read-only) share the same register address 05h. TX FIFO represents transmitted payload. On the other hand, RX circuitry synchronizes ID Code and stores received payload into RX FIFO. 21.4 Packet Format of FIFO mode O M Data whitening(optional) FEC encoded/decoded(optional) CRC -16 calculation(optional) ID code 4 bytes 4 bytes A M IC C Preamble Payload Max. 256 bytes (CRC) 2 bytes Figure 21.1 Packet Format of FIFO mode ID code ID Byte 0 ID Byte 1 ID Byte 2 ID Byte 3 Figure 21.1 ID Code Format Preamble: The packet is led by preamble composed of alternate 0 and 1. If the first bit of ID code is 0, preamble shall be 0101…0101. In the contrast, if the first bit of ID code is 1, preamble shall be 1010…1010. Preamble length is recommended to set 4 bytes by PML [1:0] (20h). ID code: ID code is recommended to set 4 bytes by IDL=1 (20h). ID Code is sequenced by Byte 0, 1, 2 and 3. If RX circuitry checks the ID code correct, payload will be written into RX FIFO. In special case, ID code could be set error tolerance (0~ 3bit error) by ETH [1:0] (21h) for ID synchronization check. Sep., 2014, Version 0.6 (Preliminary) 114 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Payload: Payload length is programmable by FEP [7:0] (03h). The physical FIFO depth is 64 bytes. A8105 also supports logical FIFO extension up to 256 bytes. See section 16.5 for details. CRC (option): In FIFO mode, if CRC is enabled (CRCS=1, 20h), 2-bytes of CRC value is transmitted automatically after payload. In the same way, RX circuitry will check CRC value and show the result to CRC Flag (00h). L 21.5 Transceiver Frequency TI A A8105 is a half-duplex transceiver with embedded PA and LNA. The receiver is a low-IF architecture consisting of a LNA, down conversion mixers, polyphase channel filters and IF limiting amplifiers with RSSI. The transmitter is direct modulation architecture with 6 dBm maximum output power and 35 dB power control range. For TX or RX frequency setting, user just needs to set up one register, CHN (0811h), for frequency agility. EN A8105’s main PLL features are:  Frantional-N to generate RX/TX frequencies for all ISM 2.4 GHz channels  Autonomous calibration loops for stable operation within the operating range  Fast PLL settling to support frequency hopping = 2400 + (CHN x 0.5) in [MHz], where CHN is the channel number, addr 0Fh. N FLO FI D During receive operation, the frequency synthesizer works as a local oscillator. During transmit operation, the voltage-controlled oscillator (VCO) is directly modulated to generate the RF transmit signal. The frequency synthesizer is implemented as a fractional-N PLL. C O A8105’s LO frequency FLO = FLO_BASE + FOFFSET. Therefore, A8105 is very easy to implement frequency hopping by ONE register setting, (CHN, 0Fh). In general, user can plan the wanted channels by a CHN Look-Up-Table between master and slaves for two-way frequency hopping. Below is the LO frequency block diagram. M DBL O F XTAL A M IC C X2 BIP[8:0] + BFP[15:0]/ 2 CHN x CHR / 2 1 F LO F PFD PFD 1/(RRC+1) VCO 0 Divider 16 F LO_BASE + + F LO 16 F OFFSET Figure 21.2 Block Diagram of Local Oscillator 21.5.1 RF Clock The master clock of A8105 (FCSCK= 32/64 MHz) is generated by the PLL clock generator which reference frequency (FCGR= 2/4 MHz) is derived from frequency divider of crystal oscillator. Sep., 2014, Version 0.6 (Preliminary) 115 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC FCGR  FXREF , where GRC [3:0] (0Eh) is the divide number to get FCGR from crystal oscillator. GRC[3 : 0]  1 Below is block diagram of system clock where FXTAL is the crystal frequency. User can set XS, GRC, CGS to get FCSCK = 32/64MHz. FXREF is a reference clock to generate FCGR and FSPLL . After delay circuitry, FCSCK (32/64MHz) is derived. And with BWS setting, the system clock FSYCK can be fixed to 8MHz. CGC CGS L GRC CE ÷ FXREF PLL (GRC+1) CE XI System clock 1 32M/ 64MHz FCGR F CSCK = 32/64MHz 0 Delay Clock Generator FXTAL FSYCK 1/[(1+BWS)*4] FI D XO FSPLL EN XS TI A CE Figure 21.3 RF Clock Block Diagram Below is the setting table of system clock for both 1MHz and 2MHz data rate 16 MHz 16 MHz 2M 16 MHz 16 MHz 21.5.2 LO Frequency Setting 2 MHz GRC [3:0] [0111] 2 MHz [0011] FCGR CGC BWS 1 0 0 32MHz 8MHz 1 1 1 64MHz 8MHz XS CGS 1 1 C O FXREF FCSCK FSYCK M FXTAL N Data rate 1M O To set up 2.4GHz LO Frequency (FLO,), user can refer to below 4 steps. Set the base frequency (FLO_BASE) by PLL Register II (0812h) and III (0813h). Recommend to set FLO_BASE ~ 2400.001MHz. 2. Set channel step FCHSP = 500KHz by PLL Register IV (0814h). 3. Set CHN [7:0] to get offset frequency by PLL Register I (0811h). FOFFSET = CHN [7:0] * FCHSP IC M LO frequency is equal to base frequency plus offset frequency. FLO = FLO_BASE + FOFFSET A 4. C 1. FLO FLO_BASE FOFFSET 21.5.2.1 How to set FLO_BASE Sep., 2014, Version 0.6 (Preliminary) 116 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Regarding to LO frequency setting, Table 21.1 shows 2400.001 MHz base frequency by 16MHz Xtal. STEP 1 2 3 4 ITEMS FXTAL BIP[7:0] BFP[15:0] FLO_BASE VALUE 16 MHz 0x96 0x0004 ~2400.001 MHz NOTE Crystal Frequency To get FLO_BASE =2400 MHz To get FLO_BASE ~ 2400.001 MHz LO Base frequency L Table 21.1 How to configure FLO_BASE TI A 21.5.2.2 How to set FLO = FLO_BASE + FOFFSET Regarding to frequency offset scheme, Table 21.2 shows Channel 11 (2405.001 MHz) by 16MHz Xtal. VALUE NOTE ~2400.001 MHz After cofigure BIP and BFP 0x0800 To get FCHSP= 500 KHz 0x0A To set channel number = 10 5 MHz To get FOFFSET= 500 KHz * (CHN) = 5MHz ~2405.001 MHz To get FLO= FLO_BASE + FOFFSET Table 21.2 How to configure FLO EN ITEMS FLO_BASE CHR[14:0] CHN[7:0] FOFFSET FLO FI D STEP 1 2 3 4 5 N 21.6 State machine In chapter 9.2 and chapter 21.1, user can learn both accessing A8105’s control registers as well as issuing Strobe commands. C O 21.6.1 Key states O M A8105 supports 6 key operation states. Those are, (1) Standby mode (2) Sleep mode (3) Idle mode (4) PLL mode (5) TX mode (6) RX mode IC C After power on reset or software reset or deep sleep mode, user has to do calibration process because all control registers are in initial values. The calibration process of A8105 is very easy, user only needs to issue Strobe commands and enable calibration registers. After calibration, A8105 is ready to do TX and RX operation. User can start wireless transmission. Strobe Command b6 1 1 1 1 1 1 0 0 0 0 1 1 b5 b4 b3 b2 b1 b0 0 0 1 1 0 0 0 1 0 1 0 1 x x x x x x x x x x x x x x x x x x x x x x x x A M b7 Mode RF Register RF retention Regulator Description Sleep mode Idle mode Standby mode PLL mode RX mode TX mode Xtal Osc. VCO PLL RX TX Strobe Command Sleep Idle Yes Yes ON ON OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF (1000-xxxx)b (1001-xxxx)b Standby PLL TX Yes Yes Yes ON ON ON ON ON ON OFF ON ON OFF ON ON OFF OFF OFF OFF OFF ON (1010-xxxx)b (1011-xxxx)b (1101-xxxx)b RX Yes ON ON ON ON ON OFF (1100-xxxx)b Sep., 2014, Version 0.6 (Preliminary) 117 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Remark: x means “don’t care” Table 21.3 Operation mode and strobe command 21.6.2 FIFO mode Strobe CMD (SCS,SCK,SDIO) TX Next Instruction Strobe RF settling (PDL+TDL) Pin preamble+ID+payload EN RFO TI A L This mode is suitable for the requirements of general purpose applications and can be chosen by setting FMS = 1. After calibration, user can issue Strobe command to enter standby mode where write TX FIFO or read RX FIFO. From standby mode to packet data transmission, only one Strobe command is needed. Once transmission is done, A8105 is auto back to standby mode. Figure 21.4 and Figure 21.5 are TX and RX timing diagram respectively. Figure 21.6 illustrates state diagram of FIFO mode. GIO1 Pin - WTR (GIO1S[2:0]=001 ) T0 FI D Transmitting Time T1 T2 Auto Back Standby Mode Strobe CMD (SCS,SCK,SDIO) N Figure 21.4 TX timing of FIFO Mode C O RX strobe RX settling RFI Pin O M GIO1 Pin- WTR (GIO1S[2:0]=001 ) preamble+ID+payload ReceivingTime T1 T3 T2 Auto Back Standby Mode Figure 21.5 RX timing of FIFO Mode A M IC C T0 Next Instruction Wait Packet Sep., 2014, Version 0.6 (Preliminary) 118 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC IC reset (POR, RST-CMD) AK PLL PLL Auto CAL. Standby 3mA Standby SLEEP 2.5uA Deep SLEEP W-FIFO 3mA 0.02uA FI D TX / RX Strobe PLL 9.5mA Auto PDL Auto N Auto ( RX FIFO Full *) PLL TDL RX 9.5mA ST (1ms) 1ms TX State State current Strobe CMD MCU delay time RF auto delay ST : apply Strobe command AK : enable control register Auto : auto entry O Auto M 18mA Auto C O 9.5mA SYMBOL EXPLAIN ( TX FIFO Empty * ) WPLL RX settling STB (2ms) EN Standby R-FIFO Deep Sleep STB (1.2ms) Sleep AK L Auto STB TI A Sleep STB (1.2ms) RSSI Measure Figure 21.6 State diagram of FIFO Mode A M IC C (ARSSI=1) Sep., 2014, Version 0.6 (Preliminary) 119 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 22. Encryption and Autherfication For Bluetooth Low Energy application, it uses AES-128 link layer encryption block with Counter Mode CBC MAC defined in IETF RFC 3610. A8105 32Kbytes version (A8105F5) integrates AES-128 encryption core for user to encrypt data using AES algorithm with 128-bits key. The AES core also supports CBC-MAC for authentication. 22.1 AES AES_IN 128-bits MUX Key Expansion FI D MUX AES_KEY 128-bits EN TI A L AES (Advanced Encryption Standard) is a symmetric block cipher on 128-bits data blocks, it consists 10 encryption rounds during encryption process. Figure 22.1 shows the structure of the AES encryption. AES can be divided into four basic operation block where data are treated at either byte or bit level. The array of bytes organized as a 4x4 matrix is also called “state” and those four basic steps, AddRoundKey, SubBytes, ShiftRows, and MixColumns. These four steps describe one round of the AES operation. The number of rounds is depended on the key length, i.e., 10, 12, and 14 rounds for the key length of 128, 192, and 256 bits respectively. The block diagram of the AES with 128 bit data is shown below in Figure 22.1. AddRoundKey AES_OUT 128-bits C O N SubBytes ShiftRows M MixColumns C 22.1.1 AddRoundKey O Figure 22.1 Structure of the AES-128 Core. IC Each byte of the array is added to a byte of the corresponding array of round subkeys. Excluding the first and the last round, the AES with 128-bits round key proceeds for 9 iterations. Round keys are generated by a procedure called round key expansion or key scheduling. Those sub-keys are derived from the original key by XOR the two previous columns. For columns that are in multiples of four, the process involves round constants addition, S-Box and shift operations. M 22.1.2 SubBytes A This operation is a non-linear byte substitution. It composes of two sub-transformations; multiplicative inverse and affine transformation. In most implementations, these two sub-steps are combined into a single table lookup called S-Box. 22.1.3 ShiftRows This step is a simple permutation process, operates on individual rows, i.e. each row of the array is rotated by a certain number of byte positions. 22.1.3 MixColumns 8 The MixColumns transformation is a substitution step that makes of arithmetic over GF(2 ). Column vector is multiplied by a fixed matrix where bytes are treated as a polynomial of degree less than 4. 22.2 CCM CCM is an authenticated encryption algorithm designed to provide both authentication and confidentiality. It is only defined for block ciphers with a block length of 128 bits. It uses encryption algorithm to generate encrypted and authenticated data at the same time. The AES-CCM process is shown in Figure 22.2. Sep., 2014, Version 0.6 (Preliminary) 120 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC AES-128 Encryption A1 AES-128 Encryption A2 Payload-1 Payload-0 B0 Cipher-0 Cipher-1 TI A AES-128 Encryption AES-128 Encryption MAC A0 EN AES-128 Encryption AES-128 Encryption L B2 B1 FI D MIC Figure 22.2 CCM Encryption Procedure. A M IC C O M C O N CCM authentication starts by defining a sequence of blocks B0, B1, and B2 and thereafter CBC-MAC is applied to those blocks so that the authentication field MIC can be obtained. CCM uses the A 0, A1, and A2 blocks to generate key-stream that is used to encrypt the MIC and the payload. Block A0 is always used to encrypt and decrypt the MIC. A1 and A2 blocks are generated as needed for encryption or decryption of the payload. Sep., 2014, Version 0.6 (Preliminary) 121 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 23. Flash memory controller 9Ah FLSHCTRL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TI A Address/Name R/W L SFR RELATED REGISTERS FLASH memory is controlled using PCON(0x87)’s PWE bit, FLSHCTRL(0x9A) and FLSHTMR (0x9B), FLSHTPG(0x9C) and FLSHTER(0x9D). An SFR register named FLASHCTRL (0x9A) is used to control communication between CPU and flash. FLSHCTRL(0x9A) is consisted of 6bits used to control all FLASH related operations. Lower five bits of FLSHTMR (0x9B) named FREQ[4:0] determine real CLK frequency with 1MHz step resolution. FREQ[4:0] after reset is set to 20MHz by default, provides optimal timing for flash macro. Please contact AMICCOM FAE for more details flash operation reference code. R/W CTRL.7 CTRL.6 CTRL.5 CTRL.4 CTRL.3 CTRL.2 CTRL.1 CTRL.0 0 R/W 9Bh FLSHTMR R/W Bit 7 Bit 6 0 0 0 Bit 5 Bit 4 0 Bit 3 Bit 2 0 Bit 1 0 Bit 0 Fewq.4 Fewq.3 Fewq.2 Fewq.1 Fewq.0 0 0 0 0 0 0 0 0 O M C O N Reset FI D Address/Name 0 EN Reset R/W 9Ch FLSHTPG R/W C Address/Name IC Reset R/W 9Dh FLSHTER R/W A M Address/Name Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 1 0 0 1 1 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 0 0 1 Setting higher clock frequency is not supported since given Flash macro has limited its clock frequency up to 20MHz by Tkp read cycle time. FLASHCTRL register is write protected by TA enable procedure listed below: CLR EA ;disable interrupt system MOV TA, #0xAA MOV TA, #0x55 MOV FLASHCTRL,# ; Any direct addressing instruction writing FLASHCTRL register. SETB EA ;Enable interrupt system Sep., 2014, Version 0.6 (Preliminary) 122 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC The Program Write Enable (PWE) bit, located in PCON register, is used to enable/ disable PRGROMWR and PRGRRAMWR pin active during MOVX instructions. PCON (087h) Power control Address/Name 87h PCON R/W Bit 7 R/W SMOD 0 Bit 5 Bit 4 Bit 3 - - PWE - 0 0 0 0 Bit 2 Bit 1 Bit 0 SWB STOP CKSE 0 0 0 L Reset Bit 6 TI A When PWE bit is set to logic 1, the MOVX @DPTR,A instruction writes data located in accumulator register in to Program Memory addressed by DPTR register (active: DPH:DPL). The MOVX @ Rx,A instruction writes data located in accumulator register into program memory addressed by P2 register (bit 15:8) and Rx register (bit 7:0). Program Memory can be read by MOVC only regardless of PWE bit. EN CHIP ERASE OPERATION FI D Chip erase operation is enabled by setting CTRL[5:0]=0x04 of FLSHCTRL register according to MCU TA enable procedure. PCON.PWE bit must be also set, then first MOVX instruction writing to program memory space at address belong to certain FLASH macro begins sector erase operation. During erase operation MCU is halted by asserting FLASHBUSY pin. When FLASH macro is blank and ready for new programming. To erase another FLASH macro, the whole procedure needs to be repeated with change MOVX address pointing to certain FLASH macro. Preprogramming of whole FLASH macro is executed automatically without any interaction with user, before real chip erase. It extends lifecycle of FLASH macro. C O N SECTOR ERASE OPERATION The 16KB Flash macro has 129 sectors (128Bytes each) which can be erased separately. Sector erase operation is enabled by setting CTRL[5:0] = 0x22 of FLSHCTRL register according to MCU TA enable procedure. PCON.PWE bit must be also set. The first MOVX instruction writing to program memory space at selected sector address begins sector erase operation. During sector erase operation, MCU is galted by asserting FLASHBUSY pin. When sector has been erased, FLASHBUSY pin is deactivated and FNOP is automatically written. MCU executes next instruction. Selected FLASH macro sector(s) is blank and ready for new programming. To erase another sectors whole procedure needs to be repeated. Programming of whole sector is executed automatically without any interaction with user, before real erase. It extends lifecycle of FLASH macro. A M IC C O M PROGRAM OPERATION Word program operation is enabled by setting CTRL[5:0]=0x01 of FLSHCTRL register according to MCU TA enable procedure. PCONE.PWE bit must be set too, then each write to program memory space by MOVX instruction addressing odd bytes begins word program operation. During program operation MCU is halted by asserting FLASHBUSY pin. When word has been programmed FLASHBUSY pin is deactivated. MCU executes next instruction which can be (i) programming of next memory word (ii) CTRL[5:0] = 0x00 according to MCU TA enable procedure. Number of programmed by bytes must be always even number(2,4,6…) . For example to program byte at address 0x003, first must be written byte at address 0x002 then second MOVX instruction write at address 0x003 begins physical write to FLASH macro. When number of programmed bytes is not even then it must be filled with extra neutral byte. The neutral bytes does not program any bit in a FLASH macro. Note: Flash memory can programmed once. Please erase sector firstly if change the content in the flash memory. Sep., 2014, Version 0.6 (Preliminary) 123 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 24 In Circuit Emulator (ICE) L A8105 support In Circuit Emulator on chip. It is a real-time hardware debugger as a non-intrusive system. It doesn’t need to occupy any hardware resource such as the UART and Timer. User develops firmware complete producing code without any modification using ICE. It helps user to track down hidden bugs within the application running with microcontroller. The ICE with Hardware USB dongle provides a powerful SOC development tool with silicon using 2-wire protocol. The ICE fully supports Keil uVision2/3/4 interface to hardware debuggers. It allows Keil software user to work with uvision2/3/4. For more detail information, please reference Application note. C O N FI D EN TI A 24.1 PIN define IC C O M Fig 24.1 The USB connectors Fig22.2 The Pin define within USB connector M Note: RSTO pin is open drain (od) type active low. It forces logic zero to issue reset. When RSTO is inactive its output is floating, and should be connected to global system reset with pull-up resistor. This pin can be left unconnected. A There are 10 pin in the ICE connectors. 2-wire ICE only use 2 pins (PIN1 and PIN3). The PIN9 is optional and it can connects reset signal. PIN2 and PIN10 are GND pin. PIN4 is VCCIO pin. The recommended circuit shows as the below figure. (Fig21.3). There is a resister (100 ohm) between A8510 and pin connected the connector. Sep., 2014, Version 0.6 (Preliminary) 124 AMICCOM Electronics Corporation A8105 EN TI A L 2.4GHz FSK/GFSK SoC FI D Fig 24.3 The connections between A8105 and USB connectors 24.2 ICE Key feature A M IC C O M C O N The ICE supports source level debugging, 2 hardware breakpoint, auto refresh of all register and In System Programming (ISP). User can use ICE to download firmware by Keil software or AMICCOM tool. Sep., 2014, Version 0.6 (Preliminary) 125 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 25. Application circuit Below are AMICCOM’s ref. design circuits. For more details, please refer AMICCOM standard module , MD8105-Axx. CRYSTAL(32.768KHz/CL=12.5pF) Y3 3 2 1 4 L3 10nH C21 100pF M O 1 2 3 4 5 P1_2/GIO2 27 P1_1 26 P1_0 25 P0_7/GIO1 24 P0_6 23 P0_5 22 P0_4/DEBUG_EN 21 P0_3 RESETN VPP P3_1 P3_0 P1_5/TTCLK EN P1_3/CKO 28 1 2 3 4 5 6 7 8 9 10 11 REGI P0_0 P0_1 P0_2 P0_3 P0_4/DEBUG_EN P0_5 P0_6 P0_7/GIO1 P1_4/TTDIO P1_5/TTCLK TI A P1_6 31 P1_5 P1_7 32 C22 0.1uF P1_4/TTDIO 29 8105 J2 CON/11P 1.27 C12 C5 2.2uF 100pF Y1 4 3 GND 1 GND 2 CRYSTAL/3.2*2.5 (16MHz/CL=12pF) A M IC C P1_6 P3_0 33 P0_3 1uF C13 C23 3.3nF P1_7 P3_1 34 P3_0 P3_2 35 P3_1 P3_3 36 P3_2 P3_4 37 P3_3 P3_5 38 P3_4 C O VDD_P C11 NC 30 GND C19 1.2pF P0_4 XO C18 1.2pF RFO P0_2 2.4nH RFI 20 10 P0_1 RFO 10pF P0_5 19 9 VDD_A P0_2 RFI 3.9pF FI D 8 18 VDD_A P0_6 P0_1 1uF P0_7 VDD_R P0_0 C8 BP_BG 17 7 P0_0 VREF REGI 120pF VDD_P C10 P1_0 amc054_QFN40_OTP 16 6 N BPBG REGI 330pF 15 C7 VDD_D VDD_P 5 P1_1 XO VDD_D VDD_S 14 1uF P1_2 XI C9 J1 CON/5P 1.27 P1_3 RESTN CP 4 VPP 13 VDD_S U1 P1_4 XI C15 NC 3 1uF C4 C20 RESETN P3_7 11 0R L5 2 C6 L1 5.6nH ANTENNA L4 1 VPP VDD_V L2 3.9nH RTCO P3_5 RTCI 39 P3_6 C3 1U 12 C2 22p 22p 40 RESETN C1 VT RTCO RTCI R1 100K L REGI Sep., 2014, Version 0.6 (Preliminary) 126 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC TI A EN FI D O M C O N Analog to Digital Converter Auto IF Frequency Compensation Automatic Gain Control Bit Error Rate Bandwidth Carrier Detect Channel Step Cyclic Redundancy Check Direct Current Forward Error Correction First in First out Frequency Shift Keying Identifier In Circuit Emulator Inter-Integrated Circuit Intermediate Frequency Industrial, Scientific and Medical Local Oscillator Micro Controller Unit Phase Frequency Detector for PLL Phase Lock Loop Power on Reset Pulse width modulation Receiver Receiver Local Oscillator Received Signal Strength Indicator Serial to Parallel Interface System Clock for digital circuit Transmitter Transmitter Radio Frequency Universal Asynchronous Receiver/Transmitter Voltage Controlled Oscillator Crystal Oscillator Crystal Reference frequency Crystal A M IC C ADC AIF FC AGC BER BW CD CHSP CRC DC FEC FIFO FSK ID ICE 2 IC IF ISM LO MCU PFD PLL POR PWM RX RXLO RSSI SPI SYCK TX TXRF UART VCO XOSC XREF XTAL L 26. Abbreviations Sep., 2014, Version 0.6 (Preliminary) 127 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 27. Ordering Information Part No. Package Units Per Reel / Tray QFN48L, Pb Free, Tape & Reel, -40℃～85℃ 3K A81X05F5009AQ6C QFN48L, Pb Free, Tray, -40℃～85℃ 490EA A81X05F5001AQ5A/Q QFN40L, Pb Free, Tape & Reel, -40℃～85℃ A81X05F5001AQ5A QFN40L, Pb Free, Tray, -40℃～85℃ A81X05F5001AH Die form, -40℃～85℃ TI A A81X05F5009AQ6C/Q L A8105F5 (32KB) 3K 490EA EN 100EA A8105F4 (16KB) QFN40L, Pb Free, Tape & Reel, -40℃～85℃ A81X05F4001AQ5A QFN40L, Pb Free, Tray, -40℃～85℃ 490EA A81X05F4001AH Die form, -40℃～85℃ 100EA 3K A M IC C O M C O N FI D A81X05F4001AQ5A/Q Sep., 2014, Version 0.6 (Preliminary) 128 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 28. Package Information QFN6*6 48L Outline Dimensions Bottom View C O M C O N FI D EN TI A L Top View A M IC Symbol A A1 A3 b D D2 E E2 e L k Sep., 2014, Version 0.6 (Preliminary) Dimensions in inches Dimensions in mm Min 0.028 0 Nom 0.030 0.001 0.009 REF. Max 0.031 0.002 Min 0.7 0.00 0.006 0.008 0.010 0.15 0.179 3.70 0.179 3.70 0.020 0.32 0.146 0.146 0.013 0.240 0.177 0.240 0.177 0.016BSC 0.016 0.008 129 Nom 0.75 0.02 0.23REF. 0.2 6.0 BSC 4.50 6.0BSC 4.50 0.4BSC 0.4 0.2 Max 0.8 0.05 0.25 4.55 4.55 0.48 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC QFN5*5 32L Outline Dimensions Bottom View D D2 25 25 24 8 17 24 1 L 17 9 16 16 FI D D 0.25 C EN E E2 e 1 32 L 32 TI A D Top View 0 . 2 C5 e b 8 9 0.10 M C A B C O C O A A1 Min Nom Max Min Nom Max 0.030 0.036 0.70 0.75 0.90 0.001 0.002 0.00 0.02 0.05 0.000 0.010 REF 0.20 REF b 0.007 0.010 0.012 0.18 0.25 0.30 C IC M A Dimensions in mm 0.028 A3 Sep., 2014, Version 0.6 (Preliminary) y C Dimensions in inches M Symbol D A3 Seating Plane A A1 N // 0.10 C D 0.193 0.197 0.200 4.90 5.00 5.10 D2 0.049 0.106 0.141 1.25 2.70 3.60 E 0.193 0.197 0.200 4.90 5.00 5.10 E2 0.049 0.106 0.141 1.25 2.70 3.60 0.020 0.30 0.020 BSC e L y 0.012 0.016 0.50 BSC 0 - 0.004 130 0.40 0.50 0 - 0.10 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC A M IC C O M C O N FI D EN TI A L 29. Top Marking Information Sep., 2014, Version 0.6 (Preliminary) 131 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Part No. Pin Count Package Type Dimension Mark Method Character Type : A81X05F4001AQ5A : 40 : QFN : 5*5 mm : Laser Mark : Arial A M IC C O M C O N FI D EN TI A L       Sep., 2014, Version 0.6 (Preliminary) 132 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC Part No. Pin Count Package Type Dimension Mark Method Character Type : A81X05F5001AQ5A : 40 : QFN : 5*5 mm : Laser Mark : Arial A M IC C O M C O N FI D EN TI A L       Sep., 2014, Version 0.6 (Preliminary) 133 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC N FI D EN TI A L 30. Reflow Profile A M IC C O M C O Actual Measurement Graph Sep., 2014, Version 0.6 (Preliminary) 134 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 31. Tape Reel Information TYPE P QFN 3*3 8±0.1 3.25 ±0.1 4.35 ±0.1 5.25 ±0.1 QFN 4*4 8±0.1 QFN 5*5 8±0.1 QFN 6*6 12±0.1 6.3±0.1 6.3±0.1 4±0.2 P1 D0 D1 4±0.2 2±0.1 1.5±0.1 1.5 4±0.2 2±0.1 1.5±0.1 1.5 N 3.2 5±0.1 4.35 ±0.1 5.25 ±0.1 P0 C O B0 4±0.2 2±0.1 1.5±0.1 1.5 2±0.1 1.5±0.1 1.5±0.5 E F W 1.75 ±0.1 1.75 ±0.1 1.75 ±0.1 1.75 ±0.1 5.5 ±0.05 5.5 ±0.05 5.5 ±0.05 7.5 ±0.1 M A0 FI D EN TI A L Cover / Carrier Tape Dimension 1.25 ±0.1 1.2 5±0.1 1.25 ±0.1 1.15 ±0.2 12±0.3 12±0.3 12±0.3 16±0.3 t 0.3 9.3±0.1 ±0.05 0.3 9.3±0.1 ±0.05 0.3 9.3±0.1 ±0.05 0.3 13.3± ±0.05 0.1 T R D N A M L IC C O REEL DIMENSIONS K0 Unit: mm Cover tape width M K G Unit: mm TYPE G N M D K L R QFN3*3/4*4/5*5 12.9±0.5 102 REF±2.0 2.3±0.2 13.15±0.35 2.0±0.5 330±3.0 19.6±2.9 QFN6*6 17±0.5 102 REF±2.0 2.3±0.2 13.15±0.35 2.0±0.5 330±3.0 19.6±2.9 Sep., 2014, Version 0.6 (Preliminary) 135 AMICCOM Electronics Corporation A8105 2.4GHz FSK/GFSK SoC 32. Product Status Product Status Planned or Under Development Definition This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary Engineering Samples and First Production This data sheet contains preliminary data, and supplementary data will be published at a later date. AMICCOM reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. No Identification Noted Full Production Obsolete Not In Production This data sheet contains the final specifications. AMICCOM reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains specifications on a product that has been discontinued by AMICCOM. The data sheet is printed for reference information only. IC C O M C O N FI D EN TI A L Data Sheet Identification Objective RF ICs AMICCOM < A M Headquarter A3, 1F, No.1, Li-Hsin 1 Hsinchu, Taiwan 30078 Tel: 886-3-5785818 st Rd., Hsinchu Science Park, DataComm 2.4 GHz Shenzhen Office Rm., 2003, DongFeng Building, No. 2010, Shennan Zhonglu Rd., Futian Dist., Shenzhen, China Post code: 518031 Web Site http://www.amiccom.com.tw Sep., 2014, Version 0.6 (Preliminary) 136 AMICCOM Electronics Corporation