A7129
FSK/GFSK Sub 1GHz Transceiver
Document Title
315/433/480/510/868/915MHz FSK/GFSK Transceiver with 2K ~ 250Kbps
Revision History
Rev. No.
History
Issue Date
Remark
0.0
Initial issue
Sep., 2011
Objective
0.1
Modify description of Ch 12 and Ch 13
Feb., 2012
Preliminary
0.2
Update specification and A50 application circuit
April, 2012
Preliminary
0.3
Update Figure 13.1, PLLII (02h) and Fdev (06h, page0)
formula
June, 2012
Preliminary
0.4
Update register setting recommendation. Add Ch 20. Modify
VCOP and VCON position and ESD descriptions
Oct., 2012
Preliminary
Important Notice:
AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service
without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable
for use in life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such
applications is understood to be fully at the risk of the customer.
Oct., 2012, Version 0.4 (PRELIMINARY)
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
Table of contents
1. Typical Applications................................................................................................................................................. 4
2. General Description................................................................................................................................................. 4
3. Features ................................................................................................................................................................. 4
4. Pin Configurations ................................................................................................................................................... 5
5. RF Chip Block Diagram ........................................................................................................................................... 6
6. Pin Descriptions ...................................................................................................................................................... 6
7. Absolute Maximum Ratings ..................................................................................................................................... 7
8. Specification............................................................................................................................................................ 8
9. Control Register .................................................................................................................................................... 12
9.1 Control Register Table................................................................................................................................... 12
9.2 Control Register Description.......................................................................................................................... 13
9.2.1 System clock (Address: 00h) ............................................................................................................... 13
9.2.2 PLL I (Address: 01h) ........................................................................................................................... 13
9.2.3 PLL II (Address: 02h) .......................................................................................................................... 14
9.2.4 PLL III (Address: 03h) ......................................................................................................................... 14
9.2.5 PLL IV (Address: 04h) ......................................................................................................................... 14
9.2.6 PLL V (Address: 05h) .......................................................................................................................... 15
9.2.7 PLL VI (Address: 06h) ......................................................................................................................... 15
9.2.8 Crystal (Address: 07h)......................................................................................................................... 15
9.2.9 TX I (Address: 08h) Page 0 ................................................................................................................. 16
9.2.9.1 WOR I (Address: 08h) Page1 ........................................................................................................... 16
9.2.9.2 WOR II (Address: 08h) Page 2 ......................................................................................................... 17
9.2.9.3 RF Current (Address: 08h) Page 3.................................................................................................... 17
9.2.9.4 Power Manage (Address: 08h) Page 4.............................................................................................. 18
9.2.9.5 AGC RSSI Threshold (Address: 08h) Page 5 .................................................................................... 18
9.2.9.6 AGC Control(Address: 08h) Page 6 .................................................................................................. 19
9.2.9.7 AGC Control II(Address: 08h) Page 7 ............................................................................................... 19
9.2.9.8 GPIO (Address: 08h) Page 8 ........................................................................................................... 20
9.2.9.9 CKO (Address: 08h) Page 9 ............................................................................................................. 21
9.2.9.10 VCO current (Address: 08h) Page 10.............................................................................................. 22
9.2.9.11 Channel Group (I) (Address: 08h) Page 11...................................................................................... 23
9.2.9.12 Channel Group (II) (Address: 08h) Page 12..................................................................................... 23
9.2.9.13 FIFO (Address: 08h) Page 13 ......................................................................................................... 23
9.2.9.14 Code (Address: 08h) Page 14......................................................................................................... 23
9.2.9.15 WCAL (Address: 08h) Page 15....................................................................................................... 24
9.2.10.0 TX II (Address: 09h) Page 0............................................................................................................ 24
9.2.10.1 IFI (Address: 09h) Page1................................................................................................................ 25
9.2.10.2 IFII (Address: 09h) Page2............................................................................................................... 25
9.2.10.3 ACK (Address: 09h) Page3............................................................................................................. 25
9.2.10.4 ART (Address: 09h) Page4 ............................................................................................................. 27
9.2.11 RX I (Address: 0Ah) .......................................................................................................................... 27
9.2.12 RX II (Address: 0Bh) ......................................................................................................................... 28
9.2.13 ADC (Address: 0Ch).......................................................................................................................... 28
9.2.14 Pin Control (Address: 0Dh)................................................................................................................ 29
9.2.15 Calibration (Address: 0Eh)................................................................................................................. 30
9.2.16 Mode control (Address: 0Fh) ............................................................................................................. 31
10. SPI (3-wire) ......................................................................................................................................................... 32
10.1 SPI Format ................................................................................................................................................. 32
10.2 SPI Timing Chart ........................................................................................................................................ 33
10.3 Control register access ............................................................................................................................... 33
10.4 SPI Timing Specification ............................................................................................................................. 33
10.5 Reset Command......................................................................................................................................... 34
10.6 Reset TX FIFO Pointer................................................................................................................................ 34
10.7 Reset Rx FIFO Pointer................................................................................................................................ 34
10.8 ID Read/Write Command ............................................................................................................................ 34
10.9 FIFO R/W Command .................................................................................................................................. 35
11. Crystal Oscillator ................................................................................................................................................. 36
11.1 Use External Crystal ................................................................................................................................... 36
11.2 Use External Clock ..................................................................................................................................... 36
12. System Clock ...................................................................................................................................................... 37
12.1 Clock Domain ............................................................................................................................................. 37
12.2 System Clock and IF Filter .......................................................................................................................... 38
12.3 Example of 10Kbps data rate by 12.8MHz Xtal ............................................................................................ 38
Oct., 2012, Version 0.4 (PRELIMINARY)
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
12.4 Example of special data rate by 19.6608MHz Xtal........................................................................................ 39
13. Tranceiver Frequency .......................................................................................................................................... 41
14. State machine ..................................................................................................................................................... 42
14.1 Key Strobe Commands ............................................................................................................................... 42
14.2 FIFO mode ................................................................................................................................................. 42
14.3 Direct mode................................................................................................................................................ 44
15. Calibration........................................................................................................................................................... 46
15.1 IF Calibration Process................................................................................................................................. 46
15.2. VCO band Calibration Process................................................................................................................... 46
16. FIFO (First In First Out)........................................................................................................................................ 47
16.1 Packet Format ............................................................................................................................................ 47
16.2 Bit Stream Process ..................................................................................................................................... 47
16.3 Transmission Time...................................................................................................................................... 48
16.4 Usage of TX and RX FIFO .......................................................................................................................... 48
16.4.1 Easy FIFO Mode............................................................................................................................... 49
16.4.2 Segment FIFO .................................................................................................................................. 49
16.4.3 FIFO Extension................................................................................................................................. 51
17. Analog Digital Converter ...................................................................................................................................... 55
17.1 Temperature Measurement ......................................................................................................................... 55
17.2 RSSI Measurement..................................................................................................................................... 55
17.3 Carrier detect.............................................................................................................................................. 55
18. Battery Detect ..................................................................................................................................................... 55
19. TX power setting ................................................................................................................................................. 56
20. Low Current RX mode setting .............................................................................................................................. 56
21. Application Circuit................................................................................................................................................ 57
21.1 MD7129-A40 (434MHz Band) ..................................................................................................................... 57
21.2 MD7129-A50 (470MHz~510MHz Band)....................................................................................................... 58
21.3 MD7129-A80 (868MHz Band) ..................................................................................................................... 59
22. Abbreviations ...................................................................................................................................................... 60
23. Ordering Information............................................................................................................................................ 60
24. Package Information............................................................................................................................................ 61
25. Top Marking Information....................................................................................................................................... 62
26. Reflow Profile ...................................................................................................................................................... 63
27. Tape Reel Information ......................................................................................................................................... 64
28. Product Status..................................................................................................................................................... 66
Oct., 2012, Version 0.4 (PRELIMINARY)
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
1. Typical Applications
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ISM Band Data Communication
Wireless Remote Controller
RKE (Remote Keyless Entry)
Building Automation
Home Security
Wireless Sensor Networking
Energy Control and Management
RKE (Remote Keyless Entry)
AMR (Auto Metering Reading)
2. General Description
A7129 is a monolithic low-IF architecture CMOS FSK/GFSK TRX for wireless applications in the 315/433/470/510/868/
915MHz ISM bands. This device is especially suitable for battery-powered application and the 470MHz ~ 510MHz
wireless AMR (Auto Meter Reading) in China and 868.3MHz wireless M-bus in Europe.
A7129 is one of AMICCOM’s Mini Power Consumption Family in sub 1GHz ISM band product line. A7129 is optimized
for very low power consumption (i.e. 434MHz band, 3.8mA @ RX mode and 24 mA @ TX mode,10.5dBm). In addition,
A7129 can offer a very good link budget with a high efficient class-E power amplifier up to 12 dBm and a low phase
noise receiver (- 110 dBm RX sensitivity @ 100Kbps / FSK / 433.92MHz). Therefore, A7129 is very suitable for battery
powered application with a nice LOS (line-of-sight) wireless range.
A7129 incorporates a baseband modem with the programmable data rate divider from 2K to 250Kbps. For a battery
powered system, A7129 supports fast PLL settling time (120 us), Xtal settling time (1100 us) and on-chip Regulator
settling time (850 us) to reduce average power consumption. The RF synthesizer contains a VCO and a low noise
fractional-N PLL with an output channel frequency resolution of 366 Hz. The VCO frequency operates at to the wanted
radio frequency to cover all RF band. Since A7129 is a low-IF architecture TRX with programmable IFBW (IF Filter
Bandwidth, 50KHz/100KHz/150KHz/250KHz), the RXLO shall be configured to offset an intermediate frequency (IF) to
TXRF regarding to the IFBW setting.
A7129’s control registers are accessed via 3-wire or 4-wire SPI interface including TX/RF FIFO, VCO frequency, to
chip calibration procedures. Another one, via SPI as well, is the unique Strobe command, A7129 can be controlled from
power saving mode (deep sleep, sleep, idle, standby), PLL mode, TX mode and RX mode. In addition to SPI, the digital
connections between A7129 and MCU are GIO1 and GIO2 (multi-function GPIO) to indicate A7129’s status so that MCU
could use either polling or interrupt for radio control.
For packet handling, A7129 supports direct mode and FIFO mode. In direct mode, MCU or Encoder shall deliver the
defined packet (preamble + sync word + payload) to GIO1 or GIO2/TXD pin. Then, in RX mode, MCU or Decoder can
receive the coming packet (preamble + sync word + payload) in bit sequence from GIO1 or GIO2/RXD pin.
In FIFO mode, preamble is self-generated by A7129. User just needs to assign the sync word to this device by ID R/W
command via SPI. For payload, the built-in separated 64-bytes TX/RX FIFO are used to be this purpose to let user R/W
the wanted payload. User can also enable additional packet features like CRC for error detection, FEC (hamming 7 by 4)
for 1-bit data correction per code word, Manchester coding, as well as data whitening for data encryption / decryption.
Additional device features such as on-chip regulator, RSSI for clear channel assessment, a thermal sensor, low battery
detector, carrier detect, preamble detect, frame sync in FIFO mode, auto-ack and auto-resend, AIF (Auto IF function),
AFC (Auto Frequency compensation), Auto calibration (VCO, IF Filter), PLL/CLK Generator, on-chip compensated
capacitors of Xtal loading, and WOR (Wake on RX) to support the ability to periodically wake up from sleep mode to RX
mode and listen for incoming packets without MCU interaction, can be used to simplify system development and cost.
Overall, A7129’s highly integrated features and low current consumption offer a reduced BOM cost for a high
performance ISM bands product. All features are integrated in a small QFN 4X4 24 pins package.
3. Features
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Small size (QFN 4X4, 24 pins).
Frequency band: 315/433/470/510/868/915 MHz.
FSK and GFSK modulation.
Programmable data rate from 2Kbps to 250Kbps.
Programmable TX power level from – 40 dBm to 12 dBm.
On chip regulator, supports input voltage 2.2 ~ 3.6 V.
Deep sleep current (0.5uA).
Sleep current (1.5 uA).
Oct., 2012, Version 0.4 (PRELIMINARY)
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
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Ultra Low Current Consumption
u
RX Current consumption (AGC Off) 434MHz: 3.8mA.
u
RX Current consumption (AGC Off) 868MHz: 4.4mA.
u
TX Current consumption 433MHz: 24mA @ 10.5dBm.
u
TX Current consumption 868MHz: 24mA @ 10dBm.
Fast PLL settling time (120 us).
Supports low cost crystal (12.8 / 16 / 19.2 MHz).
AGC (Auto Gain Control) for the wide RSSI dynamic range.
Programmable IF filter bandwidth (50KHz / 100KHz / 150KHz / 250KHz).
High RX sensitivity, i.e. 490MHz.
u
-118dBm at 2Kbps on-air data rate.
u
-115dBm at 50Kbps on-air data rate.
u
-109dBm at 100Kbps on-air data rate.
Easy to use
u
Support 3-wire or 4-wire SPI.
u
Unique Strobe command via SPI.
u
AGC ON with 9-bits RSSI.
u
AGC OFF with 8-bits RSSI.
u
Auto Calibrations (VCO, IF Filter, RSSI).
u
Auto IF function.
u
Auto Frequency Compensation.
u
Auto CRC Filtering.
u
Auto FEC by (7, 4) Hamming code (1 bit error correction / code word).
u
Auto-resend (max 15 cycles).
u
Auto-acknowledgement.
u
Manchester encoding.
u
Programmable carrier sense indicator.
u
Data Whitening for payload encryption and decryption.
u
Separated 64 bytes RX and TX FIFO.
u
Easy FIFO / Segment FIFO / FIFO Extension (16K bytes to infinite).
u
Support FIFO mode with frame sync to MCU.
u
Support direct mode with recovery clock output to MCU.
On chip 8-bits ADC.
Low Battery indication.
On-chip low power RC oscillator for WOT and WOR (Wake on TX/RX) function.
19
CKO
21
GIO2
GIO1
REGI
22
20
VDD_A
23
24
BP_BG
4. Pin Configurations
VDD_D
GND
2
17
VDD_D
RFI
3
16
SDIO
RFO
4
15
SCK
VDD_TX
5
14
SCS
6
13
GND
XO
9
VT
XI
8
VCON
VDD_PLL
7
VCOP
VDD_VCO
12
18
11
1
10
RSSI
Figure 4.1 QFN4x4 Package Top View
Oct., 2012, Version 0.4 (PRELIMINARY)
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
5. RF Chip Block Diagram
Figure 5.1 System Block Diagram
6. Pin Descriptions
Note: I (input), O(output), G(Ground).
Pin No.
Symbol
I/O
1
RSSI
I/O
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND
RFI
RFO
VDD_TX
VDD_VCO
VCON
VCOP
VT
VDD_PLL
XI
XO
GND
SCS
SCK
SDIO
VDD_D
VDD_D
G
I
O
O
I
I
I
O
O
I
O
O
DI
DI
DI/O
O
O
Oct., 2012, Version 0.4 (PRELIMINARY)
Function Description
I: ADC input.
O: RSSI bypass. Connect to bypass capacitor.
Ground.
RF input. Connect to matching circuit.
RF output. Connect to matching circuit. (recommend powered by VDD directly).
TX supply voltage input.
VCO supply voltage input.
VCO negative pin, connected to external inductor.
VCO positive pin, connected to external inductor.
Charge-pump output. Connect to loop filter.
PLL supply voltage input.
Crystal oscillator input. Connect to tank capacitor.
Crystal oscillator output. Connect to tank capacitor.
Digital ground pin.
SPI chip select input.
SPI clock input.
SPI data IO.
Digital supply voltage output. Connect to bypass capacitor.
Digital supply voltage output. Connect to bypass capacitor.
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
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20
21
22
23
24
GIO1
GIO2
CKO
REGI
VDD_A
BP_BG
DI/O
DI/O
DO
I
O
O
Back side plate
G
Multi-function IO 1 / SPI data output.
Multi-function IO 2 / SPI data output.
Multi-function clock output.
Regulator input. Connect to VDD supply.
Analog supply voltage output. Connect to bypass capacitor.
Band-gap bypass. Connect to bypass capacitor.
Ground. Backside plate shall be well solder to ground; otherwise, it will
impact RF performance.
7. Absolute Maximum Ratings
Parameter
With respect to
Rating
Unit
Supply voltage range (VDD)
GND
-0.3 ~ 3.6
V
Digital IO pins range
GND
-0.3 ~ VDD+0.3
V
Voltage on the analog pins range
GND
-0.3 ~ 2.1
V
10
dBm
-55 ~ 125
°C
HBM*
± 2K
V
MM*
± 200
V
Max. Input RF level
Storage Temperature range
ESD Rating
*Stresses above those listed under “Absolute Maximum Rating” may cause permanent damage to the device. These are stress ratings
only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
*Device is ESD sensitive. Use appropriate ESD precautions. HBM (Human Body Mode) is tested under MIL-STD-883F Method 3015.7.
MM (Machine Mode) is tested under JEDEC EIA/JESD22-A115-A. Except Pin 5 (VDD_TX) and Pin 6 (VDD_VCO) are HBM ± 1KV.
*Device is Moisture Sensitivity Level III (MSL 3).
*Pin 3 (RFI) and Pin 7/8 (VCOP/VCON) are HBM ± 1KV and MM ± 100V
*Pin 4(RFO) is -2KV and -200V of HBM and MM, respectively. No ESD protection diode connected to positive power supply.
Oct., 2012, Version 0.4 (PRELIMINARY)
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
8. Specification
(Ta=25℃, VDD=3.3V, FXTAL =12.8MHz, FSK modulation with Matching circuit and low pass filter)
Parameter
Description
Min.
Typ.
Max.
Unit
85
3.3
0.3
3.6
°C
V
uA
General
Operating Temperature
-40
Supply Voltage
Current Consumption
2.2
Deep Sleep Mode
(no register retention) 1
Sleep Mode (WOR Off) 1
Sleep Mode (WOR On) 1
Idle Mode(Xtal off)
Standby Mode(Xtal on)
PLL mode
1.5
2.5
0.14
0.5
2
uA
uA
mA
mA
mA
RX mode (AGC Off)
3.6
mA
Low Current RX mode (AGC Off)
TBD
mA
TX -40dBm (TBG=0, TDC=0, PAC=0)
TBD
mA
TX 9dBm
TBD
mA
Current Consumption
315MHz band
(TBG=6, TDC=1, PAC=1)
TX 11dBm
(TBG=7, TDC=2, PAC=1)
TBD
mA
TX 13dBm
(TBG=7, TDC=3, PAC=3)
PLL mode
TBD
2
mA
mA
RX mode (AGC Off)
3.8
mA
Low Current RX mode (AGC Off)
3
mA
TBD
mA
Current Consumption
434MHz band
TX -40dBm (TBG=0, TDC=0, PAC=0)
TBD
mA
TBD
mA
PLL mode
TBD
2
mA
mA
RX mode (AGC Off)
3.8
mA
Low Current RX mode (AGC Off)
3.1
mA
TX -32dBm (TBG=0, TDC=0, PAC=0)
15
mA
TX 11dBm
(TBG=3, TDC=2, PAC=0)
30
mA
TX 13dBm
(TBG=7, TDC=2, PAC=1)
TBD
mA
PLL mode
2.5
mA
RX mode (AGC Off)
4.4
mA
Low Current RX mode (AGC Off)
TBD
mA
TBD
mA
TX 9dBm (TBG=7, TDC=1, PAC=1)
TBD
mA
TX 11dBm
(TBG=7, TDC=2, PAC=1)
TBD
mA
TX 13dBm
(TBG=7, TDC=3, PAC=3)
TBD
mA
PLL mode
2.5
mA
RX mode (AGC Off)
4.4
mA
Low Current RX mode (AGC Off)
TBD
mA
TX -40dBm (TBG=0, TDC=0, PAC=0)
TBD
mA
TX 9dBm
TBD
mA
TX 9dBm
(TBG=7, TDC=0, PAC=1)
TX 10.5dBm
TX 12dBm
Current Consumption
470MHz ~ 510MHz band
(without LPF)
Current Consumption
868MHz band
TX -40dBm
Current Consumption
915MHz band
Oct., 2012, Version 0.4 (PRELIMINARY)
(TBG=7, TDC=2, PAC=1)
(TBG=7, TDC=3, PAC=3)
(TBG=0, TDC=0, PAC=0)
(TBG=7, TDC=0, PAC=1)
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
TX 11dBm
(TBG=7, TDC=2, PAC=1)
TBD
mA
TX 13dBm
(TBG=7, TDC=3, PAC=3)
TBD
mA
1.1
12.8/16/19.2
16
12.582912
19.6608
Phase Locked Loop
X’TAL Settling Time
X’TAL frequency
Couple=0, low current
Data rate (2K/10K/50K/100K/150Kbps)
Data rate (250Kbps)
Data rate (32.768Kbps / 16.384Kbps)
Data rate (38.4Kbps / 19.2Kbps / 9.6Kbps)
Recommend
PN @100KHz offset
PN @500KHz offset
PN @1MHz offset
PN @100KHz offset
PN @500KHz offset
PN @1MHz offset
PN @100KHz offset
PN @500KHz offset
PN @1MHz offset
PN @100KHz offset
PN @500KHz offset
PN @1MHz offset
PN @100KHz offset
PN @500KHz offset
PN @1MHz offset
20
85
105
110
85
105
110
85
105
110
81
102
109
83
105
112
ms
MHz
MHz
MHz
MHz
Ohm
pF
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
PLL Settling Time
@settle to ± 25kHz (1st packet)
Standby to PLL
750
ms
PLL Settling Time
@settle to ± 7.5kHz
Standby to PLL
120
ms
X’TAL ESR
X’TAL Capacitor Load (Cload)
315MHz PLL Phase noise
100
(loop component:
R1=8.2K,C1=22nF,C2=150pF)
434MHz PLL Phase noise
(loop component:
R1=8.2K,C1=22nF,C2=150pF)
490MHz PLL Phase noise
(loop component:
R1=8.2K,C1=22nF,C2=150pF)
868MHz PLL Phase noise
(loop component:
R1=8.2K,C1=22nF,C2=150pF)
915MHz PLL Phase noise
(loop component:
R1=8.2K,C1=22nF,C2=150pF)
Transmitter
TX Power Range
TX Power Range
TX Settling Time
TX Spurious Emission
1. Pout = 10 dBm
2. with LPF
480MHz
868MHz
PLL to TX
-31
-40
10
10
60
f < 1GHz
(RBW =100kHz)
47MHz< f Standby -> RX -> Sleep.
[1]: While WN≥1, the WOT/WOR operating will return to PLL mode. For example, if WN=2, the WOR operation period
will be: Sleep -> RX -> PLL -> RX -> PLL -> RX -> Sleep.
RGV [1:0]: Digital Regulator Voltage select. Recommend RGV = [11].
[00]: 1.2V
[01]: 1.4V
[10]: 1.6V
[11]: 1.8V
QDS: VDD_A Quick Discharge select. Recommend QDS = [1].
[0]: Normal. [1]: Quick discharge.
BVT [2:0]: Battery Voltage Threshold select.
[000]: 2.0V. [001]: 2.1V. [010]: 2.2V. [011]: 2.3V. [100]: 2.4V. [101]: 2.5V. [110]: 2.6V. [111]: 2.7V.
BDS: Battery Detection selection.
[0]: Disable. [1]: Enable.
9.2.9.5 AGC RSSI Threshold (Address: 08h) Page 5
Address/Name R/W Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9
08h
RTH
Reset
W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRTH7 IRTH6 IRTH5 IRTH4 IRTH3 IRTH2 IRTH1 IRTH0 IRTL7 IRTL6
IRTL5
IRTL4
IRTL3
IRTL2
IRTL1
IRTL0
0
0
0
0
0
0
0
0
0
Oct., 2012, Version 0.4 (PRELIMINARY)
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0
0
0
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Bit 8
0
Bit 7
0
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
IRTH[7:0]: AGC high Threshold. Recommend IRTH = [0x03].
IRTL[7:0]: AGC low Threshold. Recommend IRTL = [0x02].
If ADC ≤ IRTL.
If ADC ≥ IRTH.
If IRTL ≤ ADC ≤ IRTH.
DVT[1:0] (0Eh) = 11.
DVT[1:0] (0Eh) = 00.
DVT[1:0] (0Eh) = 01.
9.2.9.6 AGC Control(Address: 08h) Page 6
Address/Name R/W Bit15 Bit14 Bit13 Bit12
08h
AGC
W
R
Reset
EXTL VRSEL MS
Bit11
Bit10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MSCL4 MSCL3 MSCL2 MSCL1 MSCL0 HDM AGCE ERSSM EXRSI LGM1 LGM0 MGM1 MGM0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0
0
0
0
0
0
0
0
0
0
LGC1 LGC0 MGC1 MGC0
1
1
1
1
EXTL: VCO Calibration test bit. EXTL shall be [0].
VRSEL: AGC Function select.
[0]: RSSI AGC. [1]: wideband AGC.
MS: AGC Manual Scale select. Recommend MS = [0].
[0]: Auto (RL−RH).
[1]: Manual by MSCL[4:0].
MSCL[4:0]: AGC Manual Scale setting.
HDM: AGC HOLD select.
[0]: No hold.
[1]: Hold Gain Switching when ID is sync.
AGCE: Auto Gain Control Enable.
[0]: Disable. [1]: Enable.
ERSSM : Ending mode for RSSI measurement. Recommend ERSSM = [0].
[0]: RSSI value frozen before leaving RX.
[1]: RSSI value frozen when valid frame sync (ID and header check ok).
EXRSI: Reserved. EXRSI shall be [0].
LGM [1:0]: LNA Gain Attenuation select. Recommend LGM = [00].
[00]: -18dB. [01]: -12dB. [10]: -6dB. [11]: Max.
MGM [1:0]: Mixer Gain Attenuation select. Recommend MGM = [00].
[00]: -18dB. [01]: -12dB. [10]: -6dB. [11]: Max.
LGC[1:0]: LNA Gain Check (Read Only).
MGC[1:0]: Mixer Gain Check (Read Only).
9.2.9.7 AGC Control II(Address: 08h) Page 7
Address/Name R/W Bit15
08h
AGC2
Reset
W
R
Bit14
Bit13
Bit12
Bit11 Bit10
Bit 9
Bit 8
Bit 7
RGVA1 RGVA0 RGVT1 RGVT0 LHM1 LHM0 MHM1 MHM0 IGM1
--
--
--
--
--
--
--
--
LHC1 LHC0
--
MHC1 MHC0 IGC1
--
--
--
--
Bit 6
Bit 5
Bit 4
IGM0
CA1
CA0 TXIB1 TXIB0 RSAGC1 RSAGC0
IGC0
--
--
--
--
--
--
--
--
0
0
0
0
--
Bit 3
Bit 2
Bit 1
RGVA[1:0]: Analog Regulator Voltage Select. Recommend RGVA = [11].
[00]: 0.9V
[01]: 1.0V
[10]: 1.1V
[11]: 1.2V
RGVT[1:0]: PA Regulator Voltage Select. Recommend RGVT = [10].
[00]: 1.8V
[01]: 1.9V
[10]: 2.0V
[11]: 2.1V
LHM[1:0]: LNA Current Select. Recommend LHM = [10].
[00]: min.
[01]: mid.
[10]: high
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Bit 0
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FSK/GFSK Sub 1GHz Transceiver
[11]: max
LHC[1:0]: LNA Current Check. (Read only)
MHM[1:0]: Mixer Current Select. Recommend MHM = [10].
[00]: min.
[01]: mid.
[10]: high
[11]: max
MHC[1:0]: Mixer Current Check. (Read only)
IGM[1:0]: BPF Gain Select. Recommend IGM = [11].
[00]: -18dB. [01]: -12dB. [10]: -6dB. [11]: Max.
IGC[1:0]: BPF Gain Check. (Read only)
CA[1:0]: AGC peak detect test bit. CA shall be [00].
TXIB[1:0]: Reserved. TXIB shall be [00].
RSAGC[1:0]: Reserved. RSAGC shall be [00].
9.2.9.8 GPIO (Address: 08h) Page 8
Address/Name R/W Bit15
08h
GPIO
Reset
W
Bit14
Bit13
Bit12
Bit11
Bit10
Bit 9
Bit 8
Bit
Bit 6
7
Bit 5
Bit 4
Bit 3
Bit 2
Bit
Bit 0
1
WRCKS MCNT1 MCNT0 DDPC GIO2S3 GIO2S2 GIO2S1 GIO2S0 G2I G2OE GIO1S3 GIO1S2 GIO1S1 GIO1S0 G1I G1OE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WRCKS: WOR Reference clock select.
[0]: WOR Ref clock when PF8M is equal or close to 6.4MHz.
[1]: WOR Ref clock when PF8M is equal or close to 8MHz.
MCNT[1:0]: Main Clock Divider.
[00]:
f MCNT
=
[01]:
f MCNT
f MCNT
f MCNT
=
[10]:
[11]:
=
=
f MSCK
f MSCK / 2
f MSCK / 3
f MSCK / 4
Please refer to Chapter 12 for details.
DDPC (Direct mode data pin control): Direct mode modem data can be accessed via SDIO pin.
[0]: Disable. [1]: Enable.
GIO2S [3:0]: GIO2 pin function select.
GIO2S [3:0]
[0000]
[0001]
[0010]
[0011]
[0100]
[0101]
[0110]
[0111]
[1000]
[1001]
[1010]
[1011]
[1100]
[1101]
[1110]
[1111]
TX state
RX state
ARCWTR (Wait until TX or RX finished)
EOAC (end of access code)
FSYNC (frame sync)
TMEO (TX modulation enable)
CD (carrier detect)
External sync input (for direct mode), when SCT=0
Preamble Detect Output (PMDO), when SCT=1
MCU wakeup signal (TWWS) or WTR
Quadrature phase demodulator input (DMII).or DVT[0](AGC)
SDO (4 wires SPI data out)
TRXD In/Out (Direct mode)
RXD (Direct mode)
TXD (Direct mode)
PDN_TX
External FSYNC input in RX direct mode *
VPOAK (Valid Packet or Auto ACK OK Output)
FPF
Battery Detect flag. (BDF)
FMRDI. (FIFO mode RX input for testing) (for internal testing)
If GIO2S = [1011] and direct mode is selected, the internal frame sync function will be disabled. In such case, A7129
supports to accept an external frame sync signal from MCU to feed to GIO2 pin to determine the timing of fixing DC
estimation voltage of demodulator.
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FSK/GFSK Sub 1GHz Transceiver
G2I: GIO2 pin output signal invert.
[0]: Non-inverted output. [1]: Inverted output.
G2OE: GIO2 pin output enable.
[0]: High Z. [1]: Enable.
GIO1S [3:0]: GIO1 pin function select.
GIO1S [3:0]
[0000]
[0001]
[0010]
[0011]
TX state
RX state
ARCWTR (Wait until TX or RX finished)
EOAC (end of access code)
FSYNC (frame sync)
TMEO (TX modulation enable)
CD (carrier detect)
External sync input (for direct mode), when SCT=0
Preamble Detect Output (PMDO), when SCT=1
TWOR
In phase demodulator input(DMIQ) or DVT[1](AGC)
SDO (4 wires SPI data out)
TRXD In/Out (Direct mode)
RXD (Direct mode)
TXD (Direct mode)
PDN_RX
External FSYNC input in RX direct mode *
VPOAK (Valid Packet or Auto ACK OK Output)
FPF
PDN_TX
FMTDO (FIFO mode TX Data Output testing)
[0100]
[0101]
[0110]
[0111]
[1000]
[1001]
[1010]
[1011]
[1100]
[1101]
[1110]
[1111]
If GIO1S = [1011] and direct mode is selected, the internal frame sync function will be disabled. In such case, A7129
supports to accept an external frame sync signal from MCU to feed to GIO1 pin to determine the timing of fixing DC
estimation voltage of demodulator.
G1I: GIO1 pin output signal invert.
[0]: Non-inverted output. [1]: Inverted output.
G1OE: GIO1pin output enable.
[0]: High Z. [1]: Enable.
9.2.9.9 CKO (Address: 08h) Page 9
Address/Name R/W Bit15 Bit14
08h
CKO
Reset
W
INTXC XCL4
0
1
Bit13
Bit12 Bit11 Bit10
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XCL3
XCL2 XCL1 XCL0 WSEL2 WSEL1 WSEL0 CKS3
CKS2
CKS1
CKS0
CKOI
CKOE
SCT
0
0
0
0
0
0
0
0
0
0
Bit 9
0
Bit 8
Bit 7
1
0
0
INTXC: Internal Crystal Load selection. Recommend INTXC = [1].
[0]: Use external capacitors. [1]: Use on-chip capacitors.
XCL[4:0]: On-chip Crystal Capacitor Load setting.
Set XCL = [10000] as the first value to fine tune the carrier frequency and minimize the frequency drift if Xtal Cload =
20pF.
XCL is active when INTXC=1 and Each XCL step is typical 1.68 pF.
XCL is the on-chip capacitor for Xtal oscillator to fine tune offset frequency of the wanted RF carrier.
Please refer to chapter 11 or contact AMICCOM’s FAE.
XCL[4:0]
00000
00001
00010
…
11110
11111
Xtal C-load (pF)
0
1.68
3.36
50.4
52.08
WSEL[2:0]: Crystal Settling Delay setting (200us ~ 2.5ms). Recommend WSEL = [011].
[000]: 200us. [001]: 400us. [010]: 600us. [011]: 800us.
[100]: 1ms. [101]: 1.5ms. [110]: 2ms. [111]: 2.5ms.
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FSK/GFSK Sub 1GHz Transceiver
C ry s ta l
O s c illa to r
Id le
m o de
T X o r R X m od e
W SEL
35 0 us
G IO 1 P in
(W T R )
P a ck e t ( P r e a m b le + ID + P a ylo a d )
R F O P in
PD L
TD L
CKOS [3:0]: CKO pin output select.
[0000]: DCK (TX data clock).
[0001]: RCK (RX recovery clock).
[0010]: FPF (FIFO pointer flag for FIFO extension).
[0011]: Logic OR gate by EOP, EOVBC, EOFBC, EOVCC, EOVDC and RSSC_OK. (Internal usage only).
[0100]: BBCK.
[0101]: BBCK.
[0110]: BBCK.
[0111]: 0.
[1000]: WCK.
[1001]: PF8M (FSYCK ).
[1010]: ROSC.
[1011]: EOADC.
[1100]: OKADCN.
[1101]: EOCAL.
[1110]: VPOAK.
[1111]: Reserved.
CKOI: CKO pin Output signal invert.
[0]: Non-inverted output. [1]: Inverted output.
CKOE: CKO pin Output Enable.
[0]: High Z. [1]: Enable.
SCT: Reserved. SCT shall be [1].
9.2.9.10 VCO current (Address: 08h) Page 10
Address/Name R/W Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9 Bit 8 Bit 7 Bit 6
CDTM CDTM
1
0
08h
VCB
W
R
-
-
FEP
13
-
Reset
0
0
0
0
FEP
12
-
FEP
11
-
FEP
10
-
0
0
0
FEP9 FEP8 PKT1 PKT0
Bit 5
PKS
Bit 4
Bit 3
Bit 2
Bit 1
VCOC3 VCOC2 VCOC1 VCOC0
Bit 0
MVCS
-
-
-
-
-
VCCF
VCB3
VCB2
VCB1
VCB0
0
0
-
-
-
0
0
0
0
0
FEP[13:8]: FIFO End Pointer for TX FIFO and Rx FIFO. Please see 9.2.9.13 FIFO (address:08h) Page 13.
CDTM[1:0]: Carrier detect number of times setting.
[00]: 16. [01]: 32 [10]: 64. [11]:128
PKT[1:0]: VCO Peak Detect threshold test bit. PKT shall be [00].
PKS: VCO Current Calibration Mode Select. Recommend PKS = [0].
[0]: Normal.
[1]: VCO current calibration by peak detection.
VCOC [3:0]: VCO Current Bank Calibration result. Recommend VCOC = [0010].
If SWT = [0] @ 0Fh, then VCOC= [1000].
If SWT = [1] @ 0Fh, then VCOC[3:0] = Manual setting.
MVCS: VCO current calibration select. Recommend MVCS = [0].
[0]: Auto. [1]: Manual.
VCCF : VCO Current Auto Calibration Flag (Read Only).
[0]: Pass. [1]: Fail.
VCB [3:0]: VCO Current Bank Calibration Value (Read Only).
MVCS= 0: Auto calibration value.
MVCS= 1: Manual calibration value.
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9.2.9.11 Channel Group (I) (Address: 08h) Page 11
Address/Name R/W Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9 Bit 8 Bit 7
08h
CHG1
Reset
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
FPL3
FPL2 FPL1 FPL0 IPL7
IPL6
IPL5
IPL4
IPL3
IPL2
IPL1
IPL0
R
FPL3
FPL2 FPL1 FPL0 IPL7
IPL6
IPL5
IPL4
IPL3
IPL2
IPL1
IPL0
0
0
0
0
0
0
0
0
0
0
0
0
FPL [3:0]: VCO Calibration Fractional Part Setting for Low Boundary Channel Group.
Please refer to A7129’s reference code for the wanted RF band.
IPL [7:0]: VCO Calibration Integer Part Setting for Low Boundary Channel Group.
Please refer to A7129’s reference code for the wanted RF band.
9.2.9.12 Channel Group (II) (Address: 08h) Page 12
Address/Name R/W Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9 Bit 8 Bit 7
08h
CHG2
Reset
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
FPH3 FPH2 FPH1 FPH0 IPH7
IPH6
IPH5
IPH4
IPH3
IPH2
IPH1
IPH0
R
FPH3 FPH2 FPH1 FPH0 IPH7
IPH6
IPH5
IPH4
IPH3
IPH2
IPH1
IPH0
0
0
0
0
0
0
0
0
0
0
0
0
FPH [3:0]: VCO Calibration Fractional Part Setting for High Boundary Channel Group.
Please refer to A7129’s reference code for the wanted RF band.
IPH [7:0]: VCO Calibration Integer Part Setting for High Boundary Channel Group.
Please refer to A7129’s reference code for the wanted RF band.
9.2.9.13 FIFO (Address: 08h) Page 13
Address/Name R/W Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
08h
W FPM1 FPM0 PSA5 PSA4 PSA3 PSA2 PSA1 PSA0 FEP7 FEP6 FEP5 FEP4 FEP3 FEP2 FEP1 FEP0
FIFO
Reset
0
1
0
0
0
0
0
0
0
0
1
1
0
1
1
1
FPM [1:0]: FIFO Pointer Margin.
FPM is used in FIFO extension mode for an indicator.
FPM[1:0] Bytes in TX FIFO Bytes in RX FIFO
[00]
[01]
[10]
[11]
4
8
12
16
60
56
52
48
PSA [5:0]: Used for Segment FIFO.
Used in FIFO segment mode.
FEP [13:0]: FIFO End Pointer for TX FIFO and Rx FIFO.
Where FEP[7:0] are located at here and FEP[13:8] are located at 08h page 10.
FIFO Length Setting = (FEP [13:0] +1).
For example, if FEP = 0x3F, it means FIFO length is 64 bytes.
For FIFO extension mode, FEP’s value shall be set larger than 0x3F.
Please refer to section 16.4.2 for details.
9.2.9.14 Code (Address: 08h) Page 14
Address/Name R/W Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
08h
Code
Reset
W
PML2
IDL1
0
0
WS6 WS5 WS4
0
1
0
WS3 WS2 WS1 WS0 MCS WHTS FECS CRCS IDL0 PML1 PML0
1
0
1
0
0
0
0
0
1
0
PML [2:0] (bit 15 / 1 / 0): Preamble Length Select. Recommend PML= [011].
[000]: 1 byte. [001]: 2 bytes. [010]: 3 bytes. [011]: 4 bytes.
[100]: 16 byte. [101]: 32 bytes. [110]: 48 bytes. [111]: 64 bytes.
IDL[1:0] (bit 14 / 2): ID code length setting. Recommend IDL=[01].
IDL [1:0] = [Bit14, Bit2].
[00]: 2 bytes. [01]: 4 bytes. [10]: 6 bytes. [11]: 8 bytes.
WS [6:0]: Data Whitening Seed (data encryption key, only for FIFO mode).
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FSK/GFSK Sub 1GHz Transceiver
MCS: Manchester Code Enable. (only for FIFO mode)
[0]: Disable. [1]: Enable.
WHTS: Data Whitening. (Data Encryption, only for FIFO mode)
[0]: Disable. [1]: Enable (The data is whitened by multiplying with PN7).
FECS: FEC Select. (only for FIFO mode)
[0]: Disable. [1]: Enable (The FEC is (7, 4) Hamming code).
CRCS: CRC Select. (only for FIFO mode)
[0]: Disable. [1]: Enable.
9.2.9.15 WCAL (Address: 08h) Page 15
Address/Name R/W Bit15 Bit14 Bit13 Bit12 Bit11 Bit10
08h
WCAL
Reset
W
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
MRCT5 MRCT4 MRCT3 MRCT2 MRCT1 MRCT0
R
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MVS1
MVS0
MCALS
MAN
ENCAL
NUMH8 NUMH7 NUMH6 NUMH5 NUMH4 NUMH3 NUMH2 NUMH1 NUMH0 ENCAL
0
0
0
0
0
0
0
0
0
0
0
Bit 1
Bit 0
MRCT[5:0]: Manual setting of RC Timer for WOR mode.
MVS[1:0]: WOR Calibration sample clock select based on CKOT.
[00]: 1/2. [01]: 1/4. [10]: 1/8. [11]: 1/16.
MCALS: WOR Calibration select.
[0]: Continuous mode. [1]: Single mode.
MAN: WOR Calibration Manual select.
[0]: Auto
[1]: Manual
ENCAL: WOR Calibration Enable. ENCAL shall be [0] when WOR calibration is finished.
[0]: Disable. [1]: Enable.
ENCAL: WOR Calibration Flag (read only).
NUMLH[8:0]: WOR Calibration result. (Read only.)
9.2.10.0 TX II (Address: 09h) Page 0
Address/Name R/W Bit15
09h
TX II
W
R
Reset
Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9
MCNTR DPR2 DPR1 DPR0
DID15
0
Bit 5
Bit 4
Bit 3
Bit 2
TDL0
TXDI PAC1 PAC0 TDC1 TDC0 TBG2 TBG1 TBG0
DID14 DID13 DID12 DID11 DID10 DID9
DID8
DID7
DID6
DID5
DID4
DID3
DID2
DID1
DID0
0
0
0
1
1
0
1
1
1
0
0
0
BT0
Bit 6
TDL1
0
BT1
Bit 8 Bit 7
0
0
MCNTR: Divided by 2 select.
[0]: PF8M = f MCNT ¸ 2 where PF8M is one of baseband clock sources.
[1]:
PF8M
where f MCNT
f MCNT
= f MSCK ¸ ( MCNT [1 : 0]) , located in 0x08 page 8.
=
Please refer to Chapter 12 for details.
DPR [2:0]: Scaling of PDL and TDL. Recommend DPR = [000].
BT [1:0]: Moving average for Gaussian filter select.
If GS = [0],
Gaussian filter is disabled, BT = [00]: not average. [01]: 2 bit average. [10]: 4 bit average. [11]: 8 bit average
That means BT is used to smooth TX data transition.
If GS = [1],
Gaussian filter is enabled, BT = [00]: 2.0. [01]: 1.0. [10]: 0.5. [11]: 0.5
That means BT is used to configure shape of Gaussian filter.
TDL[1:0]:TX Settling Delay select.
TDL [1:0]
TX Delay Timer
00
20 us
01
40 us
10
60 us
11
80 us
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FSK/GFSK Sub 1GHz Transceiver
TXDI: TX data inverted. Recommend TXDI = [0].
[0]: normal. [1]: invert
PAC[1:0]: PA current setting.
Please refer to Chapter 8 and A7129 App. Note for programmable TX output power.
TDC[1:0]: TX Driver current setting.
Please refer to Chapter 8 and A7129 App. Note for programmable TX output power.
TBG[2:0]: TX Buffer Gain setting.
Please refer to Chapter 8 and A7129 App. Note for programmable TX output power.
DID [15:0]: Device ID data. (Read Only).
9.2.10.1 IFI (Address: 09h) Page1
Address/Name R/W Bit15
09h
IFI
W
AIF
Reset
0
Bit14
Bit13
Bit12
Bit11
Bit10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IFOA14 IFOA13 IFOA12 IFOA11 IFOA10 IFOA9 IFOA8 IFOA7 IFOA6 IFOA5 IFOA4 IFOA3 IFOA2 IFOA1 IFOA0
0
0
0
0
0
0
0
0
0
0
Bit10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
0
0
0
0
0
Bit 2
Bit 1
Bit 0
AIF: Auto IF enable.
[0]: disable. [1]: enable.
IFOA[14:0]: Auto IF offset frequency setting.
9.2.10.2 IFII (Address: 09h) Page2
Address/Name R/W
09h
IF II
W
Bit15
Bit14
Bit13
Bit12
Bit11
Bit 4
Bit 3
FPA15 FPA14 FPA13 FPA12 FPA11 FPA10 FPA9 FPA8 FPA7 FPA6 FPA5 FPA4 FPA3 FPA2 FPA1 FPA0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FPA[15:0]: LO setting for frequency offset.
f OFFSET = f PFD × (
FPA[15 : 0] × 2 6
)
216
(unit: Hz)
Where FPFD = Fxtal / (RFC[3:0]+1)
From PLL II (02h), f LO_BASE = f PFD × ( IP[8 : 0] +
FP[15 : 0]
)
216
(unit: Hz)
Therefore, VLO frequency FLO = FRF = FLO_BASE + FOFFSET.
Please refer to Ch13 for details.
9.2.10.3 ACK (Address: 09h) Page3
Address/Name R/W Bit15
09h
TX II
Reset
W
Bit14
Bit13
Bit12
Bit11
Bit10
Bit 9
Bit 8 Bit 7 Bit 6
MRCKS RNUM3 RNUM2 RNUM1 RNUM0 CDRS1 CDRS0 SYNCS VKM
R
Bit 5
Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
VPM ARTMS ARC3 ARC2 ARC1 ARC0 EARKS
ARTEF VPOAK RCR3 RCR2 RCR1 RCR0 EARKS
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
MRCKS: Reserved for internal usage only. Shall be set to [0].
RNUM[3:0]:Reserved for internal usage only. Shall be set to [011]..
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FSK/GFSK Sub 1GHz Transceiver
SYNCS: RX demodulation sync word detect type select.
[0]: Sync word detect by re-preamble.
[1]: Sync word detect by using 64bytes buffer.
CDRS[1:0]: Carrier detect range select. Recommend CDRS = [01].
[00]: 8. [01]: 16. [10]: 24. [11]:32 .
VKM: Valid Packet mode select.
[0]: by event. [1]: by pulse.
VPM: Valid Pulse width select.
[0]: 10u. [1]: 30u.
TX Mode (disable auto-resend, EARKS=0).
RX Mode (disable Auto-ack, EAKKS =0).
Note1, If auto-resend is enabled (EAR = 1), WTR behavior is different while it is output to GIO1 and GIO2.
Note2, If auto-ack is enabled (EAK = 1), WTR behavior is different while it is output to GIO1 and GIO2.
Note3, VPOAK’s behavior is controlled by VPM (0Bh) and VPW (0Bh).
Refer to chapter 19 for details
ARTMS: Auto-resend Interval select.
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[0]: random interval. [1]: fixed interval.
ARC [3:0] : Auto-resend Cycle Setting.
[0000]: resend disable.
[0001]: 1 [0010]: 2 [0011]: 3 [0100]: 4 [0101]: 5 [0110]: 6 [0111]: 7
[1000]: 8 [1001]: 9 [1010]: 10 [1011]: 11 [1100]: 12 [1101]: 13 [1110]: 14 [1111]: 15
EARKS: Auto-ack or auto-resend enable.
[0]: disable. [1]: enable auto-resend (TX) or enable auto-ack (RX)
ARTEF: Auto-resend ending flag (read only).
[0]: Resend on going. [1]: Finish resending.
VPOAK: Valid Packet or ACK OK Flag (ready only).
This flag is clear by Strobe Command.
[0]: Neither valid packet nor ACK OK.
[1]: Valid packet or ACK OK.
RCR [3:0]: Auto Resend Cycle Decremented Count (read only).
Decremented of ARC[3:0] during auto-resend.
9.2.10.4 ART (Address: 09h) Page4
Address/Name R/W Bit15
09h
TX II
W
Bit14
Bit13
Bit12
Bit11
Bit10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RND07 RND6 RND5 RND4 RND3 RND2 RND1 RND0 ARD7 ARD6 ARD5 ARD4 ARD3 ARD2 ARD1 ARD0
R
Reset
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
Bit 3
Bit 2
Bit 1
Bit 0
ETH2 DMT MPL1 MPL0 SLF2 SLF1 SLF0 ETH1 ETH0 DMOS DMG1 DMG0 IFBW1 IFBW0 ULS
RXDI
RND [7:0]: Random seed for auto-resend interval.
ARD[7:0] : Auto Resend Delay
ARD Delay = 200 us * (ARD+1) à (200us ~ 51.2 ms)
Each step is 200 us.
[0000-0000]: 200 us.
[0000-0001]: 400 us.
[0000-0010]: 600 us.
…
…
[1111-1111]: 51.2 ms.
9.2.11 RX I (Address: 0Ah)
Address/Name R/W Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9 Bit 8 Bit 7 Bit 6
0Ah
RX I
Reset
W
0
0
0
1
1
0
0
0
1
0
Bit 5
0
Bit 4
1
0
0
0
ETH [2:0] (bit 15/8/7): ID code error bit tolerance. Recommend ETH = [001].
ETH [2:0] is located in [Bit15, Bit8, Bit7]
[000]: 0 bit. [001]: 1bit. [010]: 2 bits. [011]: 3 bits. [100]: 4 bits. [101]: 5 bits. [110]: 6 bits. [111]: 7 bits.
DMT : Demodulator test bit. DMT shall be [0].
[0]: Normal.
[1]: Test mode.
MPL [1:0]: Symbol recovery loop filter setting after ID SYNC. MPL shall be [01].
SLF [2:0]: Symbol recovery loop filter setting. SLF shall be [100].
DMOS: Demodulator over-sample select. Recommend DMOS = [1].
[0]: x16.
[1]: x32.
DMG [1:0]: Demodulator Gain select. Recommend DMG = [01].
[00]: x1. [01]: x3. [1x]: x5.
IFBW [1:0]: IF Band Pass Filter select.
[00]: 50KHz.
data rate ≦50Kbps. (Xtal shall be chosen ± 10 ppm stability in case of RX sensitivity degradation.)
[01]: 100KHz.
50K < data rate ≦100Kbps.
[10]: 150KHz.
100K < data rate ≦150Kbps.
[11]: 250KHz.
150K < data rate ≦250Kbps.
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A7129
FSK/GFSK Sub 1GHz Transceiver
Since A7129 is a low-IF TRX, on-chip IFBW is implemented with 4 optional Filter Bandwidth.
The IF Filter shall be calibrated after power on reset. In performance point of view, the narrower IFBW results the better
RX sensitivity. To make a successful IFBW calibration, an appreciated setting of calibration clock is necessary.
Please refer to Chapter 12 and A7129’s reference code for details.
ULS: RX Up/Low side band select. Recommend ULS = [0].
[0]: Up side band, TX A-terminal frequency – IF = RX B-terminal frequency
[1]: Low side band, TX A-terminal frequency + IF = RX B-terminal frequency
RXDI: RX Data Invert. Recommend RXDI = [0].
[0]: normal. [1]: inverted.
9.2.12 RX II (Address: 0Bh)
Address/Name R/W Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9 Bit 8
0Bh
RX II
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
PMD2 PMD1 PMD0 DCV7 DCV6 DCV5 DCV4 DCV3 DCV2 DCV1 DCV0 DCL2 DCL1 DCL0 DCM1 DCM0
R
ADCO ADCO ADCO ADCO ADCO ADCO ADCO ADCO ADCO
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PMD[2:0]: Preamble pattern detection. Recommend PMD = [100].
When DCM[1:0] = 01, 10, 11, chip will execute preamble length detection automatically.
[000]: 0 bit
[001]: 4 bits
[010]: 8 bits (Default value)
[011]: 16 bits
[100]: 24 bits.
[101] and [11x]: 32bits.
Remark: detection length setting should be smaller than the setting value of PML[1:0](08h, Page 14).
DCV[7:0]: Data DC average value setting. Recommend DCV = [10010].
This setting is only active when DCM (09h) = [00].
DCL[2:0]: Data Length of Peak Detect average setting. Recommend DCL = [010].
DCL[2:0] is used to let A7129 detects n times “0” or n times ”1” to result DC estimation voltage of demodulator.
DC average
DCL[2:0]
Before ID Sync
After ID Sync
000
4
32
001
8
32
010
16
32
011
32
32
100
4
64
101
8
64
110
16
64
111
32
64
For example, if DCL[2:0] = 000,
Before ID sync, by peak detect method to update a new DC value for every 4 times 1” and 4 times ”0” .
After ID sync, by peak detect method, to update a new DC value for every 32 times “1” and 32 times ”0” .
DCM [1:0]: Demodulator DC estimation mode. Recommend DCM = [01].
[00]: By DC average value, DCV[7:0],(0Bh).
[01]: DC holds after preamble detected.
[10]: DC holds after ID detected.
[11]: DC value when chip receive specific data length (set by DCL[:2:0])..
ADCO[8:0]: RSSI value if AGC =1 (Read Only).
9.2.13 ADC (Address: 0Ch)
Address/Name R/W Bit15 Bit14
0Ch
ADC
Reset
W
R
Bit13
Bit12
Bit11
Bit10
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ARSSI RADC AVSEL1 AVSEL0 MVSEL1 MVSEL0 XADS CDM RTH7 RTH6 RTH5 RTH4 RTH3 RTH2 RTH1 RTH0
PWR XEM PLLEM TRSM TREM
VBD1 VBD0 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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FSK/GFSK Sub 1GHz Transceiver
ARSSI: Auto RSSI measurement enable.
[0]: Disable. [1]: Enable.
ARSSI shall be [1] for auto RSSI measurement before MCU issues RX strobe command.
RADC: ADC Read Out Average Mode.
[0]: 1, 2, 4, 8 average mode. If RADC = 0, ADC average is set by AVSEL[1:0] (0Ch).
[1]: 8, 16, 32, 64 average mode. If RADC = 1, ADC average is set by MVSEL[1:0] (0Ch).
AVSEL [1:0]: ADC average mode. Recommend AVSEL = [10].
[00]: No average. [01]: 2. [10]: 4. [11]: 8.
MVSEL [1:0]: ADC average mode for VCO calibration and RSSI. Recommend MVSEL = [10].
[00]: 8. [01]: 16. [10]: 32. [11]: 64.
XADS: ADC input signal source select.
[0]: Internal temperature sensor or RSSI signal.
[1]: External signal source.
CDM: Carrier Detect enable
[0]: RSSI/Temperature measurement.
[1]: Carrier detect
RTH[7:0]: Threshold value of Carrier Detect (Active in RX mode only).
CD (Carrier Detect) =1 when RSSI ≧ RTH.
CD (Carrier Detect) =0 when RSSI < RTL.
PWR: Power Status (Read Only).
[0]: Power off. [1]: Power on.
XEM: Crystal Status (Read Only).
[0]: Disable. [1]: Enable.
PLLER: PLL Status (Read Only).
[0]: Disable. [1]: Enable.
TRSM: TRX Mode Status (Read Only).
[0]: RX mode. [1]: TX mode.
TREM: TRX Status (Read Only).
[0]: Disable. [1]: Enable.
VBD[1:0]: VCO bias detect (Read Only).
ADC[7:0]: ADC value (Read Only).
9.2.14 Pin Control (Address: 0Dh)
Address/Name R/W Bit15 Bit14 Bit13 Bit12
0Dh
Pin control
Reset
W
Bit11
Bit10 Bit 9
Bit 8 Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CKO0 CKOE
SCKI
RFT2
RFT1
RFT0
PRS
SCMDS
WMO
DE
INFS
IRQI
IRQ1
IRQ0
IRQE
CKOI
CKO1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
RFT [2:0]: RF Analog Pin Configuration. Recommend RFT= [000].
{XADS, RFT[2:0]}
BP_BG (Pin 30)
RSSI (Pin 1)
[0000]
Band-gap voltage
RSSI voltage
[0001]
Analog temperature voltage
RSSI voltage
[0010]
Band-gap voltage
No connection
[0011]
Analog temperature voltage
No connection
[0100]
BPF positive in phase output
BPF negative in phase output
[0101]
BPF positive quadrature phase output
BPF negative quadrature phase output
[0110]
RSSI voltage
No connection
[0111]
RSSI voltage
No connection
[1000]
Band-gap voltage
External ADC input source
[1001]
Analog temperature voltage
External ADC input source
[1010]
Band-gap voltage
External ADC input source
[1011]
Analog temperature voltage
External ADC input source
[1100]
No connection
External ADC input source
[1101]
No connection
External ADC input source
[1110]
No connection
External ADC input source
[1111]
No connection
External ADC input source
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A7129
FSK/GFSK Sub 1GHz Transceiver
PRS: Read frequency mode for AFC=1. Recommend PRS= [0].
[0]: no frequency compensation.
[1]: frequency offset in AFC mode
SCMDS: Strobe Command select. Recommend SCMDS= [1].
[0]: register control. [1]: strobe control.
WMODE: WOT or WOR select for WORE=1.
[1]: WOT (Wake-on-TX).
[0]: WOR (Wake-on-RX).
INFS: Infinite FIFO length select.
[0]: fixed length. [1]: infinite length
IRQI: Reserved. IRQI shall be [0].
IRQ[1:0]: Reserved. Use GIO1S/ GIO2S instead. Shall be [00].
IRQE: Reserved. Use G1OE/ G2OE instead. Shall be [0].
CKOI: Reserved. Use 08h page 9 instead. Shall be [0].
CKO[1:0]: Reserved. Use 08h page 9 CKOS instead. Shall be [00].
CKOE: Reserved. Use 08h page 9 instead. Shall be [0].
SCKI: SPI Clock Inverted. Recommend SCKI= [0].
[0]: Normal. [1]: Inverted.
9.2.15 Calibration (Address: 0Eh)
Address/Name R/W Bit15
0Eh
Calibration
Reset
W
R
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 Bit 1
Bit 0
MSCRC
Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9
VTL2
VTL1
VTL0
VTH2
VTH1
VTH0 MVBS MVB2 MVB1
Bit 8
Bit 7
MVB0
MIFS
MIF3
MIF2
MIF1
MIF0
FCD4
FCD3
FCD2
FCD1
FCD0
DVT1
DVT0
VBCF
VB2
VB1
VB0
FBCF
FB3
FB2
FB1
FB0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
MSCRC: CRC Filtering Enable. Recommend MSCRC = [1].
[0]: Disable. [1]: Enable.
VTL[2:0]: VT low threshold setting for VCO calibration. Recommend VTL = [100].
[000]: VTL=0.1V. [001]: VTL=0.2V. [010]: VTL=0.3V. [011]: VTL=0.4V. [100]: VTL=0.5V. [101]: VTL=0.6V.
[110]: VTL=0.7V. [111]: VTL=0.8V.
VTH[2:0]: VT high threshold setting for VCO calibration. Recommend VTH = [111].
[000]: VTH=Vdd-0.1V. [001]: VTH=Vdd-0.2V. [010]: VTH=Vdd-0.3V. [011]: VTH=Vdd-0.4V. [100]: VTH=Vdd-0.5V.
[101]: VTH=Vdd-0.6V. [110]: VTH=Vdd-0.7V. [111]: VTH=Vdd-0.8V.
MVBS: VCO band calibration select.
[0]: Auto. [1]: Manual.
MVB[2:0]: VCO bank manual setting. VCO frequency increases when MVB decreases.
MIFS: IF Filter Calibration Select.
[0]: Auto. [1]: Manual.
MIF[3:0]: IF filter Manual Setting.
FCD [4:0]: IF Filter Auto Calibration Deviation from Goal (read only).
DVT[1:0]: VT output (Read Only).
[00]: VT< VTL< VTH.
[01]: VTL< VT< VTH.
[10]: No used.
[11]: VTL< VTH< VT.
VBCF: VCO Band Auto Calibration Flag (Read Only).
[0]: Pass. [1]: Fail.
VB[2:0]: VCO Bank Auto Calibration Result (Read Only).
FBCF: IF Filter Auto Calibration Flag (Read Only).
[0]: Pass. [1]: Fail.
FB[3:0]: IF Filter Auto Calibration Result (Read Only).
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FSK/GFSK Sub 1GHz Transceiver
9.2.16 Mode control (Address: 0Fh)
Address/Name R/W Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9
0Fh
Mode control
Reset
W
R
Bit 8
Bit 7
Bit 6
Bit 5
DFCD VBS SWT RSSC VCC CCE WORE FMT
--- WORE RSSC CCER FECF CRCF FMT
0
0
0
0
0
0
0
0
FMS
FMS
0
CER
CER
0
PLLE TRSR TRER VBC
PLLE TRSR TRER VBC
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
DFCD: Packet Filtering by Carrier Detect.
The received packet is filtered if the input power level is below RTH (0Ah).
[0]: Disable. [1]: Enable.
VBS: Reserved. Should set to [0].
SWT: VCO Current and ADC clock and System clock select. Recommend SWT = [0].
[0]: Original
[1]: Update
RSSC: RSSI Calibration.
[0]: Disable. [1]: Enable.
VCC: VCO current calibration
[0]: Disable
[1]: Enable
CCE: Chip enable by register.
[0]: chip turn-off. [1]: chip turn-on.
WORE: WOR or WOT function enable.
[0]: Disable. [1]: Enable.
FMT: Reserved for internal usage only. Shall be set to [0].
FMS: Direct/FIFO mode select.
[0]: Direct mode. [1]: FIFO mode.
CER: Crystal enable by register.
[0]: crystal turn-off. [1]: crystal turn-on.
PLLE: PLL enable by register.
[0]: PLL off. [1]: PLL on.
TRSR: TRX Mode select by register.
[0]: RX mode. [1]: TX mode.
When bit TRER=1, the chip will enter TX or RX mode by TRSR register.
TRER: TRX mode enable by register. Shall be set to [1].
[0]: Reserved.
[1]: By register control (CER and TRSR). In FIFO mode, this bit will be cleared after end of packet encountered.
VBC: VCO Bank calibration enable (Auto clear when done).
[0]: Disable. [1]: Enable.
FBC: IF Filter Bank calibration enable (Auto clear when done).
[0]: Disable . [1]: Enable.
ADCM: ADC measurement (Auto clear when done).
[0]: Disable. [1]: Enable.
Non-Rx mode
[0] None
[1] Temperature measurement (XADS=0) or
external analog signal conversion from pin 1 (XADS=1)
RX mode
None
RSSI, carrier detect
FECF: FEC flag. (Bit 10, FECF is read clear.)
[0]: FEC pass. [1]: FEC error.
CRCF: CRC flag. (Bit 9, CRCF is read clear.)
[0]: CRC pass. [1]: CRC error.
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FBC ADCM
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
10. SPI (3-wire)
The A7129 communicates with a host MCU via 3-wire SPI interface (SCS, SCK, SDIO) or 4-wire SPI (SDO from GIO1
or GIO2) with a max data rate 10Mbps. A SPI transition is a 24-bits sequence which consists of an 8-bits address and a
16-bits data word. The MCU should set SCS (SPI chip select) pin low in order to access A7129. Via the SPI interface,
user can access the control registers and issue Strobe commands. The SPI data will be latched into the registers at
the rising edge of SCK. When reading registers from the RF chip, after input the wanted register address, the bit data
will be transferred from the falling edge of SCK.
10.1 SPI Format
Address Byte (8 bits):
Bit A7: R/W bit
[0]: Write.
[1]: Read.
Bit A6~A4: Command
[00x]: read/write control register.
[01x]: read/write ID code.
[10x]: read/write FIFO register.
[110]: reset TX/RX FIFO pointer.
[111]: RF chip Reset (soft reset and all registers will be clean to initial value).
Bit A3~A0: Address of control register
Strobe Command table:
Address Byte (8 bits)
A7 A6 A5 A4 A3 A2 A1 A0
0
1
0
0
0
0
0
X
A3
A3
A2
A2
A1
A1
A0
A0
0
0
1
X
X
X
X
X
1
0
1
X
X
X
X
X
0
1
0
X
X
X
X
X
1
1
0
X
X
X
X
X
X
1
1
1
X
X
X
X
0
1
1
0
X
X
X
X
1
1
1
0
X
X
X
X
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
1
description
Write control register
Read control register
Write ID code command
Read ID code command
TX FIFO write command
RX FIFO read command
Software Reset command
TX FIFO address pointer reset command
RX FIFO address pointer reset command
Sleep mode
Idle mode
Standby mode
PLL mode
RX mode
TX mode
Deep sleep mode (tri-state)
Deep sleep mode (pull-high)
Remark: X (Don’t care).
Data Words (16-bits) : On-chip registers in sequence of D15~D0.
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FSK/GFSK Sub 1GHz Transceiver
10.2 SPI Timing Chart
SCS
SCK
SDIO
A7
A6
A5
A4
A3
A2
A1
A0
DW15
RF IC will latch address bit
at the rising edge of SCK
DW14
DW13
D W2
DW1
DW0
DR2
DR1
DR0
RF IC will latch data at
the rising edge of SCK
3-Wire serial interface - Write operation
SCS
SCK
SDIO
A7
A6
A5
A4
A3
RF IC will latch address at
the rising edge of SCK
A2
A1
A0
DR15
DR14
DR13
MCU can latch data at the
risinfg edge of SCK
RF IC wiill change the
data at the falling edge
of SCK
3-Wire serial interface - Read operation
Figure 10.1. SPI read/write sequence
10.3 Control register access
Figure 10.2. Access type of control register
10.4 SPI Timing Specification
SCS
T SE
TFC
THE
SCK
TSW
SDIO(Write)
THW
A7
A0
D15
D0
D15
D0
TDR
SDIO(Read)
A0
Figure 10.3 SPI timing sequence
Parameter
TFC
TSE
Description
Clock frequency.
SCS setup time.
Oct., 2012, Version 0.4 (PRELIMINARY)
Min.
50
33
Max.
10
Unit
MHz
ns
AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
THE
TSW
THW
TDR
THR
SCS hold time.
SDIO setup time.
SDIO hold time.
SDIO delay time.
SDIO hold time.
50
50
50
0
0
100
ns
ns
ns
ns
ns
10.5 Reset Command
The MCU could issue a software reset command to A7129 by sending a Reset Command through the SPI interface as
shown below. After a reset command, A7129 is in standby mode.
Figure 10.5 Reset Command
10.6 Reset TX FIFO Pointer
The SPI timing sequences for resetting TX FIFO Pointer is shown below. The address pointer of TX FIFO is reset to
0x00 at the rising edge of SCK at bit A0.
Figure 10.6 TX FIFO Pointer Reset
10.7 Reset Rx FIFO Pointer
The SPI timing sequences for resetting RX FIFO Pointer is shown below. The address pointer of RX FIFO is reset to
0x00 at the rising edge of SCK at bit A0.
Figure 10.7 RX FIFO Pointer Reset
10.8 ID Read/Write Command
A7129 has built-in 32-bits ID Registers for customized identification code. It is accessed via SPI interface. ID length is
recommended to be 32 bits by setting IDL. The timing sequences are shown below. First execute the ID Red/write
command in address byte, and then write data bytes with length of the 4 bytes.
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FSK/GFSK Sub 1GHz Transceiver
Figure 10.8 ID Write Command
Figure 10.9 ID Read Command
10.9 FIFO R/W Command
TX FIFO Write Command
To execute the TX FIFO write procedure, according to the command table, user should write the corresponding
command into Address Byte, and then write data into the Data Bytes. After completing the writing action, toggle SCS=1
to end the TX FIFO writing procedure.
Figure 10.10 TX FIFO Write Command
RX FIFO Write Command
To execute the RX FIFO read procedure, according to the command table, user should write the corresponding
command into Address Byte, and then read out RX FIFO. After completing the reading action, toggle SCS=1 to end the
RX FIFO writing procedure.
Figure 10.11 RX FIFO Read Command
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FSK/GFSK Sub 1GHz Transceiver
11. Crystal Oscillator
A7129 needs external crystal or external clock to generate internal wanted clock.
Relative Control Register / Crystal (Address: 07h)
Address/Name R/W Bit15
07h
Crystal
Reset
W
Bit14
Bit13
Bit12
Bit11
Bit10
Bit 9
Bit 8
PGAS3 PGAS2 PGAS1 PGAS0 CRCDNP CRCINV PGBS2 PGBS1 PGBS0
0
0
0
0
0
0
0
Bit
0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
0
0
-
-
0
0
XCC XCP1 XCP0 CGS XS
1
1
0
0
0
11.1 Use External Crystal
Figure 12.1 shows the connection of crystal network between XI and XO pins. C1 and C2 capacitance built inside A7129
are used to adjust different crystal loading. User can set INTXC [4:0] (08h, page 9) to meet crystal loading requirement.
A7129 supports low cost crystal within ± 30 ppm accuracy. Be aware that crystal accuracy requirement includes initial
tolerance, temperature drift, aging and crystal loading.
CKO (Address: 08h) Page 9
Address/Name R/W Bit15 Bit14
08h
CKO
Reset
W
INTXC XCL4
0
Bit13
Bit12 Bit11 Bit10
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XCL3
XCL2 XCL1 XCL0 WSEL2 WSEL1 WSEL0 CKS3
CKS2
CKS1
CKS0
CKOI
CKOE
SCT
0
0
0
0
0
0
1
0
0
0
0
Bit 9
0
Bit 8
1
Bit 7
0
0
Note: set XS= 1 (07h) and INTXC(08h, page 9) to enable external crystal oscillator and on-chip crystal compensated
capacitors.
Figure11.1 Crystal network connection for using external crystal
11.2 Use External Clock
A7129 has built-in AC couple capacitor to support external clock input. Figure 11.2 shows how to connect. In such case,
XI pin is left opened.
Note: set XS = 0 (07h) to select external clock (AC couple capacitor active.). And the frequency accuracy of external
clock shall be controlled within ± 30 ppm and the clock swing (peak-to-peak) shall be larger than 1.0V.
External clock is controlled within ± 30ppm and Vpp is above 1.0V.
Figure 11.2 Connect to external clock source
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FSK/GFSK Sub 1GHz Transceiver
12. System Clock
A7129’s main system clock, FMSCK, can be either come from Xtal oscillator itself or from the internal PLL clock generator.
The purpose of the internal clock generator is used to support multi Xtal frequency and/or special requirements of the
wanted data rate.
12.1 Clock Domain
Since FMSCK is the root of the data rate clock, IF Filter calibration clock, as well as baseband clock, therefore, there are
several clock dividers implemented by configurable registers such as CSC, SDR, DMOS, MCNT and MCNTR. Table
12.1 lists the most important constraints how to configure those registers successfully and figure 12.1 illustrates the
detailed clock domain.
Signal
FMSCK (main system clk)
DCK (data rate clock)
Constraints
If CGS = 0, FMSCK = Xtal freq.
If CGS = 1, FMSCK = Clk Gen
DCK =
f CSCK
1
×
64 SDR[6 : 0] + 1
Note
If using Clk Gen, FMSCK range can be from 20M
~ 50MHz that depends on GRC and GRS.
DCK = the wanted data rate
Demodulator Oversample
FMSCK = FIFREF x (32)
Use 32 oversample by set DMOS = 1
IFBW calibration
FIFREF = IF Filter BW x (2)
FIFREF is derived from FMSCK
PF8M
equal or close to 6.4MHz
Set WRCKS = 0 for successful WOR calibration
equal or close to 8MHz
Set WRCKS = 1 for successful WOR calibration
Table 12.1 Constraints of the key signals and its usage.
Figure 12.1 Illustrations from Xtal oscillator to main system clock and its clock domain.
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FSK/GFSK Sub 1GHz Transceiver
12.2 System Clock and IF Filter
In general, data rate is almost the first consideration to start a new design. While choosing a wanted data rate, A7129
offers 4 optional IFBW (50KHz / 100KHz / 150KHz / 250KHz) to trade off RX sensitivity and frequency tolerance.
Table 12.2 lists the recommended IFBW vs data rate. For example, 10Kbps data rate is mapping to 50KHz IFBW. In this
case, using ± 10 ppm Xtal is necessary this is because the narrower IFBW the poorer frequency tolerance, but, the
better RX sensitivity. However, user can also choose 100KHz IFBW to handle a larger frequency tolerance in a RF
system. That means using a larger Xtal tolerance is ok, i.e. ± 20 ppm. But, its disadvantage is to suffer RX sensitivity.
Data rate
2K ~ 50kbps
≦100kbps
≦150kbps
≦250kbps
IFBW
~ 50kHz
~ 100kHz
~ 150kHz
~ 250kHz
FIFREF
~ 50kHz x 2
~ 100kHz x2
~ 150kHz x2
~ 250kHz x2
Constraints
The actual FIFREF ,which is derived
from system clock, is double of
IFBW
Table 12.2 General case of IFBW mapping to Data Rate.
12.3 Example of 10Kbps data rate by 12.8MHz Xtal
Since IFBW is so important to impact RX sensitivity, A7129 has an IFBW calibration procedure to overcome the process
deviation of semiconductor. To make a successful IFBW calibration, the relationships among FMSCK, FIFREF and DCK
must be satisfied. Figure 12.2 illustrates the detailed configurations to clock dividers.
1.
2.
3.
4.
Data rate = 10Kbps
Xtal = 12.8MHz
Clk Gen = disable
IFBW[1:0] = [00], targeted BW = 50KHz
Figure 12.2 Configurations of 10Kbps when IFBW = 50KHz
5.
6.
7.
8.
9.
If choosing IFBW = 100KHz, figure 12.3 illustrates the different results of CSC and FCSCK.
Data rate = 10Kbps
Xtal = 12.8MHz
Clk Gen = disable
IFBW[1:0] = [01], targeted BW = 100KHz
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FSK/GFSK Sub 1GHz Transceiver
Figure 12.3 Configurations of 10Kbps when IFBW = 100KHz
12.4 Example of special data rate by 19.6608MHz Xtal.
A7129 can support most general data rate such as 10K, 50K, 100K, 150K, 250Kbps. For special data rate such as
38.4Kbps, the internal Clk Gen can be enabled with a special Xtal frequency to get the wanted DCK and IFBW. Figure
12.4 illustrates the detailed configurations to clock dividers.
1.
2.
3.
4.
Data rate = 38.4Kbps
Xtal = 19.6608MHz
Clk Gen = disable
IFBW[1:0]= [10] , targeted BW = 150KHz
Figure 12.4 Configurations of 38.4Kbps when IFBW = 153.6KHz
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FSK/GFSK Sub 1GHz Transceiver
5. If choosing IFBW = [11]. IFBW will become 307.2KHz instead of the expected 250KHz because of FIFREF
(higher FIFREF results larger IF bandwidth if IF Filter Calibration is successful.). Figure 12.5 illustrates the
different results of CSC and FCSCK.
6. Data rate = 38.4Kbps
7. Xtal = 19.6608MHz
8. Clk Gen = enable
9. IFBW = 307.2KHz
Figure 12.5Configurations of 38.4Kbps when IFBW = 307.2KHz
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FSK/GFSK Sub 1GHz Transceiver
13. Tranceiver Frequency
A7129 is a half-duplex transceiver with embedded PA and LNA. For TX or RX frequency setting, user just needs to set
up LO (Local Oscillator) frequency for two ways radio transmission.
To target full range of Sub 1GHz ISM band (315/433/470/868/915MHz band), A7129 applies offset concept by LO
frequency FLO = FLO_BASE + FOFFSET. Therefore, this device is easy to implement single channel operation or frequency
hopping (multi-channels) by setting, IF Register II (FPA [15:0]).
Below is the frequency synthesizer block diagram which shows that VCO frequency (FVCO) is operated at the wanted RF
frequency (FRF).
F PFD
F XTA L
/ (RFC[3:0]+1)
(MC[14:0]/ 2 16)
VCO
PFD
F VC O
F RF
Divider
If AFC = 1
F LO _B ASE
IP[8:0] +
FP[15:0]/ 2 16
+
FPA [15:0]
+
F LO
F OFFSET
Figure 13.1 Frequency synthesizer block diagram
FRF = FVCO = FLO_BASE + FOFFSET (unit: Hz)
where
f RF , the wanted RF frequency, is equal to VCO frequency.
f LO_BASE , the base frequency of LO frequency.
where
f OFFSET , the offset frequency of LO frequency.
where
Example:
How to get (FRF) = 433.921MHz by a 12.8MHz Xtal.
1.
2.
3.
4.
5.
Set
Set
Set
Set
Set
AFC = 0 to disable AFC function.
RFC (06h) = [000], (FPFD) = Xtal frequency = 12.8MHz.
MD1 (04h) = [0] for 433MHz band.
IP [7:0] (01h) for integer part. Set IP[8:0] = 33 = 0x021
FP [15:0] (02h) for fractional part. Set FP[15:0] = 58987 = 0xE66B
6.
f LO_BASE = f PFD × ( IP[8 : 0] +
7.
8.
FP[15 : 0]
58987
) = 12.8 ´ (33 + 16 )
16
2
2
= 433.921 (MHz)
Set FPA [15:0] (09h, page 2) for offset part. Set FPA = 0x0000 for zero offset.
f OFFSET
FPA[15 : 0] × 2 6
= f PFD × (
)
216
=
12.8 ´
0
210
= 0 (MHz)
9.
For TX radio frequency (FTXRF) is equal to FRF = FVCO = FLO_BASE + FOFFSET = 433.921 + 0 = 433.921 (MHz).
10.
.
RX LO frequency (FRXLO) is shall be set to ONE FIF offset because low-IF architecture.
RX LO frequency FRXLO = FTXRF － FIFREF ; when ULS (0Ah) = 0 for up side band.
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FSK/GFSK Sub 1GHz Transceiver
14. State machine
A7129 has seven major operation modes from current consumption point of view as shown in Table 14.1. From
accessing data point of view, if FMS=1 (0Fh), FIFO mode is enabled, otherwise, A7129 is in direct mode.
14.1 Key Strobe Commands
A7129 has below 7 operation modes in current consumption point of view. Those are,
(1) Deep Sleep mode
(2) Sleep mode
(3) Idle mode
(4) Standby mode
(5) PLL mode
(6) TX mode
(7) RX mode
After power on reset or software reset or deep sleep mode, user has to do calibration process because all control
registers are in initial values. The calibration process of A7129 is very easy, user only needs to issue Strobe commands
and enable calibration registers. If so, the calibrations are automatically completed by A7129’s internal state machine.
Table 14.1 shows a summary of key circuitry among those strobe commands.
Register
retention
Mode
Deep Sleep
(Tri-state)
Deep Sleep
(pull-high)
Sleep
Idle
Regulator Xtal Osc.
VCO
PLL
RX
TX
Strobe Command
No
OFF
OFF
OFF
OFF
OFF
OFF
(1101-0000)b
No
OFF
OFF
OFF
OFF
OFF
OFF
(1111-0011)b
Yes
OFF
OFF
OFF
OFF
OFF
OFF
(0000-xxxx)b
Yes
ON
OFF
OFF
OFF
OFF
OFF
(0001-xxxx)b
Standby
Yes
ON
ON
OFF
OFF
OFF
OFF
(0010-xxxx)b
PLL
Yes
ON
ON
ON
ON
OFF
OFF
(0011-xxxx)b
TX
Yes
ON
ON
ON
ON
OFF
ON
(0101-xxxx)b
RX
Yes
ON
ON
ON
ON
ON
OFF
(0100-xxxx)b
SW RST
(x111-xxxx)b
Remark: x means “don’t care”
Table 14.1. Operation mode and strobe command
14.2 FIFO mode
This mode is suitable for the requirements of general purpose applications and can be chosen by setting FMS = 1. After
calibration, user can issue Strobe command to enter standby mode where write TX FIFO or read RX FIFO. From
standby mode to packet data transmission, only one Strobe command is needed. Once transmission is done, A7129 is
auto back to standby mode. Figure 14.1 and Figure 14.2 are TX and RX timing diagram respectively. Figure 14.3
illustrates state diagram of FIFO mode.
Strobe CMD
(SCS,SCK,SDIO)
Standby
TX
Next Instruction
Strobe
RF settling
(PDL+TDL)
RFO
Pin
Preamble + ID Code + Payload
GIO1 Pin - WTR
(GIO1S[3:0]=0000)
Transmitting Time
T0
T2
T1
Auto Back
Standby Mode
Figure 14.1 TX timing of FIFO Mode
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A7129
FSK/GFSK Sub 1GHz Transceiver
Strobe CMD
Standby
(SCS,SCK,SDIO)
RX
Next Instruction
strobe
Wait
Packet
RX settling
RFI
Pin
Preamble + ID Code + Payload
GIO1 Pin - WTR
(GIO1S[3:0]=0000)
Receiving Time
T0
T1
T3
T2
Auto Back
Standby Mode
Figure 14.2 RX timing of FIFO Mode
Figure 14.3 State diagram of FIFO Mode
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A7129
FSK/GFSK Sub 1GHz Transceiver
14.3 Direct mode
This mode is suitable to let MCU to drive customized packet to A7129 directly by setting FMS = 0. In TX mode, MCU
shall send customized packet in bit sequence (simply called raw TXD) to GIO1 or GIO2 pin. In RX mode, the receiving
raw bit streams (simply called RXD) can be configured output to GIO1 or GIO2 pin. Be aware that a customized packet
shall be preceded by a 32 bits preamble to let A7129 get a suitable DC estimation voltage. After calibration flow, for every
state transition, user has to issue Strobe command to A7129 for fully control. This mode is also suitable for the
requirement of versatile packet format.
Figure 14.4 and Figure 14.5 are TX and RX timing diagram in direct mode respectively. Figure 14.3 illustrates state
diagram of direct mode.
Strobe CMD
(SCS,SCK,SDIO)
RFO
TX
STB strobe
Strobe
RF settling
(PDL+TDL)
GIO1 Pin - WTR
(GIO1S[3:0]=0000)
Modulated signals
Carrier
only
Pin
Manually back
to STB
Preamble + customized raw TXD
Modulation auto enable
GIO1 Pin - TMEO
(GIO1S[3:0]=0010)
32-bits
preamble
GIO2 Pin - TXD
(GIO2S[3:0]=1001)
T1
T0
T4
T3
Figure 14.4 TX timing of Direct Mode
Strobe CMD
(SCS,SCK,SDIO)
RX
STB strobe
Strobe
Wait
packet
RX settling
RFO
Pin
Manually back
to STB
Coming packet
Preamble + customized raw TXD
GIO1 Pin - WTR
(GIO1S[3:0]=0000)
Preamble detect output
GIO1 Pin - PMDO
(GIO1S[3:0]=0011)
GIO2 Pin - RXD
(GIO2S[3:0]=1000)
T0
T1
T4
T3
Figure 14.5 RX timing of Direct Mode
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A7129
FSK/GFSK Sub 1GHz Transceiver
Figure 14.6 State diagram of Direct Mode
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A7129
FSK/GFSK Sub 1GHz Transceiver
15. Calibration
A7129 needs calibration process during initialization with 2 calibration items, they are IF CAL (IF Filter calibration) and
VCO band CAL (VCO band calibration).
1.
2.
3.
VCO Bank Calibration is to select best VCO frequency bank for the calibrated frequency.
VCO Current Calibration.
IF Filter Bank Calibration is to calibrate IF filter bandwidth and center frequency.
Please notice that VCO Current, Bank and Deviation should be calibrated in PLL mode by sequence. IF Filter Bank and
RSSI could be calibrated in either standby or PLL mode.
15.1 IF Calibration Process
Under the Stand by state (XOSC is on), set bit MIFS=0(auto calibration) or bit MIFS=1(Manual calibration) to execute
the IF calibration. When the mode control register bit FBC=1, the chip will enter CAL state, and starts the calibration
process.
If RF chip is not in the STB state when bit FBC is set to 1, RF chip will not start the calibration process until it enters the
STB state. Once the calibration is completed, bit FBC will be cleared to 0 automatically, and RF chip will leave from CAL
state and back to STB state.
If the mode control register bit TRER=1, FBC=1 or VBC=1are set simultaneously, RF chip will enter the CAL state first,
and after completion of IF filter calibration or VCO band calibration process, RF chip can then enter into TX/RX state.
The maximum time required for A7129 RF chip to perform IF Calibration process is about 16 * 256 * (1 / system clock).
15.2. VCO band Calibration Process
Before the VCO band calibration, user should first set operating frequency in PLL I and PLL II registers, meanwhile, the
range of VT (VTH[2:0], VTL[2:0]) and VCO also needs to be set properly.
Under the Stand by state (XOSC is on), set bit MVBS=0(auto calibration) or bit MVBS=1(manual calibration) to execute
the VCO band calibration. After setting the mode control register bit VBC=1, the chip will enter CAL state, and starts the
calibration process. If RF chip is not in the STB state when bit VBC is set to 1, RF chip will not start the calibration
process until it entering STB state. When the calibration is completed, bit VBC will be cleared to 0 automatically, and
chip will leave from CAL state and back to STB state.
If the mode control register bit TRER=1, FBC=1 or VBC=1are set simultaneously, RF chip will enter the CAL state first,
and after completion of IF filter calibration or VCO band calibration process, RF chip can then enter into TX/RX state.
The maximum time required for A7129 RF chip to perform IF Calibration process is about 16 * 256 * (1 / system clock).
The maximum time required for A7129 RF chip to perform VCO band Calibration process is about 4 * PLL settling time.
Calibration (Address: 0Eh)
Address/Name R/W Bit15
0Eh
Calibration
Reset
W
R
Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 Bit 1
Bit 0
MSCRC
VTL2
VTL1
VTL0
VTH2
VTH1
VTH0 MVBS MVB2 MVB1
MVB0
MIFS
MIF3
MIF2
MIF1
MIF0
FCD4
FCD3
FCD2
FCD1
FCD0
DVT1
DVT0
VBCF
VB2
VB1
VB0
FBCF
FB3
FB2
FB1
FB0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
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FSK/GFSK Sub 1GHz Transceiver
16. FIFO (First In First Out)
A7129 supports separated 64-bytes TX and RX FIFO by enabling FMS =1 (0Fh). TX FIFO represents transmitted
payload. On the other hand, once RX circuitry synchronizes ID Code, received payload is stored into RX FIFO.
16.1 Packet Format
D a ta w h ite n in g (o p tio n a l)
F E C e n c o de d /d e co d e d (o p tio n a l)
C R C -1 6 c a lc u la tio n (o p tio n a l)
P re a m b le
ID c o d e
4 b y te s
4 b yte s
P a y lo a d
M a x. 2 5 6 b y te s
(C R C )
2 b yte s
Figure 16.1 Packet Format of FIFO mode
ID code
5xh or Axh
ID Byte 0
ID Byte 1
ID Byte 2
ID Byte 3
Figure 16.2 ID Code Format
Preamble:
The packet is led by preamble composed of alternate 0 and 1. If the first bit of ID code is 0, preamble shall be
0101…0101. In the contrast, if the first bit of ID code is 1, preamble shall be 1010…1010.
Preamble length is recommended to set 4 bytes by PML [1:0] (08h, page 14).
ID code:
ID code is recommended to set 4 bytes by IDL=1 (08h, page 14). ID Code is sequenced by Byte 2, 4, 6 and 8
(Recommend to set ID Byte 0 = 5xh or Axh). If RX circuitry checks the ID code correct, received payload will be stored
into RX FIFO. In special case, ID code could be set error tolerance (0~ 3bit error) by ETH [1:0] (0Ah) for ID
synchronization check.
Payload:
Payload length is programmable by FEP [13:0] (08h, page 10, 13) to define the FIFO length. The physical FIFO length is
64 bytes. A7129 also supports logical FIFO extension up to 16K bytes. See section 16.4.3 for details.
CRC (option):
In FIFO mode, if CRC is enabled (CRCS=1, 08h, page 14), 2-bytes of CRC value is transmitted automatically after
payload. In the same way, RX circuitry will check CRC value and show the result to CRC Flag (0Fh).
16.2 Bit Stream Process
A7129 supports 3 optional bit stream processes for payload, they are,
(1) CCITT-16 CRC (x16 + x15 + x2 + 1).
(2) (7, 4) Hamming FEC
(3) Data Whitening by XOR PN7 (7-bits Pseudo Random Sequence).
CRC (Cyclic Redundancy Check):
1.
2.
CRC is enabled by CRCS= 1 (08h, page 14). TX circuitry calculates the CRC value of payload (preamble, ID code
excluded) and transmits 2-bytes CRC value after payload.
RX circuitry checks CRC value and shows the result to CRC Flag (0Fh). If CRCF=0, received payload is correct,
else error occurred. (CRCF is read only, it is revised internally while receiving every packet.)
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FSK/GFSK Sub 1GHz Transceiver
FEC (Forward Error Correction):
1.
2.
3.
FEC is enabled by FECS= 1 (08h, page 14). Payload and CRC value (if CRCS=1) are encoded by (7, 4) Hamming
code.
Each 4-bits (nibble) of payload is encoded into 7-bits code word as well as delivered out automatically.
(ex. 64 bytes payload will be encoded to 128 code words, each code word is 7 bits.)
RX circuitry decodes received code words automatically. FEC supports 1-bit error correction each code word.
Once 1-bit error occurred, FEC flag=1 (0Fh). (FECF is read only, it is revised internally while receiving every
packet.)
Data Whitening:
1.
2.
Data whitening is enabled by WHTS= 1 (08h, page 14). The initial seed of PN7 is WS [6:0] (08h, page 14).
Payload is always encrypted by bit XOR operation with PN7. CRC and/or FEC are also encrypted if CRCS=1
and/or if FECS=1.
RX circuitry decrypts received payload and 2-bytes CRC (if CRCS=1) automatically. Please notice that user shall
set the same WS [6:0] to TX and RX.
16.3 Transmission Time
Based on CRC and FEC options, the transmission time differs depending on the chosen of CRC and FEC options. See
table 16.1 for details.
Data Rate = 250 Kbps
Preamble
ID Code
(bits)
(bits)
32
32
32
32
32
32
32
32
Payload
(bits)
512
512
512
512
CRC
(bits)
Disable
16 bits
Disable
16 x 7 / 4
Data Rate = 125 Kbps
Preamble
ID Code
(bits)
(bits)
32
32
32
32
32
32
32
32
Payload
(bits)
512
512
512
512
CRC
(bits)
Disable
16 bits
Disable
16 x 7 / 4
Data Rate = 50 Kbps
Preamble
ID Code
(bits)
(bits)
32
32
32
32
32
32
32
32
Payload
(bits)
512
512
512
512
CRC
(bits)
Disable
16 bits
Disable
16 x 7 / 4
Data Rate = 2 Kbps
Preamble
ID Code
(bits)
(bits)
32
32
32
32
32
32
32
32
Payload
(bits)
512
512
512
512
CRC
(bits)
Disable
16 bits
Disable
16 x 7 / 4
FEC
Disable
Disable
512 x 7 / 4
512 x 7 / 4
FEC
Disable
Disable
512 x 7 / 4
512 x 7 / 4
FEC
Disable
Disable
512 x 7 / 4
512 x 7 / 4
FEC
Disable
Disable
512 x 7 / 4
512 x 7 / 4
Transmission
Time / Packet
576 bit X 4 us = 2.304 ms
592 bit X 4 us = 2.368 ms
960 bit X 4 us = 3.840 ms
988 bit X 4 us = 3.952 ms
Transmission
Time / Packet
576 bit X 8 us = 4.608 ms
592 bit X 8 us = 4.736 ms
960 bit X 8 us = 7.580 ms
988 bit X 8 us = 7.904 ms
Transmission
Time / Packet
576 bit X 20 us = 11.52 ms
592 bit X 20 us = 11.84 ms
960 bit X 20 us = 19.20 ms
988 bit X 20 us = 19.76 ms
Transmission
Time / Packet
576 bit X 0.5 ms = 0.288 s
592 bit X 0.5 ms = 0.296 s
960 bit X 0.5 ms = 0.480 s
988 bit X 0.5 ms = 0.494 s
Table 16.1 Transmission time
16.4 Usage of TX and RX FIFO
In application points of view, A7129 supports 3 options of FIFO arrangement.
(1) Easy FIFO
(2) Segment FIFO
(3) FIFO Extension
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FSK/GFSK Sub 1GHz Transceiver
16.4.1 Easy FIFO Mode
In Easy FIFO mode, max FIFO length is 64 bytes. FIFO length is equal to (FEP [13:0] +1). User just needs to control
FEP [13:0] and disable PSA and FPM as shown below.
Register setting
TX
TX-FIFO (byte)
1
8
16
32
64
RX
RX-FIFO (byte)
1
8
16
32
64
Control Registers
FEP[13:0]
0x000
0x007
0x00F
0x01F
0x03F
PSA [5:0]
0
0
0
0
0
FPM [1:0]
0
0
0
0
0
Table 16.2 Control registers of Easy FIFO
Procedure of TX FIFO Transmitting
1.
Initialize all control registers (refer to A7129 reference code).
2.
Set FEP [13:0] = 0x3F for 64-bytes FIFO.
3.
Issue TX FIFO write pointer reset.
4.
MCU writes 64-bytes data to TX FIFO.
5.
Issue TX mode.
6.
Done.
Procedure of RX FIFO Reading
1.
When RX FIFO is full, WTR (or FSYNC) can be used to trigger MCU for RX FIFO reading.
2.
Issue RX FIFO read pointer reset.
3.
MCU read 64-bytes from RX FIFO.
4.
Done
Figure 16.3 Easy FIFO mode
16.4.2 Segment FIFO
In Segment FIFO, TX FIFO length is equal to (FEP [13:0] － PSA [5:0]＋1). FPM [1:0] should be zero. This function is
very useful for button applications. In such case, each button is used to transmit fixed code (data) every time. During
initialization, each fixed code is written into corresponding segment FIFO once and for all. Then, if button is triggered,
MCU just assigns corresponding segment FIFO (PSA [5:0] and FEP [13:0]) and issues TX strobe command.
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FSK/GFSK Sub 1GHz Transceiver
For example, if TX FIFO is arranged into 8 segments, each TX segment and RX FIFO length is divided into 8 bytes
TX
Segment
1
2
3
4
5
6
7
8
RX
FIFO Length
8 bytes
PSA
PSA1
PSA2
PSA3
PSA4
PSA5
PSA6
PSA7
PSA8
Control Registers
FEP
FEP1
FEP2
FEP3
FEP4
FEP5
FEP6
FEP7
FEP8
FIFO Length
8 bytes
8 bytes
8 bytes
8 bytes
8 bytes
8 bytes
8 bytes
8 bytes
PSA[5:0]
0x00
0x08
0x10
0x18
0x20
0x28
0x30
0x38
FEP[13:0]
0x007
0x00F
0x017
0x01F
0x027
0x02F
0x037
0x03F
FPM[1:0]
0
0
0
0
0
0
0
0
Control Registers
PSA[5:0]
0
FEP[13:0]
0x007
FPM[1:0]
0
Table 16.3 Segment FIFO is arranged into 8 segments
Procedures of TX FIFO Transmitting
1.
Initialize all control registers (refer to A7129 reference code).
2.
Strobe command – TX FIFO write pointer reset.
3.
Input the wanted code to the corresponding segment FIFO once and for all.
4.
To transmit segment 1, set PSA = 0x00 and FEP= 0x007
Else, to transmit segment 2, set PSA = 0x08 and FEP= 0x00F
Else, to transmit segment 3, set PSA = 0x10 and FEP= 0x017
Else, to transmit segment 4, set PSA = 0x18 and FEP= 0x01F
Else, to transmit segment 5, set PSA = 0x20 and FEP= 0x027
Else, to transmit segment 6, set PSA = 0x28 and FEP= 0x02F
Else, to transmit segment 7, set PSA = 0x30 and FEP= 0x037
Else, to transmit segment 8, set PSA = 0x38 and FEP= 0x03F
5.
Send TX Strobe Command.
6.
Done.
Procedures of RX FIFO Reading
1.
Set FEP [13:0] = 0x007.
2.
If RX FIFO is full, WTR (or FSYNC) is used to trigger MCU for RX FIFO reading.
3.
Strobe command – RX FIFO read pointer reset.
4.
MCU read 8-bytes from RX FIFO.
5.
Done.
Oct., 2012, Version 0.4 (PRELIMINARY)
50
AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
Figure 16.4 Segment FIFO Mode
16.4.3 FIFO Extension
In FIFO Extension, MCU can deliver a packet more than 64 bytes by monitoring FPF signal (from CKO or GIO1 or GIO2
pin). FIFO length is equal to (FEP [13:0] +1). PSA [5:0] shall be zero, and FPM [1:0] is used to set FPF threshold (FIFO
Pointer Flag). FIFO extension is max. 16K bytes by setting FEP [13:0].
Be notice, SPI speed is important to prevent error operation (over-write) in FIFO extension mode. We recommend the
min. SPI speed shall be equal or greater than (A7129 on-air data rate + 100Kbps).Please refer to AMICCOM’s
reference code (FIFO extension) for details.
Procedures of TX FIFO Extension
1.
Initialize all control registers (refer to A7129 reference code).
2.
Set FEP [13:0] = 0x0FF for 256-bytes FIFO extension.
3.
Set FPM [1:0] = [11] for FPF trigger condition.
4.
Set CKOS = [0010] to output FPF signal.
5.
Strobe command – TX FIFO write pointer reset.
6.
MCU writes 1st 64-bytes TX FIFO.
7.
TX Strobe command.
8.
MCU monitors FPF from A7129’s CKO pin.
9.
FPF triggers MCU to write 2nd 48-bytes TX FIFO.
10. Monitor FPF.
11. FPF triggers MCU to write 3rd 48-bytes TX FIFO.
12. Monitor FPF.
13. FPF triggers MCU to write 4th 48-bytes TX FIFO.
14. Monitor FPF.
15. FPF triggers MCU to write 5th 48-bytes TX FIFO.
16. Done.
Oct., 2012, Version 0.4 (PRELIMINARY)
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
Step 6:
MCU - Write TX FIFO
Write
64 bytes
Step 7:
StrobeCommand TX
Step 8:
Pin CKO - FPF
Step 9:
MCU - Write TX FIFO
FPF
Write
48 bytes
FPF
Step 10:
Pin CKO - FPF
Write
48 bytes
Step 11:
MCU - Write TX FIFO
FPF
Step 12:
Pin CKO - FPF
Write
48 bytes
Step 13:
MCU - Write TX FIFO
FPF
Step 14:
Pin CKO - FPF
Write
48 bytes
Step 15:
MCU - Write TX FIFO
GIO1 Pin (WTR)
TX
RFO Pin
Figure 16.5 TX FIFO Extension
Oct., 2012, Version 0.4 (PRELIMINARY)
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
Procedures of RX FIFO Reading
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
Initialize all control registers (refer A7129 reference code).
Set FEP [13:0] = 0x0FF for 256-bytes FIFO extension.
Set FPM [1:0] = 11b for FPF trigger condition.
Set CKOS = [0010] to output FPF signal.
Send Strobe command – RX FIFO read pointer reset.
Send RX Strobe command.
MCU monitors FPF from A7129’s CKO pin.
FPF triggers MCU to read 1st 48-bytes RX FIFO.
Monitor FPF.
FPF triggers MCU to read 2nd 48-bytes RX FIFO.
Monitor FPF.
FPF triggers MCU to read 3rd 48-bytes RX FIFO.
Monitor FPF.
FPF triggers MCU to read 4th 48-bytes RX FIFO.
Monitor FPF.
FPF triggers MCU to read 5th 48-bytes RX FIFO.
Monitor WTR falling edge or WTR = low, read the rest 16-bytes RX FIFO
Done.
Oct., 2012, Version 0.4 (PRELIMINARY)
53
AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
Figure 16.6 RX FIFO Extension Mode
Oct., 2012, Version 0.4 (PRELIMINARY)
54
AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
17. Analog Digital Converter
A7129 contains a built-in 8-bit ADC for internal temperature measurement, RSSI measurement.
XADS
0
0
CDM
0
1
None Rx state
Temperature measurement
N/A
RX state
RSSI measurement
Carrier detector
The conversion time of 8-bit ADC is depends on the clock input to ADC. It takes 24 cycles to complete the conversion.
The clock source of ADC comes from PF8M where ADC clock source is PF8M ÷ 2.
17.1 Temperature Measurement
A7129 has a simple on-chip temperature sensor. Set bit CDM=0 in ADC register first, then enable bit ADCM=1 in the
mode control register to start the measurement of temperature. When the measurement is completed, the bit ADCM will
be cleared to 0. User can then read the ADC[7:0] values from the ADC register.
17.2 RSSI Measurement
A7129 has a built-in RSSI (received signal strength indicator) read from ADC to measure the received RF signal
strength. When the measurement procedure is completed, the RSSI value can be read form ADC register, the range of
RSSI is 0~511. Larger signal strength is corresponding to smaller RSSI value, and vice versa. In RX state, set bit
CDM=0 in ADC register, and then set bit ADCM=1 in mode control register to start the RSSI measurement. Once the
measurement is completed, the bit ADCM will be cleared to 0. User can read the RSSI value from ADCO[8:0] (0x0B).
RSSI (AGC off)
200
ADCO[8:0]
150
100
50
-130
-120
-110 -100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Input power (dBm)
Figure 17.1 RSSI curve when AGC is disabled
17.3 Carrier detect
A7129 provides a CD signal (Carrier Detect output from GIO1 or GIO2) to monitor that there is a carrier or not. If the
carrier signal strength is greater than the value set by bit RTH[7:0] in ADC register, CD will go high, or it will stay low. In
RX state, set ADC register bit CDM=1, set mode control register bit ADCM=1 to start the carrier signal measurement.
The value is stored in bit ADC[7:0] and it will be updated in each measurement period till the end of detection action.
18. Battery Detect
Oct., 2012, Version 0.4 (PRELIMINARY)
55
AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
A7129 has built-in battery detector to check supply voltage (REGI pin). After enable battery detect function, user can
read VBD flag or output VBD to GIO1 or GIO2. The detect range is 2.0V ~ 2.7V in 8 levels.
Address/Name R/W Bit15
08h
PM
Reset
W
Bit14
Bit13 Bit12 Bit11 Bit10 Bit 9
CST POWRS CELS
-
0
0
STS
LVR
--
0
0
0
Bit 8
Bit 7
Bit 6
RGC1 RGC0 SPSS RGV1
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RGV0
QDS
BVT2
BVT1
BVT0
BDS
0
0
0
0
0
0
0
BVT [2:0]: Battery Voltage Threshold select.
[000]: 2.0V. [001]: 2.1V. [010]: 2.2V. [011]: 2.3V. [100]: 2.4V. [101]: 2.5V. [110]: 2.6V. [111]: 2.7V.
BDS: Battery Detection selection.
[0]: Disable. [1]: Enable.
Below is the procedure of battery detect for low voltage detection (ex., below 2.1V):
1.
2.
3.
4.
Set A7129 in standby or PLL mode.
Set detection level by BVT [2:0] = [001] and enable BDS = 1.
After 5 us, BDS is auto clear.
MCU check VBD flag.
If REGI pin > 2.1V,
VBD = 1. Else, VBD = 0.
19. TX power setting
A7129 supports programmable TX power by setting TBG[3:0], TDC [1:0] and PAC [1:0] from TXII register (09h).
Address/Name R/W Bit15
09h
TX II
W
Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9
MCNTR DPR2 DPR1 DPR0
DID15
R
Reset
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TDL0
TXDI PAC1 PAC0 TDC1 TDC0 TBG2 TBG1 TBG0
DID14 DID13 DID12 DID11 DID10 DID9
DID8
DID7
DID6
DID5
DID4
DID3
DID2
DID1
DID0
0
0
0
1
1
0
1
1
1
0
0
0
BT0
Bit 6
TDL1
0
BT1
Bit 8 Bit 7
0
0
0
PAC[1:0]: PA current setting.
TDC[1:0]: TX Driver current setting.
TBG[2:0]: TX Buffer Gain setting.
20. Low Current RX mode setting
A7129 supports ultra low current RX mode by reducing 2~3dB sensitivity. You could have lower RX current by setting
PLL comparing frequency to be half of crystal frequency (Compare frequency is 6.4MHz if crystal is 12.8MHz; 8MHz if
crystal is 16MHz) and setting Mixer current select register (MHM) and LNA current select register (LHM) to 0.
Address/Name R/W Bit15
06h
PLL VI
Reset
W
RFC3
Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9
Bit 8 Bit 7
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
RFC2 RFC1 RFC0 RIC11 RIC10 RIC9 RIC8 RIC7 RIC6 RIC5 RIC4 RIC3 RIC2
0
0
0
0
0
0
0
0
0
1
1
1
1
Bit 1
Bit 0
RIC1 RIC0
1
1
1
RFC[3:0]: R-Counter for Fractional-N PLL. Please set RFC[3:0]=[0001] to have FPFD as half of crystal frequency.
Address/Name R/W Bit15
08h
AGC2
Reset
W
R
Bit14
Bit13
Bit12
Bit11 Bit10
Bit 9
Bit 8 Bit 7
RGVA1 RGVA0 RGVT1 RGVT0 LHM1 LHM0 MHM1 MHM0 IGM1
--
--
--
--
--
--
--
--
LHC1 LHC0 MHC1 MHC0 IGC1
--
--
--
--
--
Bit 6
Bit 5
Bit 4
IGM0
CA1
CA0
IGC0
--
Bit 3
Bit 2
Bit 1
--
--
--
--
--
--
--
--
0
0
0
0
MHM[1:0]: Mixer Current Select. Please set MHM[1:0]=[00].
LHM[1:0]: LNA Current Select. Please set LHM[1:0]=[00].
Oct., 2012, Version 0.4 (PRELIMINARY)
56
Bit 0
TXIB1 TXIB0 RSAGC1 RSAGC0
AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
21. Application Circuit
21.1 MD7129-A40 (434MHz Band)
C5
24
43nH(HiQ)
19 GIO1
L1
10uF
20 GIO2
1nF
C1
2.2uF
21 CKO
0.1uF
22 REGI
C4
23 VDA
C2
C3
VDD_TX 5
L3
C9
6
27nH
GPIO1
GPIO2
CKO
SDIO
A7129
RFO
SCK
VDD_TX
SCS
VDD_V
0.47uF
LPF is used for passing CE/FCC
REGI
RFI
GND
18
0.1uF
17
16
SDIO
15
SCK
14
SCS
13
XO
120nH(HiQ)
47nF
LPF
4
DVDD
XI
L2
C19
GND
VDD_P
3
VT
2
0.5pF
A7129
11
12
XI
7
1uF
XO
C6
10
C18 18nH
C8
18pF
10pF
9
C17 18nH
10pF
C10
C13
5.6pF L7
43nH(HiQ)
L5
DVDD
VCON
L4
C11
RSSI
VCOP
1
TRX
BPBG
C14 470pF
1.8pF
J1
VDDA
U1
100pF
8
C12
1
2
3
4
5
6
7
8
9
10
J3
1
2
L6
11nH(HiQ)
CON/2P 1.27
J4
VDA
REGI
GND
CKO
GIO2
GIO1
SDIO
SCK
SCS
GND
X_CLK
VDA
J2
Y1
C7
12.8MHz CL=20pF
1uF
1
2
CON/2P 1.27
CON/10P 2.0
C15
R1
150pF 8.2K
C16
22nF
Where Xtal is 12.8MHz with 20 pF C-load.
Oct., 2012, Version 0.4 (PRELIMINARY)
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
21.2 MD7129-A50 (470MHz~510MHz Band)
C5
L2
4
120nH(HiQ)
6
C19
GPIO1
GPIO2
CKO
SCK
VDD_TX
SCS
VDD_V
GND
12
XI
L5
11
VDA
XO
1uF
10
0.47uF
J3
1
2
3
4
5
6
7
8
9
10
C7
SDIO
15
SCK
14
SCS
13
12.8MHz CL=20pF
1uF
1
2
16
Y1
8.2nH(HiQ)
J2
0.1uF
17
A7129
C6
C9
REGI
GND
CKO
GIO2
GIO1
SDIO
SCK
SCS
GND
X_CLK
A7129
RFO
VCON
47nF
SDIO
VDA
LPF
VDD_TX 5
DVDD
RFI
18
XO
6.8pF
GND
XI
3
VDD_P
2
0.5pF
VT
8.2pF
C13
5.6pF L6
39nH(HiQ)
9
NC
C8
DVDD
8
L4
C18 22nH
C11
RSSI
7
L3
C10
VCOP
1
J1
REGI
BPBG
C14 470pF
VDDA
U1
100pF
1.5pF
C17 15nH
19 GIO1
C3
C12
TRX
20 GIO2
24
39nH(HiQ)
10uF
21 CKO
L1
C1
2.2uF
22 REGI
0.1uF
1nF
23 VDA
C2
C4
CON/2P 1.27
J4
1
2
C15
CON/2P 1.27
R1
150pF 8.2K
CON/10P 2.0
C16
22nF
Where Xtal is 12.8MHz with 20 pF C-load.
Oct., 2012, Version 0.4 (PRELIMINARY)
58
AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
21.3 MD7129-A80 (868MHz Band)
C1
C5
C8
N.C
LPF
LPF is used for passing CE/FCC
L2
3
RFO
4
24nH(HiQ) VDD_TX 5
C9
0.47uF
C19
47nF
L3
18nH(HiQ)
6
GPIO1
GPIO2
CKO
REGI
BPBG
VDDA
GND
DVDD
RFI
SDIO
A7129
RFO
SCK
VDD_TX
SCS
VDD_V
GND
C6
1
2
3
4
5
6
7
8
9
10
1
2
1.3nH(HiQ)
16
SDIO
15
SCK
14
SCS
13
11
12
XI
Y1
C7
J3
1uF 12.8MHz CL=20pF
CON/2P 1.27
1
2
XO
10
VDA
VT 9
8
7
L6
VCOP
VCON
VDA
J2
0.1uF
17
A7129
1uF
REGI
GND
CKO
GIO2
GIO1
SDIO
SCK
SCS
GND
X_CLK
18 DVDD
XO
3.9pF
RFI
C11
DVDD
XI
C18
3.3pF
0.5pF
RSSI
VDD_P
C17
3.9pF L7
18nH(HiQ)
2
VT
9.1nH
1
VCON
10nH
RSSI
C10
C13
VDD_V
L5
L4
U1
C14
470pF
VCOP
47pF
1pF
TRX
19 GIO1
C3
C12
J1
24
18nH(HiQ)
20 GIO2
BPBG
L1
10uF
21 CKO
1nF 0.1uF
2.2uF
22 REGI
C2
23 VDA
C4
J4
CON/2P 1.27
CON/10P 2.0
C15
R1
8.2K
150pF
C16
22nF
Where Xtal is 12.8MHz with 20 pF C-load.
Oct., 2012, Version 0.4 (PRELIMINARY)
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
22. Abbreviations
ADC
AFC
AGC
BER
BW
CD
CRC
FEC
FIFO
FSK
ID
IF
ISM
LO
MCU
PFD
PLL
POR
RX
RXLO
RSSI
SPI
SYCK
TX
TXRF
VCO
XOSC
XREF
XTAL
Analog to Digital Converter
Automatic Frequency Compensation
Automatic Gain Control
Bit Error Rate
Bandwidth
Carrier Detect
Cyclic Redundancy Check
Forward Error Correction
First in First out
Frequency Shift Keying
Identifier
Intermediate Frequency
Industrial, Scientific and Medical
Local Oscillator
Micro Controller Unit
Phase Frequency Detector for PLL
Phase Lock Loop
Power on Reset
Receiver
Receiver Local Oscillator
Received Signal Strength Indicator
Serial to Parallel Interface
System Clock for digital circuit
Transmitter
Transmitter Radio Frequency
Voltage Controlled Oscillator
Crystal Oscillator
Crystal Reference frequency
Crystal
23. Ordering Information
Part No.
Package
Units Per Reel / Tray
A71X29AQFI/Q
QFN24L, Pb Free, Tape & Reel, -40℃〜85℃
3K
A71X29AQFI
QFN24L, Pb Free, Tray, -40℃〜85℃
490EA
A71X29AH
Die form, -40℃〜85℃
250EA
Oct., 2012, Version 0.4 (PRELIMINARY)
60
AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
24. Package Information
QFN 24L (4 X 4 X 0.8mm) Outline Dimensions
unit: inches/mm
TOP VIEW
BOTTOM VIEW
0.25 C
D
D2
11
13
18
L
15
10
12
19
7
24
e
E
E2
16
0.25 C
20
6
1
6
5
e
b
1
0.10 M C A B
Seating Plane
Symbol
y C
A3
A1
A
// 0.10 C
C
Dimensions in inches
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
A
0.028
0.030
0.032
0.70
0.75
0.80
A1
0.000
0.001
0.002
0.00
0.02
0.05
A3
0.008 REF
0.203 REF
b
0.007
0.010
0.012
0.18
0.25
0.30
D
0.154
0.158
0.161
3.90
4.00
4.10
D2
0.075
-.
0.114
1.90
-
2.90
E
0.154
0.158
0.161
3.90
4.00
4.10
E2
0.075
-
0.114
1.90
-
2.90
0.020 BSC
e
L
0.012
y
Oct., 2012, Version 0.4 (PRELIMINARY)
0.016
0.50 BSC
0.020
0.003
0.30
0.40
0.50
0.08
61
AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
25. Top Marking Information
A71X29AQFI
¡ Part No.
¡ Pin Count
¡ Package Type
¡ Dimension
¡ Mark Method
¡ Character Type
: A71X29AQFI
: 24
: QFN
: 4*4 mm
: Laser Mark
: Arial
J
C1
K
F
7129
NNNNNNNNN
Y Y WW X
D
L
C2
G
C3
A
B
I
v CHARACTER SIZE : (Unit in mm)
A : 0.55
B : 0.36
C1 : 0.25
D : 0.03
C2 : 0.3
C3 : 0.2
Y YWW
: DATECODE
X
: PKG HOUSE ID
N N N N N N N N N : LOT NO.
(max. 9 characters)
F=G
I=J
K=L
0.65
0.80
1.60
0.68
Oct., 2012, Version 0.4 (PRELIMINARY)
7129
62
AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
26. Reflow Profile
Oct., 2012, Version 0.4 (PRELIMINARY)
63
AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
27. Tape Reel Information
Cover / Carrier Tape Dimension
TYPE
20 QFN 4*4
24 QFN 4*4
32 QFN 5*5
QFN3*3 / DFN-10
20 SSOP
24 SSOP
P
8
8
8
4
12
12
A0
4.35
4.4
5.25
3.2
8.2
8.2
B0
4.35
4.4
5.25
3.2
7.5
8.8
TYPE
20 QFN (4X4)
24 QFN (4X4)
32 QFN (5X5)
QFN3*3 / DFN-10
20 SSOP
24 SSOP
Oct., 2012, Version 0.4 (PRELIMINARY)
P0
4.0
4.0
4.0
4.0
4.0
4.0
P1
2.0
2.0
2.0
2.0
2.0
2.0
K0
1.1
1.4
1.1
0.75
2.5
2.1
64
t
0.3
0.3
0.3
0.25
0.3
0.3
D0
1.5
1.5
1.5
1.5
1.5
1.5
D1
1.5
1.5
1.5
1.5
1.5
E
1.75
1.75
1.75
1.75
1.75
1.75
Unit: mm
F
W
5.5
12
5.5
12
5.5
12
1.9
8
7.5
16
7.5
16
COVER TAPE WIDTH
9.2
9.2
9.2
8
13.3
13.3
AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
REEL DIMENSIONS
UNIT IN mm
TYPE
20 QFN(4X4)
24 QFN(4X4)
32 QFN(5X5)
DFN-10
48 QFN(7X7)
G
N
T
M
20 SSOP
24 SSOP
K
L
R
12.8+0.6/13.0+0.5/330＋
100 REF 18.2(MAX) 1.75±0.25
2.0±0.5
20.2
0.4
0.2
0.00/-1.0
16.8+0.6/-
13.0+0.5/100 REF 22.2(MAX) 1.75±0.25
0.4
28 SSOP (150mil)
D
0.2
20.4+0.6/-
13.0+0.5/100 REF 25(MAX) 1.75±0.25
0.4
0.2
16.4+2.0/-
13.0+0.2/100 REF 22.4(MAX) 1.75±0.25
0.0
0.2
330＋
2.0±0.5 0.00/-1.0 20.2
330＋
2.0±0.5 0.00/-1.0 20.2
330＋
1.9±0.4 0.00/-1.0 20.2
T
L
D
R
N
M
K
Oct., 2012, Version 0.4 (PRELIMINARY)
G
65
AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
28. Product Status
Data Sheet Identification
Objective
Product Status
Planned or Under Development
Definition
This data sheet contains the design
specifications for product development.
Specifications may change in any manner
without notice.
Preliminary
Engineering Samples
and First Production
This data sheet contains preliminary data, and
supplementary data will be published at a later
date. AMICCOM reserves the right to make
changes at any time without notice in order to
improve design and supply the best possible
product.
No Identification
Noted Full Production
Obsolete
Not In Production
This data sheet contains the final specifications.
AMICCOM reserves the right to make changes
at any time without notice in order to improve
design and supply the best possible product.
This data sheet contains specifications on a
product that has been discontinued by
AMICCOM. The data sheet is printed for
reference information only.
RF ICs AMICCOM
Headquarter
A3, 1F, No.1, Li-Hsin 1st Rd., Hsinchu Science Park,
Hsinchu, Taiwan 30078
Tel: 886-3-5785818
Shenzhen Office
Rm., 2003, DongFeng Building, No. 2010,
Shennan Zhonglu Rd., Futian Dist., Shenzhen, China
Post code: 518031
Web Site
http://www.amiccom.com.tw
Oct., 2012, Version 0.4 (PRELIMINARY)
66
AMICCOM Electronics Corporation
工商网监
湘ICP备2023018690号
