MXD8666

MXD8666 SP6T Switch with MIPI for LTE Diversity VED APPRO This document contains information that is confidential and proprietary to Maxscend Technologies Inc. (Maxscend) and may not be reproduced in any form without express written consent of Maxscend. No transfer or licensing of technology is implied by this document. Page 1 of 10 Maxscend Technologies Inc. All rights reserved. Maxscend Confidential MXD8666 – SP6T Switch with MIPI for LTE Diversity General Description Features The MXD8666 is a low loss, high isolation SP6T  Excellent insertion loss - 0.50 dB Insertion Loss at 2.7GHz switch for antenna diversity receiving. The MXD8666 is compatible with MIPI control,  P0.1dB @ 27dBm which is a key requirement for many cellular  Multi-Band operation 700MHz to 3000MHz  RFFE serial control interface  Compact 2mm x 2mm in QFN-14 package  No DC blocking capacitors required (unless transceivers. This part is packaged in a compact 2mm x 2mm, 14-pin, QFN package which allows for a small solution size with no need for external DC external DC is applied to the RF ports) blocking capacitors (when no external DC is applied to the device ports). Applications  2G/3G/4G antenna diversity  Cellular modems and USB Devices VDD NC RF3 RF2 14 13 12 11 Functional Block Diagram and Pin Function RF1 RF2 VIO 1 SDATA 2 SCLK 3 RF3 RF4 Ground Paddle ANT RF5 10 RF1 9 ANT 8 GND 5 6 7 RF6 RF5 RF4 SCLK 4 VIO VDD GND RF6 SDATA Figure 1 Functional Block Diagram and Pinout (Top View) Page 2 of 10 Maxscend Technologies Inc. All rights reserved. Maxscend Confidential MXD8666 – SP6T Switch with MIPI for LTE Diversity RF3 RF2 12 11 Application Circuit 13 14 C4 100pF RF1 Ground Paddle ANT RF1 ANT GND C2 DN1 RF4 RF5 C3 DN1 RF6 C1 33nF Figure 2 MXD8666 Evaluation Board Schematic Table 1. Pin Description Pin No. 1 2 3 4 5 6 7 Ground Paddle Name VIO SDATA SCLK GND RF6 RF5 RF4 Description Supply voltage for MIPI MIPI data input/output MIPI clock Ground RF port6 RF port5 RF port4 GND Ground Pin No. 8 9 10 11 12 13 14 Name GND ANT RF1 RF2 RF3 NC VDD Description Ground Antenna port RF port1 RF port2 RF port3 NC Power supply Note: Bottom ground paddles must be connected to ground. Page 3 of 10 Maxscend Technologies Inc. All rights reserved. Maxscend Confidential MXD8666 – SP6T Switch with MIPI for LTE Diversity Truth Table Table 2. Control Register_0 0x06 Switched RF Outputs RF1 Insertion Loss RF2 RF3 RF4 RF5 RF6 Isolation Isolation Isolation Isolation Isolation 0x04 Isolation Insertion Loss Isolation Isolation Isolation Isolation 0x02 Isolation Isolation Insertion Loss Isolation Isolation Isolation 0x05 Isolation Isolation Isolation Insertion Loss Isolation Isolation 0x03 Isolation Isolation Isolation Isolation Insertion Loss Isolation 0x01 Isolation Isolation Isolation Isolation Isolation Insertion Loss 0x00 Isolation Isolation Isolation Isolation Isolation Isolation Recommended Operation Range Table 3. Recommended Operation Condition Parameters Operation Frequency Power supply Power supply for MIPI MIPI Control Voltage High MIPI Control Voltage Low Symbol Min Typ Max Units f1 VDD VIO VH VL 0.7 2.5 1.65 0.8*VIO 0 2.8 1.8 1.8 0 3.0 3.0 1.95 1.95 0.3 GHz V V V V Min Typical Max Units 2.5 2.8 3.0 V 30 50 uA 1.8 1.95 V 4 10 uA VIO 0 1.95 0.3 V V 10% to 90% RF 1 2 uS 0.1 to 1.0 GHz 1.0 to 2.0 GHz 2.0 to 2.7 GHz 0.1 to 1.0 GHz 1.0 to 2.0 GHz 2.0 to 2.7 GHz 0.1 to 1.0 GHz 1.0 to 2.0 GHz 2.0 to 2.7 GHz 0.30 0.40 0.50 40 30 24 25 20 15 dB dB dB dB dB dB dB dB dB +27 dBm Specifications Table 4. Electrical Specifications Parameter Symbol Test Condition DC Specifications Supply voltage VDD Supply current IDD VIO supply voltage VIO VIO Supply current SDATA, SCLK control voltage: High Lo w Switching Speed, one RF to another IIO 1.65 VCTL_H VCTL_L 0.8* VIO 0 RF Specifications Insertion loss (ANT pin to RF1/2/3/4/5/6 pins) IL Isolation (ANT pin to RF1/2/3/4/5/6 pins) Iso Input return loss (ANT pin to RF1/2/3/4/5/6 pins) RL 0.1 dB Compression Point (ANT pin to RF1/2/3/4/5/6 pins) P0.1dB 0.7 GHz to 3.0 GHz 35 25 20 20 15 12 Page 4 of 10 Maxscend Technologies Inc. All rights reserved. Maxscend Confidential MXD8666 – SP6T Switch with MIPI for LTE Diversity MIPI Read and Write Timing MIPI supports the following Command Sequences: • Register Write • Register_0 Write • Register Read Figures 3 and 4 provide the timing diagrams for register write commands and read commands, respectively. Figure 5 shows the Register 0 Write Command Sequence. Refer to the MIPI Alliance Specification for RF Front-End Control Interface (RFFE), v1.10 (26 July 2011) for additional information on MIPI USID programming sequences and MIPI bus specifications. CLK SA3 Data SA2 SA1 SA0 0 SSC 1 0 A4 A3 A2 A1 A0 P A0 P Register Write Command Frame CLK Data P D7 D6 D5 D4 D3 D2 D1 D0 P 0 Bus Park Data Frame Signal driven by Master Signal not driven, pull down only For reference only Figure 3 Register Write Command Sequence CLK SA3 Data SA2 SA1 SA0 0 SSC 1 1 A4 A3 A2 A1 Register Read Command Frame CLK Data P 0 Bus Park D7 D6 D5 D4 D3 D2 Data Frame (from Slave) D1 D0 P 0 Bus Park Signal driven by Master Signal driven by Slave Signal not driven, pull down only by Master For reference only Figure 4 Register Read Command Sequence Page 5 of 10 Maxscend Technologies Inc. All rights reserved. Maxscend Confidential MXD8666 – SP6T Switch with MIPI for LTE Diversity In the timing figures, SA[3:0] is slave address. A[4:0] is register address. D[7:0] is data. “P” is odd parity bit. Register 0 Write Command Sequence Figure shows the Register 0 Write Command Sequence. The Command Sequence starts with an SSC, followed by the Register 0 Write Command Frame containing the Slave address, a logic one, and a seven bit word to be written to Register 0. The Command Sequence ends with a Bus Park Cycle. CLK SA3 Data SSC SA2 SA1 SA0 1 D6 D5 D4 Slave Address D3 Data D2 D1 D0 P 0 Parity Bus Park Signal driven by Master Signal not driven, pull down only For reference only Figure 5 Register 0 Write Command Sequence Page 6 of 10 Maxscend Technologies Inc. All rights reserved. Maxscend Confidential MXD8666 – SP6T Switch with MIPI for LTE Diversity Register definition Table 5. Register definition table Register Address Register Name Data Bits R/W Function Description Default BROADC AST_ID support Trigger support 0x00 REGISTER_0 7:0 R/W RF Control Register_0 truth Table: Table 2 0x00 No Yes 7 R/W SOFTWARE RESET 0: Normal operation 1: Software reset Note: On software reset, this register and all configurable registers are reset except for USID, GSID, and PM_TRIG. 0 No No 6 R/W COMMAND_FR AME_PARITY_E RR Command Frame with parity error 0 No No 5 R/W COMMAND_LE NGTH_ERR Command Sequence with incorrect length 0 No No 4 R/W ADDRESS_FRA ME_PARITY_E RR Address Frame with parity error 0 No No 3 R/W DATA_FRAME_ PARITY_ERR Data Frame with parity error 0 No No 2 R/W READ_UNUSED _REG Read Command Sequence to an invalid address 0 No No 1 R/W WRITE_UNUSE D_REG Write Command Sequence to an invalid address 0 No No 0 R/W BID_GID_ERR Read Command Sequence with a BSID or GSID Note: Reading this register resets this register. 0 No No 7:4 R RESERVED 0x0 No No 3:0 R/W GSID Group Slave ID 0x0 No No 0b10 Yes No 0x001A 0x001B 0x001C RFFE_STATU S GROUP_SID PM_TRIG 0x001D PRODUCT_ID 0x001E MANUFACTU RER_ID 0x001F MAN_USID 7:6 R/W PWR_MODE 00: Normal Operation (ACTIVE) 01: Reset all registers to default settings (STARTUP) 10: Low power (LOW POWER) 11: Reserved Note: Write PWR_MODE=2’h1 will reset all register, and puts the device into STARTUP state. 5 R/W Trigger_Mask_2 If this bit is set, trigger 2 is disabled 0 No No 4 R/W Trigger_Mask_1 If this bit is set, trigger 1 is disabled 0 No No 0 No No 3 R/W Trigger_Mask_0 If this bit is set, trigger 0 is disabled Note: When all triggers are disabled, writing to a register that is associated with trigger 0, 1, or 2, causes the data to go directly to the destination register. 2 W Trigger_2 A write of a one to this bit loads trigger 2's registers 0 Yes No 1 W Trigger_1 A write of a one to this bit loads trigger 1's registers 0 Yes No 0 Yes No 0 W Trigger_0 A write of a one to this bit loads trigger 0's registers Note: Trigger processed immediately then cleared. Trigger 0, 1, and 2 will always read as 0. 7:0 R PRODUCT_ID Product Number 0x5e No No 7:0 R MANUFACTUR ER_ID[7:0] Lower eight bits of MIPI registered Manufacturer ID 0x81 No No 7:6 R RESERVED 0b00 No No 5:4 R MANUFACTUR ER_ID[9:8] Upper two bits of MIPI registered Manufacturer ID 0b11 No No 3:0 R/W USID USID of the device. 0xb No No Page 7 of 10 Maxscend Technologies Inc. All rights reserved. Maxscend Confidential MXD8666 – SP6T Switch with MIPI for LTE Diversity Absolute Maximum Ratings Table 6. Maximum ratings Parameters Symbol Minimum Maximum Units Supply voltage VIO Supply voltage MIPI Control voltage (SDATA, SCLK) RF input power (RF1 to RF6) Operating temperature Storage temperature Electrostatic Discharge Human body model (HBM), Class 1C Machine Model (MM), Class A Charged device model (CDM), Class III VDD VIO +2.0 +1.5 +3.3 +2.0 V VCTL 0 +2.0 V PIN TOP TSTG –20 –40 +28 +85 +125 dBm ℃ ℃ ESD_HBM 1000 ESD_MM 100 ESD_CDM 500 V Note: Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other parameters set at or below their nominal value. Exceeding any of the limits listed here may result in permanent damage to the device Power ON and OFF sequence Here is the recommendation about power-on/off sequence in order to avoid damaging the device. Power ON 1) Apply voltage supply - VDD 2) Apply logic supply - VIO 3) Wait 10μs or greater and then apply MIPI bus signals – SCLK and SDATA 4) Wait 5μs or greater after MIPI bus goes idle and then apply the RF Signal Power OFF 1) Remove the RF Signal 2) Remove MIPI bus – SCLK and SDATA 3) Remove logic supply - VIO 4) Remove voltage supply - VDD VDD ON VDD VIO ON MIPI RF Trigger ON RF OFF ≥100us VIO OFF VDD OFF ≥100us VIO Slave State SDATA,SCLK SHUTDOWN STARTUP ≥10us ACTIVE SHUTDOWN ≥5us RF Signal Note: VIO can be applied to the device before VDD or removed after VDD. It is important to wait 10μs after VIO & VDD are applied before sending SDATA to ensure correction data transmission. The minimum time between a power up and power down sequence (and vice versa) is ≥ 100us. Page 8 of 10 Maxscend Technologies Inc. All rights reserved. Maxscend Confidential MXD8666 – SP6T Switch with MIPI for LTE Diversity Package Outline Dimension Figure 6 package outline dimension Page 9 of 10 Maxscend Technologies Inc. All rights reserved. Maxscend Confidential MXD8666 – SP6T Switch with MIPI for LTE Diversity Reflow Chart tP TP Critical Zone TL to TP Ramp-up Temperature TL TSmax tL TSmin Ramp-down tS Preheat t 25 ℃ to Peak Time Figure 7 Recommended Lead-Free Reflow Profile Table 7. Reflow condition Profile Parameter Ramp-up rate（TSmax to Tp） Preheat temperature（TSmin to TSmax） Preheat time（ts） Time above TL , 217℃（tL） Peak temperature（Tp） Time within 5℃ of peak temperature(tp) Ramp-down rate Time 25℃ to peak temperature Lead-Free Assembly, Convection, IR/Convection 3℃/second max. 150℃ to 200℃ 60 - 180 seconds 60 - 150 seconds 260℃ 20 - 40 seconds 6℃/second max. 8 minutes max. ESD Sensitivity Integrated circuits are ESD sensitive and can be damaged by static electric charge. Proper ESD protection techniques should be used when handling these devices. RoHS Compliant This product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB) and polybrominated diphenyl ethers (PBDE), and are considered RoHS compliant. 1.1.1 Page 10 of 10 Maxscend Technologies Inc. All rights reserved. Maxscend Confidential