CMT2110/17A
CMT2110/17A
Low-Cost 240 – 960 MHz OOK Transmitter
Features
Applications
Low-Cost Consumer Electronics Applications
Very Easy Development with RFPDK
Home and Building Automation
All Features Programmable
Remote Fan Controllers
Infrared Transmitter Replacements
240 to 480 MHz (CMT2110A)
Industrial Monitoring and Controls
240 to 960 MHz (CMT2117A)
Remote Lighting Control
Embedded EEPROM
Frequency Range:
OOK Modulation
Wireless Alarm and Security Systems
Symbol Rate: 0.5 to 30 ksps
Remote Keyless Entry (RKE)
Output Power: -10 to +13 dBm
Supply Voltage: 1.8 to 3.6 V
Current Consumption: 12.4 mA @ +10 dBm
Sleep Current: < 20 nA
FCC / ETSI Compliant
RoHS Compliant
6-pin SOT23-6 Package
Ordering Information
Part Number
Frequency
Package
MOQ
CMT2110A-ESR
433.92 MHz
SOT23-6
3,000 pcs
CMT2117A-ESR
868.35 MHz
SOT23-6
3,000 pcs
More Ordering Info: See Page 20
Descriptions
The CMT2110/17A devices are ultra low-cost, highly
flexible, high performance, single-chip OOK transmitters for
various 240 to 960 MHz wireless applications. The
CMT2110A covers the frequency range from 240 to 480
MHz while the CMT2117A covers the 240 to 960 MHz
frequency range. They are part of the CMOSTEK
NextGenRFTM family, which includes a complete line of
transmitters, receivers and transceivers. With very low
SOT23-6
current consumption, the device modulates and transmits
the data which is sent from the host MCU. An embedded
EEPROM allows the frequency, output power and other
features to be programmed into the chip using the
CMOSTEK USB Programmer and RFPDK. Alternatively, in
stock products of 433.92/868.35 MHz are available for
XTAL
1
6
VDD
GND
2
5
RFO
DATA
3
4
CLK
immediate demands without the need of EEPROM
programming. The CMT2110/17A uses a 1-pin crystal
oscillator circuit with the required crystal load capacitance
integrated on-chip to minimize the number of external
components. The CMT2110/17A transmitter together with
the CMT221x receiver enables an ultra low cost RF link.
Copyright © By CMOSTEK
Rev 1.2 | Page 1/25
CMT2110/17A
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CMT2110/17A
Typical Application
CMT2110/17A
X1
J1
1
VDD
XTAL
VDD
VDD
6
ANT
1
2
3
VDD
C0
DATA
L1
CLK
2
4
U1
GND
RFO
L2
5
C1
Note: Connector J1 is for
EEPROM Programming
3
DATA
DATA
CLK
4
C2
CLK
Figure 1. CMT2110/17A Typical Application Schematic
Table 1. BOM of 433.92/868.35 MHz Low-Cost Application
Value
Designator
Descriptions
868.35 MHz[1]
433.92 MHz
U1
CMT2110/17A, Low-Cost 240 – 960 MHz
OOK Transmitter
Unit
Manufacturer
-
-
CMOSTEK
X1
±20 ppm, SMD32*25 mm crystal
26
MHz
EPSON
C0
±20%, 0402 X7R, 25 V
0.1
uF
Murata GRM15
C1
±5%, 0402 NP0, 50 V
82
82
pF
Murata GRM15
C2
±5%, 0402 NP0, 50 V
9
3.9
pF
Murata GRM15
L1
±5%, 0603 multi-layer chip inductor
180
100
nH
Murata LQG18
L2
±5%, 0603 multi-layer chip inductor
27
8.2
nH
Murata LQG18
Note:
[1]. The 868.35 MHz Application is for CMT2117A only.
Table 2. Product Selection Table
Product
Frequency
Modulation
Max Output
Power
CMT2110A
240-480 MHz
OOK
+13 dBm
CMT2117A
240-960 MHz
OOK
+13 dBm
Rev 1.2 | Page 2/25
Tx Current Consumption
13.4 mA
(+10 dBm @ 433.92 MHz)
15.5 mA
(+10 dBm @ 868.35 MHz)
Embedded
EEPROM
√
√
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CMT2110/17A
Abbreviations
Abbreviations used in this data sheet are described below
AN
Application Notes
PA
Power Amplifier
BOM
Bill of Materials
PC
Personal Computer
BSC
Basic Spacing between Centers
PCB
Printed Circuit Board
EEPROM
Electrically Erasable Programmable Read-Only
PN
Phase Noise
Memory
RCLK
Reference Clock
Electro-Static Discharge
RF
Radio Frequency
ESR
Equivalent Series Resistance
RFPDK
RF Product Development Kit
ETSI
European Telecommunications Standards
RoHS
Restriction of Hazardous Substances
Institute
Rx
Receiving, Receiver
FCC
Federal Communications Commission
SOT
Small-Outline Transistor
Max
Maximum
SR
Symbol Rate
MCU
Microcontroller Unit
TWI
Two-wire Interface
Min
Minimum
Tx
Transmission, Transmitter
MOQ
Minimum Order Quantity
Typ
Typical
NP0
Negative-Positive-Zero
USB
Universal Serial Bus
OBW
Occupied Bandwidth
XO/XOSC
Crystal Oscillator
OOK
On-Off Keying
XTAL
Crystal
ESD
Rev 1.2 | Page 3/25
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CMT2110/17A
Table of Contents
1. Electrical Characteristics ............................................................................................................................................ 5
1.1 Recommended Operating Conditions ................................................................................................................... 5
1.2 Absolute Maximum Ratings................................................................................................................................... 5
1.3 Transmitter Specifications ..................................................................................................................................... 6
1.4 Crystal Oscillator ................................................................................................................................................... 7
2. Pin Descriptions .......................................................................................................................................................... 8
3. Typical Performance Characteristics ......................................................................................................................... 9
4. Typical Application Schematics ............................................................................................................................... 10
4.1 Low-Cost Application Schematic ......................................................................................................................... 10
4.2 FCC/ETSI Compliant Application Schematic....................................................................................................... 11
5. Functional Descriptions ............................................................................................................................................ 12
5.1 Overview ............................................................................................................................................................. 12
5.2 Modulation, Frequency and Symbol Rate ........................................................................................................... 12
5.3 Embedded EEPROM and RFPDK ...................................................................................................................... 13
5.4 Power Amplifier ................................................................................................................................................... 14
5.5 PA Ramping ........................................................................................................................................................ 14
5.6 Crystal Oscillator and RCLK................................................................................................................................ 15
6. Working States and Transmission Control Interface ............................................................................................. 16
6.1 Working States .................................................................................................................................................... 16
6.2 Transmission Control Interface ........................................................................................................................... 16
6.2.1 Tx Enabled by DATA Pin Rising Edge...................................................................................................... 17
6.2.2 Tx Enabled by DATA Pin Falling Edge ..................................................................................................... 17
6.2.3 Two-wire Interface.................................................................................................................................... 17
7. Ordering Information ................................................................................................................................................. 20
8. Package Outline......................................................................................................................................................... 21
9. Top Marking ............................................................................................................................................................... 22
9.1 CMT2110/17A Top Marking ................................................................................................................................ 22
10. Other Documentations .............................................................................................................................................. 23
11. Document Change List.............................................................................................................................................. 24
12. Contact Information .................................................................................................................................................. 25
Rev 1.2 | Page 4/25
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CMT2110/17A
1. Electrical Characteristics
VDD = 3.3 V, TOP = 25 ℃, FRF = 433.92 MHz, output power is +10 dBm terminated in a matched 50 Ω impedance, unless
otherwise noted.
1.1 Recommended Operating Conditions
Table 3. Recommended Operation Conditions
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Operation Voltage Supply
VDD
1.8
3.6
V
Operation Temperature
TOP
-40
85
℃
Supply Voltage Slew Rate
1
mV/us
1.2 Absolute Maximum Ratings
Table 4. Absolute Maximum Ratings
Parameter
Symbol
Conditions
[1]
Min
Max
Unit
Supply Voltage
VDD
-0.3
3.6
V
Interface Voltage
VIN
-0.3
VDD + 0.3
V
Junction Temperature
TJ
-40
125
℃
Storage Temperature
TSTG
-50
150
℃
Soldering Temperature
TSDR
255
℃
-2
2
kV
-100
100
mA
Lasts at least 30 seconds
ESD Rating
Human Body Model (HBM)
Latch-up Current
@ 85 ℃
Note:
[1]. Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Caution! ESD sensitive device. Precaution should be used when handling the device in order
to prevent permanent damage.
Rev 1.2 | Page 5/25
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CMT2110/17A
1.3 Transmitter Specifications
Table 5. Transmitter Specifications
Parameter
Frequency Range[1]
Synthesizer Frequency
Resolution
Symbol
FRF
FRES
Conditions
Min
Typ
Max
Unit
CMT2110A
240
480
MHz
CMT2117A
240
960
MHz
FRF ≤ 480 MHz
198
398
Hz
Maximum Output Power
POUT(Max)
+13
dBm
Minimum Output Power
POUT(Min)
-10
dBm
Output Power Step Size
PSTEP
PA Ramping Time[2]
tRAMP
Current Consumption
@ 433.92 MHz
Current Consumption
@ 868.35 MHz
Sleep Current
Symbol Rate
Frequency Tune Time
Phase Noise @ 433.92
MHz
Phase Noise @ 868.35
MHz
IDD433.92
IDD868.35
FRF > 480 MHz
Hz
1
0
6.7
mA
+10 dBm, 50% duty cycle
13.4
mA
+13 dBm, 50% duty cycle
17.4
mA
0 dBm, 50% duty cycle
8.0
mA
+10 dBm, 50% duty cycle
15.5
mA
+13 dBm, 50% duty cycle
19.9
mA
20
nA
SR
0.5
tTUNE
PN868.35
us
0 dBm, 50% duty cycle
ISLEEP
PN433.92
dB
1024
30
ksps
370
us
100 kHz offset from FRF
-81
dBc/Hz
200 kHz offset from FRF
-83
dBc/Hz
400 kHz offset from FRF
-92
dBc/Hz
600 kHz offset from FRF
-97
dBc/Hz
1.2 MHz offset from FRF
-107
dBc/Hz
100 kHz offset from FRF
-75
dBc/Hz
200 kHz offset from FRF
-77
dBc/Hz
400 kHz offset from FRF
-86
dBc/Hz
600 kHz offset from FRF
-91
dBc/Hz
1.2 MHz offset from FRF
-101
dBc/Hz
nd
Harmonics Output for
H2433.92
2
-52
dBm
433.92 MHz[3]
H3433.92
3rd harm @ 1301.76 MHz, +13 dBm POUT
-60
dBm
Harmonics Output for
H2868.35
2nd harm @ 1736.7 MHz, +13 dBm POUT
-67
dBm
-55
dBm
60
dB
[3]
868.35 MHz
H3868.35
harm @ 867.84 MHz, +13 dBm POUT
rd
3 harm @ 2605.05 MHz, +13 dBm POUT
OOK Extinction Ration
Notes:
[1]. The frequency range is continuous over the specified range.
[2]. 0 and 2n us, n = 0 to 10, when set to “0”, the PA output power will ramp to its configured value in the shortest possible
time.
[3]. The harmonics output is measured with the application shown as Figure 10.
Rev 1.2 | Page 6/25
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CMT2110/17A
1.4 Crystal Oscillator
Table 6. Crystal Oscillator Specifications
Parameter
[1]
Crystal Frequency
Symbol
Conditions
FXTAL
Min
Typ
Max
Unit
26
26
26
MHz
[2]
Crystal Tolerance
[3]
Load Capacitance
Crystal ESR
±20
CLOAD
12
Rm
[4]
XTAL Startup Time
tXTAL
ppm
20
pF
60
Ω
400
us
Notes:
[1]. The CMT2110/17A can directly work with external 26 MHz reference clock input to XTAL pin (a coupling capacitor is
required) with amplitude 0.3 to 0.7 Vpp.
[2]. This is the total tolerance including (1) initial tolerance, (2) crystal loading, (3) aging, and (4) temperature dependence.
The acceptable crystal tolerance depends on RF frequency and channel spacing/bandwidth.
[3]. The required crystal load capacitance is integrated on-chip to minimize the number of external components.
[4]. This parameter is to a large degree crystal dependent.
Rev 1.2 | Page 7/25
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CMT2110/17A
2. Pin Descriptions
XTAL
1
6
VDD
GND
2
5
RFO
DATA
3
4
CLK
Figure 2. CMT2110/17A Pin Assignments
Table 7. CMT2110/17A Pin Descriptions
Pin Number
Name
I/O
1
XTAL
I
2
GND
I
Descriptions
26 MHz single-ended crystal oscillator input or
External 26 MHz reference clock input
Ground
Data input to be transmitted or
Data pin to access the embedded EEPROM
3
DATA
IO
Pulled down internally to GND when configured as Transmission Enabled by
DATA Pin Falling Edge and used as input pin
Pulled up internally to VDD when configured as Transmission Enabled by DATA
Pin Rising Edge and used as input pin
Clock pin to control the device
Clock pin to access the embedded EEPROM
4
CLK
I
5
RFO
O
Power amplifier output
6
VDD
I
Power supply input
Pulled up internally to VDD
Rev 1.2 | Page 8/25
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CMT2110/17A
3. Typical Performance Characteristics
Phase Noise @ 868.35 MHz
Phase Noise
15
20
13.2 dBm
@ 433.92 MHz
10
-5
0
-10
Power (dBm)
Power (dBm)
13.0 dBm
@ 868.35 MHz
5
-20
-30
-15
-25
-35
-55.9 dBm
@ 869.55 MHz
-45
-40
-55.0 dBm
@ 435.12 MHz
-50
-55
-65
-60
432.42 432.72 433.02 433.32 433.62 433.92 434.22 434.52 434.82 435.12 435.42
866.85 867.1 867.35 867.6 867.85 868.1 868.35 868.6 868.85 869.1 869.35 869.6 869.85
Frequency (MHz) RBW = 10 kHz
Frequency (MHz) (RBW = 10 kHz)
Figure 3. Phase Noise, FRF = 433.92 MHz,
Figure 4. Phase Noise, FRF = 868.35 MHz,
POUT = +13 dBm, Unmodulated
POUT = +13 dBm, Unmodulated
Spectrum of Various PA Ramping Options
OOK Spectrum, SR = 9.6 ksps
10
10
-10
Power (dBm)
-10
Power (dBm)
128 us
64 us
32 us
16 us
8 us
4 us
0
0
-20
-20
-30
-30
-40
-40
-50
433.18
433.37
433.55
433.74
433.92
434.11
434.29
434.48
-50
434.66
433.17
433.37
433.57
433.77
Frequency (MHz)
434.17
434.37
434.57
Figure 5. OOK Spectrum, SR = 9.6 ksps,
Figure 6. Spectrum of PA Ramping,
POUT = +10 dBm, tRAMP = 32 us
SR = 9.6 ksps, POUT = +10 dBm
Spectrum of Various PA Ramping Options
POUT vs. VDD
10
14
-10
12
10
SR = 1.2 ksps
Power (dBm)
1024 us
512 us
256 us
128 us
64 us
32 us
0
Power (dBm)
433.97
Frequency (MHz)
-20
8
0 dBm
6
+10 dBm
4
+13 dBm
-30
2
-40
0
-2
-50
433.17
433.37
433.57
433.77
433.97
434.17
Frequency (MHz)
434.37
434.57
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Supply Voltage VDD (V)
Figure 8. Spectrum of PA Ramping,
Figure 7. Output Power vs. Supply
SR = 1.2 ksps, POUT = +10 dBm
Voltages, FRF = 433.92 MHz
Rev 1.2 | Page 9/25
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CMT2110/17A
4. Typical Application Schematics
4.1 Low-Cost Application Schematic
CMT2110/17A
X1
J1
1
VDD
XTAL
VDD
VDD
6
ANT
1
2
3
VDD
C0
DATA
L1
CLK
2
4
GND
U1
RFO
L2
5
C1
Note: Connector J1 is for
EEPROM Programming
DATA
3
DATA
CLK
4
C2
CLK
Figure 9. Low-Cost Application Schematic
Notes:
1.
Connector J1 is a must for the CMT2110/17A EEPROM access during development or manufacture.
2.
The general layout guidelines are listed below. For more design details, please refer to “AN101 CMT211xA Schematic and
PCB Layout Design Guideline”
Use as much continuous ground plane metallization as possible.
Use as many grounding vias (especially near to the GND pins) as possible to minimize series parasitic inductance
Avoid using long and/or thin transmission lines to connect the components.
Avoid placing the nearby inductors in the same orientation to reduce the coupling between them.
Place C0 as close to the CMT2110/17A as possible for better filtering.
between the ground pour and the GND pins.
3.
The table below shows the BOM of 433.92/868.35 MHz Low-Cost Application. For the BOM of 315/915 MHz application,
please refer to “AN101 CMT211xA Schematic and PCB Layout Design Guideline”.
Table 8. BOM of 433.92/868.35 MHz Low-Cost Application
Value
Designator
Descriptions
Unit
Manufacturer
-
-
CMOSTEK
868.35 MHz[1]
433.92 MHz
U1
CMT2110/17A, Low-Cost 240 – 960 MHz
OOK Transmitter
X1
±20 ppm, SMD32*25 mm crystal
26
MHz
EPSON
C0
±20%, 0402 X7R, 25 V
0.1
uF
Murata GRM15
C1
±5%, 0402 NP0, 50 V
82
82
pF
Murata GRM15
C2
±5%, 0402 NP0, 50 V
9
3.9
pF
Murata GRM15
L1
±5%, 0603 multi-layer chip inductor
180
100
nH
Murata LQG18
L2
±5%, 0603 multi-layer chip inductor
27
8.2
nH
Murata LQG18
Note:
[1]. The 868.35 MHz Application is for CMT2117A only.
Rev 1.2 | Page 10/25
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CMT2110/17A
4.2 FCC/ETSI Compliant Application Schematic
CMT2110/17A
X1
J1
1
2
3
4
1
VDD
XTAL
VDD
VDD VDD
6
ANT
VDD
C0
DATA
L1
L2
CLK
2
GND
U1
GND
RFO
5
L3
C1
Note: Connector J1 is for
EEPROM Programming
3
DATA
DATA
CLK
4
C2
C3
CLK
Figure 10. FCC/ETSI Compliant Application Schematic
Notes:
1.
Connector J1 is a must for the CMT2110/17A EEPROM access during development or manufacture.
2.
The general layout guidelines are listed below. For more design details, please refer to “AN101 CMT211xA Schematic and
PCB Layout Design Guideline”.
Use as much continuous ground plane metallization as possible.
Use as many grounding vias (especially near to the GND pins) as possible to minimize series parasitic inductance
Avoid using long and/or thin transmission lines to connect the components.
Avoid placing the nearby inductors in the same orientation to reduce the coupling between them.
Place C0 as close to the CMT2110/17A as possible for better filtering.
between the ground pour and the GND pins.
3.
The table below shows the BOM of 433.92/868.35 MHz FCC/ETSI Compliant Application. For the BOM of 315/915 MHz
application, please refer to “AN101 CMT211xA Schematic and PCB Layout Design Guideline”.
Table 9. BOM of 433.92/868.35 MHz FCC/ETSI Compliant Application
Value
Designator
Descriptions
Unit
Manufacturer
-
-
CMOSTEK
868.35 MHz[1]
433.92 MHz
U1
CMT2110/17A, Low-Cost 240 – 960 MHz
OOK Transmitter
X1
±20 ppm, SMD32*25 mm crystal
26
MHz
EPSON
C0
±20%, 0402 X7R, 25 V
0.1
uF
Murata GRM15
C1
±5%, 0402 NP0, 50 V
68
68
pF
Murata GRM15
C2
±5%, 0402 NP0, 50 V
15
9.1
pF
Murata GRM15
C3
±5%, 0402 NP0, 50 V
15
8.2
pF
Murata GRM15
L1
±5%, 0603 multi-layer chip inductor
180
100
nH
Murata LQG18
L2
±5%, 0603 multi-layer chip inductor
36
8.2
nH
Murata LQG18
L3
±5%, 0603 multi-layer chip inductor
18
8.2
nH
Murata LQG18
Note:
[1]. The 868.35 MHz Application is for CMT2117A only.
Rev 1.2 | Page 11/25
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CMT2110/17A
5. Functional Descriptions
VDD
POR
LDOs
Bandgap
GND
XOSC
XTAL
VCO
PFD/CP
Loop Filter
PA
RFO
Fractional-N
DIV
OOK Modulator
EEPROM
CLK
Ramp
Control
Interface and Digital Logic
DATA
Figure 11. CMT2110/17A Functional Block Diagram
5.1 Overview
The CMT2110/17A is an ultra low-cost, highly flexible, high performance, single-chip OOK transmitter for various 240 to 960
MHz wireless applications. The CMT2110A covers the frequency range from 240 to 480 MHz while the CMT2117 covers the
240 to 960 MHz frequency range. They are part of the CMOSTEK NextGenRFTM family, which includes a complete line of
transmitters, receivers and transceivers. The chip is optimized for the low system cost, low power consumption, battery
powered application with its highly integrated and low power design.
The functional block diagram of the CMT2110/17A is shown in the figure above. The CMT2110/17A is based on direct
synthesis of the RF frequency, and the frequency is generated by a low-noise fractional-N frequency synthesizer. It uses a
1-pin crystal oscillator circuit with the required crystal load capacitance integrated on-chip to minimize the number of external
components. Every analog block is calibrated on each Power-on Reset (POR) to the highly accurate reference voltage
internally. The calibration can help the chip to finely work under different temperatures and supply voltages. The
CMT2110/17A uses the DATA pin for the host MCU to send in the data. The input data will be modulated and sent out by a
highly efficient PA which output power can be configured from -10 to +13 dBm in 1 dB step size. RF Frequency, PA output
power and other product features can be programmed into the embedded EEPROM by the RFPDK and USB Programmer.
This saves the cost and simplifies the product development and manufacturing effort. Alternatively, in stock products of
433.92/868.35 MHz are available for immediate demands with no need of EEPROM programming. The CMT2110/17A
operates from 1.8 to 3.6 V so that it can finely work with most batteries to their useful power limits. Working under 3.3 V supply
voltage when transmitting signal at +10 dBm power, it only consumes 13.4 mA at 433.92 MHz and 15.5 mA at 868.35 MHz.
5.2 Modulation, Frequency and Symbol Rate
The CMT2110/17A supports OOK modulation with the symbol rate up to 30 ksps. The CMT2110A covers the frequency range
from 240 to 480 MHz, while the CMT2117A covers the frequency range from 240 to 960 MHz, including the license free ISM
frequency band around 315 MHz, 433.92 MHz, 868.35 MHz and 915 MHz. The device contains a high spectrum purity low
power fractional-N frequency synthesizer with output frequency resolution better than 198 Hz when the frequency is lower than
480 MHz, and the frequency resolution is 397 Hz when the frequency is higher than 480 MHz. See the table below for the
modulation, frequency and symbol rate specifications.
Rev 1.2 | Page 12/25
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CMT2110/17A
Table 10. Modulation, Frequency and Symbol Rate
Parameter
Value
Unit
OOK
-
Frequency (CMT2110A)
240 to 480
MHz
Frequency (CMT2117A)
240 to 960
MHz
198
Hz
Modulation
Frequency Resolution (FRF ≤ 480 MHz)
397
Hz
0.5 to 30
ksps
Frequency Resolution (FRF > 480 MHz)
Symbol Rate
5.3 Embedded EEPROM and RFPDK
The RFPDK (RF Products Development Kit) is a very user-friendly software tool delivered for the user configuring the
CMT2110/17A in the most intuitional way. The user only needs to fill in/select the proper value of each parameter and click the
“Burn” button to complete the chip configuration. No register access and control is required in the application program. See the
figure below for the accessing of the EEPROM and Table 11 for the summary of all the configurable parameters of the
CMT2110/17A in the RFPDK.
CMT2110/17A
RFPDK
EEPROM
CLK
Interface
DATA
CMOSTEK USB
Programmer
Figure 12. Accessing Embedded EEPROM
For more details of the CMOSTEK USB Programmer and the RFPDK, please refer to “AN103 CMT211xA-221xA One-Way RF
Link Development Kits Users Guide”. For the detail of CMT2110/17A configurations with the RFPDK, please refer to “AN102
CMT2110/17A Configuration Guideline”.
Table 11. Configurable Parameters in RFPDK
Category
RF Settings
Parameters
Frequency
To input a desired transmitting radio frequency in the
(CMT2110A)
range from 240 to 480 MHz. The step size is 0.001 MHz.
Frequency
To input a desired transmitting radio frequency in the
(CMT2117A)
range from 240 to 960 MHz. The step size is 0.001 MHz.
Tx Power
Xtal Cload
PA Ramping
Start by
Transmitting
Settings
Descriptions
Stop by
To select a proper transmitting output power from -10
dBm to +14 dBm, 1 dBm margin is given above +13 dBm.
On-chip XOSC load capacitance options: from 10 to 22
pF.
To control PA output power ramp up/down time, options
are 0 and 2n us (n from 0 to 10).
Start condition of a transmitting cycle, by Data Pin
Rising/Falling Edge.
Stop condition of a transmitting cycle, by Data Pin Holding
Low for 20 to 90 ms.
Rev 1.2 | Page 13/25
Default
Mode
433.92 MHz
868.35 MHz
Basic
Advanced
Basic
Advanced
Basic
+13 dBm
Advanced
Basic
15 pF
Advanced
0 us
Advanced
Data Pin
Rising Edge
Advanced
Data Pin
Holding Low
Advanced
for 20 ms
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CMT2110/17A
5.4 Power Amplifier
A highly efficient single-ended Power Amplifier (PA) is integrated in the CMT2110/17A to transmit the modulated signal out.
Depending on the application, the user can design a matching network for the PA to exhibit optimum efficiency at the desired
output power for a wide range of antennas, such as loop or monopole antenna. Typical application schematics and the
required BOM are shown in “Chapter 4 Typical Application Schematic”. For the schematic, layout guideline and the other
detailed information please refer to “AN101 CMT211xA Schematic and PCB Layout Design Guideline”.
The output power of the PA can be configured by the user within the range from -10 dBm to +13 dBm in 1 dB step size using
the CMOSTEK USB Programmer and RFPDK.
5.5 PA Ramping
When the PA is switched on or off quickly, its changing input impedance momentarily disturbs the VCO output frequency. This
process is called VCO pulling, and it manifests as spectral splatter or spurs in the output spectrum around the desired carrier
frequency. By gradually ramping the PA on and off, PA transient spurs are minimized. The CMT2110/17A has built-in PA
ramping configurability with options of 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 and 1024 us, as shown in Figure 13. When the
option is set to “0”, the PA output power will ramp up to its configured value in the shortest possible time. The ramp down time
is identical to the ramp up time in the same configuration.
CMOSTEK recommends that the maximum symbol rate should be no higher than 1/2 of the PA ramping “rate”, as shown in the
formula below:
SRMax ≤ 0.5 * (
1
)
tRAMP
In which the PA ramping “rate” is given by (1/tRAMP). In other words, by knowing the maximum symbol rate in the application,
the PA ramping time can be calculated by:
tRAMP ≤ 0.5 * (
1
)
SRMAX
The user can select one of the values of the tRAMP in the available options that meet the above requirement. If somehow the
tRAMP is set to be longer than “0.5 * (1/SRMax)”, it will possibly bring additional challenges to the OOK demodulation of the Rx
RFO Amplitude
device. For more detail of calculating tRAMP, please refer to “AN102 CMT2110/17A Configuration Guideline”.
0 us
1 us
2 us
4 us
8 us
512 us
1024 us
Data
Time
Logic 1
Logic 0
Time
Figure 13. PA Ramping Time
Rev 1.2 | Page 14/25
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CMT2110/17A
5.6 Crystal Oscillator and RCLK
The CMT2110/17A uses a 1-pin crystal oscillator circuit with the required crystal load capacitance integrated on-chip. Figure
14 shows the configuration of the XTAL circuitry and the crystal model. The recommended specification for the crystal is 26
MHz with ±20 ppm, ESR (Rm) < 60 Ω, load capacitance CLOAD ranging from 12 to 20 pF. To save the external load capacitors, a
set of variable load capacitors CL is built inside the CMT2110/17A to support the oscillation of the crystal.
The value of load capacitors is configurable with the CMOSTEK USB Programmer and RFPDK. To achieve the best
performance, the user only needs to input the desired value of the XTAL load capacitance CLOAD of the crystal (can be found in
the datasheet of the crystal) to the RFPDK, then finely tune the required XO load capacitance according to the actual XO
frequency. Please refer to “AN103 CMT211xA-221xA One-Way RF Link Development Kits Users Guide” for the method of
choosing the right value of CL.
Crystal Model
CMT2110/17A
CMT2110/17A
Cc
XTAL
RCLK
26 MHz
0. 3 – 0. 7 Vpp
Rm
Cm
XTAL
C0
CL
CL
Lm
Figure 14. XTAL Circuitry and Crystal Model
Figure 15. RCLK Circuitry
If a 26 MHz RCLK (reference clock) is available in the system, the user can directly use it to drive the CMT2110/17A by feeding
the clock into the chip via the XTAL pin. This further saves the system cost due to the removal of the crystal. A coupling
capacitor is required if the RCLK is used. The recommended amplitude of the RCLK is 0.3 to 0.7 Vpp on the XTAL pin. Also,
the user should set the internal load capacitor CL to its minimum value. See Figure 15 for the RCLK circuitry.
Rev 1.2 | Page 15/25
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CMT2110/17A
6. Working States and Transmission Control Interface
6.1 Working States
The CMT2110/17A has 4 different working states: SLEEP, XO-STARTUP, TUNE and TRANSMIT.
SLEEP
When the CMT2110/17A is in the SLEEP state, all the internal blocks are turned off and the current consumption is minimized
to 20 nA typically.
XO-STARTUP
After detecting a valid control signal on DATA pin, the CMT2110/17A goes into the XO-STARTUP state, and the internal XO
starts to work. The valid control signal can be a rising or falling edge on the DATA pin, which can be configured on the RFPDK.
The host MCU has to wait for the tXTAL to allow the XO to get stable. The tXTAL is to a large degree crystal dependent. A typical
value of tXTAL is provided in Table 12.
TUNE
The frequency synthesizer will tune the CMT2110/17A to the desired frequency in the time tTUNE. The PA can be turned on to
transmit the incoming data only after the TUNE state is done, before that the incoming data will not be transmitted. See Figure
16 and Figure 17 for the details.
TRANSMIT
The CMT2110/17A starts to modulate and transmit the data coming from the DATA pin. The transmission can be ended in 2
methods: firstly, driving the DATA pin low for tSTOP time, where the tSTOP can be configured from 20 to 90 ms on the RFPDK;
secondly, issuing SOFT_RST command over the two-wire interface, this will stop the transmission in 1 ms. See section 6.2.3
for details of the two-wire interface.
Table 12. Timing in Different Working States
Parameter
XTAL Startup Time
Symbol
[1]
Min
Typ
Max
Unit
tXTAL
400
us
Time to Tune to Desired Frequency
tTUNE
370
us
Hold Time After Rising Edge
tHOLD
10
tSTOP
20
[2]
Time to Stop The Transmission
ns
90
ms
Notes:
[1]. This parameter is to a large degree crystal dependent.
[2]. Configurable from 20 to 90 ms in 10 ms step size.
6.2 Transmission Control Interface
The CMT2110/17A uses the DATA pin for the host MCU to send in data for modulation and transmission. The DATA pin can be
used as pin for EEPROM programming, data transmission, as well as controlling the transmission. The transmission can be
started by detecting rising or falling edge on the DATA pin, and stopped by driving the DATA pin low for tSTOP as shown in the
table above. Besides communicating over the DATA pin, the host MCU can also communicate with the device over the
two-wire interface, so that the transmission is more robust, and consumes less current.
Please note that the user is recommended to use the Tx Enabled by DATA pin Rising Edge, which is described in Section
6.2.1.
Rev 1.2 | Page 16/25
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CMT2110/17A
6.2.1 Tx Enabled by DATA Pin Rising Edge
As shown in the Figure 16, once the CMT2110/17A detects a rising edge on the DATA pin, it goes into the XO-STARTUP state.
The user has to pull the DATA pin high for at least 10 ns (tHOLD) after detecting the rising edge, as well as wait for the sum of
tXTAL and tTUNE before sending any useful information (data to be transmitted) into the chip on the DATA pin. The logic state of
the DATA pin is “Don't Care” from the end of tHOLD till the end of tTUNE. In the TRANSMIT state, PA sends out the input data after
they are modulated. The user has to pull the DATA pin low for tSTOP in order to end the transmission.
SLEEP
XO-STARTUP TUNE
SLEEP
TRANSMIT
STATE
tXTAL
Rising Edge
DATA pin
0
tTUNE
Don’t Care
1
tSTOP
Valid Transmitted Data
0
tHOLD
PA out
RF Signals
Figure 16. Transmission Enabled by DATA Pin Rising Edge
6.2.2 Tx Enabled by DATA Pin Falling Edge
As shown in the Figure 17, once the CMT2110/17A detects a falling edge on the DATA pin, it goes into XO-STARTUP state and
the XO starts to work. During the XO-STARTUP state, the DATA pin needs to be pulled low. After the XO is settled, the
CMT2110/17A goes to the TUNE state. The logic state of the DATA pin is “Don't Care” during the TUNE state. In the
TRANSMIT state, PA sends out the input data after they are modulated. The user has to pull the DATA pin low for tSTOP in order
to end the transmission. Before starting the next transmit cycle, the user has to pull the DATA pin back to high.
SLEEP
SLEEP
TRANSMIT
XO-STARTUP TUNE
STATE
Falling Edge
DATA pin
1
PA out
tXTAL
tTUNE
0
Don’t Care
tSTOP
Valid Transmitted Data
0
1
RF Signals
Figure 17. Transmission Enabled by DATA Pin Falling Edge
6.2.3 Two-wire Interface
For power-saving and reliable transmission purposes, the CMT2110/17A is recommended to communicate with the host MCU
over a two-wire interface (TWI): DATA and CLK. The TWI is designed to operate at a maximum of 1 MHz. The timing
requirement and data transmission control through the TWI are shown in this section.
Rev 1.2 | Page 17/25
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CMT2110/17A
Table 13. TWI Requirements
Parameter
Symbol
Digital Input Level High
Digital Input Level Low
Conditions
Min
VIH
Typ
Max
0.8
Unit
VDD
VIL
0.2
VDD
1,000
kHz
CLK Frequency
FCLK
10
CLK High Time
tCH
500
ns
CLK Low Time
tCL
500
ns
CLK delay time for the first falling edge of the
20
15,000
ns
15,000
ns
CLK Delay Time
tCD
DATA Delay Time
tDD
DATA Setup Time
tDS
From DATA change to CLK falling edge
20
ns
DATA Hold Time
tDH
From CLK falling edge to DATA change
200
ns
TWI_RST command, see Figure 20
The data delay time from the last CLK rising
edge of the TWI command to the time DATA
return to default state
CLK
tCH tCL
tDS tDH
DATA
Figure 18. Two-wire Interface Timing Diagram
Once the device is powered up, TWI_RST and SOFT_RST should be issued to make sure the device works in SLEEP state
robustly. On every transmission, TWI_RST and TWI_OFF should be issued before the transmission to make sure the TWI
circuit functions correctly. TWI_RST and SOFT_RST should be issued again after the transmission for the device going back to
SLEEP state reliably till the next transmission. The operation flow with TWI is shown as the figure below.
One Transmission Cycle
Reset TWI
(1) - TWI_RST
(2) - SOFT_RST
(1) - TWI_RST
(2) - TWI_OFF
TRANSMISSION
One Transmission Cycle
(1) - TWI_RST
(2) - SOFT_RST
(1) - TWI_RST
(2) - TWI_OFF
TRANSMISSION
(1) - TWI_RST
(2) - SOFT_RST
Figure 19. CMT2110/17A Operation Flow with TWI
Table 14. TWI Commands Descriptions
Command
Descriptions
Implemented by pulling the DATA pin low for 32 clock cycles and clocking in 0x8D00, 48 clock cycles in total.
It only resets the TWI circuit to make sure it functions correctly. The DATA pin cannot detect the
Rising/Falling edge to trigger transmission after this command, until the TWI_OFF command is issued.
TWI_RST
Notes:
1.
2.
Please ensure the DATA pin is firmly pulled low during the first 32 clock cycles.
When the device is configured as Transmission Enabled by DATA Pin Falling Edge, in order to issue
the TWI_RST command correctly, the first falling edge of the CLK should be sent tCD after the DATA
falling edge, which should be longer than the minimum DATA setup time 20 ns, and shorter than 15 us,
Rev 1.2 | Page 18/25
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CMT2110/17A
Command
Descriptions
as shown in Figure 20.
3.
When the device is configured as Transmission Enabled by DATA Pin Rising Edge, the default state of
the DATA is low, there is no tCD requirement, as shown in Figure 21.
Implemented by clocking in 0x8D02, 16 clock cycles in total.
TWI_OFF
It turns off the TWI circuit, and the DATA pin is able to detect the Rising/Falling edge to trigger transmission
after this command, till the TWI_RST command is issued. The command is shown as Figure 22.
Implemented by clocking in 0xBD01, 16 clock cycles in total.
SOFT_RST
It resets all the other circuits of the chip except the TWI circuit. This command will trigger internal calibration
for getting the optimal device performance. After issuing the SOFT_RST command, the host MCU should
wait 1 ms before sending in any new command. After that, the device goes to SLEEP state. The command is
shown as Figure 23.
32 clock cycles
CLK
16 clock cycles
…
…
tCD
1
DATA
tDD
0x8D00
0
1
Figure 20. TWI_RST Command When Transmission Enabled by DATA Pin Falling Edge
32 clock cycles
CLK
DATA
16 clock cycles
…
…
0
0x8D00
0
Figure 21. TWI_RST Command When Transmission Enabled by DATA Pin Rising Edge
16 clock cycles
CLK
DATA
16 clock cycles
…
CLK
tDD
0x8D02 (TWI_OFF)
Default
State
Figure 22. TWI_OFF Command
DATA
…
tDD
0xBD01 (SOFT_RST)
Default
State
Figure 23. SOFT_RST Command
The DATA is generated by the host MCU on the rising edge of CLK, and is sampled by the device on the falling edge. The CLK
should be pulled up by the host MCU during the TRANSMISSION shown in Figure 19. The TRANSMISSION process should
refer to Figure 16 or Figure 17 for its timing requirement, depending on the “Start By” setting configured on the RFPDK.
The device will go to SLEEP state by driving the DATA low for tSTOP, or issuing SOFT_RST command. A helpful practice for the
device to go to SLEEP is to issue TWI_RST and SOFT_RST commands right after the useful data is transmitted, instead of
waiting the tSTOP, this can save power significantly.
Rev 1.2 | Page 19/25
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CMT2110/17A
7. Ordering Information
Table 15. CMT2110/17A Ordering Information
Part Number
CMT2110A-ESR[1]
CMT2117A-ESR[1]
Descriptions
Low-Cost 240-480 MHz
OOK Transmitter
Low-Cost 240-960 MHz
OOK Transmitter
Package
Package
Type
Option
SOT23-6
Tape & Reel
SOT23-6
Tape & Reel
Operating
MOQ /
Condition
Multiple
1.8 to 3.6 V,
3,000
-40 to 85 ℃
1.8 to 3.6 V,
3,000
-40 to 85 ℃
Notes:
[1]. “E” stands for extended industrial product grade, which supports the temperature range from -40 to +85 ℃.
“S” stands for the package type of SOT23-6.
“R” stands for the tape and reel package option, the minimum order quantity (MOQ) for this option is 3,000 pieces.
The default frequency for CMT2110A-ESR is 433.92 MHz, for CMT2117A-ESR is 868.35 MHz, for the other settings,
please refer to the Table 11 of Page 13.
Visit www.cmostek.com/products to know more about the product and product line.
Contact sales@cmostek.com or your local sales representatives for more information.
Rev 1.2 | Page 20/25
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CMT2110/17A
8. Package Outline
The 6-pin SOT23-6 illustrates the package details for the CMT2110/17A. Table 16 lists the values for the dimensions shown in
the illustration.
e1
e
0.25
L
E1
E
c
b
θ
D
A
A2
A3
A1
Figure 24. 6-Pin SOT23-6
Table 16. 6-Pin SOT23-6 Package Dimensions
Symbol
Size (millimeters)
Min
Typ
Max
A
—
—
1.35
A1
0.04
—
0.15
A2
1.00
1.10
1.20
A3
0.55
0.65
0.75
b
0.38
—
0.48
C
0.08
—
0.20
D
2.72
2.92
3.12
E
2.60
2.80
3.00
E1
1.40
1.60
1.80
e
0.95 BSC
e1
1.90 BSC
L
0.30
—
0.60
θ
0
—
8°
Rev 1.2 | Page 21/25
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CMT2110/17A
9. Top Marking
9.1 CMT2110/17A Top Marking
6
5
4
6
5
4
0 A ① ② ③
7 A ① ② ③
1
1
2
3
2
3
Figure 25. CMT2110A (Left) and CMT2117A (Right) Top Marking
Table 17. CMT2110/17A Top Marking Explanation
Top Mark:
0A①②③ / 7A①②③
Mark Method:
Laser
Font Size:
0.6 mm, right-justified
1st letter:
nd
2
letter:
3rd – 5th letter:
0, represents CMT2110A
7, represents CMT2117A
A: represents revision A
①②③: Internal reference for data code tracking, assigned by the assembly house
Rev 1.2 | Page 22/25
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CMT2110/17A
10. Other Documentations
Table 18. Other Documentations for CMT2110/17A
Brief
AN101
AN102
AN103
Name
Descriptions
CMT211xA Schematic and PCB Layout
Design Guideline
design rules, RF matching network and other application
layout design related issues.
CMT2110/17A Configuration Guideline
CMT211xA-221xA One-Way RF Link
Development Kits Users Guide
Details of CMT2110/13/17/19A PCB schematic and layout
Details of configuring CMT2110/17A features on the RFPDK.
User’s Guides for CMT211xA and CMT221xA Development
Kits, including Evaluation Board and Evaluation Module,
CMOSTEK USB Programmer and the RFPDK.
Rev 1.2 | Page 23/25
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CMT2110/17A
11. Document Change List
Table 19. Document Change List
Rev. No.
Chapter
0.7
All
Initial released version
0
Add Ordering Information in first page
1
Update Table 5
3
Update the title of Figure8/9
4
Update the BOM of Typical Application Schematics
5
Update Section 5.3 Embedded EEPROM and RFPDK Add Section
0.8
Description of Changes
Date
2014-03-04
2014-04-05
5.5 PA Ramping
0.85
0.9
1.0
1.1
1.2
1
Update Table 5
3
Update Figure 4
0
Update ordering Information in first page
Update Description
5
Update 5.3, add Table 11
7
Update chapter 7. Ordering information
-
-
2014-04-08
2014-06-14
2014-06-30
All
Add product CMT2117A to the datasheet
6
Add Section 6.2.3
6
Update Section 6.2.3
Rev 1.2 | Page 24/25
2015-01-16
2015-01-23
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CMT2110/17A
12. Contact Information
Hope Microelectronics Co., Ltd
Address: 2/F,Building3,Pingshan Private Enterprise science and Technology Park,Xili Town,Nanshan District,Shenzhen,China
Tel: +86-755-82973805
Fax: +86-755-82973550
Email: sales@hoperf.com
hoperf@gmail.com
Website: http://www.hoperf.com
http://www.hoperf.cn
Copyright. CMOSTEK Microelectronics Co., Ltd. All rights are reserved.
The information furnished by CMOSTEK is believed to be accurate and reliable. However, no responsibility is assumed for
inaccuracies and specifications within this document are subject to change without notice. The material contained herein is
the exclusive property of CMOSTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior
written permission of CMOSTEK. CMOSTEK products are not authorized for use as critical components in life support
devices or systems without express written approval of CMOSTEK. The CMOSTEK logo is a registered trademark of
CMOSTEK Microelectronics Co., Ltd. All other names are the property of their respective owners.
Rev 1.2 | Page 25/25
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