74LV139
Dual 2-to-4 line decoder/demultiplexer
Rev. 04 — 13 December 2007
Product data sheet
1. General description
The 74LV139 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC139 and 74HCT139.
The 74LV139 is a dual 2-to-4 line decoder/demultiplexer. It has two independent
decoders, each accepting two binary weighted inputs (nA0 and nA1) and providing four
mutually exclusive outputs (nY0 to nY3) that are LOW when selected. Each decoder has
an active LOW input (nE). When nE is HIGH, every output is forced HIGH. The enable
input can be used as the data input for a 1-to-4 demultiplexer application.
2. Features
■
■
■
■
■
■
■
■
■
■
■
■
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 °C
Demultiplexing capability
Two independent 2-to-4 line decoders
Multifunction capability
Active LOW mutually exclusive outputs
ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LV139N
−40 °C to +125 °C
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
74LV139D
−40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74LV139
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
Table 1.
Ordering information …continued
Type number
Package
Temperature range
Name
Description
Version
74LV139DB
−40 °C to +125 °C
SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74LV139PW
−40 °C to +125 °C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74LV139BQ
−40 °C to +125 °C
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
SOT763-1
4. Functional diagram
1
1E
1Y0
2
3
1A0
1Y1
1A1
1Y2
1Y3
2Y0
14
13
2A0
2Y1
2A1
2Y2
2Y3
4
DX 0
0 1
G
3
1
2
2
5
0
3
6
1
3
7
5
6
7
2
3
1
X/Y 0
1
1
2
2
EN
3
4
5
6
7
12
11
DX 0
0 1
G
3
1
2
14
10
0
13
9
15
2E
15
4
3
12
11
10
9
(a)
mna779
14
13
15
X/Y 0
1
1
2
2
EN
3
(b)
12
11
10
9
mna781
a) demultiplexer
b) decoder
Fig 1. Logic symbol
Fig 2. IEC logic symbol
2
1A0
3
1A1
1
1E
14
2A0
13
2A1
DECODER
1Y0
4
1Y1
5
1Y2
6
1Y3
7
2Y0 12
2Y1 11
DECODER
2Y2 10
2Y3
15
9
2E
mna780
Fig 3. Functional diagram
74LV139_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 13 December 2007
2 of 16
74LV139
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
5. Pinning information
5.1 Pinning
1E
terminal 1
index area
16 VCC
74LV139
1
16 VCC
1A0
2
15 2E
1A0
2
15 2E
1A1
3
14 2A0
1A1
3
14 2A0
1Y0
4
13 2A1
1Y0
4
13 2A1
1Y1
5
12 2Y0
1Y2
6
1Y3
7
1
1E
1Y2
6
11 2Y1
1Y3
7
10 2Y2
GND
8
9
2Y3
VCC(1)
11 2Y1
10 2Y2
9
12 2Y0
2Y3
5
8
1Y1
GND
139
001aah107
Transparent top view
001aad029
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration DIP16, SO16 and (T)SSOP16
Fig 5. Pin configuration DHVQFN16
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1E
1
enable input (active LOW)
1A0
2
address input
1A1
3
address input
1Y0
4
output
1Y1
5
output
1Y2
6
output
1Y3
7
output
GND
8
ground (0 V)
2Y3
9
output
2Y2
10
output
2Y1
11
output
2Y0
12
output
2A0
14
address input
2A1
13
address input
2E
15
enable input (active LOW)
VCC
16
supply voltage
74LV139_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 13 December 2007
3 of 16
74LV139
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
6. Functional description
Table 3.
Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care
Input
Output
nE
nA0
nA1
H
X
X
L
L
L
L
H
L
L
L
L
H
nY0
nY1
nY2
nY3
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Max
Unit
−0.5
+7.0
V
-
±20
mA
-
±50
mA
-
±25
mA
input clamping current
VI < −0.5 V or VI > VCC + 0.5 V
[1]
IOK
output clamping current
VO < −0.5 V or VO > VCC + 0.5 V
[1]
IO
output current
VO = −0.5 V to (VCC + 0.5 V)
ICC
supply current
-
50
mA
IGND
ground current
−50
-
mA
Tstg
storage temperature
−65
+150
°C
Ptot
total power dissipation
IIK
[1]
Tamb = −40 °C to +125 °C
DIP16 package
[2]
-
750
mW
SO16 package
[3]
-
500
mW
(T)SSOP16 package
[4]
-
500
mW
DHVQFN16 package
[5]
-
500
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
Ptot derates linearly with 12 mW/K above 70 °C.
[3]
Ptot derates linearly with 8 mW/K above 70 °C.
[4]
Ptot derates linearly with 5.5 mW/K above 60 °C.
[5]
Ptot derates linearly with 4.5 mW/K above 60 °C.
74LV139_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 13 December 2007
4 of 16
74LV139
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
[1]
Min
Typ
Max
Unit
1.0
3.3
5.5
V
VI
input voltage
0
-
VCC
V
VO
output voltage
0
-
VCC
V
Tamb
ambient temperature
−40
+25
+125
°C
∆t/∆V
input transition rise and fall rate
VCC = 1.0 V to 2.0 V
-
-
500
ns/V
VCC = 2.0 V to 2.7 V
-
-
200
ns/V
VCC = 2.7 V to 3.6 V
-
-
100
ns/V
VCC = 3.6 V to 5.5 V
-
-
50
ns/V
[1]
The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIH
VIL
VOH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
Conditions
−40 °C to +85 °C
Min
Max
Min
Max
VCC = 1.2 V
0.9
-
-
0.9
-
V
VCC = 2.0 V
1.4
-
-
1.4
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
VCC = 4.5 V to 5.5 V
0.7VCC
-
-
0.7VCC
-
V
VCC = 1.2 V
-
-
0.3
-
0.3
V
VCC = 2.0 V
-
-
0.6
-
0.6
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VCC = 4.5 V to 5.5 V
-
-
0.3VCC
-
0.3VCC V
VI = VIH or VIL
IO = −100 µA; VCC = 1.2 V
-
1.2
-
-
-
V
IO = −100 µA; VCC = 2.0 V
1.8
2.0
-
1.8
-
V
IO = −100 µA; VCC = 2.7 V
2.5
2.7
-
2.5
-
V
IO = −100 µA; VCC = 3.0 V
2.8
3.0
-
2.8
-
V
IO = −100 µA; VCC = 4.5 V
4.3
4.5
-
4.3
-
V
IO = −6 mA; VCC = 3.0 V
2.4
2.82
-
2.2
-
V
IO = −12 mA; VCC = 4.5 V
3.6
4.2
-
3.5
-
V
74LV139_4
Product data sheet
−40 °C to +125 °C Unit
Typ[1]
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 13 December 2007
5 of 16
74LV139
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
Table 6.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOL
−40 °C to +85 °C
Conditions
LOW-level output voltage
Min
Typ[1]
−40 °C to +125 °C Unit
Max
Min
Max
VI = VIH or VIL
IO = 100 µA; VCC = 1.2 V
-
0
-
-
-
V
IO = 100 µA; VCC = 2.0 V
-
0
0.2
-
0.2
V
IO = 100 µA; VCC = 2.7 V
-
0
0.2
-
0.2
V
IO = 100 µA; VCC = 3.0 V
-
0
0.2
-
0.2
V
IO = 100 µA; VCC = 4.5 V
-
0
0.2
-
0.2
V
IO = 6 mA; VCC = 3.0 V
-
0.25
0.40
-
0.50
V
IO = 12 mA; VCC = 4.5 V
-
0.35
0.55
-
0.65
V
II
input leakage current
VI = VCC or GND;
VCC = 5.5 V
-
-
1.0
-
1.0
µA
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
20.0
-
160
µA
∆ICC
additional supply current
per input; VI = VCC − 0.6 V;
VCC = 2.7 V to 3.6 V
-
-
500
-
850
µA
CI
input capacitance
-
3.5
-
-
-
pF
[1]
Typical values are measured at Tamb = 25 °C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see Figure 8.
Symbol Parameter
tpd
propagation delay
−40 °C to +85 °C
Conditions
−40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
VCC = 1.2 V
-
70
-
-
-
ns
VCC = 2.0 V
-
24
31
-
39
ns
VCC = 2.7 V
-
18
23
-
29
ns
VCC = 3.0 V to 3.6 V; CL = 15 pF
[3]
-
11
-
-
-
ns
VCC = 3.0 V to 3.6 V
[3]
-
13
18
-
23
ns
-
-
15
-
19
ns
VCC = 1.2 V
-
60
-
-
-
ns
VCC = 2.0 V
-
20
27
-
34
ns
nAn to nYn; see Figure 6
[2]
VCC = 4.5 V to 5.5 V
nEn to Yn; see Figure 7
VCC = 2.7 V
-
15
20
-
25
ns
VCC = 3.0 V to 3.6 V; CL = 15 pF
[3]
-
10
-
-
-
ns
VCC = 3.0 V to 3.6 V
[3]
-
11
16
-
20
ns
-
-
13
-
16
ns
VCC = 4.5 V to 5.5 V
74LV139_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 13 December 2007
6 of 16
74LV139
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
Table 7.
Dynamic characteristics …continued
GND = 0 V; For test circuit see Figure 8.
Symbol Parameter
CPD
−40 °C to +85 °C
Conditions
power dissipation
capacitance
[4]
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
[1]
All typical values are measured at Tamb = 25 °C.
[2]
tpd is the same as tPLH and tPHL.
[3]
Typical values are measured at nominal supply voltage (VCC = 3.3 V).
[4]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
−40 °C to +125 °C
Min
Typ[1]
Max
Min
Max
-
42
-
-
-
Unit
pF
11. Waveforms
VI
VI
VM
nAn input
GND
GND
t PHL
t PLH
tPLH
tPHL
VOH
VOH
VM
nYn output
VM
nE input
VM
nYn output
VOL
VOL
mna782
Measurement points are given in Table 8.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that
occur with the output load.
VOL and VOH are typical voltage output levels that
occur with the output load.
Fig 6. Input (nAn) to output (nYn) propagation delays
Table 8.
mna783
Fig 7. Enable input (nE) to output (nYn) propagation
delays
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
< 2.7 V
0.5VCC
0.5VCC
2.7 V to 3.6 V
1.5 V
1.5 V
≥ 4.5 V
0.5VCC
0.5VCC
74LV139_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 13 December 2007
7 of 16
74LV139
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
VCC
PULSE
GENERATOR
VI
VO
D.U.T.
RT
CL
50 pF
RL
1 kΩ
001aaa663
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
Fig 8. Load circuit for switching times
Table 9.
Test data
Supply voltage
Input
VCC
VI
tr, tf
< 2.7 V
VCC
≤ 2.5 ns
2.7 V to 3.6 V
2.7 V
≤ 2.5 ns
≥ 4.5 V
VCC
≤ 2.5 ns
74LV139_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 13 December 2007
8 of 16
74LV139
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
12. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
ME
seating plane
D
A2
A
A1
L
c
e
Z
w M
b1
(e 1)
b
b2
MH
9
16
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
b2
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
0.76
inches
0.17
0.02
0.13
0.068
0.051
0.021
0.015
0.049
0.033
0.014
0.009
0.77
0.73
0.26
0.24
0.1
0.3
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
95-01-14
03-02-13
SOT38-4
Fig 9. Package outline SOT38-4 (DIP16)
74LV139_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 13 December 2007
9 of 16
74LV139
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 10. Package outline SOT109-1 (SO16)
74LV139_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 13 December 2007
10 of 16
74LV139
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
D
SOT338-1
E
A
X
c
y
HE
v M A
Z
9
16
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
8
1
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
1.00
0.55
8
o
0
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT338-1
REFERENCES
IEC
JEDEC
JEITA
MO-150
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 11. Package outline SOT338-1 (SSOP16)
74LV139_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 13 December 2007
11 of 16
74LV139
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 12. Package outline SOT403-1 (TSSOP16)
74LV139_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 13 December 2007
12 of 16
74LV139
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT763-1
16 terminals; body 2.5 x 3.5 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
7
y
y1 C
v M C A B
w M C
b
L
1
8
Eh
e
16
9
15
10
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
b
1
0.05
0.00
0.30
0.18
c
D (1)
Dh
E (1)
Eh
0.2
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
e
0.5
e1
L
v
w
y
y1
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT763-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 13. Package outline SOT763-1 (DHVQFN16)
74LV139_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 13 December 2007
13 of 16
74LV139
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LV139_4
20071213
Product data sheet
-
74LV139_3
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 3: DHVQFN16 package added.
Section 7: derating values added for DHVQFN16 package.
Section 12: outline drawing added for DHVQFN16 package.
74LV139_3
20030313
Product specification
-
74LV139_2
74LV139_2
19980428
Product specification
-
74LV139_1
74LV139_1
19970212
Product specification
-
-
74LV139_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 13 December 2007
14 of 16
74LV139
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74LV139_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 13 December 2007
15 of 16
74LV139
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 December 2007
Document identifier: 74LV139_4
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