74AUP2G57GU-Q100X

74AUP2G57-Q100 Low-power dual PCB configurable multiple function gate Rev. 1 — 8 November 2021 Product data sheet 1. General description The 74AUP2G57-Q100 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 0.8 V to 3.6 V High noise immunity ESD protection: • HBM JESD22-A114F exceeds 5000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101E exceeds 1000 V Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10% of VCC IOFF circuitry provides partial power-down mode operation 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74AUP2G57GU-Q100 -40 °C to +125 °C Name Description Version XQFN10 plastic, extremely thin quad flat package; no leads; SOT1160-1 10 terminals; body 1.40 × 1.80 × 0.50 mm 74AUP2G57-Q100 Nexperia Low-power dual PCB configurable multiple function gate 4. Marking Table 2. Marking Type number Marking code [1] 74AUP2G57GU-Q100 aC [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram nA nY nB nC Fig. 1. aaa-015371 Logic symbol (one gate) 6. Pinning information 6.1. Pinning 1A VCC 1Y 9 8 terminal 1 index area 10 74AUP2G57 6 2B 5 2 2A 1C 4 2C GND 7 3 1 2Y 1B Transparent top view aaa-015374 Fig. 2. Pin configuration SOT1160-1 (XQFN10) 6.2. Pin description Table 3. Pin description Symbol Pin Description 1A, 2A 10, 5 data input 1B, 2B 1, 6 data input 1C, 2C 2, 7 data input 1Y, 2Y 8, 3 data output GND 4 ground (0 V) VCC 9 supply voltage 74AUP2G57_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 November 2021 © Nexperia B.V. 2021. All rights reserved 2 / 15 74AUP2G57-Q100 Nexperia Low-power dual PCB configurable multiple function gate 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level. Output Input nC nB nA nY L L L H L L H L L H L H L H H L H L L L H L H L H H L H H H H H 7.1. Logic configurations Table 5. Function selection table Logic function Figure 2-input AND see Fig. 3 2-input AND with both inputs inverted see Fig. 6 2-input NAND with inverted input see Fig. 4 and Fig. 5 2-input OR with inverted input see Fig. 4 and Fig. 5 2-input NOR see Fig. 6 2-input NOR with both inputs inverted see Fig. 3 2-input XNOR see Fig. 7 Inverter see Fig. 8 Buffer see Fig. 9 nB nC VCC nY nB 1, 6 4 nB nC 5,10 nY 2, 7 nB nC nC 9 3, 8 VCC nY nB 1, 6 2, 7 4 nY nB nC 5, 10 nY 3, 8 2-input AND gate or 2-input NOR gate with both inputs inverted Fig. 4. 2-input NAND gate with input B inverted or 2-input OR gate with inverted C input VCC nA nC nY 1, 6 4 nA nC nY nA 5, 10 2, 7 VCC nA nC nC nY 1, 6 2, 7 4 9 3, 8 nA nC nY nY nA 2-input NAND gate with input C inverted or 2-input OR gate with inverted A input 74AUP2G57_Q100 Product data sheet nC 9 5, 10 3, 8 nY aaa-033890 aaa-033889 Fig. 5. nY aaa-033888 aaa-033887 Fig. 3. nC 9 Fig. 6. 2-input NOR gate or 2-input AND gate with both inputs inverted All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 November 2021 © Nexperia B.V. 2021. All rights reserved 3 / 15 74AUP2G57-Q100 Nexperia Low-power dual PCB configurable multiple function gate VCC VCC nB nC nB nY 1, 6 4 5, 10 2, 7 nC 1, 6 nA 9 3, 8 nY nY 2, 7 4 nA 5, 10 9 3, 8 aaa-033891 Fig. 7. nY aaa-033892 2-input XNOR gate Fig. 8. Inverter VCC nB nB nY 1, 6 4 5, 10 2, 7 9 3, 8 nY aaa-033893 Fig. 9. Buffer 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +4.6 V -50 - [1] -0.5 +4.6 -50 - [1] -0.5 +4.6 V - ±20 mA VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO < 0 V VO output voltage Active mode and Power-down mode IO output current VO = 0 V to VCC ICC supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 250 mW [1] [2] VI < 0 V Tamb = -40 °C to +125 °C [2] mA V mA The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT1160-1 (XQFN10) package: Ptot derates linearly with 7.1 mW/K above 115 °C. 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.8 3.6 V VI input voltage 0 3.6 V VO output voltage Active mode 0 VCC V Power-down mode; VCC = 0 V 0 3.6 V -40 +125 °C Tamb ambient temperature 74AUP2G57_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 November 2021 © Nexperia B.V. 2021. All rights reserved 4 / 15 74AUP2G57-Q100 Nexperia Low-power dual PCB configurable multiple function gate 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit Tamb = 25 °C VOH VOL HIGH-level output voltage LOW-level output voltage VI = VT+ or VTIO = -20 μA; VCC = 0.8 V to 3.6 V VCC - 0.1 - - V IO = -1.1 mA; VCC = 1.1 V 0.75 × VCC - - V IO = -1.7 mA; VCC = 1.4 V 1.11 - - V IO = -1.9 mA; VCC = 1.65 V 1.32 - - V IO = -2.3 mA; VCC = 2.3 V 2.05 - - V IO = -3.1 mA; VCC = 2.3 V 1.9 - - V IO = -2.7 mA; VCC = 3.0 V 2.72 - - V IO = -4.0 mA; VCC = 3.0 V 2.6 - - V IO = 20 μA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V VI = VT+ or VT- II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.1 μA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.2 μA ΔIOFF additional power-off VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V leakage current - - ±0.2 μA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 μA ΔICC additional supply current VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V - - 40 μA CI input capacitance VI = GND or VCC; VCC = 0 V to 3.6 V - 1.1 - pF CO output capacitance VO = GND; VCC = 0 V - 1.7 - pF 74AUP2G57_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 November 2021 © Nexperia B.V. 2021. All rights reserved 5 / 15 74AUP2G57-Q100 Nexperia Low-power dual PCB configurable multiple function gate Symbol Parameter Conditions Min Typ Max Unit IO = -20 μA; VCC = 0.8 V to 3.6 V VCC - 0.1 - - V IO = -1.1 mA; VCC = 1.1 V 0.7 × VCC - - V IO = -1.7 mA; VCC = 1.4 V 1.03 - - V IO = -1.9 mA; VCC = 1.65 V 1.30 - - V IO = -2.3 mA; VCC = 2.3 V 1.97 - - V IO = -3.1 mA; VCC = 2.3 V 1.85 - - V IO = -2.7 mA; VCC = 3.0 V 2.67 - - V IO = -4.0 mA; VCC = 3.0 V 2.55 - - V IO = 20 μA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.37 V IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V - - 0.45 V Tamb = -40 °C to +85 °C VOH VOL HIGH-level output voltage LOW-level output voltage VI = VT+ or VT- VI = VT+ or VT- II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.5 μA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.5 μA ΔIOFF additional power-off VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V leakage current - - ±0.6 μA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 μA ΔICC additional supply current VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V - - 50 μA 74AUP2G57_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 November 2021 © Nexperia B.V. 2021. All rights reserved 6 / 15 74AUP2G57-Q100 Nexperia Low-power dual PCB configurable multiple function gate Symbol Parameter Conditions Min Typ Max Unit IO = -20 μA; VCC = 0.8 V to 3.6 V VCC - 0.11 - - V IO = -1.1 mA; VCC = 1.1 V 0.6 × VCC - - V IO = -1.7 mA; VCC = 1.4 V 0.93 - - V IO = -1.9 mA; VCC = 1.65 V 1.17 - - V IO = -2.3 mA; VCC = 2.3 V 1.77 - - V IO = -3.1 mA; VCC = 2.3 V 1.67 - - V IO = -2.7 mA; VCC = 3.0 V 2.40 - - V IO = -4.0 mA; VCC = 3.0 V 2.30 - - V IO = 20 μA; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - IO = 1.7 mA; VCC = 1.4 V - - 0.41 V IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V - - 0.50 V Tamb = -40 °C to +125 °C VOH VOL HIGH-level output voltage LOW-level output voltage VI = VT+ or VT- VI = VT+ or VT0.33 × VCC V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.75 μA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.75 μA ΔIOFF additional power-off VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V leakage current - - ±0.75 μA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 μA ΔICC additional supply current VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V - - 75 μA 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit, see Fig. 11. Symbol Parameter Conditions 25 °C -40 °C to +85 °C Min Typ [1] Max -40 °C to +125 °C Min Max Min Max - Unit CL = 5 pF tpd propagation delay 74AUP2G57_Q100 Product data sheet nA, nB and nC to nY; see Fig. 10 VCC = 0.8 V [2] - 22.6 - - - - VCC = 1.1 V to 1.3 V 2.8 6.5 12.6 2.5 13.0 2.5 13.2 ns VCC = 1.4 V to 1.6 V 2.2 4.6 7.6 2.5 8.2 2.5 8.6 ns VCC = 1.65 V to 1.95 V 2.1 3.9 6.2 2.0 6.8 2.0 7.2 ns VCC = 2.3 V to 2.7 V 2.0 3.1 4.5 1.8 5.1 1.8 5.3 ns VCC = 3.0 V to 3.6 V 1.8 2.8 3.9 1.5 4.1 1.5 4.3 ns All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 November 2021 © ns Nexperia B.V. 2021. All rights reserved 7 / 15 74AUP2G57-Q100 Nexperia Low-power dual PCB configurable multiple function gate Symbol Parameter Conditions 25 °C -40 °C to +85 °C Min Typ [1] Max -40 °C to +125 °C Min Max Min Max - Unit CL = 10 pF tpd propagation delay nA, nB and nC to nY; see Fig. 10 [2] VCC = 0.8 V - 26.1 - - - - ns VCC = 1.1 V to 1.3 V 3.2 7.3 14.4 2.8 14.9 2.8 15.2 ns VCC = 1.4 V to 1.6 V 2.6 5.2 8.7 2.8 9.3 2.8 9.8 ns VCC = 1.65 V to 1.95 V 2.5 4.5 7.0 2.2 7.8 2.2 8.2 ns VCC = 2.3 V to 2.7 V 2.4 3.7 5.2 2.1 5.9 2.1 6.2 ns VCC = 3.0 V to 3.6 V 2.3 3.4 4.6 1.9 4.9 1.9 5.1 ns - ns CL = 15 pF tpd propagation delay nA, nB and nC to nY; see Fig. 10 [2] VCC = 0.8 V - 31.6 - - - - VCC = 1.1 V to 1.3 V 3.4 8.0 15.7 3.1 16.7 3.1 17.0 ns VCC = 1.4 V to 1.6 V 2.8 5.7 9.4 3.1 10.4 3.1 10.9 ns VCC = 1.65 V to 1.95 V 2.6 4.9 7.7 2.5 8.7 2.5 9.2 ns VCC = 2.3 V to 2.7 V 2.6 4.1 5.7 2.4 6.5 2.4 6.9 ns VCC = 3.0 V to 3.6 V 2.5 3.8 5.0 2.2 5.5 2.2 5.7 ns - 37.8 - - - - - ns VCC = 1.1 V to 1.3 V 4.6 10.4 20.9 3.9 21.8 3.9 22.3 ns VCC = 1.4 V to 1.6 V 3.6 7.4 12.2 3.8 13.4 3.8 14.1 ns VCC = 1.65 V to 1.95 V 3.5 6.2 9.9 3.1 11.1 3.1 11.8 ns VCC = 2.3 V to 2.7 V 3.4 5.2 7.4 3.1 8.3 3.1 8.8 ns VCC = 3.0 V to 3.6 V 3.2 4.9 6.6 2.8 7.0 2.8 7.4 ns VCC = 0.8 V - 2.6 - - - - - pF VCC = 1.1 V to 1.3 V - 2.8 - - - - - pF VCC = 1.4 V to 1.6 V - 2.9 - - - - - pF VCC = 1.65 V to 1.95 V - 3.1 - - - - - pF VCC = 2.3 V to 2.7 V - 3.7 - - - - - pF VCC = 3.0 V to 3.6 V - 4.3 - - - - - pF CL = 30 pF tpd propagation delay nA, nB and nC to nY; see Fig. 10 [2] VCC = 0.8 V CL = 5 pF, 10 pF, 15 pF and 30 pF CPD [1] [2] [3] [4] power dissipation capacitance fi = 1 MHz; VI = GND to VCC [3] [4] All typical values are measured at nominal VCC. tpd is the same as tPLH and tPHL. All specified values are the average typical values over all stated loads. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL × VCC × fo) = sum of the outputs. 74AUP2G57_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 November 2021 © Nexperia B.V. 2021. All rights reserved 8 / 15 74AUP2G57-Q100 Nexperia Low-power dual PCB configurable multiple function gate 11.1. Waveform and test circuit VI nA, nB, nC input VM VM GND tPHL tPLH VOH VM nY output VM VOL tPLH tPHL VOH nY output VM VM VOL aaa-015383 Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 10. Input nA, nB and nC to output nY propagation delay times Table 10. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 × VCC 0.5 × VCC VCC ≤ 3.0 ns VCC G VI DUT VEXT 5 kΩ VO RT CL RL 001aac521 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 11. Test circuit for measuring switching times Table 11. Test data Supply voltage Load VCC CL 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ [1] VEXT RL [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ open GND 2 × VCC For measuring enable and disable times, RL = 5 kΩ. For measuring propagation delays, set-up and hold times, and pulse width, RL = 1 MΩ. 74AUP2G57_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 November 2021 © Nexperia B.V. 2021. All rights reserved 9 / 15 74AUP2G57-Q100 Nexperia Low-power dual PCB configurable multiple function gate 12. Transfer characteristics Table 12. Transfer characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 11. Symbol Parameter VT+ VT- VH Conditions positive-going threshold voltage negative-going threshold voltage 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 0.8 V 0.30 - 0.60 0.30 0.60 0.30 0.62 V VCC = 1.1 V 0.53 - 0.90 0.53 0.90 0.53 0.92 V VCC = 1.4 V 0.74 - 1.11 0.74 1.11 0.74 1.13 V VCC = 1.65 V 0.91 - 1.29 0.91 1.29 0.91 1.31 V VCC = 2.3 V 1.37 - 1.77 1.37 1.77 1.37 1.80 V VCC = 3.0 V 1.88 - 2.29 1.88 2.29 1.88 2.32 V VCC = 0.8 V 0.10 - 0.60 0.10 0.60 0.10 0.60 V VCC = 1.1 V 0.26 - 0.65 0.26 0.65 0.26 0.65 V VCC = 1.4 V 0.39 - 0.75 0.39 0.75 0.39 0.75 V VCC = 1.65 V 0.47 - 0.84 0.47 0.84 0.47 0.84 V VCC = 2.3 V 0.69 - 1.04 0.69 1.04 0.69 1.04 V VCC = 3.0 V 0.88 - 1.24 0.88 1.24 0.88 1.24 V VCC = 0.8 V 0.07 - 0.50 0.07 0.50 0.07 0.50 V VCC = 1.1 V 0.08 - 0.46 0.08 0.46 0.08 0.46 V VCC = 1.4 V 0.18 - 0.56 0.18 0.56 0.18 0.56 V VCC = 1.65 V 0.27 - 0.66 0.27 0.66 0.27 0.66 V VCC = 2.3 V 0.53 - 0.92 0.53 0.92 0.53 0.92 V VCC = 3.0 V 0.79 - 1.31 0.79 1.31 0.79 1.31 V see Fig. 12 and Fig. 13 see Fig. 12 and Fig. 13 hysteresis voltage (VT+ - VT-); see Fig. 12, Fig. 13, Fig. 14 and Fig. 15 12.1. Waveform transfer characteristics VO VI VI VH VT- VT+ Fig. 12. Transfer characteristic 74AUP2G57_Q100 Product data sheet mna207 VT+ VH VT- VO mna208 VT+ and VT- limits at 70 % and 20 %. Fig. 13. Definition of VT+, VT-, and VH All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 November 2021 © Nexperia B.V. 2021. All rights reserved 10 / 15 74AUP2G57-Q100 Nexperia Low-power dual PCB configurable multiple function gate 001aad691 240 ICC (µA) 001aad692 1200 ICC (µA) 160 800 80 400 0 0 0.4 0.8 1.2 1.6 VI (V) 2.0 Fig. 14. Typical transfer characteristics; VCC = 1.8 V 74AUP2G57_Q100 Product data sheet 0 0 1.0 2.0 VI (V) 3.0 Fig. 15. Typical transfer characteristics; VCC = 3.0 V All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 November 2021 © Nexperia B.V. 2021. All rights reserved 11 / 15 74AUP2G57-Q100 Nexperia Low-power dual PCB configurable multiple function gate 13. Package outline XQFN10: plastic, extremely thin quad flat package; no leads; 10 terminals; body 1.40 x 1.80 x 0.50 mm SOT1160-1 X D B A terminal 1 index area E A A1 A3 detail X e1 e v w b 3 5 C C A B C y1 C y L 2 6 1 7 e2 terminal 1 index area 10 L1 8 0 1 Dimensions Unit(1) mm max nom min 2 mm scale A A1 0.5 0.05 A3 b 0.25 0.127 0.20 0.00 0.15 D E e e1 e2 1.5 1.4 1.3 1.9 1.8 1.7 0.4 0.8 0.4 L L1 0.45 0.55 0.40 0.50 0.35 0.45 v 0.1 w y y1 0.05 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT1160-1 --- --- --- sot1160-1_po European projection Issue date 09-12-28 09-12-29 Fig. 16. Package outline SOT1160-1 (XQFN10) 74AUP2G57_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 November 2021 © Nexperia B.V. 2021. All rights reserved 12 / 15 74AUP2G57-Q100 Nexperia Low-power dual PCB configurable multiple function gate 14. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model PCB Printed Circuit Board 15. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP2G57_Q100 v.1 20211108 Product data sheet - 74AUP2G57_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 November 2021 - © Nexperia B.V. 2021. All rights reserved 13 / 15 74AUP2G57-Q100 Nexperia Low-power dual PCB configurable multiple function gate equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 16. Legal information Data sheet status Document status [1][2] Product status [3] Definition Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Applications — Applications that are described herein for any of these products are for illustrative purposes only. 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In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or 74AUP2G57_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 November 2021 © Nexperia B.V. 2021. All rights reserved 14 / 15 74AUP2G57-Q100 Nexperia Low-power dual PCB configurable multiple function gate Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Marking.......................................................................... 2 5. Functional diagram.......................................................2 6. Pinning information......................................................2 6.1. Pinning.........................................................................2 6.2. Pin description............................................................. 2 7. Functional description................................................. 3 7.1. Logic configurations.....................................................3 8. Limiting values............................................................. 4 9. Recommended operating conditions..........................4 10. Static characteristics..................................................5 11. Dynamic characteristics.............................................7 11.1. Waveform and test circuit.......................................... 9 12. Transfer characteristics........................................... 10 12.1. Waveform transfer characteristics............................10 13. Package outline........................................................ 12 14. Abbreviations............................................................ 13 15. Revision history........................................................13 16. Legal information......................................................14 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 8 November 2021 74AUP2G57_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 November 2021 © Nexperia B.V. 2021. All rights reserved 15 / 15