74HC221N

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT221 Dual non-retriggerable monostable multivibrator with reset Product specification Supersedes data of April 1988 File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Dual non-retriggerable monostable multivibrator with reset 74HC/HCT221 jitter-free triggering from inputs with slow transition rates, providing the circuit with excellent noise immunity. FEATURES • Pulse width variance is typically less than ± 5% Once triggered, the outputs (nQ, nQ) are independent of further transitions of nA and nB inputs and are a function of the timing components. The output pulses can be terminated by the overriding active LOW reset inputs (nRD). Input pulses may be of any duration relative to the output pulse. • Pin-out identical to “123” • Overriding reset terminates output pulse • nB inputs have hysteresis for improved noise immunity • Output capability: standard (except for nREXT/CEXT) • ICC category: MSI Pulse width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications pulse stability will only be limited by the accuracy of the external timing components. GENERAL DESCRIPTION The 74HC/HCT221 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The output pulse width is defined by the following relationship: The 74HC/HCT221 are dual non-retriggerable monostable multivibrators. Each multivibrator features an active LOW-going edge input (nA) and an active HIGH-going edge input (nB), either of which can be used as an enable input. tW = CEXTREXTIn2 tW = 0.7CEXTREXT Pin assignments for the “221” are identical to those of the “123” so that the “221” can be substituted for those products in systems not using the retrigger by merely changing the value of REXT and/or CEXT. Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry for the nB inputs allow QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC propagation delay tPHL nA, nB, nRD to nQ, nQ tPLH nA, nB, nRD to nQ, nQ CL = 15 pF; VCC = 5 V; REXT = 5 kΩ; CEXT = 0 pF HCT 29 32 ns 35 36 ns CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package notes 1 and 2 90 96 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) + 0.33 × CEXT × VCC2 × fo + D × 28 × VCC where: fi = input frequency in MHz; fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CEXT = timing capacitance in pF; CL = output load capacitance in pF VCC = supply voltage in V; D = duty factor in % 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V December 1990 2 Philips Semiconductors Product specification Dual non-retriggerable monostable multivibrator with reset 74HC/HCT221 ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 9 1A, 2A trigger inputs (negative-edge triggered) 2, 10 1B, 2B trigger inputs (positive-edge triggered) 3, 11 1RD, 2RD direct reset inputs (active LOW) 4, 12 1Q, 2Q outputs (active LOW) 7 2REXT/CEXT external resistor/capacitor connection 8 GND ground (0 V) 13, 5 1Q, 2Q outputs (active HIGH) 14, 6 1CEXT, 2CEXT external capacitor connection 15 1REXT/CEXT external resistor/capacitor connection 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Dual non-retriggerable monostable multivibrator with reset 74HC/HCT221 FUNCTION TABLE INPUTS OUTPUTS nRD nA nB L X X nQ nQ L H (2) H (2) H (2) X H X L X X L L (2) H L ↑ H ↓ H ↑ L H (3) (3) Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH level ↓ = HIGH-to-LOW level = one HIGH-level output pulse = one LOW-level output pulse 2. If the monostable was triggered before this condition was established the pulse will continue as programmed. 3. For this combination the reset input must be LOW and the following sequence must be used: pin 1 (or 9) must be set HIGH or pin 2 (or 10) set LOW; then pin 1 (or 9) must be LOW and pin 2 (or 10) set HIGH. Now the reset input goes from LOW-to-HIGH and the device will be triggered. Fig.4 Functional diagram. December 1990 4 Philips Semiconductors Product specification Dual non-retriggerable monostable multivibrator with reset 74HC/HCT221 Fig.5 Logic diagram. Note It is recommended to ground pins 6 (2CEXT) and 14 (1CEXT) externally to pin 8 (GND). Fig.6 Timing component connections. December 1990 5 Philips Semiconductors Product specification Dual non-retriggerable monostable multivibrator with reset 74HC/HCT221 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard (except for nREXT/CEXT) ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 min typ max. min max. −40 to +125 min. UNIT VCC WAVEFORMS (V) max. tPLH propagation delay (trigger) nA, nB to nQ 72 26 21 220 44 37 275 55 47 330 66 56 ns 2.0 4.5 6.0 CEXT = 0 pF; REXT = 5 kΩ; Fig.10 tPLH propagation delay (trigger) nRD to nQ 80 29 23 245 49 42 305 61 52 370 74 63 ns 2.0 4.5 6.0 CEXT = 0 pF; REXT = 5 kΩ; Fig.10 tPHL propagation delay (trigger) nA, nB to nQ 58 21 17 180 36 31 225 45 38 270 54 46 ns 2.0 4.5 6.0 CEXT = 0 pF; REXT = 5 kΩ; Fig.10 tPHL propagation delay (trigger) nRD to nQ 63 23 18 195 39 33 245 49 42 295 59 50 ns 2.0 4.5 6,0 CEXT = 0 pF; REXT = 5 kΩ; Fig.10 tPLH propagation delay (reset) nRD to nQ 66 24 19 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 CEXT = 0 pF; REXT = 5 kΩ; Fig.11 tPLH propagation delay (reset) nRD to nQ 58 21 17 180 36 31 225 45 38 270 54 46 ns 2.0 4.5 6.0 CEXT = 0 pF; REXT = 5 kΩ; Fig.11 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.10 tW trigger pulse width nA = LOW 75 15 13 25 9 7 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.7 tW trigger pulse width nB = HIGH 90 18 15 30 11 9 115 23 20 135 27 23 ns 2.0 4.5 6.0 Fig.7 tW trigger pulse width nRD = LOW 75 15 13 25 9 7 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.8 tW output pulse width nQ = LOW nQ = HIGH 630 700 770 602 µs 5.0 CEXT = 100 nF; REXT = 10 kΩ; Fig.10 December 1990 6 798 595 805 Philips Semiconductors Product specification Dual non-retriggerable monostable multivibrator with reset 74HC/HCT221 Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 min typ max. min max. −40 to +125 min. UNIT VCC WAVEFORMS (V) max. tW output pulse width nQ or nQ 140 − − ns 2.0 4.5 6.0 CEXT = 28 nF; REXT = 2 kΩ; Fig.10 tW output pulse width nQ or nQ 1.5 − − µs 2.0 4.5 6.0 CEXT = 1 nF; REXT = 2 kΩ; Fig.10 tW output pulse width nQ or nQ 7 − − µs 2.0 4.5 6.0 CEXT = 1 nF; REXT = 10 kΩ; Fig.10 tW pulse width match between circuits in the package ±2 − − % 4.5 to 5.5 CEXT = 1000 pF; REXT = 10 kΩ trem removal time nRD to nA or nB 100 20 17 30 11 9 125 25 21 150 30 26 ns 2.0 4.5 6.0 Fig.9 REXT external timing resistor 10 2 − − kΩ 2.0 5.0 Fig.12 Fig.13 CEXT external timing capacitor no limits pF 2.0 5.0 Fig.12 Fig.13 December 1990 1000 − 1000 − 7 Philips Semiconductors Product specification Dual non-retriggerable monostable multivibrator with reset 74HC/HCT221 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard (except for nREXT/CEXT) ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT nB 0.30 nA 0.50 nRD 0.50 December 1990 8 Philips Semiconductors Product specification Dual non-retriggerable monostable multivibrator with reset 74HC/HCT221 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 −40 to +85 min typ max min max. −40 to +125 min. UNIT VCC (V) WAVEFORMS max. tPLH propagation delay (trigger) nA, nRD to nQ 30 50 63 75 ns 4.5 CEXT = 0 pF; REXT = 5 kΩ; Fig.10 tPLH propagation delay (trigger) nB to nQ 24 42 53 63 ns 4.5 CEXT = 0 pF; REXT = 5 kΩ; Fig.10 tPHL propagation delay (trigger) nA to nQ 26 44 55 66 ns 4.5 CEXT = 0 pF; REXT = 5 kΩ; Fig.10 tPHL propagation delay (trigger) nB to nQ 21 35 44 53 ns 4.5 CEXT = 0 pF; REXT = 5 kΩ; Fig.10 tPHL propagation delay (trigger) nRD to nQ 26 43 54 65 ns 4.5 CEXT = 0 pF; REXT = 5 kΩ; Fig.10 tPHL propagation delay (reset) nRD to nQ 26 43 54 65 ns 4.5 CEXT = 0 pF; REXT = 5 kΩ; Fig.11 tPLH propagation delay (reset) nRD to nQ 31 51 64 77 ns 4.5 CEXT = 0 pF; REXT = 5 kΩ; Fig.11 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.10 tW trigger pulse width nA = LOW 20 13 25 30 ns 4.5 Fig.10 tW trigger pulse width nB = HIGH 20 13 25 30 ns 4.5 Fig.10 tW pulse width nRD = LOW 22 13 28 33 ns 4.5 Fig.8 tW output pulse width nQ = LOW nQ = HIGH 630 700 770 602 µs 5.0 CEXT = 100 nF; REXT = 10 kΩ; Fig.10 tW trigger pulse width nQ or nQ 140 − − ns 4.5 CEXT = 28 pF; REXT = 2 kΩ; Fig.10 tW trigger pulse width nQ or nQ 1.5 − − µs 4.5 CEXT = 1 nF; REXT = 2 kΩ; Fig.10 December 1990 9 798 595 805 Philips Semiconductors Product specification Dual non-retriggerable monostable multivibrator with reset 74HC/HCT221 Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 −40 to +85 min typ max min max. min. UNIT VCC (V) WAVEFORMS max. 7 − − µs 4.5 CEXT = 1 nF; REXT = 10 kΩ; Fig.10 12 25 30 ns 4.5 Fig.9 − kΩ 5.0 Fig.13 pF 5.0 Fig.13 tW trigger pulse width nQ or nQ trem removal time nRD to nA or nB 20 REXT external timing resistor 2 CEXT external timing capacitor no limits December 1990 −40 to +125 1000 − 10 Philips Semiconductors Product specification Dual non-retriggerable monostable multivibrator with reset 74HC/HCT221 AC WAVEFORMS Fig.7 Output pulse control; nRD = HIGH. (1) HC : VM = VM = 50%; VI = GND to VCC. HCT : VM = VM = 1.3 V; VI = GND to 3 V. Fig.8 Fig.10 Waveforms showing the triggering of One Shot by input nA or input nB for one period (tW) and minimum pulse widths of the trigger inputs nA and nB. Output pulse control using reset input nRD; nA = LOW. (1) HC : VM = VM = 50%; VI = GND to VCC. HCT : VM = VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = VM = 50%; VI = GND to VCC. HCT : VM = VM = 1.3 V; VI = GND to 3 V. Fig.9 Fig.11 Waveforms showing the reset to nQ and nQ output propagation delays. Waveforms showing the removal times; nRD to nA or nB. December 1990 11 Philips Semiconductors Product specification Dual non-retriggerable monostable multivibrator with reset 74HC/HCT221 Fig.12 HC typical output pulse width as a function of timing capacitance (VCC = 2 V). December 1990 12 Philips Semiconductors Product specification Dual non-retriggerable monostable multivibrator with reset 74HC/HCT221 Fig.13 HC/HCT typical output pulse width as a function of timing capacitance (VCC = 4.5 V). December 1990 13 Philips Semiconductors Product specification Dual non-retriggerable monostable multivibrator with reset 74HC/HCT221 Fig.14 HC typical output pulse width as a function of timing capacitance (VCC = 6 V). December 1990 14 Philips Semiconductors Product specification Dual non-retriggerable monostable multivibrator with reset 74HC/HCT221 Fig.15 Typical output pulse width as a function of temperature; CX = 0.1 µF; RX = 10 KΩ; VCC = 5 V. Fig.16 k factor as a function of supply voltage; RX = 10 KΩ; Tamb = 25 °C. Power-down consideration PACKAGE OUTLINES A large capacitor (CX) may cause problems when powering-down the monostable due to the energy stored in this capacitor. When a system containing this device is powered-down or a rapid decrease of VCC to zero occurs, the monostable may substain damage, due to the capacitor discharging through the input protection diodes. To avoid this possibility, use a damping diode (DX) preferably a germanium or Schottky type diode able to withstand large current surges and connect as shown in Fig.17. See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.17 Power-down protection circuit. December 1990 15