74HC4015D,652

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4015 Dual 4-bit serial-in/parallel-out shift register Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015 The 74HC/HCT4015 are dual edge-triggered 4-bit static shift registers (serial-to-parallel converters). Each shift register has a serial data input (1D and 2D), a clock input (1CP and 2CP), four fully buffered parallel outputs (1Q0 to 1Q3 and 2Q0 to 2Q3) and an overriding asynchronous master reset (1MR and 2MR). Information present on nD is shifted to the first register position, and all data in the register is shifted one position to the right on the LOW-to-HIGH transition of nCP. A HIGH on nMR clears the register and forces nQ0 to nQ3 to LOW, independent of nCP and nD. FEATURES • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4015 are high-speed Si-gate CMOS devices and are pin compatible with the “4015” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC CL = 15 pF; VCC = 5 V 16 HCT tPHL/ tPLH propagation delay nCP to nQn fmax maximum clock frequency 110 74 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per register notes 1 and 2 35 40 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 18 ns Philips Semiconductors Product specification Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 5, 4, 3, 10 1Q0 to 1Q3 flip-flop outputs 6, 14 1MR, 2MR asynchronous master reset inputs (active HIGH) 7, 15 1D, 2D serial data inputs 8 GND ground (0 V) 9, 1 1CP, 2CP clock inputs (LOW-to-HIGH, edge-triggered) 13, 12, 11, 2 2Q0 to 2Q3 flip-flop outputs 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015 Fig.5 Fig.4 Functional diagram. FUNCTION TABLE INPUTS n 1 2 3 4 nCP nD OUTPUTS nMR nQ0 ↑ ↑ ↑ ↑ D1 D2 D3 D4 L L L L ↓ X L X X H nQ1 D1 D2 D3 D4 X D1 D2 D3 L L nQ2 X X D1 D2 nQ3 X X X D1 no change L L Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH clock transition ↓ = HIGH-to-LOW clock transition n = number of clock pulse transitions Dn = either HIGH or LOW APPLICATIONS • Serial-to-parallel converter • Buffer stores • General purpose register December 1990 4 Logic diagram (one 4-bit serial-in/parallel-out shift register). Philips Semiconductors Product specification Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. −40 to +85 typ. max. min. max. −40 to +125 min. UNIT VCC WAVEFORMS (V) max. tPHL/ tPLH propagation delay nCP to nQn 52 19 15 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 Fig.6 tPHL propagation delay nMR to nQn 44 16 13 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.6 tW clock pulse width HIGH or LOW 80 16 14 17 6 5 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.6 tW master reset pulse width HIGH 80 16 14 17 6 5 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.7 trem removal time nMR to nCP 60 12 10 17 6 5 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.7 tsu set-up time nD to nCP 60 12 10 8 3 2 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.8 th hold time nD to nCP 5 5 5 0 0 0 5 5 5 5 5 5 ns 2.0 4.5 6.0 Fig.8 fmax maximum clock pulse frequency 6.0 30 35 33 100 119 4.8 24 28 4.0 20 24 MHz 2.0 4.5 6.0 Fig.6 December 1990 5 Philips Semiconductors Product specification Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT nD nMR nCP 0.30 1.50 1.50 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 −40 to +85 −40 to +125 UNIT VCC (V) WAVEFORMS min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay nCP to nQn 21 35 44 53 ns 4.5 Fig.6 tPHL propagation delay nMR to nQn 18 35 44 53 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW 16 7 20 24 ns 4.5 Fig.6 tW master reset pulse width HIGH 16 5 20 24 ns 4.5 Fig.7 trem removal time nMR to nCP 20 10 25 30 ns 4.5 Fig.7 tsu set-up time nD to nCP 12 4 15 18 ns 4.5 Fig.8 th hold time nD to nCP 5 −2 5 5 ns 4.5 Fig.8 fmax maximum clock pulse frequency 30 67 24 20 MHz 4.5 Fig.6 December 1990 6 Philips Semiconductors Product specification Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the clock (nCP) to output (nQn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the master reset (nMR) pulse width, the master reset to output (nQn) propagation delay and the master reset to clock (nCP) removal time. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the data set-up and hold times for nD inputs. December 1990 7 Philips Semiconductors Product specification Dual 4-bit serial-in/parallel-out shift register PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 8 74HC/HCT4015 74HC/HCT4015 Packaging Information Type Number 74HC4015D 74HC4015D 74HC4015DB 74HC4015DB 74HC4015N 74HCT4015D 74HCT4015D 74HCT4015N Orderable Part Number 74HC4015D,653 74HC4015D,652 74HC4015DB,118 74HC4015DB,112 74HC4015N,652 74HCT4015D,118 74HCT4015D,112 74HCT4015N,112 Package Name SO16 SO16 SSOP16 SSOP16 DIP16 SO16 SO16 DIP16