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USB-QUAD08 Eight-channel Quadrature Encoder Input Device Specifications Document Revision 1.1 May 2012 © Copyright 2012 USB-QUAD08 Specifications All specifications are subject to change without notice. Typical for 25 °C unless otherwise specified. Specifications in italic text are guaranteed by design. Counter Table 1. Counter specifications Parameter Specification Counter type Counters Counter input modes Mode options Index options Resolution Quadrature mode input frequency Normal mode input frequency De-bounce times FPGA 8 (quadrature or normal) Quadrature (x1, x2, x4)/Totalize, Pulse width, Period Non-Recycle, Range Limit, Clear on Read, Modulo-N, Up/Down, Decrement Latch, Clear|Reload, Decrement, Gate; mode dependent. 16, 32 or 48-bit counters 10/5/2.5 MHz, max, in x1/x2/x4 10 MHz, max 16 steps from 500 ns to 25 ms; positive or negative edge sensitive; glitch detect mode or de-bounce mode; software-selectable. 48 MHz (24 MHz – 30 ppm with a 2xDLL (delay locked loop)) Internal or external scan pacer up to 8 MHz 20.83 ns; 208.3 ns; 2.083 µs; or 20.83 µs Time-base and accuracy Counter read pacer Period/pulse width resolution Input Table 2. Input specifications Parameter Specification Receiver type SN75ALS175 quad differential receiver Configuration 8 channels. Each channel consists of PhaseA input, PhaseB input and Index input; each input is selectable as single-ended or differential. Differential:  PhaseA, PhaseB and Index (+) inputs at the user connector are routed to the (+) inputs of differential receiver.  PhaseA, PhaseB and Index (–) inputs at the user connector are routed to the (–) inputs of the differential receiver. Single-ended:  PhaseA, PhaseB and Index (+) inputs at the user connector are routed to the (+) inputs of the differential receiver.  PhaseA, PhaseB and Index (–) inputs at the user connector are left floating. The (–) inputs of the differential receiver are routed to the +3 V reference. ±12 V ±12 V ±200 mV 50 mV, typ 12 kΩ, min ±14 V, max  Meets or exceeds ANSI EIA/TIA-422-B, EIA/TIA-423-B, RS-485.  Meets ITU recommendations V.10, V.11, X.26, X.27.  Designed for multipoint busses on long lines and in noisy environments. Common mode input voltage range Differential input voltage range Input sensitivity Input hysteresis Input impedance Absolute maximum input voltage Miscellaneous 2 Specifications USB-QUAD08 Digital I/O – Timer outputs – Terminal count outputs Table 3. Output specifications Parameter Specification Number of I/O Configurable Input: Input characteristics Input high Input low Output: Output characteristics Output logic supply CEMF Supply (CLMP+) Output high Output low Output sink current 8 independent Timer outputs (DIO6, DIO7 only), Terminal count/Modulo, Input/Output (default) Output generation Asynchronous throughput Timer outputs: Number of channels Effective frequency range Weak 10 kΩ resistor pulled-up to 5V with protection diode (+V USB – diode drop). +2.0 V to 42.4 Vpk 50 VDC 0 V to 0.8 V Open-collector Darlington transistors with CEMF suppression diodes (ULN2803) User voltage supply up to 50 VDC (42.4 Vpk) for strong drive. Connect to logic supply positive terminal up to 50 VDC (42.4 Vpk) 2.0 VDC to 50 VDC (42.4 Vpk); dependent upon logic supply.