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JTAG HS1 Programming Cable for Xilinx FPGAs Revision: June 10, 2011 1300 Henley Court | Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview The JTAG-HS1 programming cable is a highspeed programming solution for Xilinx FPGAs. It is fully compatible will all Xilinx tools, and can be seamlessly driven from iMPACT, Chipscope, and EDK. The HS-1 attaches to target boards using Digilent’s 6-pin, 100-mil spaced programming header, or Xilinx’s 2x7, 2mm connector (using the included adaptor). The JTAG-HS1 is powered from a PC’s USB port, and will be recognized as a Digilent programming cable when connected to a PC, whether or not it is attached to the target board. A separate Vdd pin is provided on the HS1 to supply JTAG signal buffers. The high speed, 24mA, three-state buffers allow target boards to drive the HS1 with signal voltages from 1.8V to 5V, with bus speeds of up to 30MBit/sec. The HS1’s Vdd pin must be tied to the same voltage supply that drives the JTAG port on the FPGA. JTAG signals are held in high-impedance except when actively driven during programming, so the JTAG bus can be shared with other devices. The HS1 uses a standard Type-A to Micro-USB cable (included with the HS1) that attaches to the end of the module opposite the system board connector. The HS1 is small and light, allowing it to be held firmly in place by the system board connector. • Small, complete, all-in-one JTAG programming solution for Xilinx FPGAs • Separate Vref drives JTAG/SPI signal voltages; Vref can be any voltage between 1.8V and 5V. • High-Speed USB2 port that can drive JTAG/SPI bus at up to 30Mbit/sec • JTAG/SPI frequency settable by user • Compatible with all Xilinx tools • Uses micro-AB USB2 connector • SPI programming solution (modes 0 and 2 supported) • Fully supported by the Adept SDK, allowing custom JTAG/SPI applications to be created Micro-USB VIO: 5V to 1.8V USB2 Port VDD VIO GND GND TCK TCK TDO TDO TDI TDI TMS TMS JTAG-HS1 Doc: 502-205 FPGA Included Adaptor 1 2 3 4 5 6 Digilent JTAG Header Single row, 100-mil, 6-pin Xilinx JTAG Header Dual row, 2-mm, 14-pin page 1 of 3 Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. JTAG HS1 Reference Manual Software Support In addition to working seamlessly with all Xilinx tools, the HS1 is supported by Digilent’s Adept software and the Adept SDK (the SDK can be freely downloaded from Digilent’s website). Adept includes a full-featured programming environment, and a set of public APIs that allow user applications to directly drive the JTAG chain. Using the Adept SDK, custom applications can be created to drive JTAG ports on virtually any device. The HS1 also supports SPI modes 0 and 2. By using the API’s provided by the SDK applications can drive any SPI device supporting those modes. Please see the Adept SDK reference manual for more information. The HS1 is also supported by Digilent’s AVR programmer that can target any AVR device. Absolute Maximum Ratings Symbol Parameter Condition Min Max Unit Vdd Operating supply voltage -0.3 4.0 V Vref I/O reference/supply voltage -0.3 6 V VIO Signal Voltage -0.3 6 V IIK,IOK TMS, TCK, TDI, TDO DC Input/Output Diode Current IOUT DC Output Current TSTG Storage Temperature ESD Doc: 502-205 VIO < -0.3V -50 VIO > 6V +20 mA ±50 mA +120 ºC Human Body Model JESD22-A114 2000 V Charge Device Model JESD22-C101 500 V -20 page 2 of 3 JTAG HS1 Reference Manual DC Operating Characteristics Symbol Parameter Min Typ Max Unit Vdd Operating supply voltage 2.97 3.3 3.63 Volts Vref I/O reference/supply voltage 1.65 2.5/3.3 5.5 Volts TDO TMS, TCK, TDI Input High Voltage (VIH) 0.75 x Vref 5.5 Volts Input Low Voltage (VIL) 0 0.25 x Vref Volts Output High (VOH) 0.85 x Vdd 0.95 x Vdd Vdd Volts Output Low (VOL) 0 0.05 x Vdd 0.15 x Vdd Volts AC Operating Characteristics HS1 JTAG/SPI signals are driven according to the timing diagram below. TCK frequencies from 30MHz to 8 KHz are supported, at integer divisions of 30MHz from 1 to 3750. Common frequencies include 30MHz, 15MHz, 10MHz, 7.5MHz, and 6HMz. Symbol Parameter TCK TCKH, TCKL TCD TSU THD TCK period TCLK pulse width TCLK to TMS, TDI TDO Setup time TDO Hold time Min Max 33ns 2.185ms 20ns 1.1ms 0 15ns 19ns 0 Design Notes The HS1 is designed to drive JTAG/SPI signals on target boards that have less than 100ohms of series resistance. Higher resistance may result in degraded operation. Doc: 502-205 page 3 of 3