HG24LC256M/TR

HG24LC128/256 Features  Wide voltage Operation  VCC = 1.8V to 5.5V  Low-Power Devices (ISB = 3 µA @ 5.5V)   1MHZ(5V),400kHz(1.8V,2.7V,3.3V) Compatibility  Write Protect Pin for Hardware Data Protection Available Operating Ambient Temperature: 64-byte Page (128K/256K) Write Modes Partial -40°C to +85°C Internally Organized 16,384 X 8 Page Writes Allowed (128K), 32,768 X 8 (256K) Two-wire Serial  Self-timed Write Cycle(5ms max) High-reliability Interface  Endurance: 1 Million Write Cycles Schmitt Trigger, Filtered Inputs for Noise  Data Retention: 100 Years Suppression Bidirectional Data Transfer  8-lead PDIP, 8-lead JEDEC SOIC and 8-lead Protocol MSOP Packages ORDERINGINFORMATION DEVICE Package Type MARKING Packing Packing Qty HG24LC128N DIP8 24LC128 TUBE 2000/box HG24LC256N DIP8 24LC256 TUBE 2000/box HG24LC128M/TR SOP8 24LC128 REEL 2500/reel HG24LC256M/TR SOP8 24LC256 REEL 2500/reel HG24LC128MM/TR MSOP8 24LC128 REEL 3000/reel HG24LC256MM/TR MSOP8 24LC256 REEL 3000/reel General Description The HG24LC128 / 256 provides 131,072/262,144 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as4096 words of 8 bits each The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The HG24LC128 / 256 is available in space-saving 8-lead DIP, 8-lead SOP8 and 8-lead MSOP packages and is accessed via a Two-wire serial interface. Pin Configuration DIP8/SOP8/MSOP8 http://www.hgsemi.com.cn 1 / 13 2022 JUNE HG24LC128/256 Pin Descriptions Pin Number Designation Type Name and Functions Address Inputs DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with other 24LCxx devices. 1–2 A0 – A1 I When the pins are hardwired, as many as four 128K/256K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). If the pins are left floating, the A2, A1 and A0 pins will be internally pulleddown to GND if the capacitive coupling to the circuit board VCC plane is 3 pF, recommends connecting the address pins to GND. Serial Data 5 SDA I/O& Open-drain SERIAL DATA (SDA):The SDA pin is bi-directional for serial data transfer. Thispin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices. Serial Clock Input 6 SCL I SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into eachEEPROM device and negative edge clock data out of each device. Write Protect WRITE PROTECT (WP):The write protect input, when connected to GND, allows normal write operations. When WP is connected high to VCC, all write operations to the memory are inhibited. If the pin is left 7 WP I floating, the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board VCCplane is 3 pF, recommends connecting the pin to GND. Switching WP to VCC prior to a write operation creates a software write protect function. The write protection feature is enabled and operates as shown in the following Table 1. 4 8 3 GND VCC NC P P NC Ground Power Supply No connect Table 1:Write Protect WP Pin Status: At VCC At GND http://www.hgsemi.com.cn Part of the Array Protected HG24LC128 HG24LC256 Full (128K) Array Full (256K) Array Normal Read/Write Operations 2 / 13 2022 JULY HG24LC128/256 Block Diagram Functional Description 1. Memory Organization HG24LC128, 128K SERIAL EEPROM: The 128K is internally organized as 256 pages of 64 bytes each. Random word addressing requires a 14 bi-t data word address. HG24LC256, 256K SERIAL EEPROM: The 256K is internally organized as 512 pages of 64 bytes each. Random word addressing requires a 15-bit data word address. 2. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see to Figure 1 on page 5). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see to Figure 2 on page 5). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 2 onpage 5). http://www.hgsemi.com.cn 3 / 13 2022 JULY HG24LC128/256 ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The HG24LC128 / 256 features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition. Figure 1.Data Validity Figure 2.Start and Stop Definition http://www.hgsemi.com.cn 4 / 13 2022 JULY HG24LC128/256 Figure 3. Output Acknowledge 3. Device Addressing The 128K/256K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see to Figure 4 on page 5). The device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices. The 128K/256K uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the chip will return to a standby state. NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins prevent small noise spikes from activating the device. DATA SECURITY: The HG24LC128 / 256 has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at VCC. Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 5 on page 8). PAGE WRITE: The 128K/256K devices are capable of 64-byte page writes. http://www.hgsemi.com.cn 5 / 13 2022 JULY HG24LC128/256 A page write is initiated the same as a byte write, but the microcontroller does not send a stopcondition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 6 on page 8). The data word address lower six (128K/256K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 64 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a “0”, allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to “1”. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the cur- rent page to the first byte of the same page. Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does generate a following stop condition (see Figure 7 on page 8). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 8 on page 8). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 9 on page 9) http://www.hgsemi.com.cn 6 / 13 2022 JULY HG24LC128/256 Figure 4.Device Address Figure 5.Byte Write Figure 6.Page Write Figure 7.Current Address Read http://www.hgsemi.com.cn 7 / 13 2022 JULY HG24LC128/256 Figure 8.Random Read Figure 9.Sequential Read Electrical Characteristics Absolute Maximum Stress Ratings Symbol Parameter VCC Supply Voltage VO Input / Output Voltage Value Unit +6.5 V GND-0.3 to VCC+0.3 V Tamb Operating Ambient Temperature -40to+85 °C Tstg Storage Temperature -55to125 °C *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. http://www.hgsemi.com.cn 8 / 13 2022 JULY HG24LC128/256 DC Electrical Characteristics Applicable over recommended operating range from: TA = –40°C to +85°C, VCC =+1.8V to +5.5V (unless otherwise noted) Parameter Symbol Min. Typ. Max. Unit Condition Supply Voltage VCC1 1.8 - 5.5 V Supply Voltage VCC2 2.5 - 5.5 V Supply Voltage VCC3 2.7 - 5.5 V Supply Voltage VCC4 4.5 - 5.5 V Supply Current VCC=5.0V ICC1 - 0.4 1.0 mA READ at 400 kHz Supply Current VCC=5.0V ICC2 - 2.0 3.0 mA WRITE at 400 kHz Supply Current VCC=1.8V ISB1 -0.6 1.0 VIN=VCC or VSS Supply Current VCC=2.5V ISB2 -1.0 2.0 VIN=VCC or VSS Supply Current VCC=2.7V ISB3 -1.0 2.0 VIN=VCC or VSS Supply Current VCC=5.0V ISB4 -1.0 3.0 VIN=VCC or VSS Input Leakage Current ILI - 0.10 3.0 VIN=VCC or VSS Output Leakage Current ILO - 0.05 3.0 VIN=VCC or VSS Input Low Level VIL -0.6 - VCC×0.3 V Input High Level VIH VCC×0.7 - VCC+0.5 V Output Low Level VCC=5.0V VOL3 - - 0.4V Output Low Level VCC=3.0V VOL2 - - 0.4 V Output Low Level VCC=1.8V VOL1 - - 0.2 V Pin Capacitance Applicable over recommended operating range from TA=25°C,f=1.0MHz,VCC=+1.8V Parameter Symbol Min. Typ. Max. Unit Condition Input/Output Capacitance(SDA) CI/O - - 8pF VI/O=0V Input Capacitance(A0,A1,A2,SCL) CIN - - 8pF VIN=0V AE Electrical Characteristics Applicable over recommended operating range from: TA = –40°C to +85°C, VCC =+1.8V to +5.5V,CL=1TTL Gate and 100pF(unless otherwise noted) Parameter Symbol Min. 1.8, 2.7, 5.0-volt Typ. Max. Units Clock Frequency, SCL fSCL - - 400 kHz Clock Pulse Width Low tLOW 1.2 - - µs Clock Pulse Width High tHIGH 0.6 - - µs Noise Suppression Time tI - - 50 ns tAA 0.1 - 0.9 µs Clock Low to Data Out Valid http://www.hgsemi.com.cn 9 / 13 2022 JULY HG24LC128/256 Time the bus must be free before a new transmission canstart tBUF 1.2 - - µs Start Hold Time tHD.STA 0.6 - - µs Start Setup Time tSU.STA 0.6 - - µs Data In Hold Time tHD.DAT 0 - - µs Data In Setup Time tSU.DAT 100 - - ns Inputs Rise Time tR - - 0.3 µs Inputs Fall Time tF - - 300 ns Stop Setup Time tSU.STO 0.6 - - µs 50 - - ns Data Out Hold Time tDH Write Cycle Time tWR - - 5 ms Endurance 1M - - Write Cycles 5.0V, 25 C, Byte Mode Bus Timing Figure 10.SCL: Serial Clock, SDA: Serial Data I/O Write Cycle Timing Figure 11.SCL: Serial Clock, SDA: Serial Data I/O Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. http://www.hgsemi.com.cn 10 / 13 2022 JULY HG24LC128/256 Physical Dimensions SOP-8L Q A C C1 B D A1 a 0.25 b Dimensions In Millimeters(SOP8L) A A1 B C C1 D Min： 1.35 0.05 4.90 5.80 3.80 0.40 0° 0.35 Max： 1.55 0.20 5.10 6.20 4.00 0.80 8° 0.45 Symbol： Q a b 1.27 BSC DIP-8L D1 L1 L E B d D A c a b Dimensions In Millimeters(DIP8L) A B D D1 E L L1 a b c Min： 6.10 9.00 8.40 7.42 3.10 0.50 3.00 1.50 0.85 0.40 Max： 6.68 9.50 9.00 7.82 3.55 0.70 3.60 1.55 0.90 0.50 Symbol： http://www.hgsemi.com.cn 11 / 13 d 2.54 BSC 2022 JULY HG24LC128/256 Physical Dimensions MSOP8 Q A C1 C B A1 D 0.20 b a Dimensions In Millimeters(MSOP8L) A A1 B C C1 D Min： 0.80 0.05 2.90 4.75 2.90 0.35 0° 0.25 Max： 0.90 0.20 3.10 5.05 3.10 0.75 8° 0.35 Symbol： http://www.hgsemi.com.cn 12 / 13 Q a b 0.65 BSC 2022 JULY HG24LC128/256 IMPORTANT STATEMENT: Huaguan Semiconductor Co,Ltd. reserves the right to change the products and services provided without notice. Customers should obtain the latest relevant information before ordering, and verify the timeliness and accuracy of this information. Customers are responsible for complying with safety standards and taking safety measures when using our products for system design and machine manufacturing to avoid potential risks that may result in personal injury or property damage. Our products are not licensed for applications in life support, military, aerospace, etc., so we do not bear the onsequences of the application of these products in these fields. Huaguan Semiconductor Co,Ltd. the performance of the semiconductor products produced by the company can reach the performance indicators that can be applied at the time of sales. The use of testing and other quality control technologies is limite d to the quality assurance scope of Huaguan semiconductor. Not all parameters of each device need to be tested. The above documents are for reference only, and all are subject to the physical parameters. Our documentation is only permitted to be copied without any tampering with the content, so we do not accept any responsibility or liability for the altered documents. http://www.hgsemi.com.cn 13 / 13 2022 JULY