HG25Q32M/TR

HG25Q32 32 M BIT SPI NOR FLASH Features ● Serial Peripheral Interface(SPI) - Standard SPI: SCLK, /CS, SI, SO, /WP, /HOLD - Dual SPI: SCLK, /CS, IO0, IO1, /WP, /HOLD - Quad SPI: SCLK, /CS, IO0, IO1, IO2, IO3 ● Read - Normal Read (Serial): 50MHz clock rate - Fast Read (Serial): 108MHz clock rate - Dual/Quad (Multi-I/O) Read: 108MHz clock rate PIN1 SOP8 ● Program - Serial-input Page Program up to 256bytes - Program Suspend and Resume ● Erase PIN1 DIP8 - Block erase (64/32 KB) - Sector erase (4 KB) - Chip erase - Erase Suspend and Resume ● Software/Hardware Write Protection - 3x256-Byte Security Registers with OTP Lock - Enable/Disable protection with WP Pin - Write protect all/portion of memory via software - Top or Bottom, Sector or Block selection ● Single Supply Voltage - Full voltage range: 2.7~3.6V ● Temperature Range ● Program/Erase Speed - Page Program time: 0.7ms typical - Sector Erase time: 60ms typical - Block Erase time: 0.2/0.3s typical - Chip Erase time: 20s typical ● Flexible Architecture - Sector of 4K-byte - Block of 32/64K-byte - Commercial (0℃ to +70℃) - Industrial (-40℃ to +85℃) ● Low Power Consumption - 20mA maximum active current - 5uA maximum power down current ● Cycling Endurance/Data Retention - Typical 100k Program-Erase cycles on any sector - Typical 20-year data retention at +55℃ ORDERING INFORMATION DEVICE Package Type MARKING Packing Packing Qty HG25Q32N DIP8 25Q32 TUBE 2000/box HG25Q32M/TR SOP8 25Q32 REEL 2500/reel http://www.hgsemi.com.cn 1 2019 OCT V1.0 HG25Q32 1. Description The HG25Q32 is 32M-bit Serial Peripheral Interface(SPI) Flash memory, and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (/WP), and I/O3 (/HOLD). The Dual I/O data is transferred with speed of 216Mbits/s and the Quad I/O & Quad output data is transferred with speed of 432Mbits/s. The device uses a single low voltage power supply, ranging from 2.7 Volt to 3.6 Volt. Additionally, the device supports JEDEC standard manufacturer and device ID and three 256-bytes Security Registers. Figure 1. Logic diagram VCC SO SCLK SI /CS HG25Q32 /WP /HOLD VSS Figure 2. Pin Configuration SOP8L/DIP8L Top View http://www.hgsemi.com.cn /CS 1 8 VCC SO 2 7 /HOLD /WP 3 6 SCLK VSS 4 5 SI 2 2019 OCT V1.0 HG25Q32 2. Signal Description During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held High or Low (according to voltages of VIH, VOH, VIL or VOL, see Section 8.6, DC Electrical Characteristics on page 43). These signals are described next. 2.1 Input/Output Summary Table 1. Signal Names Pin Name I/O /CS I SO (IO1) I/O /WP (IO2) I/O VSS Description Chip Select Serial Output for single bit data Instructions. IO1 for Dual or Quad Instructions. Write Protect in single bit or Dual data Instructions. IO2 in Quad mode. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad Instructions. Ground SI (IO0) I/O SCLK I /HOLD (IO3) I/O VCC Serial Input for single bit data Instructions. IO0 for Dual or Quad Instructions. Serial Clock Hold (pause) serial transfer in single bit or Dual data Instructions. IO3 in Quad-I/O mode. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad Instructions. Core and I/O Power Supply 2.2 Chip Select (/CS) The chip select signal indicates when a instruction for the device is in process and the other signals are relevant for the memory device. When the /CS signal is at the logic high state, the device is not selected and all input signals are ignored and all output signals are high impedance. Unless an internal Program, Erase or Write Status Registers embedded operation is in progress, the device will be in the Standby Power mode. Driving the /CS input to logic low state enables the device, placing it in the Active Power mode. After Power Up, a falling edge on /CS is required prior to the start of any instruction. 2.3 Serial Clock (SCLK) This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data input are latched on the rising edge of the SCLK signal. Data output changes after the falling edge of SCLK. http://www.hgsemi.com.cn 3 2019 OCT V1.0 HG25Q32 2.4 Serial Input (SI)/IO0 This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to be programmed. Values are latched on the rising edge of serial SCK clock signal. SI becomes IO0 an input and output during Dual and Quad Instructions for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK). 2.5 Serial Data Output (SO)/IO1 This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial SCK clock signal. SO becomes IO1 an input and output during Dual and Quad Instructions for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK). 2.6 Write Protect (/WP)/IO2 When /WP is driven Low (VIL), while the Status Register Protect bits (SRP1 and SRP0) of the Status Registers (SR2[0] and SR1[7]) are set to 0 and 1 respectively, it is not possible to write to the Status Registers. This prevents any alteration of the Status Registers. As a consequence, all the data bytes in the memory area that are protected by the Block Protect, TB, SEC, and CMP bits in the status registers, are also hardware protected against data modification while /WP remains Low. The /WP function is not available when the Quad mode is enabled (QE) in Status Register 2 (SR2[1]=1). The /WP function is replaced by IO2 for input and output during Quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK). /WP has an internal pull-up resistance; when unconnected; /WP is at VIH and may be left unconnected in the host system if not used for Quad mode. 2.7 HOLD (/HOLD)/IO3 The /HOLD signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status register, programming, or erasing in progress. The operation of HOLD, need /CS keep low, and starts on falling edge of the /HOLD signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of /HOLD signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The Hold condition starts on the falling edge of the Hold (/HOLD) signal, provided that this coincides with SCK being at the logic low state. If the falling edge does not coincide with the SCK signal being at the logic low state, the Hold condition starts whenever the SCK signal reaches the logic low state. Taking the /HOLD signal to the logic low state does not terminate any Write, Program or Erase operation that is currently in progress. http://www.hgsemi.com.cn 4 2019 OCT V1.0 HG25Q32 2.8 VCC Power Supply VCC is the supply voltage. is the single voltage used for all device functions including read, program, and erase. 2.9 VSS Ground VSS is the reference for the VCC supply voltage. http://www.hgsemi.com.cn 5 2019 OCT V1.0 HG25Q32 3. Block/Sector Addresses Table 2. Block/Sector Addresses of HG25Q32 Memory Density Block(64k byte) Block(32k byte) Sector No. Sector Size(KB) Address range Sector 0 4 000000h-000FFFh ： ： ： Sector 7 4 007000h-007FFFh Sector 8 4 008000h-008FFFh ： 4 ： Sector 15 4 00F000h-00FFFFh Sector 16 4 010000h-010FFFh ： ： ： Sector 23 4 017000h-017FFFh Sector 24 4 018000h-018FFFh ： ： ： Sector 31 4 01F000h-01FFFFh ： ： ： Sector 992 4 3E0000h-3E0FFFh Half block 0 Block 0 Half block 1 Half block 2 Block 1 Half block 3 32Mbit ： ： Half block 124 Block 62 ： ： Sector 999 4 3E7000h-3E7FFFh Sector 1000 4 3E8000h-3E8FFFh ： ： ： Sector 1007 4 3EF000h-3EFFFFh Sector 1008 4 3F0000h-3F0FFFh ： ： ： Sector 1015 4 3F7000h-3F7FFFh Sector 1016 4 3F8000h-3F8FFFh ： ： ： Sector 1023 4 3FF000h-3FFFFFh Half block 125 Half block 126 Block 63 ： Half block 127 Notes: 1. Block = Uniform Block, and the size is 64K bytes. 2. Half block = Half Uniform Block, and the size is 32k bytes. 3. Sector = Uniform Sector, and the size is 4K bytes. http://www.hgsemi.com.cn 6 2019 OCT V1.0 HG25Q32 4. SPI Operation 4.1 Standard SPI Instructions The HG25Q32 features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (/CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. 4.2 Dual SPI Instructions The HG25Q32 supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH and BBH) instructions. These instructions allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI instruction the SI and SO pins become bidirectional I/O pins: IO0 and IO1. 4.3 Quad SPI Instructions The HG25Q32 supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O Fast Read” (6BH, EBH) instructions. These instructions allow data to be transferred t-o or from the device at four times the rate of the standard SPI. When using the Quad SPI instruction the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and /WP and /HOLD pins become IO2 and IO3. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. 5. Operation Features 5.1 Supply Voltage 5.1.1 Operating Supply Voltage Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see operating ranges of page 50). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). http://www.hgsemi.com.cn 7 2019 OCT V1.0 HG25Q32 5.1.2 Power-up Conditions When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (/CS) line is not allowed to float but should follow the VCC voltage, it is therefore recommended to connect the /CS line to VCC via a suitable pull-up resistor. In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (/CS). This ensures that Chip Select (/CS) must have been High, prior to going Low to start the first operation. 5.1.3 Device Reset In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power on reset (POR) circuit is included. At Power-up, the device does not respond to any instruction until VCC has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in operating ranges of page 50). When VCC has passed the POR threshold, the device is reset. 5.1.4 Power-down At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any instruction sent to it. During Power-down, the device must be deselected (Chip Select (/CS) should be allowed to follow the voltage applied on VCC) and in Standby Power mode (that is there should be no internal Write cycle in progress). 5.2 Active Power and Standby Power Modes When Chip Select (/CS) is Low, the device is selected, and in the Active Power mode. The device consumes ICC. When Chip Select (/CS) is High, the device is deselected. If a Write cycle is not currently in progress, the device then goes in to the Standby Power mode, and the device consumption drops to ICC1. 5.3 Hold Condition The Hold (/HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial Clock (SCLK) are Don’t Care. To enter the Hold condition, the device must be selected, with Chip Select (/CS) Low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (/HOLD) signal is driven Low at the same time as Serial Clock (SCLK) already being Low (as shown in Figure 4). http://www.hgsemi.com.cn 8 2019 OCT V1.0 HG25Q32 The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C) already being Low. Figure 4 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (SCLK) being Low. Figure 4. Hold condition activation /CS SCLK /HOLD HOLD HOLD 5.4 Status Register 5.4.1 Status Register Table See Table 3 and Table 4 for detail description of the Status Register bits. Status Register-2 (SR2) and Status Register-1 (SR1) can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled the state of write protection, Quad SPI setting, Security Register lock status, and Erase/Program Suspend status. Table 3. Status Register-2 (SR2) BIT Name 7 SUS 6 CMP 5 4 3 2 LB3 LB2 LB1 Reserved Function Suspend Status Complement Protect Security Register Lock Bits Reserved 1 QE Quad Enable 0 SRP1 Status Resister Protect 1 http://www.hgsemi.com.cn Default Value 0 0 0 0 0 0 0 0 Description 0 = Erase/Program not suspended 1 = Erase/Program suspended 0 = Normal Protection Map 1 = Inverted Protection Map OTP Lock Bits 3:1 for Security Registers 3:1 0 = Security Register not protected 1 = Security Register protected 0 = Quad Mode Not Enabled, the /WP pin and /HOLD are enabled. 1 = Quad Mode Enabled, the IO2 and IO3 pins are enabled, and /WP and /HOLD functions are disabled 0 = SRP0 selects whether /WP input has effect on protection of the status register 1 = SRP0 selects Power Supply Lock Down or OTP Lock Down mode 9 2019 OCT V1.0 HG25Q32 Table 4. Status Register-1 (SR1) BIT Name Function Default Value Description 7 SRP0 Status Resister Protect 0 0 0 = /WP input has no effect or Power Supply Lock Down mode 1 = /WP input can protect the Status Register or OTP Lock Down 6 SEC Sector/Block Protect 0 0 = BP2-BP0 protect 64KB blocks 1 = BP2-BP0 protect 4KB sectors 5 TB Top/Bottom Protect 0 0 = BP2-BP0 protect from the Top down 1 = BP2-BP0 protect from the Bottom up 4 3 2 BP2 BP1 BP0 Block Protect Bits 0 0 0 000b = No protection See Table 6 and Table 7 for protection ranges 1 WEL Write Enable Latch 0 0 = Not Write Enabled, no embedded operation can start 1 = Write Enabled, embedded operation can start 0 WIP Write in Progress Status 0 0 = Not Busy, no embedded operation in progress 1 = Busy, embedded operation in progress 5.4.2 The Status and Control Bits 5.4.2.1 WIP bit The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means the device is not in program/erase/write status register progress. 5.4.2.2 WEL bit The Write Enable Latch bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. 5.4.2.3 SEC, TB, BP2, BP1, BP0 bits The Block Protect (SEC, TB, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register instruction. When the Block Protect (SEC, TB, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table 6 and Table 7).becomes protected against http://www.hgsemi.com.cn 10 2019 OCT V1.0 HG25Q32 Page Program, Sector Erase and Block Erase instructions. The Block Protect (SEC, TB, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. 5.4.2.4 SRP1, SRP0 bits The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable protection. 5.4.2.5 QE bit The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the /WP pin and /HOLD pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the /WP or /HOLD pins directly to the power supply or ground). 5.4.2.6 LB3/LB2/LB1 bit The LB bit is a non-volatile One Time Program (OTP) bit in Status Register that provide the write protect control and status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1 individually using the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the 256byte Security Registers will become read-only permanently, LB3/2/1 for Security Registers 3:1. 5.4.2.7 CMP bit The CMP bit is a non-volatile Read/Write bit in the Status Register2 (bit6). It is used in conjunction the SEC-BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The default setting is CMP=0. 5.4.2.8 SUS bit The SUS bit is a read only bit in the status register2 (bit7) that is set to 1 after executing an Erase/Program Suspend (75H) instruction. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) instruction as well as a power-down, power-up cycle. http://www.hgsemi.com.cn 11 2019 OCT V1.0 HG25Q32 5.4.3 Status Register Protect Table Table 5. Status Register protect table SRP1 SRP0 /WP Status Register Software Protected Hardware Protected Hardware Unprotected 0 0 X 0 1 0 0 1 1 1 0 X Power Supply Lock-Down(1) 1 1 X One Time Program(2) Description The Status Register can be written to after a Write Enable instruction, WEL=1.(Factory Default) /WP=0, the Status Register locked and cannot be written. /WP=1, the Status Register is unlocked and can be written to after a Write Enable instruction, WEL=1. Status Register is protected and cannot be written to again until the next Power-Down, Power-Up cycle. Status Register is permanently protected and cannot be written to. Notes: 1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. http://www.hgsemi.com.cn 12 2019 OCT V1.0 HG25Q32 5.4.4 1. Write Protect Features Software Protection: The Block Protect (SEC, TB, BP2, BP1, BP0) bits define the section of the memory array that can be read but not change. 2. Hardware Protection: /WP going low to protected the BP0~SEC bits and SRP0~1 bits. 3. Deep Power-Down: In Deep Power-Down Mode, all instructions are ignored except the Release from deep Power-Down Mode instruction. 4. Write Enable: The Write Enable Latch (WEL) bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. 5.4.5 Status Register Memory Protection 5.4.5.1 Protect Table Table 6. BG25Q32A Status Register Memory Protection (CMP=0) Status Register Content SEC TB BP2 BP1 BP0 X X 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 X X 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 X 1 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 X 1 1 1 1 0 http://www.hgsemi.com.cn Blocks NONE 63 62 to 63 60 to 63 56 to 63 48 to 63 32 to 63 0 0 to 1 0 to 3 0 to 7 0 to 15 0 to 31 0 to 63 63 63 63 63 63 0 0 0 0 0 Memory Content Addresses Density NONE NONE 3F0000H-3FFFFFH 64KB 3E0000H-3FFFFFH 128KB 3C0000H-3FFFFFH 256KB 380000H-3FFFFFH 512KB 300000H-3FFFFFH 1MB 200000H-3FFFFFH 2MB 000000H-00FFFFH 64KB 000000H-01FFFFH 128KB 000000H-03FFFFH 256KB 000000H-07FFFFH 512KB 000000H-0FFFFFH 1MB 000000H-1FFFFFH 2MB 000000H-3FFFFFH 4MB 3FF000H-3FFFFFH 4KB 3FE000H-3FFFFFH 8KB 3FC000H-3FFFFFH 16KB 3F8000H-3FFFFFH 32KB 3F8000H-3FFFFFH 32KB 000000H-000FFFH 4KB 000000H-001FFFH 8KB 000000H-003FFFH 16KB 000000H-007FFFH 32KB 000000H-007FFFH 32KB 13 Portion NONE Upper 1/64 Upper 1/32 Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 Lower 1/64 Lower 1/32 Lower 1/16 Lower 1/8 Lower 1/4 Lower 1/2 ALL Top Block Top Block Top Block Top Block Top Block Bottom Block Bottom Block Bottom Block Bottom Block Bottom Block 2019 OCT V1.0 HG25Q32 Table 7. HG25Q32 Status Register Memory Protection (CMP=1) Status Register Content SEC TB BP2 BP1 BP0 Blocks X X 0 0 0 ALL 0 0 0 0 1 0 to 62 0 0 0 1 0 0 to 61 0 0 0 1 1 0 to 59 0 0 1 0 0 0 to 55 0 0 1 0 1 0 to 47 0 0 1 1 0 0 to 31 0 1 0 0 1 1 to 63 0 1 0 1 0 2 to 63 0 1 0 1 1 4 to 63 0 1 1 0 0 8 to 63 0 1 1 0 1 16 to 63 0 1 1 1 0 32 to 63 X X 1 1 1 NONE 1 0 0 0 1 0 to 63 1 0 0 1 0 0 to 63 1 0 0 1 1 0 to 63 1 0 1 0 X 0 to 63 1 0 1 1 0 0 to 63 1 1 0 0 1 0 to 63 1 1 0 1 0 0 to 63 1 1 0 1 1 0 to 63 1 1 1 0 X 0 to 63 1 1 1 1 0 0 to 63 http://www.hgsemi.com.cn Memory Content Addresses Density 000000H-3FFFFFH 4MB 000000H-3EFFFFH 4032KB 000000H-3DFFFFH 3968KB 000000H-3BFFFFH 3840KB 000000H-37FFFFH 3584KB 000000H-2FFFFFH 3MB 000000H-1FFFFFH 2MB 010000H-3FFFFFH 4032KB 020000H-3FFFFFH 3968KB 040000H-3FFFFFH 3840KB 080000H-3FFFFFH 3584KB 100000H-3FFFFFH 3MB 200000H-3FFFFFH 2MB NONE NONE 000000H-3FEFFFH 4092KB 000000H-3FDFFFH 4088KB 000000H-3FBFFFH 4080KB 000000H-3F7FFFH 4064KB 000000H-3F7FFFH 4064KB 001000H-3FFFFFH 4092KB 002000H-3FFFFFH 4088KB 004000H-3FFFFFH 4080KB 008000H-3FFFFFH 4064KB 008000H-3FFFFFH 4064KB 14 Portion ALL Lower 63/64 Lower 31/32 Lower 15/16 Lower r 7/8 Lower 3/4 Lower 1/2 Upper 63/64 Upper 31/32 Upper 15/16 Upper 7/8 Upper 3/4 Upper 1/2 NONE L-1023/1024 L-511/512 L-255/256 L-127/128 L-127/128 U-1023/1024 U-511/512 U-255/256 U-127/128 U-127/128 2019 OCT V1.0 HG25Q32 6. Device Identification Three legacy Instructions are supported to access device identification that can indicate the manufacturer, device type, and capacity (density). The returned data bytes provide the information as shown in the below table. Table 8. HG25Q32 ID Definition table Operation Code M7-M0 ID15-ID8 ID7-ID0 9FH 90H ABH E0 E0 40 16 15 15 http://www.hgsemi.com.cn 15 2019 OCT V1.0 HG25Q32 7. Instructions Description All instructions, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after /CS is driven low. Then, the one byte instruction code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK. See Table 9, every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. /CS must be driven high after the last bit of the instruction sequence has been shifted in. For the instruction of Read, Fast Read, Read Status Register or Release from Deep Power Down, and Read Device ID, the shifted-in instruction sequence is followed by a data out sequence. /CS can be driven high after any bit of the data-out sequence is being shifted out. For the instruction of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down instruction, /CS must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is /CS must driven high when the number of clock pulses after /CS being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. http://www.hgsemi.com.cn 16 2019 OCT V1.0 HG25Q32 Table 9. Instruction Set Table Instruction Name Write Enable Write Disable Read Status Register-1 Read Status Register-2 Write Enable for Volatile Status Register Write Status Register Read Data Fast Read Dual Output Fast Read Byte 1 06H 04H 05H Byte 2 (S7-S0) 35H (S15-S8) Byte 3 Byte 4 Byte 5 Byte 6 A7-A0 A7-A0 A7-A0 (D7-D0) dummy dummy Next byte (D7-D0) (D7-D0)(1) dummy (D7-D0)(3) Next byte 50H 01H 03H 0BH 3BH (S7-S0) A23-A16 A23-A16 A23-A16 (S15-S8) A15-A8 A15-A8 A15-A8 Dual I/O Fast Read BBH A23-A8(2) (D7-D0)(1) Quad Output Fast Read 6BH A23-A16 A7-A0 M7-M0(2) A15-A8 Quad I/O Fast Read EBH dummy (D7-D0)(5) Continuous Read Reset Page Program Sector Erase Block Erase(32K) Block Erase(64K) Chip Erase Program/Erase Suspend Program/Erase Resume Deep Power-Down Release From Deep Power-Down, And Read Device ID Release From Deep Power-Down Manufacturer/ Device ID JEDEC ID Erase Security Registers(6) Program Security Registers(6) Read Security Registers(6) FFH A23-A16 A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 (D7-D0) dummy dummy dummy (ID7-ID0) 90H dummy dummy 00H (M7-M0) (ID7-ID0) 9FH (M7-M0) (ID15-ID8) (ID7-ID0) 44H A23-A16 A15-A8 A7-A0 42H A23-A16 A15-A8 A7-A0 (D7-D0) (D7-D0) 48H A23-A16 A15-A8 A7-A0 dummy (D7-D0) http://www.hgsemi.com.cn 02H 20H 52H D8H C7/60H 75H A23-A0 M7-M0(4) FFH A7-A0 7AH B9H ABH ABH 17 2019 OCT V1.0 HG25Q32 Notes: 1. Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3 3. Quad Output Data IO0 = (D4, D0,…..) IO1 = (D5, D1,…..) IO2 = (D6, D2,…..) IO3 = (D7, D3,…..) 4. Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 5. Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0,…) IO1 = (x, x, x, x, D5, D1,…) IO2 = (x, x, x, x, D6, D2,…) IO3 = (x, x, x, x, D7, D3,…) 6. Security Registers Address: Security Register0: A23-A16=00h, A15-A8=00h, A7-A0= Byte Address; Security Register1: A23-A16=00h, A15-A8=01h, A7-A0= Byte Address; Security Register2: A23-A16=00h, A15-A8=02h, A7-A0= Byte Address; Security Register3: A23-A16=00h, A15-A8=03h, A7-A0= Byte Address; http://www.hgsemi.com.cn 18 2019 OCT V1.0 HG25Q32 7.1 Configuration and Status Instructions 7.1.1 Write Enable (06H) See Figure 5, the Write Enable instruction is for setting the Write Enable Latch bit. The Write Enable Latch bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register instruction. The Write Enable instruction sequence: /CS goes low sending the Write Enable instruction /CS goes high. Figure 5. Write Enable Sequence Diagram /CS 0 1 2 3 4 5 6 7 SCLK Instruction SI 06H High_Z SO 7.1.2 Write Disable (04H) See Figure 6, the Write Disable instruction is for resetting the Write Enable Latch bit. The Write Disable instruction sequence: /CS goes low Sending the Write Disable instruction /CS goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase instructions. Figure 6. Write Disable Sequence Diagram /CS 0 1 2 3 4 5 6 7 SCLK Instruction SI SO http://www.hgsemi.com.cn 04H High_Z 19 2019 OCT V1.0 HG25Q32 7.1.3 Read Status Register (05H or 35H) See Figure 7 the Read Status Register (RDSR) instruction is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously. For instruction code “05H”, the SO will output Status Register bits S7~S0. The instruction code “35H”, the SO will output Status Register bits S15~S8. Figure 7. Read Status Register Sequence Diagram /CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Instruction SI 05H or 35H S7-S0 or S15-S8 out High_Z SO 7.1.4 7 MSB 6 5 4 3 2 1 S7-S0 or S15-S8 out 0 7 6 MSB 5 4 3 2 1 0 Write Status Register (01H) See Figure 8, the Write Status Register instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable instruction must previously have been executed. After the Write Enable instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register instruction has no effect on S15, S1 and S0 of the Status Register. /CS must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register instruction is not executed. If /CS is driven high after eighth bit of the data byte, the CMP and QE and SRP1 bits will be cleared to 0. As soon as /CS is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch is reset. The Write Status Register instruction allows the user to change the values of the Block Protect (SEC, TB, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 3. The Write Status Register instruction also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (/WP) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (/WP) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register instruction is not executed once the Hardware Protected Mode is entered. http://www.hgsemi.com.cn 20 2019 OCT V1.0 HG25Q32 Figure 8. Write Status Register Sequence Diagram /CS 0 1 2 4 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Status Register in Instruction SI 01H 7 6 5 3 4 2 1 0 15 14 13 12 11 10 9 8 MSB SO 7.1.5 High_Z Write Enable for Volatile Status Register (50H) See Figure 9, the non-volatile Status Register bits can also be written to as volatile bits. During power up reset, the non-volatile Status Register bits are copied to a volatile version of the Status Register that is used during device operation. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. To write the volatile version of the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior to each Write Status Registers (01h) instruction. Write Enable for Volatile Status Register instruction will not set the Write Enable Latch bit, it is only valid for the next following Write Status Registers instruction, to change the volatile Status Register bit values. Figure 9. Write Enable for Volatile Status Register /CS 0 1 2 3 4 5 6 7 SCLK Instruction SI SO http://www.hgsemi.com.cn 50H High_Z 21 2019 OCT V1.0 HG25Q32 7.2 Read Instructions 7.2.1 Read Data (03H) See Figure 10, the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single command as long as the clock continues. The command is completed by driving /CS high. The whole memory can be read with a single Read Data Bytes (READ) instruction. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Normal read mode running up to 50MHz. Figure 10. Read Data Bytes Sequence Diagram /CS 0 1 2 3 4 5 6 7 8 9 28 29 30 31 32 33 34 35 36 37 38 39 10 SCLK 24-Bit Address Instruction SI 03H 23 22 21 3 2 1 0 Data Byte1 MSB SO http://www.hgsemi.com.cn High_Z 7 6 MSB 22 5 4 3 High_Z 2 1 0 2019 OCT V1.0 HG25Q32 7.2.2 Fast Read (0BH) See Figure 11, the Read Data Bytes at Higher Speed (Fast Read) instruction is for quickly reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fc, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 11. Fast Read Sequence Diagram /CS 0 1 2 3 4 5 6 7 9 8 28 29 30 10 31 SCLK Instruction 24-Bit Address 23 22 0BH SI 21 3 2 1 0 High_Z SO /CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Clocks High_Z SI SO http://www.hgsemi.com.cn High_Z Data byte 1 6 7 23 5 4 3 High_Z 2 1 0 2019 OCT V1.0 HG25Q32 7.2.3 Dual Output Fast Read (3BH) See Figure 12, the Dual Output Fast Read instruction is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 12. Dual Output Fast Read Sequence Diagram /CS 0 1 2 3 4 5 6 7 9 8 28 10 29 30 31 SCLK Instruction 24-Bit Address 3BH SI SO 23 22 21 41 42 43 3 2 1 0 High_Z /CS 32 33 34 35 36 37 38 39 40 44 45 46 47 6 4 2 0 SCLK SI Dummy Clocks 6 4 2 0 Data Byte 2 Data Byte 1 SO High_Z http://www.hgsemi.com.cn 5 7 24 3 1 7 5 3 1 High_Z High_Z 2019 OCT V1.0 HG25Q32 7.2.4 Quad Output Fast Read (6BH) See Figure 13, the Quad Output Fast Read instruction is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 13. Quad Output Fast Read Sequence Diagram /CS 0 1 3 2 4 5 6 8 7 9 28 10 29 30 31 SCLK 24-Bit Address Instruction SI (IO0) 6BH SO (IO1) High_Z /WP (IO2) High_Z /HOLD (IO3) High_Z /CS 32 33 34 35 36 37 38 39 40 3 2 1 45 46 47 21 22 23 41 42 43 44 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 7 3 Byte1 7 3 7 3 Byte3 0 SCLK SI (IO0) Dummy Clocks SO (IO1) High_Z /WP (IO2) High_Z /HOLD (IO3) High_Z http://www.hgsemi.com.cn 25 Byte2 3 7 Byte4 High_Z High_Z High_Z High_Z 2019 OCT V1.0 HG25Q32 7.2.5 Dual I/O Fast Read (BBH) See Figure 14, the Dual I/O Fast Read instruction is similar to the Dual Output Fast Read instruction but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 14. Dual I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH) /CS 0 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Instruction SI (IO0) BBH SO (IO1) High_Z 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 A23-16 A15-8 A7-0 M7-0 /CS SCLK 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SI (IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 SO (IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 3 5 Byte 4 1 Byte 1 http://www.hgsemi.com.cn Byte 2 Byte 3 26 High_Z High_Z 2019 OCT V1.0 HG25Q32 7.2.6 Dual I/O Fast Read with “Continuous Read Mode” See Figure 15, the Dual I/O Fast Read instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Dual I/O Fast Read instruction (after /CS is raised and then lowered) does not require the BBH instruction code. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next instruction requires the first BBH instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset instruction can be used to reset (M7-0) before issuing normal instruction. Figure 15. Dual I/O Fast Read Sequence Diagram (M7-0= AXH) /CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK SI (IO0) 6 SO (IO1) 7 /CS 0 6 4 0 6 4 2 0 6 4 2 0 5 3 1 A23-16 7 5 3 1 A15-8 7 5 3 A7-0 1 7 5 3 M7-0 1 4 2 2 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCLK SI (IO0) 6 4 2 0 6 4 0 6 4 2 0 6 SO (IO1) 7 5 3 Byte1 1 7 5 3 1 Byte2 7 5 3 Byte3 1 7 http://www.hgsemi.com.cn 2 27 2 0 5 3 Byte4 1 4 2019 OCT V1.0 HG25Q32 7.2.7 Quad I/O Fast Read (EBH) See Figure 16, the Quad I/O Fast Read instruction is similar to the Dual I/O Fast Read instruction but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register must be set to enable for the Quad I/O Fast read instruction. Figure 16. Quad I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH) /CS 0 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK SI (IO0) Instruction EBH SO (IO1) High_Z /WP (IO2) High_Z /HOLD (IO3) High_Z http://www.hgsemi.com.cn 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 A7-0 7 3 7 3 7 3 A23-16 A15-8 28 Dummy 7 3 Byte1 7 3 Byte2 2019 OCT V1.0 HG25Q32 7.2.8 Quad I/O Fast Read with “Continuous Read Mode” See Figure 17, the Quad I/O Fast Read instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Quad I/O Fast Read instruction (after /CS is raised and then lowered) does not require the EBH instruction code. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next instruction requires the first EBH instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset instruction can be used to reset (M7-0) before issuing normal instruction. Figure 17. Quad I/O Fast Read Sequence Diagram (M7-0= AXH) /CS 0 SCLK SI (IO0) 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 4 0 4 0 4 0 4 0 4 0 4 0 SO (IO1) /WP (IO2) 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 /HOLD (IO3) 7 3 7 3 7 3 7 3 7 3 Byte1 A23-16 http://www.hgsemi.com.cn A15-8 A7-0 M7-0 29 Dummy 7 3 Byte2 2019 OCT V1.0 HG25Q32 7.2.9 Continuous Read Mode Reset (FFH or FFFFH) The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O” and “Fast Read Quad I/O” Instructions to provide the highest random Flash memory access rate with minimum SPI instruction overhead, thus allowing more efficient XIP (execute in place) with this device family. The “Continuous Read Mode” bits M7-0 are set by the Dual/Quad I/O Read Instructions. M5-4 are used to control whether the 8-bit SPI instruction code (BBh or EBh) is needed or not for the next instruction. When M5-4 = (1,0), the next instruction will be treated the same as the current Dual/Quad I/O Read instruction without needing the 8-bit instruction code; when M5-4 do not equal to (1,0), the device returns to normal SPI instruction mode, in which all instructions can be accepted. M7-6 and M3-0 are reserved bits for future use, either 0 or 1 values can be used. See Figure 18, the Continuous Read Mode Reset instruction (FFh or FFFFh) can be used to set M4 = 1, thus the device will release the Continuous Read Mode and return to normal SPI operation. To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed. The instruction is “FFh”. To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are needed to shift in instruction “FFFFh Figure 18. Continuous Read Mode Reset Sequence Diagram /CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK SI (IO0) Instruction FFH FFFFH SO (IO1) Don’t Care /WP (IO2) Don’t Care /HOLD (IO3) Don’t Care http://www.hgsemi.com.cn 30 2019 OCT V1.0 HG25Q32 7.2.10 Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” (77h) instruction prior to EBh. The “Set Burst with Wrap” (77h) instruction can either enable or disable the “Wrap Around” feature for the following EBh instructions. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the instruction. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read instructions. The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. Wrap bit W7 and the lower nibble W3-0 are not used. Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and “Word Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4=1. The default value of W4 upon power on is 1. W4 = 0 W4 =1 (DEFAULT) W6 W5 Wrap Around Wrap Length Wrap Around Wrap Length 0 0 Yes 8-byte No N/A 0 1 1 1 0 1 Yes Yes Yes 16-byte 32-byte 64-byte No No No N/A N/A N/A http://www.hgsemi.com.cn 31 2019 OCT V1.0 HG25Q32 Figure 19. Set Burst with Wrap Command Sequence /CS 0 1 2 3 4 5 6 7 8 9 11 10 12 13 14 15 SCLK SI (IO0) Instruction SO (IO1) x x x x x x W4 x High_Z x x x x x x x High_Z W5 x x x x x x x High_Z W6 x x x x x x x x High_Z /WP (IO2) High_Z /HOLD (IO3) High_Z Byte1 http://www.hgsemi.com.cn High_Z 77H 32 Byte2 Byte3 Byte4 2019 OCT V1.0 HG25Q32 7.3 ID and Security Instructions 7.3.1 Read Manufacture ID/ Device ID (90H) See Figure 20, the Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The instruction is initiated by driving the /CS pin low and shifting the instruction code “90H” followed by a 24-bit address (A23-A0) of 000000H. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 20. Read Manufacture ID/ Device ID Sequence Diagram /CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Instruction SI 24-Bit Address 3 2 23 22 21 90H High_Z SO 1 0 /CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI SO 7 6 http://www.hgsemi.com.cn Manufacturer ID 5 4 3 2 1 0 7 33 6 5 Device ID 3 2 4 1 0 2019 OCT V1.0 HG25Q32 7.3.2 JEDEC ID (9FH) The JEDEC ID instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. JEDEC ID instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The JEDEC ID instruction should not be issued while the device is in Deep Power-Down Mode. See Figure 21, he device is first selected by driving /CS to low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The JEDEC ID instruction is terminated by driving /CS to high at any time during data output. When /CS is driven high, the device is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute instructions. Figure 21. JEDEC ID Sequence Diagram /CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 9FH Instruction SI Manufacturer ID 7 MSB SO /CS 6 16 17 18 19 20 21 22 23 24 25 26 5 4 3 2 0 1 27 28 29 30 31 SCLK SI SO 7 Memory Type ID15-ID8 6 5 4 3 2 1 MSB http://www.hgsemi.com.cn 0 7 Capacity ID7-ID0 6 5 4 3 2 1 0 MSB 34 2019 OCT V1.0 HG25Q32 7.3.3 Deep Power-Down (B9H) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Deep Power-down instruction. The lower power consumption makes the Deep Power-down (DPD) instruction especially useful for battery powered applications (see ICC1 and ICC2). The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in Figure 22. The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Deep Power down instruction will not be executed. After /CS is driven high, the power-down state will entered within the time duration of tDP. While in the power-down state only the Release from Deep Power-down / Device ID instruction, which restores the device to normal operation, will be recognized. All other Instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction also makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. Figure 22. Deep Power-Down Sequence Diagram /CS 0 1 2 3 4 5 6 7 tDP SCLK Instruction SI B9H Stand-by mode http://www.hgsemi.com.cn 35 Power-down mode 2019 OCT V1.0 HG25Q32 7.3.4 Release from Deep Power-Down/Read Device ID (ABH) The Release from Power-Down or Device ID instruction is a multi-purpose instruction. It can be used to release the device from the Power-Down state or obtain the devices electronic identification (ID) number. See Figure 23a, to release the device from the Power-Down state, the instruction is issued by driving the /CS pin low, shifting the instruction code “ABH” and driving /CS high Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other instruction are accepted. The /CS pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the Power-Down state, the instruction is initiated by driving the /CS pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 23b. The Device ID value for the BG25Q32A is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high. When used to release the device from the Power-Down state and obtain the Device ID, the instruction is the same as previously described, and shown in Figure 23b, except that after /CS is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other instruction will be accepted. If the Release from Power-Down/Device ID instruction is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the instruction is ignored and will not have any effects on the current cycle. Figure 23a. Release Power-Down Sequence Diagram /CS 1 0 2 3 4 5 6 tRES1 7 SCLK Instruction SI ABH Power-down mode Stand-by mode Figure 23b. Release Power-Down/Read Device ID Sequence Diagram /CS 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 39 SCLK Instruction SI ABH SO High_Z 3 Dummy Bytes 2 1 23 22 MSB tRES2 0 7 MSB 6 Device ID 3 4 5 2 1 0 Deep Power-down mode http://www.hgsemi.com.cn 36 Stand-by mode 2019 OCT V1.0 HG25Q32 7.3.5 Read Security Registers (48H) See Figure 24, the Read Security Registers instruction is similar to Fast Read instruction. The instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the instruction is completed by driving /CS high. Address A23-A16 A15-A8 A7-A0 Security Registers 1 00H 01H Byte Address Security Registers 2 00H 02H Byte Address Security Registers 3 00H 03H Byte Address Figure 24. Read Security Registers instruction Sequence Diagram /CS 0 1 2 3 4 5 6 7 8 9 28 29 30 31 SCLK Instruction SI 48H SO High_Z 24-Bit Address 3 23 22 2 1 0 /CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI 7 6 5 SO http://www.hgsemi.com.cn 4 3 2 1 0 Data Byte 1 7 6 MSB 37 5 4 3 2 1 0 2019 OCT V1.0 HG25Q32 7.3.6 Erase Security Registers (44H) The BG25Q32A provides three 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. See Figure 25, the Erase Security Registers instruction is similar to Sector/Block Erase instruction. A Write Enable instruction must previously have been executed to set the Write Enable Latch bit. The Erase Security Registers instruction sequence: /CS goes low sending Erase Security Registers instruction /CS goes high. /CS must be driven high after the eighth bit of the instruction code has been latched in otherwise the Erase Security Registers instruction is not executed. As soon as /CS is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. The Security Registers Lock Bit (LB) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers instruction will be ignored. Address A23-A16 A15-A8 A7-A0 Security Registers 1 00H 01H Don’t Care Security Registers 2 00H 02H Don’t Care Security Registers 3 00H 03H Don’t Care Figure 25. Erase Security Registers instruction Sequence Diagram /CS 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Instruction SI http://www.hgsemi.com.cn 24-Bit Address 23 22 44H 38 2 1 0 2019 OCT V1.0 HG25Q32 7.3.7 Program Security Registers (42H) See Figure 26, the Program Security Registers instruction is similar to the Page Program instruction. It allows from 1 to 256 bytes Security Registers data to be programmed. A Write Enable instruction must previously have been executed to set the Write Enable Latch bit before sending the Program Security Registers instruction. The Program Security Registers instruction is entered by driving /CS Low, followed by the instruction code (42H), 3-byte address and at least one data byte on SI. As soon as /CS is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. If the Security Registers Lock Bit (LB3/LB2/LB1) is set to 1, the Security Registers will be permanently locked. Program Security Registers instruction will be ignored. Address A23-A16 A15-A8 A7-A0 Security Registers 1 00H 01H Byte Address Security Registers 2 00H 02H Byte Address Security Registers 3 00H 03H Byte Address Figure 26. Program Security Registers instruction Sequence Diagram /CS 0 4 3 2 1 5 6 7 9 8 29 30 28 10 31 32 33 34 35 36 37 38 39 SCLK Instruction 24-Bit Address 23 22 21 MSB 42H SI 3 Data Byte 1 1 2 0 7 MSB 6 4 5 2 3 1 0 2079 2078 2077 2076 2075 2074 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 /CS SCLK Data Byte 2 SI 7 6 5 4 3 MSB http://www.hgsemi.com.cn 2 1 0 7 6 MSB Data Byte 3 4 3 2 5 39 1 0 7 6 MSB Data Byte 256 3 2 5 4 1 0 2019 OCT V1.0 HG25Q32 7.4 Program and Erase Instructions 7.4.1 Page Program (02H) The Page Program instruction is for programming the memory. A Write Enable instruction must previously have been executed to set the Write Enable Latch bit before sending the Page Program instruction. See Figure 27, the Page Program instruction is entered by driving /CS Low, followed by the instruction code, 3-byte address and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). /CS must be driven low for the entire duration of the sequence. The Page Program instruction sequence: /CS goes low sending Page Program instruction 3-byte address on SI at least 1 byte data on SI /CS goes high. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. /CS must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program instruction is not executed. As soon as /CS is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A Page Program instruction applied to a page which is protected by the Block Protect (SEC, TB, BP2, BP1, BP0) is not executed. Figure 27. Page Program Sequence Diagram /CS 0 4 3 2 1 5 6 7 9 8 29 30 28 10 31 32 33 34 35 36 37 38 39 SCLK Instruction 24-Bit Address 23 22 21 MSB 02H SI 3 Data Byte 1 1 2 0 7 6 MSB 4 5 2 3 1 0 2079 2078 2077 2076 2075 2074 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 /CS SCLK Data Byte 2 SI 7 6 5 4 3 MSB http://www.hgsemi.com.cn 2 1 0 7 6 MSB Data Byte 3 4 3 2 5 40 1 0 7 6 MSB Data Byte 256 3 2 5 4 1 0 2019 OCT V1.0 HG25Q32 7.4.2 Sector Erase (20H) The Sector Erase instruction is for erasing the all data of the chosen sector. A Write Enable instruction must previously have been executed to set the Write Enable Latch bit. The Sector Erase instruction is entered by driving /CS low, followed by the instruction code, and 3-address byte on SI. Any address inside the sector is a valid address for the Sector Erase instruction. /CS must be driven low for the entire duration of the sequence. See Figure 28, The Sector Erase instruction sequence: /CS goes low sending 64KB Block Erase instruction 3-byte address on SI /CS goes high. /CS must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Sector Erase instruction is not executed. As soon as /CS is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A Sector Erase instruction applied to a sector which is protected by the Block Protect (SEC, TB, BP2, BP1, BP0) bit is not executed. Figure 28. Sector Erase Sequence Diagram /CS 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Instruction SI http://www.hgsemi.com.cn 24-Bit Address 23 22 20H 41 2 1 0 2019 OCT V1.0 HG25Q32 7.4.3 32KB Block Erase (52H) The 32KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable instruction must previously have been executed to set the Write Enable Latch bit. The 32KB Block Erase instruction is entered by driving /CS low, followed by the instruction code, and 3-byte address on SI. Any address inside the block is a valid address for the 32KB Block Erase instruction. /CS must be driven low for the entire duration of the sequence. See Figure 29, the 32KB Block Erase instruction sequence: /CS goes low sending 32KB Block Erase instruction 3-byte address on SI /CS goes high. /CS must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase instruction is not executed. As soon as /CS is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A 32KB Block Erase instruction applied to a block which is protected by the Block Protect (SEC, TB, BP2, BP1, BP0) bits (see Table 6&7) is not executed. Figure 29. 32KB Block Erase Sequence Diagram /CS 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Instruction SI http://www.hgsemi.com.cn 24-Bit Address 23 22 52H 42 2 1 0 2019 OCT V1.0 HG25Q32 7.4.4 64KB Block Erase (D8H) The 64KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable instruction must previously have been executed to set the Write Enable Latch bit. The 64KB Block Erase instruction is entered by driving /CS low, followed by the instruction code, and 3-byte address on SI. Any address inside the block is a valid address for the 64KB Block Erase instruction. /CS must be driven low for the entire duration of the sequence. See Figure 30, the 64KB Block Erase instruction sequence: /CS goes low sending 64KB Block Erase instruction 3-byte address on SI /CS goes high. /CS must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase instruction is not executed. As soon as /CS is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A 64KB Block Erase instruction applied to a block which is protected by the Block Protect (SEC, TB, BP2, BP1, BP0) bits (see Table 6&7) is not executed. Figure 30. 64KB Block Erase Sequence Diagram /CS 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Instruction SI http://www.hgsemi.com.cn 24-Bit Address 23 22 D8H 43 2 1 0 2019 OCT V1.0 HG25Q32 7.4.5 Chip Erase (60/C7H) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 31. The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will commence for a time duration of tCE. While the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the WIP bit. The WIP bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other Instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Table 6&7). Figure 31. Chip Erase Sequence Diagram /CS 0 1 2 3 4 5 6 7 SCLK Instruction SI SO http://www.hgsemi.com.cn 60/C7H High_Z 44 2019 OCT V1.0 HG25Q32 7.4.6 Erase / Program Suspend (75H) The Erase/Program Suspend instruction allows the system to interrupt a Sector or Block Erase operation, then read from or program data to any other sector. The Erase/Program Suspend instruction also allows the system to interrupt a Page Program operation and then read from any other page or erase any other sector or block. The Erase/Program Suspend instruction sequence is shown in Figure 32. The Write Status Registers instruction (01h) and Erase instructions (20h, D8h, C7h, 60h, 44h) are not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Registers instruction (01h), and Program instructions (02h, 32h, 42h) are not allowed during Program Suspend. Program Suspend is valid only during the Page Program operation. Figure 32. Erase/Program Suspend Command Sequence /CS 0 1 2 3 4 5 6 0 7 1 2 3 4 5 6 7 SCLK Instruction SI http://www.hgsemi.com.cn tSUS Instruction During Suspend 75H 45 2019 OCT V1.0 HG25Q32 7.4.7 Erase / Program Resume (7AH) The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah” will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the WIP bit equals to 0. After the Resume instruction is issued the SUS bit will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200 ns and the Sector or Block will complete the erase operation or the page will complete the program operation. If the SUS bit equals to 0 or the WIP bit equals to 1, the Resume instruction “7Ah” will be ignored by the device. The Erase/Program Resume instruction sequence is shown in Figure 33. Figure 33. Erase/Program Resume Command Sequence /CS 0 1 2 3 4 5 6 7 SCLK Instruction SI 7AH SO High_Z http://www.hgsemi.com.cn 46 2019 OCT V1.0 HG25Q32 8. Electrical Characteristics 8.1 Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage VCC Voltage Applied to Any Pin VIO Transient Voltage on any Pin VIOT Storage Temperature TSTG Electrostatic Discharge Voltage VESD CONDITIONS RANGE UNIT –0.5 to 4 V Relative to Ground –0.5 to 4 V