A71X37AQFI/Q

A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver Document Title A7137 Data Sheet, 2.4GHz FSK/GFSK Transceiver with 10 dBm PA at 2Mbps data rate. Revision History Issue Date 0.1 Initial issue. May, 2012 0.2 Add descriptions for HECF, FECF and CRCF clear method in 9.2.1 Aug.,2012 Remark L History Preliminary TI A Rev. No. Preliminary Add suggestion in WOR function Oct.,2012 Preliminary Add more description for ADC function July,2013 Preliminary 1.0 Full Production Mar., 2014 A M IC C O M C O N FI D EN 0.3 0.4 Important Notice: AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such applications is understood to be fully at the risk of the customer. Mar., 2014, Version 1.0 1 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver Table of Contents A M IC C O M C O N FI D EN TI A L 1. General Description....................................................................................................................................................... 1 2. Typical Applications ....................................................................................................................................................... 1 3. Feature ......................................................................................................................................................................... 1 4. Pin Configurations ......................................................................................................................................................... 6 5. Pin Description (I: input; O: output, I/O: input or output)................................................................................................... 5 6. Chip Block Diagram....................................................................................................................................................... 6 7. Absolute Maximum Ratings............................................................................................................................................ 7 8. Electrical Specification................................................................................................................................................... 8 9. Control Register ...........................................................................................................................................................10 9.1 Control register table............................................................................................................................................10 9.2 Control register description ..................................................................................................................................13 9.2.1 Mode Register (Address: 00h) ....................................................................................................................13 9.2.2 Mode Control Register (Address: 01h)......................................................................................................13 9.2.3 Calibration Control Register (Address: 02h)..............................................................................................14 9.2.4 FIFO Register I (Address: 03h).................................................................................................................14 9.2.5 FIFO Register II (Address: 04h)................................................................................................................14 9.2.6 FIFO DATA Register (Address: 05h) .........................................................................................................14 9.2.7 ID DATA Register (Address: 06h)................................................................................................................14 9.2.8 RC OSC Register I (Address: 07h) .............................................................................................................15 9.2.9 RC OSC Register II (Address: 08h).............................................................................................................15 9.2.10 RC OSC Register III (Address: 09h)..........................................................................................................15 9.2.11 CKO Pin Control Register (Address: 0Ah) .................................................................................................15 9.2.12 GIO1 Pin Control Register I (Address: 0Bh)...............................................................................................16 9.2.13 GIO2 Pin Control Register II (Address: 0Ch) .............................................................................................17 9.2.14 Clock Register (Address: 0Dh)..................................................................................................................18 9.2.15 PLL Register I (Address: 0Eh)...................................................................................................................19 9.2.16 PLL Register II (Address: 0Fh)..................................................................................................................19 9.2.17 PLL Register III (Address: 10h) .................................................................................................................19 9.2.18 PLL Register IV (Address: 11h).................................................................................................................19 9.2.19 PLL Register V (Address: 12h) ...............................................................................................................19 9.2.20 Channel Group Register I (Address: 13h)..................................................................................................19 9.2.21 Channel Group Register II (Address: 14h).................................................................................................20 9.2.22 TX Register I (Address: 15h).....................................................................................................................20 9.2.23 TX Register II (Address: 16h)....................................................................................................................20 9.2.24 Delay Register I (Address: 17h) ................................................................................................................20 9.2.25 Delay Register II (Address: 18h) ...............................................................................................................21 9.2.26 RX Register (Address: 19h) ......................................................................................................................21 9.2.27 RX Gain Register I (Address: 1Ah)............................................................................................................22 9.2.28 RX Gain Register II (Address: 1Bh)...........................................................................................................22 9.2.29 RX Gain Register III (Address: 1Ch) .........................................................................................................22 9.2.30 RX Gain Register IV (Address: 1Dh) .........................................................................................................23 9.2.31 RSSI Threshold Register (Address: 1Eh) ..................................................................................................23 9.2.32 ADC Control Register (Address: 1Fh)........................................................................................................23 9.2.33 Code Register I (Address: 20h).................................................................................................................24 9.2.34 Code Register II (Address: 21h)................................................................................................................24 9.2.35 Code Register III (Address: 22h)...............................................................................................................24 9.2.36 IF Calibration Register I (Address: 23h).....................................................................................................25 9.2.37 IF Calibration Register II (Address: 24h)....................................................................................................25 9.2.38 VCO current Calibration Register (Address: 25h).......................................................................................25 9.2.39 VCO band Calibration Register I (Address: 26h)........................................................................................26 9.2.40 VCO band Calibration Register II (Address: 27h).......................................................................................26 9.2.41 VCO Deviation Calibration Register I (Address: 28h) .................................................................................26 9.2.42 VCO Deviation Calibration Register II (Address: 29h) ................................................................................27 9.2.43 DASP0 (Address: 2Ah, Page 0 by AGT [3:0]=0) ........................................................................................27 9.2.43 DASP1 (Address: 2Ah, Page 1 by AGT[3:0]=1) .........................................................................................27 Mar., 2014, Version 1.0 2 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver A M IC C O M C O N FI D EN TI A L 9.2.43 DASP2 (Address: 2Ah, Page 2 by AGT[3:0]=2) .........................................................................................28 9.2.43 DASP3 (Address: 2Ah, Page 3 by AGT[3:0]=3) .........................................................................................28 9.2.43 DASP4 (Address: 2Ah, Page 4 by AGT[3:0]=4) .........................................................................................28 9.2.43 DASP5 (Address: 2Ah, Page 5 by AGT[3:0]=5) .........................................................................................28 9.2.43 DASP6 (Address: 2Ah, Page 6 by AGT[3:0]=6) .........................................................................................28 9.2.43 DASP7 (Address: 2Ah, Page 7 by AGT[3:0]=7) .........................................................................................28 9.2.44 VCO Modulation Delay Register (Address: 2Bh)........................................................................................29 9.2.45 Battery detect Register (Address: 2Ch) .....................................................................................................29 9.2.46 TX test Register (Address: 2Dh) ...............................................................................................................29 9.2.47 Rx DEM test Register I (Address: 2Eh) .....................................................................................................30 9.2.48 Rx DEM test Register II (Address: 2Fh).....................................................................................................30 9.2.49 Charge Pump Current Register I (Address: 30h) .......................................................................................30 9.2.50 Charge Pump Current Register II (Address: 31h).......................................................................................30 9.2.51 Crystal test Register (Address: 32h)..........................................................................................................31 9.2.52 PLL test Register (Address:33h) ...............................................................................................................31 9.2.53 VCO test Register I (Address:34h)............................................................................................................31 9.2.54 RF Analog Test Register (Address: 35h)....................................................................................................32 9.2.55 AES Key data Register (Address: 36h)......................................................................................................32 9.2.56 Channel Select Register (Address: 37h)....................................................................................................32 9.2.57 ROMP0 (Address: 38h, Page 0 by AGT[3:0]=0).........................................................................................32 9.2.57 ROMP1 (Address: 38h, Page 1 by AGT[3:0]=1).........................................................................................33 9.2.57 ROMP2 (Address: 38h, Page 2 by AGT[3:0]=2).........................................................................................33 9.2.57 ROMP3 (Address: 38h, Page 3 by AGT[3:0]=3).........................................................................................33 9.2.57 ROMP4 (Address: 38h, Page 4 by AGT[3:0]=4).........................................................................................33 9.2.58 Data Rate Clock Register (Address: 39h) ..................................................................................................33 9.2.59 FCR Register (Address: 3Ah) ...................................................................................................................34 9.2.60 ARD Register (Address: 3Bh) ...................................................................................................................34 9.2.61 AFEP Register (Address: 3Ch)..................................................................................................................34 9.2.62 FCB Register (Address: 3Dh) ...................................................................................................................35 9.2.63 KEYC Register (Address: 3Eh) .................................................................................................................35 9.2.64 USID Register (Address: 3Fh) ..................................................................................................................36 10. SPI.............................................................................................................................................................................37 10.1 SPI Format ........................................................................................................................................................38 10.2 SPI Timing Characteristic ...................................................................................................................................38 10.3 SPI Timing Chart................................................................................................................................................39 10.3.1 Timing Chart of 3-wire SPI........................................................................................................................39 10.3.2 Timing Chart of 4-wire SPI........................................................................................................................39 10.4 Strobe Commands .............................................................................................................................................40 10.4.1 Strobe Command - Sleep Mode ................................................................................................................40 10.4.2 Strobe Command - ldle Mode ...................................................................................................................40 10.4.3 Strobe Command - Standby Mode ............................................................................................................41 10.4.4 Strobe Command - PLL Mode...................................................................................................................41 10.4.5 Strobe Command - RX Mode....................................................................................................................42 10.4.6 Strobe Command - TX Mode ....................................................................................................................42 10.4.7 Strobe Command – FIFO Write Pointer Reset ...........................................................................................42 10.4.8 Strobe Command – FIFO Read Pointer Reset ...........................................................................................43 10.4.9 Strobe Command – Deep Sleep Mode ......................................................................................................43 10.5 Reset Command................................................................................................................................................44 10.6 ID Accessing Command .....................................................................................................................................44 10.6.1 ID Write Command...................................................................................................................................44 10.6.2 ID Read Command ..................................................................................................................................45 10.7 FIFO Accessing Command.................................................................................................................................45 10.7.1 TX FIFO Write Command .........................................................................................................................45 10.7.2 Rx FIFO Read Command.........................................................................................................................46 11. State machine.............................................................................................................................................................47 11.1 Key states..........................................................................................................................................................47 11.2 FIFO mode ........................................................................................................................................................48 11.3 Direct mode .......................................................................................................................................................49 12. Crystal Oscillator ........................................................................................................................................................52 12.1 Use External Crystal ..........................................................................................................................................52 Mar., 2014, Version 1.0 3 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver A M IC C O M C O N FI D EN TI A L 12.2 Use External Clock ............................................................................................................................................52 13. System Clock .............................................................................................................................................................53 13.2 Data Rate Setting ..............................................................................................................................................53 14. Transceiver LO Frequency..........................................................................................................................................54 14.1 LO Frequency Setting ........................................................................................................................................54 14.2 IF Side Band Select ...........................................................................................................................................55 14.2.1 Auto IF Exchange.....................................................................................................................................56 14.2.2 Fast Exchange.........................................................................................................................................57 14.3 Auto Frequency Compensation...........................................................................................................................58 15. Calibration..................................................................................................................................................................59 15.1 Calibration Procedure ........................................................................................................................................59 16. FIFO (First In First Out)...............................................................................................................................................59 16.1 TX Packet Format in FIFO mode ........................................................................................................................59 16.1.1 Basic FIFO mode .....................................................................................................................................59 16.1.2 Advanced FIFO mode...............................................................................................................................60 16.2 Bit Stream Process in FIFO mode.......................................................................................................................61 16.3 Transmission Time.............................................................................................................................................61 16.4 Usage of TX and RX FIFO .................................................................................................................................62 16.4.1 Easy FIFO ...............................................................................................................................................62 16.4.2 Segment FIFO .........................................................................................................................................64 16.4.3 FIFO Extension........................................................................................................................................66 17. ADC (Analog to Digital Converter) ...............................................................................................................................70 17.1 RSSI Measurement............................................................................................................................................70 18. Battery Detect ............................................................................................................................................................73 19. Auto-ack and auto-resend ...........................................................................................................................................74 19.1 Basic FIFO plus auto-ack auto-resend................................................................................................................74 19.2 Advanced FIFO plus auto-ack and auto-resend...................................................................................................74 19.3 WTR Behavior during auto-ack and auto-resend .................................................................................................76 19.6 Examples of auto-ack and auto-resend...............................................................................................................77 20. RC Oscillator ..............................................................................................................................................................79 20.1 WOR Function...................................................................................................................................................79 20.2 TWOR Function .................................................................................................................................................80 21. AES128 Security Packet .............................................................................................................................................80 22. Application circuit........................................................................................................................................................81 22.1 MD7137-A01 .....................................................................................................................................................81 23. Abbreviations..............................................................................................................................................................83 24. Ordering Information...................................................................................................................................................83 25. Package Information...................................................................................................................................................84 26. Top Marking Information..............................................................................................................................................85 27. Reflow Profile .............................................................................................................................................................86 28. Tape Reel Information.................................................................................................................................................87 29. Product Status............................................................................................................................................................89 Mar., 2014, Version 1.0 4 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 1. General Description A7137 is a 10dBm output power and low cost 2.4GHz ISM band wireless transceiver. This device integrates both high sensitivity receiver (-90dBm @ 2Mbps) and programmable power amplifier (-18 ~ 10dBm). Based on Data Rate Register (39h), user can configure on-air data rates for 2Mbps or 1Mbps or 500Kbps operation. EN TI A L A7137 supports fast settling time (90 us) for frequency hopping system. For packet handling, A7137 has built-in separated 64-bytes TX/RX FIFO (could be logically extended to 4K bytes) for data buffering and burst transmission, auto-ack and auto-resend, CRC for error packet filtering, FEC for 1-bit data correction per code word, RSSI for clear channel assessment, thermal sensor for monitoring relative temperature, WOR (Wake on RX) function to support periodically wake up from sleep mode to RX mode and listen for incoming packets without MCU interaction, data whitening for data encryption / decryption. In addition, A7137 has built-in AES128 co-processor (Advanced Encryption Standard) for advanced data encryption and decryption which consists of the transformation of a 128-bit block into an encrypted 128-bit block. Those functions are very easy to use while developing a wireless system. All features are integrated in a small QFN 4X4 20 pins package. FI D A7137’s control registers are accessed via 3-wire or 4-wire SPI interface such as TX/RF FIFO, ID register, RSSI value, frequency hopping to chip calibration procedures. Another one, via SPI as well, is the unique Strobe command; A7137 can be controlled from power saving mode (deep sleep, sleep, idle, standby), PLL mode, TX mode and RX mode. The other connections between A7137 and MCU are GIO1 and GIO2 (multi-function GPIO) to output A7137’s status so that MCU could use either polling or interrupt scheme for radio control. Overall, this device is very easy-to-use for developing a wireless application with a MCU. N 2. Typical Applications C O n 2.4GHz audio streaming n 2.4GHz active RF ID n 2.4GHz airplanes and helicopter 3. Feature M O C IC A n n n n n n n n Small size (QFN4 X4, 20 pins). Frequency band: 2400 ~ 2483.5MHz. FSK or GFSK modulation Low current consumption: RX 24mA, TX 35.5mA (at 10dBm output power). Deep sleep current (0.1 uA). Sleep current (4 uA). On chip regulator, support input voltage 2.0 ~ 3.6 V. Programmable data rate 500Kbps / 1Mbps / 2Mbps. Programmable TX power level from – 18 dBm to 10 dBm. High RX sensitivity: u -90dBm at 2Mbps on-air data rate. u -94dBm at 1Mbps on-air data rate. u -96dBm at 500Kbps on-air data rate. Fast settling time (90 us) synthesizer for frequency hopping system. On chip low power RC oscillator for WOR (Wake on RX) function. Built-in AES128 co-processor AGC (Auto Gain Control) for the wide RSSI dynamic range. AFC (Auto Frequency Compensation) for frequency drift due to temperature. Support low cost crystal (16 MHz). Low Battery Detector indication. Easy to use. u Support 3-wire or 4-wire SPI. u Unique Strobe command via SPI. u ONE register setting for new channel frequency. u CRC Error Packet Filtering. u Auto-acknowledgement and auto-resend. u Dynamic FIFO length. M n n n n n n n n n n n 2400 ~ 2483.5 MHz ISM system n Wireless home security and automation n Wireless toys and game controllers Mar., 2014, Version 1.0 1 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 8-bits RSSI measurement for clear channel indication. Auto Calibrations. Auto IF function. Auto FEC by (7, 4) Hamming code (1 bit error correction / code word). Separated 64 bytes RX and TX FIFO. Easy FIFO / Segment FIFO / FIFO Extension (up to 4K bytes). Support FIFO mode frame sync to MCU. Support direct mode with recovery clock output to MCU. L u u u u u u u u 4 GIO1 16 TI A GIO2 17 EN CKO SDIO 13 VDD_D 10 SCS XO 11 9 SCK XI 12 8 7 CP 14 V_PLL 6 5 V_VCO GND O M RFC 15 FI D RFO N 3 C O RFI 18 2 REGI BP_BG 19 1 VDD_A RSSI 20 4. Pin Configurations A M IC C Fig 4-1. A7137 QFN 4x4 Package Top View Mar., 2014, Version 1.0 6 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 5. Pin Description (I: input; O: output, I/O: input or output) Pin No. Symbol I/O Function Description 1 RSSI O 2 BP_BG O Connected to a bypass capacitor for internal Regulator bias point. 3 RFI I LNA input. Connected to matching circuit. 4 RFO O PA input. Connected to matching circuit. 5 RFC I RF Choke input. Connected to matching circuit. 6 V_VCO I VCO supply voltage input. 7 CP O Charge-pump. Connected to loop filter. 8 V_PLL I PLL supply voltage input. 9 XI I Crystal oscillator input. 10 XO O Crystal oscillator output. 11 SCS I SPI chip select. 12 SCK I SPI clock input pin. 13 VDD_D I Connected to a bypass capacitor to supply voltage for digital part. 14 SDIO I/O SPI read/write data. 15 GND G Ground 16 GIO1 I/O Multi-function GIO1 / 4-wire SPI data output. 17 GIO2 I/O 18 CKO O Multi-function GIO2 / 4-wire SPI data output. Multi-function clock output. 19 REGI I 20 VDD_A O Back side plate G C O N FI D EN TI A L Connected to a bypass capacitor for RSSI. Regulator input (External Power Input) Internal Regulator output to supply V_VCO (pin 6), V_PLL (pin 8) and RFC (pin 5). A M IC C O M Ground. Back side plate shall be well-solder to ground; otherwise, it will impact RF performance. Mar., 2014, Version 1.0 5 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver Fig 6-1. A7137 Block Diagram A M IC C O M C O N FI D EN TI A L 6. Chip Block Diagram Mar., 2014, Version 1.0 6 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 7. Absolute Maximum Ratings Parameter With respect to Rating Unit GND -0.3 ~ 3.6 V Digital IO pins range GND -0.3 ~ VDD+0.3 V Voltage on the analog pins range GND -0.3 ~ 2.1 V 10 TI A Input RF level Storage Temperature range -55 ~ 125 ESD Rating L Supply voltage range (VDD) dBm °C HBM* ± 2K V MM* ± 100 V FI D EN *Stresses above those listed under “Absolute Maximum Rating” may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. A M IC C O M C O N *Device is ESD sensitive. Use appropriate ESD precautions. HBM (Human Body Mode) is tested under MIL-STD-883F Method 3015.7. MM (Machine Mode) is tested under JEDEC EIA/JESD22-A115-A. Except Pin4 (RFO) is MM (± 25V) and HBM (+100V / -2KV). *Device is Moisture Sensitivity Level III (MSL 3). Mar., 2014, Version 1.0 7 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 8. Electrical Specification (Ta=25℃, VDD=3.3V, FXTAL =16MHz, with Match circuit and low pass filter, On Chip Regulator = 1.8V, unless otherwise noted.) Parameter Description Min. Type Max. Unit 85 °C V -40 1 2.0 Supply Voltage (VDD) * with internal regulator Current Consumption Deep Sleep mode* (No registers retention) Current Consumption Sleep mode (WOR off) * 2 4 2 Sleep mode (WOR on) * C O N FI D Idle Mode (Regulator on) * Standby Mode (XOSC on, CLK Gen. on) PLL mode RX Mode (AGC off) TX Mode (10dBm) TX Mode (7dBm) TX Mode (3dBm) TX Mode ( 0dBm) TX Mode ( -6dBm) TX Mode ( -13dBm) TX Mode ( -18dBm) 3 Idle to standby (Xtal osc. is stable at 20ppm) Idle to standby (Xtal osc. is stable at 10ppm) Data rate: 2M/1Mbps/500Kbps Data rate: 2M/1Mbps/500Kbps Crystal start up time* M O IC C Crystal frequency Crystal tolerance Crystal ESR VCO Operation Frequency PLL phase noise M 4 A PLL settling time* mA 5 mA mA 3.5 mA 12.5 24 35.5 28.5 24.5 23.5 21.5 20.5 20 mA mA mA mA mA mA mA mA mA 1 ms 2 ms 16 ±20 MHz ppm ohm MHz dBc 80 2483.5 2400 75 90 100 30 Offset 10k Offset 500K Offset 1M Loop filter based on app. circuit. (Standby to PLL) mA 0.3 EN 2 (49US type) 3.6 TI A 0.1 2 PLL block 3.3 L General Operating Temperature mS Transmitter Output power range -18 5 Out Band Spurious Emission * 6 Frequency deviation* 30MHz~1GHz 1GHz~12.75GHz 10 -36 -30 dBm dBm dBm 1.8GHz~ 1.9GHz 5.15GHz~ 5.3GHz -47 -47 dBm dBm Data rate 2Mbps ±500K Hz Data rate 1Mbps ±250K Hz Data rate 500Kbps ±186K Hz Data rate Mar., 2014, Version 1.0 5 500K 8 1M 2M bps AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 7 80 mS Data rate 2Mbps Data rate 1Mbps Data rate 500Kbps IFS = [01] for 2Mbps -90 -94 -96 2.4M dBm IFS = [00] for 1Mbps and 500Kbps 1.2M Standby to TX TX ready time* Receiver IF center frequency IFS = [01] for 2Mbps 2M 8 Co-Channel (C/I0) ±8MHz Adjacent Channel ±12MHz Adjacent Channel Maximum Operating Input Power 5 RX Ready Time Regulator dB - 25 dB - 30 dB - 45 dB dB -10 dB @RF input (BER=0.1%) 30MHz~1GHz 10 -57 dBm dBm 1GHz~12.75GHz AGC = 0 AGC = 1 -47 -50 -30 dBm dBm -95 -95 Pin 2 connected to 1nF. (Sleep to idle). 1.79 O Band-gap reference voltage Regulator output voltage - 17 - 45 M Regulator settling time dB Image (C/IIM) C O RSSI Range dB 0 ±40MHz Adjacent Channel N RX Spurious Emission * FI D ±20MHz Adjacent Channel 10 EN ±2MHz Adjacent Channel ±4MHz Adjacent Channel Hz 1M IFS = [00] for 1Mbps and 500Kbps Interference * (2Mbps , IF = 2MHz, AGC off) Hz L IF Filter bandwidth TI A Receiver sensitivity @ BER = 0.1% 80 ms 0.5 ms 1.28 1.8 2.3 V V VDD 0.2*VDD VDD 0.4 V V V V C Digital IO DC characteristics 0.8*VDD 0 VDD-0.4 0 @IOH= -0.5mA @IOL= 0.5mA M IC High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Output Voltage (VOH) Low Level Output Voltage (VOL) A Note 1: When VDD = 2.0V, the max TX output power is about 8 dBm. Note 2: When digital I/O pins are configured as input, those pins shall NOT be floating but pull either high or low (SCS shall be pulled high only); otherwise, leakage current will be induced. Note 3: Xtal settling time is depend on Xtal package type, Xtal ESR and Xtal Cm. Note 4: Refer to Delay Register I (17h) to set PDL (PLL settling delay). Note 5: With external RF filter that provides minimum 17dB of attenuation in the band: 30MHz ~ 2GHz and 3GHz ~12.75GHz. Note 6: Refer to TX Register II (16h) to set FD [7:0]. Note 7: Refer to Delay Register I (17h) to set PDL and TDL. Note 8: The wanted signal is set above sensitivity level +3dB. The modulation data of wanted signal and interferer are PN9 and PN15, respectively. Mar., 2014, Version 1.0 9 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 9. Control Register A7137 contains 69 control registers. MCU can access those control registers via 3-wire (SCS, SCK, SDIO) or 4-wire (SCS, SCK, SDIO, GIO1/GIO2) SPI interface (max. 15 Mbps). Please refer to Chapter 10 for SPI timing. In general, most of control registers are just need to configure the recommended values based on A7137 reference code. 09h RC OSC III Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W R W R RESETN HECF DDPC DDPC RESETN FECF ARSSI ARSSI RESETN CRCF AIF AIF RESETN CER DFCD CD RESETN XER WORE WORE RESETN PLLER FMT FMT RESETN TRSR FMS FMS RESETN TRER ADCM ADCM R/W -- -- -- VCC VBC VDC FBC RSSC W R W R --FEP7 LENF7 --FEP6 LENF6 --FEP5 LENF5 --FEP4 LENF4 FEP11 LENF11 FEP3 LENF3 FEP10 LENF10 FEP2 LENF2 FEP9 LENF9 FEP1 LENF1 FEP8 LENF8 FEP0 LENF0 W FPM1 FPM0 PSA5 PSA4 PSA3 PSA2 PSA1 PSA0 R/W FIFO7 FIFO6 FIFO5 FIFO4 FIFO3 FIFO2 FIFO1 FIFO0 R/W ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 W R WOR_SL7 RCOC7 WOR_SL6 RCOC6 WOR_SL5 RCOC5 WOR_SL4 RCOC4 WOR_SL3 RCOC3 WOR_SL2 RCOC2 WOR_SL1 RCOC1 WOR_SL0 RCOC0 W WOR_SL9 WOR_SL8 WOR_AC5 WOR_AC4 WOR_AC3 WOR_AC2 WOR_AC1 WOR_AC0 W RTCS RCOT2 R -- -- FI D EN TI A Bit 6 N 04h FIFO II 05h FIFO Data 06h ID Data 07h RC OSC I 08h RC OSC II Bit 7 C O 03h FIFO I R/W M Address / Name 00h Mode 01h Mode control 02h Calc RCOT1/ RTCC1 RCOT0/ RTCC0 CALWC RCOSC_E TSEL TWORE -- -- CALWR -- -- -- CKOE SCKI GIO1I GIO1OE GIO2I GIO2OE CGS -- XS -- CHN1 CHN0 CHR0 CHR0 BIP8 IP8 BIP1 BIP0 IP1 BFP9 AC9-FP9 BFP1 AC1-FP1 IP0 BFP8 AC8-FP8 BFP0 AC0-FP0 CHGL1 CHGL0 CHGH1 CHGH0 FDP1 FDP0 A M IC C O 0Ah W ECKOE CKOS3 CKOS2 CKOS1 CKOS0 CKOI CKO Pin 0Bh W VKM VPM GIO1S3 GIO1S2 GIO1S1 GIO1S0 GPIO1 Pin I 0Ch W BBCKS1 BBCKS0 GIO2S3 GIO2S2 GIO2S1 GIO2S0 GPIO2 Pin II W CGC1 CGC0 GRC3 GRC2 GRC1 GRC0 0Dh Clock R IFS1 IFS0 GRC3 GRC2 GRC1 GRC0 0Eh R/W CHN7 CHN6 CHN5 CHN4 CHN3 CHN2 PLL I W DBL RRC1 RRC0 CHR3 CHR2 CHR1 0Fh R DBL RRC1 RRC0 CHR3 CHR2 CHR1 PLL II 10h W BIP7 BIP6 BIP5 BIP4 BIP3 BIP2 PLL III R IP7 IP6 IP5 IP4 IP3 IP2 W BFP15 BFP14 BFP13 BFP12 BFP11 BFP10 11h PLL IV R FSYN-FP15 AC14-FP14 AC13-FP13 AC12-FP12 AC11-FP11 AC10-FP10 W BFP7 BFP6 BFP5 BFP4 BFP3 BFP2 12h PLL V AC6-FP6 AC5-FP5 AC4-FP4 AC3-FP3 AC2-FP2 R AC7-FP7 13h R/W CHGL7 CHGL6 CHGL5 CHGL4 CHGL3 CHGL2 Channel Group I 14h R/W CHGH7 CHGH6 CHGH5 CHGH4 CHGH3 CHGH2 Channel Group II 15h W GDR GF TMDE TXDI TME FDP2 TX I Mar., 2014, Version 1.0 Corporation L 9.1 Control register table 10 AMICCOM Electronics A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 W DPR2 DPR1 DPR0 TDL1 TDL0 PDL2 PDL1 PDL0 W WSEL2 WSEL1 WSEL0 RSSC_D1 RSSC_D0 RS_DLY2 RS_DLY1 RS_DLY0 W LNAGE AGCE RXSM1 RXSM0 AFCE RXDI DMG ULS W R W R W R PRS -RSAGC1 RH7 -RL7 MIC MICR RSAGC0 RH6 RDU RL6 IGC1 IGCR1 VTL2 RH5 IFS1 RL5 IGC0 IGCR0 VTL1 RH4 IFS0 RL4 MGC1 MGCR1 VTL0 RH3 RSM1 RL3 MGC0 MGCR0 VTH2 RH2 RSM0 RL2 LGC1 LGCR1 VTH1 RH1 W LIMC IFBC1 IFBC0 IFAS MHC1 M L W LHC1 LHC0 EN TI A RL1 LGC0 LGCR0 VTH0 RH0 RSS RL0 RTH5 RTH4 RTH3 RTH2 RTH1 RTH0 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 W AVSEL1 AVSEL0 MVSEL1 MVSEL0 RADC FSARS XADS CDM W MCS WHTS FECS CRCS IDL1 IDL0 PML1 PML0 W MSCRC EDRL HECS ETH2 ETH1 ETH0 PMD1 PMD0 W CRCINV WS6 WS5 WS4 WS3 WS2 WS1 WS0 W R W R HFR -PWORS -- CKGS1 -- CKGS0 -- MFBS FBCF MFB3 FB3 MFB2 FB2 MFB1 FB1 MFB0 FB0 TRT2 TRT1 TRT0 ASMV2 ASMV1 ASMV0 AMVS -- -- FCD4 FCD3 FCD2 FCD1 FCD0 W ROSCS RSIS VCRLS MVCS VCOC3 VCOC2 VCOC1 VCOC0 R -- -- -- VCCF VCB3 VCB2 VCB1 VCB0 W DCD1 DCD0 DAGS CWS MVBS MVB2 MVB1 MVB0 - - - - VBCF VB2 VB1 VB0 MDAG7 MDAG6 MDAG5 MDAG4 MDAG3 MDAG2 MDAG1 MDAG0 ADAG6 ADAG5 ADAG4 ADAG3 ADAG2 ADAG1 ADAG0 R C W M O R ADAG7 FI D RTH6 ADC7 C O RTH7 R N MHC0 ERSSM W IC 16h TX II 17h Delay I 18h Delay II 19h RX 1Ah RX Gain I 1Bh RX Gain II 1Ch RX Gain III 1Dh RX Gain IV 1Eh RSSI Threshold 1Fh ADC Control 20h Code I 21h Code II 22h Code III 23h IF Calibration I 24h IF Calibration II 25h VCO current Calibration 26h VCO band Calibration I 27h VCO band Calibration II 28h VCO deviation Calibration I 29h VCO deviation Calibration II 2Ah DASP0 W DEVS3 DEVS2 DEVS1 DEVS0 DAMR_M VMTE_M VMS_M MSEL R DEVA7 DEVA6 DEVA5 DEVA4 DEVA3 DEVA2 DEVA1 DEVA0 W MVDS MDEV6 MDEV5 MDEV4 MDEV3 MDEV2 MDEV1 MDEV0 R ADEV7 ADEV6 ADEV5 ADEV4 ADEV3 ADEV2 ADEV1 ADEV0 CSXTL4 CSXTL3 CSXTL2 CSXTL1 CSXTL0 QLIM RFSP DASP1 W STS CELS RGS RGC1 RGC0 VRPL1 VRPL0 INTPRC DASP2 W VTRB3 VTRB2 VTRB1 VTRB0 VMRB3 VMRB2 VMRB1 VMRB0 DASP3 W DCV7 DCV6 DCV5 DCV4 DCV3 DCV2 DCV1 DCV0 W VMG7 VMG6 VMG5 VMG4 VMG3 VMG2 VMG1 VMG0 R VMG7 VMG6 VMG5 VMG4 VMG3 VMG2 VMG1 VMG0 DASP5 W -- -- PKT1 PKT0 PKS PKIS1 PKIS0 IFPK DASP6 W -- HPLS HRS PACTL IWS CNT MXD LXD A W INTRC (CSXTL5) DASP4 Mar., 2014, Version 1.0 Corporation 11 AMICCOM Electronics A7137 DMV0 DEVFD2 DEVFD1 DEVFD0 DEVD2 DEVD1 DEVD0 W LVR RGV1 RGV0 QDS BVT2 BVT1 BVT0 BD_E R -- RGV1 RGV0 BDF BVT2 BVT1 BVT0 BD_E RMP0 TXCS PAC1 PAC0 TBG2 TBG1 TBG0 DCM1 DCM0 MLP1 MLP0 SLF2 SLF1 DCH0 DCL2 DCL1 DCL0 RAW CDTM1 CDTM0 CPM2 CPM1 CPM0 CPT3 CPT2 CPT1 CPT0 CPTX2 CPTX1 CPTX0 CPRX3 CPRX2 CPRX1 CPRX0 CPS CPH CPCS DBD XCC XCP1 XCP0 OLM PRIC1 PRIC0 PRRC1 PRRC0 SDPW NSDO DEVGD1 DEVGD0 TLB1 TLB0 RLB1 RLB0 VBS AGT2 AGT1 AGT0 RFT3 RFT2 RFT1 RFT0 KEY6 KEY5 KEY4 KEY3 KEY2 KEY1 KEY0 CHI2 CHI1 CHI0 CHD3 CHD2 CHD1 CHD0 EPRG MIGS MRGS MRSS MTMS MADS MBGS MPA1 PTM0 -STMP MPA0 CTR5 FBG4 CTR4 FBG3 CTR3 FBG2 CTR2 FBG1 CTR1 FBG0 CTR0 CRS2 CRS1 CRS0 CTS2 CTS1 CTS0 STM5 STM4 STM3 STM2 STM1 STM0 SDR6 SDR5 SDR4 SDR3 SDR2 SDR1 SDR0 FCL0 VPOAK ARC3 RCR3 ARC2 RCR2 ARC1 RCR1 ARC0 RCR0 EACKS EACKS EARTS EARTS ARD6 ARD5 ARD4 ARD3 ARD2 ARD1 ARD0 SPSS -- ACKFEP5 EARTS ACKFEP4 EARTS ACKFEP3 EARTS ACKFEP2 TXSID2 ACKFEP1 TXSID1 ACKFEP0 TXSID0 F6 F5 F4 F3 F2 F1 F0 AFIDS ARTMS MIDS AESS -- AKFS EDCRS RND6 RND5 RND4 RND3 RND2 RND1 RND0 A M IC C O M Mar., 2014, Version 1.0 Corporation TI A EN 2Dh RMP1 W TX test 2Eh W DMT Rx DEM test I 2Fh W DCH1 Rx DEM test II 30h CPM3 W Charge Pump Current I 31h W CPTX3 Charge Pump Current II 32h W CDPM Crystal test 33h MDEN W PLL test 34h DEVGD2 W VCO test 35h AGT3 W RF Analog test 36h KEY7 W/R Key Data 37h W CHI3 Channel Select 38h W MPOR ROM_P0 ROMP1 W APG ROMP2 W PTM1 ROMP3 W -ROMP4 W -39h W SDR7 Data Rate CLK W FCL1 3Ah FCR R ARTEF 3Bh W ARD7 ARD W EACKF 3Ch AFEP -R 3Dh W/R F7 FCB 3Eh W MEDCS KEYC 3Fh RND7 W USID Legend: -- = unimplemented L DMV1 FI D 2Ch Battery detect W C O 2Bh VCO modulation Delay N 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 12 SLF0 AMICCOM Electronics A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 9.2 Control register description 9.2.1 Mode Register (Address: 00h) Name R/W Mode R W Bit 7 Bit 6 HECF FECF RESETN RESETN Bit 5 CRCF RESETN Bit 4 Bit 3 CER RESETN XER RESETN Bit 2 PLLER RESETN Bit 1 TRSR RESETN L RESETN: Write to this register by 0x00 to issue reset command, then it is auto clear TI A HECF: Head Control Flag. (HECF will be clear after issue a strobe command.) HEC is CRC-8 result for the optional Packet Header (Please refer to chapter 16 for details) [0]: HEC pass. [1]: HEC error. FI D CER: RF chip enable status. [0]: RF chip is disabled. [1]: RF chip is enabled. EN FECF: FEC flag. (FECF will be clear after issue any strobe command.) [0]: FEC pass. [1]: FEC error. (FECF is read clear.) CRCF: CRC flag. (CRCF will be clear after issue any strobe command.) [0]: CRC pass. [1]: CRC error. (CRCF is read clear.) Bit 0 TRER RESETN XER: Internal crystal oscillator enabled status. [0]: Crystal oscillator is disabled. [1]: Crystal oscillator is enabled. TRSR: TRX Status Register. [0]: RX state. [1]: TX state. Serviceable if TRER=1 (TRX is enable). (Address: 01h) M 9.2.2 Mode Control Register C O TRER: TRX state enabled status. [0]: TRX is disabled. [1]: TRX is enabled. N PLLE: PLL enabled status. [0]: PLL is disabled. [1]: PLL is enabled. R/W Bit 7 Mode Control I R W DDPC DDPC O Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ARSSI ARSSI AIF AIF DFCD CD WORE WORE FMT FMT FMS FMS ADCM ADCM C DDPC (Direct mode data pin control): Direct mode modem data can be accessed via SDIO pin. [0]: Disable. [1]: Enable. IC ARSSI: Auto RSSI measurement while entering RX mode. [0]: Disable. [1]: Enable. M AIF (Auto IF Offset): RF LO frequency will auto offset one IF frequency while entering RX mode. [0]: Disable. [1]: Enable. A CD: Carrier detector (Read only). [0]: Input power below threshold. [1]: Input power above threshold. DFCD: Data Filter by CD : The received packet would be filtered if the input power level is below RTH (1Eh). [0]: Disable. [1]: Enable. WORE: WOR (Wake On RX) Function Enable. [0]: Disable. [1]: Enable. FMT: Reserved for internal usage only. Shall be set to [0]. FMS: Direct/FIFO mode select. [0]: Direct mode. [1]: FIFO mode. ADCM: ADC measurement enable (Auto clear when done). [0]: Disable measurement or measurement finished. [1]: Enable measurement. Mar., 2014, Version 1.0 Corporation 13 AMICCOM Electronics A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver Refer to chapter 17 for details. 9.2.3 Calibration Control Register (Address: 02h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mode Control II R/W -- -- -- VCC VBC VDC FBC RSSC VCC: VCO Current calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. TI A L VBC: VCO Bank calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. VDC: VCO Deviation calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. EN FBC: IF Filter Bank calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. RSSC: RSSI calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. FI D 9.2.4 FIFO Register I (Address: 03h) R/W Bit 15 Bit 14 Bit 13 Bit 12 FIFO I W R W R --FEP7 LENF7 --FEP6 LENF6 --FEP5 LENF5 --FEP4 LENF4 Bit 11 Bit 10 FEP11 FEP10 LENF11 LENF10 FEP3 FEP2 LENF3 LENF2 Bit 9 Bit 8 FEP9 LENF9 FEP1 LENF1 FEP8 LENF8 FEP0 LENF0 C O FEP [11:0]: FIFO End Pointer for TX FIFO and Rx FIFO. Data Sequence is FEP[7:0] and FEP[15:8]. Please refer to chapter 16 for details. N Name M LENF [11:0]: Received FIFO Length for dynamic FIFO function. (Ready Only) When EDRL =1, that means dynamic FIFO is enabled, MCU can read LENF [11:0] to know the RX FIFO length of the coming packet. Please refer to chapter 16 for details. O 9.2.5 FIFO Register II (Address: 04h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFO II W FPM1 FPM0 PSA5 PSA4 PSA3 PSA2 PSA1 PSA0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C Name FPM [1:0]: FIFO Pointer Margin IC PSA [5:0]: Used for Segment FIFO. Refer to chapter 16 for details. M 9.2.6 FIFO DATA Register (Address: 05h) R/W Name W R/W A Bit Bit 7 Bit 6 TX-FIFO[7:0] RX-FIFO[7:0] FIFO [7:0]: TX FIFO / RX FIFO TX FIFO and RX FIFO share the same address (05h). TX FIFO and RX FIFO are separated physical 64 Bytes. Refer to chapter 16 for details. 9.2.7 ID DATA Register (Address: 06h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID DATA R/W ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 ID [7:0]: ID data. Mar., 2014, Version 1.0 Corporation 14 AMICCOM Electronics A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver When this address is accessed, ID Data is input or output sequential (ID Byte 0,1, 2 and 3) corresponding to Write or Read. Recommend to set ID Byte 0 = 5xh or Axh. Refer to section 10.6 for details. 9.2.8 RC OSC Register I (Address: 07h) RC OSC I R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 RCOC [7:0]: Reserved for internal usage (read only). 9.2.9 RC OSC Register II (Address: 08h) R/W W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FI D WOR_SL [9:0]: 10-bits WOR Sleep Timer for WOR and TWOR Function. WOR_SL [9:0] are from address (07h) and (08h), Active period = (WOR_AC+1) x (1/4092). Sleep period = (WOR_SL+1) x (1/32) x (1/4092). Bit 7 Bit 6 W RTCS RCOT2 R -- -- Bit 5 Bit 4 RCOT1/ RTCC1 -- RCOT0/ RTCC0 -- C O R/W N 9.2.10 RC OSC Register III (Address: 09h) RC OSC III Bit 0 WOR_SL9 WOR_SL8 WOR_AC5 WOR_AC4 WOR_AC3 WOR_AC2 WOR_AC1 WOR_AC0 WOR_AC [5:0]: 6-bits WOR Active Timer for WOR and TWOR Function Name Bit 1 EN Name RC OSC II Bit 2 RCOC7 RCOC6 RCOC5 RCOC4 RCOC3 RCOC2 RCOC1 RCOC0 WOR_SL7 WOR_SL6 WOR_SL5 WOR_SL4 WOR_SL3 WOR_SL2 WOR_SL1 WOR_SL0 L R/W TI A Name Bit 3 Bit 2 Bit 1 Bit 0 CALWC RCOSC_E TSEL TWORE CALWR -- -- -- RTCS: internal Oscillator selection in sleep mode. [0]: RC oscillator. [1]: RTC oscillator. M RCOT[2]: Reserved for internal used. Recommend [0] O RCOT[1:0]: RCOSC current select for RC oscillator calibration. [00]: 240nA [01]: 280nA [10]: 320nA [11]: 360nA C TSEL: Timer select for TWOR function. [0]: Use WOR_AC. [1]: Use WOR_SL. IC CALWC: RC Oscillator Calibration Enable. [0]: Disable. [1]: Enable. M CALWR: RC Oscillator Calibration ending indication. [0]: ending. [1]: Not ending. A RCOSC_E: RC-oscillator enable. [0]: Disable. [1]: Enable. TSEL: Timer Duty select for TWOR function. [0]: Use WOR_AC. [1]: Use WOR_SL. TWORE: Enable TWOR function. [0]: WOR mode. [1]: TWOR mode. 9.2.11 CKO Pin Control Register (Address: 0Ah) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CKO Pin Control W ECKOE CKOS3 CKOS2 CKOS1 CKOS0 CKOI CKOE SCKI ECKOE: CKO pin Output Enable. [0]: Disable. [1]: Enable. Mar., 2014, Version 1.0 Corporation 15 AMICCOM Electronics A7137 TI A EN CKOS [3:0]: CKO pin output select. [0000]: DCK (TX data clock) in TX mode, RCK (RX recovery clock) in RX mode. [0001]: DCK (TX data clock) in TX mode, RCK (RX recovery clock) in RX mode. [0010]: FPF (FIFO pointer flag). [0011]: EOP, EOVBC, EOFBC, EOVCC, EOVDC, RSSC_OK. (Internal usage only). [0100]: External clock output= FSYCK / 2. [0101]: External clock output / 2= FSYCK / 4. [0110]: RXD [0111]: FSYNC. [1000]: WCK. [1001]: PF8M.(8Mhz, internal usage) [1010]: ROSC. [1011]: MXDEC(SLF[0]=1:~OKADCN, SLF[1]=0: DEC , internal usage) [1100]: BDF (Battery Detect flag). [1101]: FSYCK .. [1110]: VPOAK. [1111]: WRTC (internal usage) L 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver FI D CKOI: CKO pin output signal invert. [0]: Non-inverted output. [1]: Inverted output. CKOE: CKO pin Output Enable. [0]: High Z. [1]: Enable. N SCKI: SPI clock input invert. [0]: Non-inverted input. [1]: Inverted input. 9.2.12 GIO1 Pin Control Register I (Address: 0Bh) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W VKM VPM GIO1S3 GIO1S2 GIO1S1 GIO1S0 GIO1I GIO1OE C O Name GIO1 Pin Control I VPM: Valid Pulse width select. [0]: 20u. [1]: 40u. M VKM: Valid packet mode select. [0]: by event. [1]: by pulse. A M IC C O GIO1S [3:0]: GIO1 pin function select. GIO1S [3:0] TX state RX state [0000] WTR (Wait until TX or RX finished) [0001] EOAC (end of access code) FSYNC (frame sync) [0010] TMEO (TX modulation enable) CD (carrier detect) [0011] Preamble Detect Output (PMDO) [0100] If RCOSC_E =1, output TWOR. If RCOSC_E =0, output CWTR signal. (internal usage) [0101] In phase demodulator input(DMII)or VT[0] (internal usage) [0110] SDO ( 4 wires SPI data out) [0111] TRXD In/Out (Direct mode) [1000] RXD (Direct mode) [1001] TXD (Direct mode) [1010] PDN_RX External FSYNC input in RX direct mode (internal usage) [1011] [1100] MXINC(SLF[0]=1:EOADC.SLF[1]=0:INC.) (internal usage) [1101] FPF [1110] VPOAK (Valid Packet or Auto ACK OK Output) [1111] FMTDO (internal usage) If GIO1S = [0100] and RCOSC_E = 0, CWTR is an internal signal to monitor TX/RX cycles of auto-ack and auto-resend.If GIO1S = [1011] and direct mode is selected, the internal frame sync function will be disabled. In such case, A7137 supports Mar., 2014, Version 1.0 Corporation 16 AMICCOM Electronics A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver to accept an external frame sync signal from MCU to feed to GIO1 pin to determine the timing of fixing DC estimation voltage of demodulator. GIO1I: GIO1 pin output signal invert. [0]: Non-inverted output. [1]: Inverted output. 9.2.13 GIO2 Pin Control Register II (Address: 0Ch) L GIO1OE: GIO1pin output enable. [0]: High Z. [1]: Enable. R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIO2 Pin Control II W BBCKS1 BBCKS0 GIO2S3 GIO2S2 GIO2S1 GIO2S0 GIO2I GIO2OE BBCKS [1:0]: Clock select for digital block. Recommend BBCKS = [00]. [00]: FSYCK. [01]: FSYCK / 2. [10]: FSYCK / 4. [11]: FSYCK / 8. TI A Name O M C O N FI D EN GIO2S [3:0]: GIO2 pin function select. GIO2S TX state RX state [0000] WTR (Wait until TX or RX finished) [0001] EOAC (end of access code) FSYNC (frame sync) [0010] TMEO (TX modulation enable) CD (carrier detect) [0011] Preamble Detect Output (PMDO) [0100] If RCOSC_E =1, output TWOR. If RCOSC_E =0, output CWTR signal. (internal usage) [0101] Quadrature phase demodulator input (DMIQ) (internal usage) [0110] SDO (4 wires SPI data out) [0111] TRXD In/Out (Direct mode) [1000] RXD (Direct mode) [1001] TXD (Direct mode) [1010] PDN_TX [1011] ROMOK(ROM Program OK) (internal usage) [1100] BDF (Battery Detect Flag) [1101] FPF [1110] VPOAK (Valid Packet or Auto ACK OK Output) [1111] DCK (internal usage) If GIO2S = [0100] and RCOSC_E = 0, CWTR is an internal signal to monitor TX/RX cycles of auto-ack and auto-resend. C GIO2I: GIO2 pin output signal invert. [0]: Non-inverted output. [1]: Inverted output. A M In TX mode IC GIO2OE: GIO2 pin Output Enable. [0]: High Z. [1]: Enable. Mar., 2014, Version 1.0 Corporation 17 AMICCOM Electronics A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver SPI (SCS,SCK,SDIO) TX-Strobe Next Instruction No Command Required PLL Mode Auto Back PLL Mode 10 us + (PDL+TDL) RF Port Preamble + ID Code + Payload + CRC (Output) GIO2 Pin - TMEO (GIO2S[3:0]=0010) 16 us TI A L GIO1 Pin - WTR (GIO1S[3:0]=0000) T0 EN PA Ramp Down T2 T1 < 1us SPI (SCS,SCK,SDIO) FI D In RX mode T3 RX-Strobe Next Instruction No Command Required PLL Mode 10us+PDL+TDL RF Port (Input) Auto Back PLL Mode N Preamble + ID Code + Payload + CRC C O GIO1 Pin - WTR (GIO1S[3:0]=0000) M GIO2 Pin - FSYNC (GIO2S[3:0]=0001) O T2 T1 C T0 ID-Matched IC < 1us 9.2.14 Clock Register (Address: 0Dh) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W R CGC1 IFS1 CGC0 IFS0 GRC3 GRC3 GRC2 GRC2 GRC1 GRC1 GRC0 GRC0 CGS -- XS -- M Clock R/W A CGC [1:0]: Clock Gen. Current select. Shall be set to [01]. GRC [3:0]: Clock generation reference counter. Recommend GRC = [01111]. GRC [3:0] is used to let below formula be true when CGS = 1. FXTAL x (DBL+1) / (GRC+1) = 2MHz. CGS: Clock generator enable. Recommend CGS = [1]. [0]: Disable. [1]: Enable. XS: Crystal oscillator select. Recommend XS = [1] [0]: External clock. [1]: Crystal. IFS [1:0]: IF band selection. (Ready only) Mar., 2014, Version 1.0 Corporation 18 AMICCOM Electronics A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 9.2.15 PLL Register I (Address: 0Eh) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLL I R/W CHN7 CHN6 CHN5 CHN4 CHN3 CHN2 CHN1 CHN0 9.2.16 PLL Register II (Address: 0Fh) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 PLL II R W DBL DBL RRC1 RRC1 RRC0 RRC0 CHR3 CHR3 CHR2 CHR2 CHR1 CHR1 RRC [1:0]: RF PLL reference counter setting. Recommend RRC = [00]. The PLL comparison frequency, FPFD = FCRYSTAL *(DBL+1) / (RRC+1). 9.2.17 PLL Register III (Address: 10h) R/W Bit 7 Bit 6 Bit 5 PLL III R W IP7 BIP7 IP6 BIP6 IP5 BIP5 IP8 BIP8 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IP4 BIP4 IP3 BIP3 IP2 BIP2 IP1 BIP1 IP0 BIP0 Bit 2 Bit 1 Bit 0 N Name FI D CHR [3:0]: PLL channel step setting. Recommend CHR = [0111]. Refer to chapter 14 for details. Bit 0 CHR0 CHR0 EN DBL: Crystal frequency doublers selection. Recommend DBL = [0] [0]: Disable. FXREF = FXTAL. [1]: Enable. FXREF =2 * FXTAL. Bit 1 TI A Name L CHN [7:0]: LO channel number select. Refer to chapter 14 for details. IP [8:0]: LO frequency integer part value. IP [8:0] are from address (0Fh) and (10h), Refer to chapter 14 for details. C O BIP [8:0]: LO base frequency integer part setting. Recommend BIP[8:0] = [0x096] BIP [8:0] are from address (0Fh) and (10h), PLL IV R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 RAC15 RAC14 RAC13 RAC12 RAC11 RAC10 RAC9 RAC8 BFP15 BFP14 BFP13 BFP12 BFP11 BFP10 BFP9 BFP8 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 O R/W C Name M 9.2.18 PLL Register IV (Address: 11h) R/W Bit 7 Bit 6 R W RAC7 RAC6 RAC5 RAC4 RAC3 RAC2 RAC1 RAC0 BFP7 BFP6 BFP5 BFP4 BFP3 BFP2 BFP1 BFP0 Bit 1 CHGL1 Bit 0 CHGL0 Name M PLL V IC 9.2.19 PLL Register V (Address: 12h) A BFP [15:0]: LO base frequency fractional part setting. Recommed BFP[15:0] = [0x0004]. BFP [15:0] are from address (11h) and (12h), RAC [15:0]: Auto Frequency compensation value if AFC (19h) =1. RAC [15:0] Note AFC = 1 PLLFF [15:0] LO Freq. compensation value AFC = 0 {SYNCF, AC [14:0]} 9.2.20 Channel Group Register I (Address: 13h) Name R/W CHGI R/W Bit 7 CHGL7 Bit 6 CHGL6 Bit 5 CHGL5 Bit 4 CHGL4 Bit 3 CHGL3 Bit 2 CHGL2 CHGL [7:0]: PLL channel group low boundary setting for auto-calibration. Recommed CHGL[7:0] = 0x3C. Refer to A7137 reference code for details. Mar., 2014, Version 1.0 Corporation 19 AMICCOM Electronics A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 9.2.21 Channel Group Register II (Address: 14h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CHGII R/W CHGH7 CHGH6 CHGH5 CHGH4 CHGH3 CHGH2 CHGH1 CHGH0 CHGH [7:0]: PLL channel group high boundary setting for auto-calibration. Recommed CHGH[7:0] = 0x78. Refer to A7137 reference code for details. TI A L PLL calibration frequency is divided into 3 groups by CHGL and CHGH: Channel Group1 0 ~ CHGL-1 Group2 CHGL ~ CHGH-1 Group3 CHGH ~ 255 EN 9.2.22 TX Register I (Address: 15h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TX I W GDR GF TMDE TXDI TME FDP2 FDP1 FDP0 FI D GDR: Gaussian Filter Over Sampling Rate Select. [0]: BT= 0.7 [1]: BT= 0.5 GF: Gaussian Filter Select. [0]: Disable. [1]: Enable. N TMDE: TX modulation enable for VCO modulation. Recommend TMDE = [1]. [0]: Disable. [1]: Enable. C O TXDI: TX data invert. Recommend TXDI = [0]. [0]: Non-invert. [1]: Invert. TME: TX modulation enable. [0]: Disable. [1]: Enable. M FDP [2:0]: Frequency deviation power setting. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FD6 FD5 FD4 FD3 FD2 FD1 FD0 9.2.23 TX Register II (Address: 16h) R/W TXI W Bit 7 O Name FD7 A M Data Rate 2Mbps 1Mbps 500Kbps IC C FD [7:0]: Frequency deviation setting. FDEV = (FPFD /216) x FD[7:0] x 2(FDP-1). Where FPFD= FXTAL * (DBL+1) / (RRC [1:0]+1), PLL comparison frequency. FDP[2:0] 110 101 101 FD[7:0] 0x40 0x40 0x30 Fdev 500KHz 250KHz 187.5KHz 9.2.24 Delay Register I (Address: 17h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Delay W DPR2 DPR1 DPR0 TDL1 TDL0 PDL2 PDL1 PDL0 DPR [2:0]: Delay scale. Recommend DPR = [000]. TDL [1:0]: Delay for TX settling from WPLL to TX. TDL Delay= 20 * (TDL [1:0]+1)*(DPR [2:0]+1) us. DPR [2:0] 000 000 Mar., 2014, Version 1.0 Corporation TDL [1:0] 00 01 WPLL to TX 20 us 40 us Note 20 AMICCOM Electronics A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 000 000 10 11 60 us 80 us Recommend PDL [2:0]: Delay for TX settling from PLL to WPLL. PDL Delay= 10 + {20 * (PDL [2:0]+1)*(DPR [2:0]+1)} us. 000 001 010 011 100 PLL M ode Note Recommend TX M ode G IO 1 P in (W T R ) T X S tro be R F O P in L 000 000 000 000 000 PLL to WPLL (LO freq changed) 30 us 50 us 70 us 90 us 110 us TI A PDL [2:0] EN DPR [2:0] PA Ramp Down 10 u s + P D L TDL 9.2.25 Delay Register II (Address: 18h) R/W Bit 7 Bit 6 Bit 5 Delay W WSEL2 WSEL1 WSEL0 Bit 4 Bit 3 N Name FI D P a ck e t Bit 2 16 u s Bit 1 Bit 0 C O RSSC_D1 RSSC_D0 RS_DLY2 RS_DLY1 RS_DLY0 C ry s ta l O sc illa to r Id le m o de O 30 0 us M WSEL [2:0]: XTAL settling delay setting (200us ~ 2.5ms). Recommend WSEL = [010]. [000]: 200us. [001]: 400us. [010]: 600us. [011]: 800us. [100]: 1ms. [101]: 1.5ms. [110]: 2ms. [111]: 2.5ms. C G IO 1 P in (W T R ) P a ck e t ( P r e a m b le + ID + P a ylo a d ) 10 us + PD L TD L IC R F O P in T X or R X S tro be C m d W SEL M RSSC_D [1:0]: RSSI calibration switching time (10us ~ 40us). Recommend RSSC_D = [00]. [00]: 10us. [01]: 20us. [10]: 30us. [11]: 40us. A RS_DLY [2:0]: RSSI measurement delay (10us ~ 80us). Recommend RS_DLY = [000]. [000]: 10us. [001]: 20us. [010]: 30us. [011]: 40us. [100]: 50us. [101]: 60us. [110]: 70us. [111]: 80us. 9.2.26 RX Register (Address: 19h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RX W LNAGE AGCE RXSM1 RXSM0 AFCE RXDI DMG ULS LNAGE: Auto LNA Gain Control Select. [0]: Disable. [1]: Enable. AGCE: Auto Front end Gain Control Select. [0]: Disable. [1]: Enable. RXSM1: RX clock recovery circuit moving average filter length. Recommend RXSM1 = [1]. Mar., 2014, Version 1.0 Corporation 21 AMICCOM Electronics A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver [0]: 4 bits. [1]: 8 bits. RXSM0: Demodulator LPF Bandwidth Select. Recommend RXSM0 = [1]. [0]: 2*IF. [1]: 1*IF. AFCE: Frequency compensation select. [0]: Disable. [1]: Enable. L RXDI: RX data output invert. Recommend RXDI = [0]. [0]: Non-inverted output. [1]: Inverted output. TI A DMG: Demodulator Gain Select. Recommend DMG = [0]. [0]: x 1. [1]: x 3. EN ULS: RX Up/Low side band select. Recommend ULS = [0]. [0]: Up side band, [1]: Low side band. Refer to section 14.2 for details. 9.2.27 RX Gain Register I (Address: 1Ah) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RX Gain I W R PRS -- MIC MICR IGC1 IGCR1 IGC0 IGCR0 MGC1 MGCR1 MGC0 MGCR0 LGC1 LGCR1 LGC0 LGCR0 Bit 3 Bit 2 Bit 1 Bit 0 FI D Name PRS: Limiter amplifier discharge manual select. Recommend PRS =[0]. N MIC: Mixer buffer gain setting. Recommend MIC =[1]. [0]: 0dB. [1]: 6dB. C O IGC [1:0]: IFA Attenuation Select. Recommend IGC =[10]. [00]: 0dB. [01]: 6dB. [10]: 12dB. [11]: 18dB. MGC [1:0]: Mixer Gain Attenuation select. Recommend MGC =[11]. [00]: 0dB. [01]: 6dB. [10]: 12dB. [11]: 18dB. M LGC [1:0]: LNA Gain Attenuation select. Recommend LGC =[11]. [00]: 0dB. [01]: 6dB. [10]: 12dB. [11]: 18dB. 9.2.28 RX Gain Register II (Address: 1Bh) RX Gain II R W Bit 7 O R/W Bit 6 Bit 5 Bit 4 RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 RSAGC1 RSAGC0 VTL2 VTL1 VTL0 VTH2 VTH1 VTH0 C Name IC RSAGC [1:0]: AGC clock select. Recommend RSAGC = [11]. [00]: IF / 8. [01]: IF / 4. [10]: IF / 2. [11]: IF. M VTL [2:0]: VCO tuning voltage lower threshold level setting. Recommend VTL = [000]. [000]: 0.1V. [001]: 0.2V. [010]: 0.3V. [011]: 0.4V. [100]: 0.5V. [101]: 0.6V. [110]: 0.7V. [111]: 0.8V A VTH [2:0]: VCO tuning voltage upper threshold level setting. Recommend VTH = [010]. [000]: VDD_A – 0.6V. [001]: VDD_A – 0.7V. [010]: VDD_A – 0.8V. [011]: VDD_A – 0.9V [100]: VDD_A – 1.0V. [101]: VDD_A – 1.1V. [110]: VDD_A – 1.2V. [111]: VDD_A – 1.3V Remark: VDD_A is on chip analog regulator output voltage where is set to 1.8V. RH [7:0]: RSSI Calibration High Threshold. (Read only) 9.2.29 RX Gain Register III (Address: 1Ch) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RX Gain III R W RL7 -- RL6 RDU RL5 IFS1 RL4 IFS0 RL3 RSM1 RL2 RSM0 RL1 ERSSM RL0 RSS RDU: Clock Generator Select. Recommend RDU = [0]. Mar., 2014, Version 1.0 Corporation 22 AMICCOM Electronics A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver [0]: 128MHZ [1]: 96MHZ. IFS [1:0]: IF Frequency Select. [00]:1MHZ. [01]: 2MHz. [10]: Reserved. [11]: Reserved. L IFS [1:0] 01 00 00 TI A Data rate 2Mbps 1Mbps 2.1V, BDF = 1 (battery high). Else, BDF = 0 (battery low). A M IC C O M C O 1. 2. 3. 4. FI D Below is the procedure to detect low voltage input (ex. below 2.1V): Mar., 2014, Version 1.0 73 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 19. Auto-ack and auto-resend A7137 supports auto-resend and auto-ack scheme by enable EAK = 1 (auto-ack) and EAR = 1 (auto-resend). In application points of view, this feature is also ok to enable together with other feature options like FCB and/or EDRL (dynamic FIFO). 19.1 Basic FIFO plus auto-ack auto-resend M IC C O M C O N FI D EN TI A L Set EAF = 0, EAK = 1 and EAR = 1 to enable auto-ack and auto-resend. Please refer to the below TX and ACK packet format of the sender and the receiver site respectively. 19.2 Advanced FIFO plus auto-ack and auto-resend A In addition to set EAF = 0, EAK = 1 and EAR = 1 to enable auto-ack and auto-resend. User can also enable an optional MAC header (FCB field) in the TX packet together with auto-ack and auto resend scheme. Please refer to the below TX and ACK packet format of the sender and the receiver site. Mar., 2014, Version 1.0 74 AMICCOM Electronics Corporation A7137 A M IC C O M C O N FI D EN TI A L 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver Mar., 2014, Version 1.0 75 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 19.3 WTR Behavior during auto-ack and auto-resend If auto-ack and auto-resend are enabled (EAR = EAK = 1), WTR represents a completed transmission period and CWTR is a debug signal which represents the cyclic TX period and cyclic RX period. Please refer to the below timing diagrams for details. C O N FI D EN TI A L The sender site (auto-resend) A M IC C O M The receiver site (auto-ack) Remark: Refer to 3Bh for ARD[7:0] setting (auto resend delay). Refer to 3Fh for RND[7:0] setting (random seed for resend interval). Refer to 3Ah for EAK (enable auto-ack). Refer to 3Ah for EAR (enable auto-resend). Refer to 0Bh for VKM and VPM. Mar., 2014, Version 1.0 76 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 19.6 Examples of auto-ack and auto-resend Once EAK and EAR are enabled, below case 1 ~ case 3 illustrate the most common cases as a timing reference (assume ARD = 800 us) in two ways radio communications. Always success Success in second packet A M IC C O M C O N FI D EN TI A L Mar., 2014, Version 1.0 77 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver always resend failure A M IC C O M C O N FI D EN TI A L Mar., 2014, Version 1.0 78 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 20. RC Oscillator A7137 has an internal RC oscillator to supports WOR (Wake On RX) and TWOR (Timer Wake On RX) function. RCOSC_E (09h) is used to enable RC oscillator. WORE (01h) is used to enable WOR function and TWORE (09h) is used to enable TWOR function. After done calibrations of RC oscillator, WOR and TWOR function can be operated from -40℃ to 85℃. Max 4.2K 8007.68 85 Unit Hz ms ms ℃ Note [( WOR_SL [9:0] ) +1] x 7.8 ms [( WOR_AC [5:0] ) +1] x 244 us After calibration. L Min 3.8K 7.82 0.244 -40 TI A Parameter Calibrated Freq. Sleep period RX period Operation temperature 20.1 WOR Function EN When WOR is enabled (WORE = 1 and RCOSC_E =1), A7137 periodically wakes up from sleep and listen (auto-enter RX mode) for incoming packets without MCU interaction. Therefore, A7137 will stay in sleep mode based on WOR_SL timer and RX mode based on WOR_AC timer unless a packet is received. Strobe CMD (SCS,SCK,SDIO) C O N FI D The internal RC oscillator used for the WOR function varies with temperature and CMOS process deviation. In order to keep the frequency as accurate as possible, the RC oscillator shall be calibrated (CALWC=1) whenever possible. After done calibrations, MCU shall set WORE=1 and issue sleep strobe command to start WOR function. After a period (WOR_SL) in sleep mode, the device goes to RX mode to check coming packets. And then, A7137 is back to sleep mode for the next WOR cycle. To end up WOR function, MCU just needs to set WORE = 0. Beware, please turn on MSCRC (21h, CRC data filtering) when CRCS = 1 (20h, CRC select) in WOR function. sleep RF In Pin M GIO1 -- WTR GIO1S[3:0]=0000 Strobe cmd No Command Required Sleep WOT_SL[9:0] RX O Sleep WOR_SL[9:0] Start WOR (sleep strobe) Coming packet RX A M IC C End of WOR (set WORE = 0) Mar., 2014, Version 1.0 79 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 20.2 TWOR Function FI D EN TI A L The RC oscillator inside A7137 can also be used to supports programmable TWOR (Timer Wake-On, TWORE=1) function which enables A7137 to output a periodic square wave from GIO1 (or GIO2). The duty cycle of this square wave is set by WOR_AC (08h) or WOR_SL (08h and 07h) regarding to TSEL (09h). User can use this square wave to wake up MCU or other purposes. 21. AES128 Security Packet N A7137 has a built-in AES128 co-processor to generate a security packet by a general purpose MCU. In addition to support 128-bits key length (AES128), A7137 also support a proprietary 32-bits key length called AES32. O M C O Software procedure to use AES128. Step1: Write 16-bytes AES128 key to KEYI [127:0] (36h) Step2: Set AESS=1 (3Eh) to select standard AES128 Step3. Set AKFS=0 (3Eh) to disable attaching AES128 KEYI [127:0] into the TX packet. Step4: Set EDCRS=1 (3Eh) to enable AES co-processor. Step5: Write plain text to TX FIFO Step6: Issue TX strobe command and then A7137 will execute AES128 encryption and deliver the cipher text without latency. Step7: In RX side with the same configurations, A7137 will execute AES128 decryption and store plain text back to RX FIFO. IC C Remark 1. The unit size of AES128 encryption packet is 16-bytes. 2. In TX side, if plain text is not dividable by 16-bytes, i.e. 5-bytes only, the TX packet is complement to be 16-bytes. 3. In RX side, the coming cipher text will be decrypted and restore 5-bytes plain text back to RX FIFO. A M Software procedure to use AES32. Step1: Write 4-bytes AES128 key to KEYI [31:0] (36h) Step2: Set AESS=0 (3Eh) to select proprietary AES32. Step3. Set AKFS=0 (3Eh) to not attach AES128 KEYI [31:0] to the wanted TX packet. Step4: Set EDCRS=1 (3Eh) to enable AES co-processor. Step5: Write plain text to TX FIFO Step6: Issue TX strobe command and then A7137 will execute AES32 encryption and deliver the cipher text without latency. Step7: In RX side with the same configurations, A7137 will execute AES32 decryption and store plain text back to RX FIFO. Remark 1. The unit size of AES32 encryption packet is 4-bytes. 2. In TX side, if plain text is not dividable by 4-bytes, i.e. 5-bytes only, the TX packet is complement to 8-bytes. 3. In RX side, the coming cipher text will be decrypted and restore 5-bytes plain text back to RX FIFO. Mar., 2014, Version 1.0 80 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 22. Application circuit 22.1 MD7137-A01 AMICCOM’s ref. design module, MD7137-A01, 10 dBm output power, application circuit example. J2 2.2uF VDD_A 100nH 5 C8 0.1uF VIN CKO GIO2 GIO1 18 17 16 GIO2 CKO REGI GIO1 SCS L SDIO 14 C7 13 VDD_D 2.2uF 12 SCK SCS 11 A7137_PKG R1 NC VDD_A Y1 16M X'tal C10 NC M C11 2.2nF C12 0.1uF C13 NC 4 3 GND 1 O C14 U2 →30ppm CL:18pF Y2 XTAL_2.5*2 GND NC 2 Y3 XTAL_3.2*2.5 C 4 3 GND GND 2 IC 1 M Remark RF Matching to 50Ω. RX and TX signal are separated from RFI and RFO pin so that (DASP0 register = 0x34). Recommend 16MHz crystal with 18 pF Cload. Recommend to let C12 and C13 NC because of enabling on-chip Xtal Capacitors by (INTXC = 1 and CSXTAL = [10100]). A 1. 2. 3. 4. SCK CON/2P 2.0 15 C9 0.1uF C O C17 0.1uF TI A VDD_A 19 RFC 6 VDD_A VDD_D A7137_PKG RFO N VIN RFI 1 2 CON/10P 2.0 EN 4 J3 XO RFO CON/2P 2.0 10 L3 1.8nH 3 XI 18pF RFI SDIO 9 10nF C20 0.5pF L4 L2 2.4nH GND BP_BG VDD_PLL C16 BP_RSSI CP C19 2 8 L5 3nH C3 1.2pF 1 VDD_A C15 NC L1 2.7nH C2 1pF 1 2 3 4 5 6 7 8 9 10 U1 VDD_VCO ANT VIN GND CKO GIO2 GIO1 SDIO SCK SCS GND GND FI D TP1 ANTENNA C5 100pF 7 C4 1nF 20 C6 2.2uF 1 2 J1 Mar., 2014, Version 1.0 81 AMICCOM Electronics Corporation A7137 A M IC C O M C O N FI D EN TI A L 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver Mar., 2014, Version 1.0 82 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver TI A EN FI D N C O M Analog to Digital Converter Auto IF Frequency Compensation Automatic Gain Control Bit Error Rate Bandwidth Carrier Detect Channel Step Cyclic Redundancy Check Direct Current Forward Error Correction First in First out Frequency Shift Keying Identifier Intermediate Frequency Industrial, Scientific and Medical Local Oscillator Micro Controller Unit Phase Frequency Detector for PLL Phase Lock Loop Power on Reset Receiver Receiver Local Oscillator Received Signal Strength Indicator Serial to Parallel Interface System Clock for digital circuit Transmitter Transmitter Radio Frequency Voltage Controlled Oscillator Crystal Oscillator Crystal Reference frequency Crystal O ADC AIF FC AGC BER BW CD CHSP CRC DC FEC FIFO FSK ID IF ISM LO MCU PFD PLL POR RX RXLO RSSI SPI SYCK TX TXRF VCO XOSC XREF XTAL L 23. Abbreviations Package Units Per Reel / Tray QFN4x4-20L, Pb Free, Tape & Reel, -40℃〜85℃ 3K A71C37AQFI QFN20L, Pb Free, Tray, -40℃〜85℃ 490EA A71C37AH Die form, -40℃〜85℃ 100EA A A71C37AQFI/Q M IC Part No. C 24. Ordering Information Mar., 2014, Version 1.0 83 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 25. Package Information QFN 20L (4 X 4 X 0.8mm) Outline Dimensions TOP VIEW BOTTOM VIEW 0.25 C 11 11 15 L 15 D2 L D 10 TI A 16 10 6 1 FI D 6 5 5 20 1 e b 0.10 M C A B N 0.25 C 20 EN e E E2 16 Seating Plane Dimensions in mm Min Nom Max A 0.028 0.030 0.032 0.70 0.75 0.80 A1 0.000 0.001 0.002 0.00 0.02 0.05 0.012 0.18 0.25 0.30 O C IC M A Mar., 2014, Version 1.0 y C Dimensions in inches M Symbol C A3 A1 A C O // 0.10 C A3 b Min 0.008 REF 0.007 0.010 Nom Max 0.203 REF D 0.154 0.158 0.161 3.90 4.00 4.10 D2 0.075 0.079 0.083 1.90 2.00 2.10 E 0.154 0.158 0.161 3.90 4.00 4.10 E2 0.075 0.079 0.083 1.90 2.00 2.10 0.020 0.30 0.020 BSC e L y 0.012 0.016 0.003 0.50 BSC 0.40 0.50 0.08 84 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 26. Top Marking Information A71C37AQFI L : A71C37AQFI : 20 : QFN : 4*4 mm : Laser Mark : Arial TI A Part No. Pin Count Package Type Dimension Mark Method Character Type A M IC C O M C O N FI D EN ¡ ¡ ¡ ¡ ¡ ¡ Mar., 2014, Version 1.0 85 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver N FI D EN TI A L 27. Reflow Profile A M IC C O M C O Actual Measurement Graph Mar., 2014, Version 1.0 86 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 28. Tape Reel Information A0 4.35 4.4 5.25 3.2 8.2 8.2 B0 4.35 4.4 5.25 3.2 7.5 8.8 P0 4.0 4.0 4.0 4.0 4.0 4.0 C O P 8 8 8 4 12 12 P1 2.0 2.0 2.0 2.0 2.0 2.0 D0 1.5 1.5 1.5 1.5 1.5 1.5 D1 1.5 1.5 1.5 1.5 1.5 E 1.75 1.75 1.75 1.75 1.75 1.75 F 5.5 5.5 5.5 1.9 7.5 7.5 Unit: mm W 12 12 12 8 16 16 A M IC C O M TYPE 20 QFN 4*4 24 QFN 4*4 32 QFN 5*5 QFN3*3 / DFN-10 20 SSOP 24 SSOP N FI D EN TI A L Cover / Carrier Tape Dimension TYPE 20 QFN (4X4) 24 QFN (4X4) 32 QFN (5X5) QFN3*3 / DFN-10 20 SSOP 24 SSOP Mar., 2014, Version 1.0 K0 1.1 1.4 1.1 0.75 2.5 2.1 87 t 0.3 0.3 0.3 0.25 0.3 0.3 COVER TAPE WIDTH 9.2 9.2 9.2 8 13.3 13.3 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver REEL DIMENSIONS UNIT IN mm G N 20 QFN(4X4) 24 QFN(4X4) 32 QFN(5X5) DFN-10 12.8+0.6/-0.4 100 REF 48 QFN(7X7) 16.8+0.6/-0.4 D K L 18.2(MAX) 1.75±0.25 13.0+0.5/-0.2 2.0±0.5 R 330＋ 20.2 0.00/-1.0 100 16.4+2.0/-0.0 TI A 330＋ 25(MAX) 1.75±0.25 13.0+0.5/-0.2 2.0±0.5 0.00/-1.0 20.2 330＋ 22.4(MAX) 1.75±0.25 13.0+0.2/-0.2 1.9±0.4 0.00/-1.0 20.2 N REF 330＋ 22.2(MAX) 1.75±0.25 13.0+0.5/-0.2 2.0±0.5 0.00/-1.0 20.2 EN 100 20.4+0.6/-0.4 REF 20 SSOP 24 SSOP M FI D 100 REF 28 SSOP (150mil) T L TYPE R D N A M IC C L O M C O T Mar., 2014, Version 1.0 M G K 88 AMICCOM Electronics Corporation A7137 2.4GHz FSK/GFSK 10 dBm 2Mbps Transceiver 29. Product Status Product Status Planned or Under Development Definition This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary Engineering Samples and First Production This data sheet contains preliminary data, and supplementary data will be published at a later date. AMICCOM reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. No Identification Noted Full Production Obsolete Not In Production This data sheet contains the final specifications. AMICCOM reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains specifications on a product that has been discontinued by AMICCOM. The data sheet is printed for reference information only. IC C O M C O N FI D EN TI A L Data Sheet Identification Objective RF ICs AMICCOM A M Headquarter A3, 1F, No.1, Li-Hsin Rd. 1, Hsinchu Science Park, Taiwan 30078 Tel: 886-3-5785818 Shenzhen Office Rm., 2003, DongFeng Building, No. 2010, Shennan Zhonglu Rd., Futian Dist., Shenzhen, China Post code: 518031 Web Site http://www.amiccom.com.tw Mar., 2014, Version 1.0 89 AMICCOM Electronics Corporation