A7125
2.4GHz FSK Transceiver
Document Title
A7125 Data Sheet, 2.4GHz FSK Transceiver with 2M / 1Mbps data rate
Revision History
History
Issue Date
Remark
L
Rev. No.
0.0
Initial issue.
Aug. 31, 2007
0.1
0.2
Logo change.
Modify PIN Configuration and Description, Block Diagram,
Electrical Specifications, Diagram of State Machine. Add
Control Register and Function Description.
Oct. 18, 2007
July 31, 2008
Preliminary
0.3
Add Power Saving FIFO Mode.
Rename GPIO1 and GPIO2 into GIO1 and GIO2.
August 31, 2008
Preliminary
0.4
Modify register recommended value IGFI [2:0] = [000]
Modify register recommended value IGFQ [2:0] = [000]
Delete TWWS function
October 06, 2008
Preliminary
0.5
Modify register recommended value
Delay Register I (17h): PDL= [000]
Delay Register II (18h): WSEL= [011]
Battery Detect Register (2Ch): QDS = [1]
Crystal Test Register (32h): XCP= [00]
IFAT Register (36h): IGFI [2:0] = [111], IGFQ [2:0] = [111]
Modify PLL to WPLL settling time when PDL=[000]
If LO is changed, from 20 us to 30 us
If LO is fixed, from 20 us to 10 us
Delete Ext Voltage Measurement function
Add EOPD output to GIO2
Add PASW output to GIO2
Add EOPDS Register
Add section 16.5
Modify register recommended value
ADC Control (1Fh): CDM= [0]
Modify recommended timing of PASW
FI
D
EN
TI
A
Preliminary
Preliminary
Preliminary
Feb., 2010
Full
Production
Nov., 2010
Full
Production
Nov. 30, 2010
Full
Production
Jul. 2011
Full
Production
M
C
O
N
June 11, 2009
C
O
1.0
Change English Company Name
A
M
1.2
Add Note 8 (regulator settling time) in chapter 8.
IC
1.1
1.3
Modify the tape reel information and the add Shenzhen
office address.
Important Notice:
AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service
without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable for
use in life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such
applications is understood to be fully at the risk of the customer.
Jul., 2011, v1.3
1
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
Table of Contents
A
M
IC
C
O
M
C
O
N
FI
D
EN
TI
A
L
1. Typical Application ..................................................................................................................................................... 5
2. General Description ................................................................................................................................................... 5
3. Feature ..................................................................................................................................................................... 5
4. PIN Configuration ...................................................................................................................................................... 6
5. PIN Description (I: Input, O: Output, I/O: Input or Output, G: Ground, D: Digital)........................................................... 7
6. Block Diagram ........................................................................................................................................................... 8
7. Absolution Maximum Rating ....................................................................................................................................... 9
8. Electrical Specifications............................................................................................................................................ 10
General ................................................................................................................................................................ 10
Phase Locked Loop .............................................................................................................................................. 10
Transmitter ........................................................................................................................................................... 10
Receiver............................................................................................................................................................... 10
Regulator ............................................................................................................................................................. 10
Digital IO DC characteristics...................................................................................................................................11
9. Control Register....................................................................................................................................................... 12
9.1 Control Register Table..................................................................................................................................... 12
9.2 Control Register Description............................................................................................................................ 15
9.2.1 Mode Register (Address: 00h) ............................................................................................................... 15
9.2.2 Mode Control Register (Address: 01h) ................................................................................................... 15
9.2.3 Calibration Control Register (Address: 02h)............................................................................................ 16
9.2.4 FIFO Register I (Address: 03h) .............................................................................................................. 16
9.2.5 FIFO Register II (Address: 04h) ............................................................................................................. 16
9.2.6 FIFO DATA Register (Address: 05h)....................................................................................................... 16
9.2.7 ID DATA Register (Address: 06h) ........................................................................................................... 16
9.2.8 RC OSC Register I (Address: 07h)......................................................................................................... 17
9.2.9 RC OSC Register II (Address: 08h)........................................................................................................ 17
9.2.10 RC OSC Register III (Address: 09h)..................................................................................................... 17
9.2.11 CKO Pin Control Register (Address: 0Ah)............................................................................................. 17
9.2.12 GIO1 Pin Control Register (Address: 0Bh)............................................................................................ 17
9.2.13 GIO2 Pin Control Register (Address: 0Ch) ........................................................................................... 18
9.2.14 Data Rate Clock Register (Address: 0Dh)............................................................................................. 19
9.2.15 PLL Register I (Address: 0Eh).............................................................................................................. 21
9.2.16 PLL Register II (Address: 0Fh)............................................................................................................. 21
9.2.17 PLL Register III (Address: 10h) ............................................................................................................ 21
9.2.18 PLL Register IV (Address: 11h) ............................................................................................................ 21
9.2.19 PLL Register V (Address: 12h)............................................................................................................. 21
9.2.20 Channel Group Register I (Address: 13h) ............................................................................................. 21
9.2.21 Channel Group Register II (Address: 14h) ............................................................................................ 22
9.2.22 TX Register I (Address: 15h)................................................................................................................ 22
9.2.23 TX Register II (Address: 16h)............................................................................................................... 22
9.2.24 Delay Register I (Address: 17h) ........................................................................................................... 23
9.2.25 Delay Register II (Address: 18h) .......................................................................................................... 23
9.2.26 RX Register (Address: 19h) ................................................................................................................. 24
9.2.27 RX Gain Register I (Address: 1Ah)....................................................................................................... 24
9.2.28 RX Gain Register II (Address: 1Bh)...................................................................................................... 24
9.2.29 RX Gain Register III (Address: 1Ch)..................................................................................................... 25
9.2.30 RX Gain Register IV (Address: 1Dh) .................................................................................................... 25
9.2.31 RSSI Threshold Register (Address: 1Eh).............................................................................................. 25
9.2.32 ADC Control Register (Address: 1Fh)................................................................................................... 25
9.2.33 Code Register I (Address: 20h) ............................................................................................................ 26
9.2.34 Code Register II (Address: 21h)........................................................................................................... 26
9.2.35 Code Register III (Address: 22h) .......................................................................................................... 26
9.2.36 IF Calibration Register I (Address: 23h)................................................................................................ 26
9.2.37 IF Calibration Register II (Address: 24h)............................................................................................... 27
9.2.38 VCO Current Calibration Register (Address: 25h) ................................................................................. 27
9.2.39 VCO Bank Calibration Register I (Address: 26h)................................................................................... 27
9.2.40 VCO Bank Calibration Register II (Address: 27h).................................................................................. 28
9.2.41 VCO Deviation Calibration Register I (Address: 28h) ............................................................................ 28
9.2.42 VCO Deviation Calibration Register II (Address: 29h) ........................................................................... 28
9.2.43 VCO Deviation Calibration Register III (Address: 2Ah) .......................................................................... 28
9.2.44 VCO Modulation Delay Register (Address: 2Bh)................................................................................... 29
9.2.45 Battery Detect Register (Address: 2Ch)................................................................................................ 29
Jul., 2011, v1.3
2
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
A
M
IC
C
O
M
C
O
N
FI
D
EN
TI
A
L
9.2.46 TX test Register (Address: 2Dh)........................................................................................................... 29
9.2.47 RX DEM test Register I (Address: 2Eh)................................................................................................ 29
9.2.48 RX DEM test Register II (Address: 2Fh) ............................................................................................... 30
9.2.49 Charge Pump Current Register I (Address: 30h)................................................................................... 30
9.2.50 Charge Pump Current Register II (Address: 31h).................................................................................. 30
9.2.51 Crystal test Register (Address: 32h) ..................................................................................................... 30
9.2.52 PLL test Register (Address: 33h).......................................................................................................... 30
9.2.53 VCO test Register (Address: 34h) ........................................................................................................ 31
9.2.54 RF Analog test Register (Address: 35h)................................................................................................ 31
9.2.55 IFAT Register (Address: 36h) ............................................................................................................... 31
9.2.56 Channel Select Register (Address: 37h)............................................................................................... 32
9.2.57 VRB Register (Address: 38h) ............................................................................................................... 32
10. SPI........................................................................................................................................................................ 33
10.1 SPI Format ................................................................................................................................................... 34
10.2 SPI Timing Characteristic .............................................................................................................................. 34
10.3 SPI Timing Chart........................................................................................................................................... 34
10.3.1 Timing Chart of 3-wire SPI ................................................................................................................... 34
10.3.2 Timing Chart of 4-wire SPI ................................................................................................................... 35
10.4 Strobe Commands ........................................................................................................................................ 35
10.4.1 Strobe Command - Sleep Mode ........................................................................................................... 36
10.4.2 Strobe Command - ldle Mode............................................................................................................... 36
10.4.3 Strobe Command - Standby Mode........................................................................................................ 37
10.4.4 Strobe Command - PLL Mode.............................................................................................................. 37
10.4.5 Strobe Command - RX Mode ............................................................................................................... 38
10.4.6 Strobe Command - TX Mode................................................................................................................ 38
10.4.7 Strobe Command – FIFO Write Pointer Reset ...................................................................................... 38
10.4.8 Strobe Command – FIFO Read Pointer Reset ...................................................................................... 39
10.5 Reset Command........................................................................................................................................... 39
10.6 ID Accessing Command ................................................................................................................................ 39
10.6.1 ID Write Command.............................................................................................................................. 40
10.6.2 ID Read Command.............................................................................................................................. 40
10.7 FIFO Accessing Command............................................................................................................................ 40
10.7.1 TX FIFO Write Command .................................................................................................................... 40
10.7.2 Rx FIFO Read Command .................................................................................................................... 41
11. State machine........................................................................................................................................................ 42
11.1 Key states ..................................................................................................................................................... 42
11.1.1 Standby mode ..................................................................................................................................... 42
11.1.2 Sleep mode ......................................................................................................................................... 43
11.1.3 ldle mode ............................................................................................................................................ 43
11.1.4 PLL mode............................................................................................................................................ 43
11.1.5 TX mode ............................................................................................................................................. 43
11.1.6 RX mode............................................................................................................................................. 43
11.1.7 CAL mode ........................................................................................................................................... 44
11.2 Normal FIFO Mode........................................................................................................................................ 45
11.3 Quick FIFO Mode.......................................................................................................................................... 47
11.4 Power Saving FIFO Mode.............................................................................................................................. 48
11.5 Quick Direct Mode......................................................................................................................................... 51
12 Crystal Oscillator Circuit.......................................................................................................................................... 54
12.1 Use External Crystal...................................................................................................................................... 54
12.2 Use External Clock........................................................................................................................................ 54
13. System Clock ........................................................................................................................................................ 55
13.1 Derive System Clock ..................................................................................................................................... 55
13.2 Data Rate ..................................................................................................................................................... 56
14. Transceiver Frequency........................................................................................................................................... 57
14.1 LO Frequency Setting ................................................................................................................................... 58
14.2 IF Side Band Select ...................................................................................................................................... 61
14.2.1 Auto IF Exchange................................................................................................................................ 62
14.2.2 Fast Exchange .................................................................................................................................... 62
14.3 Band Edge Frequency Setting ....................................................................................................................... 63
14.4 Frequency Compensation.............................................................................................................................. 65
15. Calibration............................................................................................................................................................. 67
15.1 Calibration Procedure.................................................................................................................................... 67
15.2 IF Filter Bank Calibration ............................................................................................................................... 67
15.3 RSSI Calibration ........................................................................................................................................... 67
15.4 VCO Current Calibration................................................................................................................................ 68
15.5 VCO Bank Calibration ................................................................................................................................... 68
Jul., 2011, v1.3
3
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
A
M
IC
C
O
M
C
O
N
FI
D
EN
TI
A
L
15.6 VCO Deviation Calibration............................................................................................................................. 68
15.7 Channel Group Function ............................................................................................................................... 68
16. FIFO (First In First Out).......................................................................................................................................... 70
16.1 Packet Format of FIFO mode ........................................................................................................................ 70
16.2 Bit Stream Process........................................................................................................................................ 71
16.3 Transmission Time ........................................................................................................................................ 71
16.4 Usage of TX and RX FIFO............................................................................................................................. 72
16.4.1 Easy FIFO........................................................................................................................................... 72
16.4.2 Segment FIFO..................................................................................................................................... 73
16.4.3 FIFO Extension ................................................................................................................................... 76
16.5 Optimize Throughput..................................................................................................................................... 80
17. ADC (Analog to Digital Converter) .......................................................................................................................... 82
17.1 Temperature Measurement............................................................................................................................ 82
17.2 RSSI Measurement....................................................................................................................................... 82
17.3 Carrier Detect ............................................................................................................................................... 84
18. Battery Detect........................................................................................................................................................ 85
19. Application Circuit Example .................................................................................................................................... 86
20. Abbreviations......................................................................................................................................................... 87
20. Abbreviations......................................................................................................................................................... 88
21. Ordering Information .............................................................................................................................................. 88
22. Package Information .............................................................................................................................................. 89
23. Top Marking Information......................................................................................................................................... 90
24. Reflow Profile ........................................................................................................................................................ 91
25. Tape Reel Information............................................................................................................................................ 92
26. Product Status ....................................................................................................................................................... 93
Jul., 2011, v1.3
4
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
1. Typical Application
n
n
n
2.4GHz ISM band Communication System
2.4GHz Remote Control
Wireless Keyboard and Mouse
■
■
■
Wireless Intelligent sports
Wireless Toy and Gaming
Wireless Audio/Video Streaming
2. General Description
TI
A
L
A7125 is a high performance and low cost 2.4GHz ISM band wireless transceiver. It integrates high sensitivity receiver
(-90dBm @2Mbps), high efficiency power amplifier (up to 3dBm), frequency synthesizer and base-band modem. In typical
system, A7125 is used together with MCU (microcontroller) with very few external passive components. A7125 supports
both FIFO mode and direct mode that contains clock recovery circuit CKO pin to MCU.
EN
A7125 supports very fast settling time (90 us) for frequency hopping system. For packet handling, A7125 has built-in
separated 64-bytes TX/RX FIFO (could be extended to 256 bytes) for data buffering and burst transmission, CRC for error
detection, FEC for 1-bit data correction per code word, RSSI for clear channel assessment, data whitening for data
encryption/decryption, thermal sensor for monitoring relative temperature. Those functions are very easy to use while
developing a wireless system. All features are integrated in a small QFN 4X4 20 pins package.
FI
D
A7125’s data rate is up to 2Mbps and can be easily programmed to 1Mbps or 2 Mbps via 3-wire or 4-wire SPI bus. For
power saving, A7125 supports sleep mode, idle mode, standby mode. For easy-to-use, A7125 has an unique SPI
command set called Strobe command that are used to control A7125’s state machine. Based on Strobe commands, from
power saving, TX delivery, RX receiving, channel monitoring, frequency hopping to auto calibrations, MCU only needs to
define A7125’s control registers and send Strobe commands via SPI bus. In addition, A7125 supports two general purpose
I/O pins, GIO1 and GIO2, to inform MCU its status so that MCU could use either polling or interrupt scheme to do radio
control. Therefore, it is very easy to monitor transmission between MCU and A7125 because of its digital interface.
O
M
C
O
Small size (QFN 4X4, 20 pins).
Support 2400 ~ 2483.5 MHz ISM band.
FSK modulation.
Programmable data rate to 1Mbps or 2Mbps.
Low current consumption: RX 17mA, TX 15.7mA (at 0dBm output power).
Low sleep current (1.5uA).
Programmable RF output power -20dBm ~ 3dBm.
Very High sensitivity (-90dBm@2Mbps, -92dBm@1Mbps).
On chip regulator, supports input voltage 2.0 ~ 3.6V.
Easy to use
u
Support 3-wire or 4-wire SPI.
u
Unique Strobe command via SPI.
u
Change frequency channel by ONE register setting.
u
8-bits Digital RSSI for clear channel indication.
u
Fast exchange mode during TRX role switching.
u
Auto RSSI measurement.
u
Auto Calibrations.
u
Auto IF function.
u
Auto CRC Check.
u
Auto FEC by (7, 4) Hamming code (1 bit error correction / code word).
u
Data Whitening for encryption and decryption.
u
Separated 64 bytes RX and TX FIFO.
u
Easy FIFO / Segment FIFO / FIFO Extension (up to 256 bytes).
u
Support direct mode with recovery clock output to MCU.
u
Support direct mode with frame sync signal to MCU.
Support low cost crystal (6 / 8 /12 / 16MHz).
Support low accuracy crystal within ± 50ppm.
Support Auto Frequency Compensation.
Support crystal sharing, (1 / 2 / 4 / 8MHz) to MCU.
Fast settling time synthesizer for frequency hopping system.
Built-in thermal sensor for monitoring relative temperature.
Built-in Battery Detector.
A
M
IC
C
n
n
n
n
n
n
n
n
n
n
N
3. Feature
n
n
n
n
n
n
n
Jul., 2011, v1.3
5
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
C
O
N
FI
D
EN
TI
A
L
4. PIN Configuration
A
M
IC
C
O
M
Figure 4.1 A7125 QFN 4x4 Package Top View
Jul., 2011, v1.3
6
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
5. PIN Description (I: Input, O: Output, I/O: Input or Output, G: Ground, D: Digital)
L
TI
A
G
EN
Back side plate
Function Description
O: RSSI bypass. Connect to bypass capacitor.
Band-gap bypass. Connect to bypass capacitor.
RF input. Connect to matching circuit.
RF output. Connect to matching circuit.
RF choke input. Connect to matching circuit.
VCO supply voltage input.
Charge-pump output. Connect to loop filter.
PLL supply voltage input.
Crystal oscillator input. Connect to tank capacitor.
Crystal oscillator output. Connect to tank capacitor.
SPI chip select input.
SPI clock input.
Digital supply voltage output. Connect to bypass capacitor.
SPI data IO.
Ground.
Multi-function IO 1 / SPI data output.
Multi-function IO 2 / SPI data output.
Multi-function clock output.
Regulator input. Connect to VDD supply.
Analog supply voltage output. Connect to bypass capacitor.
Ground. Back side plate shall be well-solder to ground; otherwise, it will
impact RF performance.
FI
D
I/O
O
O
I
O
I
I
O
O
I
O
DI
DI
O
DI/O
G
DI/O
DI/O
DO
I
O
N
Symbol
BP_RSSI
BP_BG
RFI
RFO
RFC
VDD_VCO
CP
VDD_PLL
XI
XO
SCS
SCK
VDD_D
SDIO
GND
GIO1
GIO2
CKO
REGI
VDD_A
A
M
IC
C
O
M
C
O
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Jul., 2011, v1.3
7
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
REGI
CKO
GIO2
GIO1
20
19
18
17
16
5
8
CP
C
O
VDD_VCO
7
14
SDIO
13 VDD_D
SPI
XOSC
6
GND
TI
A
RXFIFO
TXFIFO
PLL
N
RFC
VCO
FI
D
PA
15
EN
4
BSP
RFO
LNA
9
10
XO
3
MODEM
RFI
Radio
Control
XI
2
VDD_PLL
BP_BG
Regulator/
Thermal sensor
ADC
Packet Handler
BP_RSSI 1
L
VDD_A
6. Block Diagram
12
SCK
11
SCS
A
M
IC
C
O
M
Figure 6.1 A7125 Block Diagram
Jul., 2011, v1.3
8
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
7. Absolution Maximum Rating
With respect to
Rating
Unit
Supply voltage range (VDD)
GND
-0.3 ~ 3.6
V
Digital I/O pins range
GND
-0.3 ~ VDD+0.3
V
Voltage on the analog pins range
GND
-0.3 ~ 2.1
V
Input RF level
14
dBm
-55 ~ 125
°C
HBM
± 2K
V
MM
± 100
ESD Rating
V
TI
A
Storage Temperature range
L
Parameter
EN
*Stresses above those listed under “Absolute Maximum Rating” may cause permanent damage to the device. These are
stress ratings only; functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
A
M
IC
C
O
M
C
O
N
FI
D
*Device is ESD sensitive. Use appropriate ESD precautions. HBM (Human Body Mode) is tested under MIL-STD-883F
Method 3015.7. MM (Machine Mode) is tested under JEDEC EIA/JESD22-A115-A.
*Device is Moisture Sensitivity Level III (MSL 3).
Jul., 2011, v1.3
9
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
8. Electrical Specifications
(Ta=25℃, VDD=3.3V, data rate= 2Mbps, FXTAL =16MHz, with Matching Network and low pass filter, On Chip Regulator =
1.8V, unless otherwise noted.)
Parameter
Description
Minimum
Typical
Maximum
Unit
85
°C
V
uA
uA
mA
General
-40
FI
D
Current Consumption
Phase Locked Loop
N
X’TAL Start-up Time (2*)
X’TAL Frequency (FXTAL)
VCO Operation Frequency
PLL Settling Time (4*)
C
O
O
IC
Sensitivity @BER=0.001
Sensitivity @BER=0.001
IF Frequency (FIF)
A
M
Interference (7*)
Maximum Operating Input Power
Spurious Emission (5*)
RSSI Range
RX Settling Time
300
, 8, 12, 16
(3*)
6
2483.5
0
1
2
500
40
mA
mA
mA
mA
mA
mA
mA
us
MHz
MHz
ms
30
@Loop BW =200 KHz
C
Receiver
3.6
9.8
17.0
16.2
21
15.7
13.7
13.3
30MHz~1GHz
1GHz~12.75GHz
1.8GHz~ 1.9GHz
5.15GHz~ 5.3GHz
M
TX Power Control Range
Out Band Spurious Emission (5*)
3.3
1.5(1*)
300(1*)
2.9
2400
@Loop BW = 200 KHz
Transmitter
Data rate
Frequency Deviation
TX Settling Time (6*)
2.0
L
Regulator supply input
Sleep Mode
Idle Mode (Regulator on)
Standby Mode (XOSC on,
Clock generator on)
PLL Mode
RX Mode (2Mbps)
RX Mode (1 Mbps)
TX Mode (@3dBm output)
TX Mode (@0dBm output)
TX Mode (@-10dBm output)
TX Mode (@-20dBm output)
TI
A
Supply Voltage (VDD)
EN
Operating Temperature
-36
-30
-47
-47
2
dBm
dBm
Mbps
KHz
ms
2Mbps
1Mbps
-90
-92
2
dBm
dBm
MHz
Co-Channel (C/I0)
1 Adjacent Channel (C/I 1)
2nd Adjacent Channel (C/I2)
3rd Adjacent Channel (C/I3)
Image (C/IIM)
@RF input (BER=0.1%)
30MHz~1GHz
11
2
-18
-28
-12
dB
dB
dB
dB
dB
dBm
dBm
st
1GHz~12.75GHz
@RF input
@Loop BW = 200 KHz
3
-57
-47
-50
-100
40
dBm
ms
500
1.23
1.8
ms
V
V
Regulator
Regulator settling time (8*)
Band-gap reference voltage
Regulator output voltage
Jul., 2011, v1.3
10
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
Digital IO DC characteristics
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
@IOH= -0.5mA
@IOL= 0.5mA
0.8*VDD
0
VDD-0.4
0
VDD
0.2*VDD
VDD
0.4
V
V
V
V
A
M
IC
C
O
M
C
O
N
FI
D
EN
TI
A
L
Note 1: When digital I/O pins are configured as input, those pins shall NOT be floating but pull either high or low (SCS shall
be pulled high only); otherwise, more leakage current will be induced in all operation modes.
Note 2: Refer to Delay Register II (18h) to set up crystal settling delay.
Note 3: If 6MHz external crystal is selected, A7125 only supports 1Mbps data rate.
Note 4: Refer to Delay Register I (17h) to set up PDL (PLL settling delay).
Note 5: With external RF filter that provides minimum 17dB of attenuation in the band: 30MHz ~ 2GHz and 3GHz
~12.75GHz.
Note 6: Refer to Delay Register I (17h) to set up TDL delay.
Note 7: The power level of wanted signal is set at sensitivity +3dB. The modulation data for wanted signal and interferer
are PN9 and PN15, respectively. Channel spacing is 2MHz.
Note 8: When VDD < 2.1V and temperature < -30 degree C, the regulator settling time will arise up to 20ms.
Jul., 2011, v1.3
11
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
9. Control Register
A7125 has totally built-in 57 control registers that cover all radio control. MCU can access those control registers via 3-wire
or 4-wire SPI (Support max. SPI data rate up to 10 Mbps). User can refer to chapter 10 for details of SPI bus. A7125 is
simply controlled by registers and outputs its status to MCU by GIO1 and GIO2 pins.
9.1 Control Register Table
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
R
W
R
RESETN
DDPC
DDPC
RESETN
FECF
ARSSI
ARSSI
RESETN
CRCF
AIF
AIF
RESETN
CER
DFCD
CD
RESETN
XER
WWSE
WWSE
RESETN
PLLER
FMT
FMT
RESETN
TRSR
FMS
FMS
RESETN
TRER
ADCM
ADCM
R/W
-
-
-
VCC
VBC
VDC
FBC
RSSC
W
FEP7
FEP6
FEP5
FEP4
FEP3
FEP2
FEP1
FEP0
W
FPM1
FPM0
PSA5
PSA4
PSA3
PSA2
PSA1
PSA0
R/W
FIFO7
FIFO6
FIFO5
FIFO4
FIFO3
FIFO2
FIFO1
FIFO0
R/W
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
W
R
WWS_SL7
-
WWS_SL6 WWS_SL5 WWS_SL4 WWS_SL3 WWS_SL2 WWS_SL1 WWS_SL0
RCOC5
RCOC4
RCOC3
RCOC2
RCOC1
RCOC0
W
WWS_SL9
WWS_SL8 WWS_AC5 WWS_AC4 WWS_AC3 WWS_AC2 WWS_AC1 WWS_AC0
W
BBCKS1
BBCKS0
W
ECKOE
CKOS3
W
-
W
-
W
R
R/W
A
M
Jul., 2011, v1.3
TI
A
EN
FI
D
N
-
RCOSC_E
TSEL
TWWS_E
CKOS2
CKOS1
CKOS0
CKOI
CKOE
SCKI
-
GIO1S3
GIOS2
GIO1S1
GIO1S0
GIO1I
GIO1OE
-
GIO2S3
GIO2S2
GIO2S1
GIO2S0
GIO2I
GIO2OE
SDR1
SDR1
SDR0
SDR0
GRC3
GRC3
GRC1
GRC2
GRC1
GRC1
GRC0
GRC0
CGS
-
XS
-
CHN7
CHN6
CHN5
CHN4
CHN3
CHN2
CHN1
CHN0
CHR0
CHR0
BIP1
IP1
BFP9
AC9-FP9
BFP1
AC1-FP1
IP8
BIP8
BIP0
IP0
BFP8
AC8-FP8
BFP0
AC0-FP0
O
M
C
O
-
DBL
DBL
BIP7
IP7
BFP15
-FP15
BFP7
AC7-FP7
C
W
R
W
R
W
R
W
R
-
L
R/W
IC
Address /
Name
00h
Mode
01h
Mode control
02h
Calc
03h
FIFO I
04h
FIFO II
05h
FIFO Data
06h
ID Data
07h
RC OSC I
08h
RC OSC II
09h
RC OSC III
0Ah
CKO Pin
0Bh
GIO1 Pin I
0Ch
GIO2 Pin II
0Dh
Data Rate Clock
0Eh
PLL I
0Fh
PLL II
10h
PLL III
11h
PLL IV
12h
PLL V
13h
Channel Group I
14h
Channel Group II
15h
TX I
16h
TX II
17h
Delay I
18h
Delay II
19h
RX
1Ah
RX Gain I
RRC1
RRC0
CHR3
CHR2
CHR1
RRC1
RRC0
CHR3
CHR2
CHR1
BIP6
BIP5
BIP4
BIP3
BIP2
IP6
IP5
IP4
IP3
IP2
BFP14
BFP13
BFP12
BFP11
BFP10
AC14-FP14 AC13-FP13 AC12-FP12 AC11-FP11 AC10-FP10
BFP6
BFP5
BFP4
BFP3
BFP2
AC6-FP6
AC5-FP5
AC4-FP4
AC3-FP3
AC2-FP2
R/W
CHGL7
CHGL6
CHGL5
CHGL4
CHGL3
CHGL2
CHGL1
CHGL0
R/W
CHGH7
CHGH6
CHGH5
CHGH4
CHGH3
CHGH2
CHGH1
CHGH0
W
SDMS
TMDE
TXDI
TME
-
FDP2
FDP1
FDP0
W
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
W
EOPDS
DPR1
DPR0
TDL1
TDL0
PDL2
PDL1
PDL0
W
WSEL2
WSEL1
WSEL0
RSSC_D1
RSSC_D0
RS_DLY2
RS_DLY1
RS_DLY0
W
-
RXSM1
RXSM0
FC
RXDI
DMG
RAW
ULS
R/W
MVGS
MRHL
IGS
MGS1
MGS0
LGS2
LGS1
LGS0
12
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
W
RL7
RL6
RL5
RL4
RL3
RL2
RL1
RL0
W
AVSEL1
AVSEL0
MVSEL1
MVSEL0
MHC
LHC1
LHC0
AGCE
W
R
RTH7
ADC7
RTH6
ADC6
RTH5
ADC5
RTH4
ADC4
RTH3
ADC3
RTH2
ADC2
RTH1
ADC1
RTH0
ADC0
W
RSM1
RSM0
RADC1
RADC0
FSARS
XADS
RSS
CDM
W
-
-
WHTS
FECS
CRCS
IDL
PML1
PML0
W
-
DCL2
DCL1
DCL0
ETH1
ETH0
PMD1
PMD0
W
-
WS6
WS5
WS4
WS3
WS2
WS1
WS0
W
R
-
-
-
MFBS
FBCF
MFB3
FB3
MFB2
FB2
MFB1
FB1
MFB0
FB0
R
-
-
-
FCD4
W
-
-
VCCS
MVCS
R
-
-
-
VCCF
W
DDC1
DDC0
MDAGS
R
-
-
-
W
MDAG7
MDAG6
MDAG5
R
ADAG7
ADAG6
ADAG5
W
DEVS3
DEVS2
R
DEVA7
W
Jul., 2011, v1.3
TI
A
FCD1
FCD0
VCOC3
VCOC2
VCOC1
VCOC0
VCB3
VCB2
VCB1
VCB0
-
MVBS
MVB2
MVB1
MVB0
-
VBCF
VB2
VB1
VB0
MDAG4
MDAG3
MDAG2
MDAG1
MDAG0
N
EN
FCD2
ADAG4
ADAG3
ADAG2
ADAG1
ADAG0
DEVS1
DEVS0
DAMR_M
VMTE_M
VMS_M
MSEL
DEVA6
DEVA5
DEVA4
DEVA3
DEVA2
DEVA1
DEVA0
MVDS
MDEV6
MDEV5
MDEV4
MDEV3
MDEV2
MDEV1
MDEV0
R
ADEV7
ADEV6
ADEV5
ADEV4
ADEV3
ADEV2
ADEV1
ADEV0
W
VMG7
VMG5
VMG4
VMG3
VMG2
VMG1
VMG0
-
DEVFD2
DEVFD1
DEVFD0
DEVD2
DEVD1
DEVD0
RGS
-
RGV1
-
RGV0
-
QDS
BDF
BVT2
-
BVT1
-
BVT0
-
BD_E
-
W
-
-
TXCS
PAC1
PAC0
TBG2
TBG1
TBG0
W
DMT
DCM1
DCM0
MLP1
MLP0
SLF2
SLF1
SLF0
W
DCV7
DCV6
DCV5
DCV4
DCV3
DCV2
DCV1
DCV0
W
CPM3
CPM2
CPM1
CPM0
CPT3
CPT2
CPT1
CPT0
W
CPTX3
CPTX2
CPTX1
CPTX0
CPRX3
CPRX2
CPRX1
CPRX0
W
-
-
-
-
DBD
XCC
XCP1
XCP0
W
-
CPS
PRRC1
PRRC0
PRIC1
PRIC0
SDPW
NSDO
W
-
-
-
TLB1
TLB0
RLB1
RLB0
VCBS
W
OLM
VTBS
CPH
CPCS
-
RFT2
RFT1
RFT0
C
O
M
VMG6
O
C
-
W
R
FI
D
FCD3
W
A
M
2Fh
Rx DEM test II
30h
Charge Pump
Current I
31h
Charge Pump
Current II
32h
Crystal test
33h
PLL test
34h
VCO test
35h
RF Analog test
L
W
IC
1Bh
RX Gain II
1Ch
RX Gain III
1Dh
RX Gain IV
1Eh
RSSI Threshold
1Fh
ADC Control
20h
Code I
21h
Code II
22h
Code III
23h
IF Calibration I
24h
IF Calibration II
25h
VCO current
Calibration
26h
VCO band
Calibration I
27h
VCO band
Calibration II
28h
VCO deviation
Calibration I
29h
VCO deviation
Calibration II
2Ah
VCO deviation
Calibration III
2Bh
VCO modulation
Delay
2Ch
Battery detect
2Dh
TX test
2Eh
Rx DEM test I
13
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
IGFI1
IGFI0
IGFQ2
IGFQ1
IGFQ0
IFBC
LIMC
CHI2
CHI1
CHI0
CHD3
CHD2
CHD1
CHD0
VTRB2
VTRB1
VTRB0
VMRB3
VMRB2
VMRB1
VMRB0
A
M
IC
C
O
M
C
O
N
FI
D
EN
TI
A
L
36h
W
IGFI2
IFAT
37h
W
CHI3
Channel Select
38h
W
VTRB3
VRB
Legend: - = unimplemented
Jul., 2011, v1.3
14
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
9.2 Control Register Description
9.2.1 Mode Register (Address: 00h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
W
-RESETN
--
FECF
RESETN
--
CRCF
RESETN
--
CER
RESETN
--
XER
RESETN
--
PLLER
RESETN
--
TRSR
RESETN
--
TRER
RESETN
--
Reset
RESETN: Write to this register by 0x00 to issue reset command, then it is auto clear
L
FECF: FEC flag. (FECF is read only, it is updated for each valid packet.)
[0]: FEC pass. [1]: FEC error.
TI
A
CRCF: CRC flag. (CRCF is read only, it is updated for each valid packet.)
[0]: CRC pass. [1]: CRC error.
CER: RF chip enable status.
[0]: RF chip is disabled. [1]: RF chip is enabled.
EN
XER: Internal crystal oscillator enable status.
[0]: Crystal oscillator is disabled. [1]: Crystal oscillator is enabled.
PLLE: PLL enable status.
[0]: PLL is disabled. [1]: PLL is enabled.
TRSR: TRX Status Register.
[0]: RX state. [1]: TX state.
Serviceable if TRER=1 (TRX is enable).
Bit
R/W
Bit 7
Name
R
W
DDPC
DDPC
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ARSSI
ARSSI
0
AIF
AIF
0
CD
DFCD
0
WWSE
WWSE
0
FMT
FMT
0
FMS
FMS
0
ADCM
ADCM
0
M
Reset
C
O
9.2.2 Mode Control Register (Address: 01h)
N
FI
D
TRER: TRX state enable status.
[0]: TRX is disabled. [1]: TRX is enabled.
O
DDPC (Direct mode data pin control): Direct mode modem data can be accessed via SDIO pin when this register is
enabled.
[0]: Disable. [1]: Enable.
C
ARSSI: Auto RSSI measurement while entering RX mode.
[0]: Disable. [1]: Enable.
IC
AIF (Auto IF Offset): RF LO frequency will auto offset one IF frequency while entering RX mode.
[0]: Disable. [1]: Enable.
A
M
CD / DFCD:
DFCD (Data Filter by CD): The received packet will be filtered out if Carrier Detector signal is inactive.
[0]: Disable. [1]: Enable.
CD (Read): Carrier detector signal.
[0]: Input power below threshold. [1]: Input power above threshold.
WWSE: Reserved for internal usage only. Shall be set to [0].
FMT: Reserved for internal usage only. Shall be set to [0].
FMS: Direct/FIFO mode select.
[0]: Direct mode. [1]: FIFO mode.
ADCM: ADC measurement enable (Auto clear when done).
[0]: Disable measurement or measurement finished. [1]: Enable measurement.
ADCM
A7125 @ Standby mode
[0]
Disable ADC
[1]
Measure temperature
Jul., 2011, v1.3
A7125 @ RX mode
Disable ADC
Measure RSSI, carrier detect
15
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
Refer to chapter 17 for details.
9.2.3 Calibration Control Register (Address: 02h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
R/W
---
---
---
VCC
0
VBC
0
VDC
0
FBC
0
RSSC
0
VCC: VCO Current calibration enable (Auto clear when done).
[0]: Disable. [1]: Enable.
TI
A
L
VBC: VCO Bank calibration enable (Auto clear when done).
[0]: Disable. [1]: Enable.
VDC: VCO Deviation calibration enable (Auto clear when done).
[0]: Disable. [1]: Enable.
FBC: IF Filter Bank calibration enable (Auto clear when done).
[0]: Disable. [1]: Enable.
EN
RSSC: RSSI calibration enable (Auto clear when done).
[0]: Disable. [1]: Enable.
FI
D
9.2.4 FIFO Register I (Address: 03h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
FEP7
0
FEP6
0
FEP5
1
FEP4
1
FEP3
1
FEP2
1
FEP1
1
FEP0
1
C
O
N
FEP [7:0]: FIFO End Pointer for TX FIFO and Rx FIFO.
Refer to chapter 16 for details.
9.2.5 FIFO Register II (Address: 04h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
FPM1
0
FPM0
1
PSA5
0
PSA4
0
PSA3
0
PSA2
0
PSA1
0
PSA0
0
M
Bit
FPM [1:0]: FIFO Pointer Margin
C
O
PSA [5:0]: Used for Segment FIFO.
Refer to chapter 16 for details.
IC
9.2.6 FIFO DATA Register (Address: 05h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
FIFO7
0
FIFO6
0
FIFO5
0
FIFO4
0
FIFO3
0
FIFO2
0
FIFO1
0
FIFO0
0
A
M
Bit
Name
Reset
FIFO [7:0]: FIFO data. TX FIFO (Write only) and RX FIFO (Read only).
TX FIFO and RX FIFO share the same address (05h).
Refer to chapter 16 for details.
9.2.7 ID DATA Register (Address: 06h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
R/W
ID7
0
ID6
0
ID5
0
ID4
0
ID3
0
ID2
0
ID1
0
ID0
0
ID [7:0]: ID data.
Once this address is accessed, ID Data is input/output in sequence corresponding to Write or Read.
Refer to section 10.6 for details.
Jul., 2011, v1.3
16
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
9.2.8 RC OSC Register I (Address: 07h)
Bit
R/W
Name
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCOC5
RCOC4
RCOC3
RCOC2
RCOC1
RCOC0
WWS_SL7 WWS_SL6 WWS_SL5 WWS_SL4 WWS_SL3 WWS_SL2 WWS_SL1 WWS_SL0
Reset
0
0
0
0
0
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCOC [5:0]: Reserved for internal usage only.
R/W
W
Bit 7
Bit 6
WWS_SL9 WWS_SL8 WWS_AC5 WWS_AC4 WWS_AC3 WWS_AC2 WWS_AC1 WWS_AC0
0
0
0
0
0
Bit 4
WWS_AC [5:0]: Reserved for internal usage only.
Bit
R/W
Bit 7
Bit 6
Bit 5
Name
Reset
W
BBCKS1
0
BBCKS0
0
---
Bit 3
FI
D
9.2.10 RC OSC Register III (Address: 09h)
0
EN
WWS_SL [9:0]: Reserved for internal usage only.
TI
A
Bit
Name
Reset
L
9.2.9 RC OSC Register II (Address: 08h)
---
---
0
1
Bit 2
Bit 1
Bit 0
RCOSC_E
TSEL
0
TWWS_E
1
1
C
O
RCOSC_E: Reserved for internal usage only.
N
BBCKS [1:0]: Clock select for digital block. Recommend BBCKS = [00].
[00]: FSYCK / 8. [01]: FSYCK / 16. [10]: FSYCK / 32. [11]: FSYCK / 64.
FSYCK is A7125’s System clock = 64MHz.
TSEL: Reserved for internal usage only.
TWWS_E: Reserved for internal usage only.
M
9.2.11 CKO Pin Control Register (Address: 0Ah)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
ECKOE
1
CKOS3
0
CKOS2
1
CKOS1
1
CKOS0
1
CKOI
0
CKOE
1
SCKI
0
Bit 2
Bit 1
Bit 0
O
Bit
Name
Reset
C
ECKOE: External Clock Output Enable for CKOS [3:0]= [0100] ~ [0111].
[0]: Disable. [1]: Enable.
A
M
IC
CKOS [3:0]: CKO pin output select.
[0000]: DCK (TX data clock) in TX mode, RCK (RX recovery clock) in RX mode.
[0001]: DCK (TX data clock) in TX mode, RCK (RX recovery clock) in RX mode.
[0010]: FPF (FIFO pointer flag).
[0011]: EOVBC, EOFBC, EOADC, EOVCC, OKADC (Internal usage only).
[0100]: External clock output= FSYCK / 8.
[0101]: External clock output / 2= FSYCK / 16.
[0110]: External clock output / 4= FSYCK / 32.
[0111]: External clock output / 8= FSYCK / 64.
[1xxx]: Reserved.
CKOI: CKO pin output signal invert.
[0]: Non-inverted output. [1]: Inverted output.
CKOE: CKO pin Output Enable.
[0]: High Z. [1]: Enable.
SCKI: SPI clock input invert.
[0]: Non-inverted input. [1]: Inverted input.
9.2.12 GIO1 Pin Control Register (Address: 0Bh)
Bit
Jul., 2011, v1.3
R/W
Bit 7
Bit 6
Bit 5
Bit 4
17
Bit 3
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
---
GIO1S3
0
GIO1S2
0
GIO1S [3:0]: GIO1 pin function select.
GIO1S [3:0]
TX state
RX state
[0000]
WTR (Wait until TX or RX finished)
[0001]
(Reserved.)
FSYNC(frame sync)
[0010]
TMEO(TX modulation enable)
CD(carrier detect)
[0011]
Preamble Detect Output (PMDO)
[0100]
(Reserved.)
[0101]
In phase demodulator input(DMII)
[0110]
SDO ( 4 wires SPI data out)
[0111]
TRXD In/Out ( Direct mode )
[1000]
RXD ( Direct mode )
[1001]
TXD ( Direct mode )
[1010]
In phase demodulator external input(EXDI0)
[1011]
External FSYNC input in RX direct mode
[1100]
EOP (End Of Packet)
[1101]~[1111]
Inhibited
GIO1OE: GIO1pin output enable.
[0]: High Z. [1]: Enable.
9.2.13 GIO2 Pin Control Register (Address: 0Ch)
Bit 7
Bit 6
Name
Reset
W
---
---
Bit 5
GIO2S3
0
GIO1S0
0
GIO1I
0
GIO1OE
1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIO2S2
1
GIO2S1
0
GIO2S0
0
GIO2I
0
GIO2OE
1
N
R/W
C
O
Bit
FI
D
GIO1I: GIO1 pin output signal invert.
[0]: Non-inverted output. [1]: Inverted output.
GIO1S1
0
L
---
TI
A
W
EN
Name
Reset
A
M
IC
C
O
M
GIO2S [3:0]: GIO2 pin function select.
GIO2S
TX state
RX state
[0000]
WTR (Wait until TX or RX finished)
[0001]
PASW (Output Signal to
FSYNC(frame sync)
switch off external PA ) *
[0010]
TMEO(TX modulation enable)
CD(carrier detect)
[0011]
Preamble Detect Output (PMDO)
[0100]
(Reserved.)
[0101]
Quadrature phase demodulator input(DMIQ)
[0110]
SDO ( 4 wires SPI data out )
[0111]
TRXD In/Out ( Direct mode )
[1000]
RXD ( Direct mode )
[1001]
TXD ( Direct mode )
[1010]
Quadrature phase demodulator external input(EXDI1)
[1011]
External FSYNC input in RX direct mode
[1100]
EOPD (End Of Packet Delay) *
[1101]~[1111]
Inhibited
* Refer to Section 14.3 for details.
GIO2I: GIO2 pin output signal invert.
[0]: Non-inverted output. [1]: Inverted output.
GIO2OE: GIO2 pin Output Enable.
[0]: High Z. [1]: Enable.
In TX Mode.
Timing diagram among WTR, EOP and EOPD are illustrated below when EOPDS = 1. However, if EOPDS = 0, T2~T4 is
around 1 us only.
Jul., 2011, v1.3
18
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
SPI
(SCS,SCK,SDIO)
Next Instruction
No Command Required
TX-Strobe
PLL Mode
(dummy bits)
PDL+TDL
RF Port
Auto Back
PLL Mode
Preamble + ID Code + Payload + CRC
GIO1 Pin - WTR
(GIO1S[3:0]=0000)
W
L
GIO1 Pin - EOP
(GIO1S[3:0]=1100)
GIO2 Pin - EOPD
(GIO2S = 1100)
T0
T2
T1
T3
T4
EN
< 1us
TI
A
20 us
CRC
Enable
4 bytes (default)
4 bytes (recommend)
Disable
Payload (Byte)
64
32
16
W (us)
3.5
11.5
15.5
64
32
16
11.5
19.5
3.5
FI
D
ID
4 bytes (recommend)
C
O
N
Preamble
4 bytes (default)
SPI
(SCS,SCK,SDIO)
M
In RX Mode.
WTR goes low when last bit is recieved. Compared to TX mode, there are no dummy bits in RX mode. Hence, user can
monitor the falling edge of WTR (if EOPDS=1) to turn on RX mode ahead of tunning on counterpart to TX mode for stable
transmission timeslot.
TX-Strobe
PLL Mode
O
Preamble + ID Code + Payload + CRC
IC
GIO1 Pin - WTR
(GIO1S[3:0]=0000)
Auto Back
PLL Mode
PDL+TDL
C
RF Port
Next Instruction
No Command Required
A
M
GIO1 Pin - EOP
(GIO1S[3:0]=1100)
GIO2 Pin - EOPD
(GIO2S = 1100)
T0
T2
T1
< 1us
9.2.14 Data Rate Clock Register (Address: 0Dh)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
W
SDR1
SDR1
0
SDR0
SDR0
0
GRC3
GRC3
0
GRC2
GRC2
1
GRC1
GRC1
1
GRC0
GRC0
1
-CGS
1
-XS
1
Reset
SDR [1:0]: Data rate setting.
Jul., 2011, v1.3
19
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
Data Rate
EN
GRC [3:0]: Generator Reference Counter
Due to A7125 supports different external crystals,
GRC is used to get 2 MHz Clock Generator Reference (FCGR) for internal usage.
.
Clock Generation
External Crystal (FXREF)
GRC [3:0]
Reference (CGR)
16 MHz
Must be 2 MHz
[0111]
12 MHz
Must be 2 MHz
[0101]
8 MHz
Must be 2 MHz
[0011]
6 MHz
Must be 2 MHz
[0010]
Refer to chapter 13 for details.
A
M
IC
C
O
M
C
O
N
FI
D
CGS: Clock generator enable. Shall be set to [1].
[0]: Disable. [1]: Enable.
XS: Crystal oscillator select. Recommend XS = [1]
[0]: Use external clock. [1]: Use external crystal.
L
2 Mbps
1 Mbps
Reserved
Reserved
TI
A
FSYCK
(Internal system clock)
[00]
64 MHz
[01]
64 MHz
[10]
64 MHz
[11]
64 MHz
Refer to chapter 13 for details.
SDR [1:0]
Jul., 2011, v1.3
20
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
9.2.15 PLL Register I (Address: 0Eh)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
R/W
CHN7
0
CHN6
0
CHN5
0
CHN4
0
CHN3
0
CHN2
0
CHN1
0
CHN0
0
CHN [7:0]: RF LO channel number.
Change CHN to do frequency hopping. Refer to chapter 14 for details.
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Name
R
W
DBL
DBL
0
RRC1
RRC1
0
RRC0
RRC0
1
CHR3
CHR3
0
CHR2
CHR2
1
CHR1
CHR1
1
Reset
RRC [1:0]: RF PLL reference counter setting.
Refer to chapter 14 for details.
IP8
BIP8
0
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
W
IP7
BIP7
1
IP6
BIP6
0
IP5
BIP5
0
IP4
BIP4
1
IP3
BIP3
0
IP2
BIP2
1
IP1
BIP1
1
IP0
BIP0
0
Bit 5
Bit 4
Bit 3
Bit 2
C
O
Bit 4
N
9.2.17 PLL Register III (Address: 10h)
FI
D
CHR [3:0]: PLL channel step setting.
Reset
Bit 0
EN
DBL: Crystal frequency doubler enable.
[0]: Disable. FXREF = FXTAL. [1]: Enable. FXREF =2 * FXTAL.
Bit 1
CHR0
CHR0
1
TI
A
Bit
L
9.2.16 PLL Register II (Address: 0Fh)
BIP [8:0]: LO base frequency integer part setting.
BIP [8:0] are from address (0Fh) and (10h),
O
Refer to chapter 14 for details.
M
IP [8:0]: LO frequency integer part value.
IP [8:0] are from address (0Fh) and (10h),
Bit
R/W
Bit 7
R
W
--/FP15
IC
Name
C
9.2.18 PLL Register IV (Address: 11h)
A
M
Reset
BFP15
0
Bit 6
AC14/FP14 AC13/FP13 AC12/P12 AC11/ FP11 AC10/FP10
BFP14
0
Bit 1
Bit 0
AC9/FP9
AC8/FP8
BFP13
0
BFP12
0
BFP11
0
BFP10
0
BFP9
0
BFP8
0
9.2.19 PLL Register V (Address: 12h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
W
AC7/FP7
AC6/FP6
AC5/FP5
AC4/FP4
AC3/FP3
AC2/FP2
AC1/FP1
AC0/FP0
BFP7
0
BFP6
0
BFP5
0
BFP4
0
BFP3
0
BFP2
1
BFP1
0
BFP0
0
Bit 3
Bit 2
Bit 1
Bit 0
Reset
BFP [15:0]: LO base frequency fractional part setting.
BFP [15:0] are from address (11h) and (12h),
AC [14:0] (Read): Frequency compensation value if AFC (19h) =1.
FP [15:0] (Read): LO frequency fractional part setting.
Refer to chapter 14 for details.
9.2.20 Channel Group Register I (Address: 13h)
Bit
Jul., 2011, v1.3
R/W
Bit 7
Bit 6
Bit 5
Bit 4
21
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
Name
Reset
R/W
CHGL7
0
CHGL6
0
CHGL5
1
CHGL4
1
CHGL3
1
CHGL2
1
CHGL1
0
CHGL0
0
CHGL [7:0]: PLL channel group low boundary setting.
Refer to chapter 15 for details.
9.2.21 Channel Group Register II (Address: 14h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
CHGH7
0
CHGH6
1
CHGH5
1
CHGH4
1
CHGH3
1
CHGH2
0
CHGH1
0
CHGH0
0
TI
A
CHGH [7:0]: PLL channel group high boundary setting.
Refer to chapter 15 for details.
L
Bit
Name
Reset
9.2.22 TX Register I (Address: 15h)
R/W
Bit 7
Bit 6
Bit 5
Name
Reset
W
SDMS
1
TMDE
1
TXDI
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TME
1
---
FDP2
1
FDP1
1
FDP0
0
N
Bit
FI
D
EN
PLL frequency is divided into 3 groups:
Channel
Group1
0 ~ CHGL-1
Group2
CHGL ~ CHGH-1
Group3
CHGH ~ 255
C
O
SDMS: Reserved for internal usage only. Shall be set to [1].
TMDE: TX data VCO modulation enable.
[0]: Disable. [1]: Enable.
TME: TX modulation enable.
[0]: Disable. [1]: Enable.
M
TXDI: TX data invert. Recommend TXDI = [0].
[0]: Non-invert. [1]: Invert.
O
FDP [2:0]: Frequency deviation power setting. Refer to control register (16h).
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FD7
1
FD6
1
FD5
0
FD4
0
FD3
0
FD2
0
FD1
0
FD0
0
R/W
IC
Bit
C
9.2.23 TX Register II (Address: 16h)
Name
Reset
W
A
M
FD [7:0]: Frequency deviation setting.
Frequency deviation:
(FDP [2:0] + 1)
26
FDEV= FPFD * 127 * (FD [7:0] + 1) * 2
/2 .
Recommend FDEV = 500 KHz.
Jul., 2011, v1.3
22
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
9.2.24 Delay Register I (Address: 17h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
EOPDS
0
DPR1
0
DPR0
0
TDL1
1
TDL0
0
PDL2
0
PDL1
1
PDL0
0
L
EOPDS: End Of Packet Delay Select.
[0]: 1us. [1]: 20 us.
Recommend EOPDS = [0] in external PA free requirement.
Recommend EOPDS = [1] in external PA application. See below timing diagram.
TI
A
G IO 1 P in
(W T R )
EOPDS=1
(2 0 u s )
EN
T X S tro b e C m d
G IO 2 P in
(E O P D )
T im e Z o n e to ind ic a te
M C U to sw itch o ff e xt P A
DPR [1:0]: Delay scale. Recommend DPR = [00].
FI
D
TDL [1:0]: Delay for TRX settling from WPLL to TX/RX.
Delay= 20 * (TDL [1:0] + 1) * (DPR [1:0] + 1) us.
DPR [1:0]
TDL [1:0]
WPLL to TX
00
00
20 us
00
01
40 us
00
10
60 us
00
11
80 us
Note
C
O
N
Recommend
C
O
M
PDL [2:0]: Delay for TX settling from PLL to WPLL.
Delay= 10+20 * (PDL [2:0] + 1) * (DPR [1:0] + 1) us.
DPR [1:0]
PDL [2:0]
PLL to WPLL
(LO freq. fixed)
00
000
10 us
00
001
10 us
00
010
10 us
00
011
10 us
PLL M ode
IC
G IO 1 P in
(W T R )
PLL to WPLL
(LO freq changed)
30 us
50 us
70 us
90 us
Note
Recommend
TX M ode
T X S tro be
R F O P in
A
M
P a ck e t
PDL
TDL
9.2.25 Delay Register II (Address: 18h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Name
Reset
W
WSEL2
0
WSEL1
1
WSEL0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RSSC_D1 RSSC_D0 RS_DLY2 RS_DLY1 RS_DLY0
0
0
0
0
1
WSEL [2:0]: XTAL settling delay setting (200us ~ 2.5ms). Recommend WSEL = [011].
[000]: 200us. [001]: 400us. [010]: 800us, [011]: 600us.
[100]: 1ms. [101]: 1.5ms. [110]: 2ms. [111]: 2.5ms.
Jul., 2011, v1.3
23
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
C ry s ta l
O sc illa to r
Id le
m o de
T X o r R X m od e
W SEL
30 0 us
G IO 1 P in
(W T R )
P a ck e t ( P r e a m b le + ID + P a ylo a d )
PD L
TD L
TI
A
RSSC_D [1:0]: RSSI calibration switching time (10us ~ 40us). Recommend RSSC_D = [00].
[00]: 10us. [01]: 20us. [10]: 30us. [11]: 40us.
L
R F O P in
9.2.26 RX Register (Address: 19h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Name
Reset
W
---
RXSM1
1
RXSM0
0
FC
0
Bit 3
Bit 2
Bit 1
Bit 0
RXDI
0
DMG
0
RAW
1
ULS
0
FI
D
Bit
EN
RS_DLY [2:0]: RSSI measurement delay (10us ~ 80us). Recommend RS_DLY = [001].
[000]: 10us. [001]: 20us. [010]: 30us. [011]: 40us.
[100]: 50us. [101]: 60us. [110]: 70us. [111]: 80us.
RXSM0: Reserved for internal usage only. Shall be set to [1].
C
O
AFC: Auto Frequency compensation.
[0]: Disable. [1]: Enable.
Refer to section 14.4 for details.
N
RXSM1: Reserved for internal usage only. Shall be set to [1].
RXDI: RX data output invert. Recommend RXDI = [0].
[0]: Non-inverted output. [1]: Inverted output.
DMG: Reserved for internal usage only. Shall be set to [0].
M
RAW: Reserved for internal usage only. Shall be set to [1].
C
O
ULS: RX Up/Low side band select.
[0]: Up side band, [1]: Low side band.
Refer to section 14.2 for details.
9.2.27 RX Gain Register I (Address: 1Ah)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
MVGS
0
MRHL
0
IGS
0
MGS1
0
MGS0
0
LGS2
0
LGS1
0
LGS0
0
IC
Bit
A
M
Name
Reset
MVGS: Manual VGA setting.
[0]: Auto. [1]: Manual.
MRHL: Manual RH, RL setting.
[0]: Auto. [1]: Manual.
IGS: Reserved for internal usage only. Shall be set to [1].
MGS [1:0]: Mixer gain attenuation select. Recommend MGS = [00].
[00]: 0dB. [01]: -6dB. [10]: -12dB. [11]: -18dB.
LGS [2:0]: LNA gain attenuation select. Recommend LGS = [000].
[000]: 0dB. [001]: -6dB. [010]: -12dB. [011]: -18dB. [1XX]: -24dB.
9.2.28 RX Gain Register II (Address: 1Bh)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
R/W
RH7
1
RH 6
0
RH5
0
RH4
0
RH3
0
RH2
0
RH1
0
RH0
0
Jul., 2011, v1.3
24
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
RH [7:0]: AGC calibration high threshold.
9.2.29 RX Gain Register III (Address: 1Ch)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
R/W
RL7
1
RL6
0
RL5
0
RL4
0
RL3
0
RL2
0
RL1
0
RL0
0
Bit 2
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Name
Reset
W
AVSEL1
0
AVSEL0
1
MVSEL1
0
MVSEL0
0
MHC
1
Bit 1
TI
A
9.2.30 RX Gain Register IV (Address: 1Dh)
L
RL [7:0]: AGC calibration low threshold.
LHC1
1
LHC0
1
Bit 0
AGCE
0
EN
AVSEL [1:0]: ADC average times (AGC mode). Recommend AVSEL = [11].
[00]: No average. [01]: Average 2 times. [10]: Average 4 times. [11]: Average 8 times.
MVSEL [1:0]: ADC average times (VCO calibration and RSSI measurement mode). Recommend MVSEL = [01].
[00]: Average 8 times. [01]: Average 16 times. [10]: Average 32 times. [11]: Average 64 times.
FI
D
MHC: Reserved for internal usage only. Shall be set to [0].
LHC: Reserved for internal usage only. Shall be set to [01].
N
AGCE: AGC active enable.
[0]: End AGC. [1]: AGC active.
Bit
R/W
Bit 7
Name
R
W
ADC7
RTH7
1
Reset
C
O
9.2.31 RSSI Threshold Register (Address: 1Eh)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC6
RTH6
0
ADC5
RTH5
0
ADC4
RTH4
1
ADC3
RTH3
0
ADC2
RTH2
0
ADC1
RTH1
0
ADC0
RTH0
1
O
M
RTH [7:0]: Carrier detect threshold.
Refer to chapter 17 for details.
IC
C
ADC [7:0]: ADC output value of temperature, RSSI .
ADC input voltage= 0.3 + 1.2 * ADC [7:0] / 256 V.
Refer to chapter 17 for details.
9.2.32 ADC Control Register (Address: 1Fh)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
RSM1
0
RSM0
1
RADC1
0
RADC0
0
FSARS
1
XADS
0
RSS
1
CDM
1
A
M
Bit
RSM [1:0]: RSSI margin = RTH – RTL. Recommend RSM = [11].
[00]: 5. [01]: 10. [10]: 15. [11]: 20.
Refer to chapter 17 for details.
RADC: ADC read out average mode.
[00]: No average.
[01]: 1, 2, 4, 8 average mode. The average number is according to the setting of AVSEL (in RX Gain Register IV).
[10]: 8, 16, 32, 64 average mode. The average number is according to the setting of MVSEL (in RX Gain Register IV).
[11]: Reserved.
FSARS: ADC clock select.
[0]: 4MHz. [1]: 8MHz.
XADS: ADC input signal select.
[0]: Convert RSS signal. [1]: Reserved for internal usage.
Jul., 2011, v1.3
25
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
RSS: Temperature / RSSI measurement select.
[0]: Temperature. [1]: RSSI or carrier-detect measurement.
CDM: RSSI measurement mode. Recommend CDM = [0].
[0]: Single mode. [1]: Continuous mode.
9.2.33 Code Register I (Address: 20h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
---
---
WHTS
0
FECS
0
CRCS
0
IDL
1
PML1
1
PML0
1
L
Bit
TI
A
WHTS: Data whitening (Data Encryption) select.
[0]: Disable. [1]: Enable.
FECS: FEC select.
[0]: Disable. [1]: Enable.
EN
CRCS: CRC select.
[0]: Disable. [1]: Enable.
IDL: ID code length select. Recommend IDL= [1].
[0]: 2 bytes. [1]: 4 bytes.
FI
D
PML [1:0]: Preamble length select. Recommend PML= [11].
[00]: 1 byte. [01]: 2 bytes. [10]: 3 bytes. [11]: 4 bytes.
9.2.34 Code Register II (Address: 21h)
R/W
Bit 7
Bit 6
Name
Reset
W
---
DCL2
1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DCL1
1
DCL0
1
ETH1
0
ETH0
1
PMD1
1
PMD0
1
C
O
Bit
N
Refer to chapter 16 for details.
DCL [2:0]: Demodulator DC estimation average mode. Refer to DCM (2Eh) for details.
M
DCL2: For payload average mode. Recommend DCL2 = [1].
[0]: 128 bits average. [1]: 256 bits average.
O
DCL1: For average and hold mode. Recommend DCL1 = [0].
[0]: 32 bits average. [1]: 64 bits average.
C
DCL0: Preamble detect delay. Count from preamble detected signal. Recommend DCL0 = [1].
[0]: 4 bits for DCL1=0, 8 bits for DCL1=1. [1]: 8 bits for DCL1=0, 16 bits for DCL1=1.
IC
ETH [1:0]: ID code error tolerance. Recommend ETH = [01].
[00]: 0 bit, [01]: 1 bit. [10]: 2 bit. [11]: 3 bit.
A
M
PMD [1:0]: Preamble pattern detection length. Recommend PMD = [10].
[00]: 0bit. [01]: 4bits. [10]: 8bits. [11]: 16bits.
Refer to chapter 16 for details.
9.2.35 Code Register III (Address: 22h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
---
WS6
0
WS5
1
WS4
0
WS3
1
WS2
0
WS1
1
WS0
0
WS [6:0]: Data Whitening seed setting (data encryption key).
Refer to chapter 16 for details.
9.2.36 IF Calibration Register I (Address: 23h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
--
--
--
FBCF
FB3
FB2
FB1
FB0
Jul., 2011, v1.3
26
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
W
Reset
---
---
---
MFBS
0
MFB3
0
MFB2
1
MFB1
1
MFB0
0
MFBS: IF filter calibration value select. Recommend MFBS = [0].
[0]: Auto calibration value. [1]: Manual calibration value.
MFB [3:0]: IF filter manual calibration value.
FBCF: IF filter auto calibration flag.
[0]: Pass. [1]: Fail.
Refer to chapter 15 for details.
9.2.37 IF Calibration Register II (Address: 24h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
R
---
---
---
FCD4
--
FCD3
--
FI
D
FCD [4:0]: IF filter auto calibration deviation.
Bit 3
Bit 2
Bit 1
Bit 0
FCD2
--
FCD1
--
FCD0
--
EN
Bit
Name
Reset
TI
A
L
FB [3:0]: IF filter calibration value.
MFBS= 0: Auto calibration value (AFB),
MFBS= 1: Manual calibration value (MFB).
9.2.38 VCO Current Calibration Register (Address: 25h)
R/W
Bit 7
Bit 6
Bit 5
Name
R
W
----
----
-VCCS
1
Bit 3
Bit 2
Bit 1
Bit 0
VCCF
MVCS
0
VCB3
VCOC3
1
VCB2
VCOC2
1
VCB1
VCOC1
0
VCB0
VCOC0
0
C
O
Reset
Bit 4
N
Bit
VCCS: Reserved for internal usage only. Shall be set [0].
MVCS: VCO current calibration value select. Recommend MVCS = [0].
[0]: Auto calibration value. [1]: Manual calibration value.
M
VCOC [3:0]: VCO current manual calibration value.
O
FVCC: VCO current auto calibration flag.
[0]: Pass. [1]: Fail.
IC
C
VCB [3:0]: VCO current calibration value.
MVCS= 0: Auto calibration value (AVCB).
MVCS= 1: Manual calibration value (VCOC).
Refer to chapter 15 for details.
A
M
9.2.39 VCO Bank Calibration Register I (Address: 26h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
W
-DDC1
1
-DDC0
1
-MDAGS
0
----
VBCF
MVBS
0
VB2
MVB2
1
VB1
MVB1
0
VB0
MVB0
0
Reset
DDC [1:0]: VCO deviation calibration delay. Recommend DDC = [01].
Delay time = PLL delay time × ( DDC + 1 ).
MDAGS: DAG calibration value select. Recommend MDAGS = [0].
[0]: Auto calibration value. [1]: Manual calibration value.
MVBS: VCO bank calibration value select. Recommend MVBS = [0].
[0]: Auto calibration value. [1]: Manual calibration value.
MVB [2:0]: VCO band manual calibration value.
VBCF: VCO band auto calibration flag.
[0]: Pass. [1]: Fail.
Jul., 2011, v1.3
27
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
VB [2:0]: VCO bank calibration value.
MVBS= 0: Auto calibration value (AVB).
MVBS= 1: Manual calibration value (MVB).
Refer to chapter 15 for details.
9.2.40 VCO Bank Calibration Register II (Address: 27h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
W
ADAG7
MDAG7
1
ADAG6
MDAG6
0
ADAG5
MDAG5
0
ADAG4
MDAG4
0
ADAG3
MDAG3
0
ADAG2
MDAG2
0
ADAG1
MDAG1
0
ADAG0
MDAG0
0
MDAG [7:0]: DAG manual calibration value. Recommend MDAG = [0x80].
9.2.41 VCO Deviation Calibration Register I (Address: 28h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Name
R
W
DEVA7
DEVS3
0
DEVA6
DEVS2
1
DEVA5
DEVS1
1
DEVA4
DEVS0
1
Reset
Bit 3
Bit 2
DEVA3
DEVA2
DAMR_M VMTE_M
0
0
FI
D
Bit
EN
ADAG [7:0]: DAG auto calibration value.
TI
A
Reset
L
Bit
Bit 1
Bit 0
DEVA1
VMS_M
0
DEVA0
MSEL
0
DEVS [3:0]: Deviation output scaling. Recommend DEVS = [0011].
N
DAMR_M: DAMR manual enable. Recommend DAMR_M = [0].
[0]: Disable. [1]: Enable.
C
O
VMTE_M: VMT manual enable. Recommend VMTE_M = [0].
[0]: Disable. [1]: Enable.
VMS_M: VM manual enable. Recommend VMS_M = [0].
[0]: Disable. [1]: Enable.
M
MSEL: VMS, VMTE and DAMR control select. Recommend MSEL = [0].
[0]: Auto control. [1]: Manual control.
C
O
DEVA [7:0]: Deviation output value.
MVDS= 0: Auto calibration value ((ADEV / 8) × (DEVS + 1)),
MVDS= 1: Manual calibration value (MDEV).
9.2.42 VCO Deviation Calibration Register II (Address: 29h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
W
ADEV7
MVDS
0
ADEV6
MDEV6
0
ADEV5
MDEV5
1
ADEV4
MDEV4
0
ADEV3
MDEV3
1
ADEV2
MDEV2
0
ADEV1
MDEV1
0
ADEV0
MDEV0
0
IC
Bit
Name
A
M
Reset
MVDS: VCO deviation calibration value select. Recommend MVDS = [0].
[0]: Auto calibration value. [1]: Manual calibration value.
MDEV [6:0]: VCO deviation manual calibration value.
ADEV [7:0]: VCO deviation auto calibration value.
Refer to chapter 15 for details.
9.2.43 VCO Deviation Calibration Register III (Address: 2Ah)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
VMG7
1
VMG6
0
VMG5
0
VMG4
0
VMG3
0
VMG2
0
VMG1
0
VMG0
0
VMG [7:0]: Reserved for internal usage only. Shall be set to [0x80].
Jul., 2011, v1.3
28
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
9.2.44 VCO Modulation Delay Register (Address: 2Bh)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
---
---
DEVFD2
0
DEVFD1
0
DEVFD0
0
DEVD2
0
DEVD1
0
DEVD0
0
DEVFD [2:0]: Reserved for internal usage only. Shall be set to [000].
DEVD [2:0]: Reserved for internal usage only. Shall be set to [000].
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Name
R
W
-RGS
0
-RGV1
1
-RGV0
0
BDF
QDS
0
-BVT2
0
-BVT1
1
Reset
Bit 0
-BVT0
1
-BD_E
0
EN
RGS: VDD_D voltage setting in Sleep mode.
[0]: 3/5 * REGI. [1]: 3/4 * REGI.
Bit 1
TI
A
Bit
L
9.2.45 Battery Detect Register (Address: 2Ch)
RGV [1:0]: VDD_D and VDD_A voltage setting in non-Sleep mode. Recommend RGV = [11].
[00]: 2.1V. [01]: 2.0V. [10]: 1.9V. [11]: 1.8V.
FI
D
QDS: Reserved for internal usage only. Shall be set [1].
N
BVT [2:0]: Battery voltage detect threshold.
[000]: 2.0V. [001]: 2.1V. [010]: 2.2V. [011]: 2.3V.
[100]: 2.4V. [101]: 2.5V. [110]: 2.6V. [111]: 2.7V.
C
O
BD_E: Battery detect enable.
[0]: Disable. [1]: Enable. It will be clear after battery detection done.
BDF: Battery detect flag.
[0]: Battery voltage less than threshold. [1]: Battery voltage greater than threshold.
M
Refer to chapter 19 for details.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
O
9.2.46 TX test Register (Address: 2Dh)
R/W
Name
Reset
W
---
TXCS
0
PAC1
1
PAC0
0
TBG2
1
TBG1
1
TBG0
1
---
C
Bit
TXCS: TX Current Setting.
IC
PAC [1:0]: PA Current Setting.
A
M
TBG [2:0]: TX Buffer Setting.
Typical
Recommend setting
Typical
Output Power (dBm)
TXCS
TBG
PAC
TX current (mA)
3
1
7
2
21
0
1
7
0
15.7
-10
1
4
0
13.7
-20
1
0
0
13.3
Also, refer to App. Note for more setting of TX power level.
9.2.47 RX DEM test Register I (Address: 2Eh)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
DMT
0
DCM1
1
DCM0
1
MLP1
0
MLP0
0
SLF2
1
SLF1
0
SLF0
0
Jul., 2011, v1.3
29
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
DMT: Reserved for internal usage only. Shall be set to [0].
DCM [1:0]: Demodulator DC estimation mode.
[00]: Fix mode (For ±10ppm crystal accuracy only). DC level is set by DCV [7:0].
[01]: Preamble hold mode. DC level is preamble average value at PMDO.
[10]: Average and hold mode. DC level is the average value at PMDO with DCL0 delay.
[11]: Payload average mode (For internal usage). DC level is payload data average.
MLP [1:0]: Reserved for internal usage only. Shall be set to [00].
L
SLF [2:0]: Reserved for internal usage only. Shall be set to [111].
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Name
Reset
W
DCV7
0
DCV6
1
DCV5
0
DCV4
0
DCV3
0
9.2.49 Charge Pump Current Register I (Address: 30h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Name
Reset
W
CPM3
1
CPM2
1
CPM1
1
CPM0
1
Bit 1
Bit 0
DCV2
0
DCV1
0
DCV0
0
Bit 3
Bit 2
Bit 1
Bit 0
CPT3
1
CPT2
1
CPT1
1
CPT0
1
FI
D
Bit
Bit 2
EN
DCV [7:0]: Demodulator fix mode DC value. Recommend DCV = [0x80].
TI
A
9.2.48 RX DEM test Register II (Address: 2Fh)
CPM [3:0]: Charge pump current setting for VM loop. Recommend CPM = [1111].
Charge pump current = (CPM + 1) / 16 mA.
C
O
N
CPT [3:0]: Charge pump current setting for VT loop. Recommend CPT = [0001].
Charge pump current = (CPT + 1) / 16 mA.
9.2.50 Charge Pump Current Register II (Address: 31h)
R/W
Bit 7
Name
Reset
W
CPTX3
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPTX2
1
CPTX1
1
CPTX0
1
CPRX3
0
CPRX2
0
CPRX1
1
CPRX0
1
M
Bit
O
CPTX [3:0]: Charge pump current setting for TX mode. Recommend CPTX = [0001].
Charge pump current = (CPTX + 1) / 16 mA.
C
CPRX [3:0]: Charge pump current setting for RX mode. Recommend CPRX = [0001].
Charge pump current = (CPRX + 1) / 16 mA.
IC
9.2.51 Crystal test Register (Address: 32h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
---
---
---
---
DBD
0
XCC
1
XCP1
0
XCP0
0
A
M
Bit
Name
Reset
DBD: Reserved for internal usage only. Shall be set to [0].
XCC: Reserved for internal usage only. Shall be set to [1].
XCP [1:0]: Reserved for internal usage only. Shall be set to [00].
9.2.52 PLL test Register (Address: 33h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
---
CPS
1
PRRC1
0
PRRC0
1
PRIC1
0
PRIC0
0
SDPW
0
NSDO
1
CPS: Reserved for internal usage only. Shall be set to [1].
PRRC [1:0]: Reserved for internal usage only. Shall be set to [00].
PRIC [1:0]: Reserved for internal usage only. Shall be set to [01].
Jul., 2011, v1.3
30
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
SDPW: Reserved for internal usage only. Shall be set to [0].
NSDO: Reserved for internal usage only. Shall be set to [1].
9.2.53 VCO test Register (Address: 34h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
---
---
---
TLB1
1
TLB0
1
RLB1
0
RLB0
0
VCBS
0
L
TLB [1:0]: Reserved for internal usage only. Shall be set to [11].
VCBS: Reserved for internal usage only. Shall be set to [0].
9.2.54 RF Analog test Register (Address: 35h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Name
Reset
W
OLM
0
VTBS
0
CPH
0
CPCS
0
Bit 3
Bit 2
Bit 1
Bit 0
RFT2
0
RFT1
0
RFT0
0
EN
Bit
TI
A
RLB [1:0]: Reserved for internal usage only. Shall be set to [00].
---
FI
D
OLM: Reserved for internal usage only. Shall be set to [0].
VTBS: Reserved for internal usage only. Shall be set to [0].
CPH: Reserved for internal usage only. Shall be set to [0].
N
CPCS: Reserved for internal usage only. Shall be set to [1].
C
O
RFT [2:0]: RF analog pin configuration. Recommend RFT= [000].
{XADS, RFT[2:0]}
BP_BG
[0000]
Band-gap voltage
[0001]
Analog temperature voltage
[0010]
Band-gap voltage
[0011]
Analog temperature voltage
[0100]
BPF positive in phase output
[0101]
BPF positive quadrature phase output
[0110]
No connection
[0111]
No connection
[1000]
Band-gap voltage
[1001]
Analog temperature voltage
[1010]
Band-gap voltage
[1011]
Analog temperature voltage
[1100]
No connection
[1101]
No connection
[1110]
No connection
[1111]
No connection
A
M
IC
C
O
M
BP_RSSI
RSSI voltage
RSSI voltage
No connection
No connection
BPF negative in phase output
BPF negative quadrature phase output
No connection
No connection
External ADC input source
External ADC input source
External ADC input source
External ADC input source
External ADC input source
External ADC input source
External ADC input source
External ADC input source
9.2.55 IFAT Register (Address: 36h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
IGFI2
1
IGFI1
0
IGFI0
0
IGFQ2
1
IGFQ1
0
IGFQ0
0
IFBC
1
LIMC
1
IGFI [2:0]: Reserved for internal usage only. Shall be set to [111].
IGFQ [2:0]: Reserved for internal usage only. Shall be set to [111].
IFBC: Reserved for internal usage only. Shall be set to [1].
LIMC: Reserved for internal usage only. Shall be set to [1].
Jul., 2011, v1.3
31
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
9.2.56 Channel Select Register (Address: 37h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
CHI3
0
CHI2
1
CHI1
0
CHI0
0
CHD3
0
CHD2
1
CHD1
0
CHD0
0
CHI [3:0]: Auto IF offset channel number setting.
FCHSP * (CHI + 1) = 2MHz
Refer to chapter 14 for FCHSP setting.
9.2.57 VRB Register (Address: 38h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
W
VTRB3
0
VTRB2
0
VTRB1
0
VTRB0
0
VMRB3
0
Bit 1
Bit 0
VMRB1
0
VMRB0
0
A
M
IC
C
O
M
C
O
N
FI
D
VTRB [3:0]: Reserved for internal usage only. Shall be set to [1111].
VMRB [3:0]: Reserved for internal usage only. Shall be set to [1111].
Bit 2
VMRB2
0
EN
Bit
Name
Reset
TI
A
L
CHD [3:0]: The channel frequency offset for deviation calibration. If FCHSP = 500KHz, recommend CHD = [0111].
Offset channel number = +/- (CHD + 1).
Jul., 2011, v1.3
32
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
10. SPI
A7125 only supports one SPI bus with maximum data rate 10Mbps. MCU should assert SCS pin low (SPI chip select) to
active accessing of A7125. Via SPI bus, user can access control registers and issue Strobe command. Figure 10.1 gives
an overview of SPI access manners.
3-wire SPI (SCS, SCK and SDIO) or 4-wire SPI (SCS, SCK, SDIO and GIO1/GIO2) configuration is provided. For 3-wire
SPI, SDIO pin is configured as bi-direction to be data input and output. For 4-wire SPI, SDIO pin is data input and GIO1 (or
GIO2) pin is data output. In such case, GIO1S (0bh) or GIO2S (0ch) should be set to [0110].
TI
A
L
For SPI write operation, SDIO pin is latched into A7125 at the rising edge of SCK. For SPI read operation, if input address
is latched by A7125, data output is aligned at falling edge of SCK. Therefore, MCU can latch data output at the rising edge
of SCK.
To control A7125’s internal state machine, it is very easy to send Strobe command via SPI bus. The Strobe command is a
unique command set with total 8 commands. See section 10.3, 10.4 and 10.5 for details.
Data In
Data Out
3-Wire SPI
SCS pin = 0
SDIO pin
SDIO pin
4-Wire SPI
SCS pin = 0
SDIO pin
GIO1 (GIO1S=0110) /
GIO2 (GIO2S=0110)
Read/Write ID
register
DataByte0
ADDRreg
DataByte
DataByte1
ADDRreg
DataByte2
DataByte
DataByte3
DataByten
DataByte0 DataByte1 DataByte2 DataByte3
Strobe
CommandSleep Mode
M
Strobe
CommandIdle Mode
Idle Mode
Strobe
CommandSTBY Mode
O
STBY Mode
C
Strobe
CommandPLL Mode
Strobe
CommandRX Mode
IC
RX Mode
ADDRFIFO
ADDRID
Sleep Mode
PLL Mode
DataByte
N
Read/Write RF
FIFO
ADDRreg
C
O
Read/Write register
FI
D
SCS
EN
SPI chip select
A
M
TX Mode
Strobe
CommandTX Mode
FIFO Write Reset
Strobe
CommandFIFO Write Reset
FIFO Read Reset
Strobe
CommandFIFO Read
Reset
Figure 10.1 SPI Access Manners
Jul., 2011, v1.3
33
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
10.1 SPI Format
The first bit (A7) is critical to indicate A7125 the following instruction is “Strobe command” or “control register”. See Table
10.1 for SPI format. Based on Table 10.1, if A7=0, A7125 is informed for control register accessing. So, A6 bit is used to
indicate read (A6=1) or write operation (A6=0). See Figure 10.2 and Figure 10.3 for details.
CMD
A7
R/W
A6
Address Byte (8 bits)
Address
A5
A4
A3
A2
A1
A0
7
6
5
Data Byte (8 bits)
Data
4
3
2
1
0
L
Table 10.1 SPI Format
TI
A
Address byte:
Bit 7: Command bit
[0]: Control register command.
[1]: Strobe command.
EN
Bit 6: R/W bit
[0]: Write data to control register.
[1]: Read data from control register.
Bit [5:0]: Address of control register
FI
D
Data Byte:
Bit [7:0]: SPI input or output data, see Figure 10.2 and Figure 10.3 for details.
N
10.2 SPI Timing Characteristic
A
M
IC
C
O
M
C
O
No matter 3-wire or 4-wire SPI bus is configured, the maximum SPI data rate is 10 Mbps. To active SPI bus, SCS pin must
be set to low. For correct data latching, user has to take care hold time and setup time between SCK and SDIO. See Table
10.2 for details.
Parameter
FC
TSE
THE
TSW
THW
TDR
Description
FIFO clock frequency.
Enable setup time.
Enable hold time.
TX Data setup time.
TX Data hold time.
RX Data delay time.
Min.
50
50
50
50
0
Max.
10
50
Unit
MHz
ns
ns
ns
ns
ns
Table 10.2 SPI Timing Characteristic
10.3 SPI Timing Chart
In this section, 3-wire and 4-wire SPI bus read / write timing are described.
10.3.1 Timing Chart of 3-wire SPI
Jul., 2011, v1.3
34
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
SCS
SCK
SDIO
A7
A6
A5
A4
A3
A2
A1
A0
DW7
RF IC will latch address bit at
rising edge of SCK
DW6
DW5
DW1
DW0
RF IC will latch data bit at
the rising edge of SCK
L
3-Wire serial interface - Write operation
TI
A
SCS
SCK
A7
A6
A5
A4
A3
A2
A1
A0
DR7
DR5
DR1
DR0
DW1
DW0
MCU can latch data at rising
edge of SCK
RF IC will change the data
when falling edge of SCK
RF IC will latch address bit at
rising edge of SCK
DR6
EN
SDIO
FI
D
3-Wire serial interface - Read operation
Figure 10.2 Read/Write Timing Chart of 3-Wire SPI
SCK
SDIO
A6
A5
A4
A3
A2
A1
A0
DW7
M
A7
C
O
SCS
N
10.3.2 Timing Chart of 4-wire SPI
RF IC will latch data bit at rising
edge of SCK
4-Wire serial interface - Write operation
A
M
IC
SCS
SCK
DW5
C
O
RF IC will latch address bit at
rising edge of SCK
DW6
SDI
A7
A6
A5
A4
A3
A2
A1
x
GIOx
RF IC will latch address bit at
rising edge of SCK
x
A0
DR7
RF IC will change the data
when falling edge of SCK
DR6
DR5
DR2
DR1
DR0
MCU can latch data at the
rising edge of SCK
4-Wire serial interface - Read operation
Figure 10.3 Read/Write Timing Chart of 4-Wire SPI
10.4 Strobe Commands
A7125 supports 8 Strobe commands to control internal state machine for chip’s operations. Table 10.3 is the summary of
Strobe commands.
Jul., 2011, v1.3
35
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
Be notice, Strobe command could be defined by 4-bits (A7~A4) or 8-bits (A7~A0). If 8-bits Strobe command is selected,
A3 ~ A0 are don’t care conditions. In such case, SCS pin can be remaining low for asserting next commands.
A6
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
A3
x
x
x
x
x
x
x
x
A2
x
x
x
x
x
x
x
x
A1
x
x
x
x
x
x
x
x
A0
x
x
x
x
x
x
x
x
Description
Sleep mode
Idle mode
Standby mode
PLL mode
RX mode
TX mode
FIFO write pointer reset
FIFO read pointer reset
EN
Table 10.3 Strobe Commands by SPI bus
L
A7
1
1
1
1
1
1
1
1
TI
A
Strobe Command
Strobe Command
10.4.1 Strobe Command - Sleep Mode
A6
0
A5
0
A4
0
A3
0
A2
0
A1
0
Description
A0
0 Sleep mode
Figure 10.4 Sleep mode Command Timing Chart
IC
C
O
M
C
O
A7
1
N
Strobe Command
Strobe Command
FI
D
Refer to Table 10.3, user can issue 4 bits (1000) Strobe command directly to set A7125 into Sleep mode. Below are the
Strobe command table and timing chart.
A
M
10.4.2 Strobe Command - ldle Mode
Refer to Table 10.3, user can issue 4 bits (1001) Strobe command directly to set A7125 into Idle mode. Below are the
Strobe command table and timing chart.
Strobe Command
Strobe Command
A7
A6
A5
A4
A3
A2
A1
A0
1
0
0
1
x
x
x
x
Jul., 2011, v1.3
Description
Idle mode
36
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
SCS
SCS
SCK
SCK
A7
SDIO
A6
A5
A4
SDIO
A7
A6
Idle mode
A5
A3
A4
A2
A1
A0
Idle mode
TI
A
L
Figure 10.5 Idle mode Command Timing Chart
10.4.3 Strobe Command - Standby Mode
Strobe Command
Strobe Command
A6
0
A5
1
A4
0
A3
x
A2
x
A1
x
Description
A0
x Standby mode
C
O
N
FI
D
A7
1
EN
Refer to Table 10.3, user can issue 4 bits (1010) Strobe command directly to set A7125 into Standby mode. Below are the
Strobe command table and timing chart.
M
Figure 10.6 Standby mode Command Timing Chart
O
10.4.4 Strobe Command - PLL Mode
C
Refer to Table 10.3, user can issue 4 bits (1011) Strobe command directly to set A7125 into PLL mode. Below are the
Strobe command table and timing chart.
A6
0
A5
1
A
M
A7
1
IC
Strobe Command
Strobe Command
A4
1
A3
x
A2
x
A1
x
Description
A0
x PLL mode
Figure 10.7 PLL mode Command Timing Chart
Jul., 2011, v1.3
37
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
10.4.5 Strobe Command - RX Mode
Refer to Table 10.3, user can issue 4 bits (1100) Strobe command directly to set A7125 into RX mode. Below are the
Strobe command table and timing chart.
Strobe Command
Strobe Command
A6
1
A5
0
A4
0
A3
x
A2
x
A1
x
Description
A0
x RX mode
EN
TI
A
L
A7
1
FI
D
Figure 10.8 RX mode Command Timing Chart
N
10.4.6 Strobe Command - TX Mode
Strobe Command
Strobe Command
A6
A5
A4
A3
A2
1
1
0
1
x
x
A1
A0
x
x
Description
TX mode
A
M
IC
C
O
M
A7
C
O
Refer to Table 10.3, user can issue 4 bits (1101) Strobe command directly to set A7125 into TX mode. Below are the
Strobe command table and timing chart.
Figure 10.9 TX mode Command Timing Chart
10.4.7 Strobe Command – FIFO Write Pointer Reset
Refer to Table 10.3, user can issue 4 bits (1110) Strobe command directly to reset A7125 FIFO write pointer. Below are the
Strobe command table and timing chart.
Strobe Command
Strobe Command
A7
A6
A5
A4
A3
A2
A1
A0
1
1
1
0
x
x
x
x
Jul., 2011, v1.3
Description
FIFO write pointer reset
38
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
TI
A
L
Figure 10.10 FIFO write pointer reset Command Timing Chart
10.4.8 Strobe Command – FIFO Read Pointer Reset
Strobe Command
Strobe Command
A6
A5
A4
A3
A2
A1
A0
1
1
1
1
x
x
x
x
Description
FIFO read pointer reset
C
O
N
FI
D
A7
EN
Refer to Table 10.3, user can issue 4 bits (1111) Strobe command directly to reset A7125 FIFO read pointer. Below are the
Strobe command table and timing chart.
O
10.5 Reset Command
M
Figure 10.11 FIFO read pointer reset Command Timing Chart
A
M
SCS
IC
C
In addition to power on reset (POR), MCU could issue software reset to A7125 by setting Mode Register (00h) through SPI
bus as shown below. As long as 8-bits address (A7~A0) are delivered zero and data (D7~D0) are delivered zero, A7125 is
informed to generate internal signal “RESETN” to initial itself. After reset command, A7125 is in standby mode.
SCK
SDIO
A7
A6
A5
A4
A3
A2
A1
A0
DW 7
DW 6
DW5
DW1
DW 0
RESETN
Reset RF chip
Figure 10.12 Reset Command Timing Chart
10.6 ID Accessing Command
A7125 has built-in 32-bits ID Registers for customized identification code. It is accessed via SPI bus. ID length is
recommended to be 32 bits by setting IDL (20h).
Figure 10.13 and 10.14 are timing charts of 32-bits ID accessing via 3-wire SPI.
Jul., 2011, v1.3
39
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
10.6.1 ID Write Command
User can refer to Figure 10.2 for SPI write timing chart. Below is the procedure of ID write command.
EN
TI
A
L
Step1: Deliver A7~A0 = 00000110 (A7=0 for control register, A6=0 for write operation, ID addr = 06h).
Step2: Via SDIO pin, 32-bits ID are written in sequence by Data Byte 0, 1, 2 and 3.
Step3: Toggle SCS pin to high when step2 is completed.
Figure 10.13 ID Write Command Timing Chart
FI
D
10.6.2 ID Read Command
User can refer to Figure 10.2 for SPI read timing chart in details. Below is the procedure of ID read command.
Figure 10.14 ID Read Command Timing Chart
IC
C
O
M
C
O
N
Step1: Deliver A7~A0 = 01000110 (A7=0 for control register, A6=1 for read operation, ID addr = 06h).
Step2: Via SDIO pin, 32-bits ID are read in sequence by Data Byte 0, 1, 2 and 3.
Step3: Toggle SCS pin to high when step2 is completed.
10.7 FIFO Accessing Command
A
M
A7125 has separated TX / RX FIFO, user just needs to set FMS (01h) =1 to enable FIFO mode. In FIFO mode, before
packet is delivered, write wanted data into TX FIFO and issue TX strobe command. Similarly, user can read RX FIFO once
packet is received.
User can choose polling or interrupt scheme for FIFO accessing. FIFO status is output via GIO1 (or GIO2) pin by setting
GIO1 (0Bh) or GIO2 (0Ch).
See Figure 10.15 and 10.16 for timing charts of FIFO accessing via 3-wire SPI.
10.7.1 TX FIFO Write Command
User can refer to Figure 10.2 for SPI write timing chart. Below is the procedure of TX FIFO write command.
Step1:
Step2:
Step3:
Step4:
Jul., 2011, v1.3
Deliver A7~A0 = 00000101 (A7=0 for control register, A6=0 for write operation, FIFO addr = 05h).
Via SDIO pin, write (n+1) bytes TX data into TX FIFO in sequence by Data Byte 0, 1, 2 to n.
Toggle SCS pin to high when step2 is completed.
Send TX Strobe command for packet transmitting. Refer to Figure 10.9.
40
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
L
Figure 10.15 TX FIFO Write Command Timing Chart
TI
A
10.7.2 Rx FIFO Read Command
User can refer to Figure 10.2 for SPI read timing chart. Below is the procedure of RX FIFO read command.
N
FI
D
EN
Step1: Deliver A7~A0 = 01000101 (A7=0 for control register, A6=1 for read operation, FIFO addr = 05h).
Step2: Via SDIO pin, RX FIFO is read in sequence by Data Byte 0, 1, 2 to n.
Step3: Toggle SCS pin to high when RX FIFO is read completely.
A
M
IC
C
O
M
C
O
Figure 10.16 RX FIFO Read Command Timing Chart
Jul., 2011, v1.3
41
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
11. State machine
In chapter 9 and chapter 10, user can learn both accessing A7125’s control registers as well as issuing Strobe commands.
From section 10.2 ~ 10.6, it is clear to know configurations of 3-wire SPI and 4-wire SPI, Strobe command, software reset,
and how to access ID Registers and TX/RX FIFO.
In section 11.1, built-in state machine is introduced. Then, combined with Strobe command, software reset and A7125’s
control registers, section 11.2 , 11.3 and 11.4 demonstrate 3 state diagrams to explain how transitions of A7125’s
operation.
TI
A
L
From accessing data point of view, if FMS=1 (01h), FIFO mode is enabled, otherwise, A7125 is in direct mode. If FMS=1
and FIFO Read/Write at standby mode, we call it is Normal FIFO mode. Otherwise, If FMS=1 and FIFO Read/Write at PLL
mode, we called it is Quick FIFO mode due to the reduction of PLL settling time. If FMS=1 and FIFO Read/Write at IDLE
mode, we called it is Power Saving FIFO mode due to the reduction of average current.
Data In
Data Out
Operation Mode
Clock Recovery
for Direct Mode
3-Wire SPI
SCS pin = 0
SDIO pin
SDIO pin
4-Wire SPI
SCS pin = 0
SDIO pin
GIO1 (GIO1S=0110) /
GIO2 (GIO2S=0110)
FIFO (FMS=1)
Direct(FMS=0)
FIFO (FMS=1)
Direct(FMS=0)
CKO pin
(CKOS = 0001)
CKO pin
(CKOS = 0001)
(FMS=1 and FIFO R/W @ Standby mode)
(FMS=1 and FIFO R/W @ PLL mode)
(FMS=1 and FIFO R/W @ IDLE mode)
(FMS=0 and FIFO ignored, write packet @ TX mode, read packet @ RX mode)
FI
D
Normal FIFO Mode
Quick FIFO Mode
Power Saving FIFO Mode
Quick Direct Mode
11.1 Key states
M
C
O
A7125 supports 7 key operation states. Those are,
(1) Standby mode
(2) Sleep mode
(3) Idle mode
(4) PLL mode
(5) TX mode
(6) RX mode
(7) CAL mode
N
(1)
(2)
(3)
(4)
EN
SPI chip select
IC
C
O
After power on reset or software reset, A7125 is automatically into standby mode. Then, user has to do calibration process
because all control registers are in initial values. The calibration process of A7125 is very easy, user only needs to issue
Strobe commands and enable calibration registers. If so, the calibrations are automatically completed by A7125’s internal
state machine. See 11.2, 11.3, 11.4 and chapter 15 for details. After calibration, A7125 is ready to do TX and RX operation.
User can start wireless transmission.
A
M
11.1.1 Standby mode
When Standby Strobe is issued, A7125 enters standby mode automatically. Internal power management is listed below. Be
noted that A7125 is in standby mode after power on reset or software reset.
Standby mode
On Chip
Regulator
Crystal
Oscillator
VCO
PLL
RX
Circuitry
TX
Circuitry
ON
ON
OFF
OFF
OFF
OFF
Jul., 2011, v1.3
42
Strobe Command
(1010xxxx)b
See Figure 10.6
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
11.1.2 Sleep mode
When Sleep Strobe is issued, A7125 enters sleep mode automatically. In sleep mode, A7125 still can accept other strobe
commands via SPI bus. But, A7125 can not support Read/Write FIFO in sleep mode. Internal power management is listed
below.
Sleep mode
VCO
PLL
RX
Circuitry
TX
Circuitry
OFF
OFF
OFF
OFF
OFF
OFF
Strobe Command
(1000xxxx)b
See Figure 10.4
L
Crystal
Oscillator
TI
A
On Chip
Regulator
11.1.3 ldle mode
ldle mode
Crystal
Oscillator
VCO
PLL
RX
Circuitry
ON
OFF
OFF
OFF
OFF
TX
Circuitry
OFF
FI
D
On Chip
Regulator
EN
When Idle Strobe is issued, A7125 enters idle mode automatically. In idle mode, A7125 can accept other strobe commands
as well as supporting Read/Write FIFO. Internal power management is listed below.
(1001xxxx)b
See Figure 10.5
N
11.1.4 PLL mode
Strobe Command
C
O
When PLL Strobe is issued, A7125 enters PLL mode automatically. In PLL mode, internal PLL and VCO are both turned on
to generate LO (local oscillator) frequency before TX and RX operation. Internal power management is listed below.
According to PLL Register I, II, III, IV and V, PLL circuitry is easy to control by user’s definition.
PLL mode
Crystal
Oscillator
ON
ON
VCO
M
On Chip
Regulator
RX
Circuitry
TX
Circuitry
ON
OFF
OFF
Strobe Command
(1011xxxx)b
See Figure 10.7
O
ON
PLL
C
11.1.5 TX mode
IC
When TX Strobe is issued, A7125 enters TX mode automatically for data delivery. Internal power management is listed
below.
A
M
Be notice,
(1) If A7125 is in FIFO mode, TX data packet (Preamble + ID + Payload) is delivered through TX circuitry. Then, A7125
supports auto-back function to previous state for the next packet.
(2) If A7125 is in direct mode, TX data packet is also delivered through TX circuitry. Then, A7125 stays in TX mode. User
has to issue Strobe command to back to previous state.
TX mode
On Chip
Regulator
Crystal
Oscillator
VCO
PLL
RX
Circuitry
TX
Circuitry
ON
ON
ON
ON
OFF
ON
Strobe Command
(1101xxxx)b
See Figure 10.9
11.1.6 RX mode
When RX Strobe is issued, A7125 enters RX mode automatically for data receiving. Internal power management is listed
below.
Be notice,
Jul., 2011, v1.3
43
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
(1) If A7125 is in FIFO mode, RX data packet is caught through RX circuitry. Then, A7125 supports auto-back function to
previous state for next receiving packet.
(2) If A7125 is in direct mode, RX data packet is also caught through RX circuitry. Then, A7125 stays in RX mode. User has
to issue Strobe command to back to previous state.
RX mode
VCO
PLL
RX
Circuitry
TX
Circuitry
ON
ON
ON
ON
ON
OFF
Strobe Command
(1101xxxx)b
See Figure 10.9
L
Crystal
Oscillator
TI
A
On Chip
Regulator
11.1.7 CAL mode
EN
Calibration process shall be done after power on reset or software reset. Calibration items include VCO, IF Filter and RSSI.
It is easy to implement calibration process by Strobe command and enable CALC (02h) control register. See chapter 15 for
details.
A
M
IC
C
O
M
C
O
N
FI
D
Be noted that VCO Calibration is executed in PLL mode only. However, IF Filter and RSSI Calibration can be executed in
Standby or PLL mode.
Jul., 2011, v1.3
44
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
11.2 Normal FIFO Mode
This mode is suitable for requirement of general purpose applications. After calibration, user can issue Strobe command to
enter standby mode where write TX FIFO or read RX FIFO. From standby mode to packet data transceiving, only one
Strobe command is needed. Once transmission is done, A7125 is auto back to standby mode.
CAL CMD
CMD Value
Calibration
Section
AK
CALC.0=1,
RSSI
15.3
CALC.1=1,
IF Filter
15.2
CALC.2=1,
VCO Deviation
15.6
CALC.3=1,
VCO Bank
15.5
CALC.4=1,
VCO Current
15.4
Strobe
CMD Value
Note
Section
ST1
1011b
Enter to PLL
10.4.4
ST2
1010b
Enter to Standby
10.4.3
ST3
1000b
Enter to SLEEP
10.4.1
ST4
1001b
Enter to IDLE
10.4.2
ST5-TX
1101b
Enter to TX
10.4.6
ST5-RX
1100b
Enter to RX
10.4.5
RST-CMD
00000000b
Software Reset
10.5
A
M
IC
C
O
M
C
O
N
FI
D
EN
TI
A
L
If all packets are finished and deeper power saving is necessary, user can issue Strobe command to ask A7125 staying in
sleep mode. Figure 11.1 is the state diagram of Normal FIFO mode.
l
Be notice, refer to chapter 16 for definition of RX FIFO Full and TX FIFO Empty.
Figure 11.1 State diagram of Normal FIFO Mode
From Figure 11.1, when ST5 command is issued for TX operation, see Figure 11.2 for detailed timing. A7125 status can be
represented to GIO1 or GIO2 pin to MCU for timing control.
Jul., 2011, v1.3
45
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
Strobe CMD
(SCS,SCK,SDIO)
Next Instruction
ST5
90 us (auto delay)
Pin
Preamble + ID Code + Payload
GIO1 Pin - WTR
(GIO1S[3:0]=0000)
Transmitting Time
T0
Changed
No Changed
WPLL to TX
(TDL)
60 us
60 us
TX Ready Time
EN
Standby to WPLL
(PDL)
30 us
30 us
TI
A
T0-T1: Auto Delay by Register setting (PDL + TDL)
LO Freq.
Auto Back
Standby Mode
T2
T1
L
RFO
90 us
90 us
FI
D
Figure 11.2 Transmitting Timing Chart of Normal FIFO Mode
From Figure 11.1, when ST5 command is issued for RX operation, see Figure 11.3 for detailed timing. A7125 status can be
represented to GIO1 or GIO2 pin to MCU for timing control.
Strobe CMD
(SCS,SCK,SDIO)
ST5
90 us
Pin
Preamble + ID Code + Payload
C
O
RFI
Next Instruction
N
Wait
Packet
GIO1 Pin - WTR
(GIO1S[3:0]=0000)
T1
M
T0
Receiving Time
T3
T2
Auto Back
Standby Mode
O
T0-T1: RX Settling.
T1-T2: RX is ready, Wait for valid packet
Standby to WPLL
WPLL to RX
RX Ready Time
Changed
No Changed
30 us
30 us
60 us
60 us
90 us
90 us
A
M
IC
C
LO Freq.
Jul., 2011, v1.3
Figure 11.3 Receiving Timing Chart of Normal FIFO Mode
46
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
11.3 Quick FIFO Mode
This mode is suitable for requirement of fast transceiving. After calibration flow, user can issue Strobe command to enter
PLL mode where write TX FIFO or read RX FIFO. From PLL mode to packet data transceiving, only one Strobe command is
needed. Once transmission is done, A7125 is auto back to PLL mode.
CAL CMD
CMD Value
Calibration
Section
AK
CALC.0=1,
RSSI
15.3
CALC.1=1,
IF Filter
15.2
CALC.2=1,
VCO Deviation
15.6
CALC.3=1,
VCO Bank
15.5
CALC.4=1,
VCO Current
15.4
Strobe
CMD Value
Note
Section
ST 1
1011b
Enter to PLL
10.4.4
ST 2
1010b
Enter to Standby
10.4.3
ST 3
1000b
Enter to SLEEP
10.4.1
ST 4
1001b
Enter to ID LE
10.4.2
ST 5-TX
1101b
Enter to TX
10.4.6
ST 5-R X
1100b
Enter to R X
10.4.5
RST-CMD
00000000b
Software Reset
10.5
A
M
IC
C
O
M
C
O
N
FI
D
EN
TI
A
L
When packets are finished and deeper power saving is necessary, user can issue Strobe command to ask A7125 staying in
sleep mode. Figure 11.4 is the state diagram of Quick FIFO mode.
l
l
Be notice, refer to chapter 16 for definition of RX FIFO Full and TX FIFO Empty.
Be notice, ST5 delay time is either 70 us (LO frequency changed) or 10 us (LO frequency NOT changed)
Figure 11.4 State diagram of Quick FIFO Mode
From Figure 11.4, when ST5 command is issued for TX operation, see Figure 11.5 for detailed timing. A7125 status can be
represented to GIO1 or GIO2 pin to MCU for timing control.
Jul., 2011, v1.3
47
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
Strobe CMD
(SCS,SCK,SDIO)
Next Instruction
ST5
90 us / 70 us (auto delay)
RF In/Out Pin
Preamble + ID Code + Payload
GIO1 Pin - WTR
(GIO1S[3:0]=0000)
Transmitting Time
Changed
No Changed
WPLL to TX
(TDL)
60 us
60 us
TX Ready Time
EN
PLL to WPLL
(PDL)
30 us
10 us
TI
A
T0-T1: Auto Delay by Register setting(PDL+TDL)
LO Freq.
Auto Back
PLL Mode
T2
T1
L
T0
90 us
70 us
FI
D
Figure 11.5 Transmitting Timing Chart of Quick FIFO Mode
From Figure 11.4, when ST5 command is issued for RX operation, see Figure 11.6 for detailed timing. A7125 status can be
represented to GIO1 or GIO2 pin to MCU for timing control.
Strobe CMD
(SCS,SCK,SDIO)
Wait
Packet
C
O
90 us / 70 us
RF In/Out Pin
M
GIO1 Pin - WTR
(GIO1S[3:0]=0000)
T1
Preamble + ID Code + Payload
Receiving Time
T3
T2
Auto Back
PLL Mode
O
T0
Next Instruction
N
ST5
C
T0-T1: RX Settling by register setting (PDL+TDL).
T1-T2: RX is ready, Wait for valid packet
IC
LO Freq.
A
M
Changed
No Changed
Standby to WPLL
(PDL)
30 us
10 us
WPLL to RX
(TDL)
60 us
60 us
RX Ready Time
90 us
70 us
Figure 11.6 Receiving Timing Chart of Quick FIFO Mode
11.4 Power Saving FIFO Mode
This mode is suitable for requirement of low power consumption. After calibration flow, user can issue Strobe command to
enter idle mode where write TX FIFO or read RX FIFO. From idle mode to packet data transceiving, only one Strobe
command is needed. Once transmission is done, A7125 is auto back to idle mode.
When packets are finished and deeper power saving is necessary, user can issue Strobe command to ask A7125 staying in
sleep mode. Figure 11.7 is the state diagram of Power Saving FIFO mode.
Jul., 2011, v1.3
48
AMICCOM Electronics Corporation
A7125
N
FI
D
EN
TI
A
L
2.4GHz FSK Transceiver
CMD Value
Calibration
Section
AK
CALC.0=1,
RSSI
15.3
CALC.1=1,
IF Filter
15.2
CALC.2=1,
VCO Deviation
15.6
CALC.3=1,
VCO Bank
15.5
CALC.4=1,
VCO Current
15.4
Strobe
CMD Value
Note
Section
ST 1
1011b
Enter to PLL
10.4.4
ST 2
1010b
Enter to Standby
10.4.3
ST 3
1000b
Enter to SLEEP
10.4.1
ST 4
1001b
Enter to IDLE
10.4.2
ST 5-TX
1101b
Enter to TX
10.4.6
ST 5-RX
1100b
Enter to RX
10.4.5
RST-CMD
00000000b
Software Reset
10.5
Be notice, refer to chapter 16 for definition of RX FIFO Full and TX FIFO Empty.
A
M
l
IC
C
O
M
C
O
CAL CMD
Figure 11.7 State diagram of Power Saving FIFO Mode
From Figure 11.7, when ST5 command is issued for TX operation, see Figure 11.8 for detailed timing. A7125 status can be
represented to GIO1 or GIO2 pin to MCU for timing control.
Jul., 2011, v1.3
49
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
Strobe CMD
(SCS,SCK,SDIO)
Next Instruction
ST5
990 us (auto delay)
RF In/Out Pin
Preamble + ID Code + Payload
Crystal Ready
(900 us)
GIO1 Pin - WTR
(GIO1S[3:0]=0000)
Transmitting Time
Changed
No Changed
PLL to WPLL
(PDL)
30 us
30 us
WPLL to TX
(TDL)
60 us
60 us
EN
IDLE to PLL
(WSEL, Crystal Ready)
300+600 us
300+600 us
TI
A
T0-T1: Auto Delay by Register setting (WSEL+PDL+TDL)
LO Freq.
Auto Back
IDLE Mode
T2
T1
L
T0
TX Ready Time
990 us
990 us
FI
D
Figure 11.8 Transmitting Timing Chart of Power Saving FIFO Mode
From Figure 11.7, when ST5 command is issued for RX operation, see Figure 11.9 for detailed timing. A7125 status can be
represented to GIO1 or GIO2 pin to MCU for timing control.
Strobe CMD
(SCS,SCK,SDIO)
Wait
Packet
C
O
990 us
RF In/Out Pin
Next Instruction
N
ST5
Preamble + ID Code + Payload
Crystal ready
(900 us)
M
GIO1 Pin - WTR
(GIO1S[3:0]=0000)
T1
T3
T2
Auto Back
IDLE Mode
O
T0
Receiving Time
C
T0-T1: Crystal Ready + RX settling by register setting (WSEL+PDL+TDL)
T1-T2: RX is ready, Wait for valid packet
IC
LO Freq.
A
M
Changed
No Changed
Jul., 2011, v1.3
IDLE to PLL
(WSEL)
300+600 us
300+600 us
WPLL to RX
(TDL)
30 us
30 us
WPLL to RX
(TDL)
60 us
60 us
RX Ready Time
990 us
990 us
Figure 11.9 Receiving Timing Chart of Power Saving FIFO Mode
50
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
11.5 Quick Direct Mode
This mode is suitable for fast transceiving. After calibration flow, for every state transition, user has to issue Strobe command
to A7125.This mode is also suitable for the requirement of versatile packet format. Noted that user needs to take care the
transition time by MCU’s timer.
CAL CMD
CMD Value
Calibration
Section
AK
CALC.0=1,
RSSI
15.3
CALC.1=1,
IF Filter
15.2
CALC.2=1,
VCO Deviation
15.6
CALC.3=1,
VCO Bank
15.5
CALC.4=1,
VCO Current
15.4
Strobe
CMD Value
Note
Section
ST 1
1011b
Enter to PLL
10.4.4
ST 2
1010b
Enter to Standby
10.4.3
ST 3
1000b
Enter to SLEEP
10.4.1
ST 4
1001b
Enter to ID LE
10.4.2
ST 5-TX
1101b
Enter to TX
10.4.6
ST 5-RX
1100b
Enter to RX
10.4.5
RST-CMD
00000000b
Software Reset
10.5
A
M
IC
C
O
M
C
O
N
FI
D
EN
TI
A
L
When packets are finished and deeper power saving is necessary, user can issue Strobe command to ask A7125 staying in
idle mode (or sleep mode). Figure 11.3 is the state diagram of Quick Direct mode.
l
l
Be notice, Dummy stands for dummy preamble.
Be notice, ST5 delay time is either 70 us (LO frequency changed) or 10 us (LO frequency NOT changed)
Figure 11.10 State diagram of Quick Direct Mode
Jul., 2011, v1.3
51
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
From Figure 11.10, when PLL mode transits to WPLL mode, LO (local oscillator) frequency changed or not will induce
different PLL setting time by either 70us or 10 us. Therefore, MCU total delay time is different. See Table 11.1 for details.
LO Freq.
Changed
No Changed
PLL to WPLL
30 us
10 us
WPLL to TX
50 us
50 us
TX Ready Time
80 us
60 us
Table 11.1 MCU total delay time from PLL to TX mode.
A7125
Data Rate
Dummy
Preamble
1 Mbps
2 Mbps
Packet
TI
A
L
From Figure 11.10, when A7125 enters TX mode, MCU should immediately deliver dummy preamble and defined packet to
A7125’s GIO1 or GIO2 pin. Dummy preamble is used to stabilize TX circuitry. See Table 11.2 for details.
Note
ID
Max Payload
10 bits
32 bits
32 bits
512 bytes
Total Preamble = 42 bits
20 bits
32 bits
32 bits
512 bytes
Total Preamble = 52 bits
EN
Preamble
FI
D
Table 11.2 Format of dummy preamble and packet.
Strobe CMD
(SCS,SCK,SDIO)
C
O
N
From Figure 11.10, Table 11.1 and 11.2, MCU total delay time and dummy preamble are important for quick direct mode.
When ST5 command is issued for TX operation, see Figure 11.4 for detailed timing. A7125 status can be represented to
GIO1 and GIO2 pin to MCU for timing control.
ST5
10 us
80 us / 60 us
Transmitting Output
C
GIO2 Pin - TMEO
(GPIO2S[3:0]=0010)
Dummy
Preamble
O
GIO2 Pin - WTR
(GPIO2S[3:0]=0000)
Dummy Preamble + Preamble + ID + Payload
M
GIO1 Pin - TRXD
(GPIO1S[3:0]=0111)
ST1
A
M
IC
CKO Pin - DCK
(CKOS[3:0]=0000)
T0
T1
T2
T3
T0-T1: MCU Total Delay Time, Refer to Table 11.1
T1-T2: Dummy Preamble, Refer to Table 11.2
T2:
TMEO (TX Modulation Enable) is auto triggered
T2-T3: Transmitting Time
Figure 11.11 Transmitting Timing Chart of Quick Direct Mode
From Figure 11.3, Table 11.1 and 11.2, RX settling time is important for quick direct mode. When ST5 command is issued for
RX operation, after RX settling and preamble detect, A7125 offers ID sync function (if 32 bits ID is stored in ID Register) to
generate FSYNC signal to inform MCU. Figure 11.5 is the detailed timing. A7125 status can be represented to GIO1 and
GIO2 pin to MCU for timing control.
Jul., 2011, v1.3
52
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
Strobe CMD
(SCS,SCK,SDIO)
ST1
ST5
Wait
Packet
90 us / 70 us
GIO1 Pin - TRXD
(GPIO1S[3:0]=0111)
Preamble + ID + Payload
GIO2 Pin - PMDO
(GPIO2S[3:0]=0011)
Payload Output
TI
A
ID Sync.
GIO2 Pin - FSYNC
(GPIO2S[3:0]=0001)
CKO Pin - RCK
(CKOS[3:0]=0001)
T1
T3
T2
EN
T0
T4
T0-T1: RX Ready Time
T1-T2: RX is ready, wait for valid packet
T2-T3: Preamble Detect
30 us
10 us
FI
D
Changed
No Changed
T5
T3-T4: ID Sync
T4-T5: Payload Output
WPLL to RX
RX Ready Time
60 us
60 us
90 us
70 us
N
PLL to WPLL
C
O
LO Freq.
L
Preamble
Detect
A
M
IC
C
O
M
Figure 11.12 Receiving Timing Chart of Quick Direct Mode
Jul., 2011, v1.3
53
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
12 Crystal Oscillator Circuit
A7125 needs external crystal or external clock that is either 6 or 8/12/16 MHz, to generate internal wanted clock.
Be notice if 6MHz external crystal (clock) is selected, A7125 only supports 1Mbps data rate.
Relative Control Register
Data Rate Clock Register (Address: 0Dh)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
W
SDR1
SDR1
0
SDR0
SDR0
0
GRC3
GRC3
0
GRC2
GRC2
1
GRC1
GRC1
1
GRC0
GRC0
1
-CGS
1
-XS
1
TI
A
Reset
L
Bit
12.1 Use External Crystal
C
O
N
FI
D
EN
To use external crystal, user just sets XS= 1 (0Dh) to enable crystal oscillator. Figure 12.1 shows the connection of crystal
network between XI and XO pins. C1 and C2 capacitance are used to adjust different crystal loading. A7125 support low
cost crystal within ± 50ppmaccuracy. Be noted that crystal accuracy requirement includes initial tolerance, temperature drift,
aging and crystal loading.
i.e., Crystal = 16MHz (Cload =20pF), C1=C2=33pF.
12.2 Use External Clock
M
Figure12.1 Crystal network connection for using external crystal
O
A7125 has built-in AC couple capacitor to support external clock input. Figure 11.2 shows how to connect. In such case, XI
pin is left opened.
A
M
IC
C
To use external clock from MCU instead of external crystal, user just sets XS= 0 (0Dh) to active AC couple capacitor. Be
notice, the frequency accuracy of external clock shall be controlled within ± 50ppm and the clock swing (peak-to-peak) shall
be larger than 1.5V.
(External clock is controlled within ± 50ppm and > 1.5Vpp.)
Figure 12.2 Connect to external clock source
Jul., 2011, v1.3
54
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
13. System Clock
System clock (64MHz) is generated from crystal oscillator for internal digital circuitry. User can set “Data Rate Clock
Register” (0Dh) to adapt different wanted crystal frequency (6/8/12/16MHz). Based on this, two important internal clocks
FCGR and FSYCK are generated.
(1) FCGR: Clock Generation Reference = 2MHz (Ref. clock of internal 64MHz PLL)
(2) FSYCK: System Clock = 64 MHz
(Main clock for internal digital circuit)
Data Rate Clock Register (Address: 0Dh)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Name
R
W
SDR1
SDR1
0
SDR0
SDR0
0
GRC3
GRC3
0
GRC2
GRC2
1
GRC1
GRC1
1
Reset
PLL Register II (Address: 0Fh)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Name
R
W
DBL
DBL
0
RRC1
RRC1
0
RRC0
RRC0
1
CHR3
CHR3
0
Reset
Bit 1
Bit 0
-CGS
1
-XS
1
Bit 3
Bit 2
Bit 1
Bit 0
CHR2
CHR2
1
CHR1
CHR1
1
CHR0
CHR0
1
IP8
BIP8
0
N
13.1 Derive System Clock
GRC0
GRC0
1
FI
D
Bit
Bit 2
TI
A
R/W
EN
Bit
L
Relative Control Register
FCGR =
C
O
Because A7125 supports different external crystals, GRC [3:0] (0Dh) are used to get 2 MHz Clock Generation Reference
(FCGR) for internal usage.
FXREF
.
(GRC[3 : 0] + 1)
IC
C
O
M
Below is block diagram of system clock. FXTAL is the crystal frequency. User can set registers to get FSYCK = 64MHz. FXREF is
the reference clock of Clock Generator to generate F CGR = 2MHz and FSPLL = 64MHz. After delay circuitry, System clock is
derived, FSYCK = 64MHz. ADC clock (FADC = 4MHz or 8MHz) is from FSYCK = 64MHz after frequency divider.
XS
A
M
XO
System clock
÷
PLL
(GRC+1)
CE
XI
CGS
CE
FXREF
CE
GRC
FSYCK= 64MHz
1
64MHz
DBL
X2
0
1
FCGR= 2MHz
Delay
0
FSPLL= 64MHz
Clock Generator
FXTAL
/2
/8
4MHz
8MHz
0
1
ADC clock
(FADC)
FSARS
Figure 13.1 System Clock Block Diagram
Recommend to set DBL (0Fh) = [0], then, FXREF = FXTAL
Crystal Frequency
(FXTAL)
16 MHz
Jul., 2011, v1.3
Internal Crystal
Reference
(FXREF)
16 MHz
Clock Generation
Reference
(FCGR)
Must be 2 MHz
55
GRC [3:0]
CGS
[0111]
1
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
12 MHz
12 MHz
Must be 2 MHz
[0101]
8 MHz
8 MHz
Must be 2 MHz
[0011]
6 MHz
6 MHz
Must be 2 MHz
[0010]
Be notice if 6MHz external crystal (clock) is selected, A7125 only supports 1Mbps data rate.
1
1
1
13.2 Data Rate
EN
TI
A
L
A7125 supports programmable data rate by setting SDR [1:0] (0Dh). Data rate = (FIFCK / (SDR [1:0] +1)). The data rate
clock is from IF clock (FIFCK) and FIFCK = FSYCK / 32 = 2 MHz
FSYCK
1
×
32 SDR[1 : 0] + 1
FSYCK
(system clock)
64 MHz
64 MHz
64 MHz
64 MHz
FIFCK
(IF clock)
2 MHz
2 MHz
2 MHz
2 MHz
N
A7125 Data Rate =
FI
D
Figure 13.2 Data Rate Block Diagram
Data Rate
2 Mbps
1 Mbps
Reserved
Reserved
A
M
IC
C
O
M
C
O
SDR [1:0]
(0Dh)
[00]
[01]
[10]
[11]
Jul., 2011, v1.3
56
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
14. Transceiver Frequency
A7125 is a half-duplex transceiver with embedded PA and LNA. For TX or RX frequency setting, user just needs to set up
LO (Local Oscillator) frequency for two-way radio transmission.
To target full range of 2.4GHz ISM band (2400 MHz to 2483.5 MHz), A7125 applies offset concept by LO frequency FLO =
FLO_BASE + FOFFSET. Therefore, A7125 is easy to implement frequency hopping and multi-channels by ONE register setting,
PLL Register I (CHN [7:0], 0Eh). In general, user can plan the wanted channels by a CHN Look-Up-Table to implement
hopping table for two-way radio between master and slave.
L
Below is the LO frequency block diagram.
F LO
X
(DBL+1)
/ (RRC[1:0]+1)
AC[14:0]/ 2 16
1
AFC
EN
Divider
0
F LO_BASE
+
+
F LO
FI
D
CHN / [4*(CHR+1)]
VCO
PFD
0
BIP[8:0] +
BFP[15:0]/ 2 16
TI
A
F PFD
F XTAL
F OFFSET
Relative Control Register
PLL Register I (Address: 0Eh)
R/W
Bit 7
Name
Reset
R/W
CHN7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CHN6
0
CHN5
0
CHN4
0
CHN3
0
CHN2
0
CHN1
0
CHN0
0
M
Bit
C
O
N
Figure 14.1 Block Diagram of Local Oscillator
O
PLL Register II (Address: 0Fh)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
W
DBL
DBL
0
RRC1
RRC1
0
RRC0
RRC0
1
CHR3
CHR3
0
CHR2
CHR2
1
CHR1
CHR1
1
CHR0
CHR0
1
IP8
BIP8
0
IC
Reset
C
Bit
PLL Register III (Address: 10h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
W
IP7
BIP7
1
IP6
BIP6
0
IP5
BIP5
0
IP4
BIP4
1
IP3
BIP3
0
IP2
BIP2
1
IP1
BIP1
1
IP0
BIP0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
A
M
Bit
Reset
PLL Register IV (Address: 11h)
Bit
R/W
Bit 7
Name
R
W
--/FP15
Reset
BFP15
0
AC14/FP14 AC13/FP13 AC12/P12 AC11/ FP11 AC10/FP10
Bit 1
Bit 0
AC9/FP9
AC8/FP8
BFP14
0
BFP13
0
BFP12
0
BFP11
0
BFP10
0
BFP9
0
BFP8
0
PLL Register V (Address: 12h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
W
AC7/FP7
AC6/FP6
AC5/FP5
AC4/FP4
AC3/FP3
AC2/FP2
AC1/FP1
AC0/FP0
BFP7
0
BFP6
0
BFP5
0
BFP4
0
BFP3
0
BFP2
1
BFP1
0
BFP0
0
Reset
Jul., 2011, v1.3
57
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
RX Register (Address: 19h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
---
RXSM1
1
RXSM0
0
FC
0
RXDI
0
DMG
0
RAW
1
ULS
0
14.1 LO Frequency Setting
Set the base frequency (FLO_BASE) by PLL Register II, III, IV and V (0Fh, 10h, 11h and 12h).
Recommend to set FLO_BASE ~ 2400.001MHz.
2.
Set the channel step (FCHSP) by PLL Register II (0Fh).
A7125 supports different channel steps by 2M / 1M / 500K / 250K. (500K is recommended.)
3.
Set CHN [7:0] to get offset frequency by PLL Register I (0Eh).
FOFFSET = CHN [7:0] * FCHSP
4.
LO frequency is equal to base frequency plus offset frequency.
FLO = FLO_BASE + FOFFSET
FI
D
EN
TI
A
1.
L
From Figure 14.1, FLO is not only for TX radio frequency but also to be RX LO frequency. To set up FLO, it is easy to
implement by below 8 steps.
FLO
C
O
N
FLO_BASE
FOFFSET
FXTAL
BFP[15 : 0]
BFP[15 : 0]
× ( BIP[8 : 0] +
) = ( DBL + 1) ×
)
16
RRC[1 : 0] + 1
2
216
M
FLO_BASE = FPFD × ( BIP[8 : 0] +
O
Base on the above formula, for example, if F XTAL = 16 MHz and step FCHSP = 500 KHz, To get FLO_BASE and FLO ,see Table
14.1, 14.2, 14.3 and Figure 14.2 for details.
A
M
IC
C
How to set FLO_BASE ~ 2400.001 MHz
STEP
ITEMS
1
FXTAL
2
DBL
3
RRC
4
BIP
5
BFP
6
FLO_BASE
VALUE
16 MHz
0
0
0x96
0x0004
~2400.001 MHz
NOTE
Crystal Frequency
Disable double function
If so, FPFD= 16MHz
To get FLO_BASE =2400 MHz
To get FLO_BASE ~ 2400.001 MHz
LO Base frequency
Table 14.1 How to set FLO_BASE
How to set FLO = FLO_BASE + FOFFSET ~ 2405.001 MHz
STEP
ITEMS
VALUE
NOTE
1
FLO_BASE
~2400.001 MHz
After set up BIP and BFP
2
CHR
7
To get FCHSP= 500 KHz
3
FCHSP
500 KHz
Channel step = 500KHz
4
CHN
0x0A
Set channel number = 10
5
FOFFSET
5 MHz
FOFFSET= 500 KHz * (CHN) = 5MHz
6
FLO
~2405.001 MHz
Get FLO= FLO_BASE + FOFFSET
Table 14.2 How to set FLO
Jul., 2011, v1.3
58
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
Figure 14.2 show FLO ~ 2405.001 MHz and its registers setting.
F PFD =16M
(DBL+1)
/ (RRC[1:0]+1)
DBL = 0
AC[14:0]/ 2 16
BIP[8:0] +
BFP[15:0]/ 2 16
PFD
RRC = 0
1
0
VCO
FL O=
2405.001M
AFC
0
Divider
F LO_BASE =2400.001M
(BIP = 0x96)
(BFP = 0x0004)
+
+
F LO =2405.001M
TI
A
X
CHN / [4*(CHR+1)]
(CH N=0x0A)
(CHR = 7)
L
F XT AL=16M
EN
F O FFSET = 5M
Figure 14.2 Block Diagram of FLO ~ 2405.001 MHz
( DBL + 1) × f XTAL
RRC[1 : 0] + 1
C
O
FPFD =
N
FI
D
For different crystal frequency, 16MHz / 12MHz / 8 MHz / 6MHz, below are calculation details for
(1) How to set FLO_BASE ~ 2400.001 MHz
(2) How to set FLO ~ 2405.005 MHz
C
O
M
Recommend DBL = 0
FXTAL (MHz)
DBL
PRC
FPFD (MHz)
16
0
0
16
12
0
0
12
8
0
0
8
6
0
0
6
Be notice if 6MHz external crystal (clock) is selected, A7125 only supports 1Mbps data rate.
A
M
IC
FLO _ BASE = FPFD × ( BIP[8 : 0] +
FPFD (MHz)
16
12
8
6
FCHSP =
BIP
(integer part)
0x096
0x0C8
0x12C
0x190
BFP[15 : 0]
)
216
BFP
(floating part)
0x0004
0x0005
0x0008
0x000A
FLO_BASE (MHz)
~2400.001
~2400.001
~2400.001
~2400.001
FPFD
4 × (CHR[3 : 0] + 1)
FLO = FLO _ BASE + (CHN [7 : 0] × FCHSP )
Jul., 2011, v1.3
59
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
FCHSP (KHz)
2000
1000
500
250
CHN [7:0]
0x00 ~ 0x2A
0x00 ~ 0x54
0x00 ~ 0xA8
0x00 ~ 0xFF
FOFFSET (MHz)
0 ~ 84
0 ~ 84
0 ~ 84
0 ~ 63.75
FLO (MHz)
2400 ~ 2484
2400 ~ 2484
2400 ~ 2484
Depends on FLO_BASE
FXTAL = 12 MHz, How to set FCHSP
FPFD (MHz)
CHR [3:0]
12
2
12
5
12
11
FCHSP (KHz)
1000
500
250
CHN [7:0]
0x00 ~ 0x54
0x00 ~ 0xA8
0x00 ~ 0xFF
FOFFSET (MHz)
0 ~ 84
0 ~ 84
0 ~ 63.75
FLO (MHz)
2400 ~ 2484
2400 ~ 2484
Depends on FLO_BASE
FXTAL = 8 MHz, How to set FCHSP
FPFD (MHz)
CHR [3:0]
8
0
8
1
8
3
8
7
FCHSP (KHz)
2000
1000
500
250
CHN [7:0]
0x00 ~ 0x2A
0x00 ~ 0x54
0x00 ~ 0xA8
0x00 ~ 0xFF
FOFFSET (MHz)
0 ~ 84
0 ~ 84
0 ~ 84
0 ~ 63.75
EN
TI
A
L
FXTAL = 16 MHz, How to set FCHSP
FPFD (MHz)
CHR [3:0]
16
1
16
3
16
7
16
15
FLO (MHz)
2400 ~ 2484
2400 ~ 2484
2400 ~ 2484
Depends on FLO_BASE
A
M
IC
C
O
M
C
O
N
FI
D
FXTAL = 6 MHz, How to set FCHSP
FPFD (MHz)
CHR [3:0]
FCHSP (KHz)
CHN [7:0]
FOFFSET (MHz)
FLO (MHz)
6
2
500
0x00 ~ 0xA8
0 ~ 84
2400 ~ 2484
6
5
250
0x00 ~ 0xFF
0 ~ 63.75
Depends on FLO_BASE
Be notice if 6MHz external crystal (clock) is selected and DBL=0, A7125 only supports 1Mbps data rate.
Jul., 2011, v1.3
60
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
14.2 IF Side Band Select
In two ways radio, both master and slave have two roles, TX and RX. In general, slave usually has to reply an ACK-packet
or status update. In such case, A7125 offers two methods to set up FLO while TRX exchanging.
(1) Auto IF exchange
(2) Fast exchange
Relative Control Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Name
R
W
DDPC
DDPC
0
ARSSI
ARSSI
0
AIF
AIF
0
CD
DFCD
0
WWSE
WWSE
0
FMT
FMT
0
Reset
R/W
Bit 7
Bit 6
Bit 5
Bit 4
W
---
RXSM1
1
RXSM0
0
FC
0
Bit 0
FMS
FMS
0
ADCM
ADCM
0
Bit 3
Bit 2
Bit 1
Bit 0
RXDI
0
DMG
0
RAW
1
ULS
0
FI
D
Bit
Name
Reset
EN
RX Register (Address: 19h)
Bit 1
TI
A
Bit
L
Mode Control Register (Address: 01h)
FRXLO Formula
FRXLO = FLO
FRXLO = FLO
FRXLO = FLO － 2MHz
FRXLO = FLO ＋ 2MHz
AIF Function
Disable
(AIF=0)
Enable
(AIF=1)
C
O
N
Register Setting
ULS=0
ULS=1
ULS=0
ULS=1
A
M
IC
C
O
M
Table 14.3 FRXLO Formula
Jul., 2011, v1.3
61
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
14.2.1 Auto IF Exchange
A7125 supports Auto IF offset function (AIF, 01h). If AIF is enabled, only one On-air frequency (Fcarrier) is occupied. In this
case, user has no need to change FRXLO while TRX exchanging because FRXLO is auto shifted FIF. See below Figures and
Table 14.4 for details.
AIF=1 and ULS=0, FRXLO is auto shifted lower than FTXLO for 2MHz (FIF).
FLO_BASE
L
FTXLO = FLO = FCarrier
FOFFSET =5MHz
TI
A
FRXLO
AIF=1 and ULS=0, FRXLO is auto shifted lower than FTXLO for 2MHz (FIF).
EN
FIF
2MHz
FLO_BASE
N
FRXLO
FOFFSET =5MHz
AIF
Master
TX
1
RX
1
TX
10
FCHSP
(KHz)
500
FTXLO
(KHz)
2405.001
0
0
10
500
-
1
0
10
500
2405.001
1
0
10
500
-
FRXLO
(MHz)
-
NOTE
2403.001 Up side band
FRXLO is auto shifted
2403.001 Up side band
FRXLO is auto shifted
Above setting is the same to Master and Slave.
A
M
IC
Role
Exchanging
Switching
Time
CHN[7:0]
C
RX
ULS
O
Slave
C
O
Role
FIF
2MHz
M
Item
FI
D
FTXLO = FLO = FCarrier
On air
frequency
Refer to Figure 11.4,
If A7125 delivers one packet and receives one packet,
FLO is changed from 2405.001 to 2403.001, longer switching time.
Total Switching time = TX ready time + RX ready time
=( 30 us + 60 us) + ( 30 us + 60 us)
= 180 us
Master FTXLO = 2405.001 MHz
Slave FTXLO = 2405.001 MHz
(ONE occupied frequency only.)
Table 14.4 AIF function while TRX exchanging
14.2.2 Fast Exchange
To reduce PLL settling time, user can disable AIF function. If AIF is disabled, two On-air frequency (FCarrier (master), FCarrier
are occupied. In this case, user has to control ULS =0 (Master side) and ULS = 1 (Slave side) for fast exchange in
two-way radio. See below Figures and Table 14.5 for details.
(slave))
Jul., 2011, v1.3
62
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
AIF=0 and ULS=0, Master is set Up side band.
FTXLO = FLO = FCarrier (Master)
FLO_BASE
L
FRXLO
TI
A
FOFFSET =5MHz
FIF
2M
AIF=0 and ULS=1, Slave is set Low side band.
EN
FTXLO= FLO = FCarrier (Slave)
FLO_BASE
FI
D
FRXLO
N
FOFFSET =7MHz
Role
AIF
ULS
CHN[7:0]
Master
TX
0
0
RX
0
TX
0
RX
0
0
10
500
-
1
14
500
2407.001
1
14
500
-
M
FRXLO
(MHz)
-
NOTE
2405.001 Up side band
2407.001 Low side band
O
ULS and CHN setting are different in Master and Slave site.
Refer to Figure 11.4,
If A7125 delivers one packet and receives one packet,
Master’s FLO is fixed at 2405.001MHz, shorter settling time.
IC
Role
Exchanging
Switching
Time
FTXLO
(KHz)
2405.001
C
Slave
10
FCHSP
(KHz)
500
C
O
Item
A
M
Total Settling time = TX ready time + RX ready time
= ( 10 us + 60 us) + ( 10 us + 60 us)
= 140 us
On air
frequency
Master FTXLO = 2405.001 MHz
Slave FTXLO = 2407.001 MHz
(TWO occupied on-air frequency.)
Table 14.5 Fast exchange function while TRX exchanging
14.3 Band Edge Frequency Setting
For 2.4GHz ISM band, it is free licensed from 2400 MHz to 2483.5 MHz. Due to regulation criteria, in general, most of
applications are avoided to use band edge of 2400MHz and 2483.5MHz. Therefore, in such cases, user can define specific
band edges and set different FLO_BASE. Combined with different channel step FCHSP, user can gain different on air channel
numbers. See table 14.1 for reference.
User Defined
User Defined
(Low Band Edge)
(High Band Edge)
Cover Range
(MHz)
FLO_BASE
(MHz)
FCHSP
(KHz)
On air
Channel
NOTE
(recommended)
Jul., 2011, v1.3
63
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
2400 MHz
2483.5 MHz
83.5 MHz
~2400.001
2405 MHz
2477.0 MHz
72.0 MHz
~2405.001
2405 MHz
2467.0 MHz
62.0 MHz
~2405.001
2410 MHz
2463.0 MHz
52.0 MHz
Numbers
42
2000
1000
500
2000
1000
500
2.0 MHz / on air
channel step
2.0 MHz / on air
channel step
2000
1000
500
32
2.0 MHz / on air
channel step
~2410.001
2000
1000
500
27
FCHSP
(KHz)
Cover Range
(MHz)
FLO_BASE
(MHz)
2405 MHz
2468.0 MHz
63.0 MHz
~2405.001
2410 MHz
2462.5 MHz
52.5 MHz
~2405.001
2.0 MHz / on air
channel step
TI
A
User Defined
(High Band Edge)
250
On air
Channel
Numbers
37
250
31
EN
User Defined
(Low Band Edge)
L
37
NOTE
1.75 MHz / on air
channel step
1.75 MHz / on air
channel step
FI
D
Be notice, if FCHSP = 250 KHz, due to limitation of CHN [7:0], max cover range of FLO is 63.75MHz.
Table 14.6 Band edge frequency setting vs. on air channel number
C
O
N
In long distance applications, user usually adds external PA (Ext-PA) to extend TX power level up 10dBm ~ 20 dBm. To
gain the most available hopping channels under FCC / ETSI regulations, user has to switch off Ext-PA before A7125’s
PA (Em-PA) to minimize spurious emission. In the other words, band edge becomes critical so that A7125 supports two
methods (EOPD and PASW) to let user switch Ext-PA easily.
A
M
IC
C
O
M
(1) EOPD (End Of Packet Delay)
Set GIO2S = [1100] and EOPDS=1, then EOPD outputs 20 us pulse to GIO2 pin.
Jul., 2011, v1.3
64
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
C
O
M
C
O
N
FI
D
EN
TI
A
L
(2) PASW (Ext-PA Switch)
Set GIO2S = [0001] and EOPDS=1, then PASW outputs to GIO2 pin. However, GIO2S[3:0] shall be set different in TX
mode [ 0001] and RX mode [0100] to avoid FSYNC conflict in RX mode. Therefore, before issue TX Strobe command,
write GIO2S = [0001]. Before issue RX Strobe command, write GIO2S = [0100]. Then, PASW is only active in TX mode. In
such case, user just needs to connect GIO2 pin to control external PA as shown below. Generally, this procedure could
support sufficient band edge control. In more rigorous condition, it is recommended to switch GIO2S from [0100] to [0001]
after delaying 30us counting from TX strobe command.
IC
14.4 Frequency Compensation
A
M
AFC (Auto Frequency Compensation) function supports low accuracy crystal without sensitivity degradation. If AFC=1
(19h), bit error rate is optimized because AFC circuitry adjusts RX LO frequency (FRXLO) to compensate crystal drift
automatically.
F LO
F PFD
F XTAL
X
(DBL+1)
/ (RRC[1:0]+1)
AC[14:0]/ 2 16
0
BIP[8:0] +
BFP[15:0]/ 2 16
F LO_BASE
+
CHN / [4*(CHR+1)]
VCO
PFD
1
Divider
0
AFC
+
F LO
F OFFSET
Figure 14.3 Block Diagram of enabling FC function
Jul., 2011, v1.3
65
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
Relative Control Register
RX Register (Address: 19h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
---
RXSM1
1
RXSM0
0
AFC
0
RXDI
0
DMG
0
RAW
1
ULS
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
PLL Register IV (Address: 11h)
Bit 7
Name
R
W
--/FP15
Reset
BFP15
0
BFP14
0
BFP13
0
BFP12
0
BFP11
0
PLL Register V (Address: 12h)
Bit 0
AC8/FP8
BFP9
0
BFP8
0
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
W
AC7/FP7
AC6/FP6
AC5/FP5
AC4/FP4
AC3/FP3
BFP7
0
BFP6
0
BFP5
0
BFP4
0
AC2/FP2
AC1/FP1
AC0/FP0
BFP2
1
BFP1
0
BFP0
0
BFP10
0
EN
Bit
BFP3
0
A
M
IC
C
O
M
C
O
N
FI
D
Reset
Bit 1
AC9/FP9
AC14/FP14 AC13/FP13 AC12/P12 AC11/ FP11 AC10/FP10
L
R/W
TI
A
Bit
Jul., 2011, v1.3
66
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
15. Calibration
A7125 needs calibration process during initialization by below 5 items, they are, VCO Current, VCO Bank, VCO Deviation,
IF Filter Bank and RSSI Calibration.
1.
2.
3.
4.
5.
VCO Current Calibration is to find adequate VCO current.
VCO Bank Calibration is to select best VCO frequency bank for the calibrated frequency.
VCO Deviation Calibration is to calibrate 500 KHz deviation of VCO.
IF Filter Bank Calibration is to calibrate IF filter bandwidth and center frequency.
RSSI Calibration is to find the RSSI value corresponding to -70dBm RF input and RSSI curve.
TI
A
L
Be notice that VCO Current, Bank and Deviation is calibrated in PLL mode by sequence. IF Filter Bank and RSSI can be
calibrated either in standby or PLL mode. User can set A7125 in PLL mode and enable 5 control registers together, then, all
calibration procedures are automatically executed and its results are stored in calibration flags.
Relative Control Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Name
Reset
R/W
---
---
---
VCC
0
15.1 Calibration Procedure
Bit 1
Bit 0
VBC
0
VDC
0
FBC
0
RSSC
0
N
Initialize all control registers (refer to A7125 reference code).
Select auto value mode (set MFBS, MVCS, MVBS, MVDS= 0).
Set A7125 in PLL mode.
Enable IF Filter Bank and RSSI Calibration (set FBC, RSSC= 1) and
Enable VCO Current, Bank and Deviation Calibration (VCC, VBC, VDC= 1).
After calibration done, FBC, RSSC, VCC, VBC and VDC are auto clear.
Check pass or fail by calibration flag
(FBCF) and (VCCF, VBCF).
M
5.
6.
Bit 2
C
O
1.
2.
3.
4.
Bit 3
FI
D
Bit
EN
Calibration Control Register (Address: 02h)
15.2 IF Filter Bank Calibration
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
W
----
----
----
FBCF
MFBS
0
FB3
MFB3
0
FB2
MFB2
1
FB1
MFB1
1
FB0
MFB0
0
IC
C
Bit
Reset
Initialize all control registers (refer A7125 reference code).
Set MFBS= 0 for auto calibration.
Set A7125 in PLL mode.
Set FBC= 1 (02h).
The maximum calibration time for this calibration is about 64us.
FBC is auto clear after calibration done.
User can read calibration flay (FBCF, 23h) to check pass or fail.
User also can read FB [3:0] (23h) to get the auto calibration value.
A
M
1.
2.
3.
4.
5.
6.
7.
8.
O
IF Calibration Register I (Address: 23h)
15.3 RSSI Calibration
1.
2.
3.
Initialize all control registers (refer A7125 reference code).
Set A7125 in PLL mode.
Set RSSC= 1 (02h).
RSSC is auto clear after calibration done.
Jul., 2011, v1.3
67
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
4.
No need to check calibration flag.
15.4 VCO Current Calibration
VCO Current Calibration Register (Address: 25h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
W
----
----
-VCCS
1
VCCF
MVCS
0
VCB3
VCOC3
1
VCB2
VCOC2
1
VCB1
VCOC1
0
VCB0
VCOC0
0
Reset
VCO Bank Calibration Register I (Address: 26h)
R/W
Bit 7
Bit 6
Bit 5
Name
R
W
-DDC1
1
-DDC0
1
-DAGS
0
Bit 3
Bit 2
Bit 1
Bit 0
----
VBCF
MVBS
0
VB2
MVB2
1
VB1
MVB1
0
VB0
MVB0
0
C
O
O
M
Initialize all control registers (refer A7125 reference code).
Set MVBS= 0 for auto calibration.
Set A7125 in PLL mode.
Set VBC= 1 (02h).
The maximum calibration time for VCO Bank Calibration is about 240 us (4 * PLL settling time).
VBC is auto clear after calibration done.
User can read calibration flag (VBCF, 26h) to check pass or fail.
User can read VB [2:0] (26h) to get the auto calibration value.
C
1.
2.
3.
4.
5.
6.
7.
8.
Bit 4
N
Bit
Reset
EN
15.5 VCO Bank Calibration
TI
A
Initialize all control registers (refer A7125 reference code).
Set MVCS= 0 for auto calibration.
Set A7125 in PLL mode.
Set VCC= 1 (02h).
VCC is auto clear after calibration done.
User can read calibration flag (VCCF, 25h) to check pass or fail.
User can read VCB [3:0] (25h) to get the auto calibration value.
FI
D
1.
2.
3.
4.
5.
6.
7.
L
Bit
15.6 VCO Deviation Calibration
IC
VCO Deviation Calibration Register II (Address: 29h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
W
ADEV7
MVDS
0
ADEV6
MDEV6
0
ADEV5
MDEV5
1
ADEV4
MDEV4
0
ADEV3
MDEV3
1
ADEV2
MDEV2
0
ADEV1
MDEV1
0
ADEV0
MDEV0
0
A
M
Bit
Reset
1.
2.
3.
4.
5.
6.
7.
Initialize all control registers (refer A7125 reference code).
Set MVDS= 0 for auto calibration.
Set A7125 in PLL mode.
Set VDC= 1 (02h).
VDC is auto clear after calibration done.
User can read ADEV [7:0] (29h) to get the auto calibration value.
No need to check calibration flag.
15.7 Channel Group Function
Channel group function is used for VCO calibration that supports to increase the accuracy of VCO Current, Bank and
Deviation. By this function, user can easily set Channel Group Register I and II (13h, 14h) to get 2.4G ISM band into 3
groups as shown below. Then, choose middle frequency (2415MHz / 2445MHz / 2475MHz) of 3 groups to do the VCO
Jul., 2011, v1.3
68
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
Current, Bank and Deviation Calibration.
Below is an example of channel group distribution.
2415 M Hz
2445 M Hz
2475 M Hz
IS M b a n d
2460 M Hz
(C H G H )
2 4 8 3 .5 M H z
L
2430 M Hz
(C H G L )
TI
A
2400M H z
Figure 15.1 Channel Group setting of VCO calibration
Channel Group Register I (Address: 13h)
Bit 7
Bit 6
Bit 5
Bit 4
Name
Reset
R/W
CHGL7
0
CHGL6
0
CHGL5
1
CHGL4
1
Channel Group Register II (Address: 14h)
Bit 3
R/W
Bit 7
Bit 6
Bit 5
R/W
CHGH7
0
CHGH6
1
CHGH5
1
Bit 1
Bit 0
CHGL3
1
CHGL2
1
CHGL1
0
CHGL0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CHGH4
1
CHGH3
1
CHGH2
0
CHGH1
0
CHGH0
0
N
Bit
Name
Reset
Bit 2
EN
R/W
FI
D
Bit
BFP
(floating part)
0x0004
0x0005
0x0008
0x000A
FLO_BASE (MHz)
FCHSP (KHz)
CHGL[7:0]
CHGH[7:0]
~2400.001
~2400.001
~2400.001
~2400.001
500
500
500
500
0x3C
0x3C
0x3C
0x3C
0x78
0x78
0x78
0x78
A
M
IC
C
O
16
12
8
6
BIP
(integer part)
0x096
0x0C8
0x12C
0x190
M
FPFD (MHz)
C
O
See below table for setting CHGL and CHGH to get 2430MHz and 2460MHz respectively.
Jul., 2011, v1.3
69
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
16. FIFO (First In First Out)
A7125 supports separated 64-bytes TX and RX FIFO by enabling FMS =1 (01h). For FIFO accessing, TX FIFO (write-only)
and RX FIFO (read-only) share the same register address 05h. TX FIFO represents transmitted payload. On the other
hand, once RX circuitry synchronizes ID Code, received payload is stored into RX FIFO.
L
In chapter 10 and 11, user can also find below FIFO information.
(1) Figure 10.15 and 10.16 for FIFO accessing via 3-wire SPI.
(2) Section 10.4.7 and 10.4.8 for FIFO pointer reset command.
(3) Figure 11.2 and Figure 11.3 for Normal/Quick FIFO mode.
TI
A
16.1 Packet Format of FIFO mode
P re a m b le
ID c o d e
4 b yte s
4 b yte s
EN
D a ta w h ite n in g (o p tio n a l)
F E C e n co d e d /d e c o de d (o p tio n a l)
C R C -1 6 c a lcu la tio n (o p tio n a l)
P a y lo a d
M a x . 2 5 6 b y te s
(C R C )
2 b yte s
FI
D
Figure 16.1 Packet Format of FIFO mode
ID Byte 1
ID Byte 2
ID Byte 3
C
O
ID Byte 0
N
ID code
Figure 16.2 ID Code Format
O
M
Preamble:
The packet is led by preamble which is composed of alternate 0 and 1. If the first bit of ID code is 0, preamble shall be
0101…0101. In the contrast, if the first bit of ID code is 1, preamble shall be 1010…1010.
Preamble length is recommended to set 4 bytes by PML [1:0] (20h).
IC
C
ID code:
ID code is recommended to set 4 bytes by IDL=1 (20h) and ID Code is sequenced by ID Byte 0, 1, 2 and 3. If RX circuitry
check ID code is correct, payload will be written into RX FIFO. In special case, ID code could be set error tolerance (0~ 3bit
error) by ETH [1:0] (21h) for ID synchronization check.
A
M
Payload:
Payload length is programmable by FEP [7:0] (03h). The physical FIFO depth is 64 bytes. A7125 also supports logical FIFO
extension up to 256 bytes. See section 16.5 for details.
CRC (option):
In FIFO mode, if CRC is enabled (CRCS=1, 20h), 2-bytes of CRC value is transmitted automatically after payload. In the
same way, RX circuitry will check CRC value and show the result to CRC Flag (00h).CRC Flag is updated by each received
packet.
Relative Control Register
Mode Register (Address: 00h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
W
-RESETN
--
FECF
RESETN
--
CRCF
RESETN
--
CER
RESETN
--
XER
RESETN
--
PLLER
RESETN
--
TRSR
RESETN
--
TRER
RESETN
--
Reset
Jul., 2011, v1.3
70
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
FIFO Register I (Address: 03h)
Bit
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
FEP7
0
FEP6
0
FEP5
1
FEP4
1
FEP3
1
FEP2
1
FEP1
1
FEP0
1
Code Register I (Address: 20h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
---
---
WHTS
0
FECS
0
CRCS
0
IDL
1
PML1
1
PML0
1
L
Bit
Name
Reset
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Name
Reset
W
---
DCL2
1
DCL1
1
DCL0
1
ETH1
0
Code Register III (Address: 22h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
W
---
WS6
0
WS5
1
WS4
0
Bit 1
Bit 0
ETH0
1
PMD1
1
PMD0
1
Bit 3
Bit 2
Bit 1
Bit 0
WS3
1
WS2
0
WS1
1
WS0
0
FI
D
Bit
Name
Reset
Bit 2
EN
Bit
TI
A
Code Register II (Address: 21h)
16.2 Bit Stream Process
C
O
N
A7125 supports 3 optional bit stream process for payload, they are,
(1) CCITT-16 CRC
(2) (7, 4) Hamming FEC
(3) Data Whitening by XOR PN7 (7-bits Pseudo Random Sequence).
O
M
CRC (Cyclic Redundancy Check):
1.
CRC is enabled by CRCS= 1 (20h). TX circuitry calculates the CRC value of payload (preamble, ID code excluded)
and transmits 2-bytes CRC value after payload.
2.
RX circuitry checks CRC value and shows the result to CRC Flag (00h). If CRCF=0, received payload is correct, else
error occurred. (CRCF is read only, it is updated by each valid packet.)
IC
C
FEC (Forward Error Correction):
1.
FEC is enabled by FECS= 1 (20h). Payload and CRC value (if CRCS=1) are encoded by (7, 4) Hamming code.
2.
Each 4-bits (nibble) of payload is encoded into 7-bits code word and delivered out automatically.
(ex. 64 bytes payload will be encoded to 128 code words, each code word is 7 bits.)
3.
RX circuitry decodes received code words automatically. FEC supports 1-bit error correction each code word. Once
1-bit error occurred, FEC flag=1 (00h). (FECF is read only, it is updated by each valid packet.)
A
M
Data Whitening:
1.
Data whitening is enabled by WHTS= 1 (20h). Payload and CRC value (if CRCS=1) or their encoded code words (if
FECS=1) are encrypted by bit XOR operation with PN7. The initial seed of PN7 is set by WS [6:0] (22h).
2.
RX circuitry decrypts received payload and 2-bytes CRC (if CRCS=1) automatically. Be notice, user shall set the
same WS [6:0] (22h) to TX and RX.
16.3 Transmission Time
Based on CRC and FEC options, the transmission time are different. See table 16.1 for details.
Data Rate = 2 Mbps
Data Rate Preamble
(Mbps)
(bits)
2
32
2
32
2
32
2
32
Jul., 2011, v1.3
ID Code
Payload
CRC
FEC
(bits)
(bits)
(bits)
32
512
Disable
Disable
32
512
16 bits
Disable
32
512
Disable
512 * 7 / 4
32
512
16 * 7 / 4
512 * 7 / 4
Table 16.1 Transmission time of 2 Mbps data rate
71
Transmission
Time / Packet
576 bit * 0.5 us = 288 us
592 bit * 0.5 us = 296 us
960 bit * 0.5 us = 480 us
988 bit * 0.5 us = 494 us
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
Data Rate = 1 Mbps
Data Rate Preamble
(Mbps)
(bits)
1
32
1
32
1
32
1
32
Transmission
Time / Packet
576 bit * 1.0 us = 576 us
592 bit * 1.0 us = 592 us
960 bit * 1.0 us = 960 us
988 bit * 1.0 us = 988 us
L
ID Code
Payload
CRC
FEC
(bits)
(bits)
(bits)
32
512
Disable
Disable
32
512
16 bits
Disable
32
512
Disable
512 * 7 / 4
32
512
16 * 7 / 4
512 * 7 / 4
Table 16.2 Transmission time of 1 Mbps data rate
TI
A
16.4 Usage of TX and RX FIFO
EN
In application points of view, A7125 supports 3 options of FIFO arrangement.
(1) Easy FIFO
(2) Segment FIFO
(3) FIFO Extension
Strobe Command
Strobe Command
A7
A6
A5
A4
A3
A2
A1
A0
1
1
1
1
1
1
0
1
x
x
x
x
X
X
x
x
FI
D
For FIFO operation, A7125 supports Strobe command to reset TX and RX FIFO pointer as shown below. User can refer to
section 10.5 for FIFO write pointer reset and FIFO read pointer reset.
Description
N
FIFO write pointer reset (for TX FIFO)
FIFO read pointer reset (for RX FIFO)
C
O
FIFO Register I (Address: 03h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset
W
FEP7
0
FEP6
0
FEP5
1
FEP4
1
FEP3
1
FEP2
1
FEP1
1
FEP0
1
M
Bit
O
FIFO Register II (Address: 04h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
FPM1
0
FPM0
1
PSA5
0
PSA4
0
PSA3
0
PSA2
0
PSA1
0
PSA0
0
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
FIFO7
0
FIFO6
0
FIFO5
0
FIFO4
0
FIFO3
0
FIFO2
0
FIFO1
0
FIFO0
0
IC
C
Bit
Name
Reset
FIFO DATA Register (Address: 05h)
A
M
Bit
Name
Reset
16.4.1 Easy FIFO
In Easy FIFO, max FIFO length is 64 bytes. FIFO length is equal to (FEP [7:0] +1). User just needs to control FEP [7:0]
(03h) and disable PSA and FPM as shown below.
Register setting
TX
RX
FIFO
Length
(byte)
1
FIFO
Length
(byte)
1
Jul., 2011, v1.3
Control Registers
FEP[7:0]
(03h)
PSA[5:0]
(04h)
FPM[1:0]
(04h)
0x00
0
0
72
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
8
16
32
64
8
16
32
64
0x07
0x0F
0x1F
0x3F
0
0
0
0
0
0
0
0
Table 16.3 Control registers of Easy FIFO
TI
A
L
Procedures of TX FIFO Transmitting
1.
Initialize all control registers (refer A7125 reference code).
2.
Set FEP [7:0] = 0x3F for 64-bytes FIFO.
3.
Refer to Figure 11.2 and Figure 11.3
4.
Send Strobe command – TX FIFO write pointer reset.
5.
MCU writes 64-bytes data to TX FIFO.
6.
Send TX Strobe Command.
7.
Done.
A
M
IC
C
O
M
C
O
N
FI
D
EN
Procedures of RX FIFO Reading
1.
When RX FIFO is full, WTR (or FSYNC) can be used to trigger MCU for RX FIFO reading.
2.
Send Strobe command – RX FIFO read pointer reset.
3.
MCU read 64-bytes from RX FIFO.
4.
Done.
Figure 16.3 Easy FIFO
16.4.2 Segment FIFO
In Segment FIFO, TX FIFO length is equal to (FEP [7:0] － PSA [5:0]＋1). FPM [1:0] should be zero. This function is very
useful for button applications. In such case, each button is used to transmit fixed code (data) every time. During
initialization, each fixed code is written into corresponding segment FIFO once and for all. Then, if button is triggered, MCU
just assigns corresponding segment FIFO (PSA [5:0] and FEP [7:0]) and issues TX strobe command.
If TX FIFO is arranged into 8 segments, each TX segment and RX FIFO length are 8 bytes
TX
Segment
Jul., 2011, v1.3
PSA
Control Registers
FEP
FIFO
Length
PSA[5:0]
(04h)
73
FEP[7:0]
(03h)
FPM[1:0]
(04h)
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
PSA1
PSA2
PSA3
PSA4
PSA5
PSA6
PSA7
PSA8
(byte)
8
8
8
8
8
8
8
8
FEP1
FEP2
FEP3
FEP4
FEP5
FEP6
FEP7
FEP8
0x07
0x0F
0x17
0x1F
0x27
0x2F
0x37
0x3F
0
0
0
0
0
0
0
0
Control Registers
FIFO
Length
(byte)
8
PSA[5:0]
(04h)
FEP[7:0]
(03h)
FPM[1:0]
(04h)
0
0x07
0
TI
A
RX
0x00
0x08
0x10
0x18
0x20
0x28
0x30
0x38
L
1
2
3
4
5
6
7
8
EN
Table 16.4 Segment FIFO is arranged into 8 segments
M
C
O
N
FI
D
Procedures of TX FIFO Transmitting
1.
Initialize all control registers (refer A7125 reference code).
2.
Refer to Figure 11.2 and Figure 11.3 (in chapter 11).
3.
Send Strobe command – TX FIFO write pointer reset.
4.
MCU writes fixed code into corresponding segment FIFO once and for all.
5.
To consign Segment 1, set PSA = 0x00 and FEP= 0x07
To consign Segment 2, set PSA = 0x08 and FEP= 0x0F
To consign Segment 3, set PSA = 0x10 and FEP= 0x17
To consign Segment 4, set PSA = 0x18 and FEP= 0x1F
To consign Segment 5, set PSA = 0x20 and FEP= 0x27
To consign Segment 6, set PSA = 0x28 and FEP= 0x2F
To consign Segment 7, set PSA = 0x30 and FEP= 0x37
To consign Segment 8, set PSA = 0x38 and FEP= 0x3F
6.
Send TX Strobe Command.
7.
Done.
A
M
IC
C
O
Procedures of RX FIFO Reading
1.
When RX FIFO is full, WTR (or FSYNC) is used to trigger MCU for RX FIFO reading.
2.
Send Strobe command – RX FIFO read pointer reset.
3.
MCU read 8-bytes from RX FIFO.
4.
Done.
Jul., 2011, v1.3
74
AMICCOM Electronics Corporation
A7125
FI
D
EN
TI
A
L
2.4GHz FSK Transceiver
A
M
IC
C
O
M
C
O
N
Figure 16.4 Segment FIFO Mode
Jul., 2011, v1.3
75
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
16.4.3 FIFO Extension
In FIFO Extension, FIFO length is equal to (FEP [7:0] +1). PSA [5:0] shall be zero, and FPM [1:0] is used to set FIFO
Pointer Flag (FPF) to MCU. FIFO extension could be set up to 256 bytes by FEP [7:0] with different FPF trigger conditions.
Be notice, setting of SPI data rate is important to prevent error operation of FIFO extension. The min. SPI data rate shall be
equal or greater than (A125 data rate + 500Kbps) and refer Table 16.4 and 16.5 for max. SPI Data Rate.
If A7125 data rate = 2Mbps and FIFO extension = 256 bytes.
RX
256
FIFO
Length
(byte)
Max. SPI
Data Rate
10 Mbps
10 Mbps
10 Mbps
8 Mbps
256
FPF
Trigger
Condition
Delta = 60
Delta = 56
Delta = 52
Delta = 48
Max. SPI
Data Rate
10 Mbps
10 Mbps
10 Mbps
8 Mbps
FEP[7:0]
L
FPF
Trigger
Condition
Delta = 04
Delta = 08
Delta = 12
Delta = 16
0xFF
EN
FIFO
Length
(byte)
Control Registers
FPM[1:0]
PSA[5:0]
00
01
10
11
0
0
0
0
TI
A
TX
FI
D
Table 16.5 How to set FIFO extension when A7125 is at 2Mbps data rate
If A7125 data rate = 1Mbps and FIFO extension = 256 bytes.
FPF
Trigger
Condition
Delta = 04
Delta = 08
Delta = 12
Delta = 16
10 Mbps
8 Mbps
5 Mbps
4 Mbps
FIFO
Length
(byte)
FPF
Trigger
Condition
Delta = 60
Delta = 56
Delta = 52
Delta = 48
Max SPI Data
Rate
256
10 Mbps
8 Mbps
5 Mbps
4 Mbps
Control Registers
FEP[7:0]
FPM[1:0]
PSA[5:0]
0xFF
00
01
10
11
0
0
0
0
M
256
Max SPI
Data Rate
C
O
FIFO
Length
(byte)
RX
N
TX
Table 16.6 How to set FIFO extension when A7125 is at 1Mbps data rate
O
Please refer to AMICCOM’s reference code (FIFO extension) for details.
A
M
IC
C
Procedures of TX FIFO Extension
1.
Initialize all control registers (refer A7125 reference code).
2.
Set FEP [7:0] = 0xFF for 256-bytes FIFO extension.
3.
Set FPM [1:0] = 11 for FPF trigger condition.
4.
Set CKO Register = 0x12
5.
Send Strobe command – TX FIFO write pointer reset.
6.
MCU writes 1st 64-bytes TX FIFO.
7.
Send TX Strobe command.
8.
MCU monitors FPF from A7125’s CKO pin.
9.
FPF triggers MCU to write 2nd 48-bytes TX FIFO.
10. Monitor FPF.
11. FPF triggers MCU to write 3rd 48-bytes TX FIFO.
12. Monitor FPF.
13. FPF triggers MCU to write 4th 48-bytes TX FIFO.
14. Monitor FPF.
15. FPF triggers MCU to write 5th 48-bytes TX FIFO.
16. Done.
Jul., 2011, v1.3
76
AMICCOM Electronics Corporation
A7125
A
M
IC
C
O
M
C
O
N
FI
D
EN
TI
A
L
2.4GHz FSK Transceiver
Figure 16.5 TX FIFO Extension
Jul., 2011, v1.3
77
AMICCOM Electronics Corporation
A7125
TI
A
A
M
IC
C
O
M
C
O
N
FI
D
EN
Procedures of RX FIFO Reading
1.
Initialize all control registers (refer A7125 reference code).
2.
Set FEP [7:0] = 0xFF for 256-bytes FIFO extension.
3.
Set FPM [1:0] = 11b for FPF trigger condition.
4.
Set CKO Register = 0x12
5.
Send Strobe command – RX FIFO read pointer reset.
6.
Send RX Strobe command.
7.
MCU monitors FPF from A7125’s CKO pin.
8.
FPF triggers MCU to read 1st 48-bytes RX FIFO.
9.
Monitor FPF.
10. FPF triggers MCU to read 2nd 48-bytes RX FIFO.
11. Monitor FPF.
12. FPF triggers MCU to read 3rd 48-bytes RX FIFO.
13. Monitor FPF.
14. FPF triggers MCU to read 4th 48-bytes RX FIFO.
15. Monitor FPF.
16. FPF triggers MCU to read 5th 48-bytes RX FIFO.
17. Monitor WTR falling edge or WTR = low, read the rest 16-bytes RX FIFO
18. Done.
L
2.4GHz FSK Transceiver
Jul., 2011, v1.3
78
AMICCOM Electronics Corporation
A7125
FI
D
EN
TI
A
L
2.4GHz FSK Transceiver
A
M
IC
C
O
M
C
O
N
Figure 16.6 RX FIFO Extension Mode
Jul., 2011, v1.3
79
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
16.5 Optimize Throughput
A
M
IC
C
O
M
C
O
N
FI
D
EN
TI
A
Pre-Conditions:
1.
A7125’s data rate = 2Mbps.
2.
Min. requirement of CPU SPI bus = 2.5 Mbps > A7125’s data rate.
3.
If MCU SPI bus = 8Mbps and ignore guard time of SPI.
i.
Write TX-FIFO = (addr+data) * 0.125 us = (1+64) * 8 * 0.125 = 65 us.
ii.
Read RX-FIFO = (addr+data) * 0.125 us = (1+64) * 8 * 0.125 = 65 us.
4.
CRC is enabled.
5.
Use Easy FIFO mode (64 bytes).
6.
One packet = Preamble + ID + Payload + CRC = (4+4+64+2) * 8 = 592 bit.
7.
One packet transmission time = 592 bits * 0.5 = 296 us.
8.
W=1 us if EOPDS = 0; W=23.5 us if EOPDS = 1
9.
One frequency channel for n-packets.
10. MCU monitors WTR.
L
To get the best throughput during two-way radio transmission, user can use FIFO Extension mode, section 16.4.3, to
reduce overhead of preamble, ID, settling time delay of PDL and TDL. The disadvantage of FIFO Extension is more MCU
loading and overhead of retransmission time if packet lost. In another way, by Easy FIFO mode, If MCU’s SPI bus ≧
2.5Mbps, user can use WTR signal to Read / Write FIFO during PDL+TDL settling time to gain more throughput. See below
illustrations with pre-conditions.
However, If MCU’s SPI bus < 2.5Mbps and EOPD =1 for band edge optimization in adding Ext-PA application, user can use
EOP signal to Write FIFO to gain a few throughput. See below illustrations with pre-conditions.
Jul., 2011, v1.3
80
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
TXStrobe Cmd
TXStrobe Cmd
Packet 2
70us
296 us
(PDL+TDL)
Packet n
EN
Packet 1
90us
(PDL+TDL)
GIO1 Pin - WTR
(GIO1S[3:0]=0000)
TI
A
TXStrobe Cmd
L
Pre-Conditions:
1.
A7125’s data rate = 2Mbps.
2.
If MPU SPI bus = 1Mbps and ignore guard time of SPI, CRCF Check and MCU’s ISR.
i.
Write TX-FIFO = (addr+data) * 1 us = (1+64) * 8 * 1 = 520 us.
ii.
Read RX-FIFO = (addr+data) * 1 us = (1+64) * 8 * 1 = 520 us.
3.
CRC is enabled.
4.
Use Easy FIFO mode (64 bytes).
5.
One packet = Preamble + ID + Payload + CRC = (4+4+64+2) * 8 = 592 bit.
6.
One packet transmission time = 592 bits * 0.5 = 296 us.
7.
EOPDS = 1.
8.
One frequency channel for n-packets.
9.
MCU monitors EOP.
70us
296 us
(PDL+TDL)
23.5 us
23.5 us
23.5 us
FI
D
GIO1 Pin - EOP
(GIO1S[3:0]=1100)
296 us
520 us
520 us
Write TX-FIFO
(64 bytes)
N
Write TX-FIFO
(64 bytes)
C
O
Total Transmitting Time (Master Site in TX Mode)
RXStrobe Cmd
M
RXStrobe Cmd
Packet 1
90us
(PDL+TDL)
296 us
Packet 2
70us
(PDL+TDL)
A
M
IC
C
23.5 us
GIO1 Pin - EOP
(GIO1S[3:0]=1100)
Jul., 2011, v1.3
Packet n
70us
296 us
O
GIO1 Pin - WTR
(GIO1S[3:0]=0000)
RXStrobe Cmd
520 us
Read RX-FIFO
(64 bytes)
(PDL+TDL)
296 us
23.5 us
23.5 us
520 us
520 us
Read RX-FIFO
(64 bytes)
Read RX-FIFO
(64 bytes)
Total Receiving Time (Slave Site in RX Mode)
81
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
17. ADC (Analog to Digital Converter)
A7125 has built-in 8-bits ADC that supports multi-functions to do temperature measurement, RSSI, carrier detection. User
can set FSARS (1Fh) to select 4MHz or 8MHz ADC clock (FADC). The converting time is 20 times of ADC clock periods.
RX mode
None
RSSI / Carrier detect
None
Table 17.1 ADC Function List.
Mode Control Register (Address: 01h)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Name
R
W
DDPC
DDPC
0
ARSSI
ARSSI
0
AIF
AIF
0
CD
DFCD
0
RX Gain Register IV (Address: 1Dh)
R/W
Bit 7
Bit 6
Bit 5
W
AVSEL1
0
AVSEL0
1
MVSEL1
0
Bit 7
Name
R
W
ADC7
RTH7
1
Reset
Bit 0
WWSE
WWSE
0
FMT
FMT
0
FMS
FMS
0
ADCM
ADCM
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MVSEL0
0
LHC1
1
LHC0
1
AGCE
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC6
RTH6
0
ADC5
RTH5
0
ADC4
RTH4
1
ADC3
RTH3
0
ADC2
RTH2
0
ADC1
RTH1
0
ADC0
RTH0
1
C
O
R/W
Bit 1
MHC
1
M
Bit
Bit 2
N
Bit
Name
Reset
RSSI Threshold Register (Address: 1Eh)
Bit 3
FI
D
Bit
EN
Relative Control Register
Reset
L
RSS
0
1
X
Description
Standby mode
Temperature
None
Reserved
TI
A
Bit
XADS
0
0
1
O
ADC Control Register (Address: 1Fh)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
RSM1
0
RSM0
1
RADC1
0
RADC0
0
FSARS
1
XADS
0
RSS
1
CDM
1
IC
C
Bit
Name
Reset
A
M
17.1 Temperature Measurement
A7125 has built-in thermal sensor. Combined with 8-bits ADC, it can be used to monitor the relative environment
temperature. Below is the measurement procedure:
1.
2.
3.
4.
5.
Set RSS= 0 (1Fh), FSARS= 0 (1Fh).
Enter Standby mode.
Set ADCM= 1 (01h). A7125 will enable relative temperature measurement automatically.
After measurement done, ADCM is auto clear.
User can read digital temperature value from ADC [7:0] (1Eh).
17.2 RSSI Measurement
A7125 has built-in 8-bits digital RSSI to detect RF signal strength. After measurement done, RSSI is stored in ADC [7:0]
(1Eh). The more signal power, the larger RSSI value.
Below is the measurement procedure:
Jul., 2011, v1.3
82
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
Auto RSSI measurement for TX Power:
1.
Set wanted FRXLO (Refer to chapter 14).
2.
Set ADCM=1 (01h), RSS= 1 (1Fh), FSARS= 1 (1Fh, 8MHz ADC clock).
3.
Enable MVSEL = [00] (1Dh) and RADC = [10] (1Fh) to do 8-times average RSSI measurement.
4.
Set ARSSI= 1 (01h).
5.
Send RX Strobe command.
6.
Once entering into RX mode, A7125 executes 8-times average measurement repeatedly.
7.
Once A7125 leaves RX mode, user can read digital RSSI value from ADC [7:0] (1Eh) for TX power.
Strobe CMD
(SCS,SCK,SDIO)
TI
A
L
Be notice, in step 7, if A7125 is set in direct mode, once the received packet is completed, MCU shall ask A7125 to leave
RX mode within 40 us to prevent RSSI inaccuracy.
RX-Strobe
MCU Read ADC[7:0] (1Eh)
Received Packet
GIO2 Pin - FSYNC
(GPIO2S[3:0]=0001)
T0
T2
T3
T4
T5
N
Settling Time from PLL to RX mode
Receiving Packet
A7125 leaves RX mode
MCU read RSSI value @ ADC [7:0](1Eh)
C
O
T0-T1:
T2-T3:
T3:
T4-T5:
T1
FI
D
GIO1 Pin - WTR
(GPIO1S[3:0]=0000)
EN
Read 8-bits RSSI value
RFI Pin
M
Figure 17.1 Timing chart of Auto RSSI measurement for TX Power:
A
M
IC
C
O
Auto RSSI measurement for Background Power:
1.
Set wanted FRXLO (Refer to chapter 14).
2.
Set ADCM=1 (01h), RSS= 1 (1Fh), FSARS= 1 (1Fh, 8MHz ADC clock).
3.
Enable MVSEL = [00] (1Dh) and RADC = [10] (1Fh) to do 8-times average RSSI measurement.
4.
Set ARSSI= 1 (01h).
5.
Send RX Strobe command.
6.
MCU delays min. 140us.
7.
Read digital RSSI value from ADC [7:0] (1Eh) to get background power.
8.
Send Strobe command to ask A7125 to leave RX mode.
Jul., 2011, v1.3
83
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
Strobe CMD
(SCS,SCK,SDIO)
RX-Strobe
MCU Read ADC[7:0] (1Eh)
No Packet
RFI Pin
Min. 140 us
GIO1 Pin - WTR
(GPIO1S[3:0]=0000)
MCU can read 8-bits RSSI value that Is re-calculated every 20 us
T0
T1
EN
T0-T1: MCU Delay Loop from PLL to RX mode for RSSI measurment
T1 : Auto RSSI Measurment is done by 8-times average.
MCU can read RSSI value from ADC [7:0](1Eh)
RSSI measurement Iis re-calculated every 20 us.
TI
A
L
GIO2 Pin - FSYNC
(GPIO2S[3:0]=0001)
FI
D
Figure 17.2 Timing chart of Auto RSSI measurement for Background Power:
17.3 Carrier Detect
Set RTH (1Eh) for RSSI higher threshold by user’s definition (see below Table 17.2).
Set RTL (RTL = RTH – RSM) by RSM = [11] (1Fh) (recommended).
Set GIO1S = [0010] (0Bh) for GIO1 pin to output CD signal.
Follow procedure of auto RSSI measurement.
MCU checks GIO1 pin for carrier detect (CD) signal.
M
1.
2.
3.
4.
5.
C
O
N
Base on RSSI measurement, user can extend its application to do carrier detect (CD). If CD is triggered, its output can be
set to GIO1 or GIO2 pin to inform MCU the occupied channel.
Below is the detection procedure:
O
In step 1, MCU can read RH and RL to calculate and store the RTH value corresponding to desired CD trigger level below.
RH [7:0]
IC
C
RSSI Range
A
M
Max (-50 dBm)
Min (-100 dBm)
Address
1Bh
RL [7:0]
Address
1Ch
CD
Trigger Level
(dBm)
-58
-64
-70
-76
-82
RTH
(Recommended)
(3RH - RL) / 2
RH
(RH + RL) / 2
RL
(3RL - RH) / 2
Note
Formula of
digital RSSI
values is just
approximate for
reference.
Table 17.2 RTH Recommended Setting
In step 5, CD=1 if measured RSSI ≧ RTH. That means this channel is occupied.
CD=0 if measured RSSI ≦ RTL. That means this channel is clear.
Jul., 2011, v1.3
84
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
18. Battery Detect
A7125 has built-in battery detector to check supply voltage (REGI pin). The detect range is 2.0V ~ 2.7V in 8 levels.
Relative Control Register
Battery Detect Register (Address: 2Ch)
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R
W
-RGS
0
-RGV1
1
-RGV0
0
BDF
QDS
0
-BVT2
0
-BVT1
1
-BVT0
1
-BD_E
0
Reset
EN
TI
A
BVT [2:0]: Battery voltage detect threshold.
[000]: 2.0V. [001]: 2.1V. [010]: 2.2V. [011]: 2.3V.
[100]: 2.4V. [101]: 2.5V. [110]: 2.6V. [111]: 2.7V.
L
Bit
Set A7125 in standby or PLL mode.
Set BVT (2Ch) = [001] and enable BD_E (2Ch) = 1.
After 5 us, BD_E is auto clear.
MCU check BDF (2Ch).
If REGI pin > 2.1V,
BDF = 1. Else, BDF = 0.
A
M
IC
C
O
M
C
O
N
1.
2.
3.
4.
FI
D
Below is the procedure of battery detect for low voltage detection (ex., below 2.1V):
Jul., 2011, v1.3
85
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
19. Application Circuit Example
Below are AMICCOM’s ref. design module, MD7125-A04, circuit example and its PCB layout.
C9
2.2uF
VDD_A
REGI
CKO
GIO2
GIO1
18
17
16
GIO1
CKO
REGI
GIO2
XO
XI
SDIO
12
C10
2.2uF
SCK
SCS
11
A7125PKG
C
O
R1
2.7k
C14
2.2nF
1
C16
180pF
C17
VDD_A
33pF
2
Y1
16MHz
C18
27pF
C7
C19
0.1uF 100pF
M
A7125 schematic for RF layouts with single ended 50Ω RF output.
C17 and C18 must be matched to the crystal’s load capacitance, Cload. Please see application note for detail.
A
M
IC
C
O
1.
2.
SCS
13
C6
0.1uF
N
C5
100pF
SCK
15
14
10
VDD_A
L3
1.5nH
VDD_PLL
L4
R2
1.2nH NC
RFC
9
C15
1pF
VDD_D
A7125PKG
RFO
CP
5
C12
3.9pF
RFI
8
4
L5
C8 2.2nH
1pF
GND
SDIO
6
C13
1pF
BP_BG
FI
D
ANT
3
BP_RSSI
EN
L1
2.7nH
2
U1
TI
A
1
C11
3.9pF
C1
NC
19
C3
100pF
VDD_VCO
C2
1nF
VDD_A
C4
4.7uF
HEADER 4X2A/2.54
20
REGI
SCS
SDIO
GIO2
2
4
6
8
7
SCK
GIO1
1
3
5
7
L
J1
GND
Jul., 2011, v1.3
86
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
MD7125-A04 which size is 13mm x 20mm with PCB antenna is suitable for small form factor application. MD7125-A04 is
based on a design by a double-sided FR-4 board of 0.8mm thickness. All passive components are 0402 size. This PCB
has a ground plane on the bottom layer. Additionally, there are ground areas on the component side of the board to ensure
sufficient grounding of critical components. Keep sufficient via holes to connect the top layer ground areas to the bottom
layer ground plane. Be notice, IC back side plate shall be well-solder to ground; otherwise, it will impact RF
performance.
IC
C
O
M
C
O
N
FI
D
EN
TI
A
L
To get a good RF performance, the well designed PCB is necessary. A poor layout can lead to loss of RF performance
especially on matching networks as well as VDD bypass capacitors. PCB layout of critical traces shall follow AMICCOM’s
recommended values and layout placement. Long power supply lines on the PCB should be avoided. Keep GND via holes
as close as possible to A7125’s GND pad and IC back side plate (GND).
A
M
Be Notice,
1.
IC Back side plate shall be well-solder to
ground (U1 area) for good RF performance.
2.
Need at least 9 GND via holes at U1 area
Jul., 2011, v1.3
87
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
20. Abbreviations
C
O
N
FI
D
EN
TI
A
L
Analog to Digital Converter
Auto IF
Frequency Compensation
Automatic Gain Control
Bit Error Rate
Bandwidth
Carrier Detect
Channel Step
Cyclic Redundancy Check
Direct Current
Forward Error Correction
First in First out
Frequency Shift Keying
Identifier
Intermediate Frequency
Industrial, Scientific and Medical
Local Oscillator
Micro Controller Unit
Phase Frequency Detector for PLL
Phase Lock Loop
Power on Reset
Receiver
Receiver Local Oscillator
Received Signal Strength Indicator
Serial to Parallel Interface
System Clock for digital circuit
Transmitter
Transmitter Radio Frequency
Voltage Controlled Oscillator
Crystal Oscillator
Crystal Reference frequency
Crystal
O
M
ADC
AIF
FC
AGC
BER
BW
CD
CHSP
CRC
DC
FEC
FIFO
FSK
ID
IF
ISM
LO
MCU
PFD
PLL
POR
RX
RXLO
RSSI
SPI
SYCK
TX
TXLO
VCO
XOSC
XREF
XTAL
IC
Part No.
C
21. Ordering Information
Package
Units Per Reel / Tray
QFN20L, Pb Free, Tape & Reel, -40℃〜85℃
3K
A71X25AQFI
QFN20L, Pb Free, Tray, -40℃〜85℃
490EA
A71X25AH
Die form, -40℃〜85℃
250EA
A
M
A71X25AQFI/Q
Jul., 2011, v1.3
88
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
22. Package Information
QFN 20L (4 X 4 X 0.8mm) Outline Dimensions
unit: inches/mm
TOP VIEW
BOTTOM VIEW
0.25 C
D
D2
11
11
15
L
15
10
L
16
10
e
E
E2
TI
A
16
20
0.25 C
20
EN
6
6
5
5
e
b
1
0.10 M C A B
FI
D
1
Symbol
C
Dimensions in inches
Nom
Max
Min
Nom
Max
0.030
0.032
0.70
0.75
0.80
A1
0.000
0.001
0.002
0.00
0.02
0.05
M
Min
0.028
O
0.008 REF
0.203 REF
B
0.007
0.010
0.012
0.18
0.25
D
0.154
0.158
0.161
3.90
4.00
4.10
D2
0.075
0.079
0.083
1.90
2.00
2.10
E
0.154
0.158
0.161
3.90
4.00
4.10
E2
0.075
0.079
0.083
1.90
2.00
2.10
C
IC
A
M
Dimensions in mm
A
A3
Jul., 2011, v1.3
y C
C
O
Seating Plane
A3
A1
A
N
// 0.10 C
0.020 BSC
e
L
Y
0.012
0.016
0.30
0.50 BSC
0.020
0.003
0.30
0.40
0.50
0.08
89
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
23. Top Marking Information
A71X25AQFI
L
Part No.
: A71X25AQFI
Pin Count
: 20
Package Type : QFN
Dimension
: 4*4 mm
Mark Method
: Laser Mark
Character Type : Arial
A
M
IC
C
O
M
C
O
N
FI
D
EN
TI
A
¡
¡
¡
¡
¡
¡
Jul., 2011, v1.3
90
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
A
M
IC
C
O
M
C
O
N
FI
D
EN
TI
A
L
24. Reflow Profile
Jul., 2011, v1.3
91
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
25. Tape Reel Information
8±0.1
QFN 4*4
8±0.1
QFN 5*5
8±0.1
SSOP
12±0.1
B0
P0
P1
D0
D1
3.2
5±0.1
4.35
±0.1
5.25
±0.1
3.25
±0.1
4.35
±0.1
5.25
±0.1
4±0.2
2±0.1 1.5±0.1
4±0.2
2±0.1 1.5±0.1
4±0.2
2±0.1 1.5±0.1
1.5
1.5
N
QFN3*3
A0
1.5
C
O
P
8.2±1 8.8±1.5 4.0±0.1 2.0±0.1 1.5±0.1 1.5±0.1
E
F
1.75
±0.1
1.75
±0.1
1.75
±0.1
1.75
±0.1
5.5
±0.05
5.5
±0.05
5.5
±0.05
W
Unit: mm
Cover
tape
width
t
0.3
9.3±0.1
±0.05
0.3
12±0.3
9.3±0.1
±0.05
0.3
12±0.3
9.3±0.1
±0.05
0.3
13.3
7.5±0.1 16±0.1 2.1±0.4
±0.05
±0.1
1.25
±0.1
1.2
5±0.1
1.25
±0.1
T
IC
C
O
REEL DIMENSIONS
K0
12±0.3
M
TYPE
FI
D
EN
TI
A
L
Cover / Carrier Tape Dimension
R
D
A
M
L
N
K
M
G
Unit: mm
TYPE
G
N
M
D
K
L
R
QFN
12.9±0.5
102 REF±2.0
2.3±0.2
13.15±0.35
2.0±0.5
330±3.0
19.6±2.9
SSOP
16.3±1
102 REF±2.0
2.3±0.2
13.15±0.35
2.0±0.5
330±3.0
19.6±2.9
Jul., 2011, v1.3
92
AMICCOM Electronics Corporation
A7125
2.4GHz FSK Transceiver
26. Product Status
Product Status
Planned or Under Development
Definition
This data sheet contains the design specifications
for product development. Specifications may
change in any manner without notice.
Preliminary
Engineering Samples
and First Production
This data sheet contains preliminary data, and
supplementary data will be published at a later
date. AMICCOM reserves the right to make
changes at any time without notice in order to
improve design and supply the best possible
product.
No Identification
Noted Full Production
Obsolete
Not In Production
This data sheet contains the final specifications.
AMICCOM reserves the right to make changes at
any time without notice in order to improve design
and supply the best possible product.
This data sheet contains specifications on a
product that has been discontinued by AMICCOM.
The data sheet is printed for reference information
only.
IC
C
O
M
C
O
N
FI
D
EN
TI
A
L
Data Sheet Identification
Objective
A
M
RF ICs AMICCOM
Headquarter
A3, 1F, No.1, Li-Hsin Rd. 1, Hsinchu Science Park,
Taiwan 30078
Tel: 886-3-5785818
Shenzhen Office
Rm., 2003, DongFeng Building, No. 2010,
Shennan Zhonglu Rd., Futian Dist., Shenzhen, China
Post code: 518031
Web Site
http://www.amiccom.com.tw
Jul., 2011, v1.3
93
AMICCOM Electronics Corporation
工商网监
湘ICP备2023018690号
