A71X30AQFI/Q

A7130 2.4GHz FSK/GFSK Security Transceiver Document Title A7130 Data Sheet, 2.4GHz FSK/GFSK Transceiver with 4Mbps data rate Revision History Issue Date 0.0 Initial issue. Dec, 2009 0.1 Update ch8 and the application circuit. July, 2011 Preliminary, 0.2 Modify the tape reel information and the add Shenzhen office address. July, 2011 Preliminary, 0.3 Add Ch20 WOR and Ch21 AES128. Aug., 2011 Preliminary, 0.4 Add section 16.4.3 FIFO extension and Ch21 AES128. Update sleep current, Xtal start up time and PDL formula, TMOE timing, WTR Timing, and Ch14. Apr., 2012 Preliminary,, 0.5 Remove 3Mbps data rate Add descriptions for HECF, FECF and CRCF clear method in 9.2.1 Aug.,2012 Preliminary 0.6 Add suggestion in WOR function Oct. 2012 Preliminary 1.0 Add more description for ADC function Mar. 2013 Full Production FI D EN TI A Objective A M IC C O M C O Remark L History N Rev. No. Important Notice: AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such applications is understood to be fully at the risk of the customer. Mar., 2013, Version 1.0 1 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver Table of Contents A M IC C O M C O N FI D EN TI A L 1. General Description....................................................................................................................................................... 1 2. Typical Applications ....................................................................................................................................................... 1 3. Feature ......................................................................................................................................................................... 1 4. Pin Configurations ......................................................................................................................................................... 6 5. Pin Description (I: input; O: output, I/O: input or output)................................................................................................... 5 6. Chip Block Diagram....................................................................................................................................................... 6 7. Absolute Maximum Ratings............................................................................................................................................ 7 8. Electrical Specification................................................................................................................................................... 8 9. Control Register ...........................................................................................................................................................10 9.1 Control register table............................................................................................................................................10 9.2 Control register description ..................................................................................................................................13 9.2.1 Mode Register (Address: 00h) ....................................................................................................................13 9.2.2 Mode Control Register (Address: 01h)......................................................................................................13 9.2.3 Calibration Control Register (Address: 02h)..............................................................................................14 9.2.4 FIFO Register I (Address: 03h).................................................................................................................14 9.2.5 FIFO Register II (Address: 04h)................................................................................................................14 9.2.6 FIFO DATA Register (Address: 05h) .........................................................................................................14 9.2.7 ID DATA Register (Address: 06h)................................................................................................................14 9.2.8 RC OSC Register I (Address: 07h) .............................................................................................................15 9.2.9 RC OSC Register II (Address: 08h).............................................................................................................15 9.2.10 RC OSC Register III (Address: 09h)..........................................................................................................15 9.2.11 CKO Pin Control Register (Address: 0Ah) .................................................................................................15 9.2.12 GIO1 Pin Control Register I (Address: 0Bh)...............................................................................................16 9.2.13 GIO2 Pin Control Register II (Address: 0Ch) .............................................................................................18 9.2.14 Clock Register (Address: 0Dh)..................................................................................................................19 9.2.15 PLL Register I (Address: 0Eh)...................................................................................................................19 9.2.16 PLL Register II (Address: 0Fh)..................................................................................................................19 9.2.17 PLL Register III (Address: 10h) .................................................................................................................20 9.2.18 PLL Register IV (Address: 11h).................................................................................................................20 9.2.19 PLL Register V (Address: 12h) ...............................................................................................................20 9.2.20 Channel Group Register I (Address: 13h)..................................................................................................20 9.2.21 Channel Group Register II (Address: 14h).................................................................................................20 9.2.22 TX Register I (Address: 15h).....................................................................................................................21 9.2.23 TX Register II (Address: 16h)....................................................................................................................21 9.2.24 Delay Register I (Address: 17h) ................................................................................................................21 9.2.25 Delay Register II (Address: 18h) ...............................................................................................................22 9.2.26 RX Register (Address: 19h) ......................................................................................................................22 9.2.27 RX Gain Register I (Address: 1Ah)............................................................................................................23 9.2.28 RX Gain Register II (Address: 1Bh)...........................................................................................................23 9.2.29 RX Gain Register III (Address: 1Ch) .........................................................................................................23 9.2.30 RX Gain Register IV (Address: 1Dh) .........................................................................................................24 9.2.31 RSSI Threshold Register (Address: 1Eh) ..................................................................................................24 9.2.32 ADC Control Register (Address: 1Fh)........................................................................................................24 9.2.33 Code Register I (Address: 20h).................................................................................................................24 9.2.34 Code Register II (Address: 21h)................................................................................................................25 9.2.35 Code Register III (Address: 22h)...............................................................................................................25 9.2.36 IF Calibration Register I (Address: 23h).....................................................................................................25 9.2.37 IF Calibration Register II (Address: 24h)....................................................................................................26 9.2.38 VCO current Calibration Register (Address: 25h).......................................................................................26 9.2.39 VCO band Calibration Register I (Address: 26h)........................................................................................26 9.2.40 VCO band Calibration Register II (Address: 27h).......................................................................................27 9.2.41 VCO Deviation Calibration Register I (Address: 28h) .................................................................................27 9.2.42 VCO Deviation Calibration Register II (Address: 29h) ................................................................................27 9.2.43 DASP0 (Address: 2Ah, Page 0 by AGT [3:0]=0) ........................................................................................28 9.2.43 DASP1 (Address: 2Ah, Page 1 by AGT[3:0]=1) .........................................................................................28 Mar., 2013, Version 1.0 2 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver A M IC C O M C O N FI D EN TI A L 9.2.43 DASP2 (Address: 2Ah, Page 2 by AGT[3:0]=2) .........................................................................................28 9.2.43 DASP3 (Address: 2Ah, Page 3 by AGT[3:0]=3) .........................................................................................29 9.2.43 DASP4 (Address: 2Ah, Page 4 by AGT[3:0]=4) .........................................................................................29 9.2.43 DASP5 (Address: 2Ah, Page 5 by AGT[3:0]=5) .........................................................................................29 9.2.43 DASP6 (Address: 2Ah, Page 6 by AGT[3:0]=6) .........................................................................................29 9.2.43 DASP7 (Address: 2Ah, Page 7 by AGT[3:0]=7) .........................................................................................29 9.2.44 VCO Modulation Delay Register (Address: 2Bh)........................................................................................29 9.2.45 Battery detect Register (Address: 2Ch) .....................................................................................................30 9.2.46 TX test Register (Address: 2Dh) ...............................................................................................................30 9.2.47 Rx DEM test Register I (Address: 2Eh) .....................................................................................................30 9.2.48 Rx DEM test Register II (Address: 2Fh).....................................................................................................31 9.2.49 Charge Pump Current Register I (Address: 30h) .......................................................................................31 9.2.50 Charge Pump Current Register II (Address: 31h).......................................................................................31 9.2.51 Crystal test Register (Address: 32h)..........................................................................................................31 9.2.52 PLL test Register (Address:33h) ...............................................................................................................32 9.2.53 VCO test Register I (Address:34h)............................................................................................................32 9.2.54 RF Analog Test Register (Address: 35h)....................................................................................................32 9.2.55 AES Key data Register (Address: 36h)......................................................................................................33 9.2.56 Channel Select Register (Address: 37h)....................................................................................................33 9.2.57 ROMP0 (Address: 38h, Page 0 by AGT[3:0]=0).........................................................................................33 9.2.57 ROMP1 (Address: 38h, Page 1 by AGT[3:0]=1).........................................................................................33 9.2.57 ROMP2 (Address: 38h, Page 2 by AGT[3:0]=2).........................................................................................34 9.2.57 ROMP3 (Address: 38h, Page 3 by AGT[3:0]=3).........................................................................................34 9.2.57 ROMP4 (Address: 38h, Page 4 by AGT[3:0]=4).........................................................................................34 9.2.58 Data Rate Clock Register (Address: 39h) ..................................................................................................34 9.2.59 FCR Register (Address: 3Ah) ...................................................................................................................34 9.2.60 ARD Register (Address: 3Bh) ...................................................................................................................35 9.2.61 AFEP Register (Address: 3Ch)..................................................................................................................35 9.2.62 FCB Register (Address: 3Dh) ...................................................................................................................35 9.2.63 KEYC Register (Address: 3Eh) .................................................................................................................36 9.2.64 USID Register (Address: 3Fh) ..................................................................................................................36 10. SPI...............................................................................................................................................錯誤! 尚未定義書籤。 10.1 SPI Format ........................................................................................................................................................38 10.2 SPI Timing Characteristic ...................................................................................................................................38 10.3 SPI Timing Chart................................................................................................................................................39 10.3.1 Timing Chart of 3-wire SPI........................................................................................................................39 10.3.2 Timing Chart of 4-wire SPI........................................................................................................................39 10.4 Strobe Commands .............................................................................................................................................40 10.4.1 Strobe Command - Sleep Mode ................................................................................................................40 10.4.2 Strobe Command - ldle Mode ...................................................................................................................40 10.4.3 Strobe Command - Standby Mode ............................................................................................................41 10.4.4 Strobe Command - PLL Mode...................................................................................................................41 10.4.5 Strobe Command - RX Mode....................................................................................................................42 10.4.6 Strobe Command - TX Mode ....................................................................................................................42 10.4.7 Strobe Command – FIFO Write Pointer Reset ...........................................................................................42 10.4.8 Strobe Command – FIFO Read Pointer Reset ...........................................................................................43 10.4.9 Strobe Command – Deep Sleep Mode ......................................................................................................43 10.5 Reset Command................................................................................................................................................44 10.6 ID Accessing Command .....................................................................................................................................44 10.6.1 ID Write Command...................................................................................................................................44 10.6.2 ID Read Command ..................................................................................................................................45 10.7 FIFO Accessing Command.................................................................................................................................45 10.7.1 TX FIFO Write Command .........................................................................................................................45 10.7.2 Rx FIFO Read Command.........................................................................................................................46 11. State machine.............................................................................................................................................................47 11.1 Key states..........................................................................................................................................................47 11.2 FIFO mode ........................................................................................................................................................48 11.3 Direct mode .......................................................................................................................................................49 12. Crystal Oscillator ........................................................................................................................................................52 Mar., 2013, Version 1.0 3 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver A M IC C O M C O N FI D EN TI A L 12.1 Use External Crystal ..........................................................................................................................................52 12.2 Use External Clock ............................................................................................................................................52 13. System Clock .............................................................................................................................................................53 13.2 Data Rate Setting ..............................................................................................................................................53 14. Transceiver LO Frequency..........................................................................................................................................54 14.1 LO Frequency Setting ........................................................................................................................................54 14.2 IF Side Band Select ...........................................................................................................................................55 14.2.1 Auto IF Exchange.....................................................................................................................................56 14.2.2 Fast Exchange.........................................................................................................................................57 14.3 Auto Frequency Compensation...........................................................................................................................58 15. Calibration..................................................................................................................................................................58 15.1 Calibration Procedure ........................................................................................................................................58 16. FIFO (First In First Out)...............................................................................................................................................59 16.1 TX Packet Format in FIFO mode ........................................................................................................................59 16.1.1 Basic FIFO mode .....................................................................................................................................59 16.1.2 Advanced FIFO mode...............................................................................................................................59 16.2 Bit Stream Process in FIFO mode.......................................................................................................................60 16.3 Transmission Time.............................................................................................................................................61 16.4 Usage of TX and RX FIFO .................................................................................................................................61 16.4.1 Easy FIFO ...............................................................................................................................................62 16.4.2 Segment FIFO .........................................................................................................................................63 16.4.3 FIFO Extension........................................................................................................................................65 17. ADC (Analog to Digital Converter) ...............................................................................................................................69 17.1 RSSI Measurement............................................................................................................................................69 17.2 Internal thermal sensor (temperature) measurement ...........................................................................................71 17.3 External voltage input measurement...................................................................................................................71 18. Battery Detect ............................................................................................................................................................72 19. Auto-ack and auto-resend ...........................................................................................................................................73 19.1 Basic FIFO plus auto-ack auto-resend................................................................................................................73 19.2 Advanced FIFO plus auto-ack and auto-resend...................................................................................................73 19.3 WTR Behavior during auto-ack and auto-resend .................................................................................................75 19.6 Examples of auto-ack and auto-resend...............................................................................................................76 20. RC Oscillator ..............................................................................................................................................................78 20.1 WOR Function...................................................................................................................................................78 20.2 TWOR Function .................................................................................................................................................79 21. AES128 Security Packet .............................................................................................................................................79 22. Application circuit........................................................................................................................................................80 22.1 MD7130-A01 .....................................................................................................................................................80 22.2 MD7130-F07 .....................................................................................................................................................81 23. Abbreviations..............................................................................................................................................................82 24. Ordering Information...................................................................................................................................................82 25. Package Information...................................................................................................................................................83 26. Top Marking Information..............................................................................................................................................84 27. Reflow Profile .............................................................................................................................................................85 28. Tape Reel Information.................................................................................................................................................86 29. Product Status............................................................................................................................................................87 Mar., 2013, Version 1.0 4 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 1. General Description A7130 is a high performance and low cost 2.4GHz ISM band wireless transceiver. This device integrates both high sensitivity receiver (- 88dBm @4Mbps) and programmable power amplifier (-17 ~ 5dBm). Based on Data Rate Register (39h), user can configure on-air data rates to 4Mbps. EN TI A L A7130 supports fast settling time (90 us) for frequency hopping system. For packet handling, A7130 has built-in separated 64-bytes TX/RX FIFO (could be logically extended to 4K bytes) for data buffering and burst transmission, auto-ack and auto-resend, CRC for error packet filtering, FEC for 1-bit data correction per code word, RSSI for clear channel assessment, thermal sensor for monitoring relative temperature, WOR (Wake on RX) function to support periodically wake up from sleep mode to RX mode and listen for incoming packets without MCU interaction, data whitening for data encryption / decryption. In addition, A7130 has built-in AES128 co-processor (Advanced Encryption Standard) for advanced data encryption and decryption which consists of the transformation of a 128-bit block into an encrypted 128-bit block. Those functions are very easy to use while developing a wireless system. All features are integrated in a small QFN 4X4 20 pins package. FI D A7130’s control registers are accessed via 3-wire or 4-wire SPI interface such as TX/RF FIFO, ID register, RSSI value, frequency hopping to chip calibration procedures. Another one, via SPI as well, is the unique Strobe command, A7130 can be controlled from power saving mode (deep sleep, sleep, idle, standby), PLL mode, TX mode and RX mode. The other connections between A7130 and MCU are GIO1 and GIO2 (multi-function GPIO) to output A7130’s status so that MCU could use either polling or interrupt scheme for radio control. Overall, this device is very easy-to-use for developing a wireless application with a MCU. 3. Feature M O C A M n n n n n n n n Small size (QFN4 X4, 20 pins). Frequency band: 2400 ~ 2483.5MHz. FSK or GFSK modulation Low current consumption: RX 27mA (4Mbps), TX 29mA (at 5dBm output power). Deep sleep current (0.1 uA). Sleep current (2.5 uA). On chip regulator, support input voltage 2.0 ~ 3.6 V. Data rate 4Mbps. Programmable TX power level from – 17 dBm to 5 dBm. Ultra High sensitivity: u -88dBm at 4Mbps on-air data rate. Fast settling time (90 us) synthesizer for frequency hopping system. On chip low power RC oscillator for WOR (Wake on RX) function. Built-in AES128 co-processor AGC (Auto Gain Control) for the wide RSSI dynamic range. AFC (Auto Frequency Compensation) for frequency drift due to temperature. Support low cost crystal (16 / 18 MHz). Low Battery Detector indication. Easy to use. u Support 3-wire or 4-wire SPI. u Unique Strobe command via SPI. u ONE register setting for new channel frequency. u CRC Error Packet Filtering. u Auto-acknowledgement and auto-resend. u Dynamic FIFO length. u 8-bits RSSI measurement for clear channel indication. u Auto Calibrations. IC n n n n n n n n n n n 2400 ~ 2483.5 MHz ISM system n Wireless metering and building automation n Wireless toys and game controllers C O n 2.4GHz video baby monitor n 2.4GHz PC peripherals n HiFi quality wireless audio streaming N 2. Typical Applications Mar., 2013, Version 1.0 1 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver u u u u u u Auto IF function. Auto FEC by (7, 4) Hamming code (1 bit error correction / code word). Separated 64 bytes RX and TX FIFO. Easy FIFO / Segment FIFO / FIFO Extension (up to 4K bytes). Support FIFO mode frame sync to MCU. Support direct mode with recovery clock output to MCU. GIO1 16 TI A GIO2 17 EN CKO 18 SDIO 13 VDD_D FI D 14 11 SCS 10 V_PLL CP C O SCK M V_VCO 12 XO 5 GND 9 RFC N 4 15 XI RFO 8 3 6 RFI REGI 2 19 BP_BG 7 1 VDD_A RSSI 20 L 4. Pin Configurations A M IC C O Fig 4-1. A7130 QFN 4x4 Package Top View Mar., 2013, Version 1.0 6 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 5. Pin Description (I: input; O: output, I/O: input or output) Pin No. Symbol I/O Function Description 1 RSSI O 2 BP_BG O Connected to a bypass capacitor for internal Regulator bias point. 3 RFI I LNA input. Connected to matching circuit. 4 RFO O PA input. Connected to matching circuit. 5 RFC I RF Choke input. Connected to matching circuit. 6 V_VCO I VCO supply voltage input. 7 CP O Charge-pump. Connected to loop filter. 8 V_PLL I PLL supply voltage input. 9 XI I Crystal oscillator input. 10 XO O Crystal oscillator output. 11 SCS I SPI chip select. 12 SCK I SPI clock input pin. 13 VDD_D I Connected to a bypass capacitor to supply voltage for digital part. 14 SDIO I/O SPI read/write data. 15 GND G Ground 16 GIO1 I/O Multi-function GIO1 / 4-wire SPI data output. 17 GIO2 I/O 18 CKO O Multi-function GIO2 / 4-wire SPI data output. Multi-function clock output. 19 REGI I 20 VDD_A O Back side plate G C O N FI D EN TI A L Connected to a bypass capacitor for RSSI. Regulator input (External Power Input) Internal Regulator output to supply V_VCO (pin 6), V_PLL (pin 8) and RFC (pin 5). A M IC C O M Ground. Back side plate shall be well-solder to ground; otherwise, it will impact RF performance. Mar., 2013, Version 1.0 5 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver Fig 6-1. A7130 Block Diagram A M IC C O M C O N FI D EN TI A L 6. Chip Block Diagram Mar., 2013, Version 1.0 6 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 7. Absolute Maximum Ratings Parameter With respect to Rating Unit GND -0.3 ~ 3.6 V Digital IO pins range GND -0.3 ~ VDD+0.3 V Voltage on the analog pins range GND -0.3 ~ 2.1 TI A Input RF level Storage Temperature range ESD Rating L Supply voltage range (VDD) HBM 10 dBm -55 ~ 125 °C ± 2K V ± 100 V EN MM V FI D *Stresses above those listed under “Absolute Maximum Rating” may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. A M IC C O M C O N *Device is ESD sensitive. Use appropriate ESD precautions. HBM (Human Body Mode) is tested under MIL-STD-883F Method 3015.7. MM (Machine Mode) is tested under JEDEC EIA/JESD22-A115-A. *Device is Moisture Sensitivity Level III (MSL 3). Mar., 2013, Version 1.0 7 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 8. Electrical Specification (Ta=25℃, VDD=3.3V, FXTAL =16MHz, with Match circuit and low pass filter, On Chip Regulator = 1.8V, unless otherwise noted.) Parameter Description Min. Type Max. Unit -40 Supply Voltage (VDD) with internal regulator 2.0 Current Consumption Deep Sleep mode* (No registers retention) Current Consumption Sleep mode (WOR off) * 1 1 Sleep mode (WOR on) * 1 C O N FI D Idle Mode (Regulator on) * Standby Mode (XOSC on, CLK Gen. on) PLL mode RX Mode (4Mbps) TX Mode (5dBm) TX Mode (3dBm) TX Mode (0dBm) TX Mode ( -5dBm) TX Mode ( -17dBm) PLL block 2 Idle to standby (Xtal osc. is stable at 20ppm) Idle to standby (Xtal osc. is stable at 10ppm) Data rate: 4Mbps Data rate: 4M/bps Crystal start up time* M (3225 SMD type) IC C O Crystal frequency Crystal tolerance Crystal ESR VCO Operation Frequency PLL phase noise 3 M PLL settling time* 3.6 mA 2.5 mA 3.5 mA 0.3 mA 2.7 mA 12.5 27 29 24 20 18 16 mA mA mA mA mA mA mA 1 ms 2 ms 16 ±50 MHz ppm ohm MHz dBc 80 2483.5 2400 75 90 100 30 Offset 10k Offset 500K Offset 1M Loop filter based on app. circuit. (Standby to PLL) °C V 0.1 EN 1 (DBL =0 at 0Fh, bit7) 85 3.3 TI A Operating Temperature L General mS A Transmitter Output power range -17 4 Out Band Spurious Emission * 5 Frequency deviation* Data rate 6 TX ready time* 30MHz~1GHz 0 5 -36 dBm dBm 1GHz~12.75GHz 1.8GHz~ 1.9GHz 5.15GHz~ 5.3GHz -30 -47 -47 dBm dBm dBm Data rate 4Mbps ±1M Hz 4M 90 bps Standby to TX -88 dBm mS Receiver Receiver sensitivity Mar., 2013, Version 1.0 Data rate 4Mbps 8 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver Data rate 4Mbps (GFSK) IFS = [11], 4Mbps IFS = [11], 4Mbps Co-Channel (C/I0) 7 Interference * (4Mbps , IF = 4MHz) -85 4.8M 4M 11 Hz Hz dB ±4MHz Adjacent Channel 0 dB ±8MHz Adjacent Channel - 10 dB ±12MHz Adjacent Channel - 20 dB ±16MHz Adjacent Channel - 30 TI A IF Filter bandwidth IF center frequency @RF input (BER=0.1%) 30MHz~1GHz 1GHz~12.75GHz AGC = 0 AGC = 1 4 RX Spurious Emission * RSSI Range -95 -95 FI D RX Ready Time - 10 EN Image (C/IIM) Maximum Operating Input Power Regulator Regulator settling time Pin 2 connected to 470pF. (Sleep to idle). N Band-gap reference voltage Regulator output voltage C O Digital IO DC characteristics High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Output Voltage (VOH) Low Level Output Voltage (VOL) 1.79 0.8*VDD 0 VDD-0.4 0 5 -57 -47 -50 -20 dB dB dBm dBm 80 dBm dBm ms 0.5 ms 1.28 1.8 2.3 V V VDD 0.2*VDD VDD 0.4 V V V V M @IOH= -0.5mA @IOL= 0.5mA L @ BER = 0.1% A M IC C O Note 1: When digital I/O pins are configured as input, those pins shall NOT be floating but pull either high or low (SCS shall be pulled high only); otherwise, leakage current will be induced. Note 2: Xtal settling time is depend on Xtal package type, Xtal ESR and Xtal Cm. Note 3: Refer to Delay Register I (17h) to set PDL (PLL settling delay). Note 4: With external RF filter that provides minimum 17dB of attenuation in the band: 30MHz ~ 2GHz and 3GHz ~12.75GHz. Note 5: Refer to TX Register II (16h) to set FD [7:0]. Note 6: Refer to Delay Register I (17h) to set PDL and TDL. Note 7: The wanted signal is set above sensitivity level +3dB. The modulation data of wanted signal and interferer are PN9 and PN15, respectively. Mar., 2013, Version 1.0 9 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 9. Control Register 9.1 Control register table R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 W R W R RESETN HECF DDPC DDPC RESETN FECF ARSSI ARSSI RESETN CRCF AIF AIF RESETN CER DFCD CD RESETN XER WORE WORE R/W -- -- -- VCC W R W R --FEP7 LENF7 --FEP6 LENF6 --FEP5 LENF5 --FEP4 LENF4 W FPM1 FPM0 PSA5 R/W FIFO7 FIFO6 FIFO5 R/W ID7 ID6 ID5 W R WOR_SL7 RCOC7 WOR_SL6 RCOC6 WOR_SL5 RCOC5 W WOR_SL9 WOR_SL8 WOR_AC5 WOR_AC4 WOR_AC3 WOR_AC2 WOR_AC1 WOR_AC0 W RTCS RCOT2 RCOT1/ RTCC1 RCOT0/ RTCC0 CALWC RCOSC_E TSEL TWORE R -- -- -- -- CALWR -- -- -- CKOE SCKI GIO1I GIO1OE GIO2I GIO2OE CGS -- XS -- CHN1 CHN0 CHR0 CHR0 BIP8 IP8 BIP1 BIP0 IP1 BFP9 AC9-FP9 BFP1 AC1-FP1 IP0 BFP8 AC8-FP8 BFP0 AC0-FP0 CHGL1 CHGL0 CHGH1 CHGH0 09h RC OSC III Bit 1 Bit 0 RESETN PLLER FMT FMT RESETN TRSR FMS FMS RESETN TRER ADCM ADCM VBC VDC FBC RSSC FEP11 LENF11 FEP3 LENF3 FEP10 LENF10 FEP2 LENF2 FEP9 LENF9 FEP1 LENF1 FEP8 LENF8 FEP0 LENF0 PSA3 PSA2 PSA1 PSA0 FIFO3 FIFO2 FIFO1 FIFO0 ID4 ID3 ID2 ID1 ID0 WOR_SL4 RCOC4 WOR_SL3 RCOC3 WOR_SL2 RCOC2 WOR_SL1 RCOC1 WOR_SL0 RCOC0 FI D EN Bit 2 N PSA4 FIFO4 C O 04h FIFO II 05h FIFO Data 06h ID Data 07h RC OSC I 08h RC OSC II M 03h FIFO I O Address / Name 00h Mode 01h Mode control 02h Calc TI A L A7130 contains 69 control registers. MCU can access those control registers via 3-wire (SCS, SCK, SDIO) or 4-wire (SCS, SCK, SDIO, GIO1/GIO2) SPI interface (max. 15 Mbps). Please refer to Chapter 10 for SPI timing. In general, most of control registers are just need to configure the recommended values based on A7130 reference code. A M IC C 0Ah W ECKOE CKOS3 CKOS2 CKOS1 CKOS0 CKOI CKO Pin 0Bh W VKM VPM GIO1S3 GIO1S2 GIO1S1 GIO1S0 GPIO1 Pin I 0Ch W BBCKS1 BBCKS0 GIO2S3 GIO2S2 GIO2S1 GIO2S0 GPIO2 Pin II W CGC1 CGC0 GRC3 GRC2 GRC1 GRC0 0Dh Clock R IFS1 IFS0 GRC3 GRC2 GRC1 GRC0 0Eh CHN7 CHN6 CHN5 CHN4 CHN3 CHN2 R/W PLL I W DBL RRC1 RRC0 CHR3 CHR2 CHR1 0Fh R DBL RRC1 RRC0 CHR3 CHR2 CHR1 PLL II 10h W BIP7 BIP6 BIP5 BIP4 BIP3 BIP2 PLL III R IP7 IP6 IP5 IP4 IP3 IP2 W BFP15 BFP14 BFP13 BFP12 BFP11 BFP10 11h PLL IV R FSYN-FP15 AC14-FP14 AC13-FP13 AC12-FP12 AC11-FP11 AC10-FP10 W BFP7 BFP6 BFP5 BFP4 BFP3 BFP2 12h PLL V R AC7-FP7 AC6-FP6 AC5-FP5 AC4-FP4 AC3-FP3 AC2-FP2 13h R/W CHGL7 CHGL6 CHGL5 CHGL4 CHGL3 CHGL2 Channel Group I 14h R/W CHGH7 CHGH6 CHGH5 CHGH4 CHGH3 CHGH2 Channel Group II Mar., 2013, Version 1.0 Corporation 10 AMICCOM Electronics A7130 2.4GHz FSK/GFSK Security Transceiver GDR GF TMDE TXDI TME FDP2 FDP1 FDP0 W FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 W DPR2 DPR1 DPR0 TDL1 TDL0 PDL2 PDL1 PDL0 W WSEL2 WSEL1 WSEL0 RSSC_D1 RSSC_D0 RS_DLY2 RS_DLY1 RS_DLY0 W LNAGE AGCE RXSM1 RXSM0 AFCE RXDI W R W R W R PRS -RSAGC1 RH7 -RL7 MIC MICR RSAGC0 RH6 RDU RL6 IGC1 IGCR1 VTL2 RH5 IFS1 RL5 IGC0 IGCR0 VTL1 RH4 IFS0 RL4 MGC1 MGCR1 VTL0 RH3 RSM1 RL3 W LIMC IFBC1 IFBC0 IFAS RTH5 ADC6 ADC5 W AVSEL1 AVSEL0 MVSEL1 W MCS WHTS FECS W MSCRC EDRL HECS W CRCINV WS6 WS5 W R W R HFR -PWORS -- CKGS1 -- W R W TI A ULS MHC0 LGC1 LGCR1 VTH1 RH1 RL1 LGC0 LGCR0 VTH0 RH0 RSS RL0 LHC1 LHC0 ERSSM RTH2 RTH1 RTH0 ADC3 ADC2 ADC1 ADC0 MVSEL0 RADC FSARS XADS CDM CRCS IDL1 IDL0 PML1 PML0 ETH1 ETH0 PMD1 PMD0 WS4 WS3 WS2 WS1 WS0 CKGS0 -- MFBS FBCF MFB3 FB3 MFB2 FB2 MFB1 FB1 MFB0 FB0 TRT2 TRT1 TRT0 ASMV2 ASMV1 ASMV0 AMVS -- -- FCD4 FCD3 FCD2 FCD1 FCD0 ROSCS RSIS VCRLS MVCS VCOC3 VCOC2 VCOC1 VCOC0 -- -- -- VCCF VCB3 VCB2 VCB1 VCB0 DCD1 DCD0 DAGS CWS MVBS MVB2 MVB1 MVB0 - - - - VBCF VB2 VB1 VB0 MDAG7 MDAG6 MDAG5 MDAG4 MDAG3 MDAG2 MDAG1 MDAG0 ETH2 C O M C R RTH3 DMG ADC4 O W RTH4 MGC0 MGCR0 VTH2 RH2 RSM0 RL2 EN RTH6 ADC7 FI D RTH7 R N W MHC1 L W IC 15h TX I 16h TX II 17h Delay I 18h Delay II 19h RX 1Ah RX Gain I 1Bh RX Gain II 1Ch RX Gain III 1Dh RX Gain IV 1Eh RSSI Threshold 1Fh ADC Control 20h Code I 21h Code II 22h Code III 23h IF Calibration I 24h IF Calibration II 25h VCO current Calibration 26h VCO band Calibration I 27h VCO band Calibration II 28h VCO deviation Calibration I 29h VCO deviation Calibration II 2Ah DASP0 ADAG7 ADAG6 ADAG5 ADAG4 ADAG3 ADAG2 ADAG1 ADAG0 W DEVS3 DEVS2 DEVS1 DEVS0 DAMR_M VMTE_M VMS_M MSEL R DEVA7 DEVA6 DEVA5 DEVA4 DEVA3 DEVA2 DEVA1 DEVA0 W MVDS MDEV6 MDEV5 MDEV4 MDEV3 MDEV2 MDEV1 MDEV0 R ADEV7 ADEV6 ADEV5 ADEV4 ADEV3 ADEV2 ADEV1 ADEV0 W QLIM RFSP INTRC (CSXTL5) CSXTL4 CSXTL3 CSXTL2 CSXTL1 CSXTL0 DASP1 W STS CELS RGS RGC1 RGC0 VRPL1 VRPL0 INTPRC DASP2 W VTRB3 VTRB2 VTRB1 VTRB0 VMRB3 VMRB2 VMRB1 VMRB0 DASP3 W DCV7 DCV6 DCV5 DCV4 DCV3 DCV2 DCV1 DCV0 W VMG7 VMG6 VMG5 VMG4 VMG3 VMG2 VMG1 VMG0 R VMG7 VMG6 VMG5 VMG4 VMG3 VMG2 VMG1 VMG0 W -- -- PKT1 PKT0 PKS PKIS1 PKIS0 IFPK A M R DASP4 DASP5 Mar., 2013, Version 1.0 11 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver W -- HPLS HRS PACTL IWS CNT MXD LXD W DMV1 DMV0 DEVFD2 DEVFD1 DEVFD0 DEVD2 DEVD1 DEVD0 2Ch Battery detect W LVR RGV1 RGV0 QDS BVT2 BVT1 BVT0 BD_E R -- RGV1 RGV0 BDF BVT2 BVT1 BVT0 BD_E RMP0 TXCS PAC1 PAC0 TBG2 TBG1 DCM1 DCM0 MLP1 MLP0 DCH0 DCL2 DCL1 DCL0 CPM2 CPM1 CPM0 CPT3 CPTX2 CPTX1 CPTX0 CPS CPH OLM PRIC1 DEVGD1 DEVGD0 AGT2 AGT1 TI A SLF1 SLF0 RAW CDTM1 CDTM0 CPT2 CPT1 CPT0 CPRX2 CPRX1 CPRX0 EN SLF2 FI D DBD XCC XCP1 XCP0 PRIC0 PRRC1 PRRC0 SDPW NSDO TLB1 TLB0 RLB1 RLB0 VBS AGT0 RFT3 RFT2 RFT1 RFT0 C O N CPCS KEY5 KEY4 KEY3 KEY2 KEY1 KEY0 CHI2 CHI1 CHI0 CHD3 CHD2 CHD1 CHD0 EPRG MIGS MRGS MRSS MTMS MADS MBGS MPA1 PTM0 -STMP MPA0 CTR5 FBG4 CTR4 FBG3 CTR3 FBG2 CTR2 FBG1 CTR1 FBG0 CTR0 CRS2 CRS1 CRS0 CTS2 CTS1 CTS0 STM5 STM4 STM3 STM2 STM1 STM0 SDR6 SDR5 SDR4 SDR3 SDR2 SDR1 SDR0 FCL0 VPOAK ARC3 RCR3 ARC2 RCR2 ARC1 RCR1 ARC0 RCR0 EACKS EACKS EARTS EARTS ARD6 ARD5 ARD4 ARD3 ARD2 ARD1 ARD0 SPSS -- ACKFEP5 EARTS ACKFEP4 EARTS ACKFEP3 EARTS ACKFEP2 TXSID2 ACKFEP1 TXSID1 ACKFEP0 TXSID0 F6 F5 F4 F3 F2 F1 F0 AFIDS ARTMS MIDS AESS -- AKFS EDCRS RND6 RND5 RND4 RND3 RND2 RND1 RND0 O C IC M A Mar., 2013, Version 1.0 CPRX3 TBG0 KEY6 M 2Dh W RMP1 TX test 2Eh W DMT Rx DEM test I 2Fh DCH1 W Rx DEM test II 30h W CPM3 Charge Pump Current I 31h W CPTX3 Charge Pump Current II 32h W CDPM Crystal test 33h W MDEN PLL test 34h DEVGD2 W VCO test 35h AGT3 W RF Analog test 36h KEY7 W/R Key Data 37h W CHI3 Channel Select 38h W MPOR ROM_P0 ROMP1 W APG ROMP2 W PTM1 ROMP3 W -ROMP4 W -39h W SDR7 Data Rate CLK W FCL1 3Ah FCR R ARTEF 3Bh W ARD7 ARD W EACKF 3Ch AFEP R -3Dh W/R F7 FCB 3Eh W MEDCS KEYC 3Fh W RND7 USID Legend: -- = unimplemented L DASP6 2Bh VCO modulation Delay 12 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 9.2 Control register description 9.2.1 Mode Register (Address: 00h) R/W Mode R W Bit 7 Bit 6 HECF FECF RESETN RESETN Bit 5 Bit 4 CRCF RESETN CER RESETN Bit 3 XER RESETN Bit 2 PLLER RESETN RESETN: Write to this register by 0x00 to issue reset command, then it is auto clear Bit 0 TRER RESETN TI A HECF: Head Control Flag. (HECF will be clear after issue a strobe command.) HEC is CRC-8 result for the optional Packet Header (Please refer to chapter 16 for details) [0]: HEC pass. [1]: HEC error. Bit 1 TRSR RESETN L Name EN FECF: FEC flag. (FECF will be clear after issue any strobe command.) [0]: FEC pass. [1]: FEC error. CRCF: CRC flag. (CRCF will be clear after issue any strobe command.) [0]: CRC pass. [1]: CRC error. FI D CER: RF chip enable status. [0]: RF chip is disabled. [1]: RF chip is enabled. XER: Internal crystal oscillator enabled status. [0]: Crystal oscillator is disabled. [1]: Crystal oscillator is enabled. TRSR: TRX Status Register. [0]: RX state. [1]: TX state. Serviceable if TRER=1 (TRX is enable). (Address: 01h) M 9.2.2 Mode Control Register C O TRER: TRX state enabled status. [0]: TRX is disabled. [1]: TRX is enabled. N PLLE: PLL enabled status. [0]: PLL is disabled. [1]: PLL is enabled. R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mode Control I R W DDPC DDPC ARSSI ARSSI AIF AIF DFCD CD WORE WORE FMT FMT FMS FMS ADCM ADCM O Name C DDPC (Direct mode data pin control): Direct mode modem data can be accessed via SDIO pin. [0]: Disable. [1]: Enable. IC ARSSI: Auto RSSI measurement while entering RX mode. [0]: Disable. [1]: Enable. M AIF (Auto IF Offset): RF LO frequency will auto offset one IF frequency while entering RX mode. [0]: Disable. [1]: Enable. A CD: Carrier detector (Read only). [0]: Input power below threshold. [1]: Input power above threshold. DFCD: Data Filter by CD : The received packet would be filtered if the input power level is below RTH (1Eh). [0]: Disable. [1]: Enable. WORE: WOR (Wake On RX) Function Enable. [0]: Disable. [1]: Enable. FMT: Reserved for internal usage only. Shall be set to [0]. FMS: Direct/FIFO mode select. [0]: Direct mode. [1]: FIFO mode. ADCM: ADC measurement enable (Auto clear when done). [0]: Disable measurement or measurement finished. [1]: Enable measurement. Refer to chapter 17 for details. Mar., 2013, Version 1.0 13 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 9.2.3 Calibration Control Register (Address: 02h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mode Control II R/W -- -- -- VCC VBC VDC FBC RSSC VCC: VCO Current calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. L VBC: VCO Bank calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. TI A VDC: VCO Deviation calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. FBC: IF Filter Bank calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. EN RSSC: RSSI calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. 9.2.4 FIFO Register I (Address: 03h) R/W Bit 15 Bit 14 Bit 13 Bit 12 FIFO I W R W R --FEP7 LENF7 --FEP6 LENF6 --FEP5 LENF5 --FEP4 LENF4 Bit 11 FI D Name Bit 10 Bit 9 Bit 8 FEP9 LENF9 FEP1 LENF1 FEP8 LENF8 FEP0 LENF0 N FEP11 FEP10 LENF11 LENF10 FEP3 FEP2 LENF3 LENF2 C O FEP [11:0]: FIFO End Pointer for TX FIFO and Rx FIFO. Data Sequence is FEP[7:0] and FEP[15:8]. Please refer to chapter 16 for details. M LENF [11:0]: Received FIFO Length for dynamic FIFO function. (Ready Only) When EDRL =1, that means dynamic FIFO is enabled, MCU can read LENF [11:0] to know the RX FIFO length of the coming packet. Please refer to chapter 16 for details. Name R/W FIFO II Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 O 9.2.5 FIFO Register II (Address: 04h) FPM0 PSA5 PSA4 PSA3 PSA2 PSA1 PSA0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W FPM1 C FPM [1:0]: FIFO Pointer Margin IC PSA [5:0]: Used for Segment FIFO. Refer to chapter 16 for details. M 9.2.6 FIFO DATA Register (Address: 05h) R/W W R/W A Bit Name Bit 7 Bit 6 TX-FIFO[7:0] RX-FIFO[7:0] FIFO [7:0]: TX FIFO / RX FIFO TX FIFO and RX FIFO share the same address (05h). TX FIFO and RX FIFO are separated physical 64 Bytes. Refer to chapter 16 for details. 9.2.7 ID DATA Register (Address: 06h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID DATA R/W ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 ID [7:0]: ID data. When this address is accessed, ID Data is input or output sequential (ID Byte 0,1, 2 and 3) corresponding to Write or Read. Mar., 2013, Version 1.0 14 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver Recommend to set ID Byte 0 = 5xh or Axh. Refer to section 10.6 for details. 9.2.8 RC OSC Register I (Address: 07h) Name R/W RC OSC I R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 L RCOC7 RCOC6 RCOC5 RCOC4 RCOC3 RCOC2 RCOC1 RCOC0 WOR_SL7 WOR_SL6 WOR_SL5 WOR_SL4 WOR_SL3 WOR_SL2 WOR_SL1 WOR_SL0 9.2.9 RC OSC Register II (Address: 08h) Name R/W RC OSC II W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TI A RCOC [7:0]: Reserved for internal usage (read only). Bit 2 Bit 1 Bit 0 WOR_SL9 WOR_SL8 WOR_AC5 WOR_AC4 WOR_AC3 WOR_AC2 WOR_AC1 WOR_AC0 EN WOR_AC [5:0]: 6-bits WOR Active Timer for WOR and TWOR Function Active period = (WOR_AC+1) x (1/4092). Sleep period = (WOR_SL+1) x (1/32) x (1/4092). 9.2.10 RC OSC Register III (Address: 09h) RC OSC III Bit 7 W RTCS R -- Bit 6 RCOT2 Bit 5 Bit 4 N R/W RCOT1/ RTCC1 -- RCOT0/ RTCC0 -- C O Name FI D WOR_SL [9:0]: 10-bits WOR Sleep Timer for WOR and TWOR Function. WOR_SL [9:0] are from address (07h) and (08h), -- Bit 3 Bit 2 Bit 1 Bit 0 CALWC RCOSC_E TSEL TWORE CALWR -- -- -- RTCS: internal Oscillator selection in sleep mode. Recommend RTCS= [0]. [0]: RC oscillator. [1]: RTC oscillator. M RCOT[2:0]: Reserved for internal used. Recommend RCOT= [000]. O RCOT[1:0]: RCOSC current select for RC oscillator calibration. [00]: 240nA [01]: 280nA [10]: 320nA [11]: 360nA C TSEL: Timer select for TWOR function. [0]: Use WOR_AC. [1]: Use WOR_SL. IC CALWC: RC Oscillator Calibration Enable. [0]: Disable. [1]: Enable. CALWR: RC Oscillator Calibration ending indication. [0]: ending. [1]: Not ending. M RCOSC_E: RC-oscillator enable. [0]: Disable. [1]: Enable. A TSEL: Timer Duty select for TWOR function. [0]: Use WOR_AC. [1]: Use WOR_SL. TWORE: Enable TWOR function. [0]: WOR mode. [1]: TWOR mode. 9.2.11 CKO Pin Control Register (Address: 0Ah) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CKO Pin Control W ECKOE CKOS3 CKOS2 CKOS1 CKOS0 CKOI CKOE SCKI ECKOE: CKO pin Output Enable. [0]: Disable. [1]: Enable. CKOS [3:0]: CKO pin output select. Mar., 2013, Version 1.0 15 AMICCOM Electronics Corporation A7130 TI A EN [0000]: DCK (TX data clock) in TX mode, RCK (RX recovery clock) in RX mode. [0001]: DCK (TX data clock) in TX mode, RCK (RX recovery clock) in RX mode. [0010]: FPF (FIFO pointer flag). [0011]: EOP, EOVBC, EOFBC, EOVCC, EOVDC, RSSC_OK. (Internal usage only). [0100]: External clock output= FSYCK / 2. [0101]: External clock output / 2= FSYCK / 4. [0110]: RXD [0111]: FSYNC. [1000]: WCK. [1001]: PF8M.(8Mhz, internal usage) [1010]: ROSC. [1011]: MXDEC(SLF[0]=1:~OKADCN, SLF[1]=0: DEC , internal usage) [1100]: BDF (Battery Detect flag). [1101]: FSYCK .. [1110]: VPOAK. [1111]: WRTC (internal usage) L 2.4GHz FSK/GFSK Security Transceiver CKOE: CKO pin Output Enable. [0]: High Z. [1]: Enable. SCKI: SPI clock input invert. [0]: Non-inverted input. [1]: Inverted input. N 9.2.12 GIO1 Pin Control Register I (Address: 0Bh) FI D CKOI: CKO pin output signal invert. [0]: Non-inverted output. [1]: Inverted output. R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIO1 Pin Control I W VKM VPM GIO1S3 GIO1S2 GIO1S1 GIO1S0 GIO1I GIO1OE VPM: Valid Pulse width select. [0]: 20u. [1]: 40u. M VKM: Valid packet mode select. [0]: by event. [1]: by pulse. C O Name A M IC C O TX Mode (disable auto-resend, EAR=0). Mar., 2013, Version 1.0 16 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver FI D EN TI A L RX Mode (disable Auto-ack, EAK =0). C O N Note1, If auto-resend is enabled (EAR = 1), WTR behavior is different while it is output to GIO1 and GIO2. Note2, If auto-ack is enabled (EAK = 1), WTR behavior is different while it is output to GIO1 and GIO2. Note3, VPOAK’s behavior is controlled by VPM (0Bh) and VPW (0Bh). Refer to chapter 19 for details A M IC C O M GIO1S [3:0]: GIO1 pin function select. GIO1S [3:0] TX state RX state [0000] WTR (Wait until TX or RX finished) [0001] EOAC (end of access code) FSYNC (frame sync) [0010] TMEO (TX modulation enable) CD (carrier detect) [0011] Preamble Detect Output (PMDO) [0100] If RCOSC_E =1, output TWOR. If RCOSC_E =0, output CWTR signal. (internal usage) [0101] In phase demodulator input(DMII)or VT[0] (internal usage) [0110] SDO ( 4 wires SPI data out) [0111] TRXD In/Out (Direct mode) [1000] RXD (Direct mode) [1001] TXD (Direct mode) [1010] PDN_RX External FSYNC input in RX direct mode (internal usage) [1011] [1100] MXINC(SLF[0]=1:EOADC.SLF[1]=0:INC.) (internal usage) [1101] FPF [1110] VPOAK (Valid Packet or Auto ACK OK Output) [1111] FMTDO (internal usage) If GIO1S = [0100] and RCOSC_E = 0, CWTR is an internal signal to monitor TX/RX cycles of auto-ack and auto-resend.If GIO1S = [1011] and direct mode is selected, the internal frame sync function will be disabled. In such case, A7130 supports to accept an external frame sync signal from MCU to feed to GIO1 pin to determine the timing of fixing DC estimation voltage of demodulator. GIO1I: GIO1 pin output signal invert. [0]: Non-inverted output. [1]: Inverted output. GIO1OE: GIO1pin output enable. [0]: High Z. [1]: Enable. Mar., 2013, Version 1.0 17 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 9.2.13 GIO2 Pin Control Register II (Address: 0Ch) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIO2 Pin Control II W BBCKS1 BBCKS0 GIO2S3 GIO2S2 GIO2S1 GIO2S0 GIO2I GIO2OE BBCKS [1:0]: Clock select for digital block. Recommend BBCKS = [00]. [00]: FSYCK. [01]: FSYCK / 2. [10]: FSYCK / 4. [11]: FSYCK / 8. C O N FI D EN TI A L GIO2S [3:0]: GIO2 pin function select. GIO2S TX state RX state [0000] WTR (Wait until TX or RX finished) [0001] EOAC (end of access code) FSYNC (frame sync) [0010] TMEO (TX modulation enable) CD (carrier detect) [0011] Preamble Detect Output (PMDO) [0100] If RCOSC_E =1, output TWOR. If RCOSC_E =0, output CWTR signal. (internal usage) [0101] Quadrature phase demodulator input (DMIQ) (internal usage) [0110] SDO (4 wires SPI data out) [0111] TRXD In/Out (Direct mode) [1000] RXD (Direct mode) [1001] TXD (Direct mode) [1010] PDN_TX [1011] ROMOK(ROM Program OK) (internal usage) [1100] BDF (Battery Detect Flag) [1101] FPF [1110] VPOAK (Valid Packet or Auto ACK OK Output) [1111] DCK (internal usage) If GIO2S = [0100] and RCOSC_E = 0, CWTR is an internal signal to monitor TX/RX cycles of auto-ack and auto-resend. GIO2I: GIO2 pin output signal invert. [0]: Non-inverted output. [1]: Inverted output. M GIO2OE: GIO2 pin Output Enable. [0]: High Z. [1]: Enable. SPI (SCS,SCK,SDIO) TX-Strobe Auto Back PLL Mode Preamble + ID Code + Payload + CRC IC (Output) Next Instruction No Command Required 10 us + (PDL+TDL) C PLL Mode RF Port O In TX mode M GIO1 Pin - WTR (GIO1S[3:0]=0000) A GIO2 Pin - TMEO (GIO2S[3:0]=0010) 16 us PA Ramp Down T0 T2 T1 T3 < 1us In RX mode Mar., 2013, Version 1.0 18 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver SPI (SCS,SCK,SDIO) RX-Strobe Next Instruction No Command Required PLL Mode Auto Back PLL Mode 10us+PDL+TDL RF Port (Input) Preamble + ID Code + Payload + CRC L GIO1 Pin - WTR (GIO1S[3:0]=0000) TI A GIO2 Pin - FSYNC (GIO2S[3:0]=0001) T0 EN ID-Matched T2 T1 9.2.14 Clock Register (Address: 0Dh) R/W Bit 7 Bit 6 Bit 5 Clock W R CGC1 IFS1 CGC0 IFS0 GRC3 GRC3 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GRC2 GRC2 GRC1 GRC1 GRC0 GRC0 CGS -- XS -- N Name FI D < 1us CGC [1:0]: Clock Gen. Current select. Shall be set to [10]. C O GRC [3:0]: Clock generation reference counter. Recommend GRC = [0111] for 16MHz Xtal. GRC [3:0] is used to let below formula be true when CGS = 1. FXTAL x (DBL+1) / (GRC+1) = 2MHz. M CGS: Clock generator enable. Recommend CGS = [1] [0]: Disable. [1]: Enable. XS: Crystal oscillator select. Recommend XS = [1] [0]: External clock. [1]: Crystal. O IFS [1:0]: IF band selection. (Ready only) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W CHN7 CHN6 CHN5 CHN4 CHN3 CHN2 CHN1 CHN0 IC PLL I C 9.2.15 PLL Register I (Address: 0Eh) M CHN [7:0]: LO channel number select. Refer to chapter 14 for details. A 9.2.16 PLL Register II (Address: 0Fh) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLL II R W DBL DBL RRC1 RRC1 RRC0 RRC0 CHR3 CHR3 CHR2 CHR2 CHR1 CHR1 CHR0 CHR0 IP8 BIP8 DBL: Crystal frequency doublers selection. [0]: Disable. FXREF = FXTAL. [1]: Enable. FXREF =2 * FXTAL. In FIFO mode, recommend to set DBL =0. In Direct mode, recommend to set DBL =1. Please refer to A7130 reference code for details. RRC [1:0]: RF PLL reference counter setting. Recommend RRC = [00]. The PLL comparison frequency, FPFD = FCRYSTAL *(DBL+1) / (RRC+1). Mar., 2013, Version 1.0 19 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver CHR [3:0]: PLL channel step setting. In FIFO mode, recommend to set CHR [3:0] = [0111]. In Direct mode, recommend to set CHR [3:0] = [1111]. Please refer to chapter 14 and A7130 reference code for details. 9.2.17 PLL Register III (Address: 10h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLL III R W IP7 BIP7 IP6 BIP6 IP5 BIP5 IP4 BIP4 IP3 BIP3 IP2 BIP2 IP1 BIP1 IP0 BIP0 TI A BIP [8:0]: LO base frequency integer part setting. (0Fh and 10h) In FIFO mode, recommend to set BIP [8:0] = [0x096]. In Direct mode, recommend to set BIP [8:0] = [0x04B]. Please refer to chapter 14 and A7130 reference code for details. 9.2.18 PLL Register IV (Address: 11h) R/W Bit 7 Bit 6 PLL IV R W RAC15 RAC14 RAC13 BFP15 BFP14 BFP13 9.2.19 PLL Register V (Address: 12h) R/W Bit 7 PLL V R W BFP7 RAC7 Bit 6 Bit 4 Bit 3 RAC12 RAC11 RAC10 RAC9 RAC8 BFP12 BFP11 BFP10 BFP9 BFP8 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 C O Name Bit 5 N Name FI D EN IP [8:0]: LO frequency integer part value. IP [8:0] are from address (0Fh) and (10h), Refer to chapter 14 for details. L Name Bit 4 Bit 2 Bit 1 Bit 0 RAC6 RAC5 RAC4 RAC3 RAC2 RAC1 RAC0 BFP6 BFP5 BFP4 BFP3 BFP2 BFP1 BFP0 M BFP [15:0]: LO base frequency fractional part setting. (11h and 12h) In FIFO mode, recommend to set BFP [15:0] = [0x0004]. In Direct mode, recommend to set BFP [15:0] = [0x0002]. Please refer to chapter 14 and A7130 reference code for details. C O RAC [15:0]: Auto Frequency compensation value if AFC (19h) =1. RAC [15:0] Note AFC = 1 PLLFF [15:0] LO Freq. compensation value AFC = 0 {SYNCF, AC [14:0]} IC 9.2.20 Channel Group Register I (Address: 13h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CHGI R/W CHGL7 CHGL6 CHGL5 CHGL4 CHGL3 CHGL2 CHGL1 CHGL0 M Name A CHGL [7:0]: PLL channel group low boundary setting for auto-calibration. Recommed CHGL[7:0] = 0x3C. Refer to A7130 reference code for details. 9.2.21 Channel Group Register II (Address: 14h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CHGII R/W CHGH7 CHGH6 CHGH5 CHGH4 CHGH3 CHGH2 CHGH1 CHGH0 CHGH [7:0]: PLL channel group high boundary setting for auto-calibration. Recommed CHGH[7:0] = 0x78. Refer to A7130 reference code for details. PLL calibration frequency is divided into 3 groups by CHGL and CHGH: Channel Group1 0 ~ CHGL-1 Group2 CHGL ~ CHGH-1 Mar., 2013, Version 1.0 20 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver Group3 CHGH ~ 255 9.2.22 TX Register I (Address: 15h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TX I W GDR GF TMDE TXDI TME FDP2 FDP1 FDP0 TMDE: TX modulation enable for VCO modulation. Recommend TMDE = [1]. [0]: Disable. [1]: Enable. EN TXDI: TX data invert. Recommend TXDI = [0]. [0]: Non-invert. [1]: Invert. TI A GF: Gaussian Filter Select. [0]: Disable. [1]: Enable. L GDR: Gaussian Filter Over Sampling Rate Select. Recommend GDR = [1]. [0]: BT= 0.7 [1]: BT= 0.5 TME: TX modulation enable. Recommend TME = [1]. [0]: Disable. [1]: Enable. Bit 6 N FI D FDP [2:0]: Frequency deviation power setting. Recommend FDP = [110]. In FIFO mode, recommend to set FDP [2:0] = [111]. In Direct mode, recommend to set FDP [2:0] = [110]. Please refer to chapter 14 and A7130 reference code for details. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FD6 FD5 FD4 FD3 FD2 FD1 FD0 Name R/W Bit 7 TXI W FD7 C O 9.2.23 TX Register II (Address: 16h) FDP[2:0] 111 110 FD[7:0] 0x40 0x40 Fdev 1MHz 1MHz O Data Rate 4Mbps FIFO mode 4Mbps Direct mode M FD [7:0]: Frequency deviation setting. FDEV = (FPFD /216) x FD[7:0] x 2(FDP-1). Where FPFD= FXTAL * (DBL+1) / (RRC [1:0]+1), PLL comparison frequency. R/W IC Name C 9.2.24 Delay Register I (Address: 17h) Delay W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DPR2 DPR1 DPR0 TDL1 TDL0 PDL2 PDL1 PDL0 M DPR [2:0]: Delay scale. Recommend DPR = [000]. A TDL [1:0]: Delay for TX settling from WPLL to TX. TDL Delay= 20 * (TDL [1:0]+1)*(DPR [2:0]+1) us. DPR [2:0] 000 000 000 000 TDL [1:0] 00 01 10 11 WPLL to TX 20 us 40 us 60 us 80 us Note Recommend PDL [2:0]: Delay for TX settling from PLL to WPLL. PDL Delay= 10 + {20 * (PDL [2:0]+1)*(DPR [2:0]+1)} us. DPR [2:0] PDL [2:0] 000 000 000 001 Mar., 2013, Version 1.0 PLL to WPLL (LO freq changed) 30 us 50 us 21 Note Recommend AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 000 000 000 010 011 100 70 us 90 us 110 us PLL M ode TX M ode G IO 1 P in (W T R ) PA Ramp Down R F O P in L T X S tro be 16 u s 10 u s + P D L TDL 9.2.25 Delay Register II (Address: 18h) R/W Bit 7 Bit 6 Bit 5 Delay W WSEL2 WSEL1 WSEL0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EN Name TI A P a ck e t RSSC_D1 RSSC_D0 RS_DLY2 RS_DLY1 RS_DLY0 FI D WSEL [2:0]: XTAL settling delay setting (200us ~ 2.5ms). Recommend WSEL = [011]. [000]: 200us. [001]: 400us. [010]: 600us. [011]: 800us. [100]: 1ms. [101]: 1.5ms. [110]: 2ms. [111]: 2.5ms. C ry s ta l O sc illa to r Id le m o de C O G IO 1 P in (W T R ) N T X or R X S tro be C m d W SEL 30 0 us R F O P in P a ck e t ( P r e a m b le + ID + P a ylo a d ) 10 us + PD L TD L M RSSC_D [1:0]: RSSI calibration switching time (10us ~ 40us). Recommend RSSC_D = [00]. [00]: 10us. [01]: 20us. [10]: 30us. [11]: 40us. O RS_DLY [2:0]: RSSI measurement delay (10us ~ 80us). Recommend RS_DLY = [000]. [000]: 10us. [001]: 20us. [010]: 30us. [011]: 40us. [100]: 50us. [101]: 60us. [110]: 70us. [111]: 80us. R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LNAGE AGCE RXSM1 RXSM0 AFCE RXDI DMG ULS IC Name C 9.2.26 RX Register (Address: 19h) RX W M LNAGE: Auto LNA Gain Control Select. [0]: Disable. [1]: Enable. A AGCE: Auto Front end Gain Control Select. [0]: Disable. [1]: Enable. RXSM1: RX clock recovery circuit moving average filter length. Recommend RXSM1 = [1]. [0]: 4 bits. [1]: 8 bits. RXSM0: Demodulator LPF Bandwidth Select. Recommend RXSM0 = [1]. [0]: 2*IF. [1]: 1*IF. AFCE: Frequency compensation select. [0]: Disable. [1]: Enable. RXDI: RX data output invert. Recommend RXDI = [0]. [0]: Non-inverted output. [1]: Inverted output. DMG: Demodulator Gain Select. Recommend DMG = [1]. [0]: x 1. [1]: x 3. Mar., 2013, Version 1.0 22 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver ULS: RX Up/Low side band select. Recommend ULS = [0]. [0]: Up side band, [1]: Low side band. Refer to section 14.2 for details. 9.2.27 RX Gain Register I (Address: 1Ah) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RX Gain I W R PRS -- MIC MICR IGC1 IGCR1 IGC0 IGCR0 MGC1 MGCR1 MGC0 MGCR0 LGC1 LGCR1 LGC0 LGCR0 TI A PRS: Limiter amplifier discharge manual select. Recommend PRS =[0]. MGC [1:0]: Mixer Gain Attenuation select. Recommend MGC =[11]. [00]: 0dB. [01]: 6dB. [10]: 12dB. [11]: 18dB. 9.2.28 RX Gain Register II (Address: 1Bh) R/W Bit 7 Bit 5 RX Gain II R W RH7 RH6 RH5 RSAGC1 RSAGC0 VTL2 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RH4 RH3 RH2 RH1 RH0 VTL1 VTL0 VTH2 VTH1 VTH0 C O Bit 6 N Name FI D LGC [1:0]: LNA Gain Attenuation select. Recommend LGC =[11]. [00]: 0dB. [01]: 6dB. [10]: 12dB. [11]: 18dB. EN MIC: Mixer buffer gain setting. Recommend MIC =[1]. [0]: 0dB. [1]: 6dB. IGC [1:0]: IFA Attenuation Select. Recommend IGC =[10]. [00]: 0dB. [01]: 6dB. [10]: 12dB. [11]: 18dB. L Name RSAGC [1:0]: AGC clock select. Recommend RSAGC = [11]. [00]: IF / 8. [01]: IF / 4. [10]: IF / 2. [11]: IF. M VTL [2:0]: VCO tuning voltage lower threshold level setting. Recommend VTL = [000]. [000]: 0.1V. [001]: 0.2V. [010]: 0.3V. [011]: 0.4V. [100]: 0.5V. [101]: 0.6V. [110]: 0.7V. [111]: 0.8V O VTH [2:0]: VCO tuning voltage upper threshold level setting. Recommend VTH = [010]. [000]: VDD_A – 0.6V. [001]: VDD_A – 0.7V. [010]: VDD_A – 0.8V. [011]: VDD_A – 0.9V [100]: VDD_A – 1.0V. [101]: VDD_A – 1.1V. [110]: VDD_A – 1.2V. [111]: VDD_A – 1.3V C Remark: VDD_A is on chip analog regulator output voltage where is set to 1.8V. IC RH [7:0]: RSSI Calibration High Threshold. (Read only) 9.2.29 RX Gain Register III (Address: 1Ch) M Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W RL7 -- RL6 RDU RL5 IFS1 RL4 IFS0 RL3 RSM1 RL2 RSM0 RL1 ERSSM RL0 RSS A RX Gain III R/W RDU: Clock Generator Select. Recommend RDU = [0]. [0]: 128MHZ [1]: 96MHZ. IFS [1:0]: IF Frequency Select. [00]: reserved. [01]: reserved. [10]: reserved [11]: 4MHZ. RSM [1:0]: RSSI Margin = RTH – RTL. Recommend RSM = [11]. [00]: 5. [01]: 10. [10]: 15. [11]: 20. Refer to chapter 17 for details. ERSSM: Ending Mode Select in RSSI Measurement. Recommend ERSSM = [0]. [0]: RSSI ending by RX. [1]: RSSI ending by SYNC_Ok. RSS: RSSI measurement select. (XADS=0, RSS=0, default mode is thermal sensor.) [0]: Disable. [1]: Enable (recommend). Mar., 2013, Version 1.0 23 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver RL [7:0]: RSSI Calibration Low Threshold. (Ready only) 9.2.30 RX Gain Register IV (Address: 1Dh) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RX Gain III W LIMC IFBC1 IFBC0 IFAS MHC1 MHC0 LHC1 LHC0 L LIMC: IF limiter current select. Recommend LIMC = [1]. [0]: 0.3mA. [1]: 0.6mA. TI A IFBC [1:0]: IF BPF current Select. Recommend IFBC = [11]. [00]: 0.75 mA.. [01]: 1.4mA. [10]: 2.1mA. [11]: 3.5mA. IFAS: IF Amp current select. Recommend IFAS = [0]. [0]: 0.3mA. [1]: 0.6mA. EN MHC: Mixer Current Select. Recommend MHC = [01]. [00]: 0.6mA. [01]: 1.2mA. [10]: reserved. [11]: reserved. 9.2.31 RSSI Threshold Register (Address: 1Eh) R/W Bit 7 Bit 6 Bit 5 RSSI Threshold R W ADC7 RTH7 ADC6 RTH6 ADC5 RTH5 Bit 3 Bit 2 Bit 1 Bit 0 ADC4 RTH4 ADC3 RTH3 ADC2 RTH2 ADC1 RTH1 ADC0 RTH0 C O RTH [7:0]: Carrier detect threshold. Refer to Chapter 17 for details. CD (Carrier Detect)=1 when RSSI ≧ RTH. CD (Carrier Detect)=0 when RSSI < RTL. Bit 4 N Name FI D LHC[1:0]: LNA Current Select. Recommend LHC = [11]. [00]: 0.5mA. [01]: 1mA. [10]: 1.5mA. [11]: 2mA. M ADC [7:0]: ADC output value for RSSI measurement. ADC input voltage= 1.2 * ADC [7:0] / 256 V. 9.2.32 ADC Control Register (Address: 1Fh) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADC Control W AVSEL1 AVSEL0 MVSEL1 MVSEL0 RADC FSARS XADS CDM O Name C AVSEL [1:0]: ADC average times (for Carrier / temperature sensor / external ADC). Recommend AVSEL = [11]. [00]: No average. [01]: Average 2 times. [10]: Average 4 times. [11]: Average 8 times. IC MVSEL [1:0]: ADC average times (for VCO calibration and RSSI ). Recommend MVSEL = [11]. [00]: Average 8 times. [01]: Average 16 times. [10]: Average 32 times. [11]: Average 64 times. A M RADC: ADC Read Out Average Mode. Recommend RADC = [0]. [0]: by AVSEL. [1]: by MVSEL. FSARS: ADC clock select. Recommend FSARS = [0]. [0]: 4MHz. [1]: 8MHz. XADS: External ADC Input Signal Select. [0]: Disable. [1]: Enable. CDM: ADC measurement mode. Recommend CDM = [1]. [0]: Single mode. [1]: Continuous mode. 9.2.33 Code Register I (Address: 20h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Code I W MCS WHTS FECS CRCS IDL1 IDL0 PML1 PML0 Mar., 2013, Version 1.0 24 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver MSC: Manchester Enable. [0]: Disable. [1]: Enable. WHTS: Data Whitening (Data Encryption) Select. [0]: Disable. [1]: Enable (The data is whitening by multiplying PN7). FECS: FEC Select. [0]: Disable. [1]: Enable (The FEC is (7, 4) Hamming code). TI A L CRCS: CRC Select. Recommend CRCS = [1]. [0]: Disable. [1]: Enable. IDL [1:0]: ID Code Length Select. Recommend IDL= [01]. [00]: 2 bytes. [01]: 4 bytes. [10]: 6 bytes. [11]: 8 bytes. 9.2.34 Code Register II (Address: 21h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Code II W MSCRC EDRL HECS ETH2 Bit 3 Bit 2 Bit 1 Bit 0 ETH1 ETH0 PMD1 PMD0 FI D Name EN PML [1:0]: Preamble Length Select. Recommend PML= [11]. [00]: 1 byte. [01]: 2 bytes. [10]: 3 bytes. [11]: 4 bytes. MSCRC: Mask CRC (CRC Data Filtering Enable). Recommend MSCRC = [1]. [0]: Disable. [1]: Enable. C O HECS: HEC Header CRC-8 select. [0]: Disable. [1]: Enable. Please refer to chapter 16 for details. N EDRL: Enable FIFO Dynamic Length [0]: Disable. [1]: Enable. Please refer to chapter 16 for details. ETH [2:0]: Received ID Code Error Tolerance. Recommend ETH = [001]. [000]: 0 bit, [001]: 1 bit. [010]: 2 bit. [011]: 3 bit. [100]: 4 bit, [101]: 5 bit. [110]: 6 bit. [111]: 7 bit. M PMD [1:0]: Preamble pattern detection length. Recommend PMD = [10]. [00]: 0bit. [01]: 4bits. [10]: 8bits. [11]: 16bits. O 9.2.35 Code Register III (Address: 22h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W CRCINV WS6 WS5 WS4 WS3 WS2 WS1 WS0 Bit 0 C Name Code III IC CRCINV: CRC Inverted Select. [0]: Non-inverted. [1]: inverted. M WS [6:0]: Data Whitening seed setting (data encryption key). The data is whitened by multiplying with PN7. Please refer to chapter 16 for details. A 9.2.36 IF Calibration Register I (Address: 23h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 IF Calibration I R W -- -- -- FBCF FB3 FB2 FB1 FB0 HFR CKGS1 CKGS0 MFBS MFB3 MFB2 MFB1 MFB0 HFR: Half Rate setting. Recommend HFR = [0]. [0]: Clk gen. by 32 x Data Rate. [1]: Clk gen. by 16 x Data Rate. CKGS[1:0]: Clock gen. data rate manual setting. Recommend CKGS = [11]. [00]: reserved. [01]: reserved. [10]: reserved. [11]: 4MHZ. When RDU=0, CKGS[1:0] = IFS[1:0] When RDU=1, CKGS[1:0] = Manual setting. MFBS: IF filter calibration value select. Recommend MFBS = [0]. Mar., 2013, Version 1.0 25 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver [0]: Auto calibration value. [1]: Manual calibration value. MFB [3:0]: IF filter manual calibration value. FBCF: IF filter auto calibration flag (read only). [0]: Pass. [1]: Fail. 9.2.37 IF Calibration Register II (Address: 24h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 IF Calibration II R W -PWORS -TRT2 TRT1 FCD4 TRT0 FCD3 ASMV2 Bit 2 Bit 1 Bit 0 FCD2 ASMV1 FCD1 ASMV0 FCD0 AMVS EN PWORS: TX high power setting. Recommend PWORS = [1]. [0]: Disable. [1]: Enable. TI A L FB [3:0]: IF filter calibration value (read only). MFBS= 0: Auto calibration value (AFB), MFBS= 1: Manual calibration value (MFB). TRT [2:0]: TX Ramp down discharge current select. Recommend TRT = [111]. N AMVS: TX Ramp Up Enable. Recommend AMVS = [1]. [0]: Disable. [1]: Enable. FI D AMSV [2:0]: TX Ramp up Timing Select. Recommend AMSV = [111]. [000]: 2us, [001]: 4us. [010]: 6us. [011]: 8us. [100]: 10us, [101]: 12us. [110]: 14us. [111]: 16us. Real case of TX ramping up is AMSV [2:0] multiplied by 2^(RMP[1:0]) C O FCD [4:0]: IF filter calibration deviation from goal (read only). 9.2.38 VCO current Calibration Register (Address: 25h) Name R/W Bit 7 VCO current Calibration R W -ROSCS Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -RSIS -VCRLS VCCF MVCS VCB3 VCOC3 VCB2 VCOC2 VCB1 VCOC1 VCB0 VCOC0 M ROSCS: WOR RC select. Recommend ROSCS = [1] O RSIS: WOR current select. Recommend RSIS = [0] C VCRLS: VCO Current Resistor Select. Recommend VCRLS = [0] [0]: low current select. [1]: high current select. IC MVCS: VCO current calibration value select. Recommend MVCS = [0]. [0]: Auto calibration value. [1]: Manual calibration value. VCOC [3:0]: VCO current manual calibration value. M VCCF: VCO Current Auto Calibration Flag (read only). [0]: Pass. [1]: Fail. A VCB [3:0]: VCO current calibration value (read only). MVCS= 0: Auto calibration value (VCB). MVCS= 1: Manual calibration value (VCOC). 9.2.39 VCO band Calibration Register I (Address: 26h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VCO Single band Calibration I R W -DCD1 -DCD0 -DAGS -CWS VBCF MVBS VB2 MVB2 VB1 MVB1 VB0 MVB0 DCD [1:0]: VCO Deviation Calibration Delay. Recommend DCD = [11]. Delay time = PDL (Delay Register I, 17h) × ( DDC + 1 ). DAGS: DAG Calibration Value Select. Recommend DAGS = [0]. [0]: Auto calibration value. [1]: Manual calibration value. Mar., 2013, Version 1.0 26 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver CWS: Clock Disable for VCO Modulation. Recommend CWS = [1]. [0]: Enable. [1]: Disable. MVBS: VCO bank calibration value select. Recommend MVBS = [0]. [0]: Auto calibration value. [1]: Manual calibration value. MVB [2:0]: VCO band manual calibration value. VB [2:0]: VCO bank calibration value (read only). MVBS= 0: Auto calibration value (AVB). MVBS= 1: Manual calibration value (MVB). 9.2.40 VCO band Calibration Register II (Address: 27h) R/W Bit 7 Bit 6 Bit 5 Bit 4 W R DAGM7 DAGB7 DAGM6 DAGB6 DAGM5 DAGB5 DAGM4 DAGB4 DAGB [7:0]: Auto DAG Calibration Value (read only). DAGM3 DAGB3 FI D DAGM [7:0]: DAG Manual Setting Value. Bit 3 Bit 2 Bit 1 Bit 0 DAGM2 DAGB2 DAGM1 DAGB1 DAGM0 DAGB0 Bit 2 Bit 1 Bit 0 DEVA1 VMS_M DEVA0 MSEL EN Name VCO Single band Calibration II TI A L VBCF: VCO band auto calibration flag (read only). [0]: Pass. [1]: Fail. 9.2.41 VCO Deviation Calibration Register I (Address: 28h) R/W Bit 7 Bit 6 Bit 5 VCO Deviation Calibration I R W DEVA7 DEVS3 DEVA6 DEVS2 DEVA5 DEVS1 Bit 4 C O N Name DEVA4 DEVS0 Bit 3 DEVA3 DEVA2 DAMR_M VMTE_M DEVS [3:0]: Deviation Output Scaling. Recommend DEVS = [0111]. DAMR_M: DAMR Manual Enable. Recommend DAMR_M = [0]. [0]: Disable. [1]: Enable. M VMTE_M: VMT Manual Enable. Recommend VMTE_M = [0]. [0]: Disable. [1]: Enable. O VMS_M: VM Manual Enable. Recommend VMS_M = [0]. [0]: Disable. [1]: Enable. C MSEL: VMS, VMTE and DAMR control select. Recommend MSEL = [0]. [0]: Auto control. [1]: Manual control. M IC DEVA [7:0]: Deviation Output Value (read only). MVDS (29h)= 0: Auto calibration value ((DEVC / 8) × (DEVS + 1)), MVDS (29h)= 1: Manual calibration value (DEVM [6:0]). 9.2.42 VCO Deviation Calibration Register II (Address: 29h) A Name VCO Deviation Calibration II R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W DEVC7 MVDS DEVC6 DEVM6 DEVC5 DEVM5 DEVC4 DEVM4 DEVC3 DEVM3 DEVC2 DEVM2 DEVC1 DEVM1 DEVC0 DEVM0 MVDS: VCO Deviation Calibration Select. Recommend MVDS = [0]. [0]: Auto calibration value. [1]: Manual calibration value. DEVM [6:0]: VCO Deviation Manual Calibration Value. DEVC [7:0]: VCO Deviation Auto Calibration Value (read only). Mar., 2013, Version 1.0 27 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 9.2.43 DASP0 (Address: 2Ah, Page 0 by AGT [3:0]=0) Name DASP0 R/W Bit 7 Bit 6 W QLIM RFSP Bit 5 Bit 4 INTXC CSXTL4 (CSXTL5) Bit 3 Bit 2 Bit 1 Bit 0 CSXTL3 CSXTL2 CSXTL1 CSXTL0 QLIM: quick charge select for IF limiter amp. Recommend QLIM = [0]. [0]: disable. [1]: enable. (QLIM fall down delay 10 us). INTXC: internal crystal oscillator capacitor selection. Recommend INTXC = [1]. [0]: disable. [1]: enable. TI A L RFSP: RF single port Select. Recommend RFSP = [0]. [0]: LNA (RFI) and PA (RFO) are combined internally to RFI pin. [1]: LNA (RFI) and PA (RFO) are separated to RFI pin and RFO pin. FI D EN CSXTAL[4:0]: On-chip Crystal loading select. Recommend CSXTAL = [10100] if Xtal Cload = 18 pF. {INTXC,CSXTAL[4:0]} On-chip Xtal Capacitor (pF) 0XXXXX 0 100000 16 100001 17 100010 18 … 111110 46 111111 47 R/W Bit 7 DASP1 W STS Bit 6 Bit 5 C O Name N 9.2.43 DASP1 (Address: 2Ah, Page 1 by AGT[3:0]=1) CELS RGS Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RGC1 RGC0 VRPL1 VRPL0 INTPRC STS: Start up mode select. Shall be set to [0]. CELS: Digital voltage select in standby mode. Recommend CELS = [1]. Low Power Regulator Voltage Note 3/5 *REGI 3/4 * REGI 1.8 V Recommended 1.6 V O RGS 0 1 0 1 IC C LVR (2Ch) 0 0 1 1 M RGS: Low Power Regulator Voltage Select. Recommend RGS = [0]. RGC [1:0]: Low power band-gap current select. Recommend RGC = [01]. M VRPL [1:0]: internal PLL loop filter resistor value select. Recommend VRPL = [00]. [00]: 500 ohm. [01]: 666 ohm. [10]: 1 K ohm. [11]: 2K ohm. A INTPRC: Internal PLL loop filter resistor and capacitor select. Recommend INTPRC = [1]. [0]: disable. [1]: enable 9.2.43 DASP2 (Address: 2Ah, Page 2 by AGT[3:0]=2) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DASP2 W VTRB3 VTRB2 VTRB1 VTRB0 VMRB3 VMRB2 VMRB1 VMRB0 VTRB [3:0]: Resistor Bank for VT RC Filtering. Shall be set to [0000]. VMRB [3:0]: Resistor Bank for VM RC Filtering. Shall be set to [0000]. Mar., 2013, Version 1.0 28 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 9.2.43 DASP3 (Address: 2Ah, Page 3 by AGT[3:0]=3) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DASP3 W DCV7 DCV6 DCV5 DCV4 DCV3 DCV2 DCV1 DCV0 Bit 1 Bit 0 VMG1 VMG0 DCV [7:0]: Demodulator Fix mode DC value. Recommend DCV = [0x80]. R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 DASP4 W/R VMG7 VMG6 VMG5 VMG4 VMG3 VMG2 TI A Name L 9.2.43 DASP4 (Address: 2Ah, Page 4 by AGT[3:0]=4) VMG [7:0]: VM Center Value for Deviation Calibration. Recommend VMG [7:0] = [0x80]. 9.2.43 DASP5 (Address: 2Ah, Page 5 by AGT[3:0]=5) R/W Bit 7 Bit 6 Bit 5 Bit 4 W -- -- PKT1 PKT0 PKT[1:0]: VCO Peak Detect Current Select. Recommend PKT = [00]. PKS Bit 2 Bit 1 Bit 0 PKIS1 PKIS0 IFPK FI D PKS: VCO Current Calibration Mode Select. Recommend PKS = [0]. Bit 3 EN Name DASP5 PKIS[1:0]: AGC Peak Detect Current Select. Recommend PKIS = [00]. IFPK: AGC Amplifier Current Select. Recommend IFPK = [0]. N 9.2.43 DASP6 (Address: 2Ah, Page 6 by AGT[3:0]=6) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W -- HPLS HRS PACTL IWS CNT MXD LXD C O Name DASP6 HPLS: High Power LNA Gain Select. Recommend HPLS = [0]. [0]: LGC set to 6dB when in TX Mode. [1]: LGC set to 24dB when in TX Mode. HRS: Reserved for internal usage only. Shall be set to [0]. M PACTL: Reserved for internal usage only. Shall be set to [0]. O IWS: Reserved for internal usage only. Shall be set to [1]. CNT: Reserved for internal usage only. Shall be set to [0]. C MXD: Reserved for internal usage only. Shall be set to [1]. IC LXD: Reserved for internal usage only. Shall be set to [0]. 9.2.43 DASP7 (Address: 2Ah, Page 7 by AGT[3:0]=7) M Name DASP7 R/W W Bit 7 XDS Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VRSEL MS MSCL4 MSCL3 MSCL2 MSCL1 MSCL0 A XDS: VCO Modulation Data Sampling Clock selection. Recommend XDS = [0]. [0]: 8x over-sampling Clock. [1]: XCPCK Clock. VRSEL: AGC Function select. Recommend VRSEL = [1]. [0]: RSSI AGC. [1]: Normal AGC. MS: AGC Manual scale select. Recommend MS = [0]. [0]: By (RH−RL). [1]: By MSCL[4:0]. MSCL[4:0]: AGC Manual Scale setting. Recommend MSCL = [00000]. 9.2.44 VCO Modulation Delay Register (Address: 2Bh) Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name W DMV1 DMV0 DEVFD2 DEVFD1 DEVFD0 DEVD2 DEVD1 DEVD0 Mar., 2013, Version 1.0 29 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver DMV [1:0]: Demodulator D/A Voltage Range Select. Recommend DMV = [11]. [00]: 1/32*1.2. [01]: 1/16*1.2. [10]: 1/8*1.2. [11]: 1/4*1.2. DEVFD [2:0]: VCO Modulation Data Delay by 8x over-sampling Clock. Recommend DEVFD = [011]. DEVD [2:0]: VCO Modulation Data Delay by XCPCK Clock. Recommend DEVD = [100]. 9.2.45 Battery detect Register (Address: 2Ch) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Battery detect W R LVR -- RGV1 RGV1 RGV0 RGV0 QDS BDF BVT2 BVT2 BVT1 BVT1 Bit 1 Bit 0 BVT0 BVT0 BD_E BD_E L R/W TI A Name LVR: Low Power Bandgap Select. Recommend LVR = [1]. [0]: Disable. [1]: Enable. EN RGV [1:0]: VDD_D and VDD_A voltage setting in non-Sleep mode. Recommend RGV = [11]. [00]: 2.1V. [01]: 2.0V. [10]: 1.9V. [11]: 1.8V. QDS: VDD Quick Discharge Select. Recommend QDS = [1]. [0]: Disable. [1]: Enable. FI D BVT [2:0]: Battery voltage detect threshold. [000]: 2.0V. [001]: 2.1V. [010]: 2.2V. [011]: 2.3V. [100]: 2.4V. [101]: 2.5V. [110]: 2.6V. [111]: 2.7V. N BD_E: Battery Detect Enable. [0]: Disable. [1]: Enable. It will be clear after battery detection is triggered. C O BDF: Battery detection flag. [0]: Battery voltage < BVT [2:0]. [1]: Battery voltage ≧ BVT [2:0]. 9.2.46 TX test Register (Address: 2Dh) R/W Bit 7 TX test W RMP1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RMP0 TXCS PAC1 PAC0 TBG2 TBG1 TBG0 M Name RMP [1:0]: PA ramp up timing scale. Recommend RMP = [00]. O TXCS: TX Current Setting. Recommend TXCS = [1]. [0]: lowest current. [1]: highest current. C PAC [1:0]: PA Current Setting. RF Band IC TBG [2:0]: TX Buffer Setting. Typical power (dBm) PWORS (24h) TBG TXCS PAC Typical current (mA) 5 1 7 1 2 29 0 1 0 1 0 20 -5 0 4 1 0 18 -17 Refer to A7130 App. Note for more settings. 0 0 1 0 16 A M 2.4GHz 9.2.47 Rx DEM test Register I (Address: 2Eh) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rx DEM test I W DMT DCM1 DCM0 MLP1 MLP0 SLF2 SLF1 SLF0 DMT: Reserved for internal usage only. Shall be set to [0]. DCM [1:0]: Demodulator DC estimation mode. Recommend DCM = [10]. (The average length before hold is selected by DCL in RX DEM Test Register II.) [00]: Fix mode (For testing only). DC level is set by DCV [7:0]. Mar., 2013, Version 1.0 30 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver [01]: Preamble hold mode. DC level is preamble average value. [10]: ID hold mode. DC level is the average value hold about 8 bit data rate later if preamble is detected. [11]: Payload average mode (For internal usage). DC level is payload data average. MLP1: Reserved for internal usage. Shall set MLP1 = [0]. MLP0: Reserved for internal usage. Shall set MLP0 = [0]. L SLF [2:0]: Symbol Recovery Loop Filter Setting. Shall be SLF[2:0] = [111]. Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Rx DEM test II W DCH1 DCH0 DCL2 DCL1 DCL0 Bit 2 Bit 1 Bit 0 RAW CDTM1 CDTM0 EN DCH [1:0]: DC Estimation of AGC hold mode. Recommend DCH = [11]. [00]: hold when PMDO. [01]: hold when Fsync. [10]: no hold. [11]: no hold. TI A 9.2.48 Rx DEM test Register II (Address: 2Fh) DCL [2]: DC Estimation Average Length After ID Detected. Recommend DCL[2] = [1]. [0]: 128 bits. [1]: 256 bits. RAW: Raw Data Output Select. Recommend RAW = [1]. [0]: latch data output. [1]: RAW data output. FI D DCL [1:0]: DC Estimation Average Length Before ID Detected. Recommend DCL[1:0] = [10]. [00]: 8 bits. [01]: 16 bits. [10]: 32 bits. [11]: 64 bits. N CDTM [1:0]: Preamble carrier detect setting. Recommend CDTM = [11]. [00]: 12. [01]: 24. [10]: 36. [11]: 48. Name R/W Bit 7 CPC I W CPM3 C O 9.2.49 Charge Pump Current Register I (Address: 30h) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPM2 CPM1 CPM0 CPT3 CPT2 CPT1 CPT0 M CPM [3:0]: Charge Pump Current Setting for VM loop. Recommend CPM = [1111]. Charge pump current = (CPM + 1) / 16 mA. O CPT [3:0]: Charge Pump Current Setting for VT loop. Recommend CPT = [0000]. Charge pump current = (CPT + 1) / 16 mA. 9.2.50 Charge Pump Current Register II (Address: 31h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W CPTX3 CPTX2 CPTX1 CPTX0 CPRX3 CPRX2 CPRX1 CPRX0 IC C Name CPC II CPTX [3:0]: Charge Pump Current Setting for TX mode. Recommend CPTX = [0011]. Charge pump current = (CPTX + 1) / 16 mA. M CPRX [3:0]: Charge Pump Current Setting for RX mode. Recommend CPRX = [0111]. Charge pump current = (CPRX + 1) / 16 mA. A 9.2.51 Crystal test Register (Address: 32h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Crystal test W CDPM CPS CPH CPCS DBD XCC XCP1 XCP0 CDPM:First Time Preamble Detect mode select. Recommend CDPM = [0]. CPS: PLL charge pump enable. Recommend CPS = [1]. [0]: Enable. [1]: Disable. CPH: Charge Pump High Current. Shall be set to [0]. [0]: Normal. [1]: High. CPCS: Charge Pump Current Select. Shall be set to [1]. [0]: Use CPM for TX, CPT for RX. [1]: Use CPTX for TX, CPRX for RX. Mar., 2013, Version 1.0 31 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver DBD: Crystal Frequency Doubler High Level Pulse Width Select. Recommend DBD = [0]. [0]: about 8 ns. [1]: about 16 ns. XCC: Crystal Startup Current Selection. Recommend XCC = [1]. [0]: about 0.7 mA. [1]: about 1.5 mA. 9.2.52 PLL test Register (Address:33h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 PLL test W MDEN OLM PRIC1 PRIC0 PRRC1 OLM: Open Loop Modulation Enable. Shall be set to [0]. [0]: Disable. [1]: Enable. PRIC [1:0]: Prescaler IF Part Current Setting. Shall be set to [01]. [00]: 0.95mA. [01]: 1.05mA. [10]: 1.15mA. [11]: 1.25mA. PRRC0 SDPW NSDO FI D PRRC [1:0]: Prescaler RF Part Current Setting. Shall be set to [01]. [00]: 1.0mA. [01]: 1.2mA. [10]: 1.4mA. [11]: 1.6mA. Bit 0 EN MDEN : Use for Manual VCO Calibration. Shall be set to [0]. Bit 1 TI A Name L XCP [1:0]: Crystal Oscillator Regulated Couple Setting. Recommend XCP = [01]. [00]: 1.5mA. [01]: 0.5mA. [10]: 0.35mA. [11]: 0.3mA. SDPW: Clock Delay For Sigma Delta Modulator. Shall be set to [0]. [0]: 13 ns. [1]: 26 ns. N NSDO: Sigma Delta Order Setting. Shall be set to [1]. [0]: order 2. [1]: order 3. Name R/W VCO test I W Bit 7 C O 9.2.53 VCO test Register I (Address:34h) Bit 6 Bit 5 DEVGD2 DEVGD1 DEVGD0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TLB1 TLB0 RLB1 RLB0 VBS M DEVGD [2:0]: Sigma Delta Modulator Data Delay Setting. Recommend DEVGD = [000]. O TLB [1:0]: LO Buffer Current Select. Recommend TLB[1:0] = [10]. [00]: 0.6mA. [01]: 0.75mA. [10]: 0.9mA. [11]: 1.05mA. C RLB [1:0]: RF divider Current Select. Recommend RLB[1:0] = [10]. [00]: 1.2mA. [01]: 1.5mA. [10]: 1.8mA. [11]: 2.1mA. IC VBCS : VCO Buffer Current Setting. Recommend VBCS = [1]. [0]: 1mA. [1]: 1.5mA. 9.2.54 RF Analog Test Register (Address: 35h) M Name RFT R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W AGT3 AGT2 AGT1 AGT0 RFT3 RFT2 RFT1 RFT0 A AGT[3:0]:Page selection for both DASP (2Ah) and ROMP (38h). AGT[3:0] (35h) 0 1 DASP Register Group (2Ah) DASP0 (page 0) DASP1 (page 1) ROMP Register Group (38h) ROMP0 (page 0) ROMP1 (page 1) Internal usage only Internal usage only 2 3 4 DADP2 (page 2) DASP3 (page 3) DASP4 (page 4) ROMP2 (page 2) ROMP3 (page 3) ROMP4 (page 4) Internal usage only Internal usage only Internal usage only 5 DASP5 (page 5) 6 DASP6 (page 6) Mar., 2013, Version 1.0 32 Note AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver RFT [3:0]: RF analog pin configuration for testing. Recommend RFT= [0000]. 9.2.55 AES Key data Register (Address: 36h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Key Data R W KEYO7 KEYI7 KEYO6 KEYI6 KEYO5 KEYI5 KEYO4 KEYI4 KEYO3 KEYI3 KEYO2 KEYI2 KEYO1 KEYI1 KEYO0 KEYI0 KEYI [7:0]: AES128 key input, total 16-btyes. (Write only). K e y D a ta K E Y [7 :0 ] (to ta l 1 6 B y te s ) EN A E S TI A KEYO [7:0]: AES128 key output, total 16-bytes. (Read only). Select by KEYOS (3Eh). … K E Y [1 5 :8 ] L Name K E Y [1 2 7 :1 2 0 ] Name R/W Bit 7 Bit 6 Bit 5 Channel Select W CHI3 CHI2 CHI1 FI D 9.2.56 Channel Select Register (Address: 37h) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CHI0 CHD3 CHD2 CHD1 CHD0 N CHI [3:0]: Auto IF Offset Channel Number Setting. Recommend CHI [3:0] = [0111]. FCHSP × (CHI + 1 ) = FIF Refer to chapter 14 for FCHSP setting. Name R/W Bit 7 C O CHD [3:0]: Channel Frequency Offset for Deviation Calibration. Recommend CHD [3:0] = [0111]. Offset channel number = +/- (CHD + 1). Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ROMP0 W MPOR EPRG MIGS MRGS MRSS MTMS MADS MBGS M 9.2.57 ROMP0 (Address: 38h, Page 0 by AGT[3:0]=0) O MPOR: manual SPI read in OTP program cycle. C EPRG: enable OTP program in test mode. [0]: disable. [1]: enable. IC MIGS: IF gain setting select. [0]: SPI setting. [1]: OTP setting. MRGS: LNA and mixer gain setting select. [0]: SPI setting. [1]: OTP setting. M MRSS: RSSI voltage fine trim setting select. [0]: SPI setting. [1]: OTP setting. A MTMS: Temp voltage fine trim setting select. [0]: SPI setting. [1]: OTP setting. MADS: ADC fine trim setting select. [0]: SPI setting. [1]: OTP setting. MBGS: Bandgap voltage fine trim setting select. [0]: SPI setting. [1]: OTP setting. 9.2.57 ROMP1 (Address: 38h, Page 1 by AGT[3:0]=1) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ROMP1 W APG MPA1 MPA0 FBG4 FBG3 FBG2 FBG1 FBG0 APG: OTP program select. Mar., 2013, Version 1.0 33 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver [1]: auto program. [0]: manual SPI setting. MPA [1:0]: OPT address setting in manual SPI OTP program. FBG [4:0]: Bandgap voltage SPI fine trim setting. 9.2.57 ROMP2 (Address: 38h, Page 2 by AGT[3:0]=2) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W PTM1 PTM0 CTR5 CTR4 CTR3 CTR2 CTR1 CTR0 CTR [5:0]: ADC voltage SPI fine trim setting. 9.2.57 ROMP3 (Address: 38h, Page 3 by AGT[3:0]=3) R/W Bit 7 Bit 6 Bit 5 Bit 4 W FGC1 FGC0 CRS2 CRS1 CRS [2:0]: RSSI voltage offset fine trim setting. SRS [2:0]: RSSI voltage curve slope fine time setting. CRS0 FI D FGC[1:0]: BPF fine gain control. Bit 3 Bit 2 Bit 1 Bit 0 SRS2 SRS1 SRS0 EN Name ROMP3 TI A PTM [1:0]: OTP program operation mode select. Recommend PTM = [00]. L Name ROMP2 9.2.57 ROMP4 (Address: 38h, Page 4 by AGT[3:0]=4) R/W Bit 7 Bit 6 Bit 5 ROMP4 W -- STMP STM5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STM4 STM3 STM2 STM1 STM0 C O N Name STMP: Temp voltage ADC reading select. [0]: 1 scale / degree C. [1]: 2 scale/degree C. STM [5:0]: Temperature voltage SPI fine trim setting. M 9.2.58 Data Rate Clock Register (Address: 39h) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W SDR7 SDR6 SDR5 SDR4 SDR3 SDR2 SDR1 SDR0 O Name Data Rate Clock C SDR [1:0]: Data Rate Setting. On-air Data rate = FIF / (SDR+1). FIF (Hz) 4M SDR [7:0] 0x00 Xtal 16 MHz IC Data Rate 4M Please refer to chapter 13 for details. M 9.2.59 FCR Register (Address: 3Ah) A Name FCR R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W ARTEF FCL1 VPOAK FCL0 RCR3 ARC3 RCR2 ARC2 RCR1 ARC1 RCR0 ARC0 EAK EAK EAR EAR FCL [1:0] : FCB Length. [00]: No Frame Control. [01]: 1 byte FCB (3Dh). [10]: 2 byte FCB (3Dh). [11]: 4 byte FCB (3Dh). Please refer to chapter 16 and 19 for details. ARC [3:0] : Auto Resend Cycle Setting. [0000]: resend disable. Mar., 2013, Version 1.0 34 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver [0001]: 1 [0010]: 2 [0011]: 3 [0100]: 4 [0101]: 5 [0110]: 6 [0111]: 7 [1000]: 8 [1001]: 9 [1010]: 10 [1011]: 11 [1100]: 12 [1101]: 13 [1110]: 14 [1111]: 15 EAK : Enable Auto ACK. [0]: Disable. [1]: Enable. EAR : Enable Auto Resend. [0]: Disable. [1]: Enable. TI A L ARTEF: Auto re-transmission ending flag (read only). [0]: Resend not end [1]: Finish resend. VPOAK : Valid Packet or ACK OK Flag. (read only and auto clear by Strobe command) [0]: Neither valid packet nor ACK OK. [1]: Valid packet or ACK OK. RCR [3:0] (read) : Decremented of ARC[3:0]. 9.2.60 ARD Register (Address: 3Bh) R/W Bit 7 Bit 6 Bit 5 Bit 4 ARD W ARD7 ARD6 ARD5 ARD4 ARD[7:0] : Auto Resend Delay ARD Delay = 200 us * (ARD+1) à (200us ~ 51.2 ms) Bit 2 Bit 1 Bit 0 ARD3 ARD2 ARD1 ARD0 Bit 3 Bit 2 Bit 1 Bit 0 Please refer to chapter 19 for details. C O N [0000-0000]: 200 us. [0000-0001]: 400 us. [0000-0010]: 600 us. … … [1111-1111]: 51.2 ms. Bit 3 FI D Name EN Please refer to chapter 16 and 19 for details. M 9.2.61 AFEP Register (Address: 3Ch) R/W Bit 7 Bit 6 AFEP R W 0 EAF 0 SPSS Bit 5 Bit 4 EARTS2 EARTS1 EARTS0 SID2 SID1 SID0 ACKFEP5 ACKFEP4 ACKFEP3 ACKFEP2 ACKFEP1 ACKFEP0 C O Name IC EAF: Enable ACK FIFO. [0]: Disable. [1]: Enable. SPSS : Mode Back Select for Auto ACK/Resend. [0]: Standby mode. [1]: PLL mode. A M ACKFEP [5:0]: FIFO Length setting for auto-ack packet. ACK FIFO Length = (ACKFEP[5:0] + 1) max. 64 bytes. EARTS [2:0]: Enable Auto Resend Read. SID [2:0]: Serial Packet ID. This device increases SID each time for every new packet and keep the same SID when retransmitting. Please refer to chapter 16 and 19 for details. 9.2.62 FCB Register (Address: 3Dh) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FCB R/W F7 F6 F5 F4 F3 F2 F1 F0 FCB [7:0]: Frame Control Buffer, total 20-bytes. Mar., 2013, Version 1.0 35 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver TI A L Byte Name Bit-Map Description Strobe Cmd 0 FCB0 0 0 1 1 1 SID2 SID1 SID0 For auto-resend. NA 1 FCB1 [7:0] ACK info NA by user’s attaching 2 FCB2 [7:0] 3 FCB3 [7:0] Remark: 1. Please refer to section 10.4.10 for details. 2. SID is auto incremental for every new packet if FCB0 is enabled. 3. FCB0 ~ FCB3 is controlled by FCL[1:0] (3Ah) 4. User can attach wanted ACK information to FCB1 ~ FCB3 if auto-ack is enabled (EAK =1). ID c o d e FC B 1 ~ 4 b y te s 4 b y te s 4 b y te s P H Y H e a d e r ( s e lf - g e n e r a te d ) Bit 7 KEYC W KEYOS 1 2 b it s Bit 6 Bit 5 C O R/W P a y lo a d (C R C ) P h y . 6 4 b y te s 2 b y te s M A C H e ad e r (s elf-g en era te d ) 9.2.63 KEYC Register (Address: 3Eh) Name FEP N P r e a m b le d y n a m ic F IF O FI D a u to ac k /re se n d EN Please refer to chapter 16 and 19 for details. AFIDS ARTMS Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MIDS AESS -- AKFS EDCRS M KEYOS: AES128 Key source read select. [0]: If AKFS=1, from RX received encrypted AES128 key data. If AKFS=0, from SPI write AES128 key data. [1]: From encrypted/decrypted AES128 key data. Please refer to chapter 21 for details. O AFIDS: FIFO ID appendixes Select. [0]: Disable. [1]: Enable. IC C ARTMS: auto-resend Interval Mode Select. [0]: random interval. [1]: fixed interval. Please refer to chapter 16 and 19 for details. MIDS: FIFO control byte address mapping for FIFO ID select. [0]: Received device ID. [1]: internal FIFO control byte ID. A M AESS: encryption format selection. [1]: Standard AES 128 bit. [0]: proprietary 32 bit. Please refer to chapter 21 for details. AKFS: Data packet with decrypted key appendixes select. [0]: Disable. [1]: Enable. EDRCS: Data encrypt or decrypt select. [0]: Disable. [1]: Enable. 9.2.64 USID Register (Address: 3Fh) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 USID W RND7 RND6 RND5 RND4 RND3 RND2 RND1 RND0 RND [7:0]: Random seed for auto-resend interval. Please refer to chapter 16 and 19 for details. Mar., 2013, Version 1.0 36 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 10. SPI A7130 only supports one SPI interface with maximum data rate up to 15Mbps. MCU should assert SCS pin low (SPI chip select) to active accessing of A7130. Via SPI interface, user can access control registers and issue Strobe command. Figure 10.1 gives an overview of SPI access manners. TI A L 3-wire SPI (SCS, SCK and SDIO) or 4-wire SPI (SCS, SCK, SDIO and GIO1/GIO2) configuration is provided. For 3-wire SPI, SDIO pin is configured as bi-direction to be data input and output. For 4-wire SPI, SDIO pin is data input and GIO1 (or GIO2) pin is data output. In such case, GIO1S (0bh) or GIO2S (0ch) should be set to [0110]. For SPI write operation, SDIO pin is latched into A7130 at the rising edge of SCK. For SPI read operation, if input address is latched by A7130, data output is aligned at falling edge of SCK. Therefore, MCU can latch data output at the rising edge of SCK. Data In Data Out 3-Wire SPI SCS pin = 0 SDIO pin SDIO pin 4-Wire SPI SCS pin = 0 SDIO pin GIO1 (GIO1S=0110) / GIO2 (GIO2S=0110) N FI D SPI chip select Read/Write register Read/Write RF FIFO Read/Write ID register C O SCS ADDRreg DataByte ADDRFIFO DataByte0 ADDRreg DataByte DataByte1 ADDRreg DataByte2 DataByte DataByte3 DataByten DataByte0 DataByte1 DataByte2 DataByte3 M ADDRID Strobe CommandSleep Mode O Sleep Mode Strobe CommandIdle Mode C Idle Mode Strobe CommandSTBY Mode IC STBY Mode EN To control A7130’s internal state machine, it is very easy to send Strobe command via SPI interface. The Strobe command is a unique command set with total 8 commands. See section 10.3, 10.4 and 10.5 for details. Strobe CommandPLL Mode RX Mode Strobe CommandRX Mode TX Mode Strobe CommandTX Mode A M PLL Mode FIFO Write Reset Strobe CommandFIFO Write Reset FIFO Read Reset Strobe CommandFIFO Read Reset Figure 10.1 SPI Access Manners Mar., 2013, Version 1.0 37 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 10.1 SPI Format The first bit (A7) is critical to indicate A7130 the following instruction is “Strobe command” or “control register”. See Table 10.1 for SPI format. Based on Table 10.1, To access control registers, just set A7=0, then A6 bit is used to indicate read (A6=1) or write operation (A6=0). See Figure 10.2 (3-wire SPI) and Figure 10.3 (4-wire SPI) for details. R/W A6 Address Byte (8 bits) Address A5 A4 A3 A2 A1 A0 7 6 5 Data Byte (8 bits) Data 4 3 2 EN Address byte: Bit 7: Command bit [0]: Control registers. [1]: Strobe command. FI D Bit 6: R/W bit [0]: Write data to control register. [1]: Read data from control register. Bit [5:0]: Address of control register 0 TI A Table 10.1 SPI Format 1 L CMD A7 N Data Byte: Bit [7:0]: SPI input or output data, see Figure 10.2 and Figure 10.3 for details. C O 10.2 SPI Timing Characteristic M IC C O M No matter 3-wire or 4-wire SPI interface is configured, the maximum SPI data rate is 10 Mbps. To active SPI interface, SCS pin must be set to low. For correct data latching, user has to take care hold time and setup time between SCK and SDIO. See Table 10.2 for SPI timing characteristic. A Parameter FC TSE THE TSW THW TDR Description FIFO clock frequency. Enable setup time. Enable hold time. TX Data setup time. TX Data hold time. RX Data delay time. Min. 50 50 50 50 0 Max. 10 50 Unit MHz ns ns ns ns ns Table 10.2 SPI Timing Characteristic Mar., 2013, Version 1.0 38 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 10.3 SPI Timing Chart In this section, 3-wire and 4-wire SPI interface read / write timing are described. 10.3.1 Timing Chart of 3-wire SPI L SCS SDIO A7 A6 A5 A4 A3 A2 A1 A0 DW7 RF IC will latch address bit at rising edge of SCK DW6 DW5 TI A SCK DW1 DW0 DR1 DR0 RF IC will latch data bit at the rising edge of SCK EN 3-Wire serial interface - Write operation FI D SCS SCK SDIO A7 A6 A5 A4 A3 A2 A1 A0 DR7 RF IC will change the data when falling edge of SCK DR5 MCU can latch data at rising edge of SCK N RF IC will latch address bit at rising edge of SCK DR6 C O 3-Wire serial interface - Read operation Figure 10.2 Read/Write Timing Chart of 3-Wire SPI M 10.3.2 Timing Chart of 4-wire SPI SCS A7 A6 C SDIO O SCK A5 A4 A3 A2 A1 A0 DW7 RF IC will latch address bit at rising edge of SCK DW6 DW5 DW 1 DW0 IC RF IC will latch data bit at rising edge of SCK M 4-Wire serial interface - Write operation SCS A SCK SDI A7 A6 A5 A4 A3 A2 A1 x GIOx RF IC will latch address bit at rising edge of SCK x A0 DR7 RF IC will change the data when falling edge of SCK DR6 DR5 DR2 DR1 DR0 MCU can latch data at the rising edge of SCK 4-Wire serial interface - Read operation Figure 10.3 Read/Write Timing Chart of 4-Wire SPI Mar., 2013, Version 1.0 39 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 10.4 Strobe Commands A7130 supports 8 Strobe commands to control internal state machine for chip’s operations. Table 10.3 is the summary of Strobe commands. N FI D EN TI A Strobe Command when AFIDS =0 (3Eh) and MIDS =0 (3Eh) Strobe Command Description A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 0 1 0 0 0 Deep Sleep mode (I/Os are in tri-state) 1 0 0 0 1 0 1 1 Deep Sleep mode (I/Os are pulled high) 1 0 0 0 x x x x Sleep mode 1 0 0 1 x x x x Idle mode 1 0 1 0 x x x x Standby mode 1 0 1 1 x x x x PLL mode 1 1 0 0 x x x x RX mode 1 1 0 1 x x x x TX mode 1 1 1 0 x x x x FIFO write pointer reset 1 1 1 1 x x x x FIFO read pointer reset Remark: x means “ don’t care” L Be notice, Strobe command could be defined by 4-bits (A7~A4) or 8-bits (A7~A0). If 8-bits Strobe command is selected, A3 ~ A0 are don’t care conditions. In such case, SCS pin can be remaining low for asserting next commands. C O Table 10.3 Strobe Commands by SPI interface 10.4.1 Strobe Command - Sleep Mode M Refer to Table 10.3 user can issue 4 bits (1000) Strobe command directly to set A7130 into Sleep mode. Below are the Strobe command table and timing chart. A6 0 A5 0 A4 0 A3 x A2 X A1 x Description A0 x Sleep mode A M IC C A7 1 O Strobe Command Strobe Command Figure 10.4 Sleep mode Command Timing Chart 10.4.2 Strobe Command - ldle Mode Refer to Table 10.3, user can issue 4 bits (1001) Strobe command directly to set A7130 into Idle mode. Below is the Strobe command table and timing chart. Mar., 2013, Version 1.0 40 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver Strobe Command Strobe Command A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 1 x X x x Idle mode SCS SCK SDIO A7 A6 A5 SDIO A4 A7 A6 A4 Idle mode A3 A2 A1 A0 EN Idle mode A5 TI A SCK L SCS Description Figure 10.5 Idle mode Command Timing Chart FI D 10.4.3 Strobe Command - Standby Mode Strobe Command Strobe Command A5 1 A4 0 A3 x A2 X A1 x Description A0 x Standby mode C O A6 0 IC C O M A7 1 N Refer to Table 10.3, user can issue 4 bits (1010) Strobe command directly to set A7130 into Standby mode. Below is the Strobe command table and timing chart. Figure 10.6 Standby mode Command Timing Chart M 10.4.4 Strobe Command - PLL Mode A Refer to Table 10.3, user can issue 4 bits (1011) Strobe command directly to set A7130 into PLL mode. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 1 A6 0 A5 1 Mar., 2013, Version 1.0 A4 1 A3 x A2 X A1 x Description A0 x PLL mode 41 AMICCOM Electronics Corporation A7130 10.4.5 Strobe Command - RX Mode TI A Figure 10.7 PLL mode Command Timing Chart L 2.4GHz FSK/GFSK Security Transceiver A6 1 A5 0 A4 0 A3 x A2 X A1 x Description A0 x RX mode M C O N A7 1 FI D Strobe Command Strobe Command EN Refer to Table 10.3, user can issue 4 bits (1100) Strobe command directly to set A7130 into RX mode. Below are the Strobe command table and timing chart. Figure 10.8 RX mode Command Timing Chart O 10.4.6 Strobe Command - TX Mode C Refer to Table 10.3, user can issue 4 bits (1101) Strobe command directly to set A7130 into TX mode. Below are the Strobe command table and timing chart. IC Strobe Command Strobe Command A6 A5 A4 A3 A2 A1 A0 1 1 0 1 x x x x Description TX mode A M A7 Figure 10.9 TX mode Command Timing Chart 10.4.7 Strobe Command – FIFO Write Pointer Reset Mar., 2013, Version 1.0 42 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver Refer to Table 10.3, user can issue 4 bits (1110) Strobe command directly to reset A7130 FIFO write pointer. Below is the Strobe command table and timing chart. Strobe Command Strobe Command A6 1 A5 1 A4 0 A3 x A2 x A1 x Description A0 x FIFO write pointer reset FI D EN TI A L A7 1 Figure 10.10 FIFO write pointer reset Command Timing Chart 10.4.8 Strobe Command – FIFO Read Pointer Reset Strobe Command Strobe Command C O N Refer to Table 10.3, user can issue 4 bits (1111) Strobe command directly to reset A7130 FIFO read pointer. Below are the Strobe command table and timing chart. A6 A5 A4 A3 A2 A1 A0 1 1 1 1 x x x x Description FIFO read pointer reset M IC C O M A7 A Figure 10.11 FIFO read pointer reset Command Timing Chart 10.4.9 Strobe Command – Deep Sleep Mode Refer to Table 10.3, user can issue (8 bits) deep sleep Strobe command directly to switch off power supply to A7130.In this mode, A7130 is staying minimum current consumption. All registers are no data retention and re-calibration flow is necessary. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 A6 A5 A4 A3 A2 A1 A0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 Mar., 2013, Version 1.0 Description Tri-state of GIO1 / GIO2 (no register retention) Internal Pull-High of GIO1 / GIO2 (no register retention) 43 AMICCOM Electronics Corporation A7130 EN TI A L 2.4GHz FSK/GFSK Security Transceiver FI D Figure 10.12 Deep Sleep Mode Timing Chart N 10.5 Reset Command C O In addition to power on reset (POR), MCU could issue software reset to A7130 by setting Mode Register (00h) through SPI interface as shown below. As long as 8-bits address (A7~A0) are delivered zero and data (D7~D0) are delivered zero, A7130 is informed to generate internal signal “RESETN” to initial itself. After reset command, A7130 is in standby mode and calibration procedure shall be issued again. M SCS A7 RESETN O SDIO C SCK IC A6 A5 A4 A3 A2 A1 A0 DW 7 DW 6 DW5 DW1 DW 0 Reset RF chip Figure 10.14 Reset Command Timing Chart M 10.6 ID Accessing Command A A7130 has built-in 32-bits ID Registers for customized identification code. It is accessed via SPI interface. ID length is recommended to be 32 bits by setting IDL (1Fh). Therefore, user can toggle SCS pin to high to terminate ID accessing command when ID data is output completely. Figure 10.13 and 10.14 are timing charts of 32-bits ID accessing via 3-wire SPI. 10.6.1 ID Write Command User can refer to Figure 10.2 for SPI write timing chart in details. Below is the procedure of ID write command. Step1: Step2: Step3: Deliver A7~A0 = 00000110 (A6=0 for write, A5~A0 = 000110 for ID addr, 06h). By SDIO pin, deliver 32-bits ID into A7130 in sequence by Data Byte 0 (recommend 5xh or Axh), 1, 2 and 3. Toggle SCS pin to high when step2 is completed. Mar., 2013, Version 1.0 44 AMICCOM Electronics Corporation A7130 TI A L 2.4GHz FSK/GFSK Security Transceiver Figure 10.15 ID Write Command Timing Chart EN 10.6.2 ID Read Command User can refer to Figure 10.2 for SPI read timing chart in details. Below is the procedure of ID read command. FI D Deliver A7~A0 = 01000110 (A6=1 for read, A5~A0 = 000110 for ID addr, 06h). SDIO pin outputs 32-bits ID in sequence by Data Byte 0, 1, 2 and 3. Toggle SCS pin to high when step2 is completed. M C O N Step1: Step2: Step3: O Figure 10.16 ID Read Command Timing Chart IC C 10.7 FIFO Accessing Command M To use A7130’s FIFO mode, enable FMS (01h) =1 via SPI interface. Before TX delivery, just write wanted data into TX FIFO (05h) then issue TX Strobe command. Similarly, user can read RX FIFO (05h) once payload data is received. A MCU can use polling or interrupt scheme to do FIFO accessing. FIFO status can output to GIO1 (or GIO2) pin by setting GIO1S (0Bh) or GIO2S (0Ch). Figure 10.15 and 10.16 are timing charts of FIFO accessing via 3-wire SPI. 10.7.1 TX FIFO Write Command User can refer to Figure 10.2 for SPI write timing chart in details. Below is the procedure of TX FIFO write command. Step1: Step2: Step3: Step4: Deliver A7~A0 = 00000101 (A6=0 for write control register and issue FIFO A [5:0] = 05h). By SDIO pin, deliver (n+1) bytes TX data into TX FIFO in sequence by Data Byte 0, 1, 2 to n. Toggle SCS pin to high when step2 is completed. Send Strobe command of TX mode (Figure 10.9) to do TX delivery. Mar., 2013, Version 1.0 45 AMICCOM Electronics Corporation A7130 TI A Figure 10.17 TX FIFO Write Command Timing Chart L 2.4GHz FSK/GFSK Security Transceiver 10.7.2 Rx FIFO Read Command Deliver A7~A0 = 01000101 (A6=1 for read control register and issue FIFO at address 05h). SDIO pin outputs RX data from RX FIFO in sequence by Data Byte 0, 1, 2 to n. Toggle SCS pin to high when RX FIFO is read completely. C O N FI D Step1: Step2: Step3: EN User can refer to Figure 10.2 for SPI read timing chart in details. Below is the procedure of RX FIFO read command. A M IC C O M Figure 10.18 RX FIFO Read Command Timing Chart Mar., 2013, Version 1.0 46 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 11. State machine SPI Clock SPI Data In SPI Data Out FMS register 3-Wire SPI SCS SCK SDIO SDIO 4-Wire SPI SCS SCK SDIO GIO1 or GIO2 FIFO (FMS=1) Direct (FMS=0) FIFO (FMS=1) Direct (FMS=0) TI A SPI chip select From current consumption point of view, A7130 has below 8 operation modes. EN Deep Sleep mode Sleep mode Idle mode Standby mode PLL mode TX mode RX mode Star-networking mode FI D (1) (2) (3) (4) (5) (6) (7) (8) L From accessing data point of view, if FMS=1, FIFO mode is enabled, otherwise, A7130 is in direct mode. N 11.1 Key states C O After power on reset or software reset or deep sleep mode, user has to do calibration process because all control registers are in initial values. The calibration process of A7130 is very easy, user only needs to issue Strobe commands and enable calibration registers. And then, the calibrations are automatically completed by A7130’s internal state machine. Table 11.1 shows a summary of key circuitry among those strobe commands. A M IC C O M Strobe Command when AFIDS =0 (3Eh) and MIDS =0 (3Eh) Strobe Command Description A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 0 1 0 0 0 Deep Sleep mode (I/Os are in tri-state) 1 0 0 0 1 0 1 1 Deep Sleep mode (I/Os are pulled high) 1 0 0 0 x x x x Sleep mode 1 0 0 1 x x x x Idle mode 1 0 1 0 x x x x Standby mode 1 0 1 1 x x x x PLL mode 1 1 0 0 x x x x RX mode 1 1 0 1 x x x x TX mode 1 1 1 0 x x x x FIFO write pointer reset 1 1 1 1 x x x x FIFO read pointer reset Mode Deep Sleep (Tri-state) Deep Sleep (pull-high) Sleep Idle Register retention Regulator Xtal Osc. VCO PLL RX TX Strobe Command No OFF OFF OFF OFF OFF OFF (1000-1000)b No OFF OFF OFF OFF OFF OFF (1000-1011)b Yes ON OFF OFF OFF OFF OFF (1000-xxxx)b Yes ON OFF OFF OFF OFF OFF (1001-xxxx)b Standby Yes ON ON OFF OFF OFF OFF (1010-xxxx)b PLL Yes ON ON ON ON OFF OFF (1011-xxxx)b TX Yes ON ON ON ON OFF ON (1101-xxxx)b RX Yes ON ON ON ON ON OFF (1100-xxxx)b Mar., 2013, Version 1.0 Corporation 47 AMICCOM Electronics A7130 2.4GHz FSK/GFSK Security Transceiver Remark: x means “don’t care” Table 11.1. Operation mode and strobe command 11.2 FIFO mode Strobe CMD (SCS,SCK,SDIO) TX Next Instruction Strobe RF settling 10us +(PDL+TDL) Pin Preamble + ID Code + Payload EN RFO TI A L This mode is suitable for the requirements of general purpose applications and can be chosen by setting FMS = 1. After calibration, user can issue Strobe command to enter standby mode where write TX FIFO or read RX FIFO. From standby mode to packet data transmission, only one Strobe command is needed. Once transmission is done, A7130 is auto back to standby mode. Figure 11.1 and Figure 11.2 are TX and RX timing diagram respectively. Figure 11.3 illustrates state diagram of FIFO mode. GIO1 Pin - WTR (GIO1S[3:0]=0000) T0 T1 FI D Transmitting Time T2 Auto Back Standby Mode Strobe CMD (SCS,SCK,SDIO) C O N Figure 11.1 TX timing of FIFO Mode RX strobe RX settling RFI Pin O M GIO1 Pin - WTR (GIO1S[3:0]=0000) Preamble + ID Code + Payload Receiving Time T1 T3 T2 Auto Back Standby Mode Figure 11.2 RX timing of FIFO Mode A M IC C T0 Next Instruction Wait Packet Mar., 2013, Version 1.0 48 AMICCOM Electronics Corporation A7130 Figure 11.3 State diagram of FIFO Mode A M IC C O M C O N FI D EN TI A L 2.4GHz FSK/GFSK Security Transceiver 11.3 Direct mode This mode is suitable to let MCU to drive customized packet to A7130 directly by setting FMS = 0. In TX mode, MCU shall send customized packet in bit sequence (simply called raw TXD) to GIO1 or GIO2 pin. In RX mode, the receiving raw bit streams (simply called RXD) can be configured output to GIO1 or GIO2 pin. Be aware that a customized packet shall be preceded by a 32 bits preamble to let A7130 get a suitable DC estimation voltage. After calibration flow, for every state transition, user has to issue Strobe command to A7130 for fully manual control. This mode is also suitable for the requirement of versatile packet format. Figure 11.4 and Figure 11.5 are TX and RX timing diagram in direct mode respectively. Figure 14.6 illustrates state diagram of direct mode. Mar., 2013, Version 1.0 49 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver Strobe CMD (SCS,SCK,SDIO) TX STB strobe Strobe RF settling 10us+(PDL+TDL) GIO1 Pin - WTR (GIO1S[3:0]=0000) Modulated signals Carrier only Pin Preamble + customized raw TXD L Modulation auto enable GIO1 Pin - TMEO (GIO1S[3:0]=0010) 32-bits preamble TI A RFO Manually back to STB GIO2 Pin - TXD (GIO2S[3:0]=1001) T1 T4 T3 EN T0 Strobe CMD (SCS,SCK,SDIO) FI D Figure 11.4 TX timing of Direct Mode RX Strobe Wait packet RX settling Pin Coming packet Preamble + customized raw TXD N RFO STB strobe Manually back to STB C O GIO1 Pin - WTR (GIO1S[3:0]=0000) GIO1 Pin - PMDO (GIO1S[3:0]=0011) M GIO2 Pin - RXD (GIO2S[3:0]=1000) T1 T4 T3 Figure 11.5 RX timing of Direct Mode A M IC C O T0 Preamble detect output Mar., 2013, Version 1.0 50 AMICCOM Electronics Corporation A7130 Figure 11.6 State diagram of Direct Mode A M IC C O M C O N FI D EN TI A L 2.4GHz FSK/GFSK Security Transceiver Mar., 2013, Version 1.0 51 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 12. Crystal Oscillator A7130 needs external crystal or external clock that is either 16 MHz (or 18MHz) to generate internal wanted clock. Clock Register (Address: 0Dh) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 W R CGC1 IFS1 CGC0 IFS0 GRC3 GRC3 GRC2 GRC2 GRC1 GRC1 Clock GRC0 GRC0 Bit 1 Bit 0 CGS -- XS -- EN 12.1 Use External Crystal Bit 2 TI A Name L Relative Control Register Crystal ESR ≦80 ohm O M C O N Crystal Accuracy ±50 ppm FI D Figure 12.1 shows the connection of crystal network between XI and XO pins. C1 and C2 capacitance built inside A7130 are used to adjust different crystal loading. User can set INTXC [4:0] to meet crystal loading requirement. A7130 supports low cost crystal within ± 50 ppm accuracy. Be aware that crystal accuracy requirement includes initial tolerance, temperature drift, aging and crystal loading. C Fig12.1 Crystal oscillator circuit, set INTXC[4:0] for the internal C1 and C2 values. 12.2 Use External Clock A M IC A7130 has built-in AC couple capacitor to support external clock input. Figure 12.2 shows how to connect. In such case, XI pin is left opened. XS shall be low to select external clock. The frequency accuracy of external clock shall be controlled within ± 50 ppm, and the amplitude of external clock shall be within 1.2 ~ 1.8 V peak-to-peak. Fig12.2 External clock source. R is used to tune Vpp = 1.2~1.8V Mar., 2013, Version 1.0 Corporation 52 AMICCOM Electronics A7130 2.4GHz FSK/GFSK Security Transceiver 13. System Clock L A7130 supports different crystal frequency by programmable “Clock Register”. Based on this, three important internal clocks FCGR , FDR and FSYCK are generated. DBL (0Fh) 0 (FIFO mode) 1 (Direct mode) FCGR 2MHz 2MHz CLK Gen. FCGR X 32 FCGR X 64 FSYCK 64MHz 128MHz FIF 4MHz 4MHz FDR 4MHz 4MHz EN Data Rate 4Mbps 4Mbps TI A (1) FXTAL: Crystal frequency. (2) FXREF: Crystal Ref. Clock = FXREF * (DBL+1). (3) FCGR: Clock Generation Reference = 2MHz = FXREF / (GRC+1). (4) FSYCK: System Clock is related to FIF and FDR. (6) FDR: Data Rate Clock = FIF / (SDR+1). FI D Table 13.1 System clock and related clock sources RDU/CGC XS ÷ FXREF CE DBL X2 C O (GRC+1) CE XI N GRC 0 1 PLL x64/x32 1 FCGR= 2MHz CGS CE FSYCK auto scaler FDR F IF / (SDR+1) 0 Clock Generator M FXTAL C O XO /2 FPFD / (RRC+1) auto scaler VCO 4MHz 8MHz 0 FADC 1 FSARS IC Fig13.1 System clock block diagram M 13.2 Data Rate Setting A User has to choose 16MHz Xtal (or 18MHz) for 4Mbps applications. For more data rate options, please contact AMICCOM FAE team. Data rate 4Mbps Xtal DBL (0Fh) 16MHz 0 16MHz 1 Mar., 2013, Version 1.0 GRC (0Dh) 0111 1111 RDU (1Ch) 0 0 CGS (0Dh) 1 1 RRC (0Fh) 00 00 53 CGC (0Dh) 10 10 CGS (0Dh) 1 1 IFS SDR [7:0] Note (1Ch) (39h) 11 0x00 FIFO mode 11 0x00 Direct mode AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 14. Transceiver LO Frequency A7130 is a half-duplex transceiver with embedded PA and LNA. For TX or RX frequency setting, user just needs to set up LO (Local Oscillator) frequency for two ways radio transmission. L To target full range of 2.4GHz ISM band (2400 MHz to 2483.5 MHz), A7130 applies offset concept by LO frequency FLO = FLO_BASE + FOFFSET. Therefore, this device is easy to implement frequency hopping and multi-channels by just ONE register setting, PLL Register I (CHN [7:0]). F PFD F XTAL (DBL+1) / (RRC[1:0]+1) AC[14:0]/ 2 16 PFD AFC 1 0 Divider 0 FI D F LO_BASE BIP[8:0] + BFP[15:0]/ 2 16 + CHN / [4*(CHR+1)] F LO VCO EN X TI A Below is the LO frequency block diagram. + N F OFFSET F LO C O Fig14.1 Frequency synthesizer block diagram 14.1 LO Frequency Setting O Set FLO_BASE ~ 2400.001MHz. Set FCHSP = 500 KHz. Set FOFFSET = CHN [7:0] x FCHSP The LO frequency, FLO = FLO_BASE + FOFFSET IC C 1. 2. 3. 4. M From Figure 14.1, FLO is not only for TX radio frequency but also to be RX LO frequency. To set up FLO, it is easy by below 4 steps. FLO A M FLO_BASE FOFFSET FLO_BASE FLO_BASE = FPFD × ( BIP[8 : 0] + FXTAL BFP[15 : 0] BFP[15 : 0] × ( BIP[8 : 0] + ) = ( DBL + 1) × ) 16 RRC[1 : 0] + 1 2 216 Base on the above formula, i.e. 16 MHz, please refer to Table 14.1 and 14.2 as a calculation example to get LO frequency. DBL = 0 for FIFO mode STEP ITEMS VALUE NOTE 1 FXTAL 16 MHz Crystal Frequency 2 DBL 0 Disable double function 3 RRC 0 If so, FPFD= 16MHz Mar., 2013, Version 1.0 54 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 0x096 0x0004 2400.001 MHz To get FLO_BASE =2400 MHz To get FLO_BASE ~ 2400.001 MHz LO Base frequency DBL = 1 for Direct mode STEP ITEMS 1 FXTAL 2 DBL 3 RRC 4 BIP[8:0] 5 BFP[15:0] 6 FLO_BASE VALUE 16 MHz 1 0 0x04B 0x0002 2400.001 MHz NOTE Crystal Frequency Enable double function If so, FPFD= 16MHz To get FLO_BASE =2400 MHz To get FLO_BASE ~ 2400.001 MHz LO Base frequency L BIP[8:0] BFP[15:0] FLO_BASE TI A 4 5 6 EN Table 14.1 How to set FLO_BASE C O N FI D How to set FTXRF = FLO = FLO_BASE + FOFFSET ~ 2405.001 MHz STEP ITEMS VALUE NOTE 1 FLO_BASE 2400.001 MHz After set up BIP and BFP 2 CHR[3:0] [0111] To get FCHSP= 500 KHz if DBL =0 for FIFO mode. [1111] To get FCHSP= 500 KHz if DBL =1 for Direct mode. 4 CHN[7:0] 0x0A FOFFSET= 500 KHz * (CHN) = 5MHz 6 FLO 2405.001 MHz Get FLO= FLO_BASE + FOFFSET 7 FTXRF 2405.001 MHz FTXRF = FLO Table 14.2 How to set FTXRF For 16MHz crystal, below is the calculation detail for FFPD and FCHSP. FXTAL (MHz) RRC (0Fh) 00 00 FPFD (MHz) CHR [3:0] FCHSP (KHz) Note 16 32 0111 1111 500 500 Recommend Recommend C 16 16 DBL (0Fh) 0 1 M FPFD 4 × (CHR[3 : 0] + 1) O FCHSP = IC 14.2 IF Side Band Select M Since A7130 is a low-IF TRX, in RX mode, the FRXLO shall be set to shift a FIF (i.e. FIF = 4MHz @ 4Mbps) regarding to coming FTXRF. Therefore, A7130 offers two methods to set up FLO while A7130 is exchanging from TX mode to RX mode. A AIF register is used to enable Auto IF function for Auto IF exchange mode. And ULS registers is used for fast exchange mode because of reduction of PLL settling time. (1) Auto IF exchange mode AIF (01h) ULS (19h) 1 0 1 1 FRXLO Formula FRXLO = FLO － FIF FRXLO = FLO ＋ FIF Note Auto-minus a FIF because ULS = 0 Auto-plus a FIF because ULS = 1 (2) Fast exchange mode AIF (01h) ULS (19h) 0 0 0 1 FRXLO Formula FRXLO = FLO FRXLO = FLO Note The coming FTXRF shall be (FRXLO + FIF ) The coming FTXRF shall be (FRXLO - FIF ) Mar., 2013, Version 1.0 55 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 14.2.1 Auto IF Exchange A7130 supports Auto IF offset function by setting AIF = 1. In such case, FTXRF between master and slave is the same so that there is only one carrier frequency (Fcarrier) during communications. Meanwhile, FRXLO during TRX exchanging is auto shifted FIF. See below Figures and Table 14.3 for details. L Master AIF=1 and ULS=0, FRXLO is auto shifted lower than FTXRF for a (FIF). FLO_BASE CHN[7:0] 0x0A 0x0A FCHSP (KHz) 500 500 FI D ULS 0 0 FLO_BASE (MHz) 2400.001 2400.001 FTXRF (MHz) 2405.001 -- FRXLO (MHz) -2401.001 FTXRF (MHz) 2405.001 -- FRXLO (MHz) -2401.001 N AIF 1 1 FIF 4MHz @ 4Mbps EN FRXLO FOFFSET =5MHz Master TX RX TI A FTXRF = FLO = FCarrier C O Slave AIF=1 and ULS=0, FRXLO is auto shifted lower than FTXRF for a (FIF). FTXRF = FLO = FCarrier O M FLO_BASE AIF 1 1 A M Slave TX RX IC C FOFFSET =5MHz Mar., 2013, Version 1.0 ULS 0 0 CHN[7:0] 0x0A 0x0A FRXLO FIF 4MHz @ 4Mbps FCHSP (KHz) 500 500 FLO_BASE (MHz) 2400.001 2400.001 Table 14.3 Auto IF exchange mode while TRX exchanging 56 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 14.2.2 Fast Exchange Fast exchange can reduce the PLL settling time during TRX exchanging because FRXLO and FTXRF are kept to the same FLO in either master or slave side. However, there are two on-air frequency (FCarrier (master), FCarrier (slave)) during communications. In such case, user has to control ULS =0 in master side and ULS = 1 in slave side for two ways radio. See below Figures and Table 14.4 for details. FTXLO = FLO = FCarrier (Master) FLO_BASE EN FRXLO TI A L Master AIF=0 and ULS=0, Master is set to up side band. FOFFSET =5MHz FI D FIF 4MHz @ 4Mbps Slave AIF=0 and ULS=1, Slave is set to low side band. N FTXLO= FLO = FCarrier (Slave) AIF 0 0 CHN[7:0] 0x0A 0x0A O Slave TX RX ULS 0 0 C AIF 0 0 ULS 1 1 CHN[7:0] 0x12 0x12 FRXLO FCHSP (KHz) 500 500 FLO_BASE (MHz) 2400.001 2400.001 FTXRF (MHz) 2405.001 -- FRXLO (MHz) -2405.001 FCHSP (KHz) 500 500 FLO_BASE (MHz) 2400.001 2400.001 FTXRF (MHz) 2409.001 -- FRXLO (MHz) -2409.001 Table 14.4 Fast exchange mode while TRX exchanging A M IC Master TX RX M FOFFSET =9MHz C O FLO_BASE Mar., 2013, Version 1.0 57 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 14.3 Auto Frequency Compensation L The AFC function (Auto Frequency Compensation) supports to use low accuracy crystal (±50 ppm) on A7130 without sensitivity degradation. The AFC concept is automatically fine tune RX LO frequency (FRXLO). User can read AC [14:0] to know the compensation value of FRXLO. F LO F PFD F XTAL AC[14:0]/ 2 16 0 F LO_BASE BIP[8:0] + BFP[15:0]/ 2 16 + CHN / [4*(CHR+1)] 1 Divider 0 AFC + F OFFSET VCO PFD TI A / (RRC[1:0]+1) F LO EN (DBL+1) FI D X N Figure 14.3 Block Diagram of enabling AFC function C O For AFC procedure, please refer to A7130’s reference code and contact AMICCOM FAE team for details. 15. Calibration C O VCO Current Calibration. VCO Bank Calibration. VCO Deviation Calibration. IF Filter Bank Calibration. RSSI Calibration. RC Oscillator Calibration. IC 1. 2. 3. 4. 5. 6. M A7130 needs calibration process after deep sleep mode or power on reset or software reset. Below are six calibration items inside the device. 15.1 Calibration Procedure M The purpose to execute the above calibration items is to deal with Foundry process deviation. After calibrations, A7130 will be set to the best working conditions without concerning Foundry process deviation to impact A7130’s RF performance. A In general, user can use A7130’s auto calibration function by just enabling calibration items and checking its calibration flag. For detailed calibration procedures, please refer to A7130 reference code of initRF() subroutine and A7130_Cal() subroutine. 1. Initialize A7130 by calling the subroutine of initRF(). n Initialize all control registers by calling the subroutine of A7130_Config(). n Execute all calibration items by calling the subroutine of A7130_Cal(). Mar., 2013, Version 1.0 58 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 16. FIFO (First In First Out) A7130 has the separated physical 64-bytes TX and RX FIFO inside the device. To use A7130’s FIFO mode, user just needs to enable FMS =1. For FIFO accessing, TX FIFO (write-only) and RX FIFO (read-only) share the same register address 05h. TX FIFO represents transmitted payload. On the other hand, RX circuitry synchronizes ID Code and stores received payload into RX FIFO. L 16.1 TX Packet Format in FIFO mode TI A 16.1.1 Basic FIFO mode EN If FCL[1:0] = 00 and ENRL = 0, A7130 is formed a Basic FIFO mode which can also support Auto-ack/ Auto-resend function. There is no MAC header in TX packet format. ID code is a PHY header used to be the frame sync to enable RX FIFO receiving. D a ta w h ite n in g (o p tio n a l) F E C e n c o d e d /d e c o d e d (o p tio n a l) C R C -1 6 c a lc u la tio n (o p tio n a l) ID c o d e 4 b y te s 4 b y te s P a y lo a d FI D P re a m b le P h y . 6 4 b y te s ID Byte 1 ID Byte 2 ID Byte 3 C O ID Byte 0 2 b y te s N ID code (C R C ) Figure 16.1 TX packet format of basic FIFO mode O M Preamble: The packet is led by a self-generated preamble which is composed of alternate 0 and 1. If the first bit of ID code is 0, preamble shall be 0101…0101. In the contrast, if the first bit of ID code is 1, preamble shall be 1010…1010. Preamble length is recommended to set 4 bytes by PML [1:0] (20h). IC C ID code: ID code is recommended to set 4 bytes by IDL[1:0] = [01] and ID Code is stored into ID Data register by sequence ID Byte 0, 1, 2 and 3. If RX circuitry check ID code is correct, payload will be written into RX FIFO. In addition, user can set ID code error tolerance (0~ 7bit error) by setting ETH [2:0] during ID synchronization check. A M Payload: Payload length is programmable by FEP [11:0]. The physical FIFO depth is 64 bytes. A7130 also supports logical FIFO extension up to 4K bytes. CRC: In FIFO mode, if CRC is enabled (CRCS=1), 2-bytes of CRC value is self-generated and attached at the footer of the packet. In the same way, RX circuitry will check CRC value and show the result to CRC Flag. 16.1.2 Advanced FIFO mode A7130 supports to self generated MAC header to form an advanced FIFO mode by enabling FCL[1:0], ENRL.. Therefore, A7130 can support ACK FIFO (FCB1~FCB3) and dynamic FIFO length depending on configurations. Mar., 2013, Version 1.0 59 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver a u to ac k /re se n d 4 b y te s ID c o d e FC B FEP 4 b y te s 1 ~ 4 b y te s 1 2 b i ts P H Y H e a d e r ( s e lf - g e n e r a te d ) P a y lo a d P h y . 6 4 b y te s (C R C ) 2 b y te s M A C H e a d e r ( s e lf - g e n e r a te d ) TI A Figure 16.2 TX packet format of advanced FIFO mode. L P r e a m b le d y n a m ic F IF O EN FCB: If FCL[1:0] ≠00, FCB header is enabled to support ACK FIFO by (FCB1~FCB3). The FCB is frame control byte. FCB0 is NOT allowed to program but carry a dedicated header (00111b) and SID [2:0] (Serial ID of packet number). FCB1~3 are used for customized information in FCB field. FI D FCB FCB 0 FCB 1 FCB 2 FCB 3 N Figure 16.3 FCB (Frame Control Field) C O FEP: If ENRL = 1, A7130 supports dynamic FIFO. FEP [11:0] is self-generated to add into TX packet. In RX side, FEP[11:0] of the coming TX packet will be detected and stored into LENF [11:0] register. M HEC: If HECS = 1, A7130 supports to self-generated a HEC byte which is a local CRC-8 of the MAC header. This HEC byte is an optional feature to calculate CRC result of MAC Header. HEC is located at the end of the MAC header. 4 b y te s ID c o d e 4 b y te s FE P HEC P a y lo a d (C R C ) 1 ~ 4 b y te s 1 2 b its 1 b y te P h y . 6 4 b y te s 2 b y te s M A C H e ad e r (s elf-g en era te d ) Figure 16.4 HEC (CRC for MAC Header) M IC P H Y H e a d e r ( s e lf - g e n e r a te d ) H eader CRC FC B C P r e a m b le O M AC header A 16.2 Bit Stream Process in FIFO mode A7130 supports 3 optional bit stream process for payload in FIFO mode, they are, (1) CCITT-16 CRC (2) (7, 4) Hamming FEC (3) Data Whitening by XOR PN7 (7-bits Pseudo Random Sequence). The initial seed of PN7 is set by WS [6:0] CRC (Cyclic Redundancy Check): 1. 2. CRC is enabled by CRCS= 1. TX circuitry calculates the CRC value of payload (preamble and ID code are excluded) and transmits 2-bytes CRC value after payload. RX circuitry checks CRC value and shows the result to CRCF. If CRCF=0, received payload is correct, else error occurred. Mar., 2013, Version 1.0 60 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver FEC (Forward Error Correction): FEC is enabled by FECS= 1. Payload and CRC value (if CRCS=1) are encoded by (7, 4) Hamming code. Each 4-bits (nibble) of payload is encoded into 7-bits code word and delivered out automatically. (ex., 64 bytes payload will be encoded to 128 code words, each code word is 7 bits.) RX circuitry decodes received code words automatically. Each code word can correct 1-bit error. Once 1-bit error occurred, FECF=1 (00h). 3. L 1. 2. Data whitening is enabled by WHTS= 1. Payload and CRC value (if CRCS=1) or their encoded code words (if FECS=1) are encrypted by bit XOR operation with PN7. The initial seed of PN7 is set by WS [6:0]. RX circuitry decrypts received payload and 2-bytes CRC (if CRCS=1) automatically. Please noted that user shall set the same WS [6:0] (22h) to TX and RX. 2. EN 1. TI A Data Whitening: FI D 16.3 Transmission Time Based on CRC and FEC options, the transmission time are different. See table 16.1 for details. Payload (bits) 512 512 512 512 CRC (bits) Disable 16 bits Disable 16 x 7 / 4 N ID Code (bits) 32 32 32 32 C O Data Rate = 4 Mbps Data Rate Preamble (bits) 4Mbps 32 32 32 32 FEC Disable Disable 512 x 7 / 4 512 x 7 / 4 Transmission Time / Packet 576 bit X 0.25 us = 144 us 592 bit X 0.25 us = 148 us 960 bit X 0.25 us = 240 us 988 bit X 0.25 us = 247 us M Table 16.1 Transmission time 16.4 Usage of TX and RX FIFO C O In application points of view, A7130 supports 2 options of FIFO arrangement. (1) Easy FIFO (2) Segment FIFO (3) FIFO extension IC For FIFO operation, A7130 supports Strobe command to reset TX and RX FIFO pointer as shown below. User can refer to section 10.5 for details. A6 1 1 A5 1 1 A A7 1 1 M Strobe Command Strobe Command Mar., 2013, Version 1.0 A4 0 1 A3 x x A2 x x A1 X X Description A0 x FIFO write pointer reset (for TX FIFO) x FIFO read pointer reset (for RX FIFO) 61 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 16.4.1 Easy FIFO RX-FIFO (byte) 1 8 16 32 64 FEP[11:0] (03h) 0x00 0x07 0x0F 0x1F 0x3F PSA[5:0] (04h) 0 0 0 0 0 FPM[1:0] (04h) 0 0 0 0 0 FI D Procedures of TX FIFO Transmitting 1. Initialize all control registers (refer A7130 reference code). 2. Set FEP [11:0] = 0x003F for 64-bytes FIFO. 3. Send Strobe command – TX FIFO write pointer reset. 4. MCU writes 64-bytes data to TX FIFO. 5. Send TX Strobe Command and monitor WTR signal. 6. Done. EN Table 16.2 Control registers of Easy FIFO TI A TX-FIFO (byte) 1 8 16 32 64 L In Easy FIFO mode, max FIFO length is 64 bytes. FIFO length is equal to ( FEP [11:0] +1 ) where FEP [11:0] is max 0x003F. User just needs to control FEP [11:0] (03h) and disable PSA and FPM as shown below. A M IC C O M C O N Procedures of RX FIFO Reading 1. When RX FIFO is full, WTR (or FSYNC) can be used to trigger MCU for RX FIFO reading. 2. Send Strobe command – RX FIFO read pointer reset. 3. MCU monitors WTR signal and then read 64-bytes from RX FIFO. 4. Done. Figure 16.5 Easy FIFO Mar., 2013, Version 1.0 62 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 16.4.2 Segment FIFO RX FIFO Length 8 bytes TX FIFO Length 8 bytes 8 bytes 8 bytes 8 bytes 8 bytes 8 bytes 8 bytes 8 bytes PSA[5:0] 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 TI A FEP FEP1 FEP2 FEP3 FEP4 FEP5 FEP6 FEP7 FEP8 FEP[11:0] 0x07 0x0F 0x17 0x1F 0x27 0x2F 0x37 0x3F PSA[5:0] 0 FEP[11:0] 0x0007 FPM[1:0] 0 EN PSA PSA1 PSA2 PSA3 PSA4 PSA5 PSA6 PSA7 PSA8 FI D Segment 1 2 3 4 5 6 7 8 L In Segment FIFO, TX FIFO length is equal to (FEP [11:0] － PSA [5:0]＋1). FPM [1:0] should be zero. This function is very useful for button applications. In such case, each button is used to transmit fixed code (data) every time. During initialization, each fixed code is written into corresponding segment FIFO once and for all. Then, if button is triggered, MCU just assigns corresponding segment FIFO (PSA [5:0] and FEP [11:0]) and issues TX strobe command. Table 16.4 explains the details if TX FIFO is arranged into 8 segments, each TX segment and RX FIFO length are 8 bytes. FPM[1:0] 0 0 0 0 0 0 0 0 Table 16.3 Segment FIFO is arranged into 8 segments C O M C O N Procedures of TX FIFO Transmitting 1. Initialize all control registers (refer A7130 reference code). 2. Issue Strobe command – TX FIFO write pointer reset. 3. MCU writes fixed code into corresponding segment FIFO once and for all. 4. To consign Segment 1, set PSA = 0x00 and FEP= 0x0007 To consign Segment 2, set PSA = 0x08 and FEP= 0x000F To consign Segment 3, set PSA = 0x10 and FEP= 0x0017 To consign Segment 4, set PSA = 0x18 and FEP= 0x001F To consign Segment 5, set PSA = 0x20 and FEP= 0x0027 To consign Segment 6, set PSA = 0x28 and FEP= 0x002F To consign Segment 7, set PSA = 0x30 and FEP= 0x0037 To consign Segment 8, set PSA = 0x38 and FEP= 0x003F 5. Issue TX Strobe Command and monitor WTR signal. 6. Done. A M IC Procedures of RX FIFO Reading 1. When RX FIFO is full, WTR (or FSYNC) is used to trigger MCU for RX FIFO reading. 2. Issue Strobe command – RX FIFO read pointer reset. 3. MCU monitors WTR signal and then read 8-bytes from RX FIFO. 4. Done. Mar., 2013, Version 1.0 63 AMICCOM Electronics Corporation A7130 FI D EN TI A L 2.4GHz FSK/GFSK Security Transceiver A M IC C O M C O N Figure 16.6 Segment FIFO Mode Mar., 2013, Version 1.0 64 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 16.4.3 FIFO Extension A7130 supports FIFO extension up to 4K bytes from the 64 bytes physical TX FIFO and RX FIFO. The FIFO extension length is configured by (FEP [11:0] +1 and PSA [5:0] =0). FPM [1:0] is used to set the FPF threshold which FPF is FIFO Pointer Flag to inform MCU the timing of reading RX FIFO and refilling TX FIFO. TI A Control Registers FEP[7:0] FPM[1:0] PSA[5:0] 00 01 10 11 0 0 0 0 EN For example, if A7130 data rate = 4Mbps and FIFO extension = 256 bytes. TX RX FIFO FIFO FPF Max. SPI FPF Max. SPI Length Length Threshold Data Rate Threshold Data Rate (byte) (byte) Delta = 04 10 Mbps Delta = 60 10 Mbps Delta = 08 10 Mbps Delta = 56 10 Mbps 256 256 Delta = 12 10 Mbps Delta = 52 10 Mbps Delta = 16 8 Mbps Delta = 48 8 Mbps L Please be notice, SPI speed is important to prevent error operation (over-write) in FIFO extension mode. We recommend the min. SPI speed shall be equal or greater than (A7130 on-air data rate + 500Kbps).Please refer to A7130’s reference code (FIFO extension) for details. FI D 0xFF Table 16.4 How to set FIFO extension when A7130 is at 4Mbps data rate A M IC C O M C O N Procedures of TX FIFO Extension 1. Initialize all control registers (refer A7130 reference code). 2. Set FEP [11:0] = 0x0FF for 256-bytes FIFO extension. 3. Set FPM [1:0] = 11 for FPF threshold. 4. Set CKO Register = 0x12 5. Issue Strobe command – TX FIFO write pointer reset. 6. MCU writes 1st 64-bytes TX FIFO. 7. Issue TX Strobe command. 8. MCU monitors FPF from A7130’s CKO pin. 9. FPF triggers MCU to write 2nd 48-bytes TX FIFO. 10. Monitor FPF. 11. FPF triggers MCU to write 3rd 48-bytes TX FIFO. 12. Monitor FPF. 13. FPF triggers MCU to write 4th 48-bytes TX FIFO. 14. Monitor FPF. 15. FPF triggers MCU to write 5th 48-bytes TX FIFO. 16. Done. Mar., 2013, Version 1.0 65 AMICCOM Electronics Corporation A7130 A M IC C O M C O N FI D EN TI A L 2.4GHz FSK/GFSK Security Transceiver Figure 16.7 TX FIFO Extension Mar., 2013, Version 1.0 66 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver TI A FI D EN Initialize all control registers (refer A7130 reference code). Set FEP [11:0] = 0x0FF for 256-bytes FIFO extension. Set FPM [1:0] = [11b] for FPF threshold. Set CKO Register = 0x12 Issue Strobe command – RX FIFO read pointer reset. Issue RX Strobe command. MCU monitors FPF from A7130’s CKO pin. FPF triggers MCU to read 1st 48-bytes RX FIFO. Monitor FPF. FPF triggers MCU to read 2nd 48-bytes RX FIFO. Monitor FPF. FPF triggers MCU to read 3rd 48-bytes RX FIFO. Monitor FPF. FPF triggers MCU to read 4th 48-bytes RX FIFO. Monitor FPF. FPF triggers MCU to read 5th 48-bytes RX FIFO. Monitor WTR falling edge or WTR = low, read the rest 16-bytes RX FIFO Done. A M IC C O M C O N 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. L Procedures of RX FIFO Reading Mar., 2013, Version 1.0 67 AMICCOM Electronics Corporation A7130 FI D EN TI A L 2.4GHz FSK/GFSK Security Transceiver A M IC C O M C O N Figure 16.8 RX FIFO Extension Mode Mar., 2013, Version 1.0 68 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 17. ADC (Analog to Digital Converter) A7130 has built-in 8-bits ADC for RSSI measurement, internal thermal sensor and external voltage input by enabling ADCM. To measure RSSI signal, user can just use the recommended values of ADC from Table 17.1. Please note that ADC clock can be selected by setting FSARS (4MHz or 8MHz). The ADC converting time is 20 x ADC clock periods. ARSSI (01h) 1 ADCM ERSSM FSARS CDM Standby Mode (01h) (1Ch) (1Fh) (1Fh) 1 1 0 1 Thermal sensor Table 17.1 Setting of RSSI measurement RX Mode RSSI L RSS (1Ch) 1 TI A XADS (1Fh) 0 FI D EN XADS: Measure the external voltage input when XADS = 1. Measure the internal thermal sensor or RSSI when= XADS = 0. RSS: Enable RSSI measurement when RSS = 1; Disable RSSI measurement and measure the internal thermal sensor when RSS =0. ARSSI: Auto RSSI measurement when ARSSI = 1 ADCM: Please ignore this and set ARSSI =1 for RSSI measurement. Enable ADC measurement when ADCM = 1 and then auto clear after measurement. ERSSM: RSSI measurement ending by SYNC_OK when ERSSM = 1. RSSI measurement ending by RX packet when ERSSM = 0 (recommended). FSARS: Set FSARS = 0 as the recommended as the Table 17.1 CDM: Please ignore this and set ARSSI =1 for RSSI measurement. Measure ADC sginal continously when CDM = 1. Measure ADC sginal one time when CDM = 0. N 17.1 RSSI Measurement C O A7130 supports 8-bits digital RSSI to detect RF signal strength. RSSI value is stored in ADC [7:0] (1Eh). Fig 17.1 shows a typical plot of RSSI reading as a function of input power. Be aware RSSI accuracy is about ± 6dBm. ADC value Curve (AGC on,25℃) M 300 150 O 200 C ADC Value 250 Average IC 100 A M 50 Mar., 2013, Version 1.0 0 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 Input Power (dBm) 69 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver ADC value Curve (AGC off,25℃) 250 150 100 L Average TI A ADC Value 200 0 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 EN 50 -35 -30 -25 -20 -15 -10 -5 0 5 10 FI D Input Power (dBm) Figure 17.1 Typical RSSI characteristic C O N Please refer the following steps to measure RSSI or contact AMICCOM’s FAE for more details. Prepare ADC for measuring RSSI: To measure RSSI, please set wanted FRXLO firstly. 1. Set XADS =0 and RSS =1. Let ADC to measure RSSI signal. 2. Set ARSSI =1 to measure RSSI automatically. 3. Set ERSSM = 1. The RSSI signal is hold after SYNC_OK. The RSSI value will be feed to ADC. RX-Strobe RX Mode C Strobe CMD (SCS,SCK,SDIO) O M Auto RSSI measurement for RX Power of the coming packet: 1. Send RX Strobe command. 2. Once frame sync (FSYNC) is detected or exiting RX mode, user can read digital RSSI value from ADC [7:0] for RX power of the coming packet. MCU Read ADC[7:0] RX Ready Time Received Packet IC RF-IN Read 8-bits RSSI value M GIO1 Pin - WTR (GPIO1S[3:0]=0000) A GIO2 Pin - FSYNC (GPIO2S[3:0]=0001) T0 T1 T2 T3 T4 T0-T1: Settling Time T2-T3: Receiving Packet T3 : Exit RX mode automatically in FIFO mode T3-T4: MCU read RSSI value @ ADC [7:0] Figure 17.2 RSSI Measurement of RX RSSI of the coming packet. Mar., 2013, Version 1.0 70 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver RX-Strobe MCU Read ADC[7:0] No Packet RFI Pin Min. 140 us GIO1 Pin - WTR (GPIO1S[3:0]=0000) MCU reads 8-bits RSSI value that is refresh every 40 us EN GIO2 Pin - FSYNC (GPIO2S[3:0]=0001) T1 T0 TI A Strobe CMD (SCS,SCK,SDIO) L Auto RSSI measurement for Background Power: 1. Send RX Strobe command. 2. Stay in RX mode at least 140 us and then exiting RX mode. User can read digital RSSI value from ADC [7:0] for the background power. FI D T0-T1: MCU Delay Loop from PLL to RX mode for RSSI measurment T1 : Auto RSSI Measurment is done by 8-times average. MCU can read RSSI value from ADC [7:0] C O N Figure 17.3 Measurement of Background RSSI. 17.2 Internal thermal sensor (temperature) measurement C O M A7130 has an internal thermal sensor to measure ambient temperature. However the temperature is related value not absolute. Please refer the application note or contact AMICCOM’s FAE if user uses it to measure temperature. How to setting ADC to measure temperature: 1. Please stay in STBY mode. 2. Set XADS = 0 and RSS = 0. Let ADC measure the internal thermal signal. 3. Set CDM = 0 or 1 and let ADCM = 1 to measure signal Read ADC when ADCM reset to 0 (ADC measure is ending) if CDM =0. Read ADC after 40us setting ADCM=1. The ADC updates continuously. IC 17.3 External voltage input measurement A M A7130 can measure external voltage from RSSI (pin1) and it means that user cannot use RSSI measurement function if external voltage function is selected. Please contact AMICCOM’s FAE for more detail function. How to setting ADC to measure temperature: 1. Please stay in STBY mode. 2. Set XADS = 1. Let ADC measure the external voltage input (from RSSI pin). 3. Set CDM = 0 or 1 and let ADCM = 1 to measure signal Read ADC when ADCM reset to 0 (ADC measure is ending) if CDM =0. Read ADC after 40us setting ADCM = 1. The ADC updates continuously. Mar., 2013, Version 1.0 71 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 18. Battery Detect A7130 has a built-in battery detector to check supply voltage (REGI pin). The detecting range is 2.0V ~ 2.7V into 8 levels. Battery detect Register (Address: 2Ch) R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Battery detect W R LVR -- RGV1 RGV1 RGV0 RGV0 QDS BDF BVT2 BVT2 BVT1 BVT1 BVT0 BVT0 BD_E BD_E TI A BVT [2:0]: Battery voltage detect threshold. [000]: 2.0V. [001]: 2.1V. [010]: 2.2V. [011]: 2.3V. [100]: 2.4V. [101]: 2.5V. [110]: 2.6V. [111]: 2.7V. L Name EN BD_E: Battery Detect Enable. [0]: Disable. [1]: Enable. It will be clear after battery detection is triggered. BDF: Battery detection flag. [0]: Battery voltage less than threshold. [1]: Battery voltage greater than threshold. N Set A7130 in standby or PLL mode. Set BVT [2:0] = [001] and enable BD_E = 1. After 5 us, BD_E is auto clear. User can read BDF or output BDF to GIO1 pin or CKO pin. If REGI pin > 2.1V, BDF = 1 (battery high). Else, BDF = 0 (battery low). A M IC C O M C O 1. 2. 3. 4. FI D Below is the procedure to detect low voltage input (ex. below 2.1V): Mar., 2013, Version 1.0 72 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 19. Auto-ack and auto-resend A7130 supports auto-resend and auto-ack scheme by enable EAK = 1 (auto-ack) and EAR = 1 (auto-resend). In application points of view, this feature is also ok to enable together with other feature options like FCB and/or EDRL (dynamic FIFO). 19.1 Basic FIFO plus auto-ack auto-resend M IC C O M C O N FI D EN TI A L Set EAF = 0, EAK = 1 and EAR = 1 to enable auto-ack and auto-resend. Please refer to the below TX and ACK packet format of the sender and the receiver site respectively. 19.2 Advanced FIFO plus auto-ack and auto-resend A In addition to set EAF = 0, EAK = 1 and EAR = 1 to enable auto-ack and auto-resend. User can also enable an optional MAC header (FCB field) in the TX packet together with auto-ack and auto resend scheme. Please refer to the below TX and ACK packet format of the sender and the receiver site. Mar., 2013, Version 1.0 73 AMICCOM Electronics Corporation A7130 A M IC C O M C O N FI D EN TI A L 2.4GHz FSK/GFSK Security Transceiver Mar., 2013, Version 1.0 74 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 19.3 WTR Behavior during auto-ack and auto-resend If auto-ack and auto-resend are enabled (EAR = EAK = 1), WTR represents a completed transmission period and CWTR is a debug signal which represents the cyclic TX period and cyclic RX period. Please refer to the below timing diagrams for details. C O N FI D EN TI A L The sender site (auto-resend) A M IC C O M The receiver site (auto-ack) Remark: Refer to 3Bh for ARD[7:0] setting (auto resend delay). Refer to 3Fh for RND[7:0] setting (random seed for resend interval). Refer to 3Ah for EAK (enable auto-ack). Refer to 3Ah for EAR (enable auto-resend). Refer to 0Bh for VKM and VPM. Mar., 2013, Version 1.0 75 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 19.6 Examples of auto-ack and auto-resend Once EAK and EAR are enabled, below case 1 ~ case 3 illustrate the most common cases as a timing reference (assume ARD = 800 us) in two ways radio communications. Always success Success in second packet A M IC C O M C O N FI D EN TI A L Mar., 2013, Version 1.0 76 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver always resend failure A M IC C O M C O N FI D EN TI A L Mar., 2013, Version 1.0 77 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 20. RC Oscillator A7130 has an internal RC oscillator to supports WOR (Wake On RX) and TWOR (Timer Wake On RX) function. RCOSC_E (09h) is used to enable RC oscillator. WORE (01h) is used to enable WOR function and TWORE (09h) is used to enable TWOR function. After done calibrations of RC oscillator, WOR and TWOR function can be operated from -40℃ to 85℃. Max 4.2K 8007.68 85 Unit Hz ms ms ℃ Note [( WOR_SL [9:0] ) +1] x 7.8 ms [( WOR_AC [5:0] ) +1] x 244 us After calibration. L Min 3.8K 7.82 0.244 -40 TI A Parameter Calibrated Freq. Sleep period RX period Operation temperature 20.1 WOR Function EN When WOR is enabled (WORE = 1 and RCOSC_E =1), A7130 periodically wakes up from sleep and listen (auto-enter RX mode) for incoming packets without MCU interaction. Therefore, A7130 will stay in sleep mode based on WOR_SL timer and RX mode based on WOR_AC timer unless a packet is received. Strobe CMD (SCS,SCK,SDIO) N FI D The internal RC oscillator used for the WOR function varies with temperature and CMOS process deviation. In order to keep the frequency as accurate as possible, the RC oscillator shall be calibrated (CALWC=1) whenever possible. After done calibrations, MCU shall set WORE=1 and issue sleep strobe command to start WOR function. After a period (WOR_SL) in sleep mode, the device goes to RX mode to check coming packets. And then, A7130 is back to sleep mode for the next WOR cycle. To end up WOR function, MCU just needs to set WORE = 0. Beware, please turn on MSCRC (21h, CRC data filtering) when CRCS = 1 (20h, CRC select) in WOR function. sleep C O RF In Pin M GIO1 -- WTR GIO1S[3:0]=0000 Strobe cmd No Command Required Sleep WOT_SL[9:0] RX O Sleep WOR_SL[9:0] Start WOR (sleep strobe) Coming packet RX A M IC C End of WOR (set WORE = 0) Mar., 2013, Version 1.0 78 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 20.2 TWOR Function FI D EN TI A L The RC oscillator inside A7130 can also be used to supports programmable TWOR (Timer Wake-On, TWORE=1) function which enables A7130 to output a periodic square wave from GIO1 (or GIO2). The duty cycle of this square wave is set by WOR_AC (08h) or WOR_SL (08h and 07h) regarding to TSEL (09h). User can use this square wave to wake up MCU or other purposes. 21. AES128 Security Packet N A7130 has a built-in AES128 co-processor to generate a security packet by a general purpose MCU. In addition to support 128-bits key length (AES128), A7130 also support a proprietary 32-bits key length called AES32. O M C O Software procedure to use AES128. Step1: Write 16-bytes AES128 key to KEYI [127:0] (36h) Step2: Set AESS=1 (3Eh) to select standard AES128 Step3. Set AKFS=0 (3Eh) to disable attaching AES128 KEYI [127:0] into the TX packet. Step4: Set EDCRS=1 (3Eh) to enable AES co-processor. Step5: Write plain text to TX FIFO Step6: Issue TX strobe command and then A7130 will execute AES128 encryption and deliver the cipher text without latency. Step7: In RX side with the same configurations, A7130 will execute AES128 decryption and store plain text back to RX FIFO. IC C Remark 1. The unit size of AES128 encryption packet is 16-bytes. 2. In TX side, if plain text is not dividable by 16-bytes, i.e. 5-bytes only, the TX packet is complement to be 16-bytes. 3. In RX side, the coming cipher text will be decrypted and restore 5-bytes plain text back to RX FIFO. A M Software procedure to use AES32. Step1: Write 4-bytes AES128 key to KEYI [31:0] (36h) Step2: Set AESS=0 (3Eh) to select proprietary AES32. Step3. Set AKFS=0 (3Eh) to not attach AES128 KEYI [31:0] to the wanted TX packet. Step4: Set EDCRS=1 (3Eh) to enable AES co-processor. Step5: Write plain text to TX FIFO Step6: Issue TX strobe command and then A7130 will execute AES32 encryption and deliver the cipher text without latency. Step7: In RX side with the same configurations, A7130 will execute AES32 decryption and store plain text back to RX FIFO. Remark 1. The unit size of AES32 encryption packet is 4-bytes. 2. In TX side, if plain text is not dividable by 4-bytes, i.e. 5-bytes only, the TX packet is complement to 8-bytes. 3. In RX side, the coming cipher text will be decrypted and restore 5-bytes plain text back to RX FIFO. Mar., 2013, Version 1.0 79 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 22. Application circuit 22.1 MD7130-A01 GIO2 GIO1 17 16 TI A CKO J2 1 2 J3 CON/2P 2.0 GIO1 GIO2 CKO REGI N RFC 12 SCK XO XI 9 CP SCK SCS A7130 10 8 7 6 C7 2.2uF 11 SCS C O VDD_PLL 5 C5 100pF 13 VDD_D A7130PKG RFO SDIO 14 SDIO RFI 4 15 GND BP_BG 3 VDD_A 1 2 CON/2P 2.0 EN VIN 18 BP_RSSI 2 C15 1.8pF J1 CON/10P 2.0 FI D 1 L2 2.7nH 1 2 3 4 5 6 7 8 9 10 U1 VDD_A TP1 ANTENNA ANT VDD_A C2 100pF VDD_VCO C1 470pF 19 C3 4.7uF VIN GND CKO GIO2 GIO1 SDIO SCK SCS GND GND 2.2uF 20 C4 L AMICCOM’s ref. design module, MD7130-A01, max 5 dBm output power, application circuit example. C9 NC C8 2.2nF Y1 NC C12 VDD_A R1 NC C13 NC NC Y2 NC C10 0.1uF C11 100pF 4 3 GND 1 GND 2 Y3 16MHz XTAL_3.2*2.5 M IC C O M C6 0.1uF 4 3 GND GND 2 A 1 Remark 1. 2. 3. 4. RF Matching to 50Ω. RX and TX signal are combined internally to RFI pin only so that RFSP bit = 0 (DASP0 register = 0x34). Recommend 16MHz crystal with 18 pF Cload. Recommend to let C12 and C13 NC because of enabling on-chip Xtal Capacitors by (INTXC = 1 and CSXTAL = [10100]). Mar., 2013, Version 1.0 80 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 22.2 MD7130-F07 AMICCOM’s ref. design module, MD7130-F07, typical 17 dBm output power together with a range extendor A7700. 3 TX SW C14 0.1uF C15 NC NC REGI 33 NC BG 3 RFO GND VDD_PA VDD_A NC VDD_PA 4 12 11 RFI 10 9 8 7 6 5 PA_IN C9 1.2pF REGI33 O L 19 REGI33 16 GIO1 GIO1 GIO2 XO XI 9 10 1 2 16MHz Y2 16MHz C30 0.1uF 1 2 4 1 3 GND GND 2 B CRYSTAL/5*3.2 C1 2.2pF J2 REGI33 CKO or GND GIO2 GIO1 SDIO SCK SCS TX SW RX SW GND C34 NC 1 2 3 4 5 6 7 8 9 10 C37 NC CON/10P 2.0 C57 100pF Title Size A4 Date: File: 2 A7130 3 MD7130-F07-05(2L) Number A Revision 2012.01.12 12-Jan-2012 Sheet of C:\Docu ments and Settings\ac0086\桌面 \MD7130~2.DDB Drawn By: 4 C Remark C36 NC C Y3 REGI33 C8 C7 C13 NC 8.2pF 0.1uF 1 R11 NC R12 0R M L1 4.7nH L2 3nH RFI CKO LNA_OUT 0R A7700 A C38 NC L3 RFO C O TX SW BGS ANT VDD_BA 8.2pF GND 2 GND C42 NC 1 TRX HGM C25 1pF NC L8 2.4nH RX SW U2 C33 IC RF matching to 50Ω. RX and TX signal are separated to RFI pin and RFO pin so that RFSP bit = 1 (DASP0 register = 0x74). Recommend 16MHz crystal with 18 pF Cload. Recommend to let C34 and C37 NC because of enabling on-chip Xtal Capacitors by (INTXC = 1 and CSXTAL = [10100]). A M 1. 2. 3. 4. N 13 14 16 C6 B SCS Y1 R10 NC C31 VDD_A 2.2nF C32 NC R6 6.8K BG 15 L7 2.4nH C19 1.5pF 18 CKO FI D C11 RX SW C12 SCK 11 SCS VDD_A TP1 TEST POINT 1.5pF VDD_PLL C29 100pF 12 SCK 8 RFC 6 C RFO 5 C20 2.2uF 13 VDD_D A7130PKG SDIO 14 SDIO RFI 4 15 GND CP C10 1pF TI A L10 3.3nH 3 L9 3.3nH 47 BP_BG VDD_VCO R1 PA_IN BP_RSSI 2 EN LNA_OUT D U1 1 C16 1pF 20 VDD_A C2 100pF VDD_A C3 1nF 17 GIO2 C18 2.2uF C5 4.7uF CKO D 4 REGI 2 7 1 Mar., 2013, Version 1.0 81 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver TI A EN FI D N M C O Analog to Digital Converter Auto IF Frequency Compensation Automatic Gain Control Bit Error Rate Bandwidth Carrier Detect Channel Step Cyclic Redundancy Check Direct Current Forward Error Correction First in First out Frequency Shift Keying Identifier Intermediate Frequency Industrial, Scientific and Medical Local Oscillator Micro Controller Unit Phase Frequency Detector for PLL Phase Lock Loop Power on Reset Receiver Receiver Local Oscillator Received Signal Strength Indicator Serial to Parallel Interface System Clock for digital circuit Transmitter Transmitter Radio Frequency Voltage Controlled Oscillator Crystal Oscillator Crystal Reference frequency Crystal O ADC AIF FC AGC BER BW CD CHSP CRC DC FEC FIFO FSK ID IF ISM LO MCU PFD PLL POR RX RXLO RSSI SPI SYCK TX TXRF VCO XOSC XREF XTAL L 23. Abbreviations IC Part No. C 24. Ordering Information A71C30AQFI/Q Package Units Per Reel / Tray 3K A71C30AQFI QFN20L, Pb Free, Tray, -40℃〜85℃ 490EA A71C30AH Die form, -40℃〜85℃ 100EA A M QFN20L, Pb Free, Tape & Reel, -40℃〜85℃ Mar., 2013, Version 1.0 82 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 25. Package Information QFN 20L (4 X 4 X 0.8mm) Outline Dimensions TOP VIEW BOTTOM VIEW 0.25 C D 11 11 15 L L 15 D2 10 TI A 16 10 EN e E E2 16 20 6 6 5 5 1 e b 0.10 M C A B N 1 FI D 0.25 C 20 Seating Plane C Dimensions in inches M Symbol Min Dimensions in mm Min Nom Max 0.030 0.032 0.70 0.75 0.80 0.000 0.001 0.002 0.00 0.02 0.05 O 0.028 C IC M Max A b A Nom A1 A3 Mar., 2013, Version 1.0 y C A3 A1 A C O // 0.10 C 0.008 REF 0.203 REF 0.007 0.010 0.012 0.18 0.25 0.30 D 0.154 0.158 0.161 3.90 4.00 4.10 D2 0.075 0.079 0.083 1.90 2.00 2.10 E 0.154 0.158 0.161 3.90 4.00 4.10 E2 0.075 0.079 0.083 1.90 2.00 2.10 0.020 0.30 0.020 BSC e L y 0.012 0.016 0.003 0.50 BSC 0.40 0.50 0.08 83 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 26. Top Marking Information A71C30AQFI L : A71C30AQFI : 20 : QFN : 4*4 mm : Laser Mark : Arial TI A Part No. Pin Count Package Type Dimension Mark Method Character Type A M IC C O M C O N FI D EN ¡ ¡ ¡ ¡ ¡ ¡ Mar., 2013, Version 1.0 84 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver N FI D EN TI A L 27. Reflow Profile A M IC C O M C O Actual Measurement Graph Mar., 2013, Version 1.0 85 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 28. Tape Reel Information 8±0.1 QFN 4*4 8±0.1 QFN 5*5 8±0.1 SSOP 12±0.1 B0 P0 3.2 5±0.1 4.35 ±0.1 5.25 ±0.1 3.25 ±0.1 4.35 ±0.1 5.25 ±0.1 4±0.2 2±0.1 1.5±0.1 4±0.2 2±0.1 1.5±0.1 4±0.2 P1 D0 D1 1.5 E F 1.75 ±0.1 1.75 ±0.1 1.75 ±0.1 1.75 ±0.1 5.5 ±0.05 5.5 ±0.05 5.5 ±0.05 N QFN3*3 A0 1.5 C O P 2±0.1 1.5±0.1 1.5 8.2±1 8.8±1.5 4.0±0.1 2.0±0.1 1.5±0.1 1.5±0.1 W K0 Unit: mm Cover tape width t 0.3 9.3±0.1 ±0.05 0.3 12±0.3 9.3±0.1 ±0.05 0.3 12±0.3 9.3±0.1 ±0.05 0.3 13.3 7.5±0.1 16±0.1 2.1±0.4 ±0.05 ±0.1 12±0.3 1.25 ±0.1 1.2 5±0.1 1.25 ±0.1 M TYPE FI D EN TI A L Cover / Carrier Tape Dimension O REEL DIMENSIONS R M L IC C T N A D K M G Unit: mm TYPE G N M D K L R QFN 12.9±0.5 102 REF±2.0 2.3±0.2 13.15±0.35 2.0±0.5 330±3.0 19.6±2.9 SSOP 16.3±1 102 REF±2.0 2.3±0.2 13.15±0.35 2.0±0.5 330±3.0 19.6±2.9 Mar., 2013, Version 1.0 86 AMICCOM Electronics Corporation A7130 2.4GHz FSK/GFSK Security Transceiver 29. Product Status Product Status Planned or Under Development Definition This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary Engineering Samples and First Production This data sheet contains preliminary data, and supplementary data will be published at a later date. AMICCOM reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. No Identification Noted Full Production Obsolete Not In Production This data sheet contains the final specifications. AMICCOM reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains specifications on a product that has been discontinued by AMICCOM. The data sheet is printed for reference information only. IC C O M C O N FI D EN TI A L Data Sheet Identification Objective RF ICs AMICCOM A M Headquarter A3, 1F, No.1, Li-Hsin Rd. 1, Hsinchu Science Park, Taiwan 30078 Tel: 886-3-5785818 Shenzhen Office Rm., 2003, DongFeng Building, No. 2010, Shennan Zhonglu Rd., Futian Dist., Shenzhen, China Post code: 518031 Web Site http://www.amiccom.com.tw Mar., 2013, Version 1.0 87 AMICCOM Electronics Corporation