A71X06AQFI/Q

A7106 2.4G FSK/GFSK Transceiver Document Title A7106 Data Sheet, 2.4GHz FSK/GFSK Transceiver with 500Kbps data rate Revision History Rev. No. History Issue Date Remark 0.0 Initial issue. Aug., 2009 Objective 0.1 Add chapter 11, add 15.5 RSSI calibration Feb., 2010 Preliminary 0.2 Update BD info Jun., 2010 Preliminary 0.3 Add WOR function May, 2010 Preliminary 0.4 Add Shenzhen office address and modify tape reel information. Jul., 2011 Preliminary 1.0 Update WOR procedure in page 81. Full production. Sep., 2011 Full production. 1.1 Update Xtal tolerance in Ch8. Oct., 2011 Full production. 1.2 Modify order info A71C06BH to A71C06AH and configurations of table 14.5. Nov., 2011 Full production. Important Notice: AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such applications is understood to be fully at the risk of the customer. NOV. 2011, Version 1.2 1 AMICCOM Electronics Corporation A7106 2.4G FSK/GFSK Transceiver Table of Contents 1. General Description....................................................................................................................................................... 5 2. Typical Applications ....................................................................................................................................................... 5 3. Feature ......................................................................................................................................................................... 5 4. Pin Configurations ......................................................................................................................................................... 6 5. Pin Description (I: input; O: output, I/O: input or output)................................................................................................... 7 6. Chip Block Diagram....................................................................................................................................................... 8 7. Absolute Maximum Ratings............................................................................................................................................ 9 8. Electrical Specification..................................................................................................................................................10 9. Control Register ...........................................................................................................................................................12 9.1 Control register table............................................................................................................................................12 9.2 Control register description ..................................................................................................................................14 9.2.1 Mode Register (Address: 00h)..................................................................................................................14 9.2.2 Mode Control Register (Address: 01h)......................................................................................................14 9.2.3 Calibration Control Register (Address: 02h)..............................................................................................15 9.2.4 FIFO Register I (Address: 03h).................................................................................................................15 9.2.5 FIFO Register II (Address: 04h)................................................................................................................15 9.2.6 FIFO DATA Register (Address: 05h) .........................................................................................................15 9.2.7 ID DATA Register (Address: 06h)................................................................................................................16 9.2.8 RC OSC Register I (Address: 07h) .............................................................................................................16 9.2.9 RC OSC Register II (Address: 08h).............................................................................................................16 9.2.10 RC OSC Register III (Address: 09h)..........................................................................................................16 9.2.11 CKO Pin Control Register (Address: 0Ah) .................................................................................................17 9.2.12 GIO1 Pin Control Register I (Address: 0Bh)...............................................................................................17 9.2.13 GIO2 Pin Control Register II (Address: 0Ch) .............................................................................................18 9.2.14 Clock Register (Address: 0Dh)..................................................................................................................19 9.2.15 Data Rate Register (Address: 0Eh) ...........................................................................................................20 9.2.16 PLL Register I (Address: 0Fh)...................................................................................................................20 9.2.17 PLL Register II (Address: 10h)..................................................................................................................20 9.2.18 PLL Register III (Address: 11h) .................................................................................................................20 9.2.19 PLL Register IV (Address: 12h).................................................................................................................21 9.2.20 PLL Register V (Address: 13h) ...............................................................................................................21 9.2.21 TX Register I (Address: 14h).....................................................................................................................21 9.2.22 TX Register II (Address: 15h)....................................................................................................................21 9.2.23 Delay Register I (Address: 16h) ................................................................................................................22 9.2.24 Delay Register II (Address: 17h) ...............................................................................................................22 9.2.25 RX Register (Address: 18h) ......................................................................................................................23 9.2.26 RX Gain Register I (Address: 19h)............................................................................................................23 9.2.27 RX Gain Register II (Address: 1Ah)...........................................................................................................24 9.2.28 RX Gain Register III (Address: 1Bh)..........................................................................................................24 9.2.29 RX Gain Register IV (Address: 1Ch) .........................................................................................................24 9.2.30 RSSI Threshold Register (Address: 1Dh) ..................................................................................................24 9.2.31 ADC Control Register (Address: 1Eh) .......................................................................................................25 9.2.32 Code Register I (Address: 1Fh) ................................................................................................................25 9.2.33 Code Register II (Address: 20h)................................................................................................................25 9.2.34 Code Register III (Address: 21h)...............................................................................................................26 9.2.35 IF Calibration Register I (Address: 22h).....................................................................................................26 9.2.36 IF Calibration Register II (Address: 23h)....................................................................................................26 9.2.37 VCO current Calibration Register (Address: 24h).......................................................................................26 9.2.38 VCO Single band Calibration Register I (Address: 25h) .............................................................................27 9.2.39 VCO Single band Calibration Register II (Address: 26h) ............................................................................27 9.2.40 Battery detect Register (Address: 27h)......................................................................................................27 9.2.41 TX test Register (Address: 28h) ................................................................................................................28 9.2.42 Rx DEM test Register I (Address: 29h)......................................................................................................28 9.2.43 Rx DEM test Register II (Address: 2Ah) ....................................................................................................28 NOV. 2011, Version 1.2 2 AMICCOM Electronics Corporation A7106 2.4G FSK/GFSK Transceiver 9.2.44 Charge Pump Current Register (Address: 2Bh).........................................................................................28 9.2.45 Crystal test Register (Address: 2Ch) .........................................................................................................29 9.2.46 PLL test Register (Address: 2Dh)..............................................................................................................29 9.2.47 VCO test Register I (Address: 2Eh)...........................................................................................................29 9.2.48 VCO test Register II (Address: 2Fh)..........................................................................................................30 9.2.49 IFAT Register (Address: 30h)....................................................................................................................30 9.2.50 RScale Register (Address: 31h)................................................................................................................30 9.2.51 Filter test Register (Address: 32h).............................................................................................................30 9.2.52 Filter test Register II (Address: 33h)..........................................................................................................30 10. SPI.............................................................................................................................................................................31 10.1 SPI Format ........................................................................................................................................................31 10.2 SPI Timing Characteristic ...................................................................................................................................32 10.3 SPI Timing Chart................................................................................................................................................32 10.3.1 Timing Chart of 3-wire SPI........................................................................................................................33 10.3.2 Timing Chart of 4-wire SPI........................................................................................................................33 10.4 Strobe Commands .............................................................................................................................................33 10.4.1 Strobe Command - Sleep Mode ................................................................................................................34 10.4.2 Strobe Command - ldle Mode ...................................................................................................................34 10.4.3 Strobe Command - Standby Mode ............................................................................................................35 10.4.4 Strobe Command - PLL Mode...................................................................................................................35 10.4.5 Strobe Command - RX Mode....................................................................................................................36 10.4.6 Strobe Command - TX Mode ....................................................................................................................36 10.4.7 Strobe Command – FIFO Write Pointer Reset ...........................................................................................36 10.4.8 Strobe Command – FIFO Read Pointer Reset ...........................................................................................37 10.5 Reset Command................................................................................................................................................37 10.6 ID Accessing Command .....................................................................................................................................38 10.6.1 ID Write Command...................................................................................................................................38 10.6.2 ID Read Command ..................................................................................................................................38 10.7 FIFO Accessing Command.................................................................................................................................38 10.7.1 TX FIFO Write Command .........................................................................................................................39 10.7.2 Rx FIFO Read Command.........................................................................................................................39 11. State machine.............................................................................................................................................................39 11.1 Key states..........................................................................................................................................................40 11.1.1 Standby mode ..........................................................................................................................................40 11.1.2 Sleep mode..............................................................................................................................................40 11.1.3 ldle mode .................................................................................................................................................41 11.1.4 PLL mode.................................................................................................................................................41 11.1.5 TX mode ..................................................................................................................................................41 11.1.6 RX mode..................................................................................................................................................41 11.1.7 CAL mode................................................................................................................................................42 11.2 Normal FIFO Mode ............................................................................................................................................42 11.3 Quick FIFO Mode...............................................................................................................................................44 11.4 Power Saving FIFO Mode ..................................................................................................................................46 11.5 Quick Direct Mode..............................................................................................................................................47 12 Crystal Oscillator .........................................................................................................................................................51 12.1 Use External Crystal ..........................................................................................................................................51 12.2 Use external clock .............................................................................................................................................51 13. System Clock .............................................................................................................................................................52 13.1 Bypass clock generation ....................................................................................................................................53 13.2 Enable clock generation.....................................................................................................................................54 14. Transceiver LO Frequency..........................................................................................................................................56 14.1 LO Frequency Setting ........................................................................................................................................57 14.2 IF Side Band Select ...........................................................................................................................................59 14.2.1 Auto IF Exchange.....................................................................................................................................60 14.2.2 Fast Exchange.........................................................................................................................................61 14.3 Frequency Compensation ..................................................................................................................................62 15. Calibration..................................................................................................................................................................63 15.1 Calibration Procedure ........................................................................................................................................63 15.2 IF Filter Bank Calibration....................................................................................................................................63 NOV. 2011, Version 1.2 3 AMICCOM Electronics Corporation A7106 2.4G FSK/GFSK Transceiver 15.3 VCO Current Calibration ....................................................................................................................................63 15.4 VCO Bank Calibration........................................................................................................................................64 15.5 RSSI Calibration ................................................................................................................................................64 16. FIFO (First In First Out)...............................................................................................................................................65 16.1 Packet Format ...................................................................................................................................................65 16.2 Bit Stream Process ............................................................................................................................................66 16.3 Transmission Time.............................................................................................................................................67 16.4 Usage of TX and RX FIFO .................................................................................................................................67 16.4.1 Easy FIFO ...............................................................................................................................................68 16.4.2 Segment FIFO .........................................................................................................................................69 16.4.3 FIFO Extension........................................................................................................................................70 17. ADC (Analog to Digital Converter) ...............................................................................................................................75 17.1 RSSI Measurement............................................................................................................................................75 17.2 Carrier Detect ....................................................................................................................................................77 18. Battery Detect ............................................................................................................................................................78 19 TX power setting .........................................................................................................................................................79 20 RC Oscillator...............................................................................................................................................................80 20.1 WOR Function...................................................................................................................................................81 20.2 TWOR Function .................................................................................................................................................82 21. Application circuit........................................................................................................................................................83 22. Abbreviations..............................................................................................................................................................85 23. Ordering Information...................................................................................................................................................85 24. Package Information...................................................................................................................................................86 25. Top Marking Information..............................................................................................................................................87 26. Reflow Profile .............................................................................................................................................................88 27. Tape Reel Information.................................................................................................................................................89 28. Product Status............................................................................................................................................................91 NOV. 2011, Version 1.2 4 AMICCOM Electronics Corporation A7106 2.4G FSK/GFSK Transceiver 1. General Description A7106 is a high performance and low cost 2.4GHz ISM band wireless transceiver. This device integrates both high sensitivity receiver (- 95dBm @ 500Kbps) and high efficiency power amplifier (up to 1dBm). In low data rate application, A7106 has special strength for long LOS (line-of-sight) distance because of its ultra high sensitivity (-107 dBm @ 2Kbps, - 104 dBm @ 25Kbps) with no requirement of external LNA or PA. Based on Data Rate Register (0x0E), user can configure on-air data rates from 2Kbps to 500Kbps. A7106 supports fast settling time (130 us) for frequency hopping system. For packet handling, A7106 has built-in separated 64-bytes TX/RX FIFO (could be extended to 256 bytes) for data buffering and burst transmission, CRC for error detection, FEC for 1-bit data correction per code word, RSSI for clear channel assessment, data whitening for data encryption / decryption, the internal RC oscillator for WOR (Wake-On-RX) to support periodically wake up from sleep and listen (auto-enter RX mode) for incoming packets without MCU interaction. Those functions are very easy to use while developing a wireless system. All features are integrated in a small QFN 4X4 20 pins package. A7106’s control registers can be easily accessed via 3-wire or 4-wire SPI bus. For power saving, A7106 supports sleep mode, idle mode, standby mode. For easy-to-use, A7106 has an unique SPI command set called Strobe command that are used to control internal state machine. Based on Strobe commands via SPI bus, MCU can control everything from power saving, TX delivery, RX receiving, channel monitoring, frequency hopping to auto calibrations. In addition, A7106 supports two general purpose I/O pins, GIO1 and GIO2, to inform MCU its status so that MCU could use either polling or interrupt scheme to do radio control. Hence, it is very easy to monitor radio transmission between MCU and A7106 because of its digital interface. 2. Typical Applications n 2400 ~ 2483.5 MHz ISM system n Wireless metering and building automation n Wireless toys and game controllers n Wireless keyboard and mice n Remote control n Helicopter and airplane radio controller 3. Feature n n n n n n n n n n n n n n n Small size (QFN4 X4, 20 pins). Frequency band: 2400 ~ 2483.5MHz. FSK or GFSK modulation Low current consumption: RX 16mA, TX 20mA (at 0dBm output power). Low sleep current (1.5 uA). On chip regulator, support input voltage 2.0 ~ 3.6 V. Programmable data rate from 2Kbps to 500Kbps. Programmable TX power level from – 20 dBm to 1 dBm. Ultra High sensitivity: u -95dBm at 500Kbps on-air data rate. u -97dBm at 250Kbps on-air data rate u -104dBm at 25Kbps on-air data rate u -107dBm at 2Kbps on-air data rate Fast settling time (130 us) synthesizer for frequency hopping system. Built-in Battery Detector. Support low cost crystal (6 / 8 /12 / 16 / 20 / 24MHz). Support crystal sharing, (1 / 2 / 4 / 8MHz) to MCU. Auto Frequency Compensation Easy to use. u Support 3-wire or 4-wire SPI. u Unique Strobe command via SPI. u ONE register setting for new channel frequency. u 8-bits Digital RSSI for clear channel indication. u Fast exchange mode during TRX role switching. u Auto RSSI measurement. u Auto Calibrations. NOV. 2011, Version 1.2 5 AMICCOM Electronics Corporation A7106 2.4G FSK/GFSK Transceiver u u u u u u u u u Auto IF function. Auto CRC Check. Auto FEC by (7, 4) Hamming code (1 bit error correction / code word). Data Whitening for encryption and decryption. Separated 64 bytes RX and TX FIFO. Easy FIFO / Segment FIFO / FIFO Extension (up to 256 bytes). Support direct mode with recovery clock output to MCU. Support direct mode with frame sync signal to MCU. Support WOR (Wake-On-RX) to periodically wake up from sleep to RX mode. REGI CKO GIO2 GIO1 18 17 16 BPBG 19 1 VDA1 RSSI 20 4. Pin Configurations 4 12 SCK VDA2 5 11 SCS 10 RFO VDA3 DVDD 9 13 XO 3 8 RFI XI SDIO 7 14 GND 2 6 GND VT 15 Fig 4-1. A7106 QFN 4x4 Package Top View NOV. 2011, Version 1.2 6 AMICCOM Electronics Corporation A7106 2.4G FSK/GFSK Transceiver 5. Pin Description (I: input; O: output, I/O: input or output) Pin No. Symbol I/O 1 RSSI O Connected to a bypass capacitor for RSSI reading. 2 BPBG O Connected to a bypass capacitor for internal Regulator bias point 3 RFI I Low noise amplifier input. 4 RFO O Power amplifier output. 5 VDA2 I/O Voltage supply (from VDA1, pin 20) for RX & TX analog part. 6 VT I VCO frequency control input, internal connected to PLL charge pump. 7 GND G Ground 8 XI I Crystal oscillator input node 9 XO O Crystal oscillator output node 10 VDA3 I Voltage supply (from VDA1, pin 20) for PLL part 11 SCS I 3 wire SPI chip select. 12 SCK I 3 wire SPI clock input pin. 13 DVDD I Connected to a bypass capacitor to supply voltage for digital part. 14 SDIO I/O 3 wire SPI read/write data pin. 15 GND G Ground 16 GIO1 I/O Multi-function GIO1 / 4-wire SPI data output. 17 GIO2 I/O 18 CKO O Multi-function GIO2 / 4-wire SPI data output. Multi-function clock output. 19 REGI I 20 VDA1 I/O Back side plate G NOV. 2011, Version 1.2 Function Description Internal Regulator input (External Power Input) Internal Regulator output to supply VDA2 (pin 5), VDA2 (pin 10) and RFO (pin 4). Ground. Back side plate shall be well-solder to ground; otherwise, it will impact RF performance. 7 AMICCOM Electronics Corporation A7106 2.4G FSK/GFSK Transceiver 6. Chip Block Diagram Fig 6-1. A7106 Block Diagram NOV. 2011, Version 1.2 8 AMICCOM Electronics Corporation A7106 2.4G FSK/GFSK Transceiver 7. Absolute Maximum Ratings Parameter With respect to Rating Unit Supply voltage range (VDD) GND -0.3 ~ 3.6 V Digital IO pins range GND -0.3 ~ VDD+0.3 V Voltage on the analog pins range GND -0.3 ~ 2.1 V 5 dBm -55 ~ 125 °C HBM ± 2K V MM ± 100 V Input RF level Storage Temperature range ESD Rating *Stresses above those listed under “Absolute Maximum Rating” may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. *Device is ESD sensitive. Use appropriate ESD precautions. HBM (Human Body Mode) is tested under MIL-STD-883F Method 3015.7. MM (Machine Mode) is tested under JEDEC EIA/JESD22-A115-A. *Device is Moisture Sensitivity Level III (MSL 3). NOV. 2011, Version 1.2 9 AMICCOM Electronics Corporation A7106 2.4G FSK/GFSK Transceiver 8. Electrical Specification (Ta=25℃, VDD=3.0V, data rate= 500Kbps, IF bandwidth = 500KHz, FXTAL =16MHz, with Match Networking and low pass filter, On Chip Regulator = 2.1V, unless otherwise noted.) Parameter Description Min. Type Max. Unit -40 85 2.0 3.6 °C V General Operating Temperature Supply Voltage (VDD) with internal regulator Current Consumption Sleep mode (RC OSC off) 1 mA 1 0.3* 1.9 mA 9 16 20 16 14.5 13.9 12.5 mA mA mA mA mA mA mA 1.5* Idle Mode (Regulator on) Standby Mode (XOSC on,clock generator on) PLL mode RX Mode TX Mode (@0dBm output) TX Mode (@-3dBm output) TX Mode (@-6dBm output) TX Mode (@-11dBm output) TX Mode (@-20dBm output) mA PLL block 2 Crystal start up time* Crystal frequency Crystal tolerance without AFC with AFC Crystal ESR VCO Operation Frequency PLL phase noise 0.6 ms 8, 12, 16, 20, 24 ±20 ±30 MHz ppm ppm ohm MHz dBc 80 2483.5 2400 80 85 90 70 Offset 10k Offset 100K Offset 1M @Loop BW = 500Khz 3 PLL settling time * mS Transmitter Output power range -20 4 Out Band Spurious Emission * 5 Frequency deviation* 30MHz~1GHz 1GHz~12.75GHz 0 -36 -30 dBm dBm dBm 1.8GHz~ 1.9GHz 5.15GHz~ 5.3GHz -47 -47 dBm dBm 186K 124K Data rate > 50Kbps Date rate ±5MHz Adjacent Channel - 40 dB Image (C/IIM) - 12 dB @RF input (BER=0.1%) 30MHz~1GHz -105 Data rate < = 125 Kbps LO fixed Data rate = 250 Kbps Data rate = 500 Kbps Data rate < = 125 Kbps Hopping Data rate = 250 Kbps 0 -57 dBm dBm -47 -50 dBm 10+40 ms 10+100 ms 10+60 ms 70+40 ms 70+100 ms 70+60 Data rate = 500 Kbps RX Spurious Emission dBm dBm Co-Channel (C/I0) 1GHz~12.75GHz @RF input RSSI Range -104 -107 250/500 above 1GHz -47 ms dBm Regulator 9 Regulator settling time * Band-gap reference voltage Regulator output voltage Line regulation Pin 2 connected to 1.5 nF 500 Load current 30mA 1.23 2.1 40 1.8 35 2.3 ms V V dBc Digital IO DC characteristics High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Output Voltage (VOH) Low Level Output Voltage (VOL) 0.8*VDD 0 VDD-0.4 0 @IOH= -0.5mA @IOL= 0.5mA VDD 0.2*VDD VDD 0.4 V V V V Note 1: When digital I/O pins are configured as input, those pins shall NOT be floating but pull either high or low (SCS shall be pulled high only); otherwise, leakage current will be induced. Note 2: Refer to Delay Register II (17h) to set up crystal settling delay. Note 3: Refer to Delay Register I (17h) to set up PDL (PLL settling delay). Note 4: With external RF filter that provides minimum 17dB of attenuation in the band: 30MHz ~ 2GHz and 3GHz ~12.75GHz. Note 5: Refer to TX Register II (15h) to set up FD [4:0]. Note 6: Refer to Delay Register I (17h) to set up PDL and TDL delay. Note 7: The power level of wanted signal is set at sensitivity level +3dB. The modulation data for wanted signal and interferer are PN9 and PN15, respectively. Channel spacing is 500KHz. Note 8: For 250K/500Kbps, set DCM[1:0]= [10b] by ID, (29h). For