AW21024
Sep. 2019
V1.0
24-CHANNEL INTELLIGENT 8-BIT RGB LED DRIVER
FEATURES
GENERAL DESCRIPTION
AW21024 is a 24-channel high precision constant
current LED driver. Each channel has individual 8bit DC current setting for color-mixing and 8-bit
PWM current for brightness control. The global
current of each channel is recommended to be
50mA configured via register GCCR and external
Resistor REXT.
Individual 256-level PWM for dimming
Individual 256-level current for color-mixing
a
l
ti
Global 256-level DC current configuration
High-precision current sinks
Device-to-device error: ±5%
Channel-to-channel error: ±5%
n
Group control mode, autonomous breathing pattern
and rapid RGB control mode are provided for
flexible, high efficiency lighting effect programming
and fast display updating.
EMI and audible noise reduction
Phase delay and phase inverting scheme
Spread spectrum function
d
e
24-channel RGB LED Driver
Flexible LED lighting pattern control
LED open/short detection per channel
Auto power saving mode when all LEDs off >
32ms
o
n
Over-temperature protection
400 kHz I2C interface, 16 selectable addresses
Power supply: 2.7V~5.5V
QFN 4mmX4mmX0.85mm-32L package
ic
AW21024 is available in QFN 4mmX4mmX
0.85mm-32L package. It operates from 2.7V to 5.5V
over the temperature range of -40°C to +85°C.
in
Smart speaker
AW21024 can be turned off with minimum current
consumption by either pulling the EN pin low or
using the software shutdown feature.
C
APPLICATIONS
Programmable phase-shifting and spread spectrum
technology are utilized to reduce EMI and audible
noise caused by MLCC when LEDs turn on or off
simultaneously.
fi
E-sports devices
w
Smart home appliance
a
TYPICAL APPLICATION CIRCUIT
VLED
VDD
27
25
AD0
26
AD1
VIO
R1
4.7k Ω
VDD
C2
0.1 μF
C1
1 μF
R2
4.7k Ω
LED24
24
LED23
23
LED22
22
.
.
.
AW21024
29
28
MCU
30
31
SCL
CLED
1 μF
RG
RR
.
.
.
SDA
EN
LED3
ISET
LED2
REXT
4kΩ
33
RB
GND
LED1
Note: The resistors(RR,RG,RB )
3
2
1
RBLUE=(VLED-VF-0.5V)/IOUT
R GREEN=(VLED-VF-0.5V)/IOUT
RRED=(VLED-VF-0.5V)/IOUT
between LED and IC are only for thermal reduction
AW21024 Application circuit
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1
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
PIN CONFIGURATION AND TOP MARK
AW21024QNR
(Top View)
AW21024QNR
(Top View)
25
32
1
a
l
24
n
ti
33
GND
9
16
d
e
17
8
PIN DEFINITION
o
n
fi
CWW0 – AW21024QNR
XXXX – Production Tracing Code
NAME
DESCRIPTION
1~24
LED1~LED24
Constant current sink, connect to LED’s cathode
25~26
AD0,AD1
I2C address setting, connects to GND, VDD, SCL or SDA for different device
address of I2C. Internally pulled down to GND with a resistor of 1MΩ
27
VDD
28
SDA
29
SCL
ic
Power supply
EN
Serial data I/O for I2C interface
in
w
30
C
No.
Serial clock input for I2C interface
Shutdown the chip when pulled low.
ISET
Input terminal used to connect an external resistor. This regulates the global
output current. When REXT=4.0kΩ, global current of LED is 20mA.
32
NC
Not connected
33
GND
Ground
a
31
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
FUNCTIONAL BLOCK DIAGRAM
VDD
POR
OSC
OTP
UVLO
O/S
Detection
a
l
Bandgap
PWM
Modulation
BR
Digital
Control
COL
n
AD
I2C
Interface
LED Driver
EN
Phase
Control
d
e
SDA
ti
SCL
Global Current
Setting
GND
o
n
fi
ISET
LED1-24
VDD
27
ic
25
26
a
w
MCU
LED24
24
LED23
23
LED22
22
AD0
.
.
.
AW21024
29
SCL
28
SDA
30
EN
31
LED3
ISET
LED2
REXT
4kΩ
33
VLED
RB
CLED
1 μF
RG
RR
AD1
R2
4.7k Ω
in
R1
4.7k Ω
VDD
C2
0.1 μF
C1
1 μF
VIO
C
TYPICAL APPLICATION CIRCUITS
LED1
GND
Note: The resistors(RR,RG,RB )
.
.
.
3
2
1
RBLUE=(VLED-VF-0.5V)/IOUT
R GREEN=(VLED-VF-0.5V)/IOUT
RRED=(VLED-VF-0.5V)/IOUT
between LED and IC are only for thermal reduction
AW21024 Application circuit
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
ORDERING INFORMATION
Temperature
Package
Marking
Moisture
Sensitivity
Level
Environmental
Information
Delivery Form
AW21024QNR
-40°C~85°C
QFN 4X4-32L
CWW0
MSL3
ROHS+HF
6000 units/
Tape and Reel
a
l
Part Number
ti
ABSOLUTE MAXIMUM RATINGS(NOTE1)
RANGE
n
PARAMETERS
-0.3V to 6V
d
e
Supply voltage range VDD
Input voltage range
SCL, SDA, EN, AD0,AD1
-0.3V to VDD
Output voltage range
LED1~LED24
-0.3V to VDD
Operating free-air temperature range
o
n
Maximum operating junction temperature TJMAX
fi
Junction-to-ambient thermal resistance θJA
Storage temperature TSTG
Lead temperature (soldering 10 seconds)
36.4°C/W
-40°C to 85°C
160°C
-65°C to 150°C
260°C
HBM
ic
CDM
C
ESD (NOTE 2)
JESD78E
in
Test condition:
±2000V
±1500V
Latch-Up
+IT：200mA
-IT：-200mA
a
w
NOTE1: Conditions out of those ranges listed in "absolute maximum ratings" may cause permanent damages
to the device. In spite of the limits above, functional operation conditions of the device should within the ranges
listed in "recommended operating conditions". Exposure to absolute-maximum-rated conditions for prolonged
periods may affect device reliability.
NOTE2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test
method: MIL-STD-883H Method 3015.8(HBM). ESDA/TEDEC JS-002-2018(CDM).
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
ELECTRICAL CHARACTERISTICS
TA=25°C，VDD=3.6V (unless otherwise noted) , REXT=4kΩ
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
5.5
V
Power supply voltage and current
Power supply voltage
ISD_VDD
Shutdown current of VDD
EN=GND
Standby current of VDD
VEN=3.6V,CHIPEN=
0
2.7
All LEDs off >32ms
VEN=VDD,
GCR.CHIPEN=1,
Quiescent current in active
mode
VEN=VDD,
fi
IACT_VDD
1
μA
10
μA
ti
VEN=3.6V,
GCR.APSE=1,
n
Power-save mode current
consumption
3
d
e
ISTB_VDD
0.1
a
l
VDD
GCR.CHIPEN=1,
o
n
GCCR.GCC=0xFF,
3
10
μA
2
4
mA
10
12
mA
0.1
1
μA
20.0
+5%
mA
+5
%
COLX=0xFF
VEN=0V,
ILEAKAGE
Output leakage current
IMAX
Maximum global current of
LEDX
GCCR.GCC=0xFF,
IMATCH
Output current match
accuracy
GCCR.GCC=0xFF,
VDROPOUT
Dropout voltage when the
LED current has dropped
5%
FOSC
OSC clock frequency
C
ic
in
BRX=COLX=0xFF
BRX=COLX=0xFF
ILEDX=20mA
w
a
TSD
VLEDX=5.5V
-5%
-5
150
200
250
mV
-5%
16
+5%
MHz
Thermal shutdown threshold
150
°C
Thermal shutdown
hysteresis
20
°C
AD0,AD1, EN
VIL
Input low level
AD0,AD1,EN
VIH
Input high level
AD0,AD1,EN
RADPD
Internal pull down resistance
AD0,AD1,
VDD=3.6V
RENPD
Internal pull down resistance
EN, VDD=3.6V
0.4
1.2
V
V
1M
Ω
400k
Ω
I2C Interface
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
PARAMETER
TEST CONDITION
VOL
Output low level
SDA,IOL = 10 mA
VIH
Input high level
SCL, SDA
VIL
Input low level
SCL, SDA
MIN
TYP
V1.0
MAX
UNIT
0.1
V
1.2
V
0.4
V
MIN
-
THD:STA
(Repeat-start) Start condition hold time
TLOW
Low level width of SCL
THIGH
High level width of SCL
TSU:STA
(Repeat-start) Start condition setup time
THD:DAT
Data hold time
TSU:DAT
Data setup time
TR
TF
Falling time of SDA and SCL
TSU:STO
Stop condition setup time
TBUF
Time between start and stop condition
UNIT
400
kHz
-
μs
1.3
-
μs
0.6
-
μs
0.6
-
μs
0
-
μs
0.1
-
μs
Rising time of SDA and SCL
-
0.3
μs
-
0.3
μs
0.6
-
μs
1.3
-
μs
in
ic
o
n
fi
d
e
0.6
n
Interface Clock frequency
MAX
C
FSCL
TYP
ti
PARAMETER
a
l
I2C INTERFACE TIMING
VIH
w
SDA
tBUF
VIL
tLOW
tHIGH
tR
tF
VIH
SCL
a
VIL
Stop
tHD:STA
Start
tHD:DAT
tSU:DAT
tSU:STA
Start
tSU:STO
Stop
I2C Interface Timing
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
DETAILED FUNCTIONAL DESCRIPTION
OPERATION MODE AND RESET
POWER ON RESET
a
l
Upon initial power-up, the AW21024 is reset by internal power-on-reset, and all registers are reset to default
value, and LED driver is shut down.
ti
Once the supply voltage VDD drops below the threshold voltage VPOR_VDD (2.0V), the power-on-reset will be
activated to reset the device again. By reading the bit PORST of the register UVCR (address 79h), whether
the device has been reset can be determined.
VDD
d
e
n
Below is the recommended operation timing:
POR threshold
POR
200μs
Initial
Note: The device need about 200μs for
initalization after Power ON
Initial
200μs
Note: OSC operate stable
need 200μs after CHIPEN=1
o
n
CHIPEN
fi
Note: Recommend CHIPEN=1 after Initial
(bit CHIPEN of GCR register)
OSC
Note: After OSC stable,
light effect can be set
Determined by light
effect
Light effect
C
Configure
………………………………
SOFTWARE RESET
ic
Power Up Timing
in
By writing 00H to register RESET (address 7Fh), the software reset is triggered. After software reset, all
registers will be reset to the default value and enter into standby mode.
a
w
After the software reset command is input through I2C or power on reset, it needs to wait at least 2ms before
any other I2C command can be accepted.
Soft Reset
200μs
Initial
Note: The device need about 200μs for
initalization after Power ON
Initial
Note: Recommend CHIPEN=1 after Initial
(bit CHIPEN of GCR register)
CHIPEN
200μs
Note: OSC operate stable need
200μs after CHIPEN=1
……………………………
OSC
Note: After OSC stable,
light effect can be set
Configure
Determined by light
effect
Light effect
Software Reset Timing
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
SHUTDOWN MODE
The AW21024 enters into shutdown mode automatically when EN is pulled to low level. In this situation, I2C
interface is not accessible, all registers can not be configured and will be reset.
a
l
STANDBY MODE
ti
The AW21024 enters into standby mode automatically when EN is pulled low or the bit CHIPEN of the register
GCR (address 00h) is set to “0” or UVLO is triggered(UVST=1) in active mode, meanwhile all registers will not
be reset. In standby mode, all analog blocks are power down but I2C interface is accessible, and all registers
can be configured.
d
e
n
When POR is triggered, the device enters into standby mode and all registers will be reset (more information
is showed in POWER ON RESET).
ACTIVE MODE
fi
When EN is in high level, and the bit CHIPEN of the register GCR (address 00h) is set to “1”, the AW21024
enters into the active mode.
o
n
AUTO POWER-SAVE MODE
C
The bit APSE of the register GCR (address 00h) is set to “1”, the auto power-save mode is enabled. When all
LEDs are off and the value of all register BR0~BR23 are 0x00H for more than 32ms, AW21024 automatically
enters into standby mode for power saving. Once writing a non-zero value into any register among BR0~BR23,
the device exits power-save mode immediately.
a
w
in
ic
VCC power up
EN=L
Shutdown
From all states
EN=H
Software reset
Initialization
From all states
APSE=1 &&
All LEDs off >32ms
UVST=H or PORST=H
POWER
SAVE
Stand-by
From all states
2
I C Command
Chipen=0
Chipen=1
TSD=H
Active
Thermal
Shutdown
TSD=L
AW21024 Operating Mode Transition
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
I2C INTERFACE
The AW21024 supports the I2C protocol. The maximum frequency supported by the I2C is 400kHz. The pullup resistor for the SDA and SCL can be selected from 1k to 10kΩ. Usually, 4.7kΩ is recommended for 400kHz
I2C. The voltage from 1.8V to 3.3V is allowed for the I2C interface. Additionally, the I2C device supports
continuous read and write operations.
a
l
DEVICE ADDRESS
A2:A1
GND
00
00
GND
VDD
00
01
GND
SCL
00
10
GND
SDA
00
11
VDD
GND
01
VDD
VDD
01
VDD
SCL
01
VDD
SDA
SCL
GND
SCL
VDD
SCL
SCL
SCL
SDA
SDA
A0
Device Address
d
e
A4:A3
31h
32h
33h
00
34h
01
35h
10
36h
01
11
10
00
10
01
39h
10
10
3ah
10
11
3bh
GND
11
00
3ch
SDA
VDD
11
01
3dh
SDA
SCL
11
10
3eh
SDA
11
11
3fh
ic
in
w
37h
0/1
38h
1Ch
a
SDA
011
Broadcast
Address
30h
fi
GND
A7:A5
o
n
AD0
C
AD1
n
ti
The I2C device address is 7-bit (A7~A1), followed by a R/W bit A0 (Read=1/Write=0). Set A0 to “0” for writing
and “1” for reading. The values of bit A1 and bit A2 are depended on the connection of pin AD0 and the values
of [A4:A3] are depended on the connection of pin AD1, there are 4 options: VDD, GND, SCL and SDA for each
AD. The A7 to A5 is “011” constantly. The device also supports using a broadcast slave address of 1Ch to
access registers. All slave addresses as followed.
I2C START/STOP
I2C start: SDA changes from high level to low level when SCL is high level.
I2C stop: SDA changes from low level to high level when SCL is high level.
SDA
SCL
S/Sr
P
S: START condition
Sr: START Repeated condition
P: STOP condition
I2C Start/Stop Condition Timing
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
DATA VALIDATION
When SCL is high level, SDA level must be constant. SDA can be changed only when SCL is low level.
SDA
Change
of Data
Allowed
ti
Data Line
Stable
Data Valid
a
l
SCL
d
e
ACK (ACKNOWLEDGEMENT)
n
Data Validation Diagram
ACK means the successful transfer of I2C bus data. After master sends an 8-bit data, SDA must be released;
SDA is pulled to GND by slave device when slave acknowledges.
o
n
fi
When master reads, slave device sends 8-bit data, releases the SDA and waits for ACK from master. If ACK
is send and I2C stop is not send by master, slave device sends the next data. If ACK is not send by master,
slave device stops to send data and waits for I2C stop.
Data Output
by Transmiter
C
Not Acknowledge（NACK）
Data Output
by Receiver
ic
SCL From
Master
Acknowledge（ACK）
2
1
in
9
Clock Pulse for
Acknowledgement
START
condition
I2C ACK Timing
w
WRITE CYCLE
8
a
One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock
(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the
SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction.
New data should be sent during the low SCL state. This protocol allows a single data line to transfer both
command/control information and data using the synchronous serial clock.
Each data transaction is composed of a start condition, a number of byte transfers (set by the software) and a
stop condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is
transferred with the most significant bit first. After each byte, an Acknowledge signal must follow.
In a write process, the following steps should be followed:
a)
Master device generates START condition. The “START” signal is generated by lowering the
SDA signal while the SCL signal is high.
b)
Master device sends slave address (7-bit) and the data direction bit R/W = 0).
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
Slave device sends acknowledge signal if the slave address is correct.
d)
Master sends control register address (8-bit)
e)
Slave sends acknowledge signal
f)
Master sends data byte to be written to the addressed register
g)
Slave sends acknowledge signal
h)
If master will send further data bytes the control register address will be incremented by one after
acknowledge signal (repeat step f and g)
i)
Master generates STOP condition to indicate write cycle end
a
l
c)
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
0
1
2
3
4
n
SCL
ti
j)
5
6
7
8
A6 A5 A4 A3 A2 A1 A0 R/WAck A7 A6 A5 A4 A3 A2 A1 A0 Ack D7 D6 D5 D4 D3 D2 D1 D0
Start
Device Address
Register Address
Write Data
d
e
SDA
Ack
Stop
I2C Write Byte Cycle
fi
READ CYCLE
o
n
In a read cycle, the following steps should be followed:
Master device generates START condition
b)
Master device sends slave address (7-bit) and the data direction bit (R/W = 0).
c)
Slave device sends acknowledge signal if the slave address is correct.
d)
Master sends control register address (8-bit)
e)
Slave sends acknowledge signal
f)
Master generates STOP condition followed with START condition or REPEAT START condition
g)
Master device sends slave address (7-bit) and the data direction bit (R/W = 1).
h)
Slave device sends acknowledge signal if the slave address is correct.
i)
Slave sends data byte from addressed register.
j)
If the master device sends acknowledge signal, the slave device will increase the control register
address by one, then send the next data from the new addressed register.
k)
If the master device generates STOP condition, the read cycle is ended.
a
w
in
ic
C
a)
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
SCL
0
1
2
3
4
5
SDA
A6
A5
A4
A3
A2
A1
7
8
0
1
2
3
4
5
6
A0 R/W Ack A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
A6
A5
A4
A3
A2
A1
6
7
8
0
A0 R/W Ack D7
……
0
1
2
3
4
5
A6
A5
A4
A3
A2
A1
S
...
6
D6 …… D1
7
8
D0 Ack
stop
Read Data
Device Address
Separated
Read/write
transaction ……
1
6
7
8
0
A0 R/W Ack D7
Device Address
1
...
6
7
D6 …… D1
D0
8
a
l
0
RS
P
Register Address
n
……
Using
Repeat start……
A0 Ack
ti
Device Address
8
7
Ack
Read Data
stop
d
e
start
6
V1.0
I2C Read Byte Cycle
UNDER VOLTAGE LOCK OUT (UVLO)
o
n
fi
When bit UVDIS of the register UVCR (address 79h) is set to “0”, the device monitors the voltage of VDD. If
the voltage drops below threshold (2.4V typically), the bit UVST of the register UVCR (address 79h) will be set
to “1”. After read-out, the register UVCR will be clear.
C
If both bit UVDIS and bit UVPD of the register UVCR (address 79h) is set to “0”, UVLO protection function is
enabled. Once the event of under voltage occurs, the bit CHIPEN of the register GCR (address 00h) will be
cleared to “0”, and then the device will enter into standby mode. If the voltage of VDD rises above the UVLO
threshold and then write “1” to bit CHIPEN, the device will enter into active mode again.
By default, control bits UVDIS, UVPD are all “0”. Both UVLO monitor and protection are enabled.
ic
OVER TEMPERATURE PROTECTION (OTP)
in
When bit OTDIS of the register OTCR (address 77h) is set to “0”, the over-temperature detection is enabled.
Once the temperature of this device reaches 150℃, the over-temperature condition is detected, and the bit
w
OTST of the register OTCR (address 77h) will be set to “1”. The OTST will be cleared to “0” after reading the
register OTCR.
a
If both bit OTDIS and bit OTPD of the register OTCR (address 77h) is set to “0”, the Over-Temperature
Protection (OTP) function is enabled. Once the event of over-temperature occurs, the bit CHIPEN of the
register GCR (address 00h) will be cleared to “0”, and then the device will enter into standby mode. When the
temperature returns below 130°C, the device will enter into active mode again after writing “1” to bit CHIPEN.
By default, control bits OTDIS and OTPD are all “0”, both OT monitor and OT protection are enabled.
LED OPEN/SHORT DETECTION
AW21024 supports LED open/short detection. When bit OSDE[1:0] of the register OSDCR(address 71h) is set
to “11” , open detection is enabled, and the detection results can be read out via the registers OSST0~2
(72h~74h). Similarly, when set bit OSDE [1:0] of the register OSDCR (address 71h) to “10”, short detection is
enabled, and the results also can be read out via the registers OSST0~2.
We recommend the bit PWMDIS [6:5] of the register SSCR (address 78h) being set to “11” and maintain about
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
1mA current of each LED when the open/short function is enabled.
CURRENT SETTING
The average output current of LEDn (n=1, 2, …, 24) can be expressed by the following formula,
K
GCC WB COLn BRn
REXT 255 255 255 256
n=1, 2, 3, …, 24
a
l
I OUT ( n )
n
ti
Where K=80V, REXT is the value of external resistor, GCC is the 8bit global current configured by the register
GCCR (address 6Eh), WB is 8bit white balance parameter configured by the register WBR/WBG/WBB
(address 90h/91h/92h), COLn is 8bit individual constant current parameter, and BRn is 8bit individual PWM
modulated current parameter.
d
e
The maximum output current is decided by the REXT and the GCC when WB=255, COLn=255, BRn=256. For
an example: when REXT = 4kΩ, GCC=0xFF, IOUT= IMAX=20mA.
fi
AW21024 supports white balance calibration function via 3 registers consisting of register WBR, WBG, and
WBB. Therein, WBR is used for LED X (X=1, 4, 7, …, 22), WBG is used for LEDY (Y=2, 5, 8, …, 23), WBB is
used for LEDZ (Z=3, 6, 9, …, 24). The default value of registers WBR/WBG/WBB is 0xff.
o
n
Each LED current of AW21024 features 8bit DC current and 8bit PWM modulated current that are decided by
COL source and BR source respectively. The BR and COL sources are as follows.
Mode
General Mode
Breathing Pattern Controller (BPC)
Group Control Mode
Paramete
r
GEn=0
GEn=1 and PATEN=1
GEn=1 and PATEN=0
RGBMD=
0
RGBMD=
1
#1
BR0
BR0
#2
BR1
#3
BR2
#4
#5
BR
Source
COL Source
COL Source
GCOLDIS=1
GCOLDIS=0
GCOLDIS=1
COL0
GCOLR
COL0
GCOLR
COL0
BR0
COL1
GCOLG
COL1
GCOLG
COL1
BR0
COL2
GCOLB
COL2
GCOLB
COL2
BR3
BR1
COL3
GCOLR
COL3
GCOLR
COL3
BR4
BR1
COL4
GCOLG
COL4
GCOLG
COL4
BR5
BR1
COL5
GCOLB
COL5
GCOLB
COL5
…
…
…
…
…
…
…
#22
BR21
BR7
COL21
GCOLR
COL21
GCOLR
COL21
#23
BR22
BR7
COL22
GCOLG
COL22
GCOLG
COL22
#24
BR23
BR7
COL23
GCOLB
COL23
GCOLB
COL23
a
…
w
#6
in
GCOLDIS=0
ic
LED NO.
BR
Source
C
COL
Source
BR Source
Source
BPC
FADEL
Notes:
GEn (n=0~7) refers to BPC/Group-Control-Mode control bit in register GCFG0 (address ABh). PATEN is BPC
control bit in register PATCFG (address A0h), GCOLDIS is group color disable bit in register GCFG1(address
ACh), GCOLR/GCOLG/GCOLB is for group color control decided by register GCOLR/GCOLG/GCOLB
(address A8h~A9h). More details will be introduced later.
UPDATE
www.awinic.com
13
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
After configuring the BR parameters, should write 0x00 to register UPDATE (address 49h) to update the data.
PWM MODLULATION
PWM FREQUENCY
001
010
011
100
101
PWM Freq.
[Hz]
62k
32k
4k
2k
1k
500
244
111
122
d
e
PWM PHASE CONTROL
110
ti
000
n
CLKFRQ[2:0]
a
l
The PWM frequency is decided by bits CLKFRQ [2:0] in register GCR (address 00h). Following table shows
the relationship of PWM frequency and the CLKFRQ [2:0]. To avoid the MLCC audible noise, it’s recommended
to use the PWM frequency lower than 500 Hz or higher than 20 kHz.
Phase2
LED7~LED12
Phase3
0
C
Phase1
LED1~LED6
o
n
fi
To reduce the peak load current and ceramic-capacitor audible ringing, AW21024 supports 4 PWM phase
shifting (Phase1~Phas4) and phase-inverting scheme. When setting PDE in register PHCR (address 70h) to
“1”, the phase shifting scheme is enabled, and each adjacent phase differs by 60 degrees，which meaning
only 6 of 24 LEDs could switch on in the same time.
π /3
2π /3
ic
LED13~LED18
Phase4
in
LED19~LED24
3π /3
Phase Shift Scheme
a
w
When setting PIEn in register PHCR (address 70h, n=1~4) to “1”, the PWM phase of the even-numbered
channels is inverted. As shown below, if setting PIEn to “1”, the even-numbered channels (i.e. 6x(n-1)+2, 6x(n1)+4, 6(n-1)+6) are switched off when the odd-numbered channels (i.e. 6x(n-1)+1, 6x(n-1)+3, 6(n-1)+5) are
switched on, which is good for reducing the input-current ripple. For an example, when setting PIE0 to “1”, the
channels of LED2, LED4 and LED6 are switched off when the channels of LED1, LED3 and LED5 are switched
on.
www.awinic.com
14
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
PIEn=”0”
LED[6*(n-1) +1 ]
LED[6*(n-1) +3 ]
LED[6*(n-1) +5 ]
a
l
LED[6*(n-1) +2 ]
LED[6*(n-1) +4 ]
LED[6*(n-1) +6 ]
PIEn=”1”
ti
LED[6*(n-1) +1 ]
LED[6*(n-1) +3 ]
LED[6*(n-1) +5 ]
d
e
n
LED[6*(n-1) +2 ]
LED[6*(n-1) +4 ]
LED[6*(n-1) +6 ]
Phase Invert Scheme
fi
PWM DISABLE
o
n
If the bits PWMDIS [1:0] in register SSCR (address 78h) is set to “11”, the PWM output is disabled, and the
duty of each PWM is forced to 100%. In this mode, the BR parameter is not valid, but the COL parameter is
still effective. And the PWM outputs of LED1~12 and LED13~24 enabled or not are decided by the bit 0~1 of
PWMDIS respectively.
C
It should be noted that when performing open-short detection, the bits PWMDIS [1:0] need to be set to “11”.
SPREAD SPECTRUM
in
ic
PWM is a troublesome for some application which is concerned about EMI. AW21024 has spread spectrum
function to optimize the EMI performance. If bit SSE in register SSCR (address 78h) is set to “1”, spread
spectrum function is enabled. By setting the bit SSR in register SSCR, four spread spectrum range
5%/15%/25%/35% can be selected. The total electromagnetic emitting energy can spread into a wider range
of frequency band that significantly degrades the peak energy of EMI.
w
RGB CONFIGURE MODE
a
To achieve fast register configuration for RGB applications, AW21024 provides an RGB configuration mode by
setting the bit RGBMD in register GCR2 (address 7Ah). In RGB mode, every 3 adjacent LEDs share a same
BR parameter.
If RGBMD=1, register BR0~BR7 configure brightness parameters for corresponding 8 RGB groups (every 3
adjacent LEDs form a RGB group). In other words, in RGB mode, only registers BR0~BR7 need to be
configured, and the registers BR8~BR23 not valid any more.
If RGBMD=0, register BR0~BR23 configure brightness parameters for corresponding 24 LEDs independently,
more details as follows,
BR parameter source
LED No.
#1
www.awinic.com
15
RGBMD=0
RGBMD=1
BR0
BR0
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
BR1
#3
BR2
#4
BR3
#5
BR4
#6
BR5
…
…
#22
BR21
#23
BR22
#24
BR23
BR1
…
BR7
a
l
#2
V1.0
ti
PATTERN CONTROLLERS
fi
d
e
n
There is a breathing pattern controller (BPC) in the device. When bit PATEN in register PATCGF (address A0h)
is set to “1”, breathing pattern controller is enabled. Pattern controller can be configured as autonomous
breathing mode or manual-controlled mode. Each RGB consisting of every three adjacent LEDs can be
configured as pattern controlled mode or normal mode by register GCFG0. For example, when setting GCFG0
= 0x01 and PATEN=1, the RGB1 which consists of LED1~LED3 will work in BPC mode and other LED will
work in normal mode.
o
n
AUTONOMOUS BREATHING MODE
ic
C
When bit PATMD in register PATCFG is set to “1”, the pattern controller works in autonomous breathing mode.
In this mode, the pattern controller will generate a breathing lighting effect, which is configured by the userdefined timing parameter. The waveform of the breathing lighting effect is shown in the following figure. The
parameter T0~T3 define 4 key periods in a complete breathing cycle. T0~T3 composite a breathing loop,
denoting the rise-time, on-time, fall-time and off- time respectively. Register FADEH (A6h) and FADEL (A7h)
control the max and min brightness of the breathing respectively.
in
FADEH
T0
T1
T2
T3
LED Breath Timing in Pattern Mode
a
w
FADEL
The start point and end point of autonomous breathing loop are configurable. The loop starting point could be
selected among T0~T3, which is set by bits LB [1:0] in register PATT2 (address A4h). The end point of the loop
can only be selected between the end of T0 and the end of T2, which is determined by bits LE [1:0] in register
PATT2. The repeat times is determined by the end point defined. If bits LE [1:0] is not “00”, the end point of
breathing loop is the end of T0, and the loop counter increment by 1 at the end of T0. If bit LE [1:0] is “00”, the
loop end point is the end of T2, and the loop counter increment by 1 at the end of T2.
The repeat times is decided by bit RPT [11:8] of register PATT2 (address A4h) and RPT [7:0] of register PATT3
(address A5h). When setting RPT [11:0] to “0”, the breathing pattern will run unlimited times.
After the breathing pattern is over, the status bit ENDFLAG in register PATGO (address A2h) will be set to “1”,
and ENDFLAG will be cleared to “1” after reading out through I 2C bus. Once breathing loop start again or
pattern controller switches to manual mode by setting PATMD bit to “0”, the ENDFLAG will also be cleared.
www.awinic.com
16
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
When bit RUN in register PATGO is set to “1”, breathing pattern is started. The full process of the autonomous
breathing is as follows:
Set GCOLR/G/B, FADEH/L parameter.
b)
Set GCFG0 to select the LED in breathing pattern mode or not.
c)
Configure PATT0, PATT1, PATT2, and PATT3 for parameters T0~T3, start/stop point, and repeat
times.
d)
Set PATEN=1 to enable breathing pattern mode.
e)
Set PATMD=1 and RAMPE=1 to select auto breathing mode and enable breathing ramp.
f)
Set RUN=1 to start the breath pattern.
ti
a
l
a)
MANUAL CONTROL MODE
d
e
n
If bit PATMD is set to “0”, manual control mode is selected. In manual control mode, user could program the
bit SWITCH of register PATCFG to control the output of pattern controller. When bit SWITCH is “1”, the output
of pattern controller is decided by register FADEH. When bit SWITCH is set as “0”, the output is the decided
by register FADEL.
fi
If bit RAMPEN in register PATCFG is set to “1”, the smooth ramp up/down will be enabled. At the same time,
if SWITCH changes from “0” to “1”, the output will be ramp up to FADEH smoothly. Similarly, if SWITCH
changes from “1” to “0”, the output of the pattern controller will ramp down to FADEL smoothly.
FADEH
FADEH
C
PATCFG.RAMPE =0
FADEL
o
n
However, if the RAMPEN is set to “0”, the output of the pattern controller will change to FADEH or FADEL
directly with no ramp as the SWITCH changes.
ic
PATCFG.RAMPE =1
fade-out
fade-in
FADEL
in
Set PATCFG.SWITCH =1
Set PATCFG.SWITCH =0
a
w
Manual Control Mode
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17
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
REGISTER CONFIGURATION
REGISTER LIST
ADDR
NAME
W/R
Bit7
Bit6
Bit5
Bit4
Bit3
00H
GCR
W/R
APSE
01H
~
18H
BR0
~
BR23
W/R
BR0~BR23
Bit2
CLKFRQ
Bit1
-
Bit0
Default
CHIPEN
00H
a
l
00H
49H
UPDATE
W/R
UPDATE
4AH
~
61H
COL0
~
COL23
W/R
COL0~COL23
6EH
GCCR
W/R
GCC
70H
PHCR
W/R
71H
OSDCR
W/R
72H
OSST0
R
OSST [7:0]
00H
73H
OSST1
R
OSST [15:8]
00H
74H
OSST2
R
OSST [23:16]
00H
77H
OTCR
W/R
78H
SSCR
W/R
79H
UVCR
W/R
7AH
GCR2
W/R
7CH
GCR4
-
7EH
VER
R
7FH
RESET
W/R
90H
WBR
W/R
91H
WBG
W/R
92H
WBB
W/R
A0H
PATCFG
A2H
ti
PIE
OTH
fi
OTST
OTPD
o
n
TRST
-
PWMDIS
REXT_ST
STH
d
e
-
TROF
n
-
SSE
UVST
PORST
OTDIS
SSR
OCPTH
OCPD
UVPD
-
in
W/R
00H
OSDE
00H
TRTH
00H
CLT
00H
UVDIS
00H
RGBMD
00H
SRF
00H
A8H
RESET/ID
18H
WBR
FFH
WBG
FFH
WBB
FFH
-
W/R
SRR
00H
VERSION
ic
C
-
00H
SWITCH
-
RAMPE
PATMD
PATEN
00H
ENDF
LAG
PATST
RUN
00H
PATT0
W/R
T0
T1
00H
PATT1
W/R
T2
T3
00H
RPT[11:8]
00H
a
A3H
PATGO
w
A1H
PDE
00H
A4H
PATT2
W/R
A5H
PATT3
W/R
RPT[7:0]
00H
A6H
FADEH
W/R
FADEH
00H
A7H
FADEL
W/R
FADEL
00H
A8H
GCOLR
W/R
GCOLR
00H
A9H
GCOLG
W/R
GCOLG
00H
AAH
GCOLB
W/R
GCOLB
00H
ABH
GCFG0
W/R
ACH
GCFG1
www.awinic.com
W/R
LE
GE7
LB
GE6
GE5
GE4
GCOL
DIS
-
18
GE3
GE2
GE1
-
GE0
00H
00H
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
REGISTER DETAILED DESCRIPTION
GCR：Global Control Register(Address 00H)
Description
RW
3:1
RESERVED
R
0
CHIPEN
RW
Reserved
n
CLKFRQ
Chip enable
0: disable
1: enable
000
0
0
C
6:4
a
l
OSC frequency selection
000: 16MHz
001: 8MHz
010: 1MHz
011: 512kHz
100: 256kHz
101: 125kHz
110: 62.5kHz
111: 31.25kHz
0
ti
RW
Auto power-saving mode enable
0: disable
1: enable
Default
d
e
APSE
R/W
fi
7
Symbol
o
n
Bit
Symbol
7:0
BR
R/W
w
in
Bit
ic
BR：BR Register(Address 01H~18H)
RW
Description
Individual 8bit BR parameter for LED1~24
After configuring the BR registers, should write 0x00 to
register UPDATE to update the data.
Default
0x00
UPDATE： Update Register(Address 49H)
Symbol
R/W
UPDATE
W
a
Bit
7:0
Description
Write 0x00 to update BR register.
Default
0x00
COL0~COL35：COL Register(Address 4AH~61H)
Bit
Symbol
R/W
7:0
COL
RW
www.awinic.com
Description
Individual 8bit COL parameter for LED1~24.
19
Default
0x00
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
GCCR：Global Control Register(Address 6EH)
Symbol
R/W
7:0
GCC
RW
Description
Default
Global current control.
0x00
a
l
Bit
7
PDE
RW
6:4
RESERVED
R
Description
PWM phase delay enable
0: disable
1: enable
Reserved
n
R/W
d
e
Symbol
Default
0
0
fi
Bit
ti
PHCR：Phase Control Register(Address 70H)
PIE3
RW
2
PIE2
RW
PWM phase invert for LED14, LED16 and LED18
0: Phase invert disabled
1: Phase invert enabled
0
1
PIE1
RW
PWM phase invert for LED8, LED10 and LED12
0: Phase invert disabled
1: Phase invert enabled
0
PWM phase invert for LED2, LED4 and LED6
0: Phase invert disabled
1: Phase invert enabled
0
C
ic
RW
in
PIE0
w
0
o
n
3
PWM phase invert for LED20, LED22 and LED24
0: Phase invert disabled
1: Phase invert enabled
0
OSDCR：Open Short Detect Control Register(Address 71H)
Symbol
a
Bit
7:4
RESERVED
R/W
R
Description
Reserved
3
OTH
RW
Open threshold
0: 0.1V
1: 0.2V
2
STH
RW
Short threshold
0: VDD-1V
1: VDD-0.5V
www.awinic.com
20
Default
0000
0
0
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
1:0
OSDE
RW
Open short detect enable
0x: detect disable
10: short detect enable
11: open detect enable
V1.0
00
OSST0~2：Open/Short Status Register (Address 72H~74H)
R
Description
Open/short status of LED1~LED24
0: no open/short event detected
1: open/short event detected
Symbol
0x00
d
e
OTCR：Over Temperature Control Register (Address 77H)
Bit
Default
a
l
OSST
R/W
ti
7:0
Symbol
n
Bit
R/W
Description
Default
Thermal roll off percentage of IOUT
TROF
RW
01: 75%
10: 55%
11: 30%
R
Over-temperature status
0: none over-temperature
1: over-temperature
0
RW
Over-temperature(OT) protect disable
0: OT protect enable, when OT event occurs, device will
clear GCR.CHIPEN to 0.
1: OT protect disable
0
RW
Over-temperature detect disable
0: OT detect enable, when OT event occurs, OTCR.OTST
will be set.
1: OT detect disable
OTDIS
0
RW
Thermal roll off threshold
00: 140°C
01: 120°C
10: 100°C
11: 90°C
1:0
TRTH
00
C
0
a
2
OTPD
R
ic
3
OTST
00
Thermal roll off status
0: none roll off
1: roll off
in
4
TRST
w
5
o
n
7:6
fi
00: 100%
SSCR：Spread Spectrum Control Register (Address 78H)
Bit
Symbol
www.awinic.com
R/W
Description
21
Default
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
7
RESERVED
R
6
PWMDIS1
RW
5
PWMDIS0
RW
Reserved
V1.0
0
0: PWM duty of LED 13~24 determined by BR12~BR23
0
1: PWM duty of LED 13~24 fixed as 100%
0: PWM duty of LED 1~12 determined by BR0~BR11
1:0
CLT
a
l
ti
RW
Spread spectrum cycle time
00: 1980μs (default)
01: 1200μs
10: 820μs
11: 660μs
n
RW
d
e
SSR
Spread spectrum range
00: ±5%
01: ±15%
10: ±25%
11: ±35%
fi
3:2
RW
o
n
SSE
Spread spectrum enable
0: Disable
1: Enable
C
4
0
1: PWM duty of LED 1~12 fixed as 100%
0
00
00
UVCR：UVLO Control Register (Address 79H)
REXT_ST
R/W
R
Description
Default
REXT status
00: Normal
10: REXT is open
01: REXT is short or OCP
11: Not defined
00
OCP Threshold
0: 85mA
1: 55mA
0
OCP disable
0: enable OCP
1: disable OCP
0
w
in
7:6
Symbol
ic
Bit
RW
4
OCPD
RW
3
PORST
R
Power-up reset status
0: no power-on reset
1: power-on reset (cleared after read out)
0
2
UVST
R
UVLO status
0: No UVLO detected
1: UVLO detected
0
OCPTH
a
5
www.awinic.com
22
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
0
UVPD
UVDIS
RW
0
RW
UVLO detect disable
0: UVLO detect enable, when under-voltage event
occurs, UVCR.UVST will be set.
1: UVLO detect disable
0
a
l
1
UVLO protect disable
0: UVLO protect enable, when under-voltage event
occurs, device will clear GCR.CHIPEN to 0.
1: UVLO protect disable
7:1
RESERVED
R
RGBMD
RW
Default
Reserved
RGB configure mode enable
0: disable
1: enable, every 3 LEDs share a common brightness.
0000 000
0
o
n
fi
0
Description
n
R/W
d
e
Symbol
ti
GCR2：Global Control Register 2(Address 7AH)
Bit
V1.0
GCR4：Global Control Register 4(Address 7CH)
R/W
7:3
RESERVED
R
2
SRR
RW
Description
Reserved
C
Symbol
Default
0000 0
Slew rate control for LED output rising time
0: 1ns
1: 6ns
0
Slew rate control for LED output falling time
00: 1ns
01: 3ns
10: 6ns
11:10ns
00
in
ic
Bit
SRF
RW
a
w
1:0
VER：Version Register (Address 7Eh)
Bit
Symbol
R/W
7:0
VER
R
Description
Chip version
Default
0xA8
RESET： Software Reset Register (Address 7FH)
Bit
Symbol
www.awinic.com
R/W
Description
23
Default
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
7:0
RESET
RW
Write 00H to the register will reset all registers to their
default value.
The chip ID 0x18 will be read out from the register.
V1.0
0x18
WBR： Red Scaling for White Balance(Address 90H)
7:0
WBR
RW
Description
Red Scaling for White Balance.
WBG： Green Scaling for White Balance(Address 91H)
R/W
7:0
WBG
RW
Description
d
e
Symbol
0xFF
Green Scaling for White Balance.
Default
0xFF
fi
Bit
Default
a
l
R/W
ti
Symbol
n
Bit
Symbol
R/W
7:0
WBB
RW
Description
Blue Scaling for White Balance.
Default
0xFF
C
Bit
o
n
WBB： Blue Scaling for White Balance(Address 92H)
PATCFG： Pattern Configure Register(Address A0H)
7:4
RESERVED
R
SWITCH
Description
Reserved
Default
0000
RW
Switch on or off at manual mode.
0: LED off
1: LED on
0
Ramp enable
0: ramp disable
1: ramp enable
0
w
3
R/W
ic
Symbol
in
Bit
RW
1
MODE
RW
Breath pattern control mode selection
0: manual mode (default)
1: auto breath pattern mode
0
0
PATEN
RW
Auto breath pattern controller enable
0: disable
1: enable
0
RAMPE
a
2
PATGO： Pattern Configure Register(Address A1H)
www.awinic.com
24
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
Bit
Symbol
R/W
Description
7:3
RESERVED
R
Reserved
0
0
Default
0000 0
ENDFLG
R
1
STATE
R
Auto breath pattern status
0: pattern is stop
1: pattern is running
ti
RW
Auto breath pattern run control
Write “1” to run auto breath pattern
Note: You shall write “0” and then write “1” to this bit to
restart a new auto breath pattern.
0
d
e
n
RUN
a
l
2
Auto breath pattern loop end flag
0: loop is not over
1: loop is over (will be cleared after reading out)
0
V1.0
PATT0： Pattern Timer0(Address A2H)
Bit
Symbol
R/W
Description
T0
Time
0s
1000
2.1s
0.13s
1001
2.6s
0.26s
1010
3.1s
0.38s
1011
4.2s
0100
0.51s
1100
5.2s
0101
0.77s
1101
6.2s
0110
1.04s
1110
7.3s
0111
1.6s
1111
8.3s
T1
Time
T1
Time
0000
0.04s
1000
2.1s
0001
0.13s
1001
2.6s
0010
0.26s
1010
3.1s
0011
0.38s
1011
4.2s
0100
0.51s
1100
5.2s
0101
0.77s
1101
6.2s
0110
1.04s
1110
7.3s
0111
1.6s
1111
8.3s
0000
0001
RW
0010
0011
C
RISE
a
3:0
w
in
ic
7:4
Time
o
n
T0
ON
RW
fi
Ramp rise time
Default
0000
Hold on time
0000
PATT1： Pattern Timer1(Address A3H)
Bit
Symbol
www.awinic.com
R/W
Description
25
Default
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
Ramp fall time
Time
0000
0s
1000
2.1s
0001
0.13s
1001
2.6s
0010
0.26s
1010
3.1s
0011
0.38s
1011
4.2s
0100
0.51s
1100
5.2s
0101
0.77s
1101
6.2s
0110
1.04s
1110
7.3s
0111
1.6s
1111
T3
Time
T3
0000
0.04s
0001
0.13s
0010
0.26s
0011
0.38s
0100
0.51s
RW
0101
0110
1001
2.6s
1010
3.1s
1011
4.2s
1100
5.2s
0.77s
1101
6.2s
1.04s
1110
7.3s
1.6s
1111
8.3s
0000
C
0111
2.1s
fi
OFF
Time
1000
o
n
3:0
8.3s
d
e
Hold off time
0000
a
l
RW
T2
ti
FALL
Time
n
7:4
T2
PATT2： Pattern Control Register 1(Address A4H)
Symbol
R/W
Description
ic
Bit
Default
End point of the auto-breath pattern
LE
RW
in
7:6
3:0
LB
RW
RPT[11:8]
RW
4 MSB of loop times.
w
00
Other: pattern finally stop at ON state
Start point of the auto-breath loop pattern
00: pattern start from RISE state
01: pattern start from ON state
10: pattern start from FALL state
11: pattern start from OFF state
a
5:4
00: pattern finally stop at OFF state
00
0000
PATT3： Pattern Control Register 2 (Address A5H)
Bit
Symbol
R/W
7:0
RPT[7:0]
RW
www.awinic.com
Description
8 LSB of auto-breath pattern repeat times
Note: when RPT[11:0]=0, the pattern will run forever. In
this case, you can switch auto-breath mode to manual
26
Default
0x00
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
mode and then turn the pattern off.
FADEH： Maximum Brightness for Auto Breath (Address A6H)
R/W
7:0
FADEH
RW
Description
Default
Maximum brightness configure for auto breath.
a
l
Symbol
0x00
d
e
n
ti
Bit
FADEL： Minimum Brightness for Auto Breath(Address A7H)
R/W
7:0
FADEL
RW
Description
fi
Symbol
Minimum brightness configure for auto breath.
o
n
Bit
Default
0x00
Symbol
R/W
7:0
GCOLR
RW
Description
Red mixing for group color.
in
ic
Bit
C
GCOLR： Red Mixing for Group Color (Address A8H)
Default
0x00
GCOLG： Green Mixing for Group Color(Address A9H)
GCOLG
R/W
RW
Description
Green mixing for group color.
Default
0x00
a
7:0
Symbol
w
Bit
GCOLB： Blue Mixing for Group Color(Address AAH)
Bit
Symbol
R/W
7:0
GCOLB
RW
Description
Blue mixing for group color.
Default
0x00
GCFG0： Group Configure Register0 (Address ABH)
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27
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
Symbol
R/W
Description
Default
Group-Control-Mode/Pattern-Control-Mode enable for
LED1~LED24
If bit PATEN in register PATCFG is set to “0”,
GE[0]=1: LED1~3 work in group mode
GE[1]=1: LED4~6 work in group mode
GE[2]=1: LED7~9 work in group mode
GE[3]=1: LED10~12 work in group mode
GE[4]=1: LED13~15 work in group mode
GE[5]=1: LED16~18 work in group mode
GE[6]=1: LED19~21 work in group mode
GE[7]=1: LED22~24 work in group mode
GE[7:0]
RW
0x00
n
7:0
ti
a
l
Bit
V1.0
o
n
fi
d
e
If bit PATEN in register PATCFG is set to “1”,
GE[0]=1: LED1~3 work in auto breath pattern mode
GE[1]=1: LED4~6 work in auto breath pattern mode
GE[2]=1: LED7~9 work in auto breath pattern mode
GE[3]=1: LED10~12 work in auto breath pattern mode
GE[4]=1: LED13~15 work in auto breath pattern mode
GE[5]=1: LED16~18 work in auto breath pattern mode
GE[6]=1: LED19~21 work in auto breath pattern mode
GE[7]=1: LED22~24 work in auto breath pattern mode
Symbol
R/W
7:5
RESERVED
R
in
GCOLDIS
RW
a
w
4
3:0
RESERVED
www.awinic.com
R
Description
Reserved
ic
Bit
C
GCFG1： Group Configure Register1 (Address ACH)
000
Group/pattern color disable
0: Group/pattern color enable, all LEDs in group/pattern
mode share the common COL parameters decided by
GCOL_R/G/B.
1: Group/pattern color disable, all LEDs’ color
parameter in group/pattern mode is configured by their
respective register COL.
Reserved
28
Default
0
0000
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
APPLICATION INFORMATION
REXT
The selection of REXT determined the maximum LED1~LED24 current Imax as described in below formula (1).
I max
K
(1)
REXT
a
l
Where K = 80V, the recommended minimum value of REXT is 1KΩ.
When REXT = 2KΩ, Imax = 40mA
fi
PCB LAYOUT CONSIDERATION
d
e
n
ti
When REXT = 4KΩ, Imax = 20mA.
o
n
AW21024 is a 24-channel LEDs driver programmed via I2C compatible interface. When all LEDs are operating,
the device power dissipation is large. To obtain the good thermal performance and avoid thermal shutdown,
PCB layout should be considered carefully. Here are some guidelines:
C
1. The C1、C2、 CLED should be placed as close to the chip as possible.
2. The REXT should be placed as close to the chip as possible.
a
w
in
ic
3. The Thermal PAD must be well connecting to the GND of the PCB, and add as many thermal vias as
possible beneath the thermal PAD on the PCB for the heat conductivity of the device and PCB.
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29
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
TAPE AND REEL INFORMATION
TAPE DIMENSIONS
REEL DIMENSIONS
P1
P0
P2
K0
W
a
l
B0
D1
A0
ti
Cavity
d
e
n
A0：Dimension designed to accommodate the component width
B0：Dimension designed to accommodate the component length
K0：Dimension designed to accommodate the component thickness
W：Overall width of the carrier tape
P0：Pitch between successive cavity centers and sprocket hole
P1：Pitch between successive cavity centers
P2：Pitch between sprocket hole
D1：Reel Diameter
D0：Reel Width
D0
fi
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pin 1
Q1
Q2
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
Q3
Q4
o
n
Sprocket Holes
Q1
Q2
Q3
Q4
User Direction of Feed
a
w
in
ic
C
Pocket Quadrants
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30
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
PACKAGE DESCRIPTION
PIN1 CORNER
a
l
4.00±0.10
d
e
fi
TOP VIEW
n
ti
4.00±0.10
0.20 REF
o
n
0.85±0.05
0.00~0.05
C
SIDE VIEW
2.80 T YP
9
16
0.40 TYP
8
2.90±0.10
SYMM
℄
32x(0.20±0.05)
0.30 REF
32x(0.30±0.05)
1
24
32
25
SYMM
0.30 REF ℄
a
w
in
ic
17
2.90±0.10
BOTTOM VIEW
Unit：mm
www.awinic.com
31
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
LAND PATTERN DATA
3.00 REF
32 X 0.25 REF
1
a
l
25
32
SYMM
3.00 REF
n
2.90 REF
ti
24
d
e
℄
8
17
SYMM
o
n
℄
fi
16
9
32X 0.20 TYP
32X 0.40 TYP
0.40 TYP
SOLDER MASK
OPENING
ic
0.05 MAX
All AROUND
C
2.90 REF
in
METAL
NON SOLDER MASK DEFINED
0.05 MIN
All AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK DEFINED
a
w
Unit：mm
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32
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
REVISION HISTORY
Date
Change Record
V1.0
Sep. 2019
Officially released
a
w
in
ic
C
o
n
fi
d
e
n
ti
a
l
Version
www.awinic.com
33
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW21024
Sep. 2019
V1.0
DISCLAIMER
All trademarks are the property of their respective owners. Information in this document is believed to be
accurate and reliable. However, Shanghai AWINIC Technology Co., Ltd (AWINIC Technology) does not give
any representations or warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such information.
a
l
AWINIC Technology reserves the right to make changes to information published in this document, including
without limitation specifications and product descriptions, at any time and without notice. Customers shall
obtain the latest relevant information before placing orders and shall verify that such information is current and
complete. This document supersedes and replaces all information supplied prior to the publication hereof.
d
e
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ti
AWINIC Technology products are not designed, authorized or warranted to be suitable for use in medical,
military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an AWINIC
Technology product can reasonably be expected to result in personal injury, death or severe property or
environmental damage. AWINIC Technology accepts no liability for inclusion and/or use of AWINIC Technology
products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own
risk.
fi
Applications that are described herein for any of these products are for illustrative purposes only. AWINIC
Technology makes no representation or warranty that such applications will be suitable for the specified use
without further testing or modification.
o
n
All products are sold subject to the general terms and conditions of commercial sale supplied at the time of
order acknowledgement.
C
Nothing in this document may be interpreted or construed as an offer to sell products that is open for
acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other
industrial or intellectual property rights.
ic
Reproduction of AWINIC information in AWINIC data books or data sheets is permissible only if reproduction
is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices.
AWINIC is not responsible or liable for such altered documentation. Information of third parties may be subject
to additional restrictions.
a
w
in
Resale of AWINIC components or services with statements different from or beyond the parameters stated by
AWINIC for that component or service voids all express and any implied warranties for the associated AWINIC
component or service and is an unfair and deceptive business practice. AWINIC is not responsible or liable for
any such statements.
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