AW32705/AW32710
Oct. 2018 V1.0
Over-Voltage Protection Load Switch with Surge Protection
GENERAL DESCRIPTION
The AW327XX family OVP load switch features
surge protection, an internal clamp circuit protects
the device from surge voltages up to 100V.
ti
a
n
n
This device features over-temperature protection
that prevents itself from thermal damaging.
o
Smartphones
Tablets
Charging Ports
The AW327XX is available in a RoHS compliant
WLCSP 1.17×1.57-12B package.
C
The device features an open-drain output ACOK,
when VIN_UVLO < VIN < VIN_OVLO and the switch is
on, ACOK will be driven low to indicate a good
power input, otherwise it is high impedance.
APPLICATIONS
The default OVP threshold is 6.8V (AW32705) and
10.5V (AW32710), the OVP threshold can be
adjusted from 4V to 20V through external OVLO
pin.
e
The AW327XX features an ultra-low 24mΩ (typ.)
Rdson nFET load switch. When input voltage
exceeds the OVP threshold, the switch is turned off
very fast to prevent damage to the protected
downstream devices. The IN pin is capable of
withstanding fault voltages up to 35VDC.
fi
d
Surge protection
IEC 61000-4-5: > 100V
Integrated low Rdson nFET switch: typical 24mΩ
5A continuous current capability
Default Over-Voltage Protection (OVP) threshold
AW32705: 6.8V
AW32710: 10.5V
OVP threshold adjustable range: 4V to 20V
Input system ESD protection
IEC 61000-4-2 Contact discharge: ±8kV
IEC 61000-4-2 Air gap discharge: ±15kV
Input maximum voltage rating: 35VDC
Fast turn-off response: typical 50ns
Over-Temperature Protection (OTP)
Under-Voltage Lockout (UVLO)
WLCSP 1.17×1.57-12B package
l
FEATURES
ic
TYPICAL APPLICATION CIRCUIT
USB
Port
CIN
0.1µF
50V
in
TVS
a
w
Optional
Optional
R1
Charger/
PMIC
OUT
IN
VIO
AW32705
OVLO AW32710
R2
COUT
1µF
Battery
10kΩ
ACOK
Controller
EN
GND
Figure 1 AW327XX typical application circuit
R1 and R2 are used for OVP threshold adjustment, to use default OVP threshold, connect OVLO to ground.
All the trademarks mentioned in the document are the property of their owners.
www.awinic.com.cn
1
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW32705/AW32710
Oct. 2018 V1.0
DEVICE COMPARISON TABLE
VIN_OVLO (V)
Min.
Typ.
Max.
VIN_OVLO
hysteresis (mV)
AW32705
VIN rising
6.66
6.80
6.94
140
AW32710
VIN rising
10.29
10.50
10.71
210
ti
a
l
Condition
Device
PIN CONFIGURATION AND TOP MARK
AW327XXCSR Marking
(Top View)
4
A
EN
OUT
OUT
GND
B
ACOK
OUT
IN
GND
C
OVLO
IN
IN
GND
2
1
3
4
e
3
XX
YY
A
fi
d
2
B
C
n
1
n
AW327XXCSR
(Top View)
C
o
XX – LT: AW32705CSR, TX: AW32710CSR
YY – Production Tracing Code
Figure 2 Pin Configuration and Top Mark
Pin
A1
ic
PIN DEFINITION
Name
EN
Description
Enable pin, active low
ACOK
Power good flag, active-low, open-drain
C1
OVLO
OVP threshold adjustment pin
C2, C3, B3
IN
w
in
B1
Switch input and device power supply
OUT
Switch output
A4, B4, C4
GND
Device ground
a
A2, A3, B2
www.awinic.com.cn
2
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW32705/AW32710
Oct. 2018 V1.0
FUNCTIONAL BLOCK DIAGRAM
OUT
Clamp
Detect
Gate Driver &
Charge pump
Logic Control
ACOK
e
OV comp
n
VIN Divider
Selection
OVLO
ti
a
l
IN
UV&OT comp
Oscillator
EN
GND
fi
d
Bandgap
& Ibias
a
w
in
ic
C
o
n
Figure 3 Functional Block Diagram
www.awinic.com.cn
3
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW32705/AW32710
Oct. 2018 V1.0
TYPICAL APPLICATION CIRCUITS
CIN
0.1µF
50V
VIO
AW32705
OVLO AW32710
10kΩ
Controller
ACOK
Optional
EN
n
GND
USB
Port
OUT
IN
TVS
CIN
0.1µF
50V
R1
AW32705
OVLO AW32710
R2
VIO
COUT
1µF
Battery
10kΩ
ACOK
EN
Charger/
PMIC
Controller
n
Optional
e
AW327XX typical application circuit(using default OVP threshold)
fi
d
Figure 4
Battery
COUT
1µF
l
TVS
Charger/
PMIC
OUT
IN
ti
a
USB
Port
o
GND
C
Figure 5 AW327XX typical application circuit(using external resistors set OVP threshold)
Notice for Typical Application Circuits:
ic
1. If VBUS is required to pass surge voltage greater than 100V, external TVS is needed, the maximum
clamping voltage of the TVS should be below 37V.
2. When the default OVP threshold is used, connect OVLO pin to GND directly or through a 0Ω resistor.
OVLO pin cannot be left floating.
in
3. If R1 and R2 are used to adjust the OVP threshold, it is better to use 1% precision resistors to improve the
OVP threshold precision.
w
4. If ACOK is not used, it can be left floating, or short to GND.
a
5. CIN = 0.1μF is recommended for typical application, larger CIN is also acceptable. The rated voltage of CIN
should be larger than the TVS maximum clamping voltage, if no TVS is applied and only AW327XX is
used, the rated voltage of CIN should be 50V.
6. COUT = 1μF is recommended for typical application, larger COUT is also acceptable. The rated voltage of
COUT should be larger than the OVP threshold. For example, if the OVP threshold is 6.8V, the rated voltage
of COUT should be 10V or higher.
www.awinic.com.cn
4
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW32705/AW32710
Oct. 2018 V1.0
ORDERING INFORMATION
-40°C~85°C
WLCSP
1.17mm×1.57mm12B
ABSOLUTE MAXIMUM RATINGS (NOTE 1)
Condition
Input voltage
VOUT
Output voltage
VOVLO
OVLO voltage
VACOK
ACOK voltage
MSL1
n
VIN
Parameter
TX
MSL1
o
Symbol
LT
Delivery
Form
ROHS+HF
3000
units/
Tape and
Reel
ROHS+HF
3000
units/
Tape and
Reel
l
-40°C~85°C
WLCSP
1.17mm×1.57mm12B
Environmental
Information
ti
a
Marking
n
AW32710CSR
Package
e
AW32705CSR
Temperature
fi
d
Part Number
Moisture
Sensitivity
Level
Min.
Max.
Unit
-0.3
35
V
-0.3
See(NOTE 2)
V
-0.3
6
V
-0.3
6
V
-0.3
6
V
EN voltage
ISW
Continuous current of switch
IN-OUT(NOTE 3)
Continuous current on IN and
OUT pin
5
A
IPEAK
Peak current
Peak input and output current
on IN and OUT pin(10ms)
8
A
IDIODE
Continuous diode current
Continuous forward current
through the nFET body diode
1.5
A
ic
C
VEN
Ambient temperature
-40
85
°C
TJ
Junction temperature
-40
150
°C
TSTG
Storage temperature
-65
150
°C
TLEAD
Soldering temperature
At leads, 10 seconds
260
°C
Input surge protection
IEC61000-4-5 test with 2Ω
equivalent series resistance
w
in
TA
Surge
100
V
a
NOTE1: Conditions out of those ranges listed in “absolute maximum ratings” may cause permanent damages
to the device. In spite of the limits above, functional operation conditions of the device should within the ranges
listed in “recommended operating conditions”. Exposure to absolute-maximum-rated conditions for prolonged
periods may affect device reliability.
NOTE2: 29V or VIN+0.3V, whichever is smaller.
NOTE3: Limited by thermal design.
www.awinic.com.cn
5
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW32705/AW32710
Oct. 2018 V1.0
THERMAL INFORMATION
Symbol
RJA
Parameter
Condition
Value
Unit
Thermal
resistance
from
junction to ambient (NOTE 1)
In free air
90
°C/W
ti
a
ESD AND LATCH-UP RATINGS
ILatch-up
Value
Unit
IEC61000-4-2 system ESD on
IN pin
Contact discharge
±8
kV
±15
kV
Human Body Model
ANSI/ESDA/JEDEC JS-001
±2
kV
Charged Device Model
JESD22-C101
±1.5
kV
Machine Model
JESD22-A115C
±200
V
Latch-up
JEDEC78
±200
mA
n
Condition
Air gap discharge
e
VESD
Parameter
fi
d
Symbol
l
NOTE1: Thermal resistance from junction to ambient is highly dependent on PCB layout.
VIN
Input DC voltage
CIN
Input capacitance
Output load capacitance
Min.
Typ.
3
Max.
Unit
30
V
0.1
μF
1
μF
a
w
in
ic
COUT
o
Parameter
C
Symbol
n
RECOMMENDED OPERATING CONDITIONS
www.awinic.com.cn
6
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW32705/AW32710
Oct. 2018 V1.0
ELECTRICAL CHARACTERISTICS
TA = -40°C to 85°C unless otherwise noted. Typical values are guaranteed for VIN = 5V, CIN = 0.1μF, IIN≤ 5A and
TA = 25°C.
Symbol
Description
Test Conditions
VIN_CLAMP
Input clamp voltage
IIN = 10mA
Rdson
Switch on resistance
VIN = 5V, IOUT = 1A, TA = 25°C
24
35
mΩ
Input quiescent current
VIN = 5V, VOVLO=0V,IOUT = 0A
70
140
μA
IIN_OVLO
Input current at overvoltage condition
VIN = 5V, VOVLO=3V,VOUT = 0V
67
130
μA
VOVLO_TH
OVLO set threshold
1.24
V
20
V
0.33
V
OVP threshold
adjustable range
VOVLO_SEL
External OVLO select
threshold
1.20
4
OVLO pin leakage
current
OVLO rising
Hysteresis
0.19
n
VOVLO=VOVLO_TH
o
Protection
Max.
VIN rising
Units
l
V
ti
a
n
1.16
e
VOVLO_RNG
IOVLO
Typ.
36.3
fi
d
IQ
Min.
0.26
0.06
-0.2
6.66
V
0.2
6.80
μA
6.94
VIN_OVLO
OVP trip level
C
AW32705
Hysteresis
0.14
V
VIN rising
10.29
10.50
10.71
w
TSDN
a
TSDN_HYS
RDCHG
Hysteresis
0.21
VIN rising
2.9
Hysteresis
0.1
UVLO trip level
in
VIN_UVLO
ic
AW32710
3.0
V
Shutdown temperature
150
°C
Shutdown temperature
hysteresis
20
°C
50
Ω
Output discharge
resistance
www.awinic.com.cn
VOUT=7V,VOVLO=3V
7
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW32705/AW32710
Oct. 2018 V1.0
ELECTRICAL CHARACTERISTICS (CONTINUED)
TA = -40°C to 85°C unless otherwise noted. Typical values are guaranteed for V IN = 5V, CIN = 0.1μF, IIN≤ 5A and
TA = 25°C.
Symbol
Description
Test Conditions
Min.
Typ.
Max.
ISINK=1mA
ILEAK_ACOK
ACOK leakage current
VIO=5V, ACOK de-asserted
VIH
EN input high voltage
VIL
EN input low voltage
ILEAK_EN
EN leakage current
-0.5
e
1.2
n
ACOK output low
voltage
VEN = 5V
0
fi
d
VOL
ti
a
l
Digital Logical Interface
Units
Timing Characteristics (Figure 6)
0.4
V
0.5
μA
V
0.5
V
2
μA
From VIN > VIN_UVLO to 10%
VOUT
15
ms
Start-up time
From VIN > VIN_UVLO to ACOK
low
30
ms
tON
Switch turn-on time
RL = 100Ω, CL = 22μF, VOUT
from 10% VIN to 90% VIN
2
ms
tOFF
Switch turn-off time
CL = 0μF, RL = 100Ω, VIN >
VIN_OVLO to VOUT stop rising,
VIN rise at 10V/μs
50
ns
o
C
tSTART
n
Debounce time
tDEB
in
ic
TIMING DIAGRAM
a
w
VIN
OVP trip level
tDEB
tDEB
VOUT
tON
tON
tOFF
VEN
VACOK
tSTART
tSTART
Figure 6 Timing diagram
www.awinic.com.cn
8
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW32705/AW32710
Oct. 2018 V1.0
TYPICAL CHARACTERISTICS
30.0
28.0
27.5
25.0
24.0
ti
a
26.0
l
30.0
Rdson(mΩ)
22.5
20.0
22.0
17.5
15.0
20.0
1
2
3
4
5
-40
Output Current(A)
60
85
fi
d
n
Input Supply Current (A)
350
28.0
26.0
20.0
0
4
8
C
o
24.0
22.0
12
16
300
-40℃
250
25℃
200
85℃
150
100
50
0
20
0
5
10
Input Voltage(V)
ic
OVLO Set Threshold Voltage(V)
w
1.02
1.00
0.98
0.96
-15
10
35
Temperature (°C)
60
85
30
35
1.220
1.200
1.180
1.160
-40
Figure 11 Normalized Internal OVP Threshold vs. Temp.
www.awinic.com.cn
25
1.240
Normalized to TA = 25°
C
-40
20
Figure 10 Input Supply Current vs. Supply Voltage
in
1.04
15
Input Voltage (V)
Figure 9 Rdson vs. Input Voltage (IOUT = 1A)
Normalized Threshold Voltage
35
Figure 8 Rdson vs. Temp. (IOUT = 1A)
30.0
a
10
Temperature(℃)
Figure 7 Rdson vs. Output Current
Rdson(mΩ)
-15
e
0
n
Rdson(mΩ)
VIN = 5V, VEN = 0V, VOVLO = 0V, CIN = 0.1μF, COUT = 1μF, and TA = 25°C unless otherwise specified.
9
-15
10
35
Temperature (°C)
60
85
Figure 12 OVLO set threshold vs. Temp.
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW32705/AW32710
Oct. 2018 V1.0
TYPICAL CHARACTERISTICS (CONTINUED)
VIN = 5V, VEN = 0V, VOVLO = 0V, CIN = 0.1μF, COUT = 1μF, and TA = 25°C unless otherwise specified.
VIN
5V / div
VIN
5V / div
C1
C1
ACOK
2V / div
C3
IOUT
100mA / div
C4
ti
a
ACOK
2V / div
C3
VOUT
5V / div
C2
C4
n
C2
l
VOUT
5V / div
20ms / div
IOUT
500mA / div
e
20ms / div
Figure 14 Power-up (COUT = 100μF, 100mA load)
VIN
5V / div
n
C1
fi
d
Figure 13 Power-up (COUT = 1μF, 100mA load).
o
VOUT
5V / div
C2
C
ACOK
2V / div
C3
ic
1ms / div
a
w
in
Figure 15 OVP Response (AW32705)
www.awinic.com.cn
10
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW32705/AW32710
Oct. 2018 V1.0
DETAILED FUNCTIONAL DESCRIPTION
Device Operation
If the AW327XX is enabled and the input voltage is between UVLO and OVP threshold, the internal charge
pump begins to work after debounce time, the gate of the nFET switch will be slowly charged high till the switch
l
is fully on. ACOK will be driven low about 30ms after VIN valid, indicating the switch is on with a good power
ti
a
input. If the input voltage exceeds the OVP trip level, the switch will be turned off in about 50ns. If EN is pulled
high, or input voltage falls below UVLO threshold, or over-temperature happens, the switch will also be turned
off.
Surge Protection
e
n
The AW327XX integrates a clamp circuit to suppress input surge voltage. For surge voltages between VIN_OVLO
and VIN_CLAMP, the switch will be turned off but the clamp circuit will not work. For surge voltages greater than
VIN_CLAMP, the internal clamp circuit will detect surge voltage level and discharge the surge energy to ground.
The device can suppress surge voltages up to 100V.
fi
d
Over-Voltage Protection
If the input voltage exceeds the OVP rising trip level, the switch will be turned off in about 50ns. The switch will
remain off until VIN falls below the OVP falling trip level.
n
OVP Threshold Adjustment
o
If the default OVP threshold is used, OVLO pin must be grounded. If OVLO pin is not grounded, and by
connecting external resistor divider to OVLO pin as shown in the typical application circuit, between IN and GND,
the OVP threshold can be adjusted as following:
C
VIN_OVLO =
R1+R2
VOVLO_TH
R2
in
ACOK Output
ic
For example, if we select R1 = 1MΩ and R2 = 100kΩ, then the new OVP threshold calculated from the above
formula is 13.2V. The OVP threshold adjustment range is from 4V to 20V. When the OVLO pin voltage VOVLO
exceeds VOVLO_SEL (0.26V typical), VOVLO is compared with the reference voltage VOVLO_TH (1.2V typical) to judge
whether input supply is over-voltage.
The device features an open-drain output ACOK, it should be connected to the system I/O rail through a pullup resistor. If the device is enabled and VIN_UVLO < VIN < VIN_OVLO, ACOK will be driven low indicating the switch
w
is on with a good power input. If OVP, UVLO, or OT occurs, or EN is pulled high, the switch will be turned off
and ACOK will be pulled high.
a
USB On-The-Go (OTG) Operation
If VIN = 0V and OUT is supplied by OTG voltage, the body diode of the load switch conducts current from OUT
to IN and the voltage drop from OUT to IN is approximately 0.7V. When VIN > VIN_UVLO, internal charge pump
begins to open the load switch after debounce time (about 15ms). After switch is fully on, current is supplied
through switch channel and the voltage drop from OUT to IN is minimum.
www.awinic.com.cn
11
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW32705/AW32710
Oct. 2018 V1.0
PCB LAYOUT CONSIDERATION
To obtain the optimal performance of AW327XX, PCB layout should be considered carefully. Here are some
guidelines:
l
1. All the peripherals should be placed as close to the device as possible. Place the input capacitor CIN on the
top layer (same layer as the AW327XX) and close to IN pin, and place the output capacitor COUT on the top layer
(same layer as the AW327XX) and close to OUT pin.
ti
a
2. If external TVS is used, IN pin routing passes through the external TVS firstly, and then connect AW327XX.
3. Red bold paths on figure 4 and 5 are power lines that will flow large current, please route them on PCB as
straight, wide and short as possible.
n
4. The path from device ground pins to the system ground plane must be as short as possible.
5. If R1 and R2 are used, route OVLO line on PCB as short as possible to reduce parasitic capacitance.
e
6. The power trace from USB connector to AW327XX may suffer from ESD event, keep other traces away from
it to minimize possible EMI and ESD coupling.
a
w
in
ic
C
o
n
fi
d
7. Use rounded corners on the power trace from USB connector to AW327XX to decrease EMI coupling.
www.awinic.com.cn
12
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW32705/AW32710
Oct. 2018 V1.0
TAPE AND REEL INFORMATION
TAPE DIMENSIONS
REEL DIMENSIONS
P1
P2
P0
l
K0
ti
a
W
B0
D1
A0
n
Cavity
fi
d
e
A0：Dimension designed to accommodate the component width
B0：Dimension designed to accommodate the component length
K0：Dimension designed to accommodate the component thickness
W：Overall width of the carrier tape
P0：Pitch between successive cavity centers and sprocket hole
P1：Pitch between successive cavity centers
P2：Pitch between sprocket hole
D0：Reel width
D1：Reel diameter
n
D0
C
o
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
Q3
Q4
Q3
Q4
ic
Q1
User Direction of Feed
Pocket Quadrants
in
All dimensions are nominal
D0
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P0
(mm)
P1
(mm)
P2
(mm)
W
(mm)
Pin1
Quadrant
179.00
9.00
1.29
1.69
0.73
2.00
4.00
4.00
8.00
Q2
a
w
D1
(mm)
www.awinic.com.cn
13
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW32705/AW32710
Oct. 2018 V1.0
PACKAGE DESCRIPTION
1.570
±0.025
Pin1
Corner
ti
a
l
1.170
±0.025
e
n
Top View
0.380
±0.025
fi
d
0.619
Max
Ball TYP
0.194
±0.020
4
12X(∅0.268±0.020)
C
B
SYMM
℄
A
0.400
TYP
1.200
SYMM
℄
Bottom View
Unit: mm
a
w
in
3
C
ic
0.800
0.400
TYP
2
o
1
n
Side View
www.awinic.com.cn
14
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW32705/AW32710
Oct. 2018 V1.0
LAND PATTERN DATA
1
2
3
4
12X(∅0.240)
0.400
TYP
n
C
e
SYMM
℄
fi
d
0.400
TYP
0.05 MIN
All AROUND
SOLDER MASK
OPENING
n
0.05 MAX
All AROUND
SYMM
℄
ti
a
B
l
A
C
Non-solder Mask Defined
o
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
Solder Mask Defined
a
w
in
ic
Unit: mm
www.awinic.com.cn
15
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW32705/AW32710
Oct. 2018 V1.0
REVISION HISTORY
Date
Change Record
V1.0
October 2018
Datasheet V1.0 Released
a
w
in
ic
C
o
n
fi
d
e
n
ti
a
l
Vision
www.awinic.com.cn
16
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW32705/AW32710
Oct. 2018 V1.0
DISCLAIMER
l
Information in this document is believed to be accurate and reliable. However, Shanghai AWINIC Technology
Co., Ltd (AWINIC Technology) does not give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability for the consequences of use of such
information.
ti
a
AWINIC Technology reserves the right to make changes to information published in this document, including
without limitation specifications and product descriptions, at any time and without notice. Customers shall
obtain the latest relevant information before placing orders and shall verify that such information is current and
complete. This document supersedes and replaces all information supplied prior to the publication hereof.
fi
d
e
n
AWINIC Technology products are not designed, authorized or warranted to be suitable for use in medical,
military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an AWINIC
Technology product can reasonably be expected to result in personal injury, death or severe property or
environmental damage. AWINIC Technology accepts no liability for inclusion and/or use of AWINIC Technology
products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own
risk.
n
Applications that are described herein for any of these products are for illustrative purposes only. AWINIC
Technology makes no representation or warranty that such applications will be suitable for the specified use
without further testing or modification.
All products are sold subject to the general terms and conditions of commercial sale supplied at the time of
order acknowledgement.
o
Nothing in this document may be interpreted or construed as an offer to sell products that is open for
acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other
industrial or intellectual property rights.
C
Reproduction of AWINIC information in AWINIC data books or data sheets is permissible only if reproduction is
without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. AWINIC
is not responsible or liable for such altered documentation. Information of third parties may be subject to
additional restrictions.
a
w
in
ic
Resale of AWINIC components or services with statements different from or beyond the parameters stated by
AWINIC for that component or service voids all express and any implied warranties for the associated AWINIC
component or service and is an unfair and deceptive business practice. AWINIC is not responsible or liable for
any such statements.
www.awinic.com.cn
17
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
工商网监
湘ICP备2023018690号
