AW86927
September 2021 V1.2
11V Fast Startup With F0 Detect And Tracking LRA Haptic Driver
Features
General Description
1MHz I2C Bus
8-KByte Memory
12k/24k/48k input wave sampling rate
F0 detect and tracking
Advance autobrake engine integrated
Playback mode:
Memory playback
3 Trigger playback
One wire playback
Cont playback
Drive signal monitor for LRA protect
Drive Compensation Over Battery Discharge
Fast Start Up Time ＜1ms
Dedicated interrupt output pin
Boost output voltage up to 11V
VOUT=9V@Vbat=4.2V for 8Ω LRA
Support automatically switch to standby mode
Standby current：8uA@Vbat=3.6V
Shutdown current：0.1uA
Supply voltage range 3 to 5.5V
Short-Circuit Protection, Over-Temperature
cC
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Protection, Under-Voltage Protection
FCQFN 2mm × 3mm × 0.55mm -20L Package
Applications
Tablets
Wearable Devices
fid
Mobile phones
AW86927 integrates a 8KByte SRAM for userdefined waveforms to achieve a variety of
vibration experiences, supporting 3 sampling
rate(12k/24k/48k) of waveforms loaded in SRAM,
supporting output waveform sampling rate upsampling to 48k.
AW86927 integrates an autobrake engine to
suppress the aftershocks to zero for different
drive waveforms(short or long) on different LRA
motors.
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Resistance-Based LRA Diagnostics
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Real time playback(Up to 4KByte FIFO)
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AW86927 is a high voltage H-bridge, single chip
LRA haptic driver, with F0 detecting and tracking
based on BEMF, with a boost converter up to 11V
drive voltage inside, supporting real time
playback, memory playback, cont playback, one
wire and hardware pin trigged playback. A typical
startup time of 1ms makes the AW86927 an ideal
haptic driver for fast responses.
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AW86927 supports LRA fault diagnostic based on
resistance measurement and protections of shortcircuit, over-temperature and under-voltage.
AW86927 integrates a high-efficiency boost
converter as the H-Bridge driver supply rail. The
output voltage, maximum current limit and
maximum boost current are configurable.
AW86927 features configurable automatically
switch to standby mode after haptic waveform
playback finished. This can less quiescent power
consumption. The RSTN pin provides further
power saving by fully shut down the whole device.
Dedicated interrupt output pin can detect real time
FIFO status and the error status of the chip.
AW86927 features general settings are
communicated via an I2C-bus interface and its
I2C address is configurable.
AW86927 is available in a FCQFN 2mm x 3mm x
0.55mm -20L package.
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1
Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
PIN CONFIGURATION AND TOP MARK
AW86927FCR
(Top View)
AW86927FCR Marking
(Top View)
2
15 GND
TRIG2
3
14 VBAT
TRIG1
4
13 BGND
HDN
5
12 SW
PGND
6
11
VBST
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TRIG3
CA4F –AW86927FCR
XXXX - Production Tracing Code
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AD
PVDD
HDP
10 VCP
9
8
7
en
16 TEST
CA4F
XXXX
1
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VREG 17
SDA 18
SCL 19
INTN 20
RSTN
on
Figure 1 Pin Configuration and Top Mark
Pin Definition
NAME
I/O
1
RSTN
I
2
TRIG3
I
3
TRIG2
I
4
TRIG1
I
5
HDN
O
Active low hardware reset. High: standby/active mode, Low: power-down mode.
Internal have 2MΩ pull-down resistor.
Hardware trigger 3. Internal have 2MΩ pull-down resistor.
Hardware trigger 2. Internal have 2MΩ pull-down resistor.
Hardware trigger 1. Internal have 2MΩ pull-down resistor.
Negative haptic driver differential output. Internal have 3KΩ pull-down resistor
when standby/shutdown, high resistance when active.
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DESCRIPTION
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No.
PGND
Ground
HDP
O
PVDD
Power
AD
I
I2C bus address selection. Internal have 2MΩ pull-down resistor.
VCP
O
Internal charge pump voltage.
VBST
Power
SW
O
13
BGND
Ground
Boost GND.
14
VBAT
Power
Chip power supply.
15
GND
Ground
Supply ground.
16
TEST
IO
17
VREG
Power
18
SDA
IO
19
SCL
I
I2C bus clock input.
20
INTN
O
Interrupt open drain output, low active.
7
8
9
10
11
12
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H-bridge driver GND.
Positive haptic driver differential output. Internal have 3KΩ pull-down resistor
when standby/shutdown, high resistance when active.
High voltage driver power rail output.
Boost output voltage output.
Internal boost switch pin.
Test pin, default high resistance. Internal have 2MΩ pull-down resistor.
Digital power supply output.
I2C bus data input/output(open drain).
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Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Functional Block Diagram
VBAT
SW
VCP
Logic
CP
PVDD
SDA
SRAM
RSTN
main
control
INTN
HSRC
TRIG1
Trig
interface
LRA
HDN
RL_DET
TRIG3
TEST
OSC
F0
tracking
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Auto
brake
UVLO
LDO
VREG
GND BGND
OCP
PGND
FUNCTIONAL BLOCK DIAGRAM
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Figure 2
OTP
on
TRIG2
HDP
H-Bridge
Driver
DPWM
en
AD
VBST
BIAS
I2C
interface
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Boost Converter
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Wave
editor
SCL
Typical Application Circuits
L1
1μH
VBAT
C2
0.1μF
10V
17
14
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C1
0.1μF
10V
VIO
R3
4.7kΩ
VREG
4
3
2
GPIO
VBAT
SW
VCP
8
PVDD
C6
0603
10μF
25V
TEST
TRIG1
TRIG2
TRIG3
VIO
R1
4.7kΩ
C5
22nF
10 10V
12
RSTN
20
INTN
16
VIO
C4
0.1μF
10V
1
GPIO
GPIO
C3
0603
10μF
10V
VBST
11
AW86927
7
B1
C8
0.1nF
16V
HDP
R2
4.7kΩ
19 SCL
18 SDA
9 AD
SCL
SDA
HDN
GND
15
Figure 3
C7
0603
22μF
25V
BGND
13
LRA
5 B2
PGND
6
C9
0.1nF
16V
Typical Application Circuit of AW86927
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Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Notice for Typical Application Circuits:
1: Please place C1，C2，C3，C4，C5，C6，C7 as close to the chip as possible, and C6 and C7 close to PIN
11 and the capacitors should be placed in the same layer with the AW86927 chip.
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2: For the sake of driving capability, the power lines (especially the one to Pin 12), output lines, and the
connection lines of L1, and SW should be short and wide as possible. The power path marked in red as shown
in the figures above. The peak current of VBAT to SW through L1 is about 3.75~4.0A, and the other red path
traces according to 1.5A power line alignment rules.
Package
AW86927FCR
-40°C～85°C
FCQFN
2mmX3mmX0.55mm20L
Marking
Moisture
Sensitivity
Level
Environment
Information
MSL1
ROHS+HF
fid
Temperature
CA4F
Delivery
Form
6000 units/
Tape and
Reel
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Part Number
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Ordering Information
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Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Absolute Maximum Ratings(NOTE 1)
Parameter
Range
-0.3V to 6.0V
Digital power supply VREG
-0.3V to 2.0V
Internal charge pump voltage VCP
-0.3V to 17V
Boost output voltage VBST PVDD
-0.3V to 13V
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Battery Supply Voltage VBAT
-0.3V to 15V
Internal boost switch pin SW
-0.3V to PVDD+0.3V
TRIG1/TRIG2/TRIG3/SDA/SCL/AD/INTN
en
HDP, HDN
-0.3V to 6V
-0.3V to VBAT+0.3V
BCK
Ambient Temperature Range
on
Maximum Junction Temperature TJMAX
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Package Thermal Resistance θJA
60°C/W
-40°C to 85°C
150°C
Storage Temperature Range TSTG
-65°C to 150°C
Lead Temperature(Soldering 10 Seconds)
260°C
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ESD Rating (NOTE 2 3)
HBM(Human Body Model)
±2KV
CDM(Charge Device Model)
±1.5KV
Latch-up
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+IT: 200mA
-IT: -200mA
Test Condition: JEDEC EIA/JESD78E
NOTE 1: Conditions out of those ranges listed in "absolute maximum ratings" may cause permanent
damages to the device. In spite of the limits above, functional operation conditions of the device should
within the ranges listed in "recommended operating conditions". Exposure to absolute-maximum-rated
conditions for prolonged periods may affect device reliability.
NOTE 2：The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
Test method: ANSI/ESDA/JEDEC JS-001-2017.
NOTE 3：Charge Device Model test method: ANSI/ESDA/JEDEC JS-002-2018.
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Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Electrical Characteristics
Characteristics
Test condition: TA=25°C，VBAT=4.2V，PVDD=8V，RL=8Ω+100μH(unless otherwise noted)
Description
Test Conditions
Min
Battery supply voltage
VVREG
Voltage at VREG pin
VIL
Logic input low level
RSTN/TRIG1/TRIG2/TRIG3/
AD/SCL/SDA
VIH
Logic input high level
RSTN/TRIG1/TRIG2/TRIG3/
AD/SCL/SDA
VOL
Logic output low level
VOS
Output offset voltage
I2C signal input 0
ISD
Shutdown current
VBAT=4.2V, RSTN =0V
Standby current
VBAT=3.6V, AD= 0V
TRIG1=TRIG2=TRIG3=0V
3
Max
Units
5.5
V
INTN/SDA
fid
IOUT=4mA
en
1.5
V
0.5
1.3
-30
V
V
0.4
V
0
30
mV
0.1
1
μA
8
μA
5
mA
2.7
V
Under-voltage protection
hysteresis voltage
100
mV
Over temperature
protection threshold
160
°C
130
°C
on
ISTBY
On pin VBAT
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VVBAT
Typ.
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Symbol
RSTN=SCL=SDA=1.8V
IQ
Quiescent current
VBAT=3.6V@Bypass
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Under-voltage protection
voltage
UVP
TSDR
Ton1
Ton2
Boost
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TSD
Over temperature
protection recovery
threshold
Time from shutdown to
standby
Time from standby to
active
OVP
Over-voltage threshold
FBST
Operating Frequency
IL_PEAK
TST
From trigger to output signal
8
ms
1
ms
1.1*VPVDD
Inductor peak current limit
2
MHz
3.75
A
Soft-start time
No load, COUT=20μF
0.3
ms
Drain-Source on-state
resistance
Include H and L NMOS
300
mΩ
HDRIVER
RDSON
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Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Symbol
Description
ROCP
Load impedance
threshold for over current
protection
Min
Typ.
LRA Consistency
Calibration accuracy
F0-2
RL=16Ω+100μH
Output voltage
RL=8Ω+100μH
Output voltage
F0
Units
Ω
F0+2
10.5
Hz
V
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VBAT=4.2V, PVDD set 11V
VPEAK
Max
2
VBAT=3.6V, PVDD=8V
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FCALI_ACC_LRA
Test Conditions
8.5
V
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on
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en
VBAT=4.2V, PVDD set 11V
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Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
I2C Interface Timing
Parameter
fast mode
fast mode plus
UNIT
MIN
Name
TYP
MAX
MIN
TYP
MAX
No.
Symbol
1
fSCL
SCL Clock frequency
2
tLOW
SCL Low level Duration
1.3
3
tHIGH
SCL High level Duration
0.6
4
tRISE
SCL, SDA rise time
5
tFALL
SCL, SDA fall time
6
tSU:STA
Setup time SCL to START state
0.6
0.26
μs
7
tHD:STA
(Repeat-start) Start condition hold time
0.6
0.26
μs
8
tSU:STO
Stop condition setup time
0.6
0.26
μs
9
tBUF
1.3
0.5
μs
10
tSU:DAT
SDA setup time
0.1
0.1
μs
11
tHD:DAT
SDA hold time
10
10
ns
400
(2)
tLOW
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0.3
0.12
μs
0.3
0.12
μs
en
tFALL
(4)
(5)
tSU:DAT
tHD:DAT
(10)
(11)
μs
0.26
tRI SE
SDA
Figure 4 SCL and SDA timing relationships in the data transmission process
SCL
tHD:STA
tSU:STO
(7)
(8)
(6)
(9)
tSU:STA
tBUF
SDA
Figure 5 The timing relationship between START and STOP state
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8
kHz
μs
0.5
fid
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(3)
tHI GH
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SCL
on
the Bus idle time START state to STOP
state
1000
Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Measurement Setup
AW86927 features switching digital output, as shown in Figure 6. Need to connect a low pass filter to HDP/HDN
output respectively to filter out switch modulation frequency, then measure the differential output of filter to
obtain analog output signal.
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HDP
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0.47nF
100kΩ
3.4kHz
Low-Pass Fliter
LRA
AW86927
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HDN
100kΩ
fid
0.47nF
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Figure 6 AW86927 test setup
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Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Typical Characteristics
PVDD
Acceleration
Short_wave
Acceleration
Drive
Brake
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Long_wave
Figure 7 Long Vibration with Short Vibration insdie
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Figure 9 LRA with Automatic Braking
Trig
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Acceleration
Wave
on
Brake
wave
Figure 10 Automatic Resonance Tracking
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Figure 8 Trig Application
Acceleration
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Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Detailed Functional Description
Power On Reset
Operation Mode
The device supports 3 operation modes.
Table 1 Operating Mode
Power-Down
Condition
Description
VBAT = 0V or RSTN = 0V
Power supply is not ready or RSTN is tie to low.
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Mode
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The device provides a power-on reset feature that is controlled by VREG OK. The reset signal will be generated
to perform a power-on reset operation, which will reset all circuits and configuration registers. When the VBAT
power on, the VREG voltage raises and produce the OK indication, the reset is over.
Power supply is ready and RSTN is tie to high.
and RSTN = HIGH
Most parts of the device are power down for low power
and no wave is going
consumption except I2C interface and LDO.
Playing a waveform
Most parts of the device are working
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Active
VBAT > 2.7V
on
Standby
fid
Whole chip shutdown including I2C interface.
Power-down
Power supply not ready
(VBAT = 0) or RSTN = 0
Power supply not ready
(VBAT = 0) or RSTN = 0
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Power supply OK
(VBAT > 2.7V)
And RSTN = 1
Waveform is over
or set a softrstn
Standby
Active
Start a play request
Figure 11 Device operating modes transition
POWER-DOWN MODE
The device switches to power-down mode when the supply voltage is not ready or RSTN pin is set to low.
In this mode, all circuits inside this device will be shut down. I 2C interface isn’t accessible in this mode, and all
of the internal configurable registers and Memory are cleared.
The device will jump out of the power-down mode automatically when the supply voltages are OK and RSTN
pin is set to high.
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Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Standby Mode
The device switches standby mode when the power supply voltages are OK and RSTN pin set to high. In this
mode I2C interface is accessible, other modules except LDO module are still powered down. Also in this mode,
customer can initialize waveform library in SRAM. Device will be switched to this mode after haptic waveform
playback finished.
Active Mode
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The device is fully operational in this mode. Boost and H-bridge driver circuits will start to work. Users can
send a playback request to make device in this mode.
Power On And Power Down Sequence
100μs
en
This device power on and power down sequence is illustrated in the following figure:
ms
3-5.5V
100μs
fid
VBAT
100μs
on
RSTN
I2C
I2C configuration
Playback Sequence
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Figure 12 Power On and Power Down Sequence
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Make sure the device is not in POWER-DOWN MODE before sending a playback request, then the playback
sequence is illustrated in the following figure:
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Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Power on
Set EN_RAMINIT = 1
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Download waveform to
SRAM
en
Set EN_RAMINIT = 0
Global configuration
RAM mode config
Set GO=1
Set GO=1
on
CONT mode config
fid
Receive a Playback Request
RTP mode config
Send one wire
protocol
Set GO=1
Wait 1ms
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Send a trigger
One wire mode
config
CONT MODE
RAM MODE
Wait
GLB_STATE=4'b1000
Write data to RTP FIFO
TRIG MODE
ONE WIRE
MODE
RTP MODE
Figure 13 Power up and playback sequence
Software Reset
Writing 0xAA to register SOFTRST(0x00) via I2C interface will reset the device internal circuits except SRAM,
including configuration registers.
Battery Voltage Detect
Software can send command to detect the battery voltage.
Detect steps:
Set EN_RAMINIT to 1 in register 0x45;
Set DET_SEQ0 to 0 in register 0x4e;
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Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Set DET_GO to 1 in register 0x4d;
Wait 3ms;
Set DET_GO to 0 in register 0x4d;
Set EN_RAMINIT to 0 in register 0x45;
Read AVG_DATA_H in register 0x4f and AVG_DATA_L in register 0x50. Code= AVG_DATA_H*256+
AVG_DATA_L.
6.08 × 𝑐𝑜𝑑𝑒
(𝑉)
1024
Constant Vibration Strength
tia
𝑉𝐵𝐴𝑇 =
l
The code is a 10bit unsigned number.
en
The device features power-supply feedback. If the supply voltage discharge over time, the vibration strength
remains the same as long as enough supply voltage is available to sustain the required output voltage. It is
especially useful for ring application. Power-supply feedback works in all playback mode.
Set VBAT_REF in register 0x4d;
Set VBAT_MODE to 1 in register 0x4c;
Initiates a playback request.
on
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Use steps:
LRA Consistency Calibration
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Different motor batches, assembly conditions and other factors can result in f0 deviation of LRA. When the
drive waveform does not match the LRA monomer, the vibration may be inconsistent and the braking effect
becomes worse, especially for short vibration waveforms. So it's necessary to perform consistency calibration
of LRA. Firstly the power-on f0 detection can be launched to get the f0 of LRA. Secondly the waveform
frequency stored in SRAM and the f0 of LRA are used to calculate the code for calibration. The f0 accuracy
after LRA consistency calibration is ±2Hz.
LRA Resistance Detect
Software can send command to detect the LRA’s resistance.
Detect steps:
Set EN_RAMINIT to 1 in register 0x45;
Read D2S_GAIN register and save the result as d2s_gain_pre;
Set DET_SEQ0 to 3 and set D2S_GAIN with an appropriate value in register 0x4e;
Set DET_GO to 1 in register 0x4d;
Wait 3ms;
Set DET_GO to 0 in register 0x4d;
Set EN_RAMINIT to 0 in register 0x45;
Restore the value of D2S_GAIN register to d2s_gain_pre;
Read AVG_DATA_H in register 0x4f and AVG_DATA_L in register 0x50. Code= AVG_DATA_H*256+
AVG_DATA_L.
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Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Based on this code host can diagnosis used LRA’s status. The code is a 10bit unsigned number.
608 × 𝑐𝑜𝑑𝑒
(𝛺)
1024 × D2S_GAIN
The values of the D2S_GAIN that can be configured for different sizes of RL are listed below. The higher the
RL, the smaller the configurable D2S_GAIN.
𝑅𝐿 =
D2S_GAIN
2~30
20
31~60
10
en
Flexible Haptic Data Playback
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RL(Ω)
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Table 2 D2S_GAIN Selection
fid
The device offers multiple ways to playback haptic effects data. The PLAY_MODE bits select RAM mode, RTP
mode, CONT mode. Additional flexibility is provided by the three hardware TRIG pins, which can override
PLAY_MODE bit to playback haptic effects data as configuration.
The device contains 8kB of integrated SRAM to store customer haptic waveforms’ data. The whole SRAM is
separated to RAM waveform library and RTP FIFO region by base address. And RAM waveform library is
including waveform library version, waveform header and waveform data.
on
1FFF
cC
WAVFORM
DATA
WAV DATA
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WAVFORM
HEADER
BASE_ADDR
End address low
End address high
Start address low
Start address high
End address low
End address high
Start address low
Start address high
Waveform version
Action127
Action1
RTP FIFO
0
Figure 14 Data structure in SRAM
RAM mode and TRIG mode playback the waveforms in SRAM waveform library and RTP mode playback the
waveform data written in RTP FIFO, CONT mode playback non-filtered or filtered square wave with rated drive
voltage.
Sram Structure
A SRAM waveform library consists of a waveform version byte, a waveform header section, and the waveform
data content. The waveform header defines the data boundaries for each waveform ID in the data field, and
the waveform data contains a signed data format (2's complement) to specify the magnitude of the drive.
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Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
1FFF
address
...
4 * （#N – 1） + 4 + len(#1) + len(#2)
...
4 * （#N – 1） + 5 + len(#1)
4 * （#N – 1） + 4 + len(#1)
#N
4 * （#N – 1） + 5
4 * （#N – 1） + 4
4 * （#N – 1） + 3
4 * （#N – 1） + 2
4 * （#N – 1） + 1
4
4
4
4
* （#2
* （#2
* （#2
* （#2
– 1） + 4
– 1） + 3
– 1） + 2
– 1） + 1
4
4
4
4
base_addr 0
* （#1
* （#1
* （#1
* （#1
– 1） + 4
– 1） + 3
– 1） + 2
– 1） + 1
#2
en
Waveform#2 end address low
Waveform#2 end address high
Waveform#2 start address low
Waveform#2 start address high
Waveform#1 end address low
Waveform#1 end address high
Waveform#1 start address low
Waveform#1 start address high
Waveform library version
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Waveform#N end address low
Waveform#N end address high
Waveform#N start address low
Waveform#N start address high
#1
fid
WAVEFORM SRAM
Figure 15 Waveform library data structure
Waveform version:
on
One byte located on SRAM base address, setting to different value to identify different version of RAM
waveform library.
Waveform header:
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The waveform header block consist of N-boundary definition blocks of 4 bytes each. N is the number of
waveforms stored in the SRAM (N cannot exceed 127). Each of the boundary definition blocks contain the
start address (2 bytes) and end address (2 bytes). So the total length of waveform header block are N*4 bytes.
The start address contains the location in the memory where the waveform data associated with this waveform
begins.
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The end address contains the location in the memory where the waveform data associated with this waveform
ends.
The waveform ID is determined after base address is defined. Four bytes begins with the address next to base
address are the first waveform ID’s header, and next four bytes are the second waveform ID’s header, and so
on.
Waveform data:
The waveform data contains a signed data format (2's complement) to specify the magnitude of the drive. The
begin address and end address is specified in waveform ID’s header.
Waveform library initialization steps:
Prepare waveform library data including: waveform library version, waveform header fields for waveform
in library and waveform data of each waveform;
Set register EN_RAMINIT=1 in register 0x45, open clock to enable SRAM initial;
Set base address (register 0x2D, 0x2E);
Write waveform library data into register 0x42 continually until all the waveform library data written;
Set register EN_RAMINIT=0, close clock to disable SRAM initial.
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September 2021 V1.2
Ram Mode
To playback haptic data with RAM mode, the waveform ID must first be configured into the waveform playback
queue and then the waveform can be played by writing GO bit register.
PLAYBACK QUEUE
Waveform library
GO
Waveform 1
WAVSEQ2
Waveform 2
WAVSEQ3
Waveform 3
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WAVSEQ1
..
.
WAVSEQ4
en
WAVSEQ5
Waveform N
WAVSEQ6
WAVSEQ7
fid
WAVSEQ8
Figure 16 RAM mode playback
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The waveform playback queue defines waveform IDs in waveform library for playback. Eight WAVSEQx
registers queue up to eight library waveforms for sequential playback. A waveform ID is an integer value
referring to the index of a waveform in the waveform library. Playback begins at WAVSEQ1 when the user
triggers the waveform playback queue. When playback of that waveform ends, the waveform queue plays the
next waveform ID held in WAVSEQ2 (if non-zero). The waveform queue continues in this way until the queue
reaches an ID value of zero or until all eight IDs are played whichever comes first.
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The waveform ID is a 7-bit number. The MSB of each ID register can be used to implement a delay between
queue waveforms. When the SEQxWAIT is high, bits 6-0 indicate the length of the wait time. The wait time for
that step then becomes WAVSEQ[6:0] × wait_time unit. Wait_time unit can be configuration of WAITSLOT
register(in 0x16 register).
The device allows for looping of individual waveforms by using the SEQxLOOP registers. When used, the state
machine will loop the particular waveform the number of times specified in the associated SEQxLOOP register
before moving to the next waveform. The device allows for looping of the entire playback sequence by using
the MAIN_LOOP register. The waveform-looping feature is useful for long, custom haptic playbacks, such as
a haptic ringtone.
Playback steps:
Waveform library must be initialized before playback;
Set PLAY_MODE bits to 0 in register 0x08;
Set playback queue registers (0x0A ~ 0x11) as desired;
Set playback loop registers (0x12~ 0x16) as desired;
Set GO bit to 1 in register 0x09 to trigger waveform playback;
Device will be switched to STANDBY mode after haptic waveform playback finished.
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September 2021 V1.2
Rtp Mode
The real-time playback mode is a simple, single 8-bit register interface that holds an amplitude value. When
real-time playback is enabled, begin to enters a register value to RTP_DATA over the I 2C will trigger the
playback, the value is played until the data sending finished or removes the device from RTP mode. The
maximum FIFO space is 4Kbyte.
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After FF_AEM or FF_AFM register is set to 0, HOST can obtain the RTP FIFO almost empty or almost full
status through interrupt signal(pin INTN) or read FF_AES or FF_AFS register. RTP FIFO almost empty and
almost full threshold can be configured through FIFO_AE and FIFO_AF registers.
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FIFO last address
Almost full level
en
FIFO
FIFO write address
Almost empty threshold
FIFO read address
...
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...
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0
FIFO NOT empty and
chip startup
FIFO empty
Playback steps:
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Figure 17 RTP mode playback
Prepare RTP data before playback;
Set PLAY_MODE bit to 1 in register 0x08;
Set GO bit to 1 in register 0x09 to trigger waveform playback;
Delay 1ms.
Check GLB_STATE=4’b1000，if HOST don’t send data to FIFO, chip will wait for RTP data coming in this
state forever;
Write RTP data continually to register 0x32 to playback RTP waveform;
HOST need monitor the almost full and almost empty status for RTP FIFO;
Device will be switched to STANDBY mode after wave data in RTP FIFO is played empty.
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Trig Mode
The device have three dedicated hardware pins for quickly trigger haptic data playback. Each pin can be
configured posedge/negedge/both-edge/level trigger.
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September 2021 V1.2
Waveform library
TRIG config
TRIGGER
TRG1_LEV=0
TRIG1_POSEDGE
Waveform 5
TRIG1_NEGEDGE
Waveform 1
Waveform 1
Wavef orm 2
Waveform 3
TRG2_LEV=0
Waveform 2
TRIG2_NEGEDGE
Waveform 3
TRIG3_POSEDGE
Waveform 6
TRIG3_NEGEDGE
Waveform 4
Waveform 4
.
.
.
TRIG3_LEV=1
TRG3_POLAR=0
Waveform 5
Waveform 6
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TRIG3_LEV=1
TRG3_POLAR=1
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TRIG2_POSEDGE
Figure 18 TRIG mode playback
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Edge mode or level mode is accessible by configing register TRGx_LEV. When a edge mode is needed, user
should set TRGx_LEV =0. In edge mode, register TRGxSEQ_P and TRGx_POS respestively represent the
waveform and enable signal of positive edge, where register TRGxSEQ_N and TRGx_NEG respestively
represent the waveform and enable signal of negative edge.
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When a level mode is needed, user should set TRGx_LEV =1, and positive level and negative level can be
supported by setting register TRGX_POLAR=0 and setting TRGX_POLAR=1.
Table 3 TRIG MODE CONFIG
I2C reg
TRGx_POLAR TRGx_POS
1
0
1
0
1
0
1
X
X
Waveform
0
0
1
1
↑
↓
↑/↓
none
TRGxSEQ_P
TRGxSEQ_N
TRGxSEQ_P/ TRGxSEQ_N
X
X
High level
Low level
TRGxSEQ_P
TRGxSEQ_N
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0
X
X
X
X
Trigger
TRGx_NEG
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TRGx_LVL
Playback steps:
Waveform library must be initialized before playback;
Set trigger playback registers (0x33 ~ 0x3A) as desired;
Send trigger pulse (≥1μs) on TRIG pins to playback waveform;
Device will be switched to STANDBY mode after haptic waveform playback finished.
One wire Mode
The function of one wire mode mainly transfer two information : sequence number and gain of waveform，
TRIG1 is the interface pin.
Playback steps:
Waveform library must be initialized before playback;
Set TRG_ONEWIRE to 1 in register 0x3A to enable one wire mode;
Determine sequence number and gain of waveform which you want to playback;
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Combine sequence number and gain data into a 15 bit transformation data（low 8 bit is gain, high 7 bit is
sequence number）
，the data is sent from the lowest bit;
Chip will automatically enter standby mode after playing. The interval time between two sending protocol
data should be greater than “3ms+time length of waveform”.
us
10~20us
ms
IDLE
Start
...
45~55us
Bit 14
Bit 1
Bit 0
Figure 19 One wire mode playback
Cont Mode
IDLE
ms
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us
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The CONT mode mainly performs two functions: F0 detection and real-time resonance-frequency tracking.
F0 detection can be launched by setting EN_F0_DET=1 and BRK_EN =1. When set TRACK_EN=1, real-time
resonance-frequency tracking will be launched by tracking the BEMF of actuator constantly. It provides
stronger and more consistent vibrations and lower power consumption. If the resonant frequency shifts for any
reason, the function tracks the frequency from cycle to cycle. When TRACK_EN is set to 0, the width of
waveform of cont mode is determined by DRV_WIDTH in register 0x1A.
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When the EDGE_FRE register is set to 4’b1xxx, the CONT mode outputs a filtered square wave. The edge of
filtered square wave is composed of SIN or COS wave whose frequency can be configured by EDGE_FRE
register. When SIN_MODE register is set to 1, filtered square wave is composed of COS wave.
Playback steps:
Set PLAY_MODE = 2 in register 0x08 to enable CONT mode;
(optional)Set EN_F0_DET = 1 and BRK_EN =1 to enable F0 detection;
Set cont mode by configuring registers(0x18~0x20 and 0x22);
Set GO bit to 1 in register 0x09 to trigger waveform playback;
Device will be switched to STANDBY mode after haptic waveform playback finished;
If enable F0 detection, get F0 information from registers(0x25~0x28) after GLB_STATE=0.
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Tracking
DRV1_LVL
1
3
2
4
DRV2_LVL
1
2
DRV1_TIME = 4
3
4
5
DRV2_TIME = 5
Figure 20 Cont mode playback
Auto Brake Engine
An auto-brake engine is integrated into this device. Users can adjust the brake strength by setting D2S_GAIN
in register 0x4e. The greater D2S_GAIN, the greater brake strength and the worse loop stability. Auto-brake
engine is disabled when setting BRK_EN=0 or BRK_TIME=0.
To enable Auto-brake engine, there are some points to note:
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September 2021 V1.2
TRGx_BRK in register 0x39, 0x3A should be set to 1 when in TRIG mode;
Auto-brake engine will not work when BRK_EN=0 in register 0x08；
Auto-brake engine will not work when EN_F0_DET in register 0x18 is set to 1;
Auto-brake engine will not work when BRK_TIME in register 0x21 is set to 0;
Device will be switched to STANDBY mode after haptic waveform playback finished.
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DRV_WIDTH
PLAY WAVE
BRAKE WAVE
Motor
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BRAKE ENGINE
SENSOR
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D2S_GAIN
Figure 21 Brake loop
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DC-DC Converter
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The device integrated peak current mode synchronous PWM Boost as H-bridge power stage supply,
significantly increase the output voltage dynamic range. Reduces the size of external components and saves
PCB space by using about 2 MHz switching frequency. Boost output voltage can be set through the I2C register
0x06;
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The device synchronous Boost with soft-start function to prevent overshoot current at powering-on; integrated
the output protection circuit and self-recovery function; integrated Anti-Ring circuit to reduce EMI in DCM mode;
built-in substrate switching shutdown circuit, effectively preventing the input and output leakage current antiirrigation.
Protection Mechanisms
Over Voltage Protection (OVP)
The boost circuit has integrated the over voltage protection control loop. When the output voltage PVDD is
above the threshold, the boost circuits will stop working, until the voltage of PVDD going down and under the
normal fixed working voltage.
Over Temperature Protection (OTP)
The device has automatic temperature protection mechanism which prevents heat damage to the chip. It is
triggered when the junction temperature is larger than the preset temperature high threshold (default = 160°C).
When it happens, the output stages will be disabled. When the junction temperature drops below the preset
temperature low threshold (less than 130°C), the output stages will start to operate normally again
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Over Current (Short) Protection (OCP)
The short circuit protection function is triggered when HDP/HDN is short too PVDD/GND or HDP is short to
HDN, the output stages will be shut down to prevent damage to itself. When the fault condition is disappeared,
the output stages of device will restart.
Vbat Under Voltage Lock Out Protection (UVLO)
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The device has a battery monitor that monitors the VBAT level to ensure that is above threshold 2.7V, In the
event of a VBAT drop, the device immediately power down the Boost and H-bridge driver and latches the
UVLO flag.
Drive Data Error Protection (DDEP)
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When haptic data sent to drive LRA is error such as: a DC data or almost DC data, it will cause the LRA heat
to brake. The device configurable immediately power down the Boost and H-bridge driver and latched the
DDEP flag.
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I2C Interface
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This device supports the I²C serial bus and data transmission protocol in fast mode at 400kHz and fast mode
plus at 1000kHz. This device operates as a slave on the I²C bus. Connections to the bus are made via the
open-drain I/O pin SDA and I pin SCL. The pull-up resistor can be selected in the range of 1k~10kΩ and the
typical value is 4.7kΩ. This device can support different high level (1.8V~3.3V) of this I2C interface.
Device Address
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The I2C device address (7-bit) can be set using the AD pin according to the following table:
Table 4 Address Selection
I2C address (7-bit)
0
0x5A
1
0x5B
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AD
Data Validation
When SCL is high level, SDA level must be constant. SDA can be changed only when SCL is low level.
SDA
SCL
Data Line
Stable
Data Valid
Change
of Data
Allowed
Figure 22 Data Validation Diagram
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General I2C Operation
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The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in
a system. The device is addressed by a unique 7-bit address; the same device can send and receive data. In
addition, Communications equipment has distinguish master from slave device: In the communication process,
only the master device can initiate a transfer and terminate data and generate a corresponding clock signal.
The devices using the address access during transmission can be seen as a slave device.
SDA and SCL connect to the power supply through the current source or pull-up resistor. SDA and SCL default
is a high level. There is no limit on the number of bytes that can be transmitted between start and stop
conditions. When the last word transfers, the master generates a stop condition to release the bus.
START state: The SCL maintain a high level, SDA from high to low level
STOP state: The SCL maintain a high level, SDA pulled low to high level
Start and Stop states can be only generated by the master device. In addition, if the device does not produce
STOP state after the data transmission is completed, instead re-generate a START state (Repeated START,
Sr), and it is believed that this bus is still in the process of data transmission. Functionally, Sr state and START
state is the same. As shown in Figure 23.
SCL
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START
(S)
SDA
STOP
(P)
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Figure 23 START and STOP state generation process
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In the data transmission process, when the clock line SCL maintains a high level, the data line SDA must
remain the same. Only when the SCL maintain a low level, the data line SDA can be changed, as shown in
Figure 24. Each transmission of information on the SDA is 9 bits as a unit. The first eight bits are the data to
be transmitted, and the first one is the most significant bit (Most Significant Bit, MSB), the ninth bit is an
confirmation bit (Acknowledge, ACK or A ), as shown in Figure 25. When the SDA transmits a low level in ninth
clock pulse, it means the acknowledgment bit is 1, namely the current transmission of 8 bits data are confirmed,
otherwise it means that the data transmission has not been confirmed. Any amount of data can be transferred
between START and STOP state.
SCL
SDA
Data cable
Remains the same:
At this point the
data is valid
Data transmission:
In this case the data
is invalid
Figure 24 The data transfer rules on the I2C bus
The whole process of actual data transmission is shown in Figure 25. When generating a START condition,
the master device sends an 8-bit data, including a 7-bit slave addresses (Slave Address), and followed by a
"read / write" flag ( R/ W ). The flag is used to specify the direction of transmission of subsequent data. The
master device will produce the STOP state to end the process after the data transmission is completed.
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However, if the master device intends to continue data transmission, you can directly send a Repeated
START state, without the need to use the STOP state to end transmission.
SCL
START or
repeated
START
(S or Sr)
1
2
8
9
1
R/W
ACK
MSB
2
8
9
STOP or
Repeated
START
(P or Sr)
SDA
ACK
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MSB
Figure 25 Data transmission on the I2C bus
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Write Process
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Writing process refers to the master device write data into the slave device. In this process, the transfer
direction of the data is always unchanged from the master device to the slave device. All acknowledge bits are
transferred by the slave device, in particular, the device as the slave device, the transmission process in
accordance with the following steps, as shown in Figure 26:
Master device generates START state. The START state is produced by pulling the data line SDA to a low
level when the clock SCL signal is a high level.
Master device transmits the 7-bits device address of the slave device, followed by the "read / write" flag (flag
= 0);
The slave device asserts an acknowledgment bit (ACK) to confirm whether the device address is correct;
The master device transmits the 8-bit register address to which the first data byte will written；
The slave device asserts an acknowledgment (ACK) bit to confirm the register address is correct;
Master sends 8 bits of data to register which needs to be written;
The slave device asserts an acknowledgment bit (ACK) to confirm whether the data is sent successfully;
If the master device needs to continue transmitting data by sending another pair of data bytes, just need to
repeat the sequence from step 6. In the latter case, the targeted register address will have been autoincremented by the device.
The master device generates the STOP state to end the data transmission.
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R/ W
(1)
START
(2)
slave device address
R/W
(3)
(4)
A
Register address
‘0’(write)
data
transmission
direction
From the master to the slave device
(5)
(6)
(7)
(6r)
(7r)
A write data A write data A
(9)
STOP
Data Transmission: 8 + 1 bit data acknowledge bit (ACK)
Register address auto increment - (8)
From slave to master device
Figure 26 Writing process (data transmission direction remains the same)
Read Process
Reading process refers to the slave device reading data back to the master device. In this process, the direction
of data transmission will change. Before and after the change, the master device sends START state and slave
address twice, and sends the opposite "read/write" flag. In particular, AW86927 as the slave device, the
transmission process carried out by following steps listed in Figure 27:
Master device asserts a start condition;
Master device transmits the 7 bits address of the device, and followed by a "read / write" flag ( R/ W = 0);
The slave device asserts an acknowledgment bit (ACK) to confirm whether the device address is correct;
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The master device transmits the register address to make sure where the first data byte will read;
The slave device asserts an acknowledgment (ACK) bit to confirm whether the register address is correct or
not;
The master device restarts the data transfer process by continuously generating STOP state and START state
or a separate Repeated START;
(2)
(3)
(4)
(5)
(6)
START
slave device address R/W
A
Register address
A
Sr
(7)
slave device address
‘0’(write)
(9)
(10)
(9r)
(10r)
R/W
A Read data A Read data A
(12)
STOP
‘1’(read) Data Transmission: 8 + 1 bit data acknowledge bit (ACK)
Sr = repeated START
or Send STOP state before sending START state
From the master to the slave device
From slave to master device
Register address auto increment - (11)
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data
transmission
direction
(8)
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(1)
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Master sends 7-bits address of the slave device and followed by a read / write flag (flag R/ W = 1) again;
The slave device asserts an acknowledgment (ACK) bit to confirm whether the register address is correct or
not;
Master transmits 8 bits of data to register which needs to be read;
The slave device sends an acknowledgment bit (ACK) to confirm whether the data is sent successfully;
The device automatically increment register address once after sent each acknowledge bit (ACK),
The master device generates the STOP state to end the data transmission.
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Figure 27 Reading process (data transmission direction remains the same)
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Register Configuration
Register List
ADDR
NAME
R/W
0x00
RSTCFG
WO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x01
SYSST
RO
UVLS
FF_AES
FF_AFS
OCDS
OTS
DONES
0x02
SYSINT
RC
UVLI
FF_AEI
FF_AFI
OCDI
OTI
DONEI
0x03
SYSINTM
RW
0x10
UVLM
FF_AEM
FF_AFM
OCDM
OTM
DONEM
0xFF
0x06
PLAYCFG1
RW
0x07
PLAYCFG2
RW
0x08
PLAYCFG3
RW
0x09
PLAYCFG4
RW
0x0A
WAVCFG1
RW
SEQ1WAIT
WAVSEQ1
0x0B
WAVCFG2
RW
SEQ2WAIT
WAVSEQ2
0x0C
WAVCFG3
RW
SEQ3WAIT
0x0D
WAVCFG4
RW
SEQ4WAIT
0x0E
WAVCFG5
RW
SEQ5WAIT
0x0F
WAVCFG6
RW
SEQ6WAIT
0x10
WAVCFG7
RW
SEQ7WAIT
0x11
WAVCFG8
RW
SEQ8WAIT
0x12
WAVCFG9
RW
SEQ1LOOP
0x13
WAVCFG10
RW
SEQ3LOOP
0x14
WAVCFG11
RW
SEQ5LOOP
0x15
WAVCFG12
RW
SEQ7LOOP
0x16
WAVCFG13
RW
0x18
CONTCFG1
RW
SOFTRST
0x00
STOP_MODE
BRK_EN
0x80
PLAY_MODE
STOP
0x14
GO
0x00
0x00
WAVSEQ4
0x00
WAVSEQ5
0x00
WAVSEQ6
0x00
WAVSEQ7
0x00
fid
WAVSEQ3
0x00
on
WAVSEQ8
WAITSLOT
EN_F0_DET
0x00
0x01
en
AUTO_BST
0x10
0x58
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BST_VOUT_VREFSET
GAIN
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BST_MODE
Default
SIN_MODE
SEQ2LOOP
0x00
SEQ4LOOP
0x00
SEQ6LOOP
0x00
SEQ8LOOP
0x00
MAINLOOP
0x00
EDGE_FRE
0x1E
0x19
CONTCFG2
RW
0x1A
CONTCFG3
RW
F_PRE
0x8D
0x1C
CONTCFG5
RW
0x1D
CONTCFG6
RW
0x1E
CONTCFG7
RW
0x1F
CONTCFG8
RW
0x20
CONTCFG9
RW
0x21
CONTCFG10
RW
0x22
CONTCFG11
RW
0x25
CONTRD14
0x26
CONTRD15
0x27
CONTRD16
0x28
CONTRD17
0x2D
RTPCFG1
0x2E
RTPCFG2
0x2F
RTPCFG3
0x30
RTPCFG4
0x31
RTPCFG5
0x32
RTPDATA
0x33
TRGCFG1
RW
TRG1_POS
TRG1SEQ_P
0x01
0x34
TRGCFG2
RW
TRG2_POS
TRG2SEQ_P
0x01
0x35
TRGCFG3
RW
TRG3_POS
TRG3SEQ_P
0x01
0x36
TRGCFG4
RW
TRG1_NEG
TRG1SEQ_N
0x01
0x37
TRGCFG5
RW
TRG2_NEG
TRG2SEQ_N
0x01
0x38
TRGCFG6
RW
TRG3_NEG
TRG3SEQ_N
0x39
TRGCFG7
RW
TRG1_POLAR
TRG1_LEV
TRG1_BRK
TRG1_BST
TRG2_POLAR
TRG2_LEV
TRG2_BRK
TRG2_BST
0x3A
TRGCFG8
RW
TRG3_POLAR
TRG3_LEV
TRG3_BRK
TRG3_BST
TRG_ONEWIRE
TRG1_STOP
TRG2_STOP
TRG3_STOP
0x3E
GLBCFG4
RW
DRV_WIDTH
0x6A
TRACK_EN
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BST_BRK_GAIN
BRK_GAIN
0x58
DRV1_LVL
0xFF
DRV2_LVL
0x50
DRV1_TIME
0x04
DRV2_TIME
0x06
0x08
TRACK_MARGIN
0x0C
RO
F_LRA_F0_H
0x00
RO
F_LRA_F0_L
0x00
RO
CONT_F0_H
0x00
RO
CONT_F0_L
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BRK_TIME
0x00
RW
BASE_ADDR_H
RW
RW
0x08
BASE_ADDR_L
0x00
FIFO_AEH
FIFO_AFH
0x26
RW
FIFO_AEL
0x00
RW
FIFO_AFL
0x00
RW
RTP_DATA
0x00
0x3F
GLBRD5
RO
0x40
RAMADDRH
RW
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GO_PRIO
TRG3_PRIO
0x01
TRG2_PRIO
TRG1_PRIO
GLB_STATE
RAMADDRH
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Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
0x33
0x30
0x1B
0x00
0x00
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September 2021 V1.2
0x41
RAMADDRL
RW
RAMADDRL
0x42
RAMDATA
RW
RAMDATA
0x00
0x45
SYSCTRL3
RW
0x46
SYSCTRL4
RW
0x48
PWMCFG1
RW
PRC_EN
PRCTIME
0x00
0x4A
PWMCFG3
RW
PR_EN
PRLVL
0xBF
0x00
EN_RAMINIT
EN_FIR
0x12
WAVDAT_MODE
GAIN_BYPASS
0x4B
PWMCFG4
RW
0x4C
VBAT_CTRL
RW
0x4D
DETCFG1
RW
0x4E
DETCFG2
RW
0x4F
DET_RD1
RO
0x50
DET_RD2
RO
AVG_DATA_L
0x51
DET_RD3
RO
ADC_DATA_L
0x57
IDH
RO
CHIPID_H
0x58
IDL
RO
CHIPID_L
0x08
PRTIME
0x32
VBAT_MODE
0x00
VBAT_REF
ADC_FS
0x24
D2S_GAIN
0x04
AVG_DATA_H
0x00
0x00
tia
ADC_DATA_H
l
DET_SEQ0
DET_GO
0x00
0x92
en
0x70
Register Detailed Description
fid
Note: Reserved register should not be written
RSTCFG: (Address 00h)
Bit
Symbol
7:0
SOFTRST
R/W
WO
SYSST: (Address 01h)
Bit
Symbol
7:6
Reserved
R/W
RO
Not used
on
Description
All configuration registers will be reset to default value after 0xaa is written
Description
Default
0x00
Default
0
UVLS
RO
1: VBAT voltage is under UV voltage (2.7V)
0
4
3
2
1
0
FF_AES
FF_AFS
OCDS
OTS
DONES
RO
RO
RO
RO
RO
1: RTP FIFO is almost empty
1: RTP FIFO is almost full
1: Over Current status
1: Over Temperature status
1: The indication of playback finished
1
0
0
0
0
(Address 02h)
Symbol
Reserved
UVLI
FF_AEI
FF_AFI
OCDI
OTI
DONEI
R/W
RC
RC
RC
RC
RC
RC
RC
aw
ini
SYSINT:
Bit
7:6
5
4
3
2
1
0
SYSINTM: (Address 03h)
Bit
Symbol
7:6
cC
5
RW
5
UVLM
RW
4
FF_AEM
RW
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Not used
When UVLI=1, it means UVLS has been 1 at least once since the last read
When FF_AEI=1, it means FF_AES has been 1 at least once since the last read
When FF_AFI=1, it means FF_AFS has been 1 at least once since the last read
When OCDI=1, it means OCDS has been 1 at least once since the last read
When OTI=1, it means OTS has been 1 at least once since the last read
When DONEI=1, it means DONES has been 1 at least once since the last read
R/W
Reserved
Description
Description
Default
0
0
1
0
0
0
0
Default
Not used
Interrupt mask for UVLI:
0: INTN pin will be pulled down when UVLI=1
1: INTN pin will not be pulled down when UVLI=1
Interrupt mask for FF_AEI:
0: INTN pin will be pulled down when FF_AEI=1
1: INTN pin will not be pulled down when FF_AEI=1
27
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1
1
AW86927
September 2021 V1.2
RW
2
OCDM
RW
1
OTM
RW
0
DONEM
RW
BST_VOUT_VREFSE
T
PLAYCFG2: (Address 07h)
Bit
Symbol
7:0
GAIN
R/W
RW
RW
3
STOP_MODE
RW
2
BRK_EN
RW
1:0
PLAY_MODE
PLAYCFG4: (Address 09h)
Bit
Symbol
7:2
Reserved
1
STOP
0
GO
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1
Description
Gain setting for waveform data, GAIN=code/128
GAIN_BYPASS=1, GAIN for RAM/RTP/TRIG MODE, and can be changed when
playing
GAIN_BYPASS=0, GIAN for RAM MODE waveform data, and can not be changed
when playing
Description
Not used
1: disable Boost when data is 0 in RTP and RAM mode
0: stop when current wave is over
1: stop right now
When set 1, enable auto brake after RTP/RAM/CONT playback mode is stopped
RW
Waveform play mode for GO trig
b00: RAM mode
b01: RTP mode
b10: CONT mode
b11: no play
R/W
RW
RW
Description
Not used
When set 1, stop the current playback mode
RW
RAM/RTP/CONT mode playback trig bit
when set to 1, chip will playback one of the play mode.
28
Default
0
en
RW
PVDD voltage setup: ΔV=62.5mV, default=9V
VBAT should be smaller than 0.8*PVDD and PVDD > 6V
b0000000~b0100111: code can not be configured
b0101000: 6V (3.5V+ΔV*40)
b0101001: 3.5V+ΔV*41
b0101010: 3.5V+ΔV*42
......
b1111111: 11.4375V (3.5V+ΔV*127)
aw
ini
PLAYCFG3: (Address 08h)
Bit
Symbol
7:5
Reserved
4
AUTO_BST
RW
RW
1
Description
BOOST mode
0: Bypass mode
1: Boost mode
R/W
1
fid
6:0
BST_MODE
1
on
7
R/W
cC
PLAYCFG1: (Address 06h)
Bit
Symbol
Interrupt mask for FF_AFI:
0: INTN pin will be pulled down when FF_AFI=1
1: INTN pin will not be pulled down when FF_AFI=1
Interrupt mask for OCDI:
0: INTN pin will be pulled down when OCDI=1
1: INTN pin will not be pulled down when OCDI=1
Interrupt mask for OTI:
0: INTN pin will be pulled down when OTI=1
1: INTN pin will not be pulled down when OTI=1
Interrupt mask for DONEI:
0: INTN pin will be pulled down when DONEI=1
1: INTN pin will not be pulled down when DONEI=1
l
FF_AFM
tia
3
0x58
Default
0x80
Default
0
1
0
1
0
Default
0
0
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0
AW86927
September 2021 V1.2
R/W
RW
RW
Description
When set to 1 , WAVSEQ1 means wait time, else means wave sequence number
Wait time (code*WAITSLOT) or wave sequence number
Default
0
1
WAVCFG2: (Address 0Bh)
Bit
Symbol
7
SEQ2WAIT
6:0
WAVSEQ2
R/W
RW
RW
Description
When set to 1 , WAVSEQ2 means wait time, else means wave sequence number
Wait time (code*WAITSLOT) or wave sequence number
Default
0
0
WAVCFG3: (Address 0Ch)
Bit
Symbol
7
SEQ3WAIT
6:0
WAVSEQ3
R/W
RW
RW
Description
When set to 1 , WAVSEQ3 means wait time, else means wave sequence number
Wait time (code*WAITSLOT) or wave sequence number
WAVCFG4: (Address 0Dh)
Bit
Symbol
7
SEQ4WAIT
6:0
WAVSEQ4
R/W
RW
RW
Description
When set to 1 , WAVSEQ4 means wait time, else means wave sequence number
Wait time (code*WAITSLOT) or wave sequence number
Default
0
0
WAVCFG5: (Address 0Eh)
Bit
Symbol
7
SEQ5WAIT
6:0
WAVSEQ5
R/W
RW
RW
Description
when set to 1 , WAVSEQ5 means wait time, else means wave sequence number
Wait time (code*WAITSLOT) or wave sequence number
Default
0
0
WAVCFG6: (Address 0Fh)
Bit
Symbol
7
SEQ6WAIT
6:0
WAVSEQ6
R/W
RW
RW
Description
When set to 1 , WAVSEQ6 means wait time, else means wave sequence number
Wait time (code*WAITSLOT) or wave sequence number
Default
0
0
WAVCFG7: (Address 10h)
Bit
Symbol
7
SEQ7WAIT
6:0
WAVSEQ7
R/W
RW
RW
Description
when set to 1 , WAVSEQ7 means wait time, else means wave sequence number
Wait time (code*WAITSLOT) or wave sequence number
Default
0
0
WAVCFG8: (Address 11h)
Bit
Symbol
7
SEQ8WAIT
6:0
WAVSEQ8
R/W
RW
RW
Description
When set to 1 , WAVSEQ8 means wait time, else means wave sequence number
Wait time (code*WAITSLOT) or wave sequence number
Default
0
0
WAVCFG9: (Address 12h)
Bit
Symbol
R/W
aw
ini
cC
on
fid
en
tia
l
WAVCFG1: (Address 0Ah)
Bit
Symbol
7
SEQ1WAIT
6:0
WAVSEQ1
Description
7:4
SEQ1LOOP
RW
Control the loop number of the first sequence
b0000~b1110: play (code+1) time
b1111: playback infinitely until STOP set to 1 or SEQ1LOOP ≠0xF
3:0
SEQ2LOOP
RW
Control the loop number of the second sequence
b0000~b1110: play (code+1) time
b1111: playback infinitely until STOP set to 1 or SEQ2LOOP ≠0xF
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29
Default
0
0
Default
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0
AW86927
September 2021 V1.2
WAVCFG10: (Address 13h)
Bit
Symbol
R/W
Description
Default
SEQ3LOOP
RW
Control the loop number of the third sequence
b0000~b1110: play (code+1) time
b1111: playback infinitely until STOP set to 1 or SEQ3LOOP ≠0xF
0
3:0
SEQ4LOOP
RW
Control the loop number of the fourth sequence
b0000~b1110: play (code+1) time
b1111: playback infinitely until STOP set to 1 or SEQ4LOOP ≠0xF
0
WAVCFG11: (Address 14h)
Bit
Symbol
R/W
tia
Description
l
7:4
Default
SEQ5LOOP
RW
Control the loop number of the fifth sequence
b0000~b1110: play (code+1) time
b1111: playback infinitely until STOP set to 1 or SEQ5LOOP ≠0xF
0
3:0
SEQ6LOOP
RW
Control the loop number of the sixth sequence
b0000~b1110: play (code+1) time
b1111: playback infinitely until STOP set to 1 or SEQ6LOOP ≠0xF
0
WAVCFG12: (Address 15h)
Bit
Symbol
R/W
fid
en
7:4
Description
SEQ7LOOP
RW
3:0
SEQ8LOOP
RW
Control the loop number of the eighth sequence
b0000~b1110: play (code+1) time
b1111: playback infinitely until STOP set to 1 or SEQ8LOOP ≠0xF
WAVCFG13: (Address 16h)
Bit
Symbol
7:6
Reserved
R/W
RW
RW
3:0
MAINLOOP
RW
CONTCFG1: (Address 18h)
Bit
Symbol
7:6
Reserved
R/W
RW
cC
WAITSLOT
5
EN_F0_DET
RW
4
SIN_MODE
RW
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Description
Not used
0
0
Default
0
Unit of wait time
b00: (1/WAVDAT_MODE) s
b01: (8/WAVDAT_MODE) s
b10: (64/WAVDAT_MODE) s
b11: (512/WAVDAT_MODE) s
0
Control the main loop number
b0000~b1110: play (code+1) time
b1111: playback infinitely until STOP set to 1 or MAINLOOP ≠0xF
0
aw
ini
5:4
Default
on
7:4
Control the loop number of the seventh sequence
b0000~b1110: play (code+1) time
b1111: playback infinitely until STOP set to 1 or SEQ7LOOP ≠0xF
Description
Not used
F0 detection mode enable
1: enable
0: disable
Edge mode for filtered square wave of CONT mode:
1: cos
0: sine
30
Default
0
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1
AW86927
September 2021 V1.2
EDGE_FRE
RW
Define the edge frequency
b1000 : 200Hz
b1001 : 210Hz
b1010 : 260Hz
b1011 : 280Hz
b1100 : 300Hz
b1101 : 600Hz
b1110 : 700Hz
b1111 : 800Hz
b0000-b0111: play non-filtered square wave in CONT mode
CONTCFG2: (Address 19h)
Bit
Symbol
7:0
F_PRE
R/W
RW
Description
Set the value of F0, F0=(24K/code)Hz
CONTCFG3: (Address 1Ah)
Bit
Symbol
R/W
Description
Half cycle drive time of brake and it is also the half cycle drive time of drive when
TRACK_EN=0, this value must be smaller than half cycle time of F0.
Time = code/48000 (s)
Default
Description
Gain factor of brake when BST_MODE is 1
Gain factor of brake when BST_MODE is 0
Default
5
8
Description
Default
14
CONTCFG6: (Address 1Dh)
Bit
Symbol
R/W
7
6:0
TRACK_EN
DRV1_LVL
CONTCFG7: (Address 1Eh)
Bit
Symbol
7
Reserved
6:0
RW
RW
en
R/W
RW
RW
fid
CONTCFG5: (Address 1Ch)
Bit
Symbol
7:4
BST_BRK_GAIN
3:0
BRK_GAIN
on
RW
cC
DRV_WIDTH
R/W
RW
Default
0x8D
0x6A
Track switch
1: enable
0: disable
1
Level for the first cont drive.
When VBAT_MODE=1:
no load output voltage=VBAT_REF*DRV1_LVL/128;
if (VBAT_REF*DRV1_LVL)/VBAT > 128, no load output voltage=PVDD;
When VBAT_MODE=0/BST_MODE=1:
no load output voltage=PVDD*DRV1_LVL/128
aw
ini
7:0
tia
l
3:0
0x7F
Description
Not used
Level for the second cont drive
When VBAT_MODE=1:
no load output voltage=VBAT_REF*DRV2_LVL/128;
if (VBAT_REF*DRV2_LVL)/VBAT > 128, no load output voltage=PVDD;
When VBAT_MODE=0/BST_MODE=1:
no load output voltage=PVDD*DRV2_LVL/128
Default
0
DRV2_LVL
RW
CONTCFG8: (Address 1Fh)
Bit
Symbol
7:0
DRV1_TIME
R/W
RW
Description
Number of half cycle for the first cont drive
Default
4
CONTCFG9: (Address 20h)
Bit
Symbol
7:0
DRV2_TIME
R/W
RW
Description
Number of half cycle for the second cont drive
Default
6
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31
0x50
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AW86927
September 2021 V1.2
CONTCFG10: (Address 21h)
Bit
Symbol
7:0
BRK_TIME
R/W
RW
Description
The num of half cycle of brake mode
Default
8
CONTCFG11: (Address 22h)
Bit
Symbol
R/W
Description
Margin value of tracking, the smaller margin, the higher tracking accuracy and the
lower loop stability. Time = code/480000 (s)
Default
CONTRD15: (Address 26h)
Bit
Symbol
R/W
7:0
F_LRA_F0_L
RO
CONTRD16: (Address 27h)
Bit
Symbol
R/W
7:0
CONT_F0_H
RO
CONTRD17: (Address 28h)
Bit
Symbol
R/W
7:0
CONT_F0_L
RTPCFG1: (Address 2Dh)
Bit
Symbol
7:5
Reserved
BASE_ADDR_H
RTPCFG2: (Address 2Eh)
Bit
Symbol
7:0
RO
R/W
RW
RW
BASE_ADDR_L
RTPCFG3: (Address 2Fh)
Bit
Symbol
R/W
RW
R/W
7:4
FIFO_AEH
RW
3:0
FIFO_AFH
RW
RTPCFG4: (Address 30h)
Bit
Symbol
R/W
7:0
Description
Low 8 bit of the measure value for the f0 of LRA in the f0 detection mode
F0=(384000/(F_LRA_F0_H*256+F_LRA_F0_L))Hz
FIFO_AEL
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RW
Default
0
Default
0
Description
Default
The measure value for the f0 of LRA in the continuous detection mode (high eight
bits) F0=(384000/(CONT_F0_H*256+CONT_F0_L))Hz
0
Description
Default
The measure value for the f0 of LRA in the continuous detection mode (low eight
bits) F0=(384000/(CONT_F0_H*256+CONT_F0_L))Hz
0
Description
Not used
High five bits of start address of wave SRAM
BASE_ADDR = BASE_ADDR_H * 256 + BASE_ADDR_L
Default
0
Description
Low eight bits of start address of wave SRAM
BASE_ADDR = BASE_ADDR_H * 256 + BASE_ADDR_L
Default
Description
High four bits of RTP FIFO almost empty threshold
FIFO_AE = FIFO_AEH * 256 + FIFO_AEL
High four bits of RTP FIFO almost full threshold
FIFO_AF = FIFO_AFH * 256 + FIFO_AFL
Default
Description
Low eight bits of RTP FIFO almost empty threshold
FIFO_AE = FIFO_AEH * 256 + FIFO_AEL
Default
aw
ini
4:0
12
l
RO
tia
F_LRA_F0_H
Description
High 8 bit of the measure value for the f0 of LRA in the f0 detection mode
F0=(384000/(F_LRA_F0_H*256+F_LRA_F0_L))Hz
en
7:0
R/W
fid
CONTRD14: (Address 25h)
Bit
Symbol
RW
on
TRACK_MARGIN
cC
7:0
32
0x08
0
0x02
0x06
0x00
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AW86927
September 2021 V1.2
7:0
R/W
FIFO_AFL
RW
RTPDATA: (Address 32h)
Bit
Symbol
R/W
RTP_DATA
RW
TRGCFG1: (Address 33h)
Bit
Symbol
R/W
Default
Description
RTP mode , data write entry, when data written into this register, the data will be
written into RTP FIFO
Default
0x00
0
l
7:0
Description
Low eight bits of RTP FIFO almost full threshold
FIFO_AF = FIFO_AFH * 256 + FIFO_AFL
tia
RTPCFG5: (Address 31h)
Bit
Symbol
Description
Default
TRG1_POS
RW
TRG1 rising edge enable/disable control
1: enable
0: disable
6:0
TRG1SEQ_P
RW
TRG1 posedge trigged wave sequence number
1
R/W
Description
TRG2 rising edge enable/disable control
1: enable
0: disable
TRG2 posedge trigged wave sequence number
Default
RW
6:0
TRG2SEQ_P
RW
TRGCFG3: (Address 35h)
Bit
Symbol
R/W
7
TRG3_POS
RW
6:0
TRG3SEQ_P
RW
TRGCFG4: (Address 36h)
Bit
Symbol
TRG1_NEG
6:0
TRG1SEQ_N
TRGCFG5: (Address 37h)
Bit
Symbol
Default
Description
Default
0
1
0
RW
TRG1 negedge trigged wave sequence number
1
R/W
Description
TRG2 falling edge enable/disable control
1: enable
0: disable
TRG2 negedge trigged wave sequence number
Default
Description
TRG3 falling edge enable/disable control
1: enable
0: disable
TRG3 negedge trigged wave sequence number
Default
TRG2_NEG
RW
6:0
TRG2SEQ_N
RW
R/W
7
TRG3_NEG
RW
6:0
TRG3SEQ_N
RW
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1
TRG1 falling edge enable/disable control
1: enable
0: disable
RW
7
TRGCFG6: (Address 38h)
Bit
Symbol
0
Description
TRG3 rising edge enable/disable control
1: enable
0: disable
TRG3 posedge trigged wave sequence number
aw
ini
7
R/W
0
fid
TRG2_POS
on
7
cC
TRGCFG2: (Address 34h)
Bit
Symbol
en
7
33
0
1
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AW86927
September 2021 V1.2
TRG1_LEV
RW
5
4
TRG1_BRK
TRG1_BST
RW
RW
3
TRG2_POLAR
RW
2
TRG2_LEV
RW
1
0
TRG2_BRK
TRG2_BST
RW
RW
TRGCFG8: (Address 3Ah)
Bit
Symbol
R/W
7
TRG3_POLAR
RW
6
TRG3_LEV
RW
5
4
3
2
1
0
TRG3_BRK
TRG3_BST
TRG_ONEWIRE
TRG1_STOP
TRG2_STOP
TRG3_STOP
RW
RW
RW
RW
RW
RW
GLBCFG4: (Address 3Eh)
Bit
Symbol
R/W
GO_PRIO
RW
5:4
TRG3_PRIO
RW
3:2
TRG2_PRIO
RW
1:0
TRG1_PRIO
RW
0
When set 1, enable auto brake after TRG1 playback mode is stopped
When set 1, enable boost in TRG1 playback mode.
TRIG2 pin active polarity, when host supply positive level, this bit set to 0, else set
to 1.
TRG2 mode control
1: level
0: edge
When set 1, enable auto brake after TRG2 playback mode is stopped
When set 1, enable boost in TRG2 playback mode.
1
1
Description
TRIG3 pin active polarity, when host supply positive level, this bit set to 0, else set
to 1
TRG3 mode control
1: level
0: edge
When set 1, enable auto brake after TRG3 playback mode is stopped
When set 1, enable boost in TRG3 playback mode.
When set 1,enable one wire mode
When set 1, TRG1 playback mode can be stopped immediately
When set 1, TRG2 playback mode can be stopped immediately
When set 1, TRG3 playback mode can be stopped immediately
Default
Description
Default
0
0
1
1
0
0
1
1
0
0
0
0
Priority value of GO TRIG
High priority can interrupt the playback of low priority, and low priority cannot
interrupt the playback of high priority. When the priority settings are consistent,
the default priority will be implemented
Priority value of TRIG3 pin
High priority can interrupt the playback of low priority, and low priority cannot
interrupt the playback of high priority. When the priority settings are consistent,
the default priority will be implemented
Priority value of TRIG2 pin
High priority can interrupt the playback of low priority, and low priority cannot
interrupt the playback of high priority. When the priority settings are consistent,
the default priority will be implemented
Priority value of TRIG1 pin
High priority can interrupt the playback of low priority, and low priority cannot
interrupt the playback of high priority. When the priority settings are consistent,
the default priority will be implemented
aw
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7:6
TRG1 mode control
1: level
0: edge
l
6
0
tia
RW
en
TRG1_POLAR
Default
fid
7
Description
TRIG1 pin active polarity, when host supply positive level, this bit set to 0, else set
to 1
on
R/W
cC
TRGCFG7: (Address 39h)
Bit
Symbol
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AW86927
September 2021 V1.2
Description
RO
RAMADDRH: (Address 40h)
Bit
Symbol
7:5
Reserved
4:0
RAMADDRH
R/W
RW
RW
RAMADDRL: (Address 41h)
Bit
Symbol
7:0
RAMADDRL
R/W
RW
SRAM address low eight bits
RAMDATA: (Address 42h)
Bit
Symbol
7:0
RAMDATA
R/W
RW
SRAM data entry
SYSCTRL3: (Address 45h)
Bit
Symbol
7:3
Reserved
R/W
RW
Not used
RW
1
0
EN_FIR
Reserved
RW
RW
SYSCTRL4: (Address 46h)
Bit
Symbol
7
Reserved
R/W
RW
6:5
WAVDAT_MODE
RW
4:1
Reserved
RW
GAIN_BYPASS
RW
R/W
7
PRC_EN
RW
6:0
PRCTIME
RW
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tia
fid
Description
on
EN_RAMINIT
Description
Not used
SRAM address high five bits
Default
0
0
Default
0
Description
Default
0
Description
Default
2
Enable clock:
1: open the digital module clock
0: close the digital module clock
0
Set enable of FIR filter
Not used
1
0
aw
ini
2
PWMCFG1: (Address 48h)
Bit
Symbol
0
l
GLB_STATE
0
Default
0
Not used
The state of glb state
b0000: STANDBY
b0110: CONT
b0111: RAM
b1000: RTP
b1001: TRIG
b1011: BRAKE
cC
3:0
R/W
RO
en
GLBRD5: (Address 3Fh)
Bit
Symbol
7:4
Reserved
Description
Not used
Waveform data upsample rate selection:
b00: 24kHz
b01: 48kHz
others: 12kHz rate
Not used
Default
0
0
4
1: gain can be changed when playing
0: gain can not be changed when playing
Description
Set enable of output signal protection mode of pwm:
0: disable
1: When HDP/HDN output voltage ≥ 124/128*PVDD maintains (PRCTIME/3k)s,
HDP/HDN is pulled down protectively
Set protection time of output signal protection mode of pwm, unit time is (1/3k) s
35
0
Default
0
0x00
Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
WMCFG3: (Address 4Ah)
Bit
Symbol
PR_EN
RW
6:0
PRLVL
RW
PWMCFG4: (Address 4Bh)
Bit
Symbol
7:0
PRTIME
R/W
RW
Description
Set protection time of input signal protection mode of pwm, unit time is (1/3k) s
VBATCTRL: (Address 4Ch)
Bit
Symbol
7
reserved
R/W
RW
DETCFG1: (Address 4Dh)
Bit
Symbol
7
Reserved
R/W
RW
VBAT_REF
RW
3:2
ADC_FS
RW
1:0
DET_GO
RW
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Default
0
Description
Not used
Reference voltage for VBAT hardware adjust mode:
b000: 3.3V
b001: 3.6V
b010: 4.0V
b011: 4.2V
b100: 4.5V
b101: 4.8V
b110: 5.0V
b111: 5.5V
When VBAT_MODE=1: no load output voltage=VBAT_REF*WAVE_CODE/128;
if (VBAT_REF* WAVE_CODE)/VBAT > 128, no load output voltage=PVDD;
When VBAT_MODE=0/BST_MODE=1: no load output voltage=PVDD*WAVE_CODE
/128. (WAVE_CODE is the data of wave)
ADC clock sampling rate:
b00: 192KHz(ADC_CLK=6.144MHz)
b01: 96KHz(ADC_CLK=3.072MHz)
b10: 48KHz(ADC_CLK=1.536MHz)
b11: 24KHz(ADC_CLK=768KHz)
0
0
Default
0
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6:4
0x3F
en
RW
fid
reserved
5:0
Default
0x32
1
on
RW
Description
Not used
VBAT adjust mode:
0: software adjust mode
1: hardware adjust mode
Not used
Default
cC
VBAT_MODE
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7
Description
Set enable of input signal protection mode of pwm:
0: disable
1: When output voltage >= PRLVL/128*PVDD maintains (PRTIME/3k)s, HDP/HDN is
pulled down protectively
Set protection voltage of input signal protection mode of pwm
6
R/W
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ADC sampling mode control:
b01: det
others: not det
36
Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
2
1
0
AW86927
September 2021 V1.2
Description
DET_SEQ0
RW
2:0
D2S_GAIN
RW
DET_RD1: (Address 4Fh)
Bit
Symbol
7:4
Reserved
R/W
RO
Not used
0
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6:3
Default
0
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Not used
Sequence0 detect type control:
b0000: VBAT
b0001: PVDD
b0011: RL
b0100: OS
Others: for test
Set D2S gain:
b000: 1
b001: 2
b010: 4
b011: 8
b100: 10
b101: 16
b110: 20
b111: 40
en
R/W
RW
Description
fid
DETCFG2: (Address 4Eh)
Bit
Symbol
7
Reserved
4
Default
0
ADC_DATA_H
RO
The measured value of one time adc data(high two bits)
0
1:0
AVG_DATA_H
RO
The measured value of 16 times adc average data(high two bits)
0
7:0
AVG_DATA_L
DET_RD3: (Address 51h)
Bit
Symbol
7:0
ADC_DATA_L
R/W
RO
R/W
RO
(Address 57h)
Symbol
R/W
7:0
CHIPID_H
RO
IDT_RD3: (Address 58h)
Bit
Symbol
R/W
7:0
CHIPID_L
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RO
Default
Description
0
Default
The measured value of one times adc data(low eight bits)
Description
High 8 bit of CHIP_ID
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IDH:
Bit
Description
The measured value of 16 times adc average data(low eight bits)
cC
DET_RD2: (Address 50h)
Bit
Symbol
on
3:2
Low 8 bit of CHIP_ID
37
0
Default
0x92
Description
Default
0x70
Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Application Information
Inductor Selection Guideline
𝑅
(𝑉𝑂𝑈𝑇 ×𝑅 +𝑅 𝐿
)2
𝐿
𝐷𝑆𝑂𝑁
8
=
2×𝑅𝐿 ×(1−2.3%)
(8.5×8+0.3)2
𝑤 = 4.294𝑤
cC
𝑃𝑂𝑈𝑇 =
on
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Selecting inductor needs to consider Inductance, size, magnetic shielding, saturation current and temperature
current.
a) Inductance
Inductance value is limited by the boost converter's internal loop compensation. In order to ensure phase
margin sufficient under all operating conditions, recommended 1μH inductor.
b) Size
For a certain value of inductor, the smaller the size, the greater the parasitic series resistance of the inductor
DCR, the higher the loss, corresponds to the lower efficiency.
c) Magnetic shielding
Magnetic shielding can effectively prevent the inductance of the electromagnetic radiation interference. It is
much better to choose inductance with magnetic shielding in the application of EMI sensitive environment.
d) Saturation current and temperature rise of current
Inductor saturation current and temperature rise current value are important basis for selecting the inductor.
As the inductor current increases, on the one hand, since the magnetic core begins to saturate, inductance
value will decline; on the other hand, the inductor's parasitic resistance inductance and magnetic core loss can
lead to temperature rise. In general, the current value is defined as the saturation current ISAT when the
inductance value drops to 70%; the current value is defined as temperature rise current IRMS when inductance
temperature rise 40oC.
For particular applications, need to calculate the maximum IL_PEAK and IL_RMS, which is a basis of selecting the
inductor. When VBAT=3.8V, PVDD=8.5V, RL = 8Ω，Output drive RDSON =300mΩ, when the maximum power
without distortion, the output power is calculated as follows:
2×8×0.977
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Where the coefficients in the denominator of (0.977) is the power ratio of no truncation maximum output. In
such a large output power, the overall efficiency of the output drive is typically 75%, in order to calculate the
maximum average current IMAX_AVG_VBAT and maximum peak current IMAX_PEAK_VBAT drawn from VBAT:
𝑃𝑂𝑈𝑇
4.294
𝐼𝑀𝐴𝑋_𝐴𝑉𝐺_𝑉𝐵𝐴𝑇 =
=
𝐴 = 1.507𝐴
𝑉𝐵𝐴𝑇 × ղ 3.8 × 0.75
𝐼𝑀𝐴𝑋_𝑃𝐸𝐴𝐾_𝑉𝐵𝐴𝑇 = 2 × 𝐼𝑀𝐴𝑋_𝐴𝑉𝐺_𝑉𝐵𝐴𝑇 = 2 × 1.507A = 3.014A
If inductor DCR is 50mΩ, then when the output power of 4.294W, the inductor power loss is:
2
𝑃𝐷𝐶𝑅.𝐿𝑂𝑆𝑆 = 1.5 × 𝐼𝑀𝐴𝑋_𝐴𝑉𝐺_𝑉𝐵𝐴𝑇
× 𝐷𝐶𝑅 = 1.5 × 1.5072 × 0.05 𝑊 = 170.3 𝑚𝑊
Wherein the coefficient 1.5 is the square of the ratio of the sine wave current RMS value and average value
(there is no consideration of the impact of the inductor ripple, the actual DCR loss will be even greater). If the
loss which is resulting from DCR is less than 1% at efficiency (POUT = 4.294W, η = 75%), then:
𝐷𝐶𝑅 =
𝑃𝐷𝐶𝑅.𝐿𝑂𝑆𝑆
2
1.5×𝐼𝑀𝐴𝑋_𝐴𝑉𝐺_𝑉𝐵𝐴𝑇
≤ 0.01 ×
𝑃𝑂𝑈𝑇
2
1.5×𝐼𝑀𝐴𝑋_𝐴𝑉𝐺_𝑉𝐵𝐴𝑇
×ղ
=
0.01×4.294
1.5×1.5072 ×0.75
𝛺 = 16.8 𝑚𝛺
According to the working principle of the Boost, we can calculate the size of the inductor current ripple ΔIL:
△ 𝐼𝐿 =
𝑉𝐵𝐴𝑇×(𝑃𝑉𝐷𝐷−𝑉𝐵𝐴𝑇)
𝑃𝑉𝐷𝐷×𝑓×𝐿
=
3.8×(8.5−3.8)
8.5×2×1
𝐴 = 1.050𝐴
Thus, the maximum peak inductor current IL_PEAK and maximum effective inductor current IL_RMS is:
𝐼𝐿_𝑃𝐸𝐴𝐾 = 𝐼𝑀𝐴𝑋_𝑃𝐸𝐴𝐾_𝑉𝐵𝐴𝑇 +
www.awinic.com
△𝐼𝐿
2
= 3.014 +
38
1.050
2
𝐴 = 3.539𝐴
Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
2
𝐼𝐿_𝑅𝑀𝑆 = √𝐼𝑀𝐴𝑋_𝑃𝐸𝐴𝐾_𝑉𝐵𝐴𝑇
+
△ 𝐼𝐿2
1.0502
= √3.0142 +
𝐴 = 3.029𝐴
12
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From the above calculation results:
1) For typical DCR about 50mΩ inductance, the efficiency loss caused by around 3%;
2) Need to choose AW86927 inductance input current limit value ILIMIT is greater than IL_PEAK = 3.6A (< ILIMIT =
4.5A), to guarantee the output drive power can be achieved when THD = 1% (= 4.1W) but not limited by
value ILIMIT; If you choose ISAT or IRMS of the inductance is too small, it is possible to cause the chip don’t
work properly, or the temperature of the inductance is too high.
3) In practice, the maximum output power of the drive is likely to reach 4.3W in an instant, so the selected
inductor saturation current ISAT requires more than the maximum inductor peak current IL_PEAK, and cannot
be less than 3.6A;
4) In some cases, if the IL_PEAK calculated according to the above method is greater than the set of input
inductor current limit value ILIMIT, shows the output drive is restricted by inductance input current limit, the
actual maximum output power is less than the calculated value, the measured value shall prevail, and I SAT
need greater than the set current limiting value ILIMIT, and cannot be less than 3.6A;
5) Take PVDD = 8.5V for example, under different conditions, the typical method of selecting I SAT in the
following table:
PVDD
RL
IL_PEAK
(V)
(V)
(Ω)
(A)
Inductor saturation
current ISAT minimum
value (A)
3.4
8.5
8
3.9
4.5
3.4
8.5
2.3
2.5
16
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Capacitors Selection
on
VBAT
Boost Capacitor Selection
aw
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Boost output capacitor is usually within the range 0.1μF~47μF. It needs to use Class II type (EIA) multilayer
ceramic capacitors (MLCC). Its internal dielectric is ferroelectric material (typically BaTiO3), a high the dielectric
constant in order to achieve smaller size, but at the same Class II type (EIA) multilayer ceramic capacitors has
poor temperature stability and voltage stability as compared to the Class I type (EIA) capacitance. Capacitor
is selected based on the requirements of temperature stability and voltage stability, considering the
capacitance material, capacitor voltage, and capacitor size and capacitance values.
A) temperature stability
Class II capacitance have different temperature stability in different materials, usually choose X5R type in order
to ensure enough temperature stability, and X7R type capacitance has better properties, the price is relatively
more expensive; X5R capacitance change within ± 15% in temperature range of -55°C to 85°C, X7R
capacitance change within ±15% in temperature range of -55°C~125°C. The Boost output capacitance of
AW86927 recommends X5R ceramic capacitors.
B) Voltage Stability
Class II type capacitor has poor voltage stability Capacitance values falling fast along with the DC bias voltage
applied across the capacitor increasing. The rate of decline is related to capacitance material, capacitors rated
voltage, capacitance volume. Take for TDK C series X5R for example, its pressure voltage value is 16V or 25V;
the package size is 0805, 1206 or 0603, the capacitance value is 10μF. The capacitor’s voltage stability of
different types of capacitor is as shown below:
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39
Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Capacitor Variation v.s. DC Voltage
10
0603,X5R,16V,10uF,0.80mm
0603,X5R,25V,10uF,0.80mm
0805,X5R,16V,10uF,0.85mm
0805,X5R,16V,10uF,1.25mm
0805,X5R,25V,10uF,0.85mm
0805,X5R,25V,10uF,1.25mm
1206,X5R,16V,10uF,0.85mm
1206,X5R,16V,10uF,1.60mm
1206,X5R,25V,10uF,0.85mm
1206,X5R,25V,10uF,1.60mm
0
-10
C-Change (%)
-20
-30
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-40
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-50
-60
en
-70
-80
-90
0
5
10
15
fid
-100
20
25
VDC (V)
on
Figure 28 Different types of capacitive voltage stability
Among them, the space remaining value of different types of capacitors at VDC = 8.5 V as shown in the Figure
29:
cC
Cap@VDC=8.5V
9
7.68uF
6.47uF
6.35uF
VDC=8.5V
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2.84uF
2.70uF
1206,X5R,25V,10uF,1.60mm
1206,X5R,25V,10uF,0.85mm
1206,X5R,16V,10uF,1.60mm
1206,X5R,16V,10uF,0.85mm
0805,X5R,25V,10uF,1.25mm
0805,X5R,25V,10uF,0.85mm
0805,X5R,16V,10uF,1.25mm
0805,X5R,16V,10uF,0.85mm
0603,X5R,25V,10uF,0.80mm
0603,X5R,16V,10uF,0.80mm
2.34uF
2.20uF
1.93uF
1.74uF
1.72uF
8
0
1
2
3
4
5
C (uF)
6
7
8
9
10
Figure 29 The space remaining value of different types of capacitors at VDC = 8.5 V
It can be found that the rate of capacitance capacity value descent becomes slow along with "large capacitor
size, capacitance pressure voltage rise”. The larger the package size, the better voltage stability. The higher
the height, the better voltage stability with the same length and width of the capacitance. Voltage stability of
smaller package size (0603) capacitor change affected by the pressure value is very small.
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40
Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
In AW86927 typical applications, it is necessary to ensure the output value of the Boost capacitor ≥ 5μF when
PVDD=8.5V.
Supply Decoupling Capacitor（CS）
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The device is a high voltage driver that requires adequate power supply decoupling. Place a low equivalentseries-resistance (ESR) ceramic capacitor, typically 0.1μF. This choice of capacitor and placement helps with
higher frequency transients, spikes, or digital hash on the line. Additionally, placing this decoupling capacitor
close to the device is important, as any parasitic resistance or inductance between the device and the capacitor
causes efficiency loss. In addition to the 0.1μF ceramic capacitor, place a 10μF capacitor on the VBAT supply
trace. This larger capacitor acts as a charge reservoir, providing energy faster than the board supply, thus
helping to prevent any droop in the supply voltage.
Output beads, capacitors
Wavefo rm After
PCB tra ce s
Wavefo rm afte r
bea ds
fid
Wavefo rm
from chip
en
The device output is a square wave signal, which causing switch current at the output capacitor, increasing
static power consumption, and therefore output capacitor should not be too large, 0.1nF ceramic capacitors is
recommended.
PCB tra ce s
PCB tra ce s
cC
HDN
on
Bead
HDP
0.1nF
LRA
Bead
0.1nF
Figure 30 Ferrite Chip Bead and capacitor
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The device output is a square wave signal. The voltage across the capacitor will be much larger than the PVDD
voltage after increasing the bead capacitor. It suggested the use of rated voltage above 16V capacitor. At the
same time a square wave signal at the output capacitor switching current form, the static power consumption
increases, so the output capacitance should not be too much which is recommended 0.1nF ceramic capacitor
rated voltage of 16V.
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41
Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
PCB Layout Consideration
Layout Considerations
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This device is a high voltage driver chip. To obtain the optimal performance, PCB layout should be considered
carefully. The suggested Layout is illustrated in the following diagram:
Figure 31 AW86927 Board Layout
Here are some guidelines:
1. All of the external components should be placed as close as possible to IC in top layer PCB.
2. SCL and SDA should be shield by ground.
3. The overcurrent capability of the VBAT to SW must be meet IMAX_AVG_VBAT(Take the measured data as an
example: VBAT=3.4V, PVDD=9V, RL = 8Ω, the routing overcurrent capacity should be greater than 2.6A),
and C2, C3, C4 should be placed close to IC and L1.
4. C6 and C7 are within 1.5mm to pin PVDD or pin VBST, and the overcurrent capability of the VBST and
𝑃𝑉𝐷𝐷
PVDD traces must be meet
, and the GND side of the PVDD capacitor should be directly
𝑅𝐿 +𝑅𝐷𝑆𝑂𝑁
connected to surface layer ground or punched to the main ground of the PCB. In addition, create solid
GND plane near and around the IC, connect BGND, PGND and GND together, and the overcurrent
capability of the vias should be designed according to the PVDD overcurrent capability.
5. Routing overcurrent capability of HDP/HDN output to the load should meet
𝑃𝑉𝐷𝐷
𝑅𝐿 +𝑅𝐷𝑆𝑂𝑁
. HDP and HDN
should be shield by ground and far away from the interference source especially the FLY capacitor of the
high-power charging IC, otherwise it will cause the abnormal F0 detection.
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42
Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Tape And Reel Information
TAPE DIMENSIONS
REEL DIMENSIONS
P1
P0
P2
K0
D1
A0
en
Cavity
B0
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W
fid
A0：Dimension designed to accommodate the component width
B0：Dimension designed to accommodate the component length
K0：Dimension designed to accommodate the component thickness
W：Overall width of the carrier tape
P0：Pitch between successive cavity centers and sprocket hole
P1：Pitch between successive cavity centers
P2：Pitch between sprocket hole
D1：Reel Diameter
D0：Reel Width
on
D0
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
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Pin 1
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
Q3
Q4
Q3
Q4
Sprocket Holes
User Direction of Feed
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Pocket Quadrants
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Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Package Description
3.00±0.05
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2.00±0.05
PIN1 Corner
fid
Top View
0.152 Ref
on
0.55±0.05
0.00~0.05
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Side View
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16x0.40
20x0.2
1
6
0.25±0.05
7
20
SYMM
17
10
11
16
11x(0.3±0.05)
8x(0.45±0.05)
SYMM
Bottom View
Unit:mm
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44
Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Land Pattern Data
2.20
20
0.40 TYP
17
8 X 0.1 0 R EF
8 X 0.1 0 R EF
16
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1
0.40 TYP
20X 0.20
SYMM
en
3.20
fid
8X 0.55
11
6
12X 0.40
10
on
7
0.05 MAX
All AROUND
cC
SYMM
SOLDER MASK
OPENING
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METAL
NO N-SOLDER MASK DEFINED
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45
0.05 MIN
All AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK DEFINED
Unit：mm
Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Revision History
Version
Date
Change Record
V1.0
August
2021
Official Version
V1.1
August
2021
V1.2
September
2021
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Revise Pin Definition(RSTN/HDP/HDN/TEST description)
Revise Register DRV1_LEV/ DRV2_LEV/VBAT_REF/EN_RAMINIT description
Revise PCB Layout Figure font
Revise Playback Sequence Figure
Revise Inductor Selection from 3A to 2.5A When RL=16Ω
Revise Register BST_VOUT_VREFSET description
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46
Copyright © 2021 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW86927
September 2021 V1.2
Disclaimer
l
Information in this document is believed to be accurate and reliable. However, Shanghai AWINIC Technology
Co., Ltd (AWINIC Technology) does not give any representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and shall have no liability for the consequences of use of
such information.
tia
AWINIC Technology reserves the right to make changes to information published in this document, including
without limitation specifications and product descriptions, at any time and without notice. Customers shall
obtain the latest relevant information before placing orders and shall verify that such information is current and
complete. This document supersedes and replaces all information supplied prior to the publication hereof.
fid
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AWINIC Technology products are not designed, authorized or warranted to be suitable for use in medical,
military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an AWINIC
Technology product can reasonably be expected to result in personal injury, death or severe property or
environmental damage. AWINIC Technology accepts no liability for inclusion and/or use of AWINIC
Technology products in such equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
on
Applications that are described herein for any of these products are for illustrative purposes only. AWINIC
Technology makes no representation or warranty that such applications will be suitable for the specified use
without further testing or modification.
All products are sold subject to the general terms and conditions of commercial sale supplied at the time of
order acknowledgement.
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Nothing in this document may be interpreted or construed as an offer to sell products that is open for
acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other
industrial or intellectual property rights.
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Reproduction of AWINIC information in AWINIC data books or data sheets is permissible only if reproduction
is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices.
AWINIC is not responsible or liable for such altered documentation. Information of third parties may be subject
to additional restrictions.
Resale of AWINIC components or services with statements different from or beyond the parameters stated by
AWINIC for that component or service voids all express and any implied warranties for the associated AWINIC
component or service and is an unfair and deceptive business practice. AWINIC is not responsible or liable for
any such statements.
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