AW88298
May. 2022 V1.6
I2S/TDM Input, 10.25V BOOST Digital Smart K Audio Amplifier
FEATURES
DESCRIPTION
⚫
⚫
The AW88298 is an I2S/TDM input, high efficiency
digital Smart K audio amplifier with an integrated
10.25V smart boost converter. Due to its 12uV
noise floor and ultra-low distortion, clean listening
is guaranteed. It can deliver 5.2W output power
into an 8Ω speaker at 1% THD+N.
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Smart BOOST with total efficiency up to 84%
High RF noise suppression, eliminate the
⚫
⚫
Extensive Pop-Click Suppression
Volume Control (from -96dB to 0dB)
⚫
I2S/TDM interface：
I2S, Left-Justified and Right-Justified
◼
Supports four slots TDM
◼
◼
Input Sample Rates from 8kHz to 96kHz
Data Width: 16, 20, 24, 32 Bits
⚫
I2C-bus control interface(400kHz)
⚫
Power Supplies：
◼
◼
◼ VDDIO: 1.65V~3.6V
Short-Circuit Protection, Over-Temperature
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⚫
VDD: 3.0V-5.5V
DVDD: 1.65V~1.95V
Protection, Under-Voltage Protection and Over⚫
Voltage Protection
QFN 3.5mm X3.5mm X0.75mm-24L package
⚫
⚫
⚫
The AW88298 offers Short Circuit Protection,
Over-Temperature Protection, Under-Voltage
Protection and Over-Voltage Protection to protect
the device.
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APPLICATIONS
The AW88298 features high RF suppression and
eliminates TDD noise completely benefited from
the digital audio input interface. General settings
are communicated via an I2C-bus interface, and
the device address is configurable.
on
◼
The AW88298 integrates a high-efficiency smart
boost converter as the Class-D amplifier supply
rail. The output voltage of boost converter can be
adjusted smartly according to the input amplitude,
which extremely improves the efficiency without
clipping distortion.
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Low noise: 12uV
THD+N: 0.02%
fid
⚫
⚫
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TDD noise completely
Mobile phones
Tablets
Portable Audio Devices
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
PIN CONFIGURATION AND TOP MARK
AW88298QNR MARKING
SW
5
14 SCL
NC
6
13 SDA
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15 BCK
on
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en
4
AD1 12
VBST
RSTN 11
16 DATAI
INTN 10
3
9
PVDD
VDD
17 WCK
8
2
GND
VOP
7
18 VDDIO
BGND
1
2HU3
XXXX
VON
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19 DATAO
20 DVDD
21 TEST2
22 TEST1
23 AD2
24 PGND
AW88298QNR TOP VIEW
2HU3 – AW88298QNR
XXXX – Product Tracing Code
PIN DESCRIPTION
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AW88298QNR pin diagram top view and device marking
Pin Name
1
VON
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Pin No
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Description
Inverting Class-D output
2
VOP
Non-inverting Class-D output
3
PVDD
Power stage supply
4
VBST
Boost output
5
SW
Boost switch pin
6
NC
Not connected, connect to ground
7
BGND
8
GND
GND
9
VDD
Battery power supply
10
INTN
Interrupt output
11
RSTN
Active low hardware reset
12
AD1
I2C address select input
13
SDA
I2C data I/O
Boost GND
2
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
Pin No
Pin Name
Description
14
SCL
I2C clock input
15
BCK
I2S/TDM bit clock input
16
DATAI
17
WCK
18
VDDIO
IO Voltage
19
DATAO
I2S/TDM data out
20
DVDD
Digital power supply
21
TEST2
Test Pin, connect to ground
22
TEST1
Test Pin, connect to ground
23
AD2
24
PGND
I2S/TDM data input
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on
fid
Power GND
en
I2C address select input
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I2S word select input / TDM frame sync signal
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
FUNCTIONAL BLOCK DIAGRAM
DVDD
SCL
SDA
VDD
BOOST
I2C
Interface
INTN
Digital Audio Processing path
Digital
Audio
Interface
DATA Collector
Class-D
Amplifier
VON
VOP
AW8896
PLL
fid
M
U
X
DAC
PVDD
en
BCK
WCK
DATAI
DATAO
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AD2
AD1
VBST
SW
ADC
on
OVP,OCP,OTP
DGND
BGND
Temp Sense
PVDD/VBAT Sense
PGND
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cC
FUNCTIONAL BLOCK DIAGRAM
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
APPLICATION DIAGRAM
VBAT
1.8V
L 1uH
4A
C3
10uF
1.65V ~ 3.6V
20
I2S Interface
PVDD
16
19
11
10
SCL
SDA
AD2
AD1
BCK
WCK
AW88298
DATAI
DATAO
RSTN
INTN
en
13
23
12
15
17
VBST
VOP
fid
I C Interface
SW
VDD
C11
0.1uF
14
2
DVDD
VDDIO
on
C10
1uF
5
9
3
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18
C4
0.1uF
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C2
1uF
C1
1uF
2
B+
optional
VON
GND
BGND
PGND
8
7
24
1
C6
10uF
25V
C5
10uF
25V
C7
0.1nF
SPK
B-
optional
C8
0.1nF
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NC TEST1TEST2
6 22 21
4
AW88298 Application Circuit
Note: Traces carry high current are marked in red in the above figure
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All trademarks are the property of their respective owners.
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
ORDERING INFORMATION
Product Type
Temperature
Moisture
Device
Environmenta
Sensitivity
Delivery Form
Marking
l Information
Level
Package
WBQFN
-40℃～85℃
3.5mmX3.5mm24L
2HU3
MSL3
RoHS+HF
6000 units/
Tape and Reel
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on
fid
en
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AW88298QNR
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
ABSOLUTE MAXIMUM RATING(NOTE1)
Range
Battery Supply Voltage VDD
-0.3V to 6V
Digital Supply Voltage VDVDD
-0.3V to 2V
Digital Supply Voltage VDDIO
-0.3V to 4.6V
Boost output voltage VPVDD
-0.3 to 13V
Boost SW pin voltage
-0.3 to VPVDD+2V (Note 2)
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Parameter
VOP/VON pin voltage
-0.3 to VPVDD+2V (Note 2)
Minimum load resistance RL
3.2Ω(Note 3)
60°C/W
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Package Thermal Resistance θJA
Ambient Temperature Range
Maximum Junction Temperature TJMAX
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Storage Temperature Range TSTG
Lead Temperature (Soldering 10 Seconds)
ESD Rating
165°C
-65°C to 150°C
260°C
(Note 4,5)
on
HBM (Human Body Model)
-40°C to 85°C
CDM (Charge Device Model)
±2000V
±1000V
Latch-up
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Test Condition：JEDEC STANDARD NO.78E SEPTEMBER 2016
+IT：450mA
-IT：-450mA
Note 1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
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are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under
"recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods
may affect device reliability.
Note 2: SW/VOP/VON pin can handle 16V transients for less than 5ns
Note 3: When the load resistance RL is less than 5Ω, please refer to the corresponding application notes and the maximum
boost output voltage VPVDD should be less than 9V.
Note 4: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test method:
ESDA/JEDEC JS-001
Note 5: Test method: ESDA/JEDEC JS-002
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
ELECTRICAL CHARACTERISTICS
CHARACTERISTICS
Test condition: TA=25°C，VDD=3.6V，DVDD=1.8V , VDDIO=1.8V, PVDD=10.25V，RL=8Ω+33μH，f=1kHz(unless
otherwise noted)
Test Conditions
Battery supply voltage
On pin VDD
VDVDD
Digital supply voltage
On pin DVDD
VDDIO
Digital IO supply voltage
On pin VDDIO
IVDD
Battery supply current
IDVDD
Digital supply current
Operating mode
Power down mode
Over-voltage threshold
IL_PEAK
Inductor peak current limit
Max
Units
5.5
V
1.95
V
3.6
V
5.5
on
OVP hysteresis voltage
1.8
1.65
Power down mode
Boost output voltage
VOVP
1.65
fid
VPVDD
3
Operating mode
Boost
Typ.
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VDD
Min
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Description
en
Symbol
2
A
4.5
mA
5
A
10.25(Note1)
V
VPVDD+0.5
V
500
mV
3.75(Note1)
A
1.6
MHz
90
%
Operating Frequency
DMAX
The maximum duty cycle
ηBST
Boost converter efficiency
VDD=4.2V, Iload = 0.5A
SmartBoost
88
%
Drain-Source on-state
resistance
High side MOS + Low side
MOS
300
mΩ
THD+N=1%, RL=8Ω+33μH,
VDD=4.2V, PVDD=10.25V
5.2
W
THD+N=10%, RL=8Ω+33μH,
VDD=4.2V, PVDD=10.25V
6.2
W
THD+N=1%, RL=6Ω+33μH,
VDD=4.2V, PVDD=10.25V
5.35
W
THD+N=10%, RL=6Ω+33μH,
VDD=4.2V, PVDD=10.25V
6.5
W
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FBST
Po
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Class-D
Rdson
fs = 48KHz
0.3
mA
VOS
η
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Speaker Output Power
Output offset voltage
I2S signal input 0
Total efficiency
(Class-D)
VDD=4.2V, Po=0.5W,
RL=8Ω+33μH
89
%
Total efficiency
(SmartBoost+Class-D)
VDD=4.2V, Po=1W,
RL=8Ω+33μH
84
%
8
-30
0
30
mV
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
Description
Total harmonic distortion
plus noise
EN
SNR
RL=8Ω+33μH, f=1kHz，
PVDD=10.25V
Receiver Mode Output
noise
A-weighting
12
μV
VDD=4.2V, PVDD=10.25V,
Po=5.2W, RL=8Ω+33μH,
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217Hz
1kHz
fid
Logic input low level
Logic input high level
VIL
Logic input low level
VIH
Logic input high level
VOL
Logic output low level
IOUT=2mA
VOH
Logic output high level
IOUT=-2mA
on
VIH
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RSTN, SCL, SDA, AD1, AD2
Pin
109
dB
-85
dB
-80
dB
0.7 x
VDDIO
0.7 x
VDVDD
VDDIO 0.45
0.3 x
VDDIO
V
VDDIO
V
0.3 x
VDVDD
V
3.6
V
0.45
V
VDDIO
V
Over temperature protection
threshold
160
°C
Over temperature protection
recovery threshold
130
°C
Under-voltage protection
voltage
2.6
V
Under-voltage protection
hysteresis voltage
100
mV
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UVP
%
μV
BCK, WCK, DATAI Pin
TSDR
0.02
22
Digital Logical Interface
TSD
Units
A-weighting
Receiver Mode,
Power supply rejection ratio VDD=4.2V,
Vp-p_sin=200mV
Protection
Max
VDD=4.2V, Po=1W,
A-weighting
VIL
Typ.
Speaker Mode Output
noise
Signal-to-noise ratio
PSRR
Min
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THD+N
Test Conditions
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Symbol
Note 1：Registers are adjustable; Refer to the list of registers.
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
I2C INTERFACE TIMING
Parameter
MIN
MAX
UNIT
400
kHz
Sym
1
fSCL
SCL Clock frequency
2
tLOW
SCL Low level Duration
1.3
μs
3
tHIGH
SCL High level Duration
0.6
μs
4
tRISE
SCL, SDA rise time
5
tFALL
SCL, SDA fall time
6
tSU:STA
Setup time SCL to START state
7
tHD:STA
(Repeat-start) Start condition hold time
8
tSU:STO
Stop condition setup time
9
tBUF
10
11
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Name
TYP
No.
0.3
μs
0.3
μs
en
0.6
μs
μs
0.6
μs
the Bus idle time START state to STOP state
1.3
μs
tSU:DAT
SDA setup time
0.1
μs
tHD:DAT
SDA hold time
10
ns
SDA
(2)
tLOW
on
(3)
tHI GH
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SCL
fid
0.6
tRI SE
tFALL
(4)
(5)
tSU:DAT
tHD:DAT
(10)
(11)
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SCL and SDA timing relationships in the data transmission process
SCL
tHD:STA
tSU:STO
(7)
(8)
(6)
(9)
tSU:STA
tBUF
SDA
The timing relationship between START and STOP state
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
DIGITAL AUDIO INTERFACE TIMING
Min
Parameter Name
Typ.
Max
Units
sampling frequency, on pin WCK
8
96
kHz
fbck
Bit clock frequency, on pin BCK
32*fs
128*fs
Hz
tsu
WCK, DATAI Setup time to BCK
10
th
WCK, DATAI hold time to BCK
10
td
DATAO output delay time to BCK
ns
50
ns
en
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ns
fid
WCK
BCK
td
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DATAI
th
on
tsu
DATAO
l
fs
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Digital Audio Interface Timing
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
TYPICAL CHARACTERISTIC CURVES
THD+N VS. FREQUENCY
on
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THD+N VS. FREQUENCY
THD+N VS. OUTPUT POWER
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THD+N VS. OUTPUT POWER
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
OUTPUT POWER VS. Din
on
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GAIN VS. FREQUENCY
EFFICIENCY VS. OUTPUT POWER
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EFFICIENCY VS. OUTPUT POWER
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
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on
fid
en
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RECEIVER PSRR VS. FREQUENCY
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
DETAIL FUNCTIONAL DESCRIPTION
POWER ON RESET
The device provides a power-on reset feature that is controlled by VDD and DVDD supply voltage. When the
VDD supply voltage raises from 0V to 2.1V, or DVDD supply voltage raises from 0V to 1.1V. The reset signal
will be generated to perform a power-on reset operation, which will reset all circuits and configuration registers.
The device supports 4 operation modes.
Table 1 Operating Mode
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OPERATION MODE
Condition
Description
Power-Down
VDD < 2.1V
VDVDD < 1.1V
Power supply is not ready, chipset is power down.
Stand-By
VDD > 3V
VDVDD > 1.65V
Power supply is ready, most parts of the device are power down for
low power consumption except I2C interface
Configuring
PWDN = 0
Device is biased while boost and class-D output is floating.
System configuration carried out in this mode
Operating
AMPPD = 0
Amplifier is fully operating
on
fid
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Mode
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Power-down
Power supply fault
(VBAT < 2.1V, VDVDD < 1.1V)
Power supply OK
(VBAT > 3.0V, VDVDD > 1.65V)
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SYSCTRL.PWDN = 0
Stand-By
SYSCTRL.AMPPD = 0
Configuring
SYSCTRL.PWDN = 1
Operating
SYSCTRL.AMPPD = 1
Device operating modes transition
POWER-DOWN MODE
The device switches to power-down mode when any of the following events occurred:
◼ VDVDD < 1.1 V
◼ VDD < 2.1 V
◼ RSTN pin goes LOW
In this mode, all circuits inside this device will be shut down except the power-on-reset circuit. I2C interface isn’t
accessible in this mode, and all of the internal configurable registers are cleared.
The device will jump out of the power-down mode automatically when all of the supply voltages are OK:
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
VDVDD > 1.65 V and VDD > 3 V
And RSTN goes HIGH.
STAND-BY MODE
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The device switches stand-by mode when the power supply voltages are OK and RSTN pin is HIGH. In this
mode I2C interface is accessible, other modules are still powered down. Customer can set device to mode when
the device is no needed to work.
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CONFIG MODE
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The device switches to OFF mode when:
◼ SYSCTRL.PWDN = 0;
◼ SYSCTRL.AMPPD = 1;
In this mode the internal bias, OSC, PLL will start to work
OPERATING MODE
SET PWDN = 0
Bias, OSC, PLL
DataPath Cfg
SET AMPPD = 0
2
Assuming I S Clock is active and stable at this time
Wait until PLL Locked
cC
DAP configuring
on
Power Up
fid
The device is fully operational in this mode. Boost, amplifier loop and power stage circuits will start to work.
Customer can set SYSCTRL.AMPPD = 0 to make device in this mode.
This device power up sequence is illustrated in the following figure:
Boost bootup
Class D bootup
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SET HMUTE = 0
Mute disable
Power up sequence
Detail description for each step is listed in the following table.
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
Table 2 Detail Description of Power up sequence
Index
description
Mode
1
Wait for VDD、DVDD supply power up
Power-Down
2
I2S + Data Path Configuration
Stand-By
3.1
Enable system (SYSCTRL.PWDN = 0)
3.2
3.3
Bias, OSC, PLL active
Waiting for PLL locked
Enable Boost and amplifier (SYSCTRL.AMPPD =0)
Boost and Amplifier boot up
wait SYSST.SWS =1
Release Hard-Mute
Data Path active
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Configuring
4.2
5
Operating
en
4.1
Power up sequence considering I2S, I2C timing shows as below:
2
3
4
5
＞= 0 ms
VBAT
6
7
8
9
10
7
8
9
10
fid
1
on
DVDD
＞100 μs
RSTN
＞1 ms
cC
I2S
I2S Clock Valid
＞1 ms
I2C
Chip Configuration
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Power down sequence considering I2S, I2C timing shows as below:
1
I2C
I2S
2
3
4
5
6
Chip Configuration
＞0 ms
I2S Clock Valid
＞0 ms
RSTN
100 μs
DVDD
＞0 ms
VBAT
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
SOFTWARE RESET
Writing 0x55AA to register ID (0x00) via I2C interface will reset the device internal circuits and all configuration
registers.
DIGITAL AUDIO INTERFACE
BCK
WCK
DATAI
DATAO
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◼
◼
◼
◼
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Audio data is transferred between the host processor and the device via the Digital Audio Interface. The digital
audio interface is in full-duplex via 4 dedicated pins:
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Two-slot I2S and 4-slot TDM are supported in this device. The digital audio Interface on this device is slave only
and flexible with data width options, including 16, 20, 24, or 32 bits by configurable registers.
fid
Three modes of I2S are supported, including standard I2S mode, left-justified mode and right-justified data mode,
which can be configured via I2SCTRL.I2SMD. These modes are all MSB-first, with data width programmable
via I2SCTRL.I2SFS.
on
The word clock WCK is used to define the beginning of a frame. The frequency of this clock corresponds to the
sampling frequency. The device supports the following sample rates (fs): 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz and 96 kHz. It is selected via configurable register I2SCTRL.I2SSR.
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The bit clock BCK is used to sample the digital audio data across the digital audio interface. The number of bitclock pulses in a frame is defined as slot length. Three kind of slot length are supported (16/24/32) via
configurable register I2SCTRL.I2SBCK. The frequency of BCK can be calculated according to the following
equation:
BCK frequency = SampleRate * SlotLength * SlotNumber
SampleRate: Sample rate for this digital audio interface;
SlotLength: The length of one audio slot in unit of BCK clock;
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SlotNumber: How many slots supported in this audio interface. For example: 2-slot supported in I2S mode, 4slot supported in TDM mode.
The word selects and bit clock signals of the I2S input are the reference signals for the digital audio interface
and Phased Locked Loop (PLL).
The input audio data can be attenuated -6dB in this module, by setting bit I2SCTRL.INPLEV. The audio source
can be from left channel, right channel or the average of the left and right channel, which is controlled by
I2SCTRL.CHSEL.
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
Table 3 Supported I2S interface parameters
Data width
BCK frequency
Standard I2S
16b/20b/24b/32b
32fs /48fs /64fs
left-justified
16b/20b/24b/32b
32fs /48fs /64fs
right-justified
16b/20b/24b/32b
32fs /48fs /64fs
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Interface format(MSB first)
The output port DATAO, can be enabled or disabled via bit I2SCFG1.I2STXEN. The unused slots can be set
to Hi-z or zero, which is controlled by I2SCFG1.DOHZ.
…
RIGHT CHANNEL
LEFT CHANNEL
WCK
…
MSB
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…
…
BCK
DATA
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STANDARD I2S MODE
0
MSB
…
…
0
sample data of right channel
on
sample data of left channel
I2S Timing for Standard I2S Mode
When WCK=0 indicating the left channel data, and WCK=1 indicating the right channel data.
⚫
The MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the
word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock.
LEFT-JUSTIFIED MODE
BCK
DATA
…
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WCK
cC
⚫
LEFT CHANNEL
RIGHT CHANNEL
…
…
…
MSB
…
0
…
MSB
0
sample data of right channel
sample data of left channel
I2S Timing for Left-Justified Mode
⚫
When WCK=1 indicating the left channel data, and WCK=0 indicating the right channel data.
⚫
The MSB of the left channel is valid on the first rising edge of the bit clock after the rising edge of the word
clock. Similarly, the MSB of the right channel is valid on the first rising edge of the bit clock after the falling
edge of the word clock.
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19
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
RIGHT-JUSTIFIED MODE
…
LEFT CHANNEL
WCK
RIGHT CHANNEL
…
…
…
N-1
DATA
…
0
…
N-1
0
sample data of right channel
N=16/20/24/32
sample data of left channel
N=16/20/24/32
tia
I2S Timing for Right-Justified Mode
l
BCK
When WCK is high indicating the left channel data, and WCK=0 indicating the right channel data.
⚫
The LSB (bit 0) of the left channel is valid on the rising edge of the bit clock preceding the falling edge of
the word clock. Similarly, the LSB (bit 0) of the right channel is valid on the rising edge of the bit clock
preceding the rising edge of the word clock.
en
⚫
fid
TDM MODE
All of the three kind of bit synchronization modes (standard, left-justified, right-justified) are also supported in
TDM mode. The difference between TDM and I2S is the slot number supported. 4-slot is supported in TDM
mode, while 2-slot is supported in I2S mode
...
BCK
...
Slot0
...
...
...
...
...
Slot1
Slot2
Slot3
cC
DATA
...
on
WCK
TDM Timing
aw
ini
Note: The high level pulse width of WCK signal can be one slot time or one period of BCK.
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20
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
DIGITAL AUDIO PROCESSING
HAGC
en
Volume
Mute
fid
HDCC
tia
l
This device provides algorithm supporting for audio signal processing. The following functions are processed in
this module.
⚫ HDCC
⚫ Hardware AGC
⚫ Volume control
⚫ Mute
The signal processing flow in the DAP (Digital Audio Processor) is illustrated in the following figure.
Block Diagram of DAP
on
HDCC
This module performs hardware DC canceling for the input audio stream. It blocks DC components into analog
class D loop.
cC
HAGC
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ini
In the actual audio application, system output power tends to be more than rated power of speaker, such as
in the 10.25V power supply, as for 8ohms speaker, the maximum undistorted power is about
5.3W, but many speakers’ rated power is about 1W, if there is no output power control, the overload signal can
cause damage to the speaker. The audio power amplifier with hardware AGC can protect
the speaker effectively, When the output power is not exceeding the setting threshold, the hardware AGC
module will not attenuate the internal gain. Once the output power exceeds the setting threshold, the hardware
AGC module will reduce the internal gain of amplifier and restricts the output power under the setting threshold.
VOLUME CONTROL
The volume control function attenuates the audio signal at the end of digital audio processing. The range of
volume setting is from 0db to -96db with 0.5db/step
MUTE
This module performs mute control for the audio stream
DC-DC CONVERTER
This device using smart boost converter generates the amplifier supply rail, working in 1.6MHz. The DC-DC
converter can work in different mode via BSTCTRL2.BST_MODE:
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
⚫
Pass-through mode: the voltage of VDD is transparently passed to output of converter PVDD
⚫
Force boost mode: the output voltage is boosted to the programmed output voltage
⚫
Smart boost 1 mode: the output voltage can be switch between VDD and programmed output voltage
according to the input audio level.
⚫
Smart boost 2 mode: the output voltage can be dynamically adjusted according to the amplifier output's
signal swing requirements in order to maximize efficiency.
Pass-through mode
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l
The internal boost circuit is not working; the voltage of VDD is passed to PVDD directly.
Force boost mode
en
The boost circuit is always working and converts the voltage of VDD to the programmed output voltage. The
output voltage is configured via BSTCTRL2.VOUT_VREFSET
Smart boost 1 mode
fid
Smart boost 1 mode can dynamically turn off the boost according to the amplifier output's signal swing
requirements in order to maximize efficiency.
Smart boost 2 mode
cC
on
The boost circuits working dynamically according to the input audio level. When the level of input audio signal
is below the setting threshold, the boost circuit will be deactivated. Till the level of input audio signal raised up
and above the threshold, the boost circuit starts to work and boost the amplifier supply rail to the voltage fit the
requirement of output signal before the audio stream arriving at amplifier power stage.
Audio Signal
Input
Tdeglitch
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PVDD
VBAT
Audio Signal
Output
Tpath_delay
Boost Circuit Behavior in Smart Boost 2 Mode
PROTECTION MECHANISMS
Over Voltage Protection (OVP)
The boost circuit has integrated the over voltage protection control loop. When the output voltage PVDD is above
the threshold, the boost circuits will stop working, until the voltage of PVDD going down and under the normal
fixed working voltage.
Over Temperature Protection (OTP)
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
The device has automatic temperature protection mechanism which prevents heat damage to the chip. It is
triggered when the junction temperature is larger than the preset temperature high threshold (default = 160°C).
When it happens, the output stages will be disabled. When the junction temperature drops below the preset
temperature low threshold (less than 130°C), the output stages will start to operate normally again
Over Current (short) Protection (OCP)
l
The short circuit protection function is triggered when VOP/VON is short to PVDD/GND or VOP is short to VON,
the output stages will be shut down to prevent damage to itself. When the fault condition is disappeared, the
output stages of device will restart.
tia
Under Voltage Detection (UVL)
en
The interrupt bit SYSINT.UVLI will be set to 1 when under voltage occurs, which will be cleared by a read
operation of SYSINT register. Usually the SYSINT.UVLI bit can be used to check whether an unexpected undervoltage event has taken place.
BATTERY VOLTAGE MONITORING
fid
The device monitors the voltage on the VDD pin, which is most commonly the battery for the system. The
battery voltage level is available via bits VBAT_DET in the Battery Supply Voltage register VDD. Status bits
BAT_DET can be used to calculate the battery voltage. The battery voltage level VDD is:
𝑉𝐵𝐴𝑇_𝐷𝐸𝑇
× 6.025𝑉
210 − 1
For example, if VBAT_DET = 1001100011, the battery voltage level VDD is equal to 3.6V.
on
𝑉𝐵𝐴𝑇 =
PVDD VOLTAGE MONITORING
cC
The device monitors the voltage on the PVDD pin, which is most commonly the PVDD voltage level for the
system. The PVDD pin voltage level is available via bits PVDD_DET in the Power Supply Voltage monitor
register PVDD. Status bits PVDD_DET can be used to calculate the PVDD voltage. The PVDD voltage level
VPVDD is:
𝑃𝑉𝐷𝐷_𝐷𝐸𝑇
× 12.05𝑉
210 − 1
For example, if PVDD_DET = 1001100011, the PVDD voltage level VPVDD is equal to 7.2V.
aw
ini
𝑉𝑃𝑉𝐷𝐷 =
DIE TEMPERATURE MONITORING
The device monitors the die temperature and the result is available via bits TEMP_DET in the Temperature
register TEMP. The TEMP_DET is a two’s complement value. For example, if TEMP_DET = 00011001, the die
temperature is 25℃.
AMPLIFIER TRANSFER FUNCTION
The transfer function from the input to the amplifier PWM output (when no gain and attenuation is applied in
digital signal domain) is:
𝑉𝑜 = 𝐴𝑀𝑃_𝑁𝑂𝑅𝑀_𝑉 × 𝐷𝑖𝑛
Din: the level of input signal with a range from -1 to +1
AMP_NORM_V: the equivalent amplifier output voltage when Din is 1. In receiver mode the AMP_NORM_V is
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
5V, in speaker mode it’s 16V.
RECEIVER MODE
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ini
cC
on
fid
en
tia
l
The device built-in Receiver mode is easy to realize the Speaker and Receiver combo applications, it saves the
system cost and board space. If the receiver magnification is one times, the noise floor will be 12μV. Speaker
and Receiver combo applications can be realized without changing any hardware.
When the device is set to receiver mode, the power supply of Class D driver stage is from VDD directly without
boost.
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24
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
I2C INTERFACE
This device supports the I²C serial bus and data transmission protocol in fast mode at 400 kHz. This device
operates as a slave on the I²C bus. Connections to the bus are made via the open-drain I/O pins SCL and SDA.
The pull-up resistor can be selected in the range of 1k~10kΩ and the typical value is 4.7kΩ. This device can
support different high level (1.8V~3.3V) of this I2C interface.
DEVICE ADDRESS
AD1
0
0
0
1
1
0
Address(7-bit)
0x34
0x35
fid
AD2
en
Table 4 Address Selection
tia
l
The I2C device address (7-bit) can be set using the AD pin according to the following table: The AD1, AD2 pin
configures the two LSB bits of the following 7-bit binary address A6-A0 of 01101xx. The permitted I2C
addresses are 0x34(7-bit) through 0x37(7-bit).
1
1
0x37
on
DATA VALIDATION
0x36
cC
When SCL is high level, SDA level must be constant. SDA can be changed only when SCL is low level.
SDA
SCL
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Data Line
Stable
Data Valid
Change
of Data
Allowed
Data Validation Diagram
I2C START/STOP
I2C start: SDA changes form high level to low level when SCL is high level.
I2C stop: SDA changes form low level to high level when SCL is high level.
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
SDA
SCL
S/Sr
P
P: STOP condition
tia
l
S: START condition
Sr: START Repeated condition
I2C Start/Stop Condition Timing
en
ACK (ACKNOWLEDGEMENT)
fid
ACK means the successful transfer of I2C bus data. After master sends 8bits data, SDA must be released; SDA
is pulled to GND by slave device when slave acknowledges.
When master reads, slave device sends 8bit data, releases the SDA and waits for ACK from master. If ACK is
send and I2C stop is not send by master, slave device sends the next data. If ACK is not send by master, slave
device stops to send data and waits for I 2C stop.
on
Data Output
by Transmiter
Not Acknowledge（NACK）
SCL From
Master
cC
Data Output
by Receiver
1
Acknowledge（ACK）
2
8
9
Clock Pulse for
Acknowledgement
START
condition
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I2C ACK Timing
WRITE CYCLE
One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock
(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the
SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New
data should be sent during the low SCL state. This protocol allows a single data line to transfer both
command/control information and data using the synchronous serial clock.
Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a
Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is
transferred with the most significant bit first. After each byte, an Acknowledge signal must follow.
In a write process, the following steps should be followed:
a)
Master device generates START condition. The “START” signal is generated by lowering the SDA
signal while the SCL signal is high.
b)
Master device sends slave address (7-bit) and the data direction bit (r/w = 0).
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
Slave device sends acknowledge signal if the slave address is correct.
d)
Master sends control register address (8-bit)
e)
Slave sends acknowledge signal
f)
Master sends high data byte of 16-bit data to be written to the addressed register
g)
Slave sends acknowledge signal
h)
Master sends low data byte of 16-bit data to be written to the addressed register
i)
Slave sends acknowledge signal
j)
If master will send further 16-bit data bytes, the control register address will be incremented by one
after acknowledge signal of step g (repeat step f to g)
k)
Master generates STOP condition to indicate write cycle end
A6
START
A5
A4
A3
…
DEVICE ADDRESS
A1
A0 R/W ACK A7
A6
…
…
A3
A2 A1
A0 ACK D7
…
D2
D1
D0 ACK D7 D6
WRITE DATAH
REGISTER ADDRESS
…
…
D2
D1 D0 NACK
WRITE DATAL
STOP
fid
SDA
en
…
…
SCL
tia
l
c)
I2C Write Byte Cycle
on
READ CYCLE
In a read cycle, the following steps should be followed:
Master device generates START condition
b)
Master device sends slave address (7-bit) and the data direction bit (r/w = 0).
c)
Slave device sends acknowledge signal if the slave address is correct.
d)
Master sends control register address (8-bit)
e)
Slave sends acknowledge signal
f)
Master generates STOP condition followed with START condition or REPEAT START condition
g)
Master device sends slave address (7-bit) and the data direction bit (r/w = 1).
h)
Slave device sends acknowledge signal if the slave address is correct.
i)
Slave sends read high data byte of 16-bit data from addressed register.
j)
Master sends acknowledge signal.
k)
Slave sends read low data byte of 16-bit data from addressed register.
l)
If the master device sends acknowledge signal, the slave device will increase the control register
address by one, then send the next 16-bit data from the new addressed register.
aw
ini
cC
a)
m) If the master device generates STOP condition, the read cycle is ended.
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Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
…
…
A6
START
A5
A4
A3
…
A1
A0 R/W ACK A7
DEVICE ADDRESS
A6
RS
A5
A4
A3
…
A1
A0 R/W ACK D7
A4
A3
A0 ACK
…
…
D2
D1
D0 ACK D7
…
A0 R/W ACK D7
…
D1 D0 NACK
STOP
…
D2
D1
D0 ACK D7
READ DATAH
DEVICE ADDRESS
D2
READ DATAL
…
A1
…
D6
D6
en
STOP START
A5
A1
READ DATAH
DEVI CE ADDRESS
A6
A2
…
…
Separated
read/write
transaction
A3
REGISTER ADDRESS
…
Using
repeat
start
…
A6
l
SDA
tia
SCL
…
D2
D1 D0 NACK
READ DATAL
STOP
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ini
cC
on
fid
I2C Read Byte Cycle
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28
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
REGISTER MAP
REGISTER DESCRIPTION
t
n
REGISTER LIST
ADDR
NAME
R/W
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
RO
0x01 SYSST
RO
OVP2S
UVLS
ADPS
BSTOCS
OVPS
BSTS
SWS
CLIPS
0x02 SYSINT
RC
OVP2I
UVLI
ADPI
BSTOCI
OVPI
BSTI
SWI
CLIPI
0x03 SYSINTM
RW
OVP2M
UVLM
ADPM
BSTOCM
OVPM
BSTM
SWM
CLIPM
0x04 SYSCTRL
RW
INTMODE
INTN
RCV_MODE
0x05 SYSCTRL2
RW
RMSE
0x06 I2SCTRL
RW
INPLEV I2SRXEN
0x07 I2SCFG1
RW
I2S_TX_SLOTVLD
0x09 HAGCCFG1
RW
0x0a HAGCCFG2
RW
0x0b HAGCCFG3
RW
0x0c HAGCCFG4
RW
0x10 HAGCST
RO
0x12 VDD
RO
0x13 TEMP
RO
CHSEL
c
i
in
o
C
f
n
I2SMD
I2SFS
I2S_RX_SLOTVLD
Bit4
e
id
0x00 ID
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IDCODE
Bit5
CFSEL
Bit3
Bit2
Bit1
Bit0
NOCLKS
CLKS
OCDS
CLIP_PRES
OTHS
PLLS
NOCLKI
CLKI
OCDI
CLIP_PREI
OTHI
PLLI
NOCLKM
CLKM
OCDM
CLIP_PREM
OTHM
PLLM
I2SEN
WSINV
BCKINV
IPLL
AMPPD
PWDN
HAGCE
HDCCE
HMUTE
BST_IPEAK
I2SBCK
DRVSTREN
I2SSR
DOHZ
RVTH
w
a
l
ia
FSYNC_TYPE SLOT_NUM
AVTH
ATTH
RTTH
VOL
HOLDTH
BSTVOUT_ST
VBAT_DET
TEMP_DET
29
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
I2SCHS
I2STXEN
AW88298
May. 2022 V1.6
ADDR
NAME
R/W
0x14 PVDD
RO
0x60 BSTCTRL1
RW
0x61 BSTCTRL2
RW
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit2
PVDD_DET
BST_RTH
BST_MODE
BST_TDEG
VOUT_VREFSET
f
n
c
i
in
o
C
e
id
w
a
30
l
ia
BST_ATH
t
n
www.awinic.com
Bit3
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
Bit1
Bit0
AW88298
May. 2022 V1.6
DETAILED REGISTER DESCRIPTION
R/W
RO
UVLS
RO
13
ADPS
RO
12
11
10
Reserved
BSTOCS
OVPS
RO
RO
RO
9
BSTS
RO
8
SWS
RO
7
CLIPS
RO
6
5
Reserved
NOCLKS
RO
RO
4
CLKS
RO
3
2
1
OCDS
CLIP_PRES
OTHS
RO
RO
RO
0
PLLS
RO
(Address 02h)
Symbol
OVP2I
UVLI
ADPI
Reserved
BSTOCI
OVPI
BSTI
SWI
CLIPI
R/W
RC
RC
RC
RC
RC
RC
RC
RC
RC
aw
ini
SYSINT:
Bit
15
14
13
12
11
10
9
8
7
cC
14
Description
Boost OVP2 status indicator
VDD under voltage indicator
0: VDD > 2.8V
1: VDD < 2.8V
Boost Adaptive status.
0: transparent
1: boost
Not used
Boost over current indicator
Boost OVP status indicator
Boost start up finished.
0: not finished
1: finished
Amplifier switching status.
0: not switching
1: switching
Amplifier clipping status.
0: not clipping
1: clipping
Not used
The reference clock of PLL is not available
All internal clock are stable
CLKS = PLLS & ～IDP
Over current status in amplifier
Amplifier clipping pre status.
Die Temperature is higher than 160degrees
PLL locked status.
0: unlocked
1: locked
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l
SYSST: (Address 01h)
Bit
Symbol
15
OVP2S
tia
RO
IDCODE
en
15:0
Description
Chip ID (1852h) will be returned after read.
All configuration registers will be reset to default value after 0x55aa is
written
fid
R/W
on
ID: (Address 00h)
Bit
Symbol
Description
Interrupt indicator for OVP2S.
Interrupt indicator for Power On and UVLS
Interrupt indicator for ADPS
Not used
Interrupt indicator for BSTOCS.
Interrupt indicator for OVPS.
Interrupt indicator for BSTS.
Interrupt indicator for SWS.
Interrupt indicator for CLIPS.
31
Default
0x1852
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default
0
0
0
0
0
0
0
0
0
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
R/W
RW
INTMODE
RW
8
INTN
RW
7
RCV_MODE
RW
6
I2SEN
RW
5
WSINV
RW
4
BCKINV
RW
3
IPLL
RW
Description
Reserved
Interrupt pad INTN output mode selection
0: Open-drain
1: Push Pull
Interrupt pad INTN pin-source selection
0: SYSINT
1: SYSST
Receiver mode enable, active "1".
0: Speaker mode
1: Receiver mode
Disable/Enable whole I2S interface module
0: disable
1: enable
I2S Left/Right channel switch
0: No switch
1: Left/Right switch
I2S bit clock invert control
0: not invert
1: inverted
PLL reference clock selection
0: bit clock
1: word selection signal
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9
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32
l
SYSCTRL: (Address 04h)
Bit
Symbol
15:10 Reserved
Description
Interrupt mask for OVP2I
Interrupt mask for UVLI.
Interrupt mask for ADPI
Not used
Interrupt mask for BSTOCI.
Interrupt mask for OVPI
Interrupt mask for BSTI.
Interrupt indicator for SWI.
Interrupt indicator for CLIPI.
Not used
Interrupt mask for NOCLKI.
Interrupt mask for CLKI.
Interrupt mask for OCDI.
Interrupt mask for CLIP_PREI.
Interrupt mask for OTHI.
Interrupt mask for PLLI.
tia
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
en
SYSINTM: (Address 03h)
Bit
Symbol
15
OVP2M
14
UVLM
13
ADPM
12
Reserved
11
BSTOCM
10
OVPM
9
BSTM
8
SWM
7
CLIPM
6
Reserved
5
NOCLKM
4
CLKM
3
OCDM
2
CLIP_PREM
1
OTHM
0
PLLM
Not used
Interrupt indicator for NOCLKS.
Interrupt indicator for CLKS.
Interrupt indicator for OCDS
Interrupt indicator for CLIP_PRES
Interrupt indicator for OTHS.
Interrupt indicator for PLLS.
fid
RC
RC
RC
RC
RC
RC
RC
on
Reserved
NOCLKI
CLKI
OCDI
CLIP_PREI
OTHI
PLLI
cC
6
5
4
3
2
1
0
Default
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
Default
0x10
0
0
0
0
0
0
0
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
AMPPD
RW
0
PWDN
RW
SYSCTRL2: (Address 05h)
Bit
Symbol
15:8 Reserved
R/W
RW
RMSE
RW
6
HAGCE
RW
5
HDCCE
RW
4
HMUTE
RW
0
1
1
Default
0
0
0
1
1
on
7
Description
Not used
Enable of RMS HAGC
0:disable
1:enable
Disable/Enable Peak AGC
0:disable
1:enable
Enable/Disable Hardware DC Canceling module
0: disable
1: enable
Enable/Disable Hardware mute module
0: disable
1: enable
l
1
Not used
Amplifier power down control bit, Power Down until system
configuration finished
0: normal working
1: power down
System power down control bit
0: System normal working
1: All circuits will enter power down mode
tia
RW
en
Reserved
fid
2
cC
BST_IPEAK
RW
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ini
3:0
Boost peak current limiter threshold
0000: 1.5A
0001: 1.75A
0010: 2.0A
0011: 2.25A
0100: 2.5A
0101: 2.75A
0110: 3.0A
0111: 3.25A
1000: 3.5A
1001: 3.75A
1010: 4A
1011: 4.25A
Others: Reserved
I2SCTRL: (Address 06h)
Bit
Symbol
15:14 Reserved
R/W
RW
13
INPLEV
RW
12
I2SRXEN
RW
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Description
Not used
Input level selection bit, when it is set to 1, all input signal will be
attenuated at first
0: not attenuated
1: attenuated by -6dB
Disable/Enable I2S receiver module
0: disable
1: enable
33
8
Default
0
0
1
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
3:0
I2SBCK
I2SSR
0
RW
I2S LSB justified mode data width selection
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits
RW
I2S BCK mode
00: 32*fs(16*2)
01: 48*fs(24*2)
10: 64*fs(32*2)
11: Reserved
RW
I2S interface sample rate configuration
0000: 8 kHz
0001: 11.025kHz
0010: 12 kHz
0011: 16 kHz
0100: 22.05kHz
0101: 24 kHz
0110: 32 kHz
0111: 44.1 kHz
1000: 48 kHz
1001: 96 KHz
1010: 192KHz
Others: Reserved
R/W
RW
13:12
RW
11:8
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I2SCFG1: (Address 07h)
Bit
Symbol
15:14 Reserved
I2S_TX_SLOTVLD
I2S_RX_SLOTVLD
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RW
I2S interface mode
00: Philip standard I2S (default)
01: MSB justified
10: LSB justified
11: Reserved
en
5:4
I2SFS
1
3
2
fid
7:6
I2SMD
RW
on
9:8
CHSEL
8
cC
11:10
Left/right channel selection for I2S input
00: reserved
01: left
10: right
11: mono, (L+R)/2
RW
Description
Not used
TX slot selection, data will be sent to one of the four slots in TDM
mode.
00: Slot 0
01: Slot 1
10: Slot 2
11: Slot 3
RX slots selection, two slots will be chosen as active slots in TDM mode.
Valid settings are as follows
0011: Slots 0 and 1
0101: Slots 0 and 2
1001: Slots 0 and 3
0110: Slots 1 and 2
1010: Slots 1 and 3
1100: Slots 2 and 3
Others: Reserved
34
Default
0
0
3
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
CFSEL
RW
5
DRVSTREN
RW
4
DOHZ
RW
3
FSYNC_TYPE
RW
2
SLOT_NUM
RW
1
I2SCHS
RW
0
I2STXEN
RW
0
I2S_DATAO PAD driving strength setting
0: 2mA
1: 8mA
Unused channel data control
0: All Channels available
1: Hi-Z
Audio Frame synchronization signal (WCK) pulse width configuration
0: one slot width
1: one BCK clock cycle
Slot number selection, the 2-slot mode is compatible with I2S, and 4slot mode is for TDM mode (max 4 slots support).
0: 2 slots
1: 4 slots
I2S TX Channel output selection
0: Left channel
1: Right channel
Disable/Enable I2S transmitter module
0: disable
1: enable
1
1
AVTH
RW
HAGCCFG2: (Address 0ah)
Bit
Symbol
R/W
ATTH
RW
HAGCCFG3: (Address 0bh)
Bit
Symbol
R/W
15:0
RTTH
RW
HAGCCFG4: (Address 0ch)
Bit
Symbol
R/W
15:8
VOL
RW
7:0
HOLDTH
RW
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en
fid
0
0
0
Default
0x39
Description
Attack time threshold in unit of 20.8μs
0: reserved
n: gain decreased 0.5db per n*20.8us
Default
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15:0
0
Description
Release Amplitude threshold, in percent of signal full scale
Attack Amplitude threshold, in percent of signal full scale
RMSE = 0 : P0= ((i/256*Gain)**2)/8/2
RMSE = 1 : P0=(i/256)*(Gain**2)/8
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7:0
on
HAGCCFG1: (Address 09h)
Bit
Symbol
R/W
15:8 RVTH
RW
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7:6
I2S legacy path output data selection
00: HAGC data
Others: Reserved
0x40
0x0030
Description
Release time threshold in unit of 20.8μs
0: reserved
n: gain decreased 0.5db per n*20.8μs
Default
Description
Volume control, from 0 to -96dB
[3:0] : in unit of -0.5dB
[7:4] : in unit of -6dB
Attack time threshold in unit of about 1.33ms
0: reserved
n: attack counter holding at least n*1.33ms
Default
35
0x01E0
0
0x64
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
VBAT_DET
TEMP: (Address 13h)
Bit
Symbol
15:10 Reserved
9:0
TEMP_DET
PVDD: (Address 14h)
Bit
Symbol
15:10 Reserved
RO
R/W
RO
PVDD_DET
RO
BSTCTRL1: (Address 60h)
Bit
Symbol
15:14 Reserved
R/W
RW
13:8
BST_RTH
RW
7:6
Reserved
RW
5:0
BST_ATH
RW
BSTCTRL2: (Address 61h)
Bit
Symbol
15
Reserved
R/W
RW
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Default
0
0
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R/W
RO
Description
Not used
Detected Voltage of battery, and the fullrange is 6.025V
V_BATS=(VDD)/1023×6.025
Description
Not used
Detected Die Temperature (Two's Complement), typical values are as
follows.
0x3D8: -40degree
0x00: 0 degree
0x01: 1 degree
0x19: 25 degree
0x37: 55 degree
Please convert it to decimal number please.
Description
Not used
Detected Voltage of PVDD, and the full range is 12.05V
PVDD=(PVDD_DET)/1023×12.05
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9:0
RO
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9:0
R/W
RO
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VDD: (Address 12h)
Bit
Symbol
15:10 Reserved
RO
fid
BSTVOUT_ST
Description
Not used
Actual setting of boost output voltage (125mV/Step)
001111: 5.0V
…...
111001: 10.25V
Others: Reserved
Default
0
0x263
Default
0
0x019
on
5:0
R/W
RO
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HAGCST: (Address 10h)
Bit
Symbol
15:6 Reserved
Default
0
0x263
Description
Not used
Smart boost release threshold setting, When signal is below the
threshold, the voltage of VBST will not be raised up higher than VDD in
smart boost mode
Release threshold = BST_RTH * 1/64 Full-scale
Not used
Smart boost attack threshold setting. When signal is above over the
threshold, the voltage of VBST will be raised up higher than VDD in
smart boost mode
Attack threshold = BST_ATH * 1/64 Full-scale
Default
0
Description
Default
0
Not used
36
4
0
2
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
14:12
11
BST_MODE
RW
Reserved
RW
BOOST mode selection, Initialize to 6.
000: Transparent Mode
001: Force Boost Mode
011: Reserved
101: Smart Boost 1 Mode
Others: Smart Boost 2 Mode
Not used
0x6
0
BST_TDEG
RW
7:6
Reserved
RW
Not Used
RW
BOOST max output voltage control bits (125mV/Step)
001111: 5.0V
…...
111001: 10.25V
Others: Reserved
en
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VOUT_VREFSET
0x6
1
0x33
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5:0
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10:8
Smart Boost 1 small signal level detection deglitch time
000: 0.33 ms
001: 1.40 ms
010: 5.60 ms
011: 21.30 ms
100: 44 ms
101: 88 ms
110: 352 ms
111: 1.4 s
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37
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
APPLICATION INFORMATION
EXTERNAL COMPONENTS
BOOST INDUCTOR SELECTION
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Selecting inductor needs to consider Inductance, size, magnetic shielding, saturation current and temperature
current.
a) Inductance
Inductance value is limited by the boost converter's internal loop compensation. In order to ensure phase margin
sufficient under all operating conditions, recommended 1μH inductor.
b) Size
For a certain value of inductor, the smaller the size, the greater the parasitic series resistance of the inductor
DCR, the higher the loss, corresponds to the lower efficiency.
c) Magnetic shielding
Magnetic shielding can effectively prevent the inductance of the electromagnetic radiation interference. It is
much better to choose inductance with magnetic shielding in the application of EMI sensitive environment.
d) Saturation current and temperature rise of current
Inductor saturation current and temperature rise current value are important basis for selecting the inductor. As
the inductor current increases, on the one hand, since the magnetic core begins to saturate, inductance value
will decline; on the other hand, the inductor's parasitic resistance inductance and magnetic core loss can lead
to temperature rise. In general, the current value is defined as the saturation current ISAT when the inductance
value drops to 70%; the current value is defined as temperature rise current IRMS when inductance temperature
rise 40℃.
For particular applications, need to calculate the maximum IL_PEAK and IL_RMS, which is a basis of selecting the
inductor. When VDD = 4.2V, PVDD=9.5V, RL = 8Ω，amplifier RDSON = 300mΩ, when THD = 1% (the maximum
power without distortion), the output power is calculated as follows:
2
2
𝑅𝐿
8
(𝑉𝑜𝑢𝑡 ×
)
(9.5
×
)
𝑅𝐿 + 𝑅𝐷𝑆𝑂𝑁
8 + 0.3 = 5.24𝑊
𝑃𝑜𝑢𝑡 =
=
2 × 𝑅𝐿
2×8
In such a large output power, the overall efficiency of the power amplifier is typically 70%, in order to calculate
the maximum average current IMAX_AVG_VDD and maximum peak current IMAX_PEAK_VDD drawn from VDD:
𝑃𝑜𝑢𝑡
5.24
𝐼𝑀𝐴𝑋𝐴𝑉𝐺
=
=
= 1.78𝐴
𝑉𝐷𝐷
𝑉𝑖𝑛 × 𝜂 4.2 × 0.7
𝐼𝑀𝐴𝑋_𝑃𝐸𝐴𝐾_𝑉𝐷𝐷 = 2 × 𝐼𝑀𝐴𝑋_𝐴𝑉𝐺_𝑉𝐷𝐷 = 2 × 1.78𝐴 = 3.6𝐴
If inductor DCR is 50mΩ, the inductor power loss at this time is:
2
𝑃𝐷𝐶𝑅_𝐿𝑂𝑆𝑆 = 1.5 × 𝐼𝑀𝐴𝑋_𝐴𝑉𝐺_𝑉𝐷𝐷
× DCR = 1.5 × 1.782 × 0.05𝑊 = 240𝑚𝑊
Wherein the coefficient 1.5 is the square of the ratio of the sine wave current RMS value and average value
(there is no consideration of the impact of the inductor ripple, the actual DCR loss will be even greater). If the
loss which is resulting from DCR is less than 1% at maximum efficiency (POUT = 2.5W, η = 80%), then:
𝐼𝐴𝑉𝐺_𝑉𝐷𝐷 =
DCR =
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𝑃𝑜𝑢𝑡
2.5
=
= 0.75𝐴
𝑉𝑖𝑛 × 𝜂 4.2 × 0.8
𝑃𝐷𝐶𝑅_𝐿𝑂𝑆𝑆
𝑃𝑜𝑢𝑡
0.01 × 2.5
≤ 1% ×
=
Ω = 37𝑚Ω
2
2
1.5 × 𝐼𝑀𝐴𝑋_𝐴𝑉𝐺_𝑉𝐷𝐷
1.5 × 𝐼𝐴𝑉𝐺_𝑉𝐷𝐷 × 𝜂 1.5 × 0.752 × 0.8
38
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
According to the working principle of the Boost, we can calculate the size of the inductor current ripple Δ IL:
∆𝐼𝐿 =
𝑉𝑖𝑛 × (𝑉𝑜𝑢𝑡 − 𝑉𝑖𝑛 )
4.2 × (9.5 − 4.2)
=
= 1.46𝐴
𝑉𝑜𝑢𝑡 × 𝑓 × 𝐿
9.5 × 1.6 × 106 × 1 × 10−6
Thus, the maximum peak inductor current IL_PEAK and maximum effective inductor current IL_RMS is:
2
𝐼𝐿_𝑅𝑀𝑆 = √𝐼𝑀𝐴𝑋_𝑃𝐸𝐴𝐾_𝑉𝐷𝐷
+
2
= 3.6 +
1.46
𝐴 = 4.33𝐴
2
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∆𝐼𝐿
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𝐼𝐿_𝑃𝐸𝐴𝐾 = 𝐼𝑀𝐴𝑋_𝑃𝐸𝐴𝐾_𝑉𝐷𝐷 +
∆𝐼𝐿2
1.462
= √3.62 +
𝐴 = 3.62𝐴
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From the above calculation results:
1) For typical DCR about 50mΩ inductance, the efficiency loss caused by around1.5%;
2) In practice, the maximum output power of the amplifier is likely to reach 5.6W in an instant, so the selected
inductor saturation current ISAT requires more than the maximum inductor peak current IL_PEAK;
3) In some cases, if the IL_PEAK calculated according to the above method is greater than the set of input inductor
current limit value IPEAK, shows the power amplifier is restricted by inductance input current limit, the actual
maximum output power is less than the calculated value, the measured value shall prevail, and ISAT need
greater than the set current limiting value IPEAK, and cannot be less than 3.5A;
4) Take PVDD = 9.5V for example, under different conditions, the typical method of selecting I SAT in the
following table:
PVDD
RL
IPEAK
Efficiency(η)
PO
IL_PEAK
(V)
(V)
(Ω)
(A)
(%)
(W)
(A)
4.2
9.5
8
4.2
9.5
6
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VDD
Inductor
saturation
current ISAT
minimum
value (A)
4.25
74
5.2
4.33
4.2
4.25
69
5.4
4.5
4.2
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5) As the result of the action of AGC，amplifier will not work long hours at maximum power without distortion,
the actual average inductor current is far less than the maximum inductor current effective I L_RMS, so when
selecting the inductor, the inductor temperature rise current is not usually a limiting factor;
6) Inductor Selection example: the inductor package size is 252012, inductance value is 1μH, DCR Typical
value is 48mΩ, the typical saturation current ISAT is 4.2A, the typical temperature rise current IRMS is 3.4A,
suitable for VDD=3.6V, PVDD=9.5V, speaker impedance RL=8Ω, inductor input current limit IPEAK= 4.25A. If
you choose ISAT or IRMS of the inductance is too small, it is possible to cause the chip don’t work properly, or
the temperature of the inductance is too high.
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Inductance value
size
DCR
（Ω）
（A）
IRMS
（A）
1μH
2.5×2.0×1.2mm
0.054
4.2
3.4
39
ISAT
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
BOOST CAPACITOR SELECTION
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Boost output capacitor is usually within the range 0.1μF~47μF. It needs to use Class II type (EIA) multilayer
ceramic capacitors (MLCC). Its internal dielectric is ferroelectric material (typically BaTiO 3), a high the dielectric
constant in order to achieve smaller size, but at the same Class II type (EIA) multilayer ceramic capacitors has
poor temperature stability and voltage stability as compared to the Class I type (EIA) capacitance. Capacitor is
selected based on the requirements of temperature stability and voltage stability, considering the capacitance
material, capacitor voltage, and capacitor size and capacitance values.
A) temperature stability
Class II capacitance have different temperature stability in different materials, usually choose X5R type in order
to ensure enough temperature stability, and X7R type capacitance has better properties, the price is relatively
more expensive; X5R capacitance change within ± 15% in temperature range of 55°C to 85°C, X7R capacitance
change within ±15% in temperature range of -55°C~125°C. The Boost output capacitance of DEVICE
recommends X5R ceramic capacitors.
B) Voltage Stability
Class II type capacitor has poor voltage stability Capacitance values falling fast along with the DC bias voltage
applied across the capacitor increasing. The rate of decline is related to capacitance material, capacitors rated
voltage, capacitance volume. Take TDK C series X5R for example, its pressure voltage value is 16V or 25V; the
package size is 0805, 1206 or 0603, the capacitance value is 10μF. The capacitor’s voltage stability of different
types of capacitor is as shown below:
Capacitor Variation v.s. DC Voltage
on
10
0
-10
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-30
-40
-50
-60
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C-Change (%)
-20
0603,X5R,16V,10uF,0.80mm
0603,X5R,25V,10uF,0.80mm
0805,X5R,16V,10uF,0.85mm
0805,X5R,16V,10uF,1.25mm
0805,X5R,25V,10uF,0.85mm
0805,X5R,25V,10uF,1.25mm
1206,X5R,16V,10uF,0.85mm
1206,X5R,16V,10uF,1.60mm
1206,X5R,25V,10uF,0.85mm
1206,X5R,25V,10uF,1.60mm
-70
-80
-90
-100
0
5
10
15
20
25
VDC (V)
Different types of capacitive voltage stability
It can be found that the rate of capacitance capacity value descent becomes slow along with "large capacitor
size, capacitance pressure voltage rise”. The larger the package size, the better voltage stability. The higher the
height, the better voltage stability with the same length and width of the capacitance. Voltage stability of smaller
package size (0603) capacitor change affected by the pressure value is very small.
In typical applications, it is necessary to ensure the residual capacitance should ≥4μF when PVDD=10.25V.
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40
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
Take the following capacitances as the Boost of the output capacitor for example:
value
material
size (mm3)
rated
voltage
(V)
quantity
value@10.25V
10μF
X5R
1.60×0.80×0.40
(0603)
16
3
4.5μF
10μF
X5R
2.00×1.25×0.50
(0805)
25
2
4.2μF
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As for the different manufacturers’ capacitors, it’s important to determine the type and quantity of the capacitors
through the capacitor voltage stability data provided by the manufacturer.
SUPPLY DECOUPLING CAPACITOR
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The device is a high-performance audio amplifier that requires adequate power supply decoupling. Place a low
equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1μF. This choice of capacitor and placement
helps with higher frequency transients, spikes, or digital hash on the line. Additionally, placing this decoupling
capacitor close to the DEVICE is important, as any parasitic resistance or inductance between the device and
the capacitor causes efficiency loss. In addition to the 0.1μF ceramic capacitor, place a 10μF capacitor on the
VDD supply trace. This larger capacitor acts as a charge reservoir, providing energy faster than the board supply,
thus helping to prevent any droop in the supply voltage.
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41
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
PACKAGE DESCRIPTION
3.50 BSC
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PIN1 Corner
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3.50 BSC
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TOP VIEW
on
0.00~0.05
SIDE VIEW
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0.203 REF
2.30±0.10
2.00 BSC
7
12
13
2.00 BSC
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6
2.30±0.10
0.75±0.05
SYMM
0.40 BSC
24x(0.20±0.05)
18
1
24
0.40 BSC
19
SYMM
24x(0.30±0.10)
BOTTOM VIEW
Dimensions are all in Millimeters
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42
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
LAND PATTERN DATA
SYMM
0.400 BSC
24
19
18
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1
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0.400 BSC
2.300
en
SYMM
3.700
24x 0.400
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2.300
24x 0.200
on
6
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7
13
12
3.700
SOLDER MASK
OPENING
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0.05 MAX
All AROUND
0.05 MIN
All AROUND
METAL
SOLDER MASK
OPENING
METAL UNDE R
SOLDER MASK
SOLDER MASK DEFINED
NON SOLDER MASK DEFINED
Dimensions are all in millimeters
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43
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
TAPE AND REEL INFORMATION
TAPE DIMENSIONS
REEL DIMENSIONS
P1
P0
P2
K0
W
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B0
D1
A0
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Cavity
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A0：Dimension designed to accommodate the component width
B0：Dimension designed to accommodate the component length
K0：Dimension designed to accommodate the component thickness
W：Overall width of the carrier tape
P0：Pitch between successive cavity centers and sprocket hole
P1：Pitch between successive cavity centers
P2：Pitch between sprocket hole
D0：Reel width
D1：Reel diameter
on
D0
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QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
Q3
Q4
Q3
Q4
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Q1
User Direction of Feed
Pocket Quadrants
All dimensions are nominal
D1
(mm)
330
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D0
A0
(mm) (mm)
12.4
3.8
B0
(mm)
K0
(mm)
P0
(mm)
P1
(mm)
P2
(mm)
W
(mm)
Pin1 Quadrant
3.8
1.1
2
8
4
12
Q1
44
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
REVISION HISTORY
Date
Change Record
V1.0
May. 2020
Officially Released
V1.1
July. 2020
Fix Typos
V1.2
Oct. 2020
Modify Power On/Power Off timing sequence
V1.3
Mar.2021
Update Characteristics
V1.4
Jun.2021
Update Characteristics
V1.5
Oct.2021
Update 4Ω application
V1.6
May.2022
Officially Released (Universal version)
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Version
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45
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW88298
May. 2022 V1.6
DISCLAIMER
Information in this document is believed to be accurate and reliable. However, Shanghai AWINIC Technology
Co., Ltd (AWINIC Technology) does not give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability for the consequences of use of such
information.
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AWINIC Technology reserves the right to make changes to information published in this document, including
without limitation specifications and product descriptions, at any time and without notice. Customers shall
obtain the latest relevant information before placing orders and shall verify that such information is current and
complete. This document supersedes and replaces all information supplied prior to the publication hereof.
en
AWINIC Technology products are not designed, authorized or warranted to be suitable for use in medical,
military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an AWINIC
Technology product can reasonably be expected to result in personal injury, death or severe property or
environmental damage. AWINIC Technology accepts no liability for inclusion and/or use of AWINIC Technology
products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own
risk.
on
fid
Applications that are described herein for any of these products are for illustrative purposes only. AWINIC
Technology makes no representation or warranty that such applications will be suitable for the specified use
without further testing or modification.
All products are sold subject to the general terms and conditions of commercial sale supplied at the time of
order acknowledgement.
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Nothing in this document may be interpreted or construed as an offer to sell products that is open for
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