AW2026
September 2018 V1.3
3-Channel Breathing LED Driver with IIC Interface
GENERAL DESCRIPTION
AW2026 is a three channels constant current LED
driver. The max output current is 4-level selectable
among 3mA, 6mA, 12mA and 25.5mA. Each LED is
256 current levels configurable so as to achieve
256*256*256 color mixing. The 256-level dimming
and 12 bits PWM resolution create fine and smooth
dimming effect even in low brightness.
ti
a
256 current levels setting for each LED
Supports 256*256*256 color-mixing
256-level PWM dimming, 12-bit PWM resolution
Automatic breathing light with flexible pattern
configuration and running mode
three independent pattern controllers
pulses repeating, multiple colors alternative
multiple patterns running successively or
cyclically
400kHz fast I2C interface , 1.8V ~ 3.3V
Single power supply, 2.4V~5.5V
Low power consumption
AW2026 is available in a 1.5mm×1.5mm×0.45mm
DFN-8L package.
C
Less than 1μA in shut down mode
Less than 10μA in standby mode
1.5mm×1.5mm×0.45mm DFN-8L package
ic
The device requires only 2.4V~5.5V single power
supply. An I2C compatible interface in 400kHz fast
mode is provided, the device address is 64h.
o
In shut down mode, AW2026 turns off all internal
circuit and the consumption is less than 1μA. In
standby mode, I2C interface works and the
consumption is less than 10μA.
n
e
fi
d
4- level IMAX selections: 3/6/12/25.5mA
n
3-channel constant current LED drivers
l
FEATURES
a
w
in
TYPICAL APPLICATION CIRCUIT
VIO
VBAT
VBAT
4.7k
1uF
GND
LED1
MCU
LED2
SCL
SDA
LED3
SCL
SDA
AW2026
All the trademarks mentioned in the document are the property of their owners.
www.awinic.com.cn
1
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
PIN CONFIGURATION AND TOP MARK
AW2026 TOP
MARKING
AW2026 TOP VIEW
SDA
SCL
VBAT
8
7
6
5
ti
a
l
GND
A26
XXX
2
3
4
NC
LED3
LED2
LED1
A26 ---- AW2026
XXX ---- Manufacture trace code
n
1
fi
d
e
n
9
Exposed
Pad
o
PIN DEFINITION
NAME
1
NC
2
LED3
3
LED2
LED2 Cathode Driver, anode connected to VBAT
LED1
LED1 Cathode Driver, anode connected to VBAT
VBAT
Power Supply (2.4V-5.5V)
5
ic
4
DESCRIPTION
C
No.
Not connected
LED3 Cathode Driver, anode connected to VBAT
SCL
Serial Clock Input for I2C Interface
7
SDA
Serial Data I/O for I2C Interface
8
GND
GND
w
in
6
Exposed Pad
Exposed pad, should be connected to GND.
a
9
www.awinic.com.cn
2
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
l
OSC
ti
a
LDO
GND
VBAT
FUNCTIONAL BLOCK DIAGRAM
PWM Control
BG
SCL
fi
d
VBAT
LED1
LED2
LED3
C
o
n
SDA
IDAC
Current
Source
Control
I2C
e
n
Powerdown
control
4.7k
VIO
VBAT
VBAT
1uF
GND
LED1
MCU
LED2
SCL
SDA
SCL
SDA
a
w
in
ic
TYPICAL APPLICATION CIRCUITS
www.awinic.com.cn
LED3
AW2026
3
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
ORDERING INFORMATION
Temperature
Package
Marking
MSL
Level
ROHS
AW2026DNR
-40℃～85℃
1.5mm×1.5mm×0.45mm
DFN-8L
A26
XXX
MSL1
ROHS+HF
Delivery
Form
Tape and
Reel
3000pcs/Reel
ti
a
l
Part
Number
AW2026
PARAMETERS
Supply voltage range VBAT
fi
d
ABSOLUTE MAXIMUM RATINGS (NOTE 1)
e
Package Type
DN: DFN
-0.3V to 6.0V
-0.3V to 6.0V
LED1~LED3
-0.3V to 6.0V
n
Output voltage range
RANGE
SCL, SDA,
o
Input voltage range
n
Shipping
R: Tape & Reel
SDA
-0.3V to 6.0V
Junction-to-ambient thermal resistance θJA
C
121.6℃/W
Operating free-air temperature range
-40℃ to 85℃
150℃
Storage temperature TSTG
-65℃ to 150℃
ic
Maximum Junction temperature TJMAX
Lead Temperature (Soldering 10 Seconds)
260℃
ESD(NOTE 2)
±2000V
CDM (charge device mode)
±1500V
MM (machine mode)
±300V
w
in
HBM (human body mode)
Latch-up
±300mA
a
Test Condition: JEDEC STANDARD NO.78E September 2016
NOTE1: Conditions out of those ranges listed in “absolute maximum ratings” may cause permanent damages to the
device. In spite of the limits above, functional operation conditions of the device should within the ranges listed in
“recommended operating conditions”. Exposure to absolute-maximum-rated conditions for prolonged periods may affect
device reliability.
NOTE2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test method:
MIL-STD-883J Method 3015.9
www.awinic.com.cn
4
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
ELECTRICAL CHARACTERISTICS
VBAT=3.8V, TA=25℃ for typical values (unless otherwise noted)
Symbol
Description
Test Conditions
Min
Typ.
Max
Units
5.5
V
0.1
1
A
5
10
A
100
A
Input operation voltage
2.4
ISHUTDOWN
Current in Shutdown mode
ISTANDBY
Current in Standby mode
SCL/SDA=1.8V
IQ
Quiescent Current in Active
mode
register CHIPEN=1
SCL/ SDA =0V
(over 130ms)
80
n
all LED off
LED2, LED3 off
IACTIVE
Current in Active mode
277
fi
d
All channel set to 25.5mA
565
e
All channel set to 25.5mA
LED1 set to 25.5mA
ti
a
VBAT
l
Power supply
TRISE=2.1s,TON=0.04s
TFALL=2.1s, TOFF=1s
181
A
LED1 set to 25.5mA
n
LED2, LED3 off
121
Digital Logical Interface
o
TRISE=2.1s,TON=0.04s
TFALL=2.1s, TOFF=1s
Logic input low level
VIH
Logic input high level
SDA,SCL
IIL
Low level input current
SDA,SCL
5
nA
IIH
High level input current
SDA,SCL
5
nA
VOL
Logic output low level
SDA, IOUT=3mA
0.4
V
IL
Output leakage current
SDA open drain
1
nA
400
kHz
0.4
ic
1.3
in
I2C Interface
FSCL
SDA,SCL
C
VIL
V
V
I2C-BUS clock frequency
SCL deglitch time
200
ns
SDA deglitch time
250
ns
w
TDEGLITCH
LED Driver
Current accuracy
ILED=25.5mA
-5%
+5%
%
IMATCH
Matching accuracy
ILED=25.5mA
-5%
+5%
%
VDROP
Dropout voltage
ILED=25.5mA
60
100
mV
FPWM
PWM frequency
a
IACC
www.awinic.com.cn
Register PWM_F=0
115
122
128
Hz
Register PWM_F=1
230
244
256
Hz
5
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
I2C INTERFACE TIMING
TDEGLITCH
Deglitch time
SCL
200
SDA
250
(Repeat-start) Start condition hold time
0.6
TLOW
Low level width of SCL
1.3
THIGH
High level width of SCL
0.6
TSU:STA
(Repeat-start) Start condition setup time
0.6
THD:DAT
Data hold time
0
TSU:DAT
Data setup time
0.1
TR
Rising time of SDA and SCL
TF
Falling time of SDA and SCL
TSU:STO
Stop condition setup time
TBUF
Time between start and stop condition
kHz
ns
ns
μs
μs
fi
d
n
400
μs
μs
μs
μs
0.3
μs
0.3
μs
0.6
μs
1.3
μs
o
tBUF
tLOW
SCL
tHD:DAT
VIH
VIL
tSP
tF
VIH
VIL
tSU:DAT
tSU:STA
Start
tSU:STO
Stop
a
w
in
Start
tHIGH
tR
ic
tHD:STA
C
SDA
Stop
Units
e
THD:STA
Max
l
Interface Clock frequency
Typ.
n
FSCL
Min
ti
a
Parameter Name
www.awinic.com.cn
6
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
FUNCTIONAL DESCRIPTION
POWER_ON RESET
ti
a
l
AW2026 provides a power-on reset feature that is controlled by VBAT supply voltage. When the VBAT supply
voltage rises from 0V to 2.4V, the internal LDO starts to work. The reset signal will be generated to perform a
power-on reset operation, which will reset all control circuits and configuration registers until the internal power
voltage become stable.
The status bit STATUS.PUIS (register: 0x02 bit4) will be set to 1 when power-on reset operation occurs, which
will be cleared by a read operation of STATUS register. Usually the STATUS.PUIS bit can be used to check
whether an unexpected power-on event has taken place.
n
OPERATING MODE
fi
d
Shut Down
e
In AW2026, pin SCL provides power down control. There are three work modes available: Shut-down, Standby
and Active mode.
( SCL=0 for 130ms)
( SCL=0 for 130ms)
n
SCL = 1
C
Standby
o
CHIPEN=1
Active
CHIPEN=0
ic
Figure 1 AW2026 operating modes transition
SHUT-DOWN MODE
w
in
AW2026 enters into the shut-down mode when SCL level is pulled to low for over 130ms (prevents system
against wrong resets caused by electromagnetically influences)
In shut-down mode, AW2026 will reset all internal circuits and configuration register, all blocks inside AW2026
are basically switched off except the power on reset circuit and the SCL level detect circuit, and the current
consumption is very low (< 1A).
STANDBY MODE
a
AW2026 enters into standby mode when SCL level is pulled high from shut-down mode or CHIPEN is 0 from
active mode. In standby mode, only part of internal circuit can work, the OSC still keep closed so that there is
not internal clock, the LDO operates in low power state. The current consumption is less than 10A.
In stand-by mode, the I2C interface is accessible, but only registers RSTIDR and GCR can be operated.
www.awinic.com.cn
7
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
ACTIVE MODE
IACTIVE
ti
a
IF
l
When bit CHIPEN of GCR register is set to 1in standby mode, AW2026 enters into active mode.
In active mode, the internal OSC starts to work to provide clock signal. User can configure the device to produce
the pre-defined pattern lighting effects in pattern mode or turn each LED on or off directly.
When PWM level is low in fade-in and fade-out, only the OSC module works and the consumption is about
80Ua(IQ). So the average consumption of breathing is every low.
When PWM level is low, only
the timer module works and
the consumption is IQ
TON
TFALL
Time
TOFF
e
TRISE
n
IQ
Figure 2 AW2026 consumption in active mode
IMAX 3mA
6.375mA
IF
223μA 272μA
12.75mA
368μA
25.5mA
565μA
IQ
80μA
80μA
80μA
80μA
n
(T
+ TFALL ) * 25% + TON
IACTIVE = (IF - IQ ) * RISE
+ IQ
TRISE + TON + TFALL + TOFF
fi
d
Refer the following detailed formula (LED1/LED2/LED3 on)
o
SOFTWARE RESET
C
Writing 0x55 to register RSTIDR (register: 0x00) via I2C interface will reset the AW2026 internal circuits and all
configuration registers.
I2C INTERFACE
in
ic
AW2026 supports the I²C serial bus and data transmission protocol in fast mode at 400 kHz. AW2026 operates
as a slave on the I²C bus. Connections to the bus are made via the open-drain I/O pins SCL and SDA. The pullup resistor can be selected in the range of 1k~10kΩ and the typical value is 4.7kΩ. AW2026 can support different
high level (1.8V~3.3V) of this I2C interface.
DEVICE ADDRESS
w
The I2C device address (7-bit) of AW2026 is 0x64, followed by the R/W bit (Read=1/Write=0).
DATA VALIDATION
a
When SCL is high level, SDA level must be constant. SDA can be changed only when SCL is low level.
www.awinic.com.cn
8
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
SDA
SCL
l
Change
of Data
Allowed
ti
a
Data Line
Stable
Data Valid
Figure 3 Data Validation Diagram
I2C START/STOP
n
I2C start: SDA changes form high level to low level when SCL is high level.
fi
d
e
I2C stop: SDA changes form low level to high level when SCL is high level.
SDA
SCL
S/Sr
P
P: STOP condition
o
n
S: START condition
Sr: START Repeated condition
ACK (ACKNOWLEDGEMENT)
C
Figure 4 I2C Start/Stop Condition Timing
in
ic
ACK means the successful transfer of I2C bus data. After master sends 8bits data, SDA must be released; SDA
is pulled to GND by slave device when slave acknowledges.
When master reads, slave device sends 8bit data, releases the SDA and waits for ACK from master. If ACK is
send and I2C stop is not send by master, slave device sends the next data. If ACK is not send by master, slave
device stops to send data and waits for I2C stop.
a
w
Data Output
by Transmiter
Not Acknowledge（NACK）
Data Output
by Receiver
Acknowledge（ACK）
2
1
SCL From
Master
8
9
Clock Pulse for
Acknowledgement
START
condition
Figure 5 I2C ACK Timing
www.awinic.com.cn
9
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
WRITE CYCLE
ti
a
l
One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock
(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the
SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New
data should be sent during the low SCL state. This protocol allows a single data line to transfer both
command/control information and data using the synchronous serial clock.
Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a
Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is
transferred with the most significant bit first. After each byte, an Acknowledge signal must follow.
In a write process, the following steps should be followed:
Master device generates START condition. The “START” signal is generated by lowering the
i)
n
SDA signal while the SCL signal is high.
Master device sends slave address (7-bit) and the data direction bit (r/w = 0).
c)
Slave device sends acknowledge signal if the slave address is correct.
d)
Master sends control register address (8-bit)
e)
Slave sends acknowledge signal
f)
Master sends data byte to be written to the addressed register
g)
Slave sends acknowledge signal
h)
If master will send further data bytes the control register address will be incremented by one after
acknowledge signal (repeat step 6,7)
j)
Master generates STOP condition to indicate write cycle end
0
1
2
3
4
5
6
7
8
0
C
SCL
o
n
fi
d
e
b)
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
A6 A5 A4 A3 A2 A1 A0 R/WAck A7 A6 A5 A4 A3 A2 A1 A0 Ack D7 D6 D5 D4 D3 D2 D1 D0
Start
Register Address
Write Data
Stop
Figure 6 I2C Write Byte Cycle
in
READ CYCLE
Device Address
ic
SDA
In a read cycle, the following steps should be followed:
Master device generates START condition
a
w
a)
b)
Master device sends slave address (7-bit) and the data direction bit (r/w = 0).
c)
Slave device sends acknowledge signal if the slave address is correct.
d)
Master sends control register address (8-bit)
e)
Slave sends acknowledge signal
f)
Master generates STOP condition followed with START condition or REPEAT START condition
g)
Master device sends slave address (7-bit) and the data direction bit (r/w = 1).
h)
Slave device sends acknowledge signal if the slave address is correct.
www.awinic.com.cn
10
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
Slave sends data byte from addressed register.
j)
If the master device sends acknowledge signal, the slave device will increase the control register
address by one, then send the next data from the new addressed register.
k)
If the master device generates STOP condition, the read cycle is ended.
0
1
2
3
4
5
SDA
A6
A5
A4
A3
A2
A1
7
8
0
1
2
3
4
5
6
7
A0 R/W Ack A7
A6
A5
A4
A3
A2
A1
A0
0
1
2
3
4
5
A6
A5
A4
A3
A2
A1
RS
6
7
8
0
A0 R/W Ack D7
……
S
1
...
6
D6 …… D1
Write Data
Device Address
Separated
Read/write
transaction ……
P
Register Address
0
1
2
3
4
5
A6
A5
A4
A3
A2
A1
Device Address
6
7
8
0
A0 R/W Ack D7
7
8
1
...
Ack
D0 Ack
stop
e
……
Using
Repeat start……
8
n
Device Address
6
7
D6 …… D1
D0
fi
d
start
6
ti
a
SCL
l
i)
Write Data
8
Ack
stop
n
Figure 7 I2C Read Byte Cycle
o
LED DRIVER
C
AW2026 has three LED drivers to drive one RGB LED or three single-color LEDs. Each LED is driven by
common-anode mode constant current source with duty cycle controlled by PWM. Both current and PWM can
be configured via I2C interface.
ic
LED CURRENT
a
w
in
Globally, the maximum output current for three LEDs is 4-level selectable among 3mA, 6mA, 12mA and 25.5mA
via register IMAX (register: 0x03). In general, IMAX is used to set the max brightness of LED output.
For each LED, there is 256 current levels configurable via 8-bit register groups ILEDx_y (x=1~3, y=1~4). So in
RGB application it is possible to combine into 256x256x256 color-mixing schemes totally to achieve so-called
true-color effect.
Generally the current level register is used to form specified LED color for RGB application. AW2026 has 4
groups pre-defined current registers capable of forming 4 dedicated colors in true-color pattern scheme, in which
up to 4 pre-defined colors can be configured to represent 4 kinds of message, more than one color can flash
one by one successively in the same pattern when it’s necessary to transmit more than one messages.
PWM DIMMING CONTROL
In AW2026, each LED current source is gated by a 256-level, 12bit resolution PWM signal to create fine dimming
effect.
Each LED has an 8 bit PWM register PWMx (register: 0x1c, 0x1d, 0x1e) to control the duty cycle of constant
current source. The ramp up and down are automatically implemented by PWM duty continuously adjusted to
www.awinic.com.cn
11
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
form a smooth LED current transition between ON and OFF state. The ramp slope, for rise and fall, are
separately set via configuring the bit4~bit7 in pattern registers PATx_T1 and PATx_T2.
The ramping can be configured as linear and logarithmic curve by setting bit0~1 (PWMLOG) in register
LEDCTR (register 0x08).
l
LED CONTROL
n
fi
d
e
n
ti
a
Each LED of AW2026 can be independently configured to work or not via control bit LEDxEN.
- LEDxEN = 0, LEDx channel is disabled and no current output.
- LEDxEN = 1, LEDx channel is enabled to output lighting effect in different work mode.
By register configuration, AW2026 provides two types of LED control modes:
- Pattern control mode.
AW2026 contains three independent pattern controller and three groups of pattern parameter register
to generate user-defined breathing lighting effect. In RGB application, one pattern controller control 3
LED simultaneously to produce true-color breathing lighting, and three groups of pattern parameter can
be executed successively or cyclically. For LED-independent application, three pattern controller are
allocated to three different LEDs respectively, each operates with individual pattern parameter, user can
start or stop each pattern independently
- Manual control mode.
User directly set the brightness level of each LED by configuring relative current level register and PWM
level register via I2C interface. Usually it’s recommended to modify the PWM level to set on or off. For
each variation of PWM level register, the smoothly ramping effect is supported by setting FADE_IN bit
and/or FADE_OUT bit in register LCFGx (x=1~3).
o
PATTERN CONTROL MODE
C
BREATHING LIGHTING CONTROL
ic
When register bit LCFGx.LEDMD (register: 0x04, 0x05, 0x06 bit0) is set to 1, the corresponding LEDx operates
in pattern mode.
User should configure the related pattern parameter registers according to actual timing requirements via I2C
interface before starting pattern. The repeating times of pattern is configurable also, which may be 1~ 2048 or
infinite according to setting of register PATx_T5 (x=1~3).
in
Single Pulse mode
Current
a
w
Basically one pattern contains only one blinking, it’s called as single pulse mode. In single pulse mode, the
pattern parameters includes delay time, rise time, on time, fall time, off time and repeat times can be set by
corresponding configuration registers (PATx_T1~T5), The meanings of basic single-pulse pattern parameters
are shown in Figure and table below.
TDELAY
TRISE
TON
TFALL
TOFF
Time
Figure 8 Basic single-pulse pattern parameter definition
www.awinic.com.cn
12
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
Parameters
Delay time until pattern start
Rise time for dimming up
On time
Fall time for dimming down
Off time
Min
0
0
0.04
0
0.04
Typ.
Max
8.3
8.3
8.3
8.3
8.3
Unit
s
s
s
s
s
l
Symbol
TDELAY
TRISE
TON
TFALL
TOFF
ti
a
Multi-pulse mode
fi
d
e
n
A serial fast pulse blinking can be used to transmit message different from that carried by single pulse. In multipulse mode, up to 4 pulses are allowed during one color blinking. Besides the basic timing parameter defined in
single-pulse mode, there are 2 additional parameter need to be set:
The number of multi-pulse is defined by setting bit4~5 (MPULSE) in register PATx_T4 (register: 0x33/0x38/
0x3D) , the actual blinking times is MPULSE+1.
The interval time between two adjacent pulses is defined by TSLOT, bit5~7 in PATx_T4 (register:
0x32/0x37/0x3C).
Symbol
Parameter
Min
Typ.
Max
Unit
TSLOT
Pause time between multiple pulses
0
1.024
s
TRISE TON TFALL TSLOT
TSLOT
...
TOFF
Time
Pattern
o
Pattern
n
Current
Figure 9 Multi-pulse pattern parameter definition
C
An example of multi-pulse pattern is shown below:
ic
Current
in
Pattern
...
Pattern
Pattern
Time
Figure 10 Multi-pulse pattern example
w
Multi-color mode
a
Blinking with multiple different colors is allowed in one pattern period in RGB LED application, if different color
is expected to carry different message.
In AW2026, the LED color is defined by LED current configure register ILEDx_y (x=1~3, y=1~4), there are 4
RGB current combination to generate 4 pre-defined colors for display. More than one of the 4 pre-defined colors
can be chosen by setting CE1~CE4 , bit0~bit3 in PATx_T4 (register:x32/0x37/0x3C), when Cex is set to 1, the
color#x is allow to be displayed in current pattern.
If the color setting on CE1~CE4 is modified during current pattern is running, the updating of new color setting
will not occur until present pattern period is over.
If both multi-pulse and multi-color is enabled simultaneously, every selected color will blink specified times before
www.awinic.com.cn
13
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
switching to another color, and the display order of color is always from color #1 to color #4.
An example of 4-color /single-pulse pattern is shown below, in which the CE1~CE4 are changed twice during
pattern is running.
color#2
color#3
color#4
color#1
color#3
CE=0x5
CE=0xF
color#2
CE=0xA
Pattern
color#4
ti
a
color#1
l
Current
Time
Pattern
n
Pattern
Figure 11 Example of multi-color mode and color scheme modification
e
TRUE –COLOR BREATHING LIGHTING
ic
C
o
n
fi
d
In true-color breathing lighting application, the LEDMD, bit0 in LCFGx (register: 0x04, 0x05, 0x06), and the
SYNC, bit3 in LEDCTR (register: 0x08 bit3) should be set to 1, three LED output share the same pattern
controller to generate PWM dimming simultaneously. Multi-pulse, multi-color and multi-pattern modes are
supported fully in this mode.
The RGB color is defined by LED current setting register ILEDx_y (x=1~3, y=1~4), there are 4 RGB current
combination to generate 4 pre-defined color for display.
In true-color mode (SYNC=1), 3 groups of pattern timer parameters could be applied to defined 3 different
breathing lighting effects, which can be executed successively or keep looping forever, without external
processor involved to control every pattern switching. For each pattern, if PATx_T4.SW (register: 0x33, 0x38,
0x3E) is set to 1, the next pattern parameter will be loaded and started automatically after current pattern has
finished.
The following table gives the current, pattern and the start/stop control source for each LED channel in truecolor pattern mode.
Current Configuration
Channel
Pattern used
Pattern Start
Pattern Stop
Register
LED1
ILED1_y
pattern #1,
Write 1 to register
Write 1 to register
LED2
ILED2_y
pattern #2,
PATRUN bit0
PATRUN bit4
pattern #3
LED3
ILED3_y
in
Note: Y=1~4, denotes 4 pre-defined color code ( color #1, color #2, color #3 and color #4).
An example of single pulse and color pattern repeating in true-color pattern mode is depicted in the figure
below.
a
w
Current
Pattern
Pattern
Pattern
Time
Figure 12 Example of single-pulse/single-color true-color pattern
www.awinic.com.cn
14
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
The following figure is an example of multi pulse and multi-color pattern repeating in true-color pattern mode.
Time
Pattern
Figure 13 Example of 2-pulse/2-color in true-color pattern
ti
a
Pattern
l
Current
The following figure is another example of three patterns running successively in true-color pattern mode.
Pattern1
fi
d
e
n
Current
Pattern2
Pattern3
Time
Figure 14 Example of 3 pattern running successively in true-color mode
n
INDIVIDUAL BREATHING LIGHTING
w
in
ic
C
o
In some application where three LED need blinking individually. When register bit LCFGx.LEDMD (register: 0x04,
0x05, 0x06 bit0) is set to 1, the corresponding LEDx operates in pattern mode. If register bit LEDCTR.SYNC
(register: 0x08 bit3) is 0, all pattern run in individually. In this mode, the 3 internal pattern controllers and 3 groups
of pattern parameters are distributed to 3 LED channel respectively. Each LED can be controlled independently
to blink according to its own pattern definition.
In this mode, multi-pulse pattern is supported, but multi-color is not supported, the bits CE1~CE4 in register
PATx_T4 are ignored. Only registers ILEDx_1 is active for LED current setting, the other register including
ILEDx_2, ILEDx_3 and ILEDx_4 are all useless.
The following table gives the current, pattern parameter and the start/stop control source selection for each LED
channel in individual breathing lighting mode.
Pattern
Channel
Current Setting Register
Pattern Start
Pattern Stop
used
write 1 to PATRUN
write 1 to PATRUN
LED1
ILED1_1 (register: 0x10)
pattern #1
bit0
bit4
write 1 to PATRUN
write 1 to PATRUN
LED2
ILED2_1 (register: 0x11)
pattern #2
bit1
bit5
write 1 to PATRUN
write 1 to PATRUN
LED3
ILED3_1 (register: 0x12)
pattern #3
bit2
bit6
a
The following figure shows an example of 3 patterns run individually with different pattern parameters.
www.awinic.com.cn
15
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
LED1
Pattern#1: repeat times = 1
Time
LED2
Time
n
Pattern#3: repeat times = infinite
LED3
ti
a
l
Pattern#2: repeat times = 3
Time
e
Figure 15 Example of Individual Pattern Mode
fi
d
MANUAL CONTROL MODE
ic
C
o
n
When control bit LCFGx.LEDMD (register: 0x04, 0x05, 0x06 bit0) is set to 0, the corresponding LEDx is work in
manual control mode.
In manual control mode, the LED lighting effects including color-mixed and brightness is directly configured by
setting current/ PWM level register via I2C interface.
When LEDCTR.SYNC (register: 0x08, bit3) is set to 0, three LED are controlled individually, the PWM level and
current for each is defined by PWM1/PWM2/PWM3 (register: 0x1C/0x1D/0x1E) and ILEDx_1 (register
0x10/0x11/0x12) respectively.
When LEDCTR.SYNC (register: 0x08, bit3) is set to 1, the output currents of three LED are defined by register
ILEDx_1 respectively, but their PWM level are determined commonly by register PWM1. So user can change
the brightness of all LED simultaneously by modifying the value of register PWM1 only.
Brightness
Trise and Tfall time
Channel
Current
SYNC=0
SYNC=1
SYNC=0
SYNC=1
LED1
ILED1_1
PWM1
PAT1_T1/T2
LED2
ILED2_1
PWM2
PWM1
PAT2_T1/T2
PAT1_T1/T2
LED3
ILED3_1
PWM3
PAT3_T1/T2
a
w
in
In manual control mode, auto dimming is supported. If LCFGx.FADE_OUT (register: 0x04, 0x05 0x06 bit2) is
set to 1, automatic fade-out is enabled. If LCFGx.FADE_IN (register: 0x04, 0x05, 0x06 bit1) is set to 1, automatic
fade-in is enabled. If a new value is set on PWMx register and auto dimming is enabled, the brightness of LED
output ramp up/down smoothly, with its Trise and Tfall time defined by corresponding pattern configuration
(PATx_T1 and PATx_T2).
www.awinic.com.cn
16
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
PWMx
0xFF
0xBF
FADE_IN=0
0x7F
FADE_OUT=0
0x3F
0
PWMx
l
Time
0xBF
0x7F
FADE_OUT=1
FADE_IN=1
0x3F
0
PWMx=0xFF
ti
a
0xFF
Time
n
PWMx=0
a
w
in
ic
C
o
n
fi
d
e
Figure 16 Manual Control Mode
www.awinic.com.cn
17
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
REGISTER DESCRIPTION
REGISTER LIST
RSTIDR
GCR
STATUS
IMAX
LCFG1
LCFG2
LCFG3
LEDEN
LEDCTR
PATRUN
ILED1_1
ILED2_1
ILED3_1
ILED1_2
ILED2_2
ILED3_2
ILED1_3
ILED2_3
ILED3_3
ILED1_4
ILED2_4
ILED3_4
PWM1
PWM2
PWM3
PAT1_T1
PAT1_T2
PAT1_T3
PAT1_T4
PAT1_T5
PAT2_T1
PAT2_T2
PAT2_T3
PAT2_T4
PAT2_T5
PAT3_T1
PAT3_T2
PAT3_T3
PAT3_T4
PAT3_T5
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
5
0
1
-
-
3
2
1
0
PUIS
SYNC
STOP2
STOP1
ILED1_1
ILED2_1
ILED3_1
ILED1_2
ILED2_2
ILED3_2
ILED1_3
ILED2_3
ILED3_3
ILED1_4
ILED2_4
ILED3_4
PWM1
PWM2
PWM3
STOP3
1
0
PWM_F
LS2
FADE_OUT
FADE_OUT
FADE_OUT
LED3EN
RUN3
0
0
1
CHIPEN
LS1
LS0
IMAX
FADE_IN
LEDMD
FADE_IN
LEDMD
FADE_IN
LEDMD
LED2EN
LED1EN
PWMLOG
RUN2
RUN1
RESERVE
o
n
fi
d
e
-
4
-
-
TRISE
TFALL
TSLOT
PATSW
MPULSE
C
PATCTR
ic
in
6
l
7
ti
a
R/W
n
Name
PATCTR
TRISE
TFALL
TSLOT
PATSW
MPULSE
PATCTR
TRISE
TFALL
TSLOT
PATSW
MPULSE
TON
TOFF
TDELAY
CE4
REPTIM
CE3
CE2
CE1
CE2
CE1
CE2
CE1
TON
TOFF
TDELAY
CE4
REPTIM
CE3
TON
TOFF
TDELAY
CE4
REPTIM
CE3
a
w
Addr
(Hex)
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
DETAILED REGISTER DESCRIPTION
RSTIDR, Chip ID and Software Reset Register
Address: 0x00, R/W, default: 0x31
7
6
5
D7
D6
D5
www.awinic.com.cn
4
D4
3
D3
18
2
D2
1
D1
0
D0
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
Bit
7:0
Symbol
IDR
Description
Chip ID, 0x31
Reset: write 0x55 to RSTIDR, reset internal logic and register
RESERVE
CHIPEN
1
RESERVE
Description
PWM Modulation Frequency Select
0: 122Hz PWM modulation
1: 245Hz PWM modulation
Should be set to “1”
Device operating Enable
0: Disable, the device is in standby state
1: Enable, the device enters active state
STATUS Register
4
PUIS
3
-
2
LS3
1
LS2
0
LS1
n
Address: 0x02, R/W, default: 0x10
7
6
5
0
0
0
0
CHIPEN
n
1
0
2
PWM_F
e
Symbol
PWM_F
3
-
fi
d
Bit
2
4
-
ti
a
Address: 0x01, R/W, default: 0x00
7
6
5
-
l
GCR, Global Control Register
Symbol
PUIS
Description
Power Up Interrupt Status
0: No power-up reset has taken place
1: Power-up reset has taken place
2
LS3
operating status indication for pattern controller 3
0: stop state
1: running state
1
LS2
operating status indication for pattern controller 2
0: stop state
1: running state
0
LS1
operating status indication for pattern controller 1
0: stop state
1: running state
in
ic
C
o
Bit
4
w
IMAX, LED Maximum Current Register
a
Address: 0x03, R/W, default: 0x01
7
6
5
Bit
1:0
Symbol
IMAX
www.awinic.com.cn
4
-
3
-
2
-
1
0
IMAX
Description
Maximum LED output Current Select
00：3.1875Ma
01：6.375Ma
10：12.75Ma
11：25.5Ma
19
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
LCFG1-3 LED Configure Register
4
-
3
-
2
FADE_OUT
1
FADE_IN
Symbol
FADE_OUT
Description
Fade-out enable control, only active in manual mode
0: PWM fade-out is disable,
1: PWM fade-out is enable, the dimming time decide by TFALL
1
FADE_IN
Fade-in enable control, only active in manual mode
0: PWM fade-in is disable,
1: PWM fade-in is enable, the dimming time decide by TRISE
0
LEDMD
n
ti
a
Bit
2
0
LEDMD
l
LCFG1: Address: 0x04, R/W, default: 0x01
LCFG2: Address: 0x05, R/W, default: 0x00
LCFG3: Address: 0x06, R/W, default: 0x00
7
6
5
-
fi
d
e
LED Operating Mode Select.
0: Manual mode, LEDx is control directly by register ILEDx_1 and PWMx
1: Pattern mode
LEDEN, LED Channel Enable Register
Address: 0x07, R/W, default: 0x01
7
6
5
-
4
-
3
-
2
LED3EN
Symbol
LED3EN
Description
LED3 Enable
0: LED3 module stop work and LED3 out disable
1: LED3 output is enabled
1
LED2EN
LED2 Enable
0: LED2 module stop work and LED2 out disable
1: LED2 output is enabled
0
LED1EN
LED1 Enable
0: LED1 module stop work and LED1 out disable
1: LED1 output is enabled
0
LED1EN
ic
C
o
n
Bit
2
1
LED2EN
in
LEDCTR, LED Control Register
a
w
Address: 0x08, R/W, default: 0x00
7
6
5
Bit
3
Symbol
SYNC
1:0
PWMLOG
www.awinic.com.cn
4
-
3
SYNC
2
-
1
0
PWMLOG
Description
LED Breathing Synchronous Mode Select
0: 3 LED work in asynchronous mode with independent control
1: 3 LED work in synchronous mode for RGB application.
PWM Logarithmic curve select
0x: Log60
10: Log10
11: Linearity
20
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
PATRUN, Pattern Run/Stop Register
2
RUN3
Symbol
STOP3
Description
Write 1, LED3 pattern stop if independent mode;
The bit clears to 0 automatically after write 1.
5
STOP2
Write 1, LED2 pattern stop if independent mode;
The bit clears to 0 automatically after write 1.
4
STOP1
Write 1, LED1 pattern stop if independent mode;
Write 1, pattern stop if pattern mode;
The bit clears to 0 automatically after write 1.
2
RUN3
Write 1, LED3 pattern run if independent mode;
The bit clears to 0 automatically after write 1.
1
RUN2
Write 1, LED2 pattern run if independent mode;
The bit clears to 0 automatically after write 1.
0
RUN1
Write 1, LED1 pattern run if independent mode;
Write 1, pattern run if pattern mode;
The bit clears to 0 automatically after write 1.
fi
d
LED1 Current Register
C
o
ILED1_1: Address: 0x10, R/W, default: 0Xff
ILED1_2: Address: 0x13, R/W, default: 0x00
ILED1_3: Address: 0x16, R/W, default: 0x00
ILED1_4: Address: 0x19, R/W, default: 0x00
7
6
5
n
ILED1_y,
0
RUN1
e
Bit
6
1
RUN2
l
3
-
ti
a
4
STOP1
n
Address: 0x09, R/W, default: 0x00
7
6
5
STOP3
STOP2
Symbol
ILED1_y
3
2
1
0
Description
LED1 Current Configure Register for 4 pre-defined colors,
The LED1 output current value is IMAX * ILED1_y / 255.
ic
Bit
2:0
4
ILED1_y
in
ILED2_y, LED2 Current Register
w
ILED2_y: Address: 0x11/0x14/0x17/0x1A, R/W, default: 0x00
7
6
5
4
ILED2_y
Symbol
ILED2_y
2
1
0
Description
LED2Current Configure Register for 4 pre-defined colors,
The LED2 output current value is IMAX * ILED2_y / 255.
a
Bit
7:0
3
ILED3_y, LED3 Current Register
ILED3_y: Address: 0x12/0x15/0x18/0x1B, R/W, default: 0x00
7
6
5
4
ILED3_y
www.awinic.com.cn
21
3
2
1
0
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
Bit
7:0
Symbol
ILED3_y
Description
LED3 Current Configure Register, for 4 pre-defined colors
The LED3 output current value is IMAX * ILED3_y / 255.
PWM1/PWM2/PWM3 , PWM duty level Register
4
3
ti
a
l
PWM1: Address: 0x1C, R/W, default:0Xff
PWM2: Address: 0x1D, R/W, default:0x00
PWM3: Address: 0x1E, R/W, default:0x00
7
6
5
2
1
PWMx
Symbol
PWMx
Description
PWM level for LEDx (x=1,2,3)
n
Bit
7:0
PAT1_T1: Address: 0x30, R/W, default: 0x80
PAT2_T1: Address: 0x35, R/W, default: 0x00
PAT3_T1: Address: 0x3A, R/W, default: 0x00
7
6
5
TRISE
0001
a
w
www.awinic.com.cn
TRISE
Time
1000
2.1s
0.13s
1001
2.6s
0.26s
1010
3.1s
0s
0011
0.38s
1011
4.2s
0100
0.51s
1100
5.2s
0101
0.77s
1101
6.2s
0110
1.04s
1110
7.3s
0111
1.6s
1111
8.3s
On Time of pattern:
TON
Time
TON
Time
ic
in
TON
2
C
0010
n
Description
Rise Time of pattern:
TRISE
Time
0000
3:0
3
o
Symbol
TRISE
4
fi
d
e
PATx_T1, Time Parameter of Pattern x Register
Bit
7:4
0
0000
0.04s
1000
2.1s
0001
0.13s
1001
2.6s
0010
0.26s
1010
3.1s
0011
0.38s
1011
4.2s
0100
0.51s
1100
5.2s
0101
0.77s
1101
6.2s
0110
1.04s
1110
7.3s
0111
1.6s
1111
8.3s
22
1
0
TON
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
PATx_T2, Time Parameter of Pattern x Register
PAT1_T2: Address: 0x31, R/W, default: 0x86
PAT2_T2: Address: 0x36, R/W, default: 0x00
PAT3_T2: Address: 0x3B, R/W, default: 0x00
7
6
5
TFALL
1
l
Time
1000
2.1s
0001
0.13s
1001
2.6s
0010
0.26s
1010
3.1s
0011
0.38s
1011
4.2s
0100
0.51s
1100
5.2s
0101
0.77s
1101
6.2s
0110
1.04s
1110
7.3s
0111
1.6s
e
0s
ti
a
TFALL
0000
0000
0.04s
1000
2.1s
0001
0.13s
1001
2.6s
0010
0.26s
1010
3.1s
0.38s
1011
4.2s
0.51s
1100
5.2s
Off Time of pattern:
TOFF
Time
0011
C
0100
0
n
Description
Fall Time of pattern:
TFALL
Time
fi
d
TOFF
2
TOFF
1111
8.3s
TOFF
Time
n
2:0
Symbol
TFALL
3
o
Bit
6:4
4
0.77s
1101
6.2s
0110
1.04s
1110
7.3s
0111
1.6s
1111
8.3s
ic
0101
PATx_T3, Time Parameter of Pattern x Register
w
in
PAT1_T3: Address: 0x32, R/W, default: 0x00
PAT2_T3: Address: 0x37, R/W, default: 0x00
PAT3_T3: Address: 0x3C, R/W, default: 0x00
7
6
5
4
TSLOT
a
Bit
6:4
www.awinic.com.cn
Symbol
TSLOT
3
2
1
0
TDELAY
Description
Slot Time Between Pulses:
TSLOT
Time
000
0ms
001
130ms
010
260ms
011
380ms
23
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
110
800ms
111
1024ms
Startup Delay Time of Pattern:
TDELAY
Time
TDELAY
Time
0000
0s
1000
2.1s
0001
0.13s
1001
2.6s
0010
0.26s
1010
3.1s
0011
0.38s
1011
4.2s
0100
0.51s
1100
5.2s
0101
0.77s
1101
6.2s
0110
1.04s
1110
7.3s
0111
1.6s
1111
8.3s
n
PATx_T4, Time Parameter of Pattern x Register
4
3
CE4
2
CE3
1
CE2
Symbol
PAT_CTR
Description
Pattern running forever control
0: pattern run forever
1: pattern stop or switch to next pattern after repeating specified times.
6
PAT_SW
Pattern Switch enable, active only in true-color pattern mode.
0: Pattern switch is disabled
1: Pattern switch is enabled
5:4
MPULSE
in
ic
C
Bit
7
Multiple Pulse mode selection.
00: single pulse
01: pulse repeats 2 times
10: pulse repeats 3 times
11: pulse repeats 4 times
CE4
Color #4 display enable
0: Color#4 is masked
1: Color#4 is allow to display
2
CE3
Color #3 display enable
0: Color#3 is masked
1: Color#3 is allow to display
1
CE2
Color #2 display enable
0: Color#2 is masked
1: Color#2 is allow to display
a
w
3
www.awinic.com.cn
0
CE1
o
PAT1_T4: Address: 0x33, R/W, default: 0x00
PAT2_T4: Address: 0x38, R/W, default: 0x00
PAT3_T4: Address: 0x3D, R/W, default: 0x00
7
6
5
PAT_CTR
PAT_SW
MPULSE
ti
a
670ms
n
101
e
TDELAY
540ms
fi
d
3:0
100
l
September 2018 V1.3
24
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
0
CE1
Color #1 display enable
0: Color#1 is masked
1: Color#1 is allow to display
Note: if CE1~CE4 are all set to 0, Color #1 is displayed by default
4
3
ti
a
PAT1_T5: Address: 0x34, R/W, default: 0x00
PAT2_T5: Address: 0x39, R/W, default: 0x00
PAT3_T5: Address: 0x3E, R/W, default: 0x00
7
6
5
l
PATx_T5, Time Parameter of Pattern x Register
2
1
REPTIM
Description
PATTERN Repeat Times
REPTIM [7] = 0: Pattern repeats REPTIM[6:0]+1 times
REPTIM [7] = 1: Pattern repeats (REPTIM[6:0]+1) * 16 times
n
Symbol
REPTIM
a
w
in
ic
C
o
n
fi
d
e
Bit
7:0
0
www.awinic.com.cn
25
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
TAPE AND REEL INFORMATION
C
o
n
fi
d
e
n
ti
a
l
CARRIER TAPE
ic
NOTE: ALL DIMS IN mm.
PIN 1
w
in
Pin 1
a
User Direction of Feed
www.awinic.com.cn
26
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
o
a
w
in
ic
C
NOTE:
1、 ALL DIMS IN mm;
2、 General Tolerance ±0.25mm.
n
fi
d
e
n
ti
a
l
REEL
www.awinic.com.cn
27
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
PACKAGE DESCRIPTION
Dimensions in
Inches
Min.
Max.
Min.
Max.
A
0.400
0.500
0.016
0.200
A1
0.000
0.050
A3
0.127REF.
1.450
1.550
E
1.450
1.550
D1
0.650
E1
0.200REF.
1.150
1.250
0.050REF.
fi
d
E2
0.750
e
D2
E3
k
1.350
0.200REF.
0.150
n
b
e
0.250
0.400BSC.
0.150
0.250
0.002
0.005REF.
0.057
0.061
0.057
0.061
0.026
0.030
0.008REF.
0.045
0.049
0.002REF.
0.049
0.053
0.008REF.
0.006
0.010
0.016BSC.
0.006
0.010
C
o
L
LAND PATTERN EXAMPLE
1.250
0.000
n
D
ti
a
SYMBOL
l
Dimensions in
Millimeters
0.40
ic
0.20
1.05
0.80
1.45
a
w
in
0.45
NOTE: All dimensions are measured in millimeter (mm)
www.awinic.com.cn
28
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
fi
d
e
n
ti
a
l
REFLOW
n
Figure 17 Package Reflow Oven Thermal Profile
o
Reflow Note
Spec
Max. 3℃ /sec
Time of Preheat temp.(from 150℃ to 200℃)
60-120sec
C
Average ramp-up rate (217℃c to Peak)
60-150sec
Peak Temperature
>260℃
Time within 5℃ of actual peak temp
20-40sec.
ic
Time to be maintained above 217℃
Max. 6℃ /sec
Time from 25℃ to peak temp
Max. 8min.
a
w
in
Ramp-down rate
www.awinic.com.cn
29
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
REVISION HISTORY
Date
Change Record
V0.9
June 2016
Datasheet V0.9 Released
V0.91
July 2016
Datasheet V0.91 Released
V1.0
October 2016
Datasheet V1.0 Released
V1.1
November 2016
1. Added Pin 1 and Land pattern information;
2. Corrected mistake at pin configuration.
December 2017
1. Added exposed pad description in Pin
definition;
2. Added RoHS and MSL statements in
Ordering information.
September 2018
1. Refreshed Land Pattern Example (P28);
2. Refreshed Pin1 information (P26);
3. Refreshed AMR ESD and Temperature
information (P4);
4. Refreshed Package Description (P28).
ti
a
a
w
in
ic
C
o
n
fi
d
V1.3
e
n
V1.2
l
Vision
www.awinic.com.cn
30
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW2026
September 2018 V1.3
DISCLAIMER
l
Information in this document is believed to be accurate and reliable. However, Shanghai AWINIC Technology
Co., Ltd (AWINIC Technology) does not give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability for the consequences of use of such
information.
ti
a
AWINIC Technology reserves the right to make changes to information published in this document, including
without limitation specifications and product descriptions, at any time and without notice. Customers shall
obtain the latest relevant information before placing orders and shall verify that such information is current and
complete. This document supersedes and replaces all information supplied prior to the publication hereof.
fi
d
e
n
AWINIC Technology products are not designed, authorized or warranted to be suitable for use in medical,
military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an AWINIC
Technology product can reasonably be expected to result in personal injury, death or severe property or
environmental damage. AWINIC Technology accepts no liability for inclusion and/or use of AWINIC Technology
products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own
risk.
n
Applications that are described herein for any of these products are for illustrative purposes only. AWINIC
Technology makes no representation or warranty that such applications will be suitable for the specified use
without further testing or modification.
All products are sold subject to the general terms and conditions of commercial sale supplied at the time of
order acknowledgement.
o
Nothing in this document may be interpreted or construed as an offer to sell products that is open for
acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other
industrial or intellectual property rights.
C
Reproduction of AWINIC information in AWINIC data books or data sheets is permissible only if reproduction is
without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. AWINIC
is not responsible or liable for such altered documentation. Information of third parties may be subject to
additional restrictions.
a
w
in
ic
Resale of AWINIC components or services with statements different from or beyond the parameters stated by
AWINIC for that component or service voids all express and any implied warranties for the associated AWINIC
component or service and is an unfair and deceptive business practice. AWINIC is not responsible or liable for
any such statements.
www.awinic.com.cn
31
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
工商网监
湘ICP备2023018690号
