AW32001ACSR

AW32001A Apr 2020 V1.0 AW32001A Single Cell Li-ion Battery Charger with Power Path Management and Full USB Compliance Features General Description  The AW32001A is a highly-integrated Li-Ion/LiPolymer battery linear charger with system power path management. The charge process of AW32001A includes: Pre-Charge, Fast Charge and Constant Voltage Regulation. The charge parameters and operating modes are programmable through I2C interface. The charge process runs automatically and recharging occurs when the battery voltage drops below VBAT_REGVRCH after the charge done status. Charge Voltage Regulation Accuracy:  Minimum -5V Input Voltage Protection  Complete Charge Process with Pre-Charge, Fast Charge and Constant Voltage Regulation  Programmable Charge Parameters Through I2C Compatible Interface  Programmable Charge Autonomous Recharge Termination  Wide Range 2mA~500mA Charge  Strong and Robust Protection: VIN OVP, Battery OVP, OCP, Reverse Leakage Protection, Short Protection, Thermal Protection, PCB Over Temperature Protection  BATFET Control to Support Shipping Mode, Wake Up and System Reset Function  Fully Integrated Power Path Management  Ultra-low Battery Leakage Current to Support Shipping Mode  WLCSP 1.68mm×1.68mm×0.63mm-9B, 0.5mm Pitch Package  7-bit slave address binary(0x49H) d Current: C o ic in w is 1001001 a (A7~A1) Applications  Smart Handheld Devices  Wearable Devices  Smart Watches  Fitness Accessories www.awinic.com The AW32001A is targeted at space limited portable applications. The chip can take input power from either an AC adaptor or a USB port to supply the system load and charge the battery. Meanwhile, the chip provides system short circuit protection function by limiting the current from the input to the system and the battery to the system. These features are effective to protect the battery or chip from damage. The parameters of input current limit, the discharge current limit and safety timer can be programmed by the I2C interface. Additionally, input over voltage protection, input under voltage lockout and input headroom voltage are integrated for good input source detection. fi Fast and n of a Maximum 28V Input Voltage Rating with OverVoltage Protection ti  n Charge Current Accuracy: ±5% e  l ±0.5% ( 0°C to 50°C ) 1 AW32001A separates the charging route from the system power supply to fulfill the power management function. The system power supply is at first priority with no dependency on battery existence. Once a bad power-limited adapter appears at the input, AW32001A would reduce the charging current firstly. If the system load is still too heavy for input source, AW32001A will reduce the input-system current to prevent the input source from being pulled down. Under this circumstance, if the system voltage drops 30mV below the battery voltage, the battery to system supply route will be fully turned on to power the system load, which is supplement mode. Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW32001A Apr 2020 V1.0 Typical Application Circuit CSYS 50V 4.7mF 4.7mF TVS CVDD VDD BAT CBAT 4.7mF a 1mF VDD AW32001A RT1 10kΩ NTC INT SCL RNTC GND fi d SDA Typical Application Circuit of AW32001A n Figure 1 RT2 BATTERY e Host n 10kΩ ti VIO 10kΩ System Load SYS IN CIN1 l USB Port a w in ic C o All trademarks are the property of their respective owners. www.awinic.com 2 Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW32001A Apr 2020 V1.0 Pin Configuration and Top Mark AW32001ACSR PIN Configuration AW32001ACSR Marking (Top View) (Top View) 2 3 A IN SYS BAT A B NTC INT VDD B C SDA SCL GND C 1 2 3 d e n ti a 3GP4 XXXX YYYY YYYY l 1 Pin Definition Pin Name IN SYS BAT in NTC a w B1 B2 Description Input power pin. Bypass with a 4.7μF capacitor to GND. System power supply pin. Bypass with a 4.7μF capacitor to GND. Battery pin. Bypass with a 4.7μF capacitor to GND. Temperature sense input. Connect a negative temperature coefficient thermistor. Program the hot and cold temperature window with resistor dividers from VDD to GND, and NTC is the middle node. Pull NTC to VDD if NTC function is not used. Interrupt output. The INT pin can send charge status and fault interrupt to the host. This pin is also used to disconnect the system from battery, and awake the chip from shipping mode. Internal power supply pin. Bypass with a 1μF capacitor to GND. No external load is allowed. I2C Interface serial date. I2C Interface clock. Ground. ic Pin No. A1 A2 A3 Pin Configuration and Top Mark C o Figure 2 n fi 3GP4 - AW32001ACSR Marking XXXX - Production Tracing Code YYYY YYYY - Die Location INT B3 VDD C1 C2 C3 SDA SCL GND www.awinic.com 3 Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW32001A Apr 2020 V1.0 Ordering Information Part Number Temperature Package Marking Moisture Sensitivity Level Environmental Information AW32001ACSR -40°C～85°C WLCSP 1.68mm×1.68mm-9B 3GP4 MSL1 ROHS+HF Delivery Form 3000 units/ a w in ic C o n fi d e n ti a l Tape and Reel www.awinic.com 4 Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW32001A Apr 2020 V1.0 Absolute Maximum Ratings(NOTE1) MIN MAX UNIT -5 28 V IN NTC voltage range VNTC (with respect to GND) NTC -0.3 VVDD+0.3 V Other pins voltage range (with respect to GND) SYS, BAT, INT, VDD, SCL, SDA -0.3 6 V Operating free-air temperature range -40 85 °C Operating junction temperature TJ -40 150 °C Storage temperature TSTG -65 150 °C 260 °C a Input voltage range VIN (with respect to GND) l PARAMETERS ti Lead temperature (Soldering 10 seconds) d e n NOTE1: Conditions out of those ranges listed in "absolute maximum ratings" may cause permanent damages to the device. In spite of the limits above, functional operation conditions of the device should within the ranges listed in "recommended operating conditions". Exposure to absolute-maximum-rated conditions for prolonged periods may affect device reliability. UNIT HBM (Human Body Model) (NOTE 2) ±2 kV CDM(NOTE 3) ±1.5 kV n VALUE C o PARAMETERS fi ESD Rating and Latch Up Latch-Up(NOTE 4) +IT：200 -IT：-200 mA ic NOTE2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test method: ESDA/JEDEC JS-001-2017 in NOTE3: Test method: ESDA/JEDEC JS-002-2018 a w NOTE4: Test method: JESD78E www.awinic.com 5 Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW32001A Apr 2020 V1.0 Recommended Operating Conditions MIN MAX UNIT 5.5 V Supply current IIN 500 mA Discharge current IBAT 3.2 A 2 456 mA Battery regulated voltage VBAT_REG 3.6 4.545 V Operating junction temperature TJ -40 125 °C Supply voltage range VIN NORM 4 a Charge current ICHG l PARAMETERS PARAMETERS n ti Thermal Information UNIT 122 °C/W VALUE a w in ic C o n fi d e Junction-to-ambient thermal resistance θJA www.awinic.com 6 Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW32001A Apr 2020 V1.0 Electrical Characteristics VIN=5V, VBAT=3.5V, TJ=25°C for typical values (unless otherwise noted) TEST CONDITION PARAMETER MIN TYP MAX UNIT 3.5 3.6 3.7 V INPUT SOURCE AND BATTERY PROTECTION Hysteresis for UVLO VIN rising 300 mV Deglitch time for VIN_UVLO Exits UVLO 30 ms VIN_OVP threshold voltage VIN rising VIN_OVP hysteresis VIN falling from above VIN_OVP VBAT_UVLO REG01[2:0]=100 Input vs battery voltage headroom threshold Input vs battery voltage headroom threshold hysteresis CHARGE PROCESS REG04[1]=1, VBAT rising VBAT_PRE hysteresis in w Battery charge voltage regulation voltage a VBAT_REG Recharge threshold voltage VRECH Deglitch time for VRCH Battery OVP threshold voltage VBAT_OVP VBAT_OVP hysteresis www.awinic.com 7 V 2.64 2.76 2.88 V 2.93 3.03 3.13 V 190 80 130 mV 170 60 2.9 VBAT falling REG04[7:2]=000000, VBAT_REG=3.6V REG04[7:2]=101000, VBAT_REG=4.2V REG04[7:2]=110010, VBAT_REG=4.38V REG04[7:2]=111110, VBAT_REG=4.53V REG04[0]=0, VBAT_REG=4.2V, below VBAT_REG REG04[0]=1, VBAT_REG=4.2V, below VBAT_REG VBAT falling after charge termination VBAT threshold over VBAT_REG to turn off charger during charging 4.6 V VIN falling ic VBAT_PRE Pre-charge to fast charge threshold VIN rising C o VHDRM mV 2.53 VBAT_UVLO =2.76V n Hysteresis voltage V 2.43 fi REG01[2:0]=111 6.15 2.33 e UVLO threshold voltage for BAT voltage, VBAT falling, entry UVLO n BAT input voltage REG01[2:0]=000 6 350 d VBAT 5.85 a VIN_OVP l VIN falling ti VIN_UVLO UVLO threshold voltage, entry UVLO 3.0 mV mV 3.1 200 V mV 3.585 3.6 3.615 V 4.18 4.2 4.22 V 4.36 4.38 4.4 V 4.507 4.53 4.553 V 60 100 140 mV 160 200 240 mV 130 ms 130 mV 50 mV Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW32001A Apr 2020 V1.0 Electrical Characteristics (Continued) VIN=5V, VBAT=3.5V, TJ=25°C for typical values (unless otherwise noted) TEST CONDITION PARAMETER MIN TYP MAX UNIT 4.51 4.60 4.69 V 30 45 60 mA 112 125 140 mA 275 296 d IN to SYS switch on resistance RON_Q2 BAT to SYS switch on resistance IIN_Q Input quiescent current (not include the current from external NTC resistor) ic in Battery quiescent current (not include the current from external NTC resistor) a w IBAT_Q ISYS-BAT_LKG SYS reverse to BAT switch leakage IDSCHG BAT FET discharge current limit IDSCHG=400mA IDSCHG=2000mA VFWD Ideal diode forward voltage in supplement mode www.awinic.com 50mA discharge current 8 a mA 3.88 4.18 V 4.32 4.52 4.82 V 4.88 5.08 5.35 V 3.68 C o RON_Q1 460 mA 500 e Dynamic input power management clamp voltage VIN_DPM 440 320 ti Input current limit fi IIN_LMT VIN=5.5V, EN_HIZ=0, RSYS=100Ω, ICHG=0A, VSYS_REG=4.6V REG00[3:0]=0000, IIN_LMT=50mA REG00[3:0]=0011, IIN_LMT=140mA REG00[3:0]=1001, IIN_LMT=320mA REG00[3:0]=1111, IIN_LMT=500mA REG00[7:4]=0000, VIN_DPM=3.88V REG00[7:4]=1000, VIN_DPM=4.52V REG00[7:4]=1111, VIN_DPM=5.08V VIN_DPM=3.88V, VIN=4.5V, ISYS=100mA VIN