AW5005
May. 2019 V1.4
Ultra-Low Noise Amplifier for Global Navigation
l
Satellite Systems (GNSS)
GENERAL DESCRIPTION
The AW5005 is a Low Noise Amplifier
designed for Global Navigation Satellite
Systems (GNSS) as GPS, GLONASS, Galileo
and Compass. With on-chip DC blocking
capacitors at RFIN and RFOUT, The AW5005
can be close to the antenna, requires only one
external input matching inductor, and reduces
assembly complexity and the PCB area,
enabling a cost-effective solution.
The AW5005 with patented Smart Linearity
Technology (SLT) achieves ultra-low noise
figure, high linearity, high gain, over a wide
range of supply voltages from 1.5V up to 3.6V.
All these features make AW5005 an excellent
choice for GNSS LNA as it improves sensitivity
with low noise figure and high gain, provides
better immunity against out-of-band jammer
signals with high linearity, reduces filtering
requirement of preceding stage and hence
reduces the overall cost of the GNSS receiver.
Reduce RF environment Interference with
patented Smart-Linearity-Technology (SLT);
low noise figure(NF)=0.85dB@1.575GHz; NF
n
=0.79dB@1.227GHz;NF=0.80dB@1.176GHz;
High power gain=18.2dB@1.575GHz;power
gain=18.9dB@1.227GHz;power gain=18.7dB
High linearity IIP3oob=+6.5dBm;
High input 1dB-compression point=-7.6dBm;
Requires only one input matching inductor;
RF output internally matched to 50 ohm;
Supply voltage: 1.5V to 3.6V;
Operating frequencies: GPS L1、L2/L5 band;
DFN 1.5mmX1.0mmX0.55mm-6L package;
3KV HBM ESD protection (including RFIN and
RFOUT pin);
The AW5005 is available in a small lead-free,
RoHS-Compliant, DFN 1.5mm X 1.0mm X
0.55mm -6L package.
ic
APPLICATIONS
C
o
n
fi
d
@1.176 GHz;
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ti
a
FEATURES
Smart phones, feature phones;
Tablet PCs;
Personal Navigation Devices;
Digital Still Cameras, Digital Video Cameras;
RF Front End modules;
w
in
Complete GPS chipset modules;
Theft protection(laptop, ATM);
a
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1
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
AW5005
1
GND
6
5
RF OUTPUT
EN
fi
d
e
2
RFOUT
n
GND
ti
a
l
TYPICAL APPLICATION CIRCUIT
LOGIC
CONTROL
BIAS
RFIN
RF INPUT
(optional)
VCC L2
4
3
C1
(optional)
o
n
L1
SUPPLY
VOLTAGE
C1, L2 Closed to LNA
C
Figure 1 Typical Application Circuit of AW5005 for GNSS L1、L2/L5
a
w
in
ic
All trademarks are the property of their respective owners.
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2
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
RFOUT
GND
2
5
EN
RFIN
3
4
VCC
e
6
fi
d
1
AXY
GND
ti
a
AW5005DNRZ Marking
(Top View)
n
AW5005DNRZ
(Top View)
l
PIN CONFIGURATION AND TOP MARK
A – AW5005DNRZ
XY– Production Tracing Code
o
PIN DEFINITION
Pin Configuration and Top Mark
n
Figure 2
NAME
1
GND
2
GND
3
RFIN
LNA input
VCC
DC Supply
EN
in
5
ic
4
C
No.
RFOUT
Ground
Ground
Logic control
LNA output
a
w
6
DESCRIPTION
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3
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
GND
2
AW5005
6
RFOUT
5
EN
fi
d
BIAS
3
4
VCC
-40°C～85°C
Package
1.5mmX1.0mm-
Environmental
Information
Delivery Form
A
MSL3
ROHS+HF
3000 units/
Tape and Reel
6L
AW5005
Z
Shipping
R: Tape & Reel
a
www.awinic.com.cn
Marking
Moisture
Sensitivity
Level
DFN
w
in
AW5005DNRZ
Temperature
ic
Part Number
C
ORDERING INFORMATION
o
n
RFIN
n
1
e
GND
ti
a
l
FUNCTIONAL BLOCK DIAGRAM
Package Type
DN: DFN
4
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
ABSOLUTE MAXIMUM RATINGS[1]
Values
Typ.
Max.
5
V
Unit
5
V
30
mA
10
dBm
Supply Voltage at pin VCC
VCC
-0.3
-
Voltage at pin EN [2]
VEN
-0.3
-
Current into pin VCC
ICC
-
-
RF input power [3]
PIN
-
Package thermal resistance
θJA
Junction temperature
TJ
n
Ambient temperature range
o
Solder temperature(10s)
ESD range
C
HBM [4]
Latch-up
ic
CDM
e
-
-
148.2
-
℃/W
-
-
150
℃
TSTG
-65
-
150
℃
Tamb
-40
-
85
℃
-
260
-
℃
fi
d
Storage temperature range
ti
a
Min.
l
Symbol
n
PARAMETERS
±3000
V
±1000
V
+IT: +400
Standard: JEDEC STANDARD NO.78E SEPTEMBER 2016
mA
in
-IT: -400
Note1: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
w
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated
conditions for extended periods may affect device reliability.
a
Note2: Warning: due to internal ESD diode protection, the applied DC voltage should not exceed 5.0V in order
to avoid excess current.
Note3: The RF input and RF output are AC coupled through internal DC blocking capacitor.
Note4: HBM standard: MIL-STD-883J Method 3015.9.
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5
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
ELECTRICAL CHARACTERISTICS
(AW5005 EVB[1]; VCC=1.5 to 3.6V, TA=-40~+85°C, f=1550MHz to 1615MHz; Typical values are at VCC=2.8V
TEST CONDITION
MIN
TYP
1.5
-
DC ELECTRICAL CHARACTERISTICS
Supply Voltage
ISD
Shut-Down Current
EN=Low
ICC
Supply Current
EN=High
VEN
Digital Input-Logic High
VEN
Digital Input-Logic Low
e
0.80
16.0
RLin
Input Return Loss
RLout
Output Return Loss
ISL
Reverse Isolation
NF
Noise Figure[2]
n
Power Gain
fi
d
AC ELECTRICAL CHARACTERISTICS
Gp
8.0
25.0
o
Zs=50 ohm;
No jammer
f=20MHz…10GHz
Stability factor
C
Kf
Noise Figure with jammer
IP1dB
in
f1=1712.7MHz[3];
f2=1850MHz;
Pin=-20dBm;
f1=1712.7MHz[3];
f2=1850MHz;
Pin=-30dBm;
f1=824.6MHz[4];
f2=2400MHz;
Pin=-20dBm
f1=824.6MHz[4];
f2=2400MHz;
Pin=-30dBm
Out-of-band input
3rd-order intercept point
w
IIP3oob
a
IIP2oob
IIP2oob
Out-of-band input
3rd-order intercept point
Out-of-band input
2nd-order intercept point
Out-of-band input
2nd-order intercept point
H2-input
LTE band-13 2nd Harmonic
f=787.76MHz;
Pin=-25dBm;
referred
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fjam=850MHz
f=1575.42MHz
1dB-compression point
IIP3oob
Pjam=-20dBm;
fjam= 1850MHz
Inband input
6
V
1
μA
13.0
mA
V
0.45
V
18.5
dB
5.6
dB
10
dB
28.5
dB
0.85
dB
1
Pjam=-20dBm;
ic
NFj
18.2
UNIT
3.6
n
VCC
MAX
ti
a
PARAMETER
l
and TA=+25°C, f=1575.42MHz, input matched to 50 using a 9.1nH inductor, unless otherwise noted)
0.72
1.10
dB
1.14
1.50
dB
-9.0
-7.6
dBm
+4.0
+6.1
dBm
+4.5
+6.5
dBm
-2.0
-1.2
dBm
-2.0
-1.2
dBm
-74.4
-70.0
dBm
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
turn-on time
time from VEN ON to
90% of the final gain
2.2
2.5
μs
toff
turn-off time
time from VEN OFF to
10% of the gain
1.7
2.0
μs
ti
a
ton
l
fH2=1575.52MHz
Note1: input matched to 50 ohm using a high quality‐factor 9.1nH inductor.
Note2: 0.08dB PCB losses are subtracted.
n
Note3: IIP3=0.5*(Po_f1-IM3)+Pi_f1.
a
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in
ic
C
o
n
fi
d
e
Note4: IIP2=Po_f2+Pi_f2-IM2.
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7
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
(AW5005 EVB[1] ; VCC=1.5 to 3.6V, TA=-40~+85°C, f=1550MHz to 1615MHz; Typical values are at VCC=1.8V
and TA=+25°C, f=1575.42MHz, input matched to 50 using a 9.1nH inductor, unless otherwise noted)
TEST CONDITION
MIN
TYP
MAX
UNIT
1.5
-
3.6
V
1
μA
15.0
mA
VCC
Supply Voltage
ISD
Shut-Down Current
EN=Low
ICC
Supply Current
EN=High
VEN
Digital Input-Logic High
VEN
Digital Input-Logic Low
RLin
Input Return Loss
RLout
Output Return Loss
ISL
Reverse Isolation
NF
Noise Figure[2]
e
16.0
fi
d
Power Gain
25.0
Zs=50 ohm;
n
No jammer
f=20MHz…10GHz
Stability factor
Pjam=-20dBm;
Noise Figure with jammer
Inband input
1dB-compression point
IIP3oob
in
Out-of-band input
w
3rd-order intercept point
a
IIP2oob
IIP2oob
H2-input
Out-of-band input
2nd-order intercept point
Out-of-band input
2nd-order intercept point
LTE band-13 2nd Harmonic
referred
ton
turn-on time
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18.0
dB
5.3
dB
10
dB
28.0
dB
0.83
dB
0.76
1.10
dB
1.18
1.50
dB
fjam= 1850MHz
f1=1712.7MHz[3];
f2=1850MHz;
Pin=-20dBm;
f1=1712.7MHz[3];
f2=1850MHz;
Pin=-30dBm;
f1=824.6MHz[4];
f2=2400MHz;
Pin=-20dBm
f1=824.6MHz[4];
f2=2400MHz;
Pin=-30dBm
f=787.76MHz;
Pin=-25dBm;
fH2=1575.52MHz
Out-of-band input
3rd-order intercept point
IIP3oob
Pjam=-20dBm;
f=1575.42MHz
ic
IP1dB
V
fjam=850MHz
C
NFj
17.5
0.45
1
o
Kf
V
n
0.80
AC ELECTRICAL CHARACTERISTICS
Gp
6.0
ti
a
DC ELECTRICAL CHARACTERISTICS
time from VEN ON to
90% of the final gain
8
l
PARAMETER
-14.0
-12.5
dBm
-1.0
0.7
dBm
0
2.5
dBm
-3.0
-1.9
dBm
-3.0
-1.7
dBm
-72.6
-70.0
dBm
2.2
2.5
μs
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
PARAMETER
toff
TEST CONDITION
turn-off time
MIN
time from VEN OFF to
10% of the gain
TYP
MAX
UNIT
1.7
2.0
μs
l
Note1: input matched to 50 ohm using a high quality‐factor 9.1nH inductor.
ti
a
Note2: 0.08dB PCB losses are subtracted.
Note3: IIP3=0.5*(Po_f1-IM3)+Pi_f1.
n
Note4: IIP2=Po_f2+Pi_f2-IM2.
(AW5005 EVB[1]; VCC=1.5 to 3.6V, TA=-40~+85°C, f=1227.60±1.023MHz; Typical values are at VCC=2.8V
TEST CONDITION
DC ELECTRICAL CHARACTERISTICS
MIN
fi
d
PARAMETER
e
and TA=+25°C, f=1227.60MHz, input matched to 50 using a 15nH inductor, unless otherwise noted)
VCC
Supply Voltage
ISD
Shut-Down Current
EN=Low
ICC
Supply Current
EN=High
VEN
Digital Input-Logic High
VEN
Digital Input-Logic Low
MAX
UNIT
-
3.6
V
1
μA
13.0
mA
8
0.80
V
o
n
1.5
TYP
0.45
V
18.5
dB
C
AC ELECTRICAL CHARACTERISTICS
Power Gain
RLin
Input Return Loss
RLout
Output Return Loss
ISL
Reverse Isolation
NF
Noise Figure[2]
a
NFj
IP1dB
IIP3oob
Zs=50 ohm;
No jammer
f=20MHz…10GHz
Stability factor
fjam=850MHz
Noise Figure with jammer
Pjam=-20dBm;
fjam= 1850MHz
Inband input
f=1575.42MHz
1dB-compression point
f1=1712.7MHz[3];
f2=1850MHz;
Pin=-20dBm;
f1=1712.7MHz[3];
f2=1850MHz;
Out-of-band input
Out-of-band input
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9
18.9
5.5
dB
12.3
dB
26.2
dB
0.79
dB
1
Pjam=-20dBm;
3rd-order intercept point
IIP3oob
16.0
25.0
in
w
Kf
ic
Gp
0.72
1.10
dB
1.14
1.50
dB
-9.0
-7.6
dBm
+4.0
+6.1
dBm
+4.5
+6.5
dBm
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
Out-of-band input
f1=824.6MHz[4];
f2=2400MHz;
Pin=-20dBm
f1=824.6MHz[4];
f2=2400MHz;
Pin=-30dBm
f=787.76MHz;
Pin=-25dBm;
fH2=1575.52MHz
2nd-order intercept point
IIP2oob
Out-of-band input
2nd-order intercept point
H2-input
LTE band-13 2nd Harmonic
referred
turn-on time
time from VEN ON to
90% of the final gain
toff
turn-off time
time from VEN OFF to
10% of the gain
-1.2
-2.0
-1.2
UNIT
dBm
-74.4
dBm
-70.0
dBm
2.2
2.5
μs
2.0
μs
1.7
fi
d
ton
-2.0
MAX
l
Pin=-30dBm;
TYP
ti
a
3rd-order intercept point
MIN
n
IIP2oob
TEST CONDITION
e
PARAMETER
Note1: input matched to 50 ohm using a high quality‐factor 9.1nH inductor.
Note2: 0.08dB PCB losses are subtracted.
n
Note3: IIP3=0.5*(Po_f1-IM3)+Pi_f1.
o
Note4: IIP2=Po_f2+Pi_f2-IM2.
(AW5005 EVB[1]; VCC=1.5 to 3.6V, TA=-40~+85°C, f=1227.60±1.023MHz; Typical values are at VCC=1.8V
PARAMETER
C
and TA=+25°C, f=1227.60MHz, input matched to 50 using a 15nH inductor, unless otherwise noted)
TEST CONDITION
MIN
TYP
MAX
UNIT
1.5
-
3.6
V
1
μA
13.0
mA
ic
DC ELECTRICAL CHARACTERISTICS
Supply Voltage
ISD
Shut-Down Current
EN=Low
ICC
Supply Current
EN=High
VEN
w
VEN
in
VCC
Digital Input-Logic High
6.0
0.80
V
Digital Input-Logic Low
0.45
V
18.5
dB
AC ELECTRICAL CHARACTERISTICS
Power Gain
RLin
Input Return Loss
5.4
dB
RLout
Output Return Loss
12.4
dB
ISL
Reverse Isolation
25.6
dB
NF
Noise Figure[2]
0.83
dB
a
Gp
16.0
25.0
Zs=50 ohm;
No jammer
Kf
f=20MHz…10GHz
Stability factor
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10
18.2
1
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
Pjam=-20dBm;
NFj
fjam=850MHz
Noise Figure with jammer
Pjam=-20dBm;
fjam= 1850MHz
Inband input
f=1575.42MHz
1dB-compression point
IIP3oob
f1=1712.7MHz[3];
f2=1850MHz;
Pin=-20dBm;
f1=1712.7MHz[3];
f2=1850MHz;
Pin=-30dBm;
f1=824.6MHz[4];
f2=2400MHz;
Pin=-20dBm
f1=824.6MHz[4];
f2=2400MHz;
Pin=-30dBm
f=787.76MHz;
Pin=-25dBm;
fH2=1575.52MHz
Out-of-band input
3rd-order intercept point
IIP3oob
Out-of-band input
3rd-order intercept point
Out-of-band input
2nd-order intercept point
IIP2oob
Out-of-band input
H2-input
LTE band-13 2nd Harmonic
turn-on time
toff
turn-off time
C
ton
1.10
dB
1.14
1.50
dB
+4.0
+6.1
+4.5
dBm
dBm
+6.5
dBm
-2.0
-1.2
dBm
-2.0
-1.2
dBm
-74.4
-70.0
dBm
time from VEN ON to
90% of the final gain
2.2
2.5
μs
time from VEN OFF to
10% of the gain
1.7
2.0
μs
o
referred
0.72
-7.6
n
2nd-order intercept point
UNIT
-9.0
fi
d
IIP2oob
MAX
e
IP1dB
TYP
l
MIN
ti
a
TEST CONDITION
n
PARAMETER
ic
Note1: input matched to 50 ohm using a high quality‐factor 9.1nH inductor.
Note2: 0.08dB PCB losses are subtracted.
in
Note3: IIP3=0.5*(Po_f1-IM3)+Pi_f1.
w
Note4: IIP2=Po_f2+Pi_f2-IM2.
(AW5005 EVB[1]; VCC=1.5 to 3.6V, TA=-40~+85°C, f=1176.45±1.023MHz; Typical values are at VCC=2.8V
a
and TA=+25°C, f=1176.45MHz, input matched to 50 using a 15nH inductor, unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
1.5
-
3.6
V
1
μA
13.0
mA
DC ELECTRICAL CHARACTERISTICS
VCC
Supply Voltage
ISD
Shut-Down Current
EN=Low
ICC
Supply Current
EN=High
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11
8.0
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
PARAMETER
TEST CONDITION
VEN
Digital Input-Logic High
VEN
Digital Input-Logic Low
MIN
TYP
MAX
0.80
UNIT
V
0.45
V
18.9
dB
Power Gain
RLin
Input Return Loss
RLout
Output Return Loss
12.0
14.3
ISL
Reverse Isolation
25.0
26.0
Noise
4.9
Figure[2]
Zs=50 ohm;
NFj
1
dB
1.14
1.50
dB
Pjam=-20dBm;
fjam= 1850MHz
Inband input
f=1575.42MHz
n
IP1dB
1dB-compression point
Out-of-band input
IIP3oob
Out-of-band input
C
3rd-order intercept point
3rd-order intercept point
Out-of-band input
ic
IIP2oob
2nd-order intercept point
IIP2oob
Out-of-band input
in
2nd-order intercept point
H2-input
LTE band-13 2nd Harmonic
referred
w
f1=1712.7MHz[3];
f2=1850MHz;
Pin=-20dBm;
f1=1712.7MHz[3];
f2=1850MHz;
Pin=-30dBm;
f1=824.6MHz[4];
f2=2400MHz;
Pin=-20dBm
f1=824.6MHz[4];
f2=2400MHz;
Pin=-30dBm
f=787.76MHz;
Pin=-25dBm;
fH2=1575.52MHz
o
IIP3oob
dB
1.10
fjam=850MHz
Noise Figure with jammer
dB
0.72
fi
d
Pjam=-20dBm;
dB
e
f=20MHz…10GHz
Stability factor
dB
0.80
No jammer
Kf
18.7
n
NF
16.0
ti
a
Gp
l
AC ELECTRICAL CHARACTERISTICS
-9.0
-7.6
dBm
+4.0
+6.1
dBm
+4.5
+6.5
dBm
-2.0
-1.2
dBm
-2.0
-1.2
dBm
-74.4
-70.0
dBm
turn-on time
time from VEN ON to
90% of the final gain
2.2
2.5
μs
toff
turn-off time
time from VEN OFF to
10% of the gain
1.7
2.0
μs
a
ton
Note1: input matched to 50 ohm using a high quality‐factor 9.1nH inductor.
Note2: 0.08dB PCB losses are subtracted.
Note3: IIP3=0.5*(Po_f1-IM3)+Pi_f1.
Note4: IIP2=Po_f2+Pi_f2-IM2.
www.awinic.com.cn
12
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
(AW5005 EVB[1]; VCC=1.5 to 3.6V, TA=-40~+85°C, f=1176.45±1.023MHz; Typical values are at VCC=1.8V
and TA=+25°C, f=1176.45MHz, input matched to 50 using a 15nH inductor, unless otherwise noted)
TEST CONDITION
MIN
TYP
MAX
UNIT
1.5
-
3.6
V
1
μA
13.0
mA
VCC
Supply Voltage
ISD
Shut-Down Current
EN=Low
ICC
Supply Current
EN=High
VEN
Digital Input-Logic High
VEN
Digital Input-Logic Low
RLin
Input Return Loss
RLout
Output Return Loss
ISL
Reverse Isolation
NF
Noise Figure[2]
e
16.0
n
f=20MHz…10GHz
dB
25.0
25.4
dB
0.84
dB
o
1
fjam=850MHz
C
Noise Figure with jammer
Inband input
1dB-compression point
IIP3oob
in
Out-of-band input
w
3rd-order intercept point
a
IIP2oob
IIP2oob
H2-input
Out-of-band input
2nd-order intercept point
Out-of-band input
2nd-order intercept point
LTE band-13 2nd Harmonic
referred
ton
turn-on time
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fjam= 1850MHz
f1=1712.7MHz[3];
f2=1850MHz;
Pin=-20dBm;
f1=1712.7MHz[3];
f2=1850MHz;
Pin=-30dBm;
f1=824.6MHz[4];
f2=2400MHz;
Pin=-20dBm
f1=824.6MHz[4];
f2=2400MHz;
Pin=-30dBm
f=787.76MHz;
Pin=-25dBm;
fH2=1575.52MHz
Out-of-band input
3rd-order intercept point
IIP3oob
Pjam=-20dBm;
f=1575.42MHz
ic
IP1dB
time from VEN ON to
90% of the final gain
13
dB
14.2
Pjam=-20dBm;
NFj
18.7
12.0
Zs=50 ohm;
Stability factor
V
dB
No jammer
Kf
18.0
0.45
5.2
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Power Gain
V
n
0.80
AC ELECTRICAL CHARACTERISTICS
Gp
6.0
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DC ELECTRICAL CHARACTERISTICS
l
PARAMETER
0.72
1.10
dB
1.14
1.50
dB
-9.0
-7.6
dBm
+4.0
+6.1
dBm
+4.5
+6.5
dBm
-2.0
-1.2
dBm
-2.0
-1.2
dBm
-74.4
-70.0
dBm
2.2
2.5
μs
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
PARAMETER
toff
TEST CONDITION
turn-off time
MIN
time from VEN OFF to
10% of the gain
TYP
MAX
UNIT
1.7
2.0
μs
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Note1: input matched to 50 ohm using a high quality‐factor 9.1nH inductor.
Note2: 0.08dB PCB losses are subtracted.
Note3: IIP3=0.5*(Po_f1-IM3)+Pi_f1.
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Note4: IIP2=Po_f2+Pi_f2-IM2.
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APPLICATION BOARD
Figure 3.
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Drawing of Application Board
14
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
Copper
35um
n
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FR4
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Vias
Application Board Cross-Section
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Figure 4.
e
AW5005DNRZ_application_board_sideview
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15
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
TEST CIRCUITS
RFOUT
5
2
EN
BIAS
RFIN
RF INPUT
RF OUTPUT
n
6
e
GND
AW5005
1
fi
d
GND
3
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The following is the test bench for power supply, pin voltage, supply current, standby current
l
DC Characteristics
LOGIC
CONTROL
SUPPLY
VOLTAGE
L2
VCC
(optional)
4
n
L1
C1
o
(optional)
C
C1, L2 Closed to LNA
S Parameter
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The following is the test bench for input return loss, output return loss, reverse isolation, forward gain, and
1dB gain compression.
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RF
AW5005 EVB
INPUT
RF
OUTPUT
NetWork Analyzer
16
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
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Noise Figure
The following is the test bench for noise figure, power gain.
AW5015 EVB
AW5005
RF
OUTPUT
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RF
INPUT
n
Noise Analyzer
Intermodulation distortion
C
o
The following is the test bench for third-order intercept point and second-order intercept point.
Signal
Generator
ic
Circulator
Circulator
w
in
Signal
Generator
Power
Combiner
RF
OUTPUT AW5005 EVB
RF
INPUT
a
Signal Analyzer
Harmonic distortion
The following is the test bench for second-order harmonic distortion.
Signal
Generator
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RF
INPUT
AW5005
EVB
17
RF
OUTPUT
Notch Filter
Signal
Analyzer
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
RECOMMENDED COMPONENTS LIST
Table1: list of inductor for GNSS L1
Units
nH
LQW15A
9.1
25
250
Murata
0402
9.1
24
250
Sunlord
0402
100
20
150
Murata
0402
SDWL1005C
L1
LQW15A
L2
MHz
Component Part Number
Capacitance
pF
GRM155
1000
Rated Voltage
Supplier
Size
Murata
0402
V
50
o
n
Units
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Table2: list of capacitor
C1
Size
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L1
Inductance Q(min) Q Test Frequency Supplier
n
Part Number
e
Component
l
Table1 lists the recommended inductor types and values; Table 2 lists the recommended capacitor types
and values.
C
PCB LAYOUT CONSIDERATION
The AW5005 requires only one external inductor for input matching. If the device/phone manufacturers
implement very good power supply filtering on their boards, the bypass capacitor mentioned in this
application circuit may be optional. With the capacitor we can get better performance like a little higher
gain etc. The value is optimized for the best gain, noise figure, return loss performance. Typical value of
inductor is 9.1nH, capacitor is 1nF. For schematics see Figure1.
2.
The output of AW5005 is internally matched to 50 ohm and a DC blocking capacitor is integrated on-chip,
thus no external component is required at the output.
3.
The AW5005 should be placed close to the GPS antenna with the input-matching inductor. Use 50 ohm
micro strip lines to connect RF INPUT and RF OUTPUT. Bypass capacitor should be located close to the
device. For long VCC lines, it may be necessary to add more decoupling capacitors. Proper grounding of
the GND pins is very important.
a
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1.
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18
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
TAPE AND REEL INFORMATION
TAPE DIMENSIONS
REEL DIMENSIONS
P1
P0
P2
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K0
W
B0
D1
A0
e
n
Cavity
fi
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A0：Dimension designed to accommodate the component width
B0：Dimension designed to accommodate the component length
K0：Dimension designed to accommodate the component thickness
W：Overall width of the carrier tape
P0：Pitch between successive cavity centers and sprocket hole
P1：Pitch between successive cavity centers
P2：Pitch between sprocket hole
D1：Reel Diameter
D0：Reel Width
o
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D0
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QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
a
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Q1
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19
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
PACKAGE DESCRIPTION
1.00
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Pin 1
Indicator
fi
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n
1.50
n
0.55±0.05
0.152
0.05
0.55±0.05
C
5X(0.35±0.05)
o
0.00~0.05
5X 0.15
4X 0.15
4
ic
3
0.00~0.05
0.50
6X(0.20±0.05)
1
0.10
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M
6
0.10
0.10
0.152
0.40±0.05
a
w
in
0.10 Ty p.
Unit：mm
20
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
LAND PATTERN DATA
l
1.20
1
6
℄
n
SYMM
1.20
6X0.20
ti
a
6X0.50
fi
d
4
3
SYMM
℄
0.05 MIN
All AROUND
n
0.05 MAX
All AROUND
o
SOLDER MASK
OPENING
C
METAL
e
0.50
ic
NON SOLDER MASK DEFINED
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK DEFINED
a
w
in
Unit: mm
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21
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
REVISION HISTORY
Release date
AW5005_V1.4
2019-5
Updated S11 AND S22 OF L1 BAND
AW5005_V1.3
2019-5
Updated SP AND NF OF L1/L2/L5 BAND
Updated S21
OF L1S21
BAND
Added
AND NF OF L2/L5 BAND
Added S21 AND
NFS21
OFAND
L2/L5
BAND
Added
NF
OF L2/L5 BAND
Updated TAPE AND REEL INFORMATION
Updated PACKAGE DESCRIPTION
Updated LAND PATTERN DATA
Updated the Awinic logo
2016-12
Officially Released
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AW5005_V1.0
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2019-2
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AW5005_V1.1
e
2019-5
fi
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AW5005_V1.2
Change Record
l
Document ID
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22
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW5005
May. 2019 V1.4
DISCLAIMER
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Information in this document is believed to be accurate and reliable. However, Shanghai AWINIC
Technology Co., Ltd (AWINIC Technology) does not give any representations or warranties, expressed or
implied, as to the accuracy or completeness of such information and shall have no liability for the
consequences of use of such information.
n
AWINIC Technology reserves the right to make changes to information published in this document, including
without limitation specifications and product descriptions, at any time and without notice. Customers shall
obtain the latest relevant information before placing orders and shall verify that such information is current
and complete. This document supersedes and replaces all information supplied prior to the publication
hereof.
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AWINIC Technology products are not designed, authorized or warranted to be suitable for use in medical,
military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an
AWINIC Technology product can reasonably be expected to result in personal injury, death or severe
property or environmental damage. AWINIC Technology accepts no liability for inclusion and/or use of
AWINIC Technology products in such equipment or applications and therefore such inclusion and/or use is
at the customer’s own risk.
o
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Applications that are described herein for any of these products are for illustrative purposes only. AWINIC
Technology makes no representation or warranty that such applications will be suitable for the specified use
without further testing or modification.
All products are sold subject to the general terms and conditions of commercial sale supplied at the time of
order acknowledgement.
C
Nothing in this document may be interpreted or construed as an offer to sell products that is open for
acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other
industrial or intellectual property rights.
ic
Reproduction of AWINIC information in AWINIC data books or data sheets is permissible only if reproduction
is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices.
AWINIC is not responsible or liable for such altered documentation. Information of third parties may be
subject to additional restrictions.
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Resale of AWINIC components or services with statements different from or beyond the parameters stated
by AWINIC for that component or service voids all express and any implied warranties for the associated
AWINIC component or service and is an unfair and deceptive business practice. AWINIC is not responsible
or liable for any such statements.
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23
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