BTHQ128064AVD1-COG-FSTF-12-LEDWHITE

Specification BT45228 BTHQ128064AVD1-FSTF-12-LEDWHITE-COG Doc. No.: COG-BTD12864-42 Version November 2010 DOCUMENT REVISION HISTORY: DOCUMENT DATE DESCRIPTION REVISION FROM TO A 2010.11.02 First Release. CHANGED BY CHECKED BY LI WEI CHI SHAO BO Based on: a.) VL-QUA-012B REV.Y 2010.12.10 According to VL-QUA-012B, LCD size is small because Unit Per Laminate=24 which is more than 6pcs/Laminate. 2 CONTENTS Page No. 1. GENERAL DESCRIPTION 4 2. MECHANICAL SPECIFICATIONS 4 3. INTERFACE SIGNALS 7 4. 4.1 4.2 ABSOLUTE MAXIMUM RATINGS ELECTRICAL MAXIMUM RATINGS – FOR IC ONLY ENVIRONMENTAL CONDITION 9 9 10 5. 5.1 5.2 5.3 5.4 5.5 5.6 ELECTRICAL SPECIFICATIONS TYPICAL ELECTRICAL CHARACTERISTICS APPENDIX – LED CHROMATICS COORDINATES TIMING SPECIFICATIONS COMMAND TABLE INITIAL CODE SETTING (FOR REFERENCE ONLY) REFERENCE CIRCUIT 11 11 11 12 15 16 16 6. 6.1 6.2 ELECTRO-OPTICAL CHARACTERISTICS ISO PLOT OPTICAL CHARACTERISTICS DEFINITION 17 17 18 7. LCD COSMETIC CONDITIONS 19 8. REMARK 19 3 Specification of LCD Module Type Model No.: COG-BTD12864-42 1. General Description • • • • • • • • 2. 128 x 64 Dots FSTN Positive Black & White Transflective Dot Matrix LCD Module. Viewing Angle: 12 o’clock direction. Driving duty: 1/65 Duty, 1/7 bias. ‘SITRONIX’ ST7565P (COG) Dot Matrix LCD Driver or equivalent. Logic voltage: 3.3V. FPC connection. White LED02 backlight. “RoHS” compliance. Mechanical Specifications The mechanical detail is shown in Fig. 2 and summarized in Table 1 below. Table 1 Parameter Outline dimensions Viewing area Active area Display format Dot size Dot spacing Dot pitch Weight Specifications 55.6(W) x 70.2(H) x 4.42(D) (Included FPC. Excluded pins) 50.60(W) x 31.0(H) 46.577(W) x 27.697(H) 128(W) x 64(H) 0.349(W) x 0.418(H) 0.015(W) x 0.015(H) 0.364(W) x 0.433(H) Approx: 14 Unit mm mm mm dots mm mm mm grams 4 Figure 1: Module Specification 5 32 COG-BTD12864-42 LCD GRAPHIC DISPLAY 32 128 128X64 DOTS RES CS1 D/C R/W(WR) E(RD) D7~D0 VDD 8 LCD DRIVER & CONTROLLER VSS VOUT "SITIRONIX" ST7565P C3+ C1+ C1C2C2+ V0 V1 V2 V3 V4 C86 P/S A WHITE LED02 BACKLIGHT K Figure 3: Block Diagram. 6 3. Interface signals Table 2(a): Pin Assignment Pin No. Symbol Description This pin configures the interface to be parallel mode or serial mode. P/S = “H”: Parallel data input/output. P/S = “L”: Serial data input. 1 P/S The following applies depending on the P/S status: P/S Data/Command Data Read/Write _____ _____ “H” D/C D0 to D7 RD, WR “L” D/C D7 Write only When P/S = “L”, D0 to D5 must be fixed to “H”. _____ 2 C86 3 4 5 6 V0 V1 V2 V3 7 V4 8 C2- 9 C2+ 10 C1+ 11 C1- 12 C3+ 13 VOUT 14 15 VSS VDD Serial Clock X D6 _______ RD (E) and WR (R/W) are fixed to either “H” or “L”. The serial access mode does NOT support read operation. This is the MPU interface selection pin. C86 = “H”: 6800 Series MPU interface. C86 = “L”: 8080 Series MPU interface. This is a multi-level power supply for the liquid crystal drive. The voltage supply applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through changing the impedance using an op. amp. Voltage levels are determined based on VSS, and must maintain the relative magnitudes shown below. V0≧V1≧V2≧V3≧V4≧VSS When the power supply turns ON, the internal power supply circuits produce the V1 to V4 voltages shown below. The voltage settings are selected using the LCD bias set command. For 1/7 bias: V1= 6/7 * V0, V2=5/7 * V0, V3=2/7 *V0, V4=1/7 * V0. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2P terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2N terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1P terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N terminal. DC/DC voltage converter. Connect a capacitor between this terminal and VSS or VDD. Ground. Power supply pins for logic. 7 Table 2(b): Pin Assignment Pin No. 16 17 18 19 20 21 22 23 Symbol D7 D6 D5 D4 D3 D2 D1 D0 Description This is an 8-bit bi-directional data bus that connects to an 8-bit standard MPU data bus. When the serial interface is selected (P/S = LOW), then D7 serves as the serial data input terminal (SI) and D6 serves as the serial clock input terminal (SCL). At this time, D0 to D5 are set to high impedance. When the chip select is inactive, D0 to D7 are set to high impedance. ______ 24 _____ E(RD) When connected to 8080 series MPU, this pin is treated as the “RD ” signal of the 8080 MPU and is LOW-active. The data bus is in an output status when this signal is “L”. When connected to 6800 series MPU, this pin is treated as the “E” signal of the 6800 MPU and is HIGH-active. This is the enable clock input terminal of the 6800 Series MPU. ______ When connected to 8080 series MPU, this pin is treated as the “WR” signal of the 8080 MPU and is LOW-active. ______ 25 26 27 The signals on the data bus are latched at the rising edge of the WR signal. R/W(WR) When connected to 6800 series MPU, this pin is treated as the “R/W” signal of the 6800 MPU and decides the access type : When R/W = “H”: Read. When R/W = “L”: Write. This is connect to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or command. D/C D/C = “H”: Indicates that D0 to D7 are display data. D/C= “L”: Indicates that D0 to D7 are control data. _______ This is the chip select signal. When /CS1 = “L”, then the chip select CS1 becomes active, and data/command I/O is enabled. _____ ________ 28 _______ RES When RES is set to “L”, the register settings are initialized (cleared). The reset operation is performed by the /RES signal level. 8 4. Absolute Maximum Ratings 4.1 Electrical Maximum Ratings – for IC Only Table 3 Parameter Power Supply voltage (Logic) Power Supply voltage (VDD2) Power Supply voltage (V0, VOUT) Power Supply voltage (V1, V2, V3, V4) Symbol VDD VDD2 V0, VOUT V1, V2, V3, V4 Min. +0.3 +0.3 +0.3 V0 Max. +3.6 +3.6 +14.5 +0.3 Unit V V V V Note: 1. The VDD2, V0 to V4 and VOUT are relative to the VSS = 0V reference. 2. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VOUT ≧ V0 ≧ V1 ≧ V2 ≧ V3 ≧ V4. 3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover, it is recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of the LSI outside of these conditions may not only result in malfunctions of the LSI, but may have a negative impact on the LSI reliability as well. Figure 3 9 4.2 Environmental Condition Table 4 Item Operating Temperature (Topr) Storage Temperature (Tstg) (Note 1) Min. Max. -20°C +65°C Min. Max. Ambient Temperature 0°C +50°C 90% max. RH for Ta ≤ 40°C Humidity (Note 1) < 50% RH for 40°C < Ta ≤ Maximum operating temperature Vibration (IEC 68-2-6) Frequency: 10 ∼ 55 Hz cells must be mounted on Amplitude: 0.75 mm a suitable connector Duration: 20 cycles in each direction. Pulse duration: 11 ms Shock (IEC 68-2-27) Peak acceleration: 981 m/s2 = 100g Half-sine pulse shape Number of shocks: 3 shocks in 3 mutually perpendicular axes. Note 1: Product cannot sustain at extreme storage conditions for long time. Remark Dry No condensation 3 directions 3 directions 10 5. Electrical Specifications 5.1 Typical Electrical Characteristics At Ta = +25 °C, VDD = +3.3± ±5%, VSS = 0V. Table 5 Parameter Supply voltage (Logic) Supply voltage (LCD) (built-in) Low-level input signal voltage High-level input signal voltage Supply Current (Logic & LCD) Symbol VDD-VSS Conditions VLCD =V0-VSS VILC Ta = 0 °C, Character mode, VDD = +3.3V, Note 1 Ta = 25 °C, Character mode, VDD = +3.3V, Note 1 Ta = +50 °C, Character mode, VDD = +3.3V, Note 1 Note 2 VIHC Note 2 IDD VDD = +3.3V,Note 1, Character mode VDD = +3.3V,Note 1, Checker board mode Min. Typ. Max. Unit 3.14 3.3 3.47 V - 8.9 - V 8.5 8.8 9.1 V - 8.5 - V VSS - 0.2xVDD V 0.8xVDD - VDD V - 0.46 0.69 mA - 0.78 1.2 mA Supply current of Forward current White LED02 VLED 3.2 3.6 4.0 = 2 x 15mA backligh Luminance (on the Number of LED dice 495 backlight surface) of =2dies. backlight Note 1: There is tolerance in optimum LCD driving voltage during production and it will be within the specified range. ______ _______ ______ V cd/m2 _______ Note 2: D/C, D0 to D5, D6, D7, E( RD ),R/W( WR ),CS1,C86,P/S,RES terminals. Note 3: Do not display a fixed pattern for more than 30 min. because it may cause image sticking due to LCD characteristics. It is recommended to change display pattern frequently. If customer must fix display pattern on the screen, please consider to activate screen saver. 5.2 Appendix - LED Chromatics Coordinates Figure 4 11 5.3 Timing Specifications System Bus read/Write Characteristics 1 (For the 8080 Series MPU) At Ta = 0 °C to +50 °C, VDD = +3.3V± ±5%, VSS = 0V. Table 6 Figure 5: The timing diagram of system bus read/write (For the 8080 Series MPU) 12 System Bus read/Write Characteristics 2 (For the 6800 Series MPU) At Ta =0 °C to +50 °C, VDD = +3.3V± ±5%, VSS = 0V. Table 7 Figure 6: The timing diagram of system bus read/write (For the 6800 Series MPU) 13 Reset Timing At Ta =0 °C to +50 °C, VDD = +3.3V± ±5%, VSS = 0V. Table 8 Figure 7: Reset Timing 14 5.4 Command Table Table 9 15 5.5 Initial code setting (for reference only) Table 10 Description Setting data Reset 0xe2 LCD bias set 0xa3 ADC select 0xa0 Common output mode select 0xc8 V5 voltage regulator internal resistor ratio set 0x25 Electronic volume mode set 0x81 Electronic volume Power control set 0x13 0x25 Display start line set 0x40 Page address set 0xb0 Column address upper bit set 0x10 Column address lower bit set 0x04 Display all point ON/OFF 0xa4 Display normal or reverse 0xa6 5.6 Reference circuit 16 6. Electro-Optical Characteristics Table 11 Item Symbol Driving voltage Vop Temp. °C Min. +25 - Ton Max. - 202 303 +25 Response time Optimum viewing area Cr ≥ 2 - Value Typ. 8.8 Toff - 85 128 θ1(6 o’clock) θ2(12 o’clock) φ1(3 o’clock) φ2(9 o’clock) 27 21 28 31 38 30 40 30 - +25 Unit Condition V Vop= optimum voltage msec Vop= Optimum voltage θ = 0°, φ = 0° φ = 0° DEG θ = 0° Vop= Optimum voltage (Remark 1) Vop = Optimum voltage θ = 0°, φ = 0° Transmittance +25 13% 19% Vop = Optimum voltage Remark 1: Due to hardware limitation, the maximum measurable angle is 50 O Contrast ratio 6.1 Cr +25 3 4.7 - ISO plot 17 6. 2 Optical Characteristics Definition a.) Viewing Angle b.) Contrast Ratio B1 = segments luminance in case of non-selected waveform B2 = segments luminance in case of selected waveform Non-selected dot Contrast Ratio is defined by Cr = B2/B1 Luminance 100% B2 Selected dot Select waveform Non-select waveform B1 Vop c.) Response Time Non-selecected condition Selected Condition 90 % 10 % 100 % Luminance Non-selecected condition Ton rise time Toff fall time 18