Rev 1.0
F60C1A0004-M7
ial
t
n
de
fi
n
Co
ys
s
g
n
Lo
fi
n
Co
ti
n
e
d
al
4Gb DDR3L Datasheet
F60C1A0004-M7
Series
ys
s
g
n
Lo
M-00131
Rev 1.0
tial
den
i
f
n2019-09
Co
s
y
s
g
www.longsys.com
n
Lo
Longsys Electronics
Page 1
Rev 1.0
F60C1A0004-M7
ial
t
n
de
Revision History:
fi
n
Co
Rev.
Date
Change
1.0
2019/09
Basic spec and architecture
Remark
ys
s
g
n
Lo
NOTE: INFORMATION IN THIS PRODUCT SPECIFICATION IS SUBJECT TO CHANGE AT ANYTIME WITHOUT NOTICE, ALL PRODUCT
SPECIFICATIONS ARE PROVIDED FOR REFERENCE ONLY.TO ANY INTELLECTUAL, PROPERTY RIGHTS IN LONGSYS ELECTRONICS CO.,LTD.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED.
fi
n
Co
ti
n
e
d
al
ys
s
g
n
Lo
al
i
t
en
d
nfi
o
C
s
y
s
g
www.longsys.com
n
Lo
Longsys Electronics
Page 2
Rev 1.0
F60C1A0004-M7
ial
t
n
de
fi
n
Co
Contents
1.
INTRODUCTION .................................................................................................................................................................... 5
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
2.
General Description ............................................................................................................................................................................. 5
Device Features ..................................................................................................................................................................................... 5
Product List ............................................................................................................................................................................................. 6
Connection Diagram ............................................................................................................................................................................ 7
Pin Description ...................................................................................................................................................................................... 8
System Block Diagram ..................................................................................................................................................................... 12
ys
s
g
n
Lo
COMMAND OPERATION .................................................................................................................................................. 13
2.1.
2.2.
2.3.
2.4.
2.5.
2.6.
2.7.
2.8.
2.9.
2.10.
2.11.
2.12.
2.13.
fi
n
Co
3.
ti
n
e
d
al
Electrical Characteristic ................................................................................................................................................. 16
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
3.7.
3.8.
3.9.
3.10.
3.11.
3.12.
3.13.
3.14.
3.15.
3.16.
3.17.
3.18.
3.19.
4.
Command Sets .................................................................................................................................................................................... 13
No Operation Command [NOP] ................................................................................................................................................... 14
Device Deselect Command [DESL]............................................................................................................................................. 14
Mode Register Set Command [MR0 to MR3] ......................................................................................................................... 14
Bank Activate Command [ACT] ................................................................................................................................................... 14
Read Command [READ, RDS4, RDS8, READA, RDAS4, RDAS8] ..................................................................................... 14
Write Command [WRIT, WRS4, WRS8, WRITA, WRAS4, WRAS8] ............................................................................... 14
Precharge Command [PRE, PALL] .............................................................................................................................................. 14
Auto precharge Command [READA, WRITA] ........................................................................................................................ 14
Auto-Refresh Command [REF] .................................................................................................................................................... 15
Self-Refresh Command [SELF]..................................................................................................................................................... 15
ZQ calibration Command [ZQCL, ZQCS] ................................................................................................................................... 15
CKE Truth Table ................................................................................................................................................................................. 15
Absolute Ratings ................................................................................................................................................................................ 16
Operating Temperature Condition ............................................................................................................................................. 16
Recommended DC Operating Conditions ............................................................................................................................... 16
1.35V DDR3L AC and DC Logic Input Levels for Single-Ended Signals ...................................................................... 17
1.35V DDR3L Electrical Characteristics and AC Timing ................................................................................................... 17
Address / Command Setup, Hold and Derating ................................................................................................................... 17
Data Setup, Hold and Slew Rate Derating ............................................................................................................................... 17
Overshoot and Undershoot Specifications ............................................................................................................................. 17
1.35V DDR3L Output Driver DC Electrical Characteristics ............................................................................................. 17
1.35V DDR3L On-Die Termination (ODT) Levels and I-V Characteristics ................................................................ 17
1.35V DDR3L Single Ended Output Slew Rate ...................................................................................................................... 17
1.35V Differential Output Slew Rate ......................................................................................................................................... 17
1.35V DDR3L AC and DC Logic Input Levels for Differential Signals.......................................................................... 17
Differential Input Cross point voltage ...................................................................................................................................... 17
DQS Output Cross point voltage .................................................................................................................................................. 17
DC Characteristics ............................................................................................................................................................................. 18
Pin Capacitance(TC = 25°C, VDD, VDDQ = 1.35V ) .............................................................................................................. 19
Standard Speed Bins ........................................................................................................................................................................ 20
AC Timing Characteristics ............................................................................................................................................................. 23
ys
s
g
n
Lo
al
i
t
en
fid
n
Simplified State Diagram................................................................................................................................................................
38
Co
RESET and Initialization Procedure ..........................................................................................................................................
39
Functional Description and Timing ........................................................................................................................... 38
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
Programming the Mode Register ................................................................................................................................................ 40
DDR3 SDRAM Mode Register 0 [MR0] ..................................................................................................................................... 42
DDR3 SDRAM Mode Register 1 [MR1] ..................................................................................................................................... 43
DDR3 SDRAM Mode Register 2 [MR2] ..................................................................................................................................... 44
DDR3 SDRAM Mode Register 3 [MR3] ..................................................................................................................................... 45
Extended Temperature Usage ...................................................................................................................................................... 45
s
y
s
g
www.longsys.com
n
Lo
Longsys Electronics
Page 3
Rev 1.0
F60C1A0004-M7
ial
t
n
de
4.9.
4.10.
4.11.
4.12.
4.13.
4.14.
4.15.
4.16.
4.17.
4.18.
4.19.
4.20.
5.
fi
n
Refresh Command .............................................................................................................................................................................
46
Co
Self-Refresh Operation .................................................................................................................................................................... 47
DLL-off Mode ....................................................................................................................................................................................... 49
DLL on/off switching procedure ................................................................................................................................................ 49
Input clock frequency change ...................................................................................................................................................... 49
Write Leveling ..................................................................................................................................................................................... 49
Multi Purpose Register ................................................................................................................................................................... 49
Read Operation ................................................................................................................................................................................... 49
Write Operation ................................................................................................................................................................................. 49
Power-Down Modes ......................................................................................................................................................................... 49
On-Die Termination (ODT) ............................................................................................................................................................ 49
ZQ Calibration ..................................................................................................................................................................................... 49
ys
s
g
n
Lo
Physical Diagram .............................................................................................................................................................. 50
5.1.
5.2.
fi
n
Co
al
FBGA 78-ball ×8bit............................................................................................................................................................................ 50
FBGA 96-ball ×16bit ......................................................................................................................................................................... 51
ti
n
e
d
ys
s
g
n
Lo
al
i
t
en
d
nfi
o
C
s
y
s
g
www.longsys.com
n
Lo
Longsys Electronics
Page 4
Rev 1.0
F60C1A0004-M7
ial
t
n
de
fi
n
Co
1. INTRODUCTION
1.1. General Description
The FORESEE DDR3L SDRAM (1.35V) is a low voltage version of the DDR3 (1.5V) SDRAM. Refer to the DDR3 (1.5V) SDRAM datasheet
specifications when running in 1.5V compatible mode.
1.2. Device Features
ys
s
g
n
Lo
Density: 4G bits
The high-speed data transfer is realized by the 8bits
Organization
prefetch pipelined architecture
l x 8 bits
- 8 banks x 64M
iawords
t
n
- 8 banks
dex 32M words x 16 bits
i
f
n
Package
Co
Double data-rate architecture: two data transfers per clock
cycle
Bi-directional differential data strobe (DQS and DQS#) is
- 78-ball FBGA
transmitted/received with data for capturing data at
- 96-ball FBGA
the receiver
Lead-free(RoHS compliant) and Halogen-free
DQS is edge-aligned with data for READs; center aligned
Power supply
with data for WRITEs
- VDD, VDDQ =1.35V (1.283 to 1.45V)
Differential clock inputs (CK and CK#)
- Backward compatible DDR3 (1.5V) operation
DLL aligns DQ and DQS transitions with CK transitions
Data Rate: 1600Mbps/1866Mbps/2133Mbps
Commands entered on each positive CK edge; data and data
1KB page size (x8)
mask referenced to both edges of DQS
- Row address: AX0 to AX15
Data mask (DM) for write data
- Column address: AY0 to AY9
Posted CAS by programmable additive latency for better
2KB page size (x16)
command and data bus efficiency
- Row address: AX0 to AX14
On-Die Termination (ODT) for better signal quality
- Column address: AY0 to AY9
- Synchronous ODT
Eight internal banks for concurrent operation
- Dynamic ODT
Burst lengths(BL): 8 and 4 with Burst Chop(BC)
- Asynchronous ODT
Burst type(BT)
Multi Purpose Register (MPR) for pre-defined pattern read
ys
s
g
n
ZQ calibration for DQ drive and
LoODT Access
- Sequential (8, 4 with BC)
out
- Interleave (8, 4 with BC)
CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
Programmable partial array self-refresh (PASR)
CAS Write Latency (CWL): 5, 6, 7, 8, 9, 10
RESET pin for Power-up sequence and reset function
Precharge: auto precharge option for each burst access
SRT(Self Refresh Temperature) range
- Normal/Extended/ASR
al
i
t
en
Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)
Refresh: auto-refresh, self-refresh
Average refresh period
- 7.8us at TC ≤ +85℃
- 3.9us at TC > +85℃
d
nfi
o
C
Programmable output driver impedance control
JEDEC compliant DDR3
RH-Free(Row Hammer Free) option is available
Operating temperature range
- TC = 0°C to +85°C (Commercial grade)
s
y
s
g
www.longsys.com
n
Lo
Longsys Electronics
Page 5
Rev 1.0
F60C1A0004-M7
ial
t
n
de
fi
n
Co
[Table 1]Key Timing Parameters
Data Rate(Mbps)
2133
1866
1600
CL
14
13
11
[Table 2] Product List
i
t
n
de
tRP
14
13
11
ys
s
g
n
Lo
1.3. Product List
Part Number
F60C1A0004-M7 9R
tRCD
14
13
11
Density
4Gb
Package Type
FBGA 96
Organization
×16bit
Package Size(mm)
7.5*13.5
VCC Range
1.283V ~ 1.45V
Data Rate(Mbps)
1866
al
fi
n
o
Part Number Chart
CMarketing
F
60 C
1
A 0004
-
M7
X
X
Brand
F=FORESEE
Product Family
Brand
R=0~85℃
60= 1.35V DDR3
Data Rate
8 = 1600 Mbps
9 = 1866 Mbps
A = 2133 Mbps
Package Type
C= FBGA 96(7.5mm*13.5mm)
Dram
ys Type
s
g
n
Lo Hyphen
DIE stack number
1= *1
2= *2
3= *3
Width
8= 8bit
A= 16bit
de
i
f
n
tial
n
Co
Density
0001= 1Gb
0002= 2Gb
0004= 4Gb
Figure 1 Part Number
s
y
s
g
www.longsys.com
n
Lo
Longsys Electronics
Page 6
Rev 1.0
F60C1A0004-M7
ial
t
n
de
fi
n
Co
1.4. Connection Diagram
ys
s
g
n
Lo
fi
n
Co
i
t
n
de
al
Figure 2 78ball FBGA(x8 organization) top view
Figure 3 96ball FBGA(x16 organization) top view
ys
s
g
n
Lo
al
i
t
en
d
nfi
o
C
s
y
s
g
www.longsys.com
n
Lo
Longsys Electronics
Page 7
Rev 1.0
F60C1A0004-M7
ial
t
n
de
fi
n
Co
1.5. Pin Description
[Table 3] 78-Ball FBGA – x8 Ball Descriptions
Symbol
Type
Description
A[15:13], A12, A11,
A10/AP, A[9:0]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto
precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs
also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12
is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4).
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE
command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded
during the LOAD MODE command. BA[2:0] are referenced to VREFCA.
Input
Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the
crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is
referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks
on the DRAM. The specific circuitry that is enabled/ disabled is dependent upon the DDR3 SDRAM
configuration and operating mode.
Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),
or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and
for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE,
RESET#, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are
disabled during SELF REFRESH. CKE is referenced to VREFCA.
CS#
Input
fi
n
Co
ial
t
n
deCK, CK#
ys
s
g
n
Lo
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All
commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems
with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA.
Input
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled
HIGH along with the input data during a write access.
Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM
is referenced to VREFDQ. DM has an optional use.
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination
resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each
of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4.
The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are
referenced to VREFCA.
DM
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS
input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and DC LOW ≤ 0.2 × VDDQ. RESET#
assertion and desertion are asynchronous.
ys
s
g
n
Lo
al
i
t
en
d
nfi
o
C
s
y
s
g
www.longsys.com
n
Lo
Longsys Electronics
Page 8
Rev 1.0
F60C1A0004-M7
ial
t
n
de
fi
n
Co
[Table 4] 78-Ball FBGA –x8 Ball Descriptions (Continued)
Symbol
Description
DQ[7:0]
I/O
Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to
VREFDQ.
DQS, DQS#
I/O
Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned
to write data.
VDD
Supply
VDDQ
Supply
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA must be maintained at all times(including
self refresh) for proper device operation.
Supply
Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper
device operation.
Supply
Ground.
tial
VREFDQ
Co
Type
enVSS
d
i
nf
ys
s
g
n
Lo supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity.
DQ power
Power supply: 1.5V ±0.075V.
ZQ
Reference
External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ),
which is tied to VSSQ.
NC
–
No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other
balls).
ys
s
g
n
Lo
al
i
t
en
d
nfi
o
C
s
y
s
g
www.longsys.com
n
Lo
Longsys Electronics
Page 9
Rev 1.0
F60C1A0004-M7
ial
t
n
de
fi
n
Co
[Table 5] 96-Ball FBGA – x16 Ball Descriptions
Symbol
Type
Description
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto
precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs
also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12
is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4).
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE
command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded
during the LOAD MODE command. BA[2:0] are referenced to VREFCA.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the
crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is
referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks
on the DRAM. The specific circuitry that is enabled/ disabled is dependent upon the DDR3 SDRAM
configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is synchronous
for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input
buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during POWER-DOWN. Input buffers
(excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All
commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems
with multiple ranks. CSB is considered part of the command code. CS# is referenced to VREFCA.
DML
Input
Input data mask: DML is a lower-byte, input mask signal for write data. Lower-byte input data is masked
when DML is sampled HIGH along with the input data during a write access.
Although the DML ball is input-only, the DML loading is designed to match that of the DQ and DQS balls.
DML is referenced to VREFDQ.
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
Term ination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to each of the following balls: DQL/DQU[7:0], DQSL, DQSL#,
DQSU,DQSU#, DML, and DMU for the x16. The ODT input is ignored if disabled via the LOAD MODE
command. ODT is referenced to VREFCA.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#,and WEB (along with CS#) define the command being entered and are
referenced to VREFCA.
RESET#
Input
A[15:13], A12, A11, A10,
A[9:0]
fi
n
Co
i
t
n
de
al
s
y
s
g
www.longsys.com
n
Lo
ys
s
g
n
Lo
ys
s
g
n
Lo
al
i
t
nCMOS input referenced to VSS. The RESET# input receiver is a CMOS
Reset: RESET# is an active LOW
designal
i
input defined as a rail-to-rail
with DC HIGH ≥ 0.8 × VDD and DC LOW ≤ 0.2 × VDDQ. RESET#
f
nare asynchronous.
assertion and desertion
o
C
Longsys Electronics
Page 10
Rev 1.0
F60C1A0004-M7
ial
t
n
de
fi
n
Co
[Table 6] 96-Ball FBGA –x16 Ball Descriptions (Continued)
Symbol
DMU
fi
n
Co
Type
Description
Input
Input data mask: DMU is an upper-byte, input mask signal for write data. Upper byte input data is
masked when DMU is sampled HIGH along with that input data during a WRITE access.
Although the DMU ball is input-only, the DMU loading is designed to match that of the DQ and DQS balls.
DMU is referenced to VREFDQ.
DQL[7:0]
I/O
ys
s
g
Data input/output:
n Bidirectional data bus for the x16 configuration. DQL[7:0] are referenced to VREFDQ.
Lo
DQU[7:0]
I/O
Data input/output: Bidirectional data bus for the x16 configuration. DQU[7:0] are referenced to VREFDQ.
DQSL, DQSL#
I/O
al
Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned
to write data.
DQSU, DQSU#
I/O
Data strobe: Output with read data. Edge-aligned with read data. Input with write data. DQS is Centeraligned to write data.
VDD
Supply
Power supply: 1.5V ±0.075V.
VDDQ
Supply
DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity.
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA must be maintained at all times(including
self refresh) for proper device operation.
VREFDQ
Supply
Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper
device operation.
VSS
Supply
Ground.
ZQ
Reference
External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ),
which is tied to VSSQ.
NC
–
No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other
balls).
i
t
n
de
ys
s
g
n
Lo
al
i
t
en
d
nfi
o
C
s
y
s
g
www.longsys.com
n
Lo
Longsys Electronics
Page 11
Rev 1.0
F60C1A0004-M7
ial
t
n
de
fi
n
Co
1.6. System Block Diagram
ys
s
g
n
Lo
fi
n
Co
i
t
n
de
al
Figure 4 512M×8 Functional Block Diagram
ys
s
g
n
Lo
al
i
t
en
fid
n
o Functional Block Diagram
Figure 5C
256M×16
s
y
s
g
www.longsys.com
n
Lo
Longsys Electronics
Page 12
Rev 1.0
F60C1A0004-M7
ial
t
n
de
fi
n
Co
2. COMMAND OPERATION
2.1. Command Sets
The DDR3 SDRAM recognizes the following commands specified by the CS#, RAS#, CAS#, WE# and address pins.
[Table 7] Command Truth Table
Co
PRE
PALL
ACT
WRIT
WRS4
WRS8
H
H
H
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
X
H
L
L
L
H
H
H
L
L
L
X
H
H
H
H
L
L
L
L
H
H
X
H
L
L
H
L
L
L
BA02
BA
V
V
X
V
BA
V
BA
BA
BA
BA
WRITA
H
H
L
H
L
L
BA
V
H
CA
WRAS4
H
H
L
H
L
L
BA
L
H
CA
WRAS8
H
H
L
H
L
L
BA
H
H
CA
READ
RDS4
RDS8
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
BA
BA
BA
V
L
H
L
L
L
CA
CA
CA
READA
H
H
L
H
L
H
BA
V
H
CA
RDAS4
H
H
L
H
L
H
BA
L
H
CA
RDAS8
H
H
L
H
L
H
BA
H
H
CA
NOP
DESL
H
H
H
H
L
L
H
H
H
H
L
L
H
H
H
H
L
H
H
L
H
L
L
L
H
X
X
H
X
H
H
H
H
X
X
H
X
H
H
H
H
X
X
H
X
H
L
L
V
X
X
V
X
V
X
X
V
X
X
V
X
V
X
X
V
X
X
V
X
V
H
L
V
X
X
V
X
V
X
X
Function
Symbol
Mode register set
Auto refresh
Self refresh entry
MRS
REF
SELF
Self refresh exit
SELEX
al
iprecharge
Single bank
t
n
Precharge
all banks
e activate
dBank
i
f
n Write(Fixed BL)
Write(BC4,on the fly)
Write(BL8,on the fly)
Write with auto precharge
(Fixed BL)
Write with auto precharge
(BC4,on the fly)
Write with auto precharge
(BL8,on the fly)
Read(Fixed BL)
Read(BC4,on the fly)
Read(BL8,on the fly)
Read with auto precharge
(Fixed BL)
Read with auto precharge
(BC4,on the fly)
Read with auto precharge
(BL8,on the fly)
No operation
Device deselect
ys
s
g
oCKEn
L
Previous Current
Power down mode entry
PDEN
Power down mode exit
PDEX
ZQ calibration long
ZQ calibration short
ZQCL
ZQCS
CS#
RAS#
CAS#
WE#
A12(/BS)
V
V
X
V
V
V
V
L
H
A10(AP)
op-code
V
V
X
V
L
H
RA
L
L
L
ys
s
g
n
Lo
A0A15
V
V
X
V
V
V
Note
6,8,11
6,8,7
11
12
CA
CA
CA
9
10
5,11
5,11
Remark:
[1] H = VIH; L = VIL; V =VIH or VIL(defined logical level).
[2] X = Don’t care (defined or undefined, including floating around VREF) logical level. [3] BA = Bank Address. RA = Row Address. CA = Column Address. /BC = Bust
Chop.
Notes:
[1] All DDR3 commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock. The most significant bit (MSB) of BA, RA, and CA are
device density and configuration dependent.
[2] RESET# is an active low asynchronous signal that must be driven high during normal operation.
[3] Bank Addresses (BA) determines which bank is to be operated upon. For MRS, BA selects a mode register.
[4] Burst READs or WRITEs cannot be terminated or interrupted and fixed/on the fly BL will be defined by MRS.
[5] The power-down mode does not perform any refresh operations.
[6] The state of ODT does not affect the states described in this table. The ODT function is not available during self-refresh.
[7] Self-refresh exit is asynchronous.
[8] VREF (both VREFDQ and VREFCA) must be maintained during self-refresh operation. VREFDQ supply may be turned off and VREFDQ may take any value between
VSS and VDD during self-refresh operation, provided that VREFDQ is valid and stable prior to CKE going back high and that first write operation or first write leveling
activity may not occur earlier than 512 nCK after exit from self-refresh.
[9] The No Operation command (NOP) should be used in cases when the DDR3 SDRAM is in an idle or a wait state. The purpose of the NOP command is to prevent the
DDR3 SDRAM from registering any unwanted commands between operations. A NOP command will not terminate a previous operation that is still executing, such as
a burst read or write cycle.
[10] The DESL command performs the same function as a NOP command.
[11] Refer to the CKE Truth Table for more detail with CKE transition.
[12]. No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW (ns) by tCK (ns) and rounding up to next integer
value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate
commands may be issued in clock N+1 through N+9.
al
i
t
en
d
nfi
o
C
s
y
s
g
www.longsys.com
n
Lo
Longsys Electronics
Page 13
Rev 1.0
F60C1A0004-M7
ial
t
n
de
fi
n
Co
2.2. No Operation Command [NOP]
The No Operation command (NOP) should be used in cases when the DDR3 SDRAM is in an idle or a wait state. The purpose of the NOP
command is to prevent the DDR3 SDRAM from registering any unwanted commands between operations. A NOP command will not
terminate a previous operation that is still executing, such as a burst read or write cycle.
The no operation (NOP) command is used to instruct the selected DDR3 SDRAM to perform a NOP (CS# low, RAS#, CAS#, WE# high).
This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.
s
y
2.3. Device Deselect Command [DESL]
ngs
Lo
The deselect function (CS# high) prevents new commands from being executed by the DDR3 SDRAM. The DDR3 SDRAM is effectively
deselected. Operations already in progress are not affected.
2.4. Mode Register Set Command [MR0 to MR3]
i
t
n
de
al
The mode registers are loaded via row address inputs. See mode register descriptions in the Programming the mode register section. The
mode register set command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until
tMRD is met.
fi
n
o
C2.5.
Bank Activate Command [ACT]
This command is used to open (or activate) a row in a particular bank for a subsequent access. The values on the BA inputs select the bank,
and the address provided on row address inputs selects the row. This row remains active (or open) for accesses until a precharge command
is issued to that bank. A precharge command must be issued before opening a different row in the same bank.
Note: No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW (ns) by tCK (ns) and rounding up to next integer
value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate
commands may be issued in clock N+1 through N+9.
2.6. Read Command [READ, RDS4, RDS8, READA, RDAS4, RDAS8]
The read command is used to initiate a burst read access to an active row. The values on the BA inputs select the bank, and the address
provided on column address inputs selects the starting column location. The value on input A10 determines whether or not auto precharge
is used. If auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not
selected, the row will remain open for subsequent accesses.
2.7. Write Command [WRIT, WRS4, WRS8, WRITA, WRAS4, WRAS8]
The write command is used to initiate a burst write access to an active row. The values on the BA inputs select the bank, and the address
provided on column address inputs selects the starting column location. The value on input A10 determines whether or not auto precharge
is used. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not
selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the
DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data will be written to
memory; if the DM signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that
byte/column location.
ys
s
g
n
Lo
2.8. Precharge Command [PRE, PALL]
al
i
t
en
The precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available
for a subsequent row access a specified time (tRP) after the precharge command is issued. Input A10 determines whether one or all banks
are to be precharged, and in the case where only one bank is to be precharged, inputs BA select the bank. Otherwise BA are treated as
"Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being
issued to that bank. A precharge command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously
open row is already in the process of precharging.
d
nfi
o
C
2.9. Auto precharge Command [READA, WRITA]
Before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto
precharge function. When a read or a write command is given to the DDR3 SDRAM, the CAS# timing accepts one extra address, column
s
y
s
g
www.longsys.com
n
Lo
Longsys Electronics
Page 14
Rev 1.0
F60C1A0004-M7
ial
t
n
de
fi
n
address A10, to allow the active bank to automatically begin precharge at the earliest possible moment
Co during the burst read or write cycle.
If A10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active
at the completion of the burst sequence. If A10 is high when the read or write command is issued, then the auto precharge function is
engaged. During auto precharge, a read command will execute as normal with the exception that the active bank will begin to precharge
on the rising edge which is (AL* + tRTP) cycles later from the read with auto precharge command.
Auto precharge can also be implemented during write commands. The precharge operation engaged by the Auto precharge command will
not begin until the last data of the burst write sequence is properly stored in the memory array.
This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS# latency)
thus improving system performance for random data access. The tRAS lockout circuit internally delays the Precharge operation until the
array restore operation has been completed so that the auto precharge command may be issued with any read or write command.
Note: AL (Additive Latency), refer to Posted CAS# description in the Register Definition section.
ys
s
g
n
Lo
2.10. Auto-Refresh Command [REF]
Auto-refresh is used during normal operation of the DDR3 SDRAM and is analogous to CAS#-before-RAS# (CBR) refresh in FPM/EDO
DRAM. This command is non persistent, so it must be issued each time a refresh is required. The addressing is generated by the internal
refresh controller. This makes the address bits a "Don't Care" during an auto-refresh command.
A maximum of eight auto-refresh commands can be posted to any given DDR3, meaning that the maximum absolute interval between any
auto-refresh command and the next auto-refresh command is 9 x tREFI. This maximum absolute interval is to allow DDR3 output drivers
and internal terminators to automatically recalibrate compensating for voltage and temperature changes.
fi
n
Co
i
t
n
de
al
2.11. Self-Refresh Command [SELF]
The self-refresh command can be used to retain data in the DDR3, even if the rest of the system is powered down. When in the self-refresh
mode, the DDR3 retains data without external clocking. The self-refresh command is initiated like an auto-refresh command except CKE is
disabled (low).
The DLL is automatically disabled upon entering self-refresh and is automatically enabled and reset upon exiting self-refresh. The active
termination is also disabled upon entering self-refresh and enabled upon exiting self-refresh. (512 clock cycles must then occur before a
read command can be issued). Input signals except CKE are "Don't Care" during self-refresh. The procedure for exiting self-refresh requires
a sequence of commands.
First, CK and /CK must be stable prior to CKE going back high. Once CKE is high, the DDR3 must have NOP commands issued for tXS DLL
because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh, DLL
requirements and out-put calibration is to apply NOPs for 512 clock cycles before applying any other command to allow the DLL to lock
and the output drivers to recalibrate.
2.12. ZQ calibration Command [ZQCL, ZQCS]
ZQ calibration command (short or long) is used to calibrate DRAM RON and ODT values over PVT. ZQ Calibration Long (ZQCL) command
is used to perform the initial calibration during power-up initialization sequence.
ZQ Calibration Short (ZQCS) command is used to perform periodic calibrations to account for VT variations. All banks must be precharged
and tRP met before ZQCL or ZQCS commands are issued by the controller.
ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self-refresh.
ys
s
g
n
Lo
2.13. CKE Truth Table
[Refer to section 4.2 in JEDEC Standard No. JESD79-3F]
al
i
t
en
d
nfi
o
C
s
y
s
g
www.longsys.com
n
Lo
Longsys Electronics
Page 15
Rev 1.0
F60C1A0004-M7
ial
t
n
de
fi
n
Co
3. Electrical Characteristic
All voltages are referenced to each VSS (GND).
Execute power-up and Initialization sequence before proper device operation can be achieved.
3.1. Absolute Ratings
ys
s
g
Stresses greater than those listed may cause permanent
damage to the device. This is a stress rating only, and functional operation of the
on indicated
Lthose
device at these or any other conditions outside
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may adversely affect reliability.
[Table 8] Absolute Maximum Ratings
Symbol
VDD
i
t
n
VIN, VOUT
e
fidTC
n
Co
VDDQ
al
TSTG
Parameter
VDD
VDD
Min
Max
Unit
Notes
supply voltage relative to VSS
–0.4
1.975
V
1
supply voltage relative to VSSQ
–0.4
1.975
V
Voltage on any pin relative to VSS
–0.4
1.975
V
Operating case temperature – Commercial
0
95
°C
2, 3
Operating case temperature – Industrial
–40
95
°C
2, 3
Storage temperature
–55
150
°C
Notes:
[1] VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be greater than 0.6 × VDDQ. When VDD and VDDQ are 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B must be derated by 2%; IDD2Px must be derated by 30%.
ys
s
g
n
Lo
al
i
t
en
d
nfi
o
C
s
y
s
g
www.longsys.com
n
Lo
Longsys Electronics
Page 18
Rev 1.0
F60C1A0004-M7
ial
t
n
de
fi
n
Co
3.17. Pin Capacitance(TC = 25°C, VDD, VDDQ = 1.35V )
[Table 13] Pin Capacitance
Capacitance
Parameters
CK and CKB
ΔC: CK to CKB
n
Co
DDR3L
-1600
Sym
yCCKs
s
g
n
Lo CDCK
DDR3L
-1866
DDR3L
-2133
Unit
Min
Max
Min
Max
Min
Max
0.8
1.4
0.8
1.3
0.8
1.3
pF
0.0
0.15
0.0
0.15
0.0
0.15
pF
Notes
Single-end I/O: DQ, DM
CIO
1.4
2.2
1.4
2.1
1.4
2.1
pF
2
Differential I/O: DQS, DQSB
CIO
1.4
2.2
1.4
2.1
1.4
2.1
pF
3
CDDQS
0.0
0.15
0.0
0.15
0.0
0.15
pF
3
CDIO
–0.5
0.3
–0.5
0.3
–0.5
0.3
pF
4
CI
0.75
1.2
0.75
1.2
0.75
1.2
pF
5
ΔC: CTRL to CK
CDI_CTRL
–0.4
0.2
–0.4
0.2
–0.4
0.2
pF
6
ΔC: CMD_ADDR
to CK
CDI_CMD
_ADDR
–0.4
0.4
–0.4
0.4
–0.4
0.4
pF
7
ZQ pin capacitance
CZQ
–
3.0
–
3.0
–
3.0
pF
Reset pin capacitance
CRE
–
3.0
–
3.0
–
3.0
pF
ΔC: DQS to DQSB
l
a
i
ΔC: DQ to DQS
t
n
e
Inputs (CTRL, CMD, ADDR)
fid
Notes:
[1] VDD = 1.35V (1.283–1.45V), VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25°C. VOUT(DC) = 0.5× VDDQ, VOUT = 0.1V (peak-to-peak).
[2] DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
[3] Includes .CDDQS is for DQS vs. DQS# separately.
[4] CDIO = CIO(DQ) - 0.5 × (CIO(DQS) + CIO(DQS#)).
[5] Excludes CK, CKB; CTRL = ODT, CSB, and CKE; CMD = RASB, CASB, and WEB; ADDR= A[n:0], BA[2:0].
[6] CDI_CTRL = CI(CTRL) - 0.5 × (CCK(CK) + CCK(CKB)).
[7] CDI_CMD_ADDR = CI(CMD_ADDR) - 0.5 × (CCK(CK) + CCK(CKB)).
ys
s
g
n
Lo
al
i
t
en
d
nfi
o
C
s
y
s
g
www.longsys.com
n
Lo
Longsys Electronics
Page 19
Rev 1.0
F60C1A0004-M7
ial
t
n
de
fi
n
Co
3.18. Standard Speed Bins
Refer to section 12.3 in JEDEC Standard No. JESD79-3F.
[Table 14] DDR3L-1600 Speed Bins
ys
s
g
n
DDR3L-1600 Speed Bin
800MHz
CL-tRCD-tRP
11-11-11
Lo
Symbol
Min
Max
Unit
Internal READ command to first data
tAA
13.75
–
ns
ACTIVATE to internal READ or WRITE delay time
tRCD
13.75
–
ns
PRECHARGE command period
tRP
13.75
–
ns
tRC
48.75
–
ns
Parameter
ial
t
ACTIVATE-to-PRECHARGE
n
e
fid CL = 5
ACTIVATE-to-ACTIVATE or REFRESH command period
n
Co
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
CL = 11
command period
Notes
tRAS
35
9 x tREFI
ns
2
CWL = 5
tCK (AVG)
3.0
3.3
ns
3
CWL = 6, 7, 8
tCK (AVG)
ns
4
CWL = 5
tCK (AVG)
ns
3
4
Reserved
2.5
3.3
CWL = 6
tCK (AVG)
Reserved
ns
CWL = 7, 8
tCK (AVG)
Reserved
ns
4
ns
4
ns
3
Reserved
ns
4
CWL = 5
tCK (AVG)
CWL = 6
tCK (AVG)
CWL = 7
tCK (AVG)
Reserved
1.875
工商网监
湘ICP备2023018690号
