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FSNAND Datasheet
FS33ND04GS1
Series
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Rev 2.0
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Revision History:
Rev 2.0
FS33ND04GS1
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Rev.
Date
Change
A0
A1
1.0
1.1
2.0
2017/06
2017/07
2017/09
2017/10
2018/07
Basic spec and architecture
Revise some descriptions
Revise some descriptions
Revise some descriptions
Revise some descriptions
NOP=1
Add Marketing Part Number
Chart
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NOTE: INFORMATION IN THIS PRODUCT SPECIFICATION
IS SUBJECT TO CHANGE AT ANYTIME WITHOUT NOTICE, ALL PRODUCT
o
L
SPECIFICATIONS ARE PROVIDED FOR REFERENCE ONLY.TO ANY INTELLECTUAL, PROPERTY RIGHTS IN LONGSYS ELECTRONICS
CO.,LTD. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED.
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Contents
1.
INTRODUCTION .......................................................................................................................................... 5
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
1.7.
1.8.
2.
General Description ............................................................................................................................................................................. 5
Flash ID ..................................................................................................................................................................................................... 5
Device Features ..................................................................................................................................................................................... 5
Product List ............................................................................................................................................................................................. 6
Connection Diagram ............................................................................................................................................................................ 7
Pin Description ...................................................................................................................................................................................... 8
System Block Diagram ........................................................................................................................................................................ 8
Addressing ............................................................................................................................................................................................... 9
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DEVICE OPERATION ................................................................................................................................. 10
2.1.
2.2.
2.3.
2.4.
2.5.
2.6.
2.7.
2.8.
2.9.
2.10.
2.11.
2.12.
2.13.
2.14.
2.15.
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Valid Block ............................................................................................................................................................................................ 21
Recommended Operating Conditions ...................................................................................................................................... 21
Absolute Maximum DC Ratings ................................................................................................................................................... 21
DC Operating Characteristics ....................................................................................................................................................... 21
Input / Output Capacitance (TA=25℃, VCC=3.3V, f=1.0Mhz) ....................................................................................... 22
Read / Program / Erase Characteristics .................................................................................................................................. 22
AC Timing Parameters Table ........................................................................................................................................................ 22
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Initial Invalid Block(s) .....................................................................................................................................................................
23
L
Identifying Initial Invalid Block(s) ............................................................................................................................................. 23
NAND FLASH TECHNICAL NOTES............................................................................................................. 23
4.1.
4.2.
4.3.
4.4.
4.5.
5.
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Command Sets .................................................................................................................................................................................... 10
Reset Operation .................................................................................................................................................................................. 10
Read ID ................................................................................................................................................................................................... 11
Page Read Operation ........................................................................................................................................................................ 12
Page Program Operation ................................................................................................................................................................ 14
Copy-Back Program Operation .................................................................................................................................................... 14
Block Erase Operation ..................................................................................................................................................................... 15
Unaligned Two-Plane Operation ................................................................................................................................................ 15
Two-Plane Page Program Operation ......................................................................................................................................... 16
Two-Plane Copy-Back Program Operation ............................................................................................................................ 17
Two-Plane Block Erase Operation ............................................................................................................................................. 18
Read Status ........................................................................................................................................................................................... 19
ECC Read Status ................................................................................................................................................................................. 19
ECC Sector Information .................................................................................................................................................................. 20
Ready/Busy .......................................................................................................................................................................................... 20
Electrical Characteristic .......................................................................................................................... 21
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
3.7.
4.
Rev 2.0
FS33ND04GS1
Error in Write or Read Operation .............................................................................................................................................. 24
Addressing for Program Operation ........................................................................................................................................... 26
System Interface Using CE# Don’t-Care................................................................................................................................... 27
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Timing ...................................................................................................................................................... 28
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
5.9.
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Data Protection & Power Up Sequence .................................................................................................................................... 28
Mode Selection ................................................................................................................................................................................... 28
Command Latch Cycle ..................................................................................................................................................................... 29
Address Latch Cycle .......................................................................................................................................................................... 29
Input Data Latch Cycle .................................................................................................................................................................... 30
Serial Access Cycle after Read (CLE=L, WE#=H, ALE=L) ................................................................................................. 30
Read Status Cycle ............................................................................................................................................................................... 31
ECC Read Status Cycle ..................................................................................................................................................................... 31
Read Operation ................................................................................................................................................................................... 32
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5.10.
5.11.
5.12.
5.13.
5.14.
5.15.
5.16.
5.17.
5.18.
5.19.
5.20.
6.
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Page Program Operation ................................................................................................................................................................ 32
Read Operation (Intercepted by CE#) ...................................................................................................................................... 33
Random Data Output In a Page Operation ............................................................................................................................. 33
Page Program Operation with Random Data Input Operation ..................................................................................... 34
Copy-Back Program Operation .................................................................................................................................................... 35
Copy-Back Program Operation with Random Data Input Operation ......................................................................... 36
Block Erase Operation ..................................................................................................................................................................... 37
Read ID Operation ............................................................................................................................................................................. 37
Two-Plane Page Program Operation ......................................................................................................................................... 38
Two-Plane Copy-Back Program Operation ............................................................................................................................ 39
Two-Plane Block Erase Operation ............................................................................................................................................. 41
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Physical Diagram ..................................................................................................................................... 42
6.1.
6.2.
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48-Pin Thin Small Outline Package(TSOP) ............................................................................................................................ 42
63-Pin Ball Grid Array (BGA) ....................................................................................................................................................... 43
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1. INTRODUCTION
1.1. General Description
The FORESEE FSNAND is offered in 3.3 VCC with x8 I/O interface. Its NAND cell provides the most cost-effective solution for the solid
state application market. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write
controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining
of data.
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1.2. Flash ID
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Product Family
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
ECh
DCh
10h
95h
56h
1.3. Device Features
Voltage Supply
- VCC: 3.3V (2.7V ~ 3.6V)
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Organization
- Memory Cell Array : (512M + 16M) Byte
- Page Size : (2K + 64) Byte
- Data Register : (2K + 64) Byte
- Block Erase : (128K + 4K) Byte
Command Driven Operation
Operation Temperature
- -40℃~85℃
Automatic Program and Erase
- Page Program : (2K + 64) Byte
Reliability
- Up to 100,000 P/E Cycle
- 10 Year Data retention (Typ.)
Page Read Operation
- Random Read: 25μs(Max.)
- Serial Access : 25ns(Min.)
- Data Transfer Rate : SDR 40Mhz (40MB/s)
Fast Write Cycle Time
- Page Program time : 400μs(Typ.)
- Block Erase Time : 4.5ms(Typ.)
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Command/Address/Data Multiplexed I/O Port
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1.4. Product List
[Table 1] Product List
Part Number
FS33ND04GS108TFI0
FS33ND04GS108BFI0
Rev 2.0
FS33ND04GS1
Density
4Gb
4Gb
Package Type
TSOP 48
BGA 63
Organization
x8
x8
Package Size(mm)
12*20
9*11
VCC Range
2.7V ~ 3.6V
2.7V ~ 3.6V
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33 ND 04G
S1 xx
x x x x
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Tracking Code
0 ,1 ,2
Voltage
Range
33 = 3.3V
Temperature Range
C = 0°C to +70°C
I = -40°C to +85°C
18 = 1.8V
Product Family
ND= SLC NAND
Green Code
Density
Package Type
T=TSOP48
B=BGA63(9*11mm)
01G= 1Gbits
02G= 2Gbits
04G= 4Gbits
Flash Type
Device
s08=8-bitWidth
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16=16-bit
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1.5. Connection Diagram
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Figure 1 48-Pin TSOP1 Contact x8 Device
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Figure 2 63-BGA Contact, x8 Device (Top View)
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1.6. Pin Description
[Table 2] Pin Description
Pin Name
Pin Function
I/O0 ~ I/O7
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O
pins float to high-z when the chip is deselected or when the outputs are disabled.
CLE
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE# signal.
ALE
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are latched
on the rising edge of WE# with ALE high.
CE#
CHIP ENABLE
The CE# input is the device selection control. When the device is in the Busy state, CE# high is ignored, and the
device does not return to standby mode in program or erase operation.
RE#
READ ENABLE
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid t REA
after the falling edge of RE# which also increments the internal column address counter by one.
WE#
WRITE ENABLE
The WE# input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE# pulse.
WP#
WRITE PROTECT
The WP# pin provides inadvertent program/erase protection during power transitions. The internal high
voltage generator is reset when the WP# pin is active low.
R/B#
READY/BUSY OUTPUT
The R/B# output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
VCC
POWER
VCC is the power supply for device.
VSS
GROUND
NC
NO CONNECTION
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NOTE:
Connect all VCC and VSS pins of each device to common power supply outputs.
1.7. System Block Diagram
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Figure 3 FSNAND Functional Block Diagram
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Figure 4 FSNAND Array Organization
1.8. Addressing
[Table 3] Address Cycle Map
Bus cycle
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A8
A9
A10
A11
L
L
L
L
3rd Cycle
A12
A13
A14
A15
A16
A17
A18
A19
4th Cycle
A20
A21
A22
A23
A24
A25
A26
A27
5th Cycle
A28
A29
L
L
L
L
L
L
Column Address
Row Address
Page Address : A12~ A17
Plane Address : A18
Block Address : A19~A29
NOTE :
Column Address : Starting Address of the Register.
L must be set to "Low".
The device ignores any additional input of address cycles than required.
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2. DEVICE OPERATION
2.1. Command Sets
[Table 4] Command Sets
Function
Read 3)
2nd Cycle
30h
Lo00h
90h
Read for Copy Back
Read ID
Reset
Page Program
Copy-Back Program
Block Erase
Two-Plane Page Program2)
Two-Plane Copy-Back Program2)
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1st Cycle
00h
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Block Erase
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Random
Data
Co Random Data Input
Output
35h
FFh
80h
10h
85h
60h
80h---11h
85h---11h
10h
D0h
81h---10h
81h---10h
60h---60h
D0h
85h
-
Read Status
05h
70h
E0h
-
ECC Read Status
7Ah
1)
1)
Acceptable Command during Busy
O
O
NOTE :
1) Random Data Input/Output can be executed in a page.
2) Any command between 11h and 81h is prohibited except 70h and FFh.
3) Command 80h + Address 1cycle must be inserted before the Read CMD(00h-30h).
2.2. Reset Operation
The reset command FFh resets the read/program/erase operation and clear the status register to be C0h (when WP# is high).
The reset command during the program/erase operation will result in the content of the selected locations(perform
programming/erasing) might be partially programmed/erased. If the Flash memory has already been set to reset stage with
reset command, the additional new reset command is invalid.
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Figure 5 Reset Sequence
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2.3. Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address
input of 00h.
For the FORESEE device, five read cycles sequentially output the 1st Cycle, and the device code and 3rd, 4th, and 5th cycle ID,
respectively. The command register remains in Read ID mode until further commands are issued to it.
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Figure 6 Read ID Sequence
[Table 5]00h Address ID cycle
Part Number
FS33ND04GS1
1st Cycle
ECh
2nd Cycle
DCh
3rd Cycle
10h
4th Cycle
95h
5th Cycle
56h
[Table 6]3rd ID Data
Description
Internal Chip Number
Cell Type
Number of
Simultaneously
Programmed Pages
I/O7
I/O6
1
2
4
8
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
1
2
4
8
Interleave Program
Between multiple chips
Not Support
Support
Cache Program
Not Support
Support
I/O5
I/O4
I/O3
0
0
1
1
0
0
1
1
0
1
0
1
I/O2
I/O1
I/O0
0
0
1
1
0
1
0
1
0
1
0
1
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0
1
0
1
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[Table 7]4th ID Data
Description
Page Size
(w/o redundant area )
1KB
2KB
4KB
8KB
Block Size
(w/o redundant area )
64KB
128KB
256KB
512KB
Redundant Area Size
( byte/512byte)
8
16
Organization
x8
x16
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I/O7
Plane Size
(w/o redundant Area)
Proccess
I/O5
0
0
1
1
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3
I/O2
I/O1
I/O0
0
0
1
1
0
1
0
1
I/O1
I/O0
0
1
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
1
50ns/30ns
25ns
Reserved
Reserved
0
1
0
1
Description
Plane Number
I/O6
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I/O7
1
2
4
8
64Mb
128Mb
256Mb
512Mb
1Gb
2Gb
4Gb
8Gb
21nm
1ynm
reserved
reserved
0
0
1
1
I/O6
0
0
0
0
1
1
1
1
Reserved
I/O5
0
0
1
1
0
0
1
1
I/O4
I/O3
I/O2
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
2.4. Page Read Operation
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Command 80h + Address 1cycle must be inserted before the Read CMD(00h-30h).
The device array is accessed in Page of 2,112 bytes. External reads begins after the R/B# pin goes to READY.
The Read operation may also be initiated by writing the 00h command and giving the address (column and row address) and
being confirmed by the 30h command, the device begins the internal read operation and the chip enters busy state. The data
can be read out in sequence after the chip is ready.
The device may output random data in a page instead of the consecutive sequential data by writing random data output
command. The column address of next data, which is going to be out, may be changed to the address which follows random
data output command. Random data output can be operated multiple times regardless of how many times it is done in a page.
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Figure 7 Page Read Sequence
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Figure 8 Page Read with Random Data Output Sequence
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2.5. Page Program Operation
The device is programmed basically on a page basis, and each page shall be programmed only once before being erased.
The memory is programmed by page, which is 2,112 bytes. After Program load command (80h) is issued and the row and
column address is given, the data will be loaded into the chip sequentially. Random Data Input command (85h) allows multiple
data load in non-sequential address. After data load is complete, program confirm command (10h) is issued to start the page
program operation. The page program operation in a block should start from the low address to high address.
Once the program process starts, the Read Status Register command may be entered to read the status register. The system
controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status
Register. When the Page Program is complete, the Write Status Bit (I/O0) may be checked (Figure 9). The internal write verify
detects only errors for "1"s that are not successfully programmed to "0"s.
During the Page Program progressing, only the read status register command and reset command are accepted, others are
ignored.
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Figure 9 Page Program Sequence
Figure 10 Program Operation with Random Data Input Sequence
2.6. Copy-Back Program Operation
Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page. The
benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to the newly
assigned free block. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program with the
destination page address. A read operation with "35h" command and the address of the source page moves the whole
2,112-byte data into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where
there is no bit error, the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing
Page-Copy Data-Input command (85h) with destination page address. Actual programming operation begins after Program
Confirm command (10h) is issued. Once the program process starts, the Read Status Register command (70h) may be entered
to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B# output,
or the Status bit(I/O6) of the Status Register. When the Copy-Back Program is complete, the Write Status Bit(I/O0) may be
checked(Figure 11). The command register remains in Read Status command mode until another valid command is written to
the command register.
During copy-back program, data modification is possible using random data input command (85h) as shown in Figure 11.
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Figure 11 Copy-Back Program Sequence
NOTE :
Copy-Back Program operation is allowed only within the same memory plane.
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Figure 12 Copy-Back Program with Random Data Input Sequence
2.7. Block Erase Operation
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup
command(60h). Only address A18 to A29 is valid while A12 to A17 is ignored. The Erase Confirm command(D0h) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
The completion of the erase operation can be detected by R/B# pin or Status register bit (IO6). Recommend to check the status
register bit IO0 after the erase operation completes.
During the erasing process, only the read status register command and reset command can be accepted,others are ignored.
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Figure 13 Block Erase Sequence
2.8. Unaligned Two-Plane Operation
Two-Plane Read/Program operation is supported in unaligned block addresses, as long as page addresses are same in all
planes.
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Figure 14 Example of Unaligned Two-Plane Operation
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2.9. Two-Plane Page Program Operation
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Two-Plane Page Program is an extension of Page Program, for a single plane with 2112 byte page registers. Since the device is
equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous programming of
two pages. After writing the first set of data up to 2112 byte into the selected page register, Dummy Page Program command
(11h) instead of actual Page Program command (10h) is inputted to finish data-loading of the first plane. Since no
programming process is involved, R/B# remains in Busy state for a short period of time(tDBSY). Read Status command (70h)
may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set
of data for the other plane is inputted after the 81h command and address sequences. After inputting data for the last plane,
actual True Page Program(10h) instead of dummy Page Program command (11h) must be followed to start the programming
process. The operation of R/B and Read Status is the same as that of Page Program. Although two planes are programmed
simultaneously, pass/fail is not available for each page when the program operation completes. Status bit of I/O 0 is set to "1"
when any of the pages fails.
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NOTE :
1) It is noticeable that same row address except for A18 is applied to the two blocks.
2) Any command between 11h and 81h is prohibited except 70h and FFh.
Figure 15 Two-Plane Page Program Sequence
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2.10. Two-Plane Copy-Back Program Operation
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Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 2112 byte page registers. Since
the device is equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous
programming of two pages.
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Figure 16 Two-Plane Copy-Back Program Sequence
NOTE :
1) Copy-Back Program operation is allowed only within the same memory plane.
2) Any command between 11h and 81h is prohibited except 70h and FFh.
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Figure 17 Two-Plane Copy-Back Program Operation with Random Data Input Sequence
NOTE :
1) Copy-Back Program operation is allowed only within the same memory plane.
2) Any command between 11h and 81h is prohibited except 70h and FFh.
2.11. Two-Plane Block Erase Operation
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Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from
each plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h)
followed by three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected
from each plane. The Erase Confirm command(D0h) initiates the actual erasing process. The completion is detected by
monitoring R/B pin or Ready/Busy status bit (I/O6).
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Figure 18 Two-Plane Block Erase Sequence
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2.12. Read Status
The device provides a status register that outputs the device status by writing a command code 70h, and then the IO pins
output the status at the falling edge of CE# or RE# which occurs last. Even though when multiple flash devices are connecting
in system and the R/B# pins are common-wired, the two lines of CE# and RE# may be checked for individual devices status
separately. The command register remains in Read Status mode until further commands are issued to it. Therefore, if the status
register is read during a random read cycle, the read command(00h) should be given before starting read cycles.
s
yRead
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use
Lo Not
Not use
[Table 9] Status Register Definition for 70h Command
I/O
Page Program
Block Erase
I/O 0
Pass/Fail
Pass/Fail
I/O 1
Not use
Not use
I/O 2
Not use
Not use
I/O 3
Not use
Not use
I/O 4
I/O 5
I/O 6
Co
en
d
i
nf I/O
7
Not use
Normal or uncorrectable /
Recommended to rewrite
Not use
Not use
Ready/Busy
Not use
Not use
Ready/Busy
Not use
Not use
Ready/Busy
Write Protect
Write Protect
Write Protect
tial
Definition
Pass : "0"
Fail : "1"
Don’t -cared
Don’t -cared
Chip Read Status
Normal or uncorrectable : 0
Recommended to rewrite : 1
Don’t -cared
Don’t -cared
Busy : "0"
Ready : "1"
Protected : "0"
Not Protected : "1"
NOTE :
I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
2.13. ECC Read Status
Using the ECC Read Status function, the Error Correction Status can be identified.
ECC is performed on the NAND Flash main and spare areas.
The ECC Read Status function also shows the number of errors in a sector as identified from a ECC check during a read
operation.
[Table 10] ECC Status Bytes
I/O7
I/O6
Sector Information
I/O5
I/O4
I/O3
ECC Status
I/O2
[Table 11] ECC Status
I/O3 to I/O0
0000
0001
0010
0011
0100
Others
ECC Status
No Error
1bit error (Correctable)
2bit error (Correctable)
3bit error (Correctable)
4bit error (Correctable)
Reserve
[Table 12]Sector Information
I/O7 to I/O4
0000
0001
0010
0011
Others
Sector Information
1st Sector (Main and Spare area)
2nd Sector (Main and Spare area)
3rd Sector (Main and Spare area)
4th Sector (Main and Spare area)
Reserved
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2.14. ECC Sector Information
ECC is generated by internal ECC logic during program operation.
During Read operation, the device automatically executes ECC. After read operation is executed, read status command can be
issued to identify the read status the read status remains unmodified until other valid commands are executed.
[Table 13] 2KByte Page Assignment
1’st Main
512B
2’nd Main
512B
s
4’thy
Main
s
512B
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3’rd Main
512B
1’st Spare
16B
2’nd Spare
16B
3’rd Spare
16B
4’th Spare
16B
[Table 14]Definition of 528Byte Sector
Sector
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1’st Sector
2’nd Sector
3’rd Sector
4’th Sector
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Column Address (Byte)
Main Field
0 ~ 511
512 ~ 1,023
1,024 ~ 1,535
1,536 ~ 2,047
Spare Field
2,048 ~ 2,063
2,064 ~ 2,079
2,080 ~ 2,095
2,096 ~ 2,111
NOTE :
The Internal ECC manages all data of Main area and Spare area.
A sector is the minimum unit for program operation and the number of program per page must not exceed 1.
2.15. Ready/Busy
The R/B# is an open-drain output pin and a pull-up resistor is necessary to add on the R/B# pin. The R/B# outputs the
ready/busy status of read/program/ erase operation of the device. When the R/B# is at low, the device is busy for read or
program or erase operation. When the R/B# is at high, the read/program/erase operation is finished.
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Figure 20 Rp vs tr, tf & Rp vs ibusy
Rp Value Guidence
The rise time of the R/B# signal depends on the combination of Rp and capacitive loading of the R/B# circuit.
It is approximately two times constants (Tc) between the 10% and 90% points on the R/B# waveform.
TC = R × C
Where R = Rp (Resistance of pull-up resistor), and C = CL (Total capacitive load)
The fall time of the R/B# signal majorly depends on the output impedance of the R/B# signal and the total load capacitance.
al
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en
fid
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Co 𝑉𝑐𝑐 (𝑀𝑎𝑥. ) − 𝑉𝑂𝐿 (𝑀𝑎𝑥. )
Rp (Min. ) =
𝐼𝑂𝐿 + 𝛴𝐼𝐿
Notes:
Considering of the variation of device-by-device, the above data is for reference to decide the resistor value.
Rp maximum value depends on the maximum permissible limit of tr.
IL is the total sum of the input currents of all devices tied to the R/B pin.
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3. Electrical Characteristic
3.1. Valid Block
[Table 15] The Number of Valid Block
Parameter
Symbol
FS33ND04GS1
NVB
sMin
y
s
ng 4,016
Lo
Typ.
Max
-
4,096
Unit
Blocks
3.2. Recommended Operating Conditions
[Table 16] Recommended Operating Conditions
ial Voltage
t
PowernSupply
Ground
de Supply Voltage
i
f
n
Parameter
Co
Symbol
Min
Typ.
Max
Unit
VCC
2.7
3.3
3.6
V
VSS
0
0
0
V
3.3. Absolute Maximum DC Ratings
[Table 17] Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Temperature Under Bias
Symbol
VCC
VIN
VI/O
TBIAS
Rating
-0.6 to + 4.6
-0.6 to + 4.6
-0.6 to VCC + 0.3 (< 4.6V)
-40 to +85
Unit
V
℃
NOTE :
Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods Block Replacement
Single bit Failure
Verify ECC -> ECC Correction
Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
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Figure 22 Program Flow Chart
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If program operation results in an error, map out the block including the page in error and copy the target data to another block.
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*If erase operation results in an error, map out the failing
block and replace it with another block.
Figure 23 Erase Flow Chart& Read Flow Chart
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Figure 24 Block Replacement
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1.When an error happens in the nth page of the Block ‘A’ during erase or program operation.
2.Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block‘B’)
3. Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block’B’.
4. Do not erase or program to Block ‘A’ by creating an ‘invalid block’ table or other appropriate scheme.
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4.4. Addressing for Program Operation
Within a block, The page program operation in a block should start from the low address to high address. Random page
address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed.
Therefore, LSB doesn't need to be page 0.
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Figure 25
[Table 23]Address Information
Device
FS30ND04GS108BFI0
FS30ND04GS108BFI0
I/O
I/Ox
I/O 0 ~ I/O 7
I/O 0 ~ I/O 7
DATA
Data In/Out
2112Byte
2112Byte
Col. Add1
A0~A7
A0~A7
Col. Add2
A8~A11
A8~A11
ADDRESS
Row Add1
A12~A19
A12~A19
Row Add2
A20~A27
A20~A27
Row Add3
A28~A29
A28~A29
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4.5. System Interface Using CE# Don’t-Care
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For an easier system interface, CE# may be inactive during the data-loading or serial access as shown below. The internal 2,112
byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of μ-seconds, deactivating CE# during the data-loading and
serial access would provide significant savings in power consumption.
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Figure 26 Program Operation with CE# don’t-care
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Figure 27 Read Operation with CE# don’t-care
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5. Timing
5.1. Data Protection & Power Up Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage
detector disables all functions whenever VCC is below about 2V(3.3V device). WP# pin provides hardware protection and is
recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 1ms is required before
internal circuit gets ready for any command sequences as shown in Figure 28. The two step command sequence for
program/erase provides additional software protection.
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Figure 28 AC Waveforms for Power Transition
NOTE :
1) During the initialization, the device consumes a maximum current of 30mA (ICC1).
2) Once Vcc drops under 2.5V, Vcc is recommended that it should be driven down to 0.5V and stay low under 0.5V for at least 1ms before Vcc power up.
5.2. Mode Selection
[Table 24]Mode Selection
CLE
ALE
CE#
WE#
RE#
WP#
X
H
L
L
H
L
H
L
H
X
H
L
L
H
H
L
H
L
H
L
L
L
H
L
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X1)
X
X
H
X
X
H
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tialH
n
X
X
X
X
Mode
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Read Mode
Address Input(5cycles)
Command Input
Write Mode
Address Input(5cycles)
Data Input
X
Data Output
X
During Read(Busy)
H
H
During Program(Busy)
During Erase(Busy)
L
Write Protect
0V/VCC2) Stand-by
NOTE :
1) X can be VIL or VIH.
2) WP should be biased to CMOS high or CMOS low for standby.
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5.3. Command Latch Cycle
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Figure 29 Command Latch Cycle
5.4. Address Latch Cycle
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Figure 30 Address Latch Cycle
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5.5. Input Data Latch Cycle
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Figure 31 Input Data Latch Cycle
5.6. Serial Access Cycle after Read (CLE=L, WE#=H, ALE=L)
Figure 32 Serial Access Cycle after Read (CLE=L, WE#=H, ALE=L)
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NOTE :
1) Transition is measured at 200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
2) tRHOH starts to be valid when frequency is lower than 20Mhz.
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5.7. Read Status Cycle
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Figure 33 Read Status Cycle
5.8. ECC Read Status Cycle
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Figure 34 ECC Read Status Cycle
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NOTE :
1) ECC Read Status output should include all 4 sector information.
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5.9. Read Operation
Command 80h + Address 1cycle must be inserted before the Read Operation.
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Figure 35 Read Operation
5.10. Page Program Operation
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Figure 36 Page Program Operation
NOTE :
tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
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5.11. Read Operation (Intercepted by CE#)
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Figure 37 Read Operation (Intercepted by CE#)
5.12. Random Data Output In a Page Operation
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Figure 38 Random Data Output In a Page Operation
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5.13.
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Figure 39 Page Program Operation with Random Data Input Operation
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5.14. Copy-Back Program Operation
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Figure 40 Copy-Back Program Operation
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5.15.
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Copy-Back Program Operation with Random Data Input
Co Operation
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Figure 41 Copy-Back Program Operation with Random Data Input Operation
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1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
2)Copy-Back Program operation is allowed only within the same memory plane.
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5.16. Block Erase Operation
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Figure 42 Block Erase Operation
5.17. Read ID Operation
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Figure 43 Read ID Operation
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5.18. Two-Plane Page Program Operation
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Figure 44 Two-Plane Page Program Operation
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5.19. Two-Plane Copy-Back Program Operation
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Figure 45 Two-Plane Copy-Back Program Operation
NOTE :
tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
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5.20. Two-Plane Block Erase Operation
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Figure 46 Two-Plane Block Erase Operation
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6. Physical Diagram
6.1. 48-Pin Thin Small Outline Package(TSOP)
Unit :mm/Inch
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Figure 47 48-Pin Thin Small Outline Package
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6.2. 63-Pin Ball Grid Array (BGA)
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Figure 48 63-Pin Ball Grid Array
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